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gerrit-public.fairphone.software / kernel / msm-4.9 / 85d44cbdb07b3c1dfb749944853378c787f57e39 / . / arch / arm64 / boot / dts / qcom / sdm845-v2.dtsi
blob: 89bab4a98edaf8a4579575eb0cb26f32c029744d [file] [log] [blame]
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "sdm845.dtsi"
Soundrapandian Jeyaprakash3cc03bb2017-08-09 15:16:41 -0700[diff] [blame]14#include "sdm845-v2-camera.dtsi"
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]15
16/ {
17 model = "Qualcomm Technologies, Inc. SDM845 V2";
18 qcom,msm-id = <321 0x20000>;
19};
David Collins36050182017-04-26 11:41:22 -0700[diff] [blame]20
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]21&sdhc_2 {
Subhash Jadavani3497a962017-07-31 13:57:47 -0700[diff] [blame]22 /delete-property/ qcom,sdr104-wa;
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]23};
24
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]25/delete-node/ &apc0_cpr;
26/delete-node/ &apc1_cpr;
27
28&soc {
29 /* CPR controller regulators */
30 apc0_cpr: cprh-ctrl@17dc0000 {
31 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
32 reg = <0x17dc0000 0x4000>,
33 <0x00784000 0x1000>,
34 <0x17840000 0x1000>;
35 reg-names = "cpr_ctrl", "fuse_base", "saw";
36 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
37 clock-names = "core_clk";
38 qcom,cpr-ctrl-name = "apc0";
39 qcom,cpr-controller-id = <0>;
40
41 qcom,cpr-sensor-time = <1000>;
42 qcom,cpr-loop-time = <5000000>;
43 qcom,cpr-idle-cycles = <15>;
44 qcom,cpr-up-down-delay-time = <3000>;
45 qcom,cpr-step-quot-init-min = <11>;
46 qcom,cpr-step-quot-init-max = <12>;
47 qcom,cpr-count-mode = <0>; /* All at once */
48 qcom,cpr-count-repeat = <20>;
49 qcom,cpr-down-error-step-limit = <1>;
50 qcom,cpr-up-error-step-limit = <1>;
51 qcom,cpr-corner-switch-delay-time = <1042>;
52 qcom,cpr-voltage-settling-time = <1760>;
53 qcom,cpr-reset-step-quot-loop-en;
54
55 qcom,voltage-step = <4000>;
56 qcom,voltage-base = <352000>;
57 qcom,cpr-saw-use-unit-mV;
58
59 qcom,saw-avs-ctrl = <0x101C031>;
60 qcom,saw-avs-limit = <0x3B803B8>;
61
62 qcom,cpr-enable;
63 qcom,cpr-hw-closed-loop;
64
65 qcom,cpr-panic-reg-addr-list =
66 <0x17dc3a84 0x17dc3a88 0x17840c18>;
67 qcom,cpr-panic-reg-name-list =
68 "APSS_SILVER_CPRH_STATUS_0",
69 "APSS_SILVER_CPRH_STATUS_1",
70 "SILVER_SAW4_PMIC_STS";
71
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]72 qcom,cpr-aging-ref-voltage = <1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]73 vdd-supply = <&pm8998_s13>;
74
75 thread@0 {
76 qcom,cpr-thread-id = <0>;
77 qcom,cpr-consecutive-up = <0>;
78 qcom,cpr-consecutive-down = <0>;
79 qcom,cpr-up-threshold = <2>;
80 qcom,cpr-down-threshold = <2>;
81
82 apc0_pwrcl_vreg: regulator {
83 regulator-name = "apc0_pwrcl_corner";
84 regulator-min-microvolt = <1>;
85 regulator-max-microvolt = <18>;
86
87 qcom,cpr-fuse-corners = <4>;
88 qcom,cpr-fuse-combos = <16>;
89 qcom,cpr-speed-bins = <2>;
90 qcom,cpr-speed-bin-corners = <18 18>;
91 qcom,cpr-corners = <18>;
92
93 qcom,cpr-corner-fmax-map = <6 12 15 18>;
94
95 qcom,cpr-voltage-ceiling =
96 <828000 828000 828000 828000 828000
97 828000 828000 828000 828000 828000
98 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]99 932000 1000000 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]100
101 qcom,cpr-voltage-floor =
102 <568000 568000 568000 568000 568000
103 568000 568000 568000 568000 568000
104 568000 568000 568000 568000 568000
105 568000 568000 568000>;
106
107 qcom,cpr-floor-to-ceiling-max-range =
108 <32000 32000 32000 32000 32000
109 32000 32000 32000 32000 32000
110 32000 32000 32000 32000 32000
111 32000 40000 40000>;
112
113 qcom,corner-frequencies =
114 <300000000 403200000 480000000
115 576000000 652800000 748800000
116 825600000 902400000 979200000
117 1056000000 1132800000 1228800000
118 1324800000 1420800000 1516800000
119 1612800000 1689600000 1766400000>;
120
121 qcom,cpr-ro-scaling-factor =
122 <2594 2795 2576 2761 2469 2673 2198
123 2553 3188 3255 3191 2962 3055 2984
124 2043 2947>,
125 <2594 2795 2576 2761 2469 2673 2198
126 2553 3188 3255 3191 2962 3055 2984
127 2043 2947>,
128 <2259 2389 2387 2531 2294 2464 2218
129 2476 2525 2855 2817 2836 2740 2490
130 1950 2632>,
131 <2259 2389 2387 2531 2294 2464 2218
132 2476 2525 2855 2817 2836 2740 2490
133 1950 2632>;
134
135 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame^]136 /* Speed bin 0 */
137 < 0 0 12000 12000>,
138 <(-15000) (-15000) (-3000) (-3000)>,
139 <(-15000) (-15000) (-3000) (-3000)>,
140 <(-15000) (-15000) (-3000) (-3000)>,
141 <(-15000) (-15000) (-3000) (-3000)>,
142 <(-15000) (-15000) (-3000) (-3000)>,
143 <(-15000) (-15000) (-3000) (-3000)>,
144 <(-15000) (-15000) (-3000) (-3000)>,
145 /* Speed bin 1 */
146 < 0 0 12000 12000>,
147 <(-15000) (-15000) (-3000) (-3000)>,
148 <(-15000) (-15000) (-3000) (-3000)>,
149 <(-15000) (-15000) (-3000) (-3000)>,
150 <(-15000) (-15000) (-3000) (-3000)>,
151 <(-15000) (-15000) (-3000) (-3000)>,
152 <(-15000) (-15000) (-3000) (-3000)>,
153 <(-15000) (-15000) (-3000) (-3000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]154
155 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame^]156 /* Speed bin 0 */
157 < 0 0 12000 10000>,
158 <(-15000) (-15000) (-3000) (-5000)>,
159 <(-15000) (-15000) (-3000) (-5000)>,
160 <(-15000) (-15000) (-3000) (-5000)>,
161 <(-15000) (-15000) (-3000) (-5000)>,
162 <(-15000) (-15000) (-3000) (-5000)>,
163 <(-15000) (-15000) (-3000) (-5000)>,
164 <(-15000) (-15000) (-3000) (-5000)>,
165 /* Speed bin 1 */
166 < 0 0 12000 10000>,
167 <(-15000) (-15000) (-3000) (-5000)>,
168 <(-15000) (-15000) (-3000) (-5000)>,
169 <(-15000) (-15000) (-3000) (-5000)>,
170 <(-15000) (-15000) (-3000) (-5000)>,
171 <(-15000) (-15000) (-3000) (-5000)>,
172 <(-15000) (-15000) (-3000) (-5000)>,
173 <(-15000) (-15000) (-3000) (-5000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]174
175 qcom,allow-voltage-interpolation;
176 qcom,allow-quotient-interpolation;
177 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
178
179 qcom,cpr-aging-max-voltage-adjustment = <15000>;
180 qcom,cpr-aging-ref-corner = <18>;
181 qcom,cpr-aging-ro-scaling-factor = <1620>;
182 qcom,allow-aging-voltage-adjustment =
183 /* Speed bin 0 */
184 <0 1 1 1 1 1 1 1>,
185 /* Speed bin 1 */
186 <0 1 1 1 1 1 1 1>;
187 qcom,allow-aging-open-loop-voltage-adjustment =
188 <1>;
189 };
190 };
191
192 thread@1 {
193 qcom,cpr-thread-id = <1>;
194 qcom,cpr-consecutive-up = <0>;
195 qcom,cpr-consecutive-down = <0>;
196 qcom,cpr-up-threshold = <2>;
197 qcom,cpr-down-threshold = <2>;
198
199 apc0_l3_vreg: regulator {
200 regulator-name = "apc0_l3_corner";
201 regulator-min-microvolt = <1>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]202 regulator-max-microvolt = <15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]203
204 qcom,cpr-fuse-corners = <4>;
205 qcom,cpr-fuse-combos = <16>;
206 qcom,cpr-speed-bins = <2>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]207 qcom,cpr-speed-bin-corners = <14 15>;
208 qcom,cpr-corners =
209 /* Speed bin 0 */
210 <14 14 14 14 14 14 14 14>,
211 /* Speed bin 1 */
212 <15 15 15 15 15 15 15 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]213
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]214 qcom,cpr-corner-fmax-map =
215 /* Speed bin 0 */
216 <4 8 11 14>,
217 /* Speed bin 1 */
218 <4 8 11 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]219
220 qcom,cpr-voltage-ceiling =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]221 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]222 <828000 828000 828000 828000 828000
223 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]224 828000 932000 932000 1000000>,
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]225 /* Speed bin 1 */
226 <828000 828000 828000 828000 828000
227 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]228 828000 932000 932000 1000000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]229 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]230
231 qcom,cpr-voltage-floor =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]232 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]233 <568000 568000 568000 568000 568000
234 568000 568000 568000 568000 568000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]235 568000 568000 568000 568000>,
236 /* Speed bin 1 */
237 <568000 568000 568000 568000 568000
238 568000 568000 568000 568000 568000
239 568000 568000 568000 568000
240 568000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]241
242 qcom,cpr-floor-to-ceiling-max-range =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]243 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]244 <32000 32000 32000 32000 32000
245 32000 32000 32000 32000 32000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]246 32000 32000 32000 40000>,
247 /* Speed bin 1 */
248 <32000 32000 32000 32000 32000
249 32000 32000 32000 32000 32000
250 32000 32000 32000 40000 40000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]251
252 qcom,corner-frequencies =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]253 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]254 <300000000 403200000 480000000
255 576000000 652800000 748800000
256 844800000 940800000 1036800000
257 1132800000 1209600000 1305600000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]258 1401600000 1478400000>,
259 /* Speed bin 1 */
260 <300000000 403200000 480000000
261 576000000 652800000 748800000
262 844800000 940800000 1036800000
263 1132800000 1209600000 1305600000
264 1401600000 1497600000 1593600000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]265
266 qcom,cpr-ro-scaling-factor =
267 <2857 3056 2828 2952 2699 2796 2447
268 2631 2630 2579 2244 3343 3287 3137
269 3164 2656>,
270 <2857 3056 2828 2952 2699 2796 2447
271 2631 2630 2579 2244 3343 3287 3137
272 3164 2656>,
273 <2439 2577 2552 2667 2461 2577 2394
274 2536 2132 2307 2191 2903 2838 2912
275 2501 2095>,
276 <2439 2577 2552 2667 2461 2577 2394
277 2536 2132 2307 2191 2903 2838 2912
278 2501 2095>;
279
280 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame^]281 /* Speed bin 0 */
282 < 8000 16000 16000 12000>,
283 < (-7000) 1000 1000 (-3000)>,
284 < (-7000) 1000 1000 (-3000)>,
285 < (-7000) 1000 1000 (-3000)>,
286 < (-7000) 1000 1000 (-3000)>,
287 < (-7000) 1000 1000 (-3000)>,
288 < (-7000) 1000 1000 (-3000)>,
289 < (-7000) 1000 1000 (-3000)>,
290 /* Speed bin 1 */
291 < 8000 16000 16000 12000>,
292 < (-7000) 1000 1000 (-3000)>,
293 < (-7000) 1000 1000 (-3000)>,
294 < (-7000) 1000 1000 (-3000)>,
295 < (-7000) 1000 1000 (-3000)>,
296 < (-7000) 1000 1000 (-3000)>,
297 < (-7000) 1000 1000 (-3000)>,
298 < (-7000) 1000 1000 (-3000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]299
300 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame^]301 /* Speed bin 0 */
302 < 6000 14000 16000 12000>,
303 < (-9000) (-1000) 1000 (-3000)>,
304 < (-9000) (-1000) 1000 (-3000)>,
305 < (-9000) (-1000) 1000 (-3000)>,
306 < (-9000) (-1000) 1000 (-3000)>,
307 < (-9000) (-1000) 1000 (-3000)>,
308 < (-9000) (-1000) 1000 (-3000)>,
309 < (-9000) (-1000) 1000 (-3000)>,
310 /* Speed bin 1 */
311 < 6000 14000 16000 12000>,
312 < (-9000) (-1000) 1000 (-3000)>,
313 < (-9000) (-1000) 1000 (-3000)>,
314 < (-9000) (-1000) 1000 (-3000)>,
315 < (-9000) (-1000) 1000 (-3000)>,
316 < (-9000) (-1000) 1000 (-3000)>,
317 < (-9000) (-1000) 1000 (-3000)>,
318 < (-9000) (-1000) 1000 (-3000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]319
320 qcom,allow-voltage-interpolation;
321 qcom,allow-quotient-interpolation;
322 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
323
324 qcom,cpr-aging-max-voltage-adjustment = <15000>;
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]325 qcom,cpr-aging-ref-corner = <14 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]326 qcom,cpr-aging-ro-scaling-factor = <1620>;
327 qcom,allow-aging-voltage-adjustment =
328 /* Speed bin 0 */
329 <0 1 1 1 1 1 1 1>,
330 /* Speed bin 1 */
331 <0 1 1 1 1 1 1 1>;
332 qcom,allow-aging-open-loop-voltage-adjustment =
333 <1>;
334 };
335 };
336 };
337
338 apc1_cpr: cprh-ctrl@17db0000 {
339 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
340 reg = <0x17db0000 0x4000>,
341 <0x00784000 0x1000>,
342 <0x17830000 0x1000>;
343 reg-names = "cpr_ctrl", "fuse_base", "saw";
344 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
345 clock-names = "core_clk";
346 qcom,cpr-ctrl-name = "apc1";
347 qcom,cpr-controller-id = <1>;
348
349 qcom,cpr-sensor-time = <1000>;
350 qcom,cpr-loop-time = <5000000>;
351 qcom,cpr-idle-cycles = <15>;
352 qcom,cpr-up-down-delay-time = <3000>;
353 qcom,cpr-step-quot-init-min = <9>;
354 qcom,cpr-step-quot-init-max = <14>;
355 qcom,cpr-count-mode = <0>; /* All at once */
356 qcom,cpr-count-repeat = <20>;
357 qcom,cpr-down-error-step-limit = <1>;
358 qcom,cpr-up-error-step-limit = <1>;
359 qcom,cpr-corner-switch-delay-time = <1042>;
360 qcom,cpr-voltage-settling-time = <1760>;
361 qcom,cpr-reset-step-quot-loop-en;
362
363 qcom,apm-threshold-voltage = <800000>;
364 qcom,apm-crossover-voltage = <880000>;
365 qcom,mem-acc-threshold-voltage = <852000>;
366 qcom,mem-acc-crossover-voltage = <852000>;
367
368 qcom,voltage-step = <4000>;
369 qcom,voltage-base = <352000>;
370 qcom,cpr-saw-use-unit-mV;
371
372 qcom,saw-avs-ctrl = <0x101C031>;
373 qcom,saw-avs-limit = <0x4700470>;
374
375 qcom,cpr-enable;
376 qcom,cpr-hw-closed-loop;
377
378 qcom,cpr-panic-reg-addr-list =
379 <0x17db3a84 0x17830c18>;
380 qcom,cpr-panic-reg-name-list =
381 "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
382
383 qcom,cpr-aging-ref-voltage = <1136000>;
384 vdd-supply = <&pm8998_s12>;
385
386 thread@0 {
387 qcom,cpr-thread-id = <0>;
388 qcom,cpr-consecutive-up = <0>;
389 qcom,cpr-consecutive-down = <0>;
390 qcom,cpr-up-threshold = <2>;
391 qcom,cpr-down-threshold = <2>;
392
393 apc1_perfcl_vreg: regulator {
394 regulator-name = "apc1_perfcl_corner";
395 regulator-min-microvolt = <1>;
396 regulator-max-microvolt = <33>;
397
398 qcom,cpr-fuse-corners = <5>;
399 qcom,cpr-fuse-combos = <16>;
400 qcom,cpr-speed-bins = <2>;
401 qcom,cpr-speed-bin-corners = <28 31>;
402 qcom,cpr-corners =
403 /* Speed bin 0 */
404 <28 28 28 28 28 28 28 28>,
405 /* Speed bin 1 */
406 <31 31 31 31 31 31 31 31>;
407
408 qcom,cpr-corner-fmax-map =
409 /* Speed bin 0 */
410 <7 14 22 27 28>,
411 /* Speed bin 1 */
412 <7 14 22 27 31>;
413
414 qcom,cpr-voltage-ceiling =
415 /* Speed bin 0 */
416 <828000 828000 828000 828000 828000
417 828000 828000 828000 828000 828000
418 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]419 828000 828000 828000 932000 932000
420 932000 932000 1104000 1104000 1104000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]421 1104000 1136000 1136000>,
422 /* Speed bin 1 */
423 <828000 828000 828000 828000 828000
424 828000 828000 828000 828000 828000
425 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]426 828000 828000 828000 932000 932000
427 932000 932000 1104000 1104000 1104000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]428 1104000 1136000 1136000 1136000 1136000
429 1136000>;
430
431 qcom,cpr-voltage-floor =
432 /* Speed bin 0 */
433 <568000 568000 568000 568000 568000
434 568000 568000 568000 568000 568000
435 568000 568000 568000 568000 568000
436 568000 568000 568000 568000 568000
437 568000 568000 568000 568000 568000
438 568000 568000 568000>,
439 /* Speed bin 1 */
440 <568000 568000 568000 568000 568000
441 568000 568000 568000 568000 568000
442 568000 568000 568000 568000 568000
443 568000 568000 568000 568000 568000
444 568000 568000 568000 568000 568000
445 568000 568000 568000 568000 568000
446 568000>;
447
448 qcom,cpr-floor-to-ceiling-max-range =
449 /* Speed bin 0 */
450 <32000 32000 32000 32000 32000
451 32000 32000 32000 32000 32000
452 32000 32000 32000 32000 32000
453 32000 32000 32000 32000 32000
454 32000 32000 32000 32000 32000
455 32000 32000 32000>,
456 /* Speed bin 1 */
457 <32000 32000 32000 32000 32000
458 32000 32000 32000 32000 32000
459 32000 32000 32000 32000 32000
460 32000 32000 32000 32000 32000
461 32000 32000 32000 32000 32000
462 32000 32000 40000 40000 40000
463 40000>;
464
465 qcom,corner-frequencies =
466 /* Speed bin 0 */
467 <300000000 403200000 480000000
468 576000000 652800000 748800000
469 825600000 902400000 979200000
470 1056000000 1132800000 1209600000
471 1286400000 1363200000 1459200000
472 1536000000 1612800000 1689600000
473 1766400000 1843200000 1920000000
474 1996800000 2092800000 2169600000
475 2246400000 2323200000 2400000000
476 2400000000>,
477 /* Speed bin 1 */
478 <300000000 403200000 480000000
479 576000000 652800000 748800000
480 825600000 902400000 979200000
481 1056000000 1132800000 1209600000
482 1286400000 1363200000 1459200000
483 1536000000 1612800000 1689600000
484 1766400000 1843200000 1920000000
485 1996800000 2092800000 2169600000
486 2246400000 2323200000 2400000000
David Collinsae2591d2017-08-22 14:15:14 -0700[diff] [blame]487 2476800000 2553600000 2649600000
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]488 2707200000>;
489
490 qcom,cpr-ro-scaling-factor =
491 <2857 3056 2828 2952 2699 2796 2447
492 2631 2630 2579 2244 3343 3287 3137
493 3164 2656>,
494 <2857 3056 2828 2952 2699 2796 2447
495 2631 2630 2579 2244 3343 3287 3137
496 3164 2656>,
497 <2086 2208 2273 2408 2203 2327 2213
498 2340 1755 2039 2049 2474 2437 2618
499 2003 1675>,
500 <2086 2208 2273 2408 2203 2327 2213
501 2340 1755 2039 2049 2474 2437 2618
502 2003 1675>,
503 <2086 2208 2273 2408 2203 2327 2213
504 2340 1755 2039 2049 2474 2437 2618
505 2003 1675>;
506
507 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame^]508 /* Speed bin 0 */
509 < 8000 8000 8000 0 0>,
510 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
511 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
512 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
513 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
514 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
515 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
516 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
517 /* Speed bin 1 */
518 < 8000 8000 8000 0 16000>,
519 < (-7000) (-7000) (-7000) (-15000) 1000>,
520 < (-7000) (-7000) (-7000) (-15000) 1000>,
521 < (-7000) (-7000) (-7000) (-15000) 1000>,
522 < (-7000) (-7000) (-7000) (-15000) 1000>,
523 < (-7000) (-7000) (-7000) (-15000) 1000>,
524 < (-7000) (-7000) (-7000) (-15000) 1000>,
525 < (-7000) (-7000) (-7000) (-15000) 1000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]526
527 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame^]528 /* Speed bin 0 */
529 < 6000 6000 8000 0 0>,
530 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
531 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
532 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
533 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
534 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
535 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
536 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
537 /* Speed bin 1 */
538 < 6000 6000 8000 0 16000>,
539 < (-9000) (-9000) (-7000) (-15000) 1000>,
540 < (-9000) (-9000) (-7000) (-15000) 1000>,
541 < (-9000) (-9000) (-7000) (-15000) 1000>,
542 < (-9000) (-9000) (-7000) (-15000) 1000>,
543 < (-9000) (-9000) (-7000) (-15000) 1000>,
544 < (-9000) (-9000) (-7000) (-15000) 1000>,
545 < (-9000) (-9000) (-7000) (-15000) 1000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]546
547 qcom,allow-voltage-interpolation;
548 qcom,allow-quotient-interpolation;
549 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
550
551 qcom,cpr-aging-max-voltage-adjustment = <15000>;
552 qcom,cpr-aging-ref-corner = <27 31>;
553 qcom,cpr-aging-ro-scaling-factor = <1700>;
554 qcom,allow-aging-voltage-adjustment =
555 /* Speed bin 0 */
556 <0 1 1 1 1 1 1 1>,
557 /* Speed bin 1 */
558 <0 1 1 1 1 1 1 1>;
559 qcom,allow-aging-open-loop-voltage-adjustment =
560 <1>;
561 };
562 };
563 };
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]564
565 gpu_gx_domain_addr: syscon@0x5091508 {
566 compatible = "syscon";
567 reg = <0x5091508 0x4>;
568 };
569
570 gpu_gx_sw_reset: syscon@0x5091008 {
571 compatible = "syscon";
572 reg = <0x5091008 0x4>;
573 };
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]574};
575
Kyle Yanf248e352017-09-14 11:15:58 -0700[diff] [blame]576&pil_modem {
577 qcom,mss_pdc_offset = <9>;
578};
579
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]580/* VDD_APC0 */
581&pm8998_s13 {
582 regulator-min-microvolt = <568000>;
583 regulator-max-microvolt = <1000000>;
584};
585
586/* VDD_APC1 */
587&pm8998_s12 {
588 regulator-min-microvolt = <568000>;
589 regulator-max-microvolt = <1136000>;
590};
591
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]592&clock_cpucc {
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]593 compatible = "qcom,clk-cpu-osm-v2";
594
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]595 vdd-l3-supply = <&apc0_l3_vreg>;
596 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]597 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
598
599 qcom,l3-speedbin0-v0 =
600 < 300000000 0x000c000f 0x00002020 0x1 1 >,
601 < 403200000 0x500c0115 0x00002020 0x1 2 >,
602 < 480000000 0x50140219 0x00002020 0x1 3 >,
603 < 576000000 0x5014031e 0x00002020 0x1 4 >,
604 < 652800000 0x401c0422 0x00002020 0x1 5 >,
605 < 748800000 0x401c0527 0x00002020 0x1 6 >,
606 < 844800000 0x4024062c 0x00002323 0x2 7 >,
607 < 940800000 0x40240731 0x00002727 0x2 8 >,
608 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
609 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
610 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
611 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
612 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
613 < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
614
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]615 qcom,l3-speedbin1-v0 =
616 < 300000000 0x000c000f 0x00002020 0x1 1 >,
617 < 403200000 0x500c0115 0x00002020 0x1 2 >,
618 < 480000000 0x50140219 0x00002020 0x1 3 >,
619 < 576000000 0x5014031e 0x00002020 0x1 4 >,
620 < 652800000 0x401c0422 0x00002020 0x1 5 >,
621 < 748800000 0x401c0527 0x00002020 0x1 6 >,
622 < 844800000 0x4024062c 0x00002323 0x2 7 >,
623 < 940800000 0x40240731 0x00002727 0x2 8 >,
624 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
625 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
626 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
627 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
628 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
629 < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
630 < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
631
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]632 qcom,pwrcl-speedbin0-v0 =
633 < 300000000 0x000c000f 0x00002020 0x1 1 >,
634 < 403200000 0x500c0115 0x00002020 0x1 2 >,
635 < 480000000 0x50140219 0x00002020 0x1 3 >,
636 < 576000000 0x5014031e 0x00002020 0x1 4 >,
637 < 652800000 0x401c0422 0x00002020 0x1 5 >,
638 < 748800000 0x401c0527 0x00002020 0x1 6 >,
639 < 825600000 0x401c062b 0x00002222 0x1 7 >,
640 < 902400000 0x4024072f 0x00002626 0x1 8 >,
641 < 979200000 0x40240833 0x00002929 0x1 9 >,
642 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
643 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
644 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
645 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
646 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
647 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
648 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
649 < 1689600000 0x40441058 0x00004646 0x2 17 >,
650 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
651
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]652 qcom,pwrcl-speedbin1-v0 =
653 < 300000000 0x000c000f 0x00002020 0x1 1 >,
654 < 403200000 0x500c0115 0x00002020 0x1 2 >,
655 < 480000000 0x50140219 0x00002020 0x1 3 >,
656 < 576000000 0x5014031e 0x00002020 0x1 4 >,
657 < 652800000 0x401c0422 0x00002020 0x1 5 >,
658 < 748800000 0x401c0527 0x00002020 0x1 6 >,
659 < 825600000 0x401c062b 0x00002222 0x1 7 >,
660 < 902400000 0x4024072f 0x00002626 0x1 8 >,
661 < 979200000 0x40240833 0x00002929 0x1 9 >,
662 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
663 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
664 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
665 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
666 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
667 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
668 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
669 < 1689600000 0x40441058 0x00004646 0x2 17 >,
670 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
671
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]672 qcom,perfcl-speedbin0-v0 =
673 < 300000000 0x000c000f 0x00002020 0x1 1 >,
674 < 403200000 0x500c0115 0x00002020 0x1 2 >,
675 < 480000000 0x50140219 0x00002020 0x1 3 >,
676 < 576000000 0x5014031e 0x00002020 0x1 4 >,
677 < 652800000 0x401c0422 0x00002020 0x1 5 >,
678 < 748800000 0x401c0527 0x00002020 0x1 6 >,
679 < 825600000 0x401c062b 0x00002222 0x1 7 >,
680 < 902400000 0x4024072f 0x00002626 0x1 8 >,
681 < 979200000 0x40240833 0x00002929 0x1 9 >,
682 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
683 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
684 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
685 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
686 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
687 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
688 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
689 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
690 < 1689600000 0x40441158 0x00004646 0x2 18 >,
691 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
692 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
693 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
694 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
695 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
696 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
697 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
698 < 2323200000 0x40541979 0x00006161 0x2 26 >,
699 < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
700
701 qcom,perfcl-speedbin1-v0 =
702 < 300000000 0x000c000f 0x00002020 0x1 1 >,
703 < 403200000 0x500c0115 0x00002020 0x1 2 >,
704 < 480000000 0x50140219 0x00002020 0x1 3 >,
705 < 576000000 0x5014031e 0x00002020 0x1 4 >,
706 < 652800000 0x401c0422 0x00002020 0x1 5 >,
707 < 748800000 0x401c0527 0x00002020 0x1 6 >,
708 < 825600000 0x401c062b 0x00002222 0x1 7 >,
709 < 902400000 0x4024072f 0x00002626 0x1 8 >,
710 < 979200000 0x40240833 0x00002929 0x1 9 >,
711 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
712 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
713 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
714 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
715 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
716 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
717 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
718 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
719 < 1689600000 0x40441158 0x00004646 0x2 18 >,
720 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
721 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
722 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
723 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
724 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
725 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
726 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
727 < 2323200000 0x40541979 0x00006161 0x2 26 >,
728 < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
729 < 2476800000 0x40541b81 0x00006767 0x2 28 >,
730 < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
Deepak Katragadda1a183252017-08-21 12:44:34 -0700[diff] [blame]731 < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
732 < 2745600000 0x40511e8f 0x00007272 0x2 31 >;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]733
734 qcom,l3-memacc-level-vc-bin0 = <8 13>;
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]735 qcom,l3-memacc-level-vc-bin1 = <8 13>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]736
737 qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]738 qcom,pwrcl-memacc-level-vc-bin1 = <12 16>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]739
740 qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
741 qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]742};
743
Tony Truong80258d62017-08-16 11:41:33 -0700[diff] [blame]744&pcie1 {
745 qcom,phy-sequence = <0x1804 0x03 0x0
746 0x00dc 0x27 0x0
747 0x0014 0x01 0x0
748 0x0020 0x31 0x0
749 0x0024 0x01 0x0
750 0x0028 0xde 0x0
751 0x002c 0x07 0x0
752 0x0034 0x4c 0x0
753 0x0038 0x06 0x0
754 0x0054 0x18 0x0
755 0x0058 0xb0 0x0
756 0x006c 0x8c 0x0
757 0x0070 0x20 0x0
758 0x0078 0x14 0x0
759 0x007c 0x34 0x0
760 0x00b4 0x06 0x0
761 0x00b8 0x06 0x0
762 0x00c0 0x16 0x0
763 0x00c4 0x16 0x0
764 0x00cc 0x36 0x0
765 0x00d0 0x36 0x0
766 0x00f0 0x05 0x0
767 0x00f8 0x42 0x0
768 0x0100 0x82 0x0
769 0x0108 0x68 0x0
770 0x011c 0x55 0x0
771 0x0120 0x55 0x0
772 0x0124 0x03 0x0
773 0x0128 0xab 0x0
774 0x012c 0xaa 0x0
775 0x0130 0x02 0x0
776 0x0150 0x3f 0x0
777 0x0158 0x3f 0x0
778 0x0178 0x10 0x0
779 0x01cc 0x04 0x0
780 0x01d0 0x30 0x0
781 0x01e0 0x04 0x0
782 0x01e8 0x73 0x0
783 0x01f0 0x1c 0x0
784 0x01fc 0x15 0x0
785 0x021c 0x04 0x0
786 0x0224 0x01 0x0
787 0x0228 0x22 0x0
788 0x022c 0x00 0x0
789 0x0098 0x05 0x0
790 0x080c 0x00 0x0
791 0x0818 0x0d 0x0
792 0x0860 0x01 0x0
793 0x0864 0x3a 0x0
794 0x087c 0x2f 0x0
795 0x08c0 0x09 0x0
796 0x08c4 0x09 0x0
797 0x08c8 0x1a 0x0
798 0x08d0 0x01 0x0
799 0x08d4 0x07 0x0
800 0x08d8 0x31 0x0
801 0x08dc 0x31 0x0
802 0x08e0 0x03 0x0
803 0x08fc 0x02 0x0
804 0x0900 0x01 0x0
805 0x0908 0x12 0x0
806 0x0914 0x25 0x0
807 0x0918 0x00 0x0
808 0x091c 0x05 0x0
809 0x0920 0x01 0x0
810 0x0924 0x26 0x0
811 0x0928 0x12 0x0
812 0x0930 0x04 0x0
813 0x0934 0x04 0x0
814 0x0938 0x09 0x0
815 0x0954 0x15 0x0
816 0x0960 0x32 0x0
817 0x0968 0x7f 0x0
818 0x096c 0x07 0x0
819 0x0978 0x04 0x0
820 0x0980 0x70 0x0
821 0x0984 0x8b 0x0
822 0x0988 0x08 0x0
823 0x098c 0x09 0x0
824 0x0990 0x03 0x0
825 0x0994 0x04 0x0
826 0x0998 0x02 0x0
827 0x099c 0x0c 0x0
828 0x09a4 0x02 0x0
829 0x09c0 0x5c 0x0
830 0x09c4 0x3e 0x0
831 0x09c8 0x3f 0x0
832 0x0a30 0x01 0x0
833 0x0a34 0xa0 0x0
834 0x0a38 0x08 0x0
835 0x0aa4 0x01 0x0
836 0x0aac 0xc3 0x0
837 0x0ab0 0x00 0x0
838 0x0ab8 0x8c 0x0
839 0x0ac0 0x7f 0x0
840 0x0ac4 0x2a 0x0
841 0x0810 0x0c 0x0
842 0x0814 0x00 0x0
843 0x0acc 0x04 0x0
844 0x093c 0x20 0x0
845 0x100c 0x00 0x0
846 0x1018 0x0d 0x0
847 0x1060 0x01 0x0
848 0x1064 0x3a 0x0
849 0x107c 0x2f 0x0
850 0x10c0 0x09 0x0
851 0x10c4 0x09 0x0
852 0x10c8 0x1a 0x0
853 0x10d0 0x01 0x0
854 0x10d4 0x07 0x0
855 0x10d8 0x31 0x0
856 0x10dc 0x31 0x0
857 0x10e0 0x03 0x0
858 0x10fc 0x02 0x0
859 0x1100 0x01 0x0
860 0x1108 0x12 0x0
861 0x1114 0x25 0x0
862 0x1118 0x00 0x0
863 0x111c 0x05 0x0
864 0x1120 0x01 0x0
865 0x1124 0x26 0x0
866 0x1128 0x12 0x0
867 0x1130 0x04 0x0
868 0x1134 0x04 0x0
869 0x1138 0x09 0x0
870 0x1154 0x15 0x0
871 0x1160 0x32 0x0
872 0x1168 0x7f 0x0
873 0x116c 0x07 0x0
874 0x1178 0x04 0x0
875 0x1180 0x70 0x0
876 0x1184 0x8b 0x0
877 0x1188 0x08 0x0
878 0x118c 0x09 0x0
879 0x1190 0x03 0x0
880 0x1194 0x04 0x0
881 0x1198 0x02 0x0
882 0x119c 0x0c 0x0
883 0x11a4 0x02 0x0
884 0x11c0 0x5c 0x0
885 0x11c4 0x3e 0x0
886 0x11c8 0x3f 0x0
887 0x1230 0x01 0x0
888 0x1234 0xa0 0x0
889 0x1238 0x08 0x0
890 0x12a4 0x01 0x0
891 0x12ac 0xc3 0x0
892 0x12b0 0x00 0x0
893 0x12b8 0x8c 0x0
894 0x12c0 0x7f 0x0
895 0x12c4 0x2a 0x0
896 0x1010 0x0c 0x0
897 0x1014 0x0f 0x0
898 0x12cc 0x04 0x0
899 0x113c 0x20 0x0
900 0x195c 0x3f 0x0
901 0x1974 0x50 0x0
902 0x196c 0x9f 0x0
903 0x182c 0x19 0x0
904 0x1840 0x07 0x0
905 0x1854 0x17 0x0
906 0x1868 0x09 0x0
907 0x1800 0x00 0x0
908 0x0aa8 0x01 0x0
909 0x12a8 0x01 0x0
910 0x1808 0x01 0x0>;
911};
912
Jonathan Avila29bc1972017-08-24 16:49:18 -0700[diff] [blame]913&devfreq_l3lat_0 {
914 qcom,core-dev-table =
915 < 300000 300000000 >,
916 < 480000 403200000 >,
917 < 652800 480000000 >,
918 < 748800 576000000 >,
919 < 902400 652800000 >,
920 < 979200 748800000 >,
921 < 1132800 844800000 >,
922 < 1228800 940800000 >,
923 < 1324800 1036800000 >,
924 < 1420800 1132800000 >,
925 < 1516800 1209600000 >,
926 < 1612800 1401600000 >,
927 < 1689600 1497600000 >,
928 < 1766400 1593600000 >;
929};
930
931&devfreq_l3lat_4 {
932 qcom,core-dev-table =
933 < 300000 300000000 >,
934 < 825600 576000000 >,
935 < 1132800 748800000 >,
936 < 1363200 940800000 >,
937 < 1689600 1209600000 >,
938 < 1996800 1401600000 >,
939 < 2400000 1593600000 >;
940};
941
Stephen Boydcbe46a02017-08-02 13:59:31 -0700[diff] [blame]942&bwmon {
943 qcom,count-unit = <0x10000>;
944};
945
Stephen Boyd31aac5f2017-09-01 09:16:06 -0700[diff] [blame]946&cpubw {
947 qcom,bw-tbl =
948 < MHZ_TO_MBPS(150, 16) >, /* 2288 MB/s */
949 < MHZ_TO_MBPS(300, 16) >, /* 4577 MB/s */
950 < MHZ_TO_MBPS(426, 16) >, /* 6500 MB/s */
951 < MHZ_TO_MBPS(533, 16) >, /* 8132 MB/s */
952 < MHZ_TO_MBPS(600, 16) >, /* 9155 MB/s */
953 < MHZ_TO_MBPS(806, 16) >, /* 12298 MB/s */
954 < MHZ_TO_MBPS(933, 16) >; /* 14236 MB/s */
955};
956
957&devfreq_cpufreq {
958 mincpubw-cpufreq {
959 cpu-to-dev-map-4 =
960 < 1881600 MHZ_TO_MBPS(200, 4) >,
961 < 2400000 MHZ_TO_MBPS(681, 4) >;
962 };
963};
964
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]965&clock_gcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]966 compatible = "qcom,gcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]967};
968
969&clock_camcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]970 compatible = "qcom,cam_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]971};
972
973&clock_dispcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]974 compatible = "qcom,dispcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]975};
976
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]977&clock_gpucc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]978 compatible = "qcom,gpucc-sdm845-v2", "syscon";
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]979};
980
981&clock_gfx {
982 compatible = "qcom,gfxcc-sdm845-v2";
983};
984
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]985&clock_videocc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]986 compatible = "qcom,video_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]987};
Praneeth Paladugu55381212017-07-05 15:02:44 -0700[diff] [blame]988
989&msm_vidc {
990 qcom,allowed-clock-rates = <100000000 200000000 330000000
991 404000000 444000000 533000000>;
992};
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]993
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]994&refgen {
995 status = "ok";
David Collinsd388dd82017-08-15 16:23:21 -0700[diff] [blame]996 regulator-always-on;
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]997};
998
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]999&spss_utils {
1000 qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
1001 qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
1002 qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
1003};
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]1004
1005&mdss_mdp {
1006 clock-max-rate = <0 0 0 0 430000000 19200000 0>;
Narendra Muppalla86a46a02017-08-17 11:14:37 -0700[diff] [blame]1007 qcom,sde-min-core-ib-kbps = <4800000>;
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]1008};
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1009
1010&energy_costs {
1011 CPU_COST_0: core-cost0 {
1012 busy-cost-data = <
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1013 300000 12
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1014 403200 17
1015 480000 21
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1016 576000 27
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1017 652800 31
1018 748800 37
1019 825600 42
1020 902400 47
1021 979200 52
1022 1056000 57
1023 1132800 62
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1024 1228800 70
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1025 1324800 78
1026 1420800 89
1027 1516800 103
1028 1612800 122
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1029 1689600 141
1030 1766400 160
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1031 >;
1032 idle-cost-data = <
1033 22 18 14 12
1034 >;
1035 };
1036 CPU_COST_1: core-cost1 {
1037 busy-cost-data = <
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1038 300000 189
1039 403200 523
1040 480000 763
1041 576000 1052
1042 652800 1273
1043 748800 1536
1044 825600 1736
1045 902400 1926
1046 979200 2108
1047 1056000 2284
1048 1132800 2456
1049 1209600 2628
1050 1286400 2804
1051 1363200 2992
1052 1459200 3255
1053 1536000 3499
1054 1612800 3786
1055 1689600 4128
1056 1766400 4535
1057 1843200 5019
1058 1920000 5583
1059 1996800 6226
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1060 2092800 7120
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1061 2169600 7876
1062 2246400 8628
1063 2323200 9344
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1064 2400000 10030
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1065 2476800 10806
1066 2553600 12045
1067 2649600 15686
1068 2745600 25586
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1069 >;
1070 idle-cost-data = <
1071 100 80 60 40
1072 >;
1073 };
1074 CLUSTER_COST_0: cluster-cost0 {
1075 busy-cost-data = <
1076 300000 3
1077 403200 4
1078 480000 4
1079 576000 4
1080 652800 5
1081 748800 5
1082 825600 6
1083 902400 7
1084 979200 7
1085 1056000 8
1086 1132800 9
1087 1228800 9
1088 1324800 10
1089 1420800 11
1090 1516800 12
1091 1612800 13
1092 1689600 15
1093 1766400 17
1094 >;
1095 idle-cost-data = <
1096 4 3 2 1
1097 >;
1098 };
1099 CLUSTER_COST_1: cluster-cost1 {
1100 busy-cost-data = <
1101 300000 24
1102 403200 24
1103 480000 25
1104 576000 25
1105 652800 26
1106 748800 27
1107 825600 28
1108 902400 29
1109 979200 30
1110 1056000 32
1111 1132800 34
1112 1209600 37
1113 1286400 40
1114 1363200 45
1115 1459200 50
1116 1536000 57
1117 1612800 64
1118 1689600 74
1119 1766400 84
1120 1843200 96
1121 1920000 106
1122 1996800 113
1123 2092800 120
1124 2169600 125
1125 2246400 127
1126 2323200 130
1127 2400000 135
1128 2476800 140
1129 2553600 145
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1130 2649600 150
1131 2745600 155
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1132 >;
1133 idle-cost-data = <
1134 4 3 2 1
1135 >;
1136 };
1137};
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]1138
1139&gpu_gx_gdsc {
1140 domain-addr = <&gpu_gx_domain_addr>;
1141 sw-reset = <&gpu_gx_sw_reset>;
1142 qcom,reset-aon-logic;
1143};
Lokesh Batra835f0162017-08-01 11:55:53 -0700[diff] [blame]1144
1145/* GPU overrides */
1146&msm_gpu {
1147 /* Updated chip ID */
1148 qcom,chipid = <0x06030001>;
1149 qcom,initial-pwrlevel = <5>;
1150
1151 qcom,gpu-pwrlevels {
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154
1155 compatible = "qcom,gpu-pwrlevels";
1156
1157 qcom,gpu-pwrlevel@0 {
1158 reg = <0>;
1159 qcom,gpu-freq = <675000000>;
1160 qcom,bus-freq = <12>;
1161 qcom,bus-min = <10>;
1162 qcom,bus-max = <12>;
1163 };
1164
1165 qcom,gpu-pwrlevel@1 {
1166 reg = <1>;
1167 qcom,gpu-freq = <596000000>;
1168 qcom,bus-freq = <10>;
1169 qcom,bus-min = <9>;
1170 qcom,bus-max = <11>;
1171 };
1172
1173 qcom,gpu-pwrlevel@2 {
1174 reg = <2>;
1175 qcom,gpu-freq = <520000000>;
1176 qcom,bus-freq = <9>;
1177 qcom,bus-min = <8>;
1178 qcom,bus-max = <10>;
1179 };
1180
1181 qcom,gpu-pwrlevel@3 {
1182 reg = <3>;
1183 qcom,gpu-freq = <414000000>;
1184 qcom,bus-freq = <8>;
1185 qcom,bus-min = <7>;
1186 qcom,bus-max = <9>;
1187 };
1188
1189 qcom,gpu-pwrlevel@4 {
1190 reg = <4>;
1191 qcom,gpu-freq = <342000000>;
1192 qcom,bus-freq = <6>;
1193 qcom,bus-min = <5>;
1194 qcom,bus-max = <7>;
1195 };
1196
1197 qcom,gpu-pwrlevel@5 {
1198 reg = <5>;
1199 qcom,gpu-freq = <257000000>;
1200 qcom,bus-freq = <4>;
1201 qcom,bus-min = <3>;
1202 qcom,bus-max = <5>;
1203 };
1204
1205 qcom,gpu-pwrlevel@6 {
1206 reg = <6>;
1207 qcom,gpu-freq = <0>;
1208 qcom,bus-freq = <0>;
1209 qcom,bus-min = <0>;
1210 qcom,bus-max = <0>;
1211 };
1212 };
1213};
1214
1215&gmu {
1216 qcom,gmu-pwrlevels {
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219
1220 compatible = "qcom,gmu-pwrlevels";
1221
1222 qcom,gmu-pwrlevel@0 {
1223 reg = <0>;
1224 qcom,gmu-freq = <500000000>;
1225 };
1226
1227 qcom,gmu-pwrlevel@1 {
1228 reg = <1>;
1229 qcom,gmu-freq = <200000000>;
1230 };
1231
1232 qcom,gmu-pwrlevel@2 {
1233 reg = <2>;
1234 qcom,gmu-freq = <0>;
1235 };
1236 };
1237};