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Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
Charulatha V1a5d8192011-02-02 17:52:14 +05306 * Juha Yrj�l� <juha.yrjola@nokia.com>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070017 */
18
19#include <linux/kernel.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070020#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
Russell King53741ed2012-04-23 13:51:48 +010025#include <linux/dmaengine.h>
Pascal Huerstbeca3652015-11-19 16:18:28 +010026#include <linux/pinctrl/consumer.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070027#include <linux/platform_device.h>
28#include <linux/err.h>
29#include <linux/clk.h>
30#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Govindraj.R1f1a4382011-02-02 17:52:15 +053032#include <linux/pm_runtime.h>
Benoit Coussond5a80032012-02-15 18:37:34 +010033#include <linux/of.h>
34#include <linux/of_device.h>
Illia Smyrnovd33f4732013-06-17 16:31:06 +030035#include <linux/gcd.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070036
37#include <linux/spi/spi.h>
Michael Wellingbc7f9bb2015-05-08 13:31:01 -050038#include <linux/gpio.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070039
Arnd Bergmann22037472012-08-24 15:21:06 +020040#include <linux/platform_data/spi-omap2-mcspi.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070041
42#define OMAP2_MCSPI_MAX_FREQ 48000000
Stefan Sørensenfaee9b02014-02-02 16:24:25 +010043#define OMAP2_MCSPI_MAX_DIVIDER 4096
Illia Smyrnovd33f4732013-06-17 16:31:06 +030044#define OMAP2_MCSPI_MAX_FIFODEPTH 64
45#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
Shubhrajyoti D27b52842012-03-26 17:04:22 +053046#define SPI_AUTOSUSPEND_TIMEOUT 2000
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070047
48#define OMAP2_MCSPI_REVISION 0x00
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070049#define OMAP2_MCSPI_SYSSTATUS 0x14
50#define OMAP2_MCSPI_IRQSTATUS 0x18
51#define OMAP2_MCSPI_IRQENABLE 0x1c
52#define OMAP2_MCSPI_WAKEUPENABLE 0x20
53#define OMAP2_MCSPI_SYST 0x24
54#define OMAP2_MCSPI_MODULCTRL 0x28
Illia Smyrnovd33f4732013-06-17 16:31:06 +030055#define OMAP2_MCSPI_XFERLEVEL 0x7c
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070056
57/* per-channel banks, 0x14 bytes each, first is: */
58#define OMAP2_MCSPI_CHCONF0 0x2c
59#define OMAP2_MCSPI_CHSTAT0 0x30
60#define OMAP2_MCSPI_CHCTRL0 0x34
61#define OMAP2_MCSPI_TX0 0x38
62#define OMAP2_MCSPI_RX0 0x3c
63
64/* per-register bitmasks: */
Illia Smyrnovd33f4732013-06-17 16:31:06 +030065#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070066
Jouni Hogander7a8fa722009-09-22 16:45:58 -070067#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070070
Jouni Hogander7a8fa722009-09-22 16:45:58 -070071#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72#define OMAP2_MCSPI_CHCONF_POL BIT(1)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070073#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070074#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070075#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070076#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070078#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070079#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83#define OMAP2_MCSPI_CHCONF_IS BIT(18)
84#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
Illia Smyrnovd33f4732013-06-17 16:31:06 +030086#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
87#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
Stefan Sørensenfaee9b02014-02-02 16:24:25 +010088#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070089
Jouni Hogander7a8fa722009-09-22 16:45:58 -070090#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
Illia Smyrnovd33f4732013-06-17 16:31:06 +030093#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070094
Jouni Hogander7a8fa722009-09-22 16:45:58 -070095#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
Stefan Sørensenfaee9b02014-02-02 16:24:25 +010096#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070097
Jouni Hogander7a8fa722009-09-22 16:45:58 -070098#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070099
100/* We have 2 DMA channels per CS, one for RX and one for TX */
101struct omap2_mcspi_dma {
Russell King53741ed2012-04-23 13:51:48 +0100102 struct dma_chan *dma_tx;
103 struct dma_chan *dma_rx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700104
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700105 struct completion dma_tx_completion;
106 struct completion dma_rx_completion;
Matt Porter74f3aaa2013-06-22 23:07:38 +0530107
108 char dma_rx_ch_name[14];
109 char dma_tx_ch_name[14];
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700110};
111
112/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
114 */
Roman Tereshonkov8b66c132010-04-12 09:07:54 +0000115#define DMA_MIN_BYTES 160
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700116
117
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530118/*
119 * Used for context save and restore, structure members to be updated whenever
120 * corresponding registers are modified.
121 */
122struct omap2_mcspi_regs {
123 u32 modulctrl;
124 u32 wakeupenable;
125 struct list_head cs;
126};
127
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700128struct omap2_mcspi {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700129 struct spi_master *master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700130 /* Virtual base address of the controller */
131 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100132 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700133 /* SPI1 has 4 channels, while SPI2 has 2 */
134 struct omap2_mcspi_dma *dma_channels;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530135 struct device *dev;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530136 struct omap2_mcspi_regs ctx;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300137 int fifo_depth;
Daniel Mack0384e902012-10-07 18:19:44 +0200138 unsigned int pin_dir:1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700139};
140
141struct omap2_mcspi_cs {
142 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100143 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700144 int word_len;
Mark A. Greer97ca0d62014-07-01 20:28:32 -0700145 u16 mode;
Tero Kristo89c05372009-09-22 16:46:17 -0700146 struct list_head node;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700147 /* Context save and restore shadow register */
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100148 u32 chconf0, chctrl0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700149};
150
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700151static inline void mcspi_write_reg(struct spi_master *master,
152 int idx, u32 val)
153{
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200156 writel_relaxed(val, mcspi->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700157}
158
159static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
160{
161 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
162
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200163 return readl_relaxed(mcspi->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700164}
165
166static inline void mcspi_write_cs_reg(const struct spi_device *spi,
167 int idx, u32 val)
168{
169 struct omap2_mcspi_cs *cs = spi->controller_state;
170
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200171 writel_relaxed(val, cs->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700172}
173
174static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
175{
176 struct omap2_mcspi_cs *cs = spi->controller_state;
177
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200178 return readl_relaxed(cs->base + idx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700179}
180
Hemanth Va41ae1a2009-09-22 16:46:16 -0700181static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
182{
183 struct omap2_mcspi_cs *cs = spi->controller_state;
184
185 return cs->chconf0;
186}
187
188static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
189{
190 struct omap2_mcspi_cs *cs = spi->controller_state;
191
192 cs->chconf0 = val;
193 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
Roman Tereshonkova330ce22010-03-15 09:06:28 +0000194 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700195}
196
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300197static inline int mcspi_bytes_per_word(int word_len)
198{
199 if (word_len <= 8)
200 return 1;
201 else if (word_len <= 16)
202 return 2;
203 else /* word_len <= 32 */
204 return 4;
205}
206
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700207static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
208 int is_read, int enable)
209{
210 u32 l, rw;
211
Hemanth Va41ae1a2009-09-22 16:46:16 -0700212 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700213
214 if (is_read) /* 1 is read, 0 write */
215 rw = OMAP2_MCSPI_CHCONF_DMAR;
216 else
217 rw = OMAP2_MCSPI_CHCONF_DMAW;
218
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530219 if (enable)
220 l |= rw;
221 else
222 l &= ~rw;
223
Hemanth Va41ae1a2009-09-22 16:46:16 -0700224 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700225}
226
227static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
228{
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100229 struct omap2_mcspi_cs *cs = spi->controller_state;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700230 u32 l;
231
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100232 l = cs->chctrl0;
233 if (enable)
234 l |= OMAP2_MCSPI_CHCTRL_EN;
235 else
236 l &= ~OMAP2_MCSPI_CHCTRL_EN;
237 cs->chctrl0 = l;
238 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000239 /* Flash post-writes */
240 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700241}
242
Michael Wellingddcad7e2015-05-12 12:38:57 -0500243static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700244{
Sebastian Reichel5f74db12015-07-22 20:46:09 +0200245 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700246 u32 l;
247
Michael Welling4373f8b2015-05-23 21:13:43 -0500248 /* The controller handles the inverted chip selects
249 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
250 * the inversion from the core spi_set_cs function.
251 */
252 if (spi->mode & SPI_CS_HIGH)
253 enable = !enable;
254
Michael Wellingddcad7e2015-05-12 12:38:57 -0500255 if (spi->controller_state) {
Sebastian Reichel5f74db12015-07-22 20:46:09 +0200256 int err = pm_runtime_get_sync(mcspi->dev);
257 if (err < 0) {
258 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
259 return;
260 }
261
Michael Wellingddcad7e2015-05-12 12:38:57 -0500262 l = mcspi_cached_chconf0(spi);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530263
Michael Wellingddcad7e2015-05-12 12:38:57 -0500264 if (enable)
265 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
266 else
267 l |= OMAP2_MCSPI_CHCONF_FORCE;
268
269 mcspi_write_chconf0(spi, l);
Sebastian Reichel5f74db12015-07-22 20:46:09 +0200270
271 pm_runtime_mark_last_busy(mcspi->dev);
272 pm_runtime_put_autosuspend(mcspi->dev);
Michael Wellingddcad7e2015-05-12 12:38:57 -0500273 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700274}
275
276static void omap2_mcspi_set_master_mode(struct spi_master *master)
277{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530278 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
279 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700280 u32 l;
281
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530282 /*
283 * Setup when switching from (reset default) slave mode
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700284 * to single-channel master mode
285 */
286 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530287 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
288 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700289 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700290
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530291 ctx->modulctrl = l;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700292}
293
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300294static void omap2_mcspi_set_fifo(const struct spi_device *spi,
295 struct spi_transfer *t, int enable)
296{
297 struct spi_master *master = spi->master;
298 struct omap2_mcspi_cs *cs = spi->controller_state;
299 struct omap2_mcspi *mcspi;
300 unsigned int wcnt;
Illia Smyrnov5db542e2013-10-09 15:05:08 +0300301 int max_fifo_depth, fifo_depth, bytes_per_word;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300302 u32 chconf, xferlevel;
303
304 mcspi = spi_master_get_devdata(master);
305
306 chconf = mcspi_cached_chconf0(spi);
307 if (enable) {
308 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
309 if (t->len % bytes_per_word != 0)
310 goto disable_fifo;
311
Illia Smyrnov5db542e2013-10-09 15:05:08 +0300312 if (t->rx_buf != NULL && t->tx_buf != NULL)
313 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
314 else
315 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
316
317 fifo_depth = gcd(t->len, max_fifo_depth);
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300318 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
319 goto disable_fifo;
320
321 wcnt = t->len / bytes_per_word;
322 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
323 goto disable_fifo;
324
325 xferlevel = wcnt << 16;
326 if (t->rx_buf != NULL) {
327 chconf |= OMAP2_MCSPI_CHCONF_FFER;
328 xferlevel |= (fifo_depth - 1) << 8;
Illia Smyrnov5db542e2013-10-09 15:05:08 +0300329 }
330 if (t->tx_buf != NULL) {
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300331 chconf |= OMAP2_MCSPI_CHCONF_FFET;
332 xferlevel |= fifo_depth - 1;
333 }
334
335 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
336 mcspi_write_chconf0(spi, chconf);
337 mcspi->fifo_depth = fifo_depth;
338
339 return;
340 }
341
342disable_fifo:
343 if (t->rx_buf != NULL)
344 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
Jorge A. Ventura3d0763c2014-08-09 16:06:58 -0500345
346 if (t->tx_buf != NULL)
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300347 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
348
349 mcspi_write_chconf0(spi, chconf);
350 mcspi->fifo_depth = 0;
351}
352
Hemanth Va41ae1a2009-09-22 16:46:16 -0700353static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
354{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530355 struct spi_master *spi_cntrl = mcspi->master;
356 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
357 struct omap2_mcspi_cs *cs;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700358
359 /* McSPI: context restore */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530360 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
361 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700362
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530363 list_for_each_entry(cs, &ctx->cs, node)
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200364 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700365}
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700366
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300367static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
368{
369 unsigned long timeout;
370
371 timeout = jiffies + msecs_to_jiffies(1000);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200372 while (!(readl_relaxed(reg) & bit)) {
Sebastian Andrzej Siewiorff23fa32013-03-21 13:22:48 +0100373 if (time_after(jiffies, timeout)) {
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200374 if (!(readl_relaxed(reg) & bit))
Sebastian Andrzej Siewiorff23fa32013-03-21 13:22:48 +0100375 return -ETIMEDOUT;
376 else
377 return 0;
378 }
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300379 cpu_relax();
380 }
381 return 0;
382}
383
Russell King53741ed2012-04-23 13:51:48 +0100384static void omap2_mcspi_rx_callback(void *data)
385{
386 struct spi_device *spi = data;
387 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
388 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
389
Russell King53741ed2012-04-23 13:51:48 +0100390 /* We must disable the DMA RX request */
391 omap2_mcspi_set_dma_req(spi, 1, 0);
Felipe Balbi830379e2012-12-12 10:45:59 +0200392
393 complete(&mcspi_dma->dma_rx_completion);
Russell King53741ed2012-04-23 13:51:48 +0100394}
395
396static void omap2_mcspi_tx_callback(void *data)
397{
398 struct spi_device *spi = data;
399 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
400 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
401
Russell King53741ed2012-04-23 13:51:48 +0100402 /* We must disable the DMA TX request */
403 omap2_mcspi_set_dma_req(spi, 0, 0);
Felipe Balbi830379e2012-12-12 10:45:59 +0200404
405 complete(&mcspi_dma->dma_tx_completion);
Russell King53741ed2012-04-23 13:51:48 +0100406}
407
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530408static void omap2_mcspi_tx_dma(struct spi_device *spi,
409 struct spi_transfer *xfer,
410 struct dma_slave_config cfg)
411{
412 struct omap2_mcspi *mcspi;
413 struct omap2_mcspi_dma *mcspi_dma;
414 unsigned int count;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530415
416 mcspi = spi_master_get_devdata(spi->master);
417 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
418 count = xfer->len;
419
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530420 if (mcspi_dma->dma_tx) {
421 struct dma_async_tx_descriptor *tx;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530422
423 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
424
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -0500425 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
426 xfer->tx_sg.nents,
427 DMA_MEM_TO_DEV,
428 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530429 if (tx) {
430 tx->callback = omap2_mcspi_tx_callback;
431 tx->callback_param = spi;
432 dmaengine_submit(tx);
433 } else {
434 /* FIXME: fall back to PIO? */
435 }
436 }
437 dma_async_issue_pending(mcspi_dma->dma_tx);
438 omap2_mcspi_set_dma_req(spi, 0, 1);
439
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530440}
441
442static unsigned
443omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
444 struct dma_slave_config cfg,
445 unsigned es)
446{
447 struct omap2_mcspi *mcspi;
448 struct omap2_mcspi_dma *mcspi_dma;
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -0500449 unsigned int count, transfer_reduction = 0;
450 struct scatterlist *sg_out[2];
451 int nb_sizes = 0, out_mapped_nents[2], ret, x;
452 size_t sizes[2];
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530453 u32 l;
454 int elements = 0;
455 int word_len, element_count;
456 struct omap2_mcspi_cs *cs = spi->controller_state;
457 mcspi = spi_master_get_devdata(spi->master);
458 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
459 count = xfer->len;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300460
Franklin S Cooper Jr4bd00412016-06-27 09:54:08 -0500461 /*
462 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
463 * it mentions reducing DMA transfer length by one element in master
464 * normal mode.
465 */
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300466 if (mcspi->fifo_depth == 0)
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -0500467 transfer_reduction = es;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300468
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530469 word_len = cs->word_len;
470 l = mcspi_cached_chconf0(spi);
471
472 if (word_len <= 8)
473 element_count = count;
474 else if (word_len <= 16)
475 element_count = count >> 1;
476 else /* word_len <= 32 */
477 element_count = count >> 2;
478
479 if (mcspi_dma->dma_rx) {
480 struct dma_async_tx_descriptor *tx;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530481
482 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
483
Franklin S Cooper Jr4bd00412016-06-27 09:54:08 -0500484 /*
485 * Reduce DMA transfer length by one more if McSPI is
486 * configured in turbo mode.
487 */
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300488 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -0500489 transfer_reduction += es;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530490
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -0500491 if (transfer_reduction) {
492 /* Split sgl into two. The second sgl won't be used. */
493 sizes[0] = count - transfer_reduction;
494 sizes[1] = transfer_reduction;
495 nb_sizes = 2;
496 } else {
497 /*
498 * Don't bother splitting the sgl. This essentially
499 * clones the original sgl.
500 */
501 sizes[0] = count;
502 nb_sizes = 1;
503 }
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530504
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -0500505 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
506 0, nb_sizes,
507 sizes,
508 sg_out, out_mapped_nents,
509 GFP_KERNEL);
510
511 if (ret < 0) {
512 dev_err(&spi->dev, "sg_split failed\n");
513 return 0;
514 }
515
516 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
517 sg_out[0],
518 out_mapped_nents[0],
519 DMA_DEV_TO_MEM,
520 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530521 if (tx) {
522 tx->callback = omap2_mcspi_rx_callback;
523 tx->callback_param = spi;
524 dmaengine_submit(tx);
525 } else {
526 /* FIXME: fall back to PIO? */
527 }
528 }
529
530 dma_async_issue_pending(mcspi_dma->dma_rx);
531 omap2_mcspi_set_dma_req(spi, 1, 1);
532
533 wait_for_completion(&mcspi_dma->dma_rx_completion);
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -0500534
535 for (x = 0; x < nb_sizes; x++)
536 kfree(sg_out[x]);
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300537
538 if (mcspi->fifo_depth > 0)
539 return count;
540
Franklin S Cooper Jr4bd00412016-06-27 09:54:08 -0500541 /*
542 * Due to the DMA transfer length reduction the missing bytes must
543 * be read manually to receive all of the expected data.
544 */
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530545 omap2_mcspi_set_enable(spi, 0);
546
547 elements = element_count - 1;
548
549 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
550 elements--;
551
552 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
553 & OMAP2_MCSPI_CHSTAT_RXS)) {
554 u32 w;
555
556 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
557 if (word_len <= 8)
558 ((u8 *)xfer->rx_buf)[elements++] = w;
559 else if (word_len <= 16)
560 ((u16 *)xfer->rx_buf)[elements++] = w;
561 else /* word_len <= 32 */
562 ((u32 *)xfer->rx_buf)[elements++] = w;
563 } else {
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300564 int bytes_per_word = mcspi_bytes_per_word(word_len);
Jarkko Nikulaa1829d22013-10-11 13:53:59 +0300565 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300566 count -= (bytes_per_word << 1);
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530567 omap2_mcspi_set_enable(spi, 1);
568 return count;
569 }
570 }
571 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
572 & OMAP2_MCSPI_CHSTAT_RXS)) {
573 u32 w;
574
575 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
576 if (word_len <= 8)
577 ((u8 *)xfer->rx_buf)[elements] = w;
578 else if (word_len <= 16)
579 ((u16 *)xfer->rx_buf)[elements] = w;
580 else /* word_len <= 32 */
581 ((u32 *)xfer->rx_buf)[elements] = w;
582 } else {
Jarkko Nikulaa1829d22013-10-11 13:53:59 +0300583 dev_err(&spi->dev, "DMA RX last word empty\n");
Illia Smyrnov56cd5c12013-06-14 19:12:07 +0300584 count -= mcspi_bytes_per_word(word_len);
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530585 }
586 omap2_mcspi_set_enable(spi, 1);
587 return count;
588}
589
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700590static unsigned
591omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
592{
593 struct omap2_mcspi *mcspi;
594 struct omap2_mcspi_cs *cs = spi->controller_state;
595 struct omap2_mcspi_dma *mcspi_dma;
Russell King8c7494a2012-04-23 13:56:25 +0100596 unsigned int count;
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000597 u32 l;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530598 u8 *rx;
599 const u8 *tx;
Russell King53741ed2012-04-23 13:51:48 +0100600 struct dma_slave_config cfg;
601 enum dma_slave_buswidth width;
602 unsigned es;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300603 u32 burst;
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530604 void __iomem *chstat_reg;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300605 void __iomem *irqstat_reg;
606 int wait_res;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700607
608 mcspi = spi_master_get_devdata(spi->master);
609 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000610 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700611
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300612
Russell King53741ed2012-04-23 13:51:48 +0100613 if (cs->word_len <= 8) {
614 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
615 es = 1;
616 } else if (cs->word_len <= 16) {
617 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
618 es = 2;
619 } else {
620 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
621 es = 4;
622 }
623
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300624 count = xfer->len;
625 burst = 1;
626
627 if (mcspi->fifo_depth > 0) {
628 if (count > mcspi->fifo_depth)
629 burst = mcspi->fifo_depth / es;
630 else
631 burst = count / es;
632 }
633
Russell King53741ed2012-04-23 13:51:48 +0100634 memset(&cfg, 0, sizeof(cfg));
635 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
636 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
637 cfg.src_addr_width = width;
638 cfg.dst_addr_width = width;
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300639 cfg.src_maxburst = burst;
640 cfg.dst_maxburst = burst;
Russell King53741ed2012-04-23 13:51:48 +0100641
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700642 rx = xfer->rx_buf;
643 tx = xfer->tx_buf;
644
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530645 if (tx != NULL)
646 omap2_mcspi_tx_dma(spi, xfer, cfg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700647
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530648 if (rx != NULL)
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530649 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700650
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530651 if (tx != NULL) {
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530652 wait_for_completion(&mcspi_dma->dma_tx_completion);
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530653
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300654 if (mcspi->fifo_depth > 0) {
655 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
656
657 if (mcspi_wait_for_reg_bit(irqstat_reg,
658 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
659 dev_err(&spi->dev, "EOW timed out\n");
660
661 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
662 OMAP2_MCSPI_IRQSTATUS_EOW);
663 }
664
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530665 /* for TX_ONLY mode, be sure all words have shifted out */
666 if (rx == NULL) {
Illia Smyrnovd33f4732013-06-17 16:31:06 +0300667 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
668 if (mcspi->fifo_depth > 0) {
669 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
670 OMAP2_MCSPI_CHSTAT_TXFFE);
671 if (wait_res < 0)
672 dev_err(&spi->dev, "TXFFE timed out\n");
673 } else {
674 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
675 OMAP2_MCSPI_CHSTAT_TXS);
676 if (wait_res < 0)
677 dev_err(&spi->dev, "TXS timed out\n");
678 }
679 if (wait_res >= 0 &&
680 (mcspi_wait_for_reg_bit(chstat_reg,
681 OMAP2_MCSPI_CHSTAT_EOT) < 0))
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530682 dev_err(&spi->dev, "EOT timed out\n");
683 }
684 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700685 return count;
686}
687
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700688static unsigned
689omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
690{
691 struct omap2_mcspi *mcspi;
692 struct omap2_mcspi_cs *cs = spi->controller_state;
693 unsigned int count, c;
694 u32 l;
695 void __iomem *base = cs->base;
696 void __iomem *tx_reg;
697 void __iomem *rx_reg;
698 void __iomem *chstat_reg;
699 int word_len;
700
701 mcspi = spi_master_get_devdata(spi->master);
702 count = xfer->len;
703 c = count;
704 word_len = cs->word_len;
705
Hemanth Va41ae1a2009-09-22 16:46:16 -0700706 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700707
708 /* We store the pre-calculated register addresses on stack to speed
709 * up the transfer loop. */
710 tx_reg = base + OMAP2_MCSPI_TX0;
711 rx_reg = base + OMAP2_MCSPI_RX0;
712 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
713
Michael Jonesadef6582011-02-25 16:55:11 +0100714 if (c < (word_len>>3))
715 return 0;
716
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700717 if (word_len <= 8) {
718 u8 *rx;
719 const u8 *tx;
720
721 rx = xfer->rx_buf;
722 tx = xfer->tx_buf;
723
724 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800725 c -= 1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700726 if (tx != NULL) {
727 if (mcspi_wait_for_reg_bit(chstat_reg,
728 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
729 dev_err(&spi->dev, "TXS timed out\n");
730 goto out;
731 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900732 dev_vdbg(&spi->dev, "write-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700733 word_len, *tx);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200734 writel_relaxed(*tx++, tx_reg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700735 }
736 if (rx != NULL) {
737 if (mcspi_wait_for_reg_bit(chstat_reg,
738 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
739 dev_err(&spi->dev, "RXS timed out\n");
740 goto out;
741 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000742
743 if (c == 1 && tx == NULL &&
744 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
745 omap2_mcspi_set_enable(spi, 0);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200746 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900747 dev_vdbg(&spi->dev, "read-%d %02x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000748 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000749 if (mcspi_wait_for_reg_bit(chstat_reg,
750 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
751 dev_err(&spi->dev,
752 "RXS timed out\n");
753 goto out;
754 }
755 c = 0;
756 } else if (c == 0 && tx == NULL) {
757 omap2_mcspi_set_enable(spi, 0);
758 }
759
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200760 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900761 dev_vdbg(&spi->dev, "read-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700762 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700763 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200764 } while (c);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700765 } else if (word_len <= 16) {
766 u16 *rx;
767 const u16 *tx;
768
769 rx = xfer->rx_buf;
770 tx = xfer->tx_buf;
771 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800772 c -= 2;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700773 if (tx != NULL) {
774 if (mcspi_wait_for_reg_bit(chstat_reg,
775 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
776 dev_err(&spi->dev, "TXS timed out\n");
777 goto out;
778 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900779 dev_vdbg(&spi->dev, "write-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700780 word_len, *tx);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200781 writel_relaxed(*tx++, tx_reg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700782 }
783 if (rx != NULL) {
784 if (mcspi_wait_for_reg_bit(chstat_reg,
785 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
786 dev_err(&spi->dev, "RXS timed out\n");
787 goto out;
788 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000789
790 if (c == 2 && tx == NULL &&
791 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
792 omap2_mcspi_set_enable(spi, 0);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200793 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900794 dev_vdbg(&spi->dev, "read-%d %04x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000795 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000796 if (mcspi_wait_for_reg_bit(chstat_reg,
797 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
798 dev_err(&spi->dev,
799 "RXS timed out\n");
800 goto out;
801 }
802 c = 0;
803 } else if (c == 0 && tx == NULL) {
804 omap2_mcspi_set_enable(spi, 0);
805 }
806
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200807 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900808 dev_vdbg(&spi->dev, "read-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700809 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700810 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200811 } while (c >= 2);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700812 } else if (word_len <= 32) {
813 u32 *rx;
814 const u32 *tx;
815
816 rx = xfer->rx_buf;
817 tx = xfer->tx_buf;
818 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800819 c -= 4;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700820 if (tx != NULL) {
821 if (mcspi_wait_for_reg_bit(chstat_reg,
822 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
823 dev_err(&spi->dev, "TXS timed out\n");
824 goto out;
825 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900826 dev_vdbg(&spi->dev, "write-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700827 word_len, *tx);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200828 writel_relaxed(*tx++, tx_reg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700829 }
830 if (rx != NULL) {
831 if (mcspi_wait_for_reg_bit(chstat_reg,
832 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
833 dev_err(&spi->dev, "RXS timed out\n");
834 goto out;
835 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000836
837 if (c == 4 && tx == NULL &&
838 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
839 omap2_mcspi_set_enable(spi, 0);
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200840 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900841 dev_vdbg(&spi->dev, "read-%d %08x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000842 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000843 if (mcspi_wait_for_reg_bit(chstat_reg,
844 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
845 dev_err(&spi->dev,
846 "RXS timed out\n");
847 goto out;
848 }
849 c = 0;
850 } else if (c == 0 && tx == NULL) {
851 omap2_mcspi_set_enable(spi, 0);
852 }
853
Victor Kamensky21b2ce52013-11-16 02:01:16 +0200854 *rx++ = readl_relaxed(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900855 dev_vdbg(&spi->dev, "read-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700856 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700857 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200858 } while (c >= 4);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700859 }
860
861 /* for TX_ONLY mode, be sure all words have shifted out */
862 if (xfer->rx_buf == NULL) {
863 if (mcspi_wait_for_reg_bit(chstat_reg,
864 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
865 dev_err(&spi->dev, "TXS timed out\n");
866 } else if (mcspi_wait_for_reg_bit(chstat_reg,
867 OMAP2_MCSPI_CHSTAT_EOT) < 0)
868 dev_err(&spi->dev, "EOT timed out\n");
Jason Wange1993ed2010-10-19 18:03:27 +0800869
870 /* disable chan to purge rx datas received in TX_ONLY transfer,
871 * otherwise these rx datas will affect the direct following
872 * RX_ONLY transfer.
873 */
874 omap2_mcspi_set_enable(spi, 0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700875 }
876out:
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000877 omap2_mcspi_set_enable(spi, 1);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700878 return count - c;
879}
880
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200881static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
882{
883 u32 div;
884
885 for (div = 0; div < 15; div++)
886 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
887 return div;
888
889 return 15;
890}
891
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700892/* called only when no transfer is active to this device */
893static int omap2_mcspi_setup_transfer(struct spi_device *spi,
894 struct spi_transfer *t)
895{
896 struct omap2_mcspi_cs *cs = spi->controller_state;
897 struct omap2_mcspi *mcspi;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700898 struct spi_master *spi_cntrl;
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100899 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700900 u8 word_len = spi->bits_per_word;
Scott Ellis9bd45172010-03-10 14:23:13 -0700901 u32 speed_hz = spi->max_speed_hz;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700902
903 mcspi = spi_master_get_devdata(spi->master);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700904 spi_cntrl = mcspi->master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700905
906 if (t != NULL && t->bits_per_word)
907 word_len = t->bits_per_word;
908
909 cs->word_len = word_len;
910
Scott Ellis9bd45172010-03-10 14:23:13 -0700911 if (t && t->speed_hz)
912 speed_hz = t->speed_hz;
913
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200914 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100915 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
916 clkd = omap2_mcspi_calc_divisor(speed_hz);
917 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
918 clkg = 0;
919 } else {
920 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
921 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
922 clkd = (div - 1) & 0xf;
923 extclk = (div - 1) >> 4;
924 clkg = OMAP2_MCSPI_CHCONF_CLKG;
925 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700926
Hemanth Va41ae1a2009-09-22 16:46:16 -0700927 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700928
929 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
930 * REVISIT: this controller could support SPI_3WIRE mode.
931 */
Daniel Mack2cd45172012-11-14 11:14:26 +0800932 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
Daniel Mack0384e902012-10-07 18:19:44 +0200933 l &= ~OMAP2_MCSPI_CHCONF_IS;
934 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
935 l |= OMAP2_MCSPI_CHCONF_DPE0;
936 } else {
937 l |= OMAP2_MCSPI_CHCONF_IS;
938 l |= OMAP2_MCSPI_CHCONF_DPE1;
939 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
940 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700941
942 /* wordlength */
943 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
944 l |= (word_len - 1) << 7;
945
946 /* set chipselect polarity; manage with FORCE */
947 if (!(spi->mode & SPI_CS_HIGH))
948 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
949 else
950 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
951
952 /* set clock divisor */
953 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100954 l |= clkd << 2;
955
956 /* set clock granularity */
957 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
958 l |= clkg;
959 if (clkg) {
960 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
961 cs->chctrl0 |= extclk << 8;
962 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
963 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700964
965 /* set SPI mode 0..3 */
966 if (spi->mode & SPI_CPOL)
967 l |= OMAP2_MCSPI_CHCONF_POL;
968 else
969 l &= ~OMAP2_MCSPI_CHCONF_POL;
970 if (spi->mode & SPI_CPHA)
971 l |= OMAP2_MCSPI_CHCONF_PHA;
972 else
973 l &= ~OMAP2_MCSPI_CHCONF_PHA;
974
Hemanth Va41ae1a2009-09-22 16:46:16 -0700975 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700976
Mark A. Greer97ca0d62014-07-01 20:28:32 -0700977 cs->mode = spi->mode;
978
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700979 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
Stefan Sørensenfaee9b02014-02-02 16:24:25 +0100980 speed_hz,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700981 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
982 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
983
984 return 0;
985}
986
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700987/*
988 * Note that we currently allow DMA only if we get a channel
989 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
990 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700991static int omap2_mcspi_request_dma(struct spi_device *spi)
992{
993 struct spi_master *master = spi->master;
994 struct omap2_mcspi *mcspi;
995 struct omap2_mcspi_dma *mcspi_dma;
Peter Ujfalusib085c612016-04-29 16:11:56 +0300996 int ret = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700997
998 mcspi = spi_master_get_devdata(master);
999 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1000
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001001 init_completion(&mcspi_dma->dma_rx_completion);
1002 init_completion(&mcspi_dma->dma_tx_completion);
1003
Peter Ujfalusib085c612016-04-29 16:11:56 +03001004 mcspi_dma->dma_rx = dma_request_chan(&master->dev,
1005 mcspi_dma->dma_rx_ch_name);
1006 if (IS_ERR(mcspi_dma->dma_rx)) {
1007 ret = PTR_ERR(mcspi_dma->dma_rx);
Russell King53741ed2012-04-23 13:51:48 +01001008 mcspi_dma->dma_rx = NULL;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001009 goto no_dma;
Russell King53741ed2012-04-23 13:51:48 +01001010 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001011
Peter Ujfalusib085c612016-04-29 16:11:56 +03001012 mcspi_dma->dma_tx = dma_request_chan(&master->dev,
1013 mcspi_dma->dma_tx_ch_name);
1014 if (IS_ERR(mcspi_dma->dma_tx)) {
1015 ret = PTR_ERR(mcspi_dma->dma_tx);
1016 mcspi_dma->dma_tx = NULL;
1017 dma_release_channel(mcspi_dma->dma_rx);
1018 mcspi_dma->dma_rx = NULL;
1019 }
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001020
1021no_dma:
Peter Ujfalusib085c612016-04-29 16:11:56 +03001022 return ret;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001023}
1024
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001025static int omap2_mcspi_setup(struct spi_device *spi)
1026{
1027 int ret;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301028 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1029 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001030 struct omap2_mcspi_dma *mcspi_dma;
1031 struct omap2_mcspi_cs *cs = spi->controller_state;
1032
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001033 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1034
1035 if (!cs) {
Russell King10aa5a32012-06-18 11:27:04 +01001036 cs = kzalloc(sizeof *cs, GFP_KERNEL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001037 if (!cs)
1038 return -ENOMEM;
1039 cs->base = mcspi->base + spi->chip_select * 0x14;
Russell Kinge5480b732008-09-01 21:51:50 +01001040 cs->phys = mcspi->phys + spi->chip_select * 0x14;
Mark A. Greer97ca0d62014-07-01 20:28:32 -07001041 cs->mode = 0;
Hemanth Va41ae1a2009-09-22 16:46:16 -07001042 cs->chconf0 = 0;
Stefan Sørensenfaee9b02014-02-02 16:24:25 +01001043 cs->chctrl0 = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001044 spi->controller_state = cs;
Tero Kristo89c05372009-09-22 16:46:17 -07001045 /* Link this to context save list */
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301046 list_add_tail(&cs->node, &ctx->cs);
Michael Welling2f538c02015-11-30 09:02:39 -06001047
1048 if (gpio_is_valid(spi->cs_gpio)) {
1049 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1050 if (ret) {
1051 dev_err(&spi->dev, "failed to request gpio\n");
1052 return ret;
1053 }
1054 gpio_direction_output(spi->cs_gpio,
1055 !(spi->mode & SPI_CS_HIGH));
1056 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001057 }
1058
Russell King8c7494a2012-04-23 13:56:25 +01001059 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001060 ret = omap2_mcspi_request_dma(spi);
Peter Ujfalusib085c612016-04-29 16:11:56 +03001061 if (ret)
1062 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1063 ret);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001064 }
1065
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301066 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301067 if (ret < 0)
1068 return ret;
Hemanth Va41ae1a2009-09-22 16:46:16 -07001069
Kyungmin Park86eeb6f2007-10-16 01:27:45 -07001070 ret = omap2_mcspi_setup_transfer(spi, NULL);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301071 pm_runtime_mark_last_busy(mcspi->dev);
1072 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001073
1074 return ret;
1075}
1076
1077static void omap2_mcspi_cleanup(struct spi_device *spi)
1078{
1079 struct omap2_mcspi *mcspi;
1080 struct omap2_mcspi_dma *mcspi_dma;
Tero Kristo89c05372009-09-22 16:46:17 -07001081 struct omap2_mcspi_cs *cs;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001082
1083 mcspi = spi_master_get_devdata(spi->master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001084
Scott Ellis5e774942010-03-10 14:22:45 -07001085 if (spi->controller_state) {
1086 /* Unlink controller state from context save list */
1087 cs = spi->controller_state;
1088 list_del(&cs->node);
Tero Kristo89c05372009-09-22 16:46:17 -07001089
Russell King10aa5a32012-06-18 11:27:04 +01001090 kfree(cs);
Scott Ellis5e774942010-03-10 14:22:45 -07001091 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001092
Scott Ellis99f1a432010-05-24 14:20:27 +00001093 if (spi->chip_select < spi->master->num_chipselect) {
1094 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1095
Russell King53741ed2012-04-23 13:51:48 +01001096 if (mcspi_dma->dma_rx) {
1097 dma_release_channel(mcspi_dma->dma_rx);
1098 mcspi_dma->dma_rx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +00001099 }
Russell King53741ed2012-04-23 13:51:48 +01001100 if (mcspi_dma->dma_tx) {
1101 dma_release_channel(mcspi_dma->dma_tx);
1102 mcspi_dma->dma_tx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +00001103 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001104 }
Michael Wellingbc7f9bb2015-05-08 13:31:01 -05001105
1106 if (gpio_is_valid(spi->cs_gpio))
1107 gpio_free(spi->cs_gpio);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001108}
1109
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001110static int omap2_mcspi_transfer_one(struct spi_master *master,
1111 struct spi_device *spi,
1112 struct spi_transfer *t)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001113{
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001114
1115 /* We only enable one channel at a time -- the one whose message is
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301116 * -- although this controller would gladly
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001117 * arbitrate among multiple channels. This corresponds to "single
1118 * channel" master mode. As a side effect, we need to manage the
1119 * chipselect with the FORCE bit ... CS != channel enable.
1120 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001121
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001122 struct omap2_mcspi *mcspi;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001123 struct omap2_mcspi_dma *mcspi_dma;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301124 struct omap2_mcspi_cs *cs;
1125 struct omap2_mcspi_device_config *cd;
1126 int par_override = 0;
1127 int status = 0;
1128 u32 chconf;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001129
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001130 mcspi = spi_master_get_devdata(master);
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001131 mcspi_dma = mcspi->dma_channels + spi->chip_select;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301132 cs = spi->controller_state;
1133 cd = spi->controller_data;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001134
Mark A. Greer97ca0d62014-07-01 20:28:32 -07001135 /*
1136 * The slave driver could have changed spi->mode in which case
1137 * it will be different from cs->mode (the current hardware setup).
1138 * If so, set par_override (even though its not a parity issue) so
1139 * omap2_mcspi_setup_transfer will be called to configure the hardware
1140 * with the correct mode on the first iteration of the loop below.
1141 */
1142 if (spi->mode != cs->mode)
1143 par_override = 1;
1144
Illia Smyrnovd33f4732013-06-17 16:31:06 +03001145 omap2_mcspi_set_enable(spi, 0);
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +01001146
Michael Wellinga06b4302015-05-23 21:13:44 -05001147 if (gpio_is_valid(spi->cs_gpio))
1148 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1149
Michael Wellingb28cb942015-05-07 18:36:53 -05001150 if (par_override ||
1151 (t->speed_hz != spi->max_speed_hz) ||
1152 (t->bits_per_word != spi->bits_per_word)) {
1153 par_override = 1;
1154 status = omap2_mcspi_setup_transfer(spi, t);
1155 if (status < 0)
1156 goto out;
1157 if (t->speed_hz == spi->max_speed_hz &&
1158 t->bits_per_word == spi->bits_per_word)
1159 par_override = 0;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301160 }
Michael Wellingb28cb942015-05-07 18:36:53 -05001161 if (cd && cd->cs_per_word) {
1162 chconf = mcspi->ctx.modulctrl;
1163 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1164 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1165 mcspi->ctx.modulctrl =
1166 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1167 }
1168
Michael Wellingb28cb942015-05-07 18:36:53 -05001169 chconf = mcspi_cached_chconf0(spi);
1170 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1171 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1172
1173 if (t->tx_buf == NULL)
1174 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1175 else if (t->rx_buf == NULL)
1176 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1177
1178 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1179 /* Turbo mode is for more than one word */
1180 if (t->len > ((cs->word_len + 7) >> 3))
1181 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1182 }
1183
1184 mcspi_write_chconf0(spi, chconf);
1185
1186 if (t->len) {
1187 unsigned count;
1188
1189 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001190 master->cur_msg_mapped &&
1191 master->can_dma(master, spi, t))
Michael Wellingb28cb942015-05-07 18:36:53 -05001192 omap2_mcspi_set_fifo(spi, t, 1);
1193
1194 omap2_mcspi_set_enable(spi, 1);
1195
1196 /* RX_ONLY mode needs dummy data in TX reg */
1197 if (t->tx_buf == NULL)
1198 writel_relaxed(0, cs->base
1199 + OMAP2_MCSPI_TX0);
1200
1201 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001202 master->cur_msg_mapped &&
1203 master->can_dma(master, spi, t))
Michael Wellingb28cb942015-05-07 18:36:53 -05001204 count = omap2_mcspi_txrx_dma(spi, t);
1205 else
1206 count = omap2_mcspi_txrx_pio(spi, t);
1207
1208 if (count != t->len) {
1209 status = -EIO;
1210 goto out;
1211 }
1212 }
1213
Michael Wellingb28cb942015-05-07 18:36:53 -05001214 omap2_mcspi_set_enable(spi, 0);
1215
1216 if (mcspi->fifo_depth > 0)
1217 omap2_mcspi_set_fifo(spi, t, 0);
1218
1219out:
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301220 /* Restore defaults if they were overriden */
1221 if (par_override) {
1222 par_override = 0;
1223 status = omap2_mcspi_setup_transfer(spi, NULL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001224 }
1225
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +01001226 if (cd && cd->cs_per_word) {
1227 chconf = mcspi->ctx.modulctrl;
1228 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1229 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1230 mcspi->ctx.modulctrl =
1231 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1232 }
1233
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301234 omap2_mcspi_set_enable(spi, 0);
1235
Michael Wellinga06b4302015-05-23 21:13:44 -05001236 if (gpio_is_valid(spi->cs_gpio))
1237 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1238
Illia Smyrnovd33f4732013-06-17 16:31:06 +03001239 if (mcspi->fifo_depth > 0 && t)
1240 omap2_mcspi_set_fifo(spi, t, 0);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301241
Michael Wellingb28cb942015-05-07 18:36:53 -05001242 return status;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001243}
1244
Neil Armstrong468a3202015-10-09 15:47:41 +02001245static int omap2_mcspi_prepare_message(struct spi_master *master,
1246 struct spi_message *msg)
1247{
1248 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1249 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1250 struct omap2_mcspi_cs *cs;
1251
1252 /* Only a single channel can have the FORCE bit enabled
1253 * in its chconf0 register.
1254 * Scan all channels and disable them except the current one.
1255 * A FORCE can remain from a last transfer having cs_change enabled
1256 */
1257 list_for_each_entry(cs, &ctx->cs, node) {
1258 if (msg->spi->controller_state == cs)
1259 continue;
1260
1261 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1262 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1263 writel_relaxed(cs->chconf0,
1264 cs->base + OMAP2_MCSPI_CHCONF0);
1265 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1266 }
1267 }
1268
1269 return 0;
1270}
1271
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001272static bool omap2_mcspi_can_dma(struct spi_master *master,
1273 struct spi_device *spi,
1274 struct spi_transfer *xfer)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001275{
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001276 return (xfer->len >= DMA_MIN_BYTES);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001277}
1278
Grant Likelyfd4a3192012-12-07 16:57:14 +00001279static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001280{
1281 struct spi_master *master = mcspi->master;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301282 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301283 int ret = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001284
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301285 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301286 if (ret < 0)
1287 return ret;
Jouni Hoganderddb22192009-07-29 15:02:11 -07001288
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301289 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
Matthias Brugger18dd6192013-01-24 13:28:58 +01001290 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301291 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001292
1293 omap2_mcspi_set_master_mode(master);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301294 pm_runtime_mark_last_busy(mcspi->dev);
1295 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001296 return 0;
1297}
1298
Govindraj.R1f1a4382011-02-02 17:52:15 +05301299static int omap_mcspi_runtime_resume(struct device *dev)
1300{
1301 struct omap2_mcspi *mcspi;
1302 struct spi_master *master;
1303
1304 master = dev_get_drvdata(dev);
1305 mcspi = spi_master_get_devdata(master);
1306 omap2_mcspi_restore_ctx(mcspi);
1307
1308 return 0;
1309}
1310
Benoit Coussond5a80032012-02-15 18:37:34 +01001311static struct omap2_mcspi_platform_config omap2_pdata = {
1312 .regs_offset = 0,
1313};
1314
1315static struct omap2_mcspi_platform_config omap4_pdata = {
1316 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1317};
1318
1319static const struct of_device_id omap_mcspi_of_match[] = {
1320 {
1321 .compatible = "ti,omap2-mcspi",
1322 .data = &omap2_pdata,
1323 },
1324 {
1325 .compatible = "ti,omap4-mcspi",
1326 .data = &omap4_pdata,
1327 },
1328 { },
1329};
1330MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
Girishccc7bae2008-02-06 01:38:16 -08001331
Grant Likelyfd4a3192012-12-07 16:57:14 +00001332static int omap2_mcspi_probe(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001333{
1334 struct spi_master *master;
Uwe Kleine-König83a01e72012-05-21 21:57:39 +02001335 const struct omap2_mcspi_platform_config *pdata;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001336 struct omap2_mcspi *mcspi;
1337 struct resource *r;
1338 int status = 0, i;
Benoit Coussond5a80032012-02-15 18:37:34 +01001339 u32 regs_offset = 0;
1340 static int bus_num = 1;
1341 struct device_node *node = pdev->dev.of_node;
1342 const struct of_device_id *match;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001343
1344 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1345 if (master == NULL) {
1346 dev_dbg(&pdev->dev, "master allocation failed\n");
1347 return -ENOMEM;
1348 }
1349
David Brownelle7db06b2009-06-17 16:26:04 -07001350 /* the spi->mode bits understood by this driver: */
1351 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -06001352 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001353 master->setup = omap2_mcspi_setup;
Mark Brownf0278a12013-07-28 15:34:37 +01001354 master->auto_runtime_pm = true;
Neil Armstrong468a3202015-10-09 15:47:41 +02001355 master->prepare_message = omap2_mcspi_prepare_message;
Franklin S Cooper Jr0ba18702016-07-07 12:17:50 -05001356 master->can_dma = omap2_mcspi_can_dma;
Michael Wellingb28cb942015-05-07 18:36:53 -05001357 master->transfer_one = omap2_mcspi_transfer_one;
Michael Wellingddcad7e2015-05-12 12:38:57 -05001358 master->set_cs = omap2_mcspi_set_cs;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001359 master->cleanup = omap2_mcspi_cleanup;
Benoit Coussond5a80032012-02-15 18:37:34 +01001360 master->dev.of_node = node;
Axel Linaca09242014-02-18 22:02:47 +08001361 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1362 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
Benoit Coussond5a80032012-02-15 18:37:34 +01001363
Jingoo Han24b5a822013-05-23 19:20:40 +09001364 platform_set_drvdata(pdev, master);
Daniel Mack0384e902012-10-07 18:19:44 +02001365
1366 mcspi = spi_master_get_devdata(master);
1367 mcspi->master = master;
1368
Benoit Coussond5a80032012-02-15 18:37:34 +01001369 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1370 if (match) {
1371 u32 num_cs = 1; /* default number of chipselect */
1372 pdata = match->data;
1373
1374 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1375 master->num_chipselect = num_cs;
1376 master->bus_num = bus_num++;
Daniel Mack2cd45172012-11-14 11:14:26 +08001377 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1378 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
Benoit Coussond5a80032012-02-15 18:37:34 +01001379 } else {
Jingoo Han8074cf02013-07-30 16:58:59 +09001380 pdata = dev_get_platdata(&pdev->dev);
Benoit Coussond5a80032012-02-15 18:37:34 +01001381 master->num_chipselect = pdata->num_cs;
1382 if (pdev->id != -1)
1383 master->bus_num = pdev->id;
Daniel Mack0384e902012-10-07 18:19:44 +02001384 mcspi->pin_dir = pdata->pin_dir;
Benoit Coussond5a80032012-02-15 18:37:34 +01001385 }
1386 regs_offset = pdata->regs_offset;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001387
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001388 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1389 if (r == NULL) {
1390 status = -ENODEV;
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301391 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001392 }
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301393
Benoit Coussond5a80032012-02-15 18:37:34 +01001394 r->start += regs_offset;
1395 r->end += regs_offset;
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301396 mcspi->phys = r->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001397
Thierry Redingb0ee5602013-01-21 11:09:18 +01001398 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1399 if (IS_ERR(mcspi->base)) {
1400 status = PTR_ERR(mcspi->base);
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301401 goto free_master;
Russell King55c381e2008-09-04 14:07:22 +01001402 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001403
Govindraj.R1f1a4382011-02-02 17:52:15 +05301404 mcspi->dev = &pdev->dev;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001405
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301406 INIT_LIST_HEAD(&mcspi->ctx.cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001407
Axel Lina6f936d2014-03-29 21:37:44 +08001408 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1409 sizeof(struct omap2_mcspi_dma),
1410 GFP_KERNEL);
1411 if (mcspi->dma_channels == NULL) {
1412 status = -ENOMEM;
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301413 goto free_master;
Axel Lina6f936d2014-03-29 21:37:44 +08001414 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001415
Charulatha V1a5d8192011-02-02 17:52:14 +05301416 for (i = 0; i < master->num_chipselect; i++) {
Peter Ujfalusib085c612016-04-29 16:11:56 +03001417 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1418 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001419 }
1420
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301421 if (status < 0)
Axel Lina6f936d2014-03-29 21:37:44 +08001422 goto free_master;
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301423
Shubhrajyoti D27b52842012-03-26 17:04:22 +05301424 pm_runtime_use_autosuspend(&pdev->dev);
1425 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301426 pm_runtime_enable(&pdev->dev);
1427
Wei Yongjun142e07b2013-04-18 11:14:59 +08001428 status = omap2_mcspi_master_setup(mcspi);
1429 if (status < 0)
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301430 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001431
Jingoo Hanb95e02b2013-09-24 13:40:29 +09001432 status = devm_spi_register_master(&pdev->dev, master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001433 if (status < 0)
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301434 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001435
1436 return status;
1437
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301438disable_pm:
Tony Lindgren0e6f3572016-02-10 15:02:46 -08001439 pm_runtime_dont_use_autosuspend(&pdev->dev);
1440 pm_runtime_put_sync(&pdev->dev);
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301441 pm_runtime_disable(&pdev->dev);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301442free_master:
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301443 spi_master_put(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001444 return status;
1445}
1446
Grant Likelyfd4a3192012-12-07 16:57:14 +00001447static int omap2_mcspi_remove(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001448{
Axel Lina6f936d2014-03-29 21:37:44 +08001449 struct spi_master *master = platform_get_drvdata(pdev);
1450 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001451
Tony Lindgren0e6f3572016-02-10 15:02:46 -08001452 pm_runtime_dont_use_autosuspend(mcspi->dev);
Shubhrajyoti Da93a2022012-08-22 11:35:14 +05301453 pm_runtime_put_sync(mcspi->dev);
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301454 pm_runtime_disable(&pdev->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001455
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001456 return 0;
1457}
1458
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001459/* work with hotplug and coldplug */
1460MODULE_ALIAS("platform:omap2_mcspi");
1461
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001462#ifdef CONFIG_SUSPEND
1463/*
1464 * When SPI wake up from off-mode, CS is in activate state. If it was in
1465 * unactive state when driver was suspend, then force it to unactive state at
1466 * wake up.
1467 */
1468static int omap2_mcspi_resume(struct device *dev)
1469{
1470 struct spi_master *master = dev_get_drvdata(dev);
1471 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301472 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1473 struct omap2_mcspi_cs *cs;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001474
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301475 pm_runtime_get_sync(mcspi->dev);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301476 list_for_each_entry(cs, &ctx->cs, node) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001477 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001478 /*
1479 * We need to toggle CS state for OMAP take this
1480 * change in account.
1481 */
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301482 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
Victor Kamensky21b2ce52013-11-16 02:01:16 +02001483 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301484 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
Victor Kamensky21b2ce52013-11-16 02:01:16 +02001485 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001486 }
1487 }
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301488 pm_runtime_mark_last_busy(mcspi->dev);
1489 pm_runtime_put_autosuspend(mcspi->dev);
Pascal Huerstbeca3652015-11-19 16:18:28 +01001490
1491 return pinctrl_pm_select_default_state(dev);
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001492}
Pascal Huerstbeca3652015-11-19 16:18:28 +01001493
1494static int omap2_mcspi_suspend(struct device *dev)
1495{
1496 return pinctrl_pm_select_sleep_state(dev);
1497}
1498
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001499#else
Pascal Huerstbeca3652015-11-19 16:18:28 +01001500#define omap2_mcspi_suspend NULL
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001501#define omap2_mcspi_resume NULL
1502#endif
1503
1504static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1505 .resume = omap2_mcspi_resume,
Pascal Huerstbeca3652015-11-19 16:18:28 +01001506 .suspend = omap2_mcspi_suspend,
Govindraj.R1f1a4382011-02-02 17:52:15 +05301507 .runtime_resume = omap_mcspi_runtime_resume,
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001508};
1509
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001510static struct platform_driver omap2_mcspi_driver = {
1511 .driver = {
1512 .name = "omap2_mcspi",
Benoit Coussond5a80032012-02-15 18:37:34 +01001513 .pm = &omap2_mcspi_pm_ops,
1514 .of_match_table = omap_mcspi_of_match,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001515 },
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001516 .probe = omap2_mcspi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001517 .remove = omap2_mcspi_remove,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001518};
1519
Felipe Balbi9fdca9d2012-03-14 11:18:31 +02001520module_platform_driver(omap2_mcspi_driver);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001521MODULE_LICENSE("GPL");