blob: fa9b03c78b74754f84a8e0ae5ff981807cea1dcf [file] [log] [blame]
Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Chris Wilson5eddb702010-09-11 13:48:45 +010028#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
Paulo Zanonia5c961d2012-10-24 15:59:34 -020029#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
Chris Wilson5eddb702010-09-11 13:48:45 +010030
Eugeni Dodonov2b139522012-03-29 12:32:22 -030031#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
Chon Ming Lee00fc31b2014-04-09 13:28:15 +030032#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c)
33#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c)
Eugeni Dodonov2b139522012-03-29 12:32:22 -030034
Daniel Vetter6b26c862012-04-24 14:04:12 +020035#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
36#define _MASKED_BIT_DISABLE(a) ((a) << 16)
37
Jesse Barnes585fb112008-07-29 11:54:06 -070038/* PCI config space */
39
40#define HPLLCC 0xc0 /* 855 only */
Jesse Barnes652c3932009-08-17 13:31:43 -070041#define GC_CLOCK_CONTROL_MASK (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070042#define GC_CLOCK_133_200 (0 << 0)
43#define GC_CLOCK_100_200 (1 << 0)
44#define GC_CLOCK_100_133 (2 << 0)
45#define GC_CLOCK_166_250 (3 << 0)
Jesse Barnesf97108d2010-01-29 11:27:07 -080046#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -070047#define GCFGC 0xf0 /* 915+ only */
48#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
49#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
50#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +020051#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
52#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
53#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
54#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
55#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
56#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -070057#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -070058#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
60#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
61#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
62#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
63#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
64#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
65#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
66#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
67#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
68#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
72#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
73#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
74#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
75#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
76#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Daniel Vetter7f1bdbc2014-01-16 16:42:54 +010077#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
78
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070079
80/* Graphics reset regs */
Kenneth Graunke0573ed42010-09-11 03:17:19 -070081#define I965_GDRST 0xc0 /* PCI config register */
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070082#define GRDOM_FULL (0<<2)
83#define GRDOM_RENDER (1<<2)
84#define GRDOM_MEDIA (3<<2)
Jesse Barnes8a5c2ae2013-03-28 13:57:19 -070085#define GRDOM_MASK (3<<2)
Daniel Vetter5ccce182012-04-27 15:17:45 +020086#define GRDOM_RESET_ENABLE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -070087
Ville Syrjäläb3a3f032014-05-19 19:23:24 +030088#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
89#define ILK_GRDOM_FULL (0<<1)
90#define ILK_GRDOM_RENDER (1<<1)
91#define ILK_GRDOM_MEDIA (3<<1)
92#define ILK_GRDOM_MASK (3<<1)
93#define ILK_GRDOM_RESET_ENABLE (1<<0)
94
Jesse Barnes07b7ddd2011-08-03 11:28:44 -070095#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
96#define GEN6_MBC_SNPCR_SHIFT 21
97#define GEN6_MBC_SNPCR_MASK (3<<21)
98#define GEN6_MBC_SNPCR_MAX (0<<21)
99#define GEN6_MBC_SNPCR_MED (1<<21)
100#define GEN6_MBC_SNPCR_LOW (2<<21)
101#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
102
Imre Deak9e72b462014-05-05 15:13:55 +0300103#define VLV_G3DCTL 0x9024
104#define VLV_GSCKGCTL 0x9028
105
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100106#define GEN6_MBCTL 0x0907c
107#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
108#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
109#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
110#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
111#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
112
Eric Anholtcff458c2010-11-18 09:31:14 +0800113#define GEN6_GDRST 0x941c
114#define GEN6_GRDOM_FULL (1 << 0)
115#define GEN6_GRDOM_RENDER (1 << 1)
116#define GEN6_GRDOM_MEDIA (1 << 2)
117#define GEN6_GRDOM_BLT (1 << 3)
118
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100119#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
120#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
121#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
122#define PP_DIR_DCLV_2G 0xffffffff
123
Ben Widawsky94e409c2013-11-04 22:29:36 -0800124#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
125#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
126
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100127#define GAM_ECOCHK 0x4090
128#define ECOCHK_SNB_BIT (1<<10)
Ben Widawskye3dff582013-03-20 14:49:14 -0700129#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100130#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
131#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300132#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
133#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
134#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
135#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
136#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100137
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200138#define GAC_ECO_BITS 0x14090
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300139#define ECOBITS_SNB_BIT (1<<13)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200140#define ECOBITS_PPGTT_CACHE64B (3<<8)
141#define ECOBITS_PPGTT_CACHE4B (0<<8)
142
Daniel Vetterbe901a52012-04-11 20:42:39 +0200143#define GAB_CTL 0x24000
144#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
145
Jesse Barnes585fb112008-07-29 11:54:06 -0700146/* VGA stuff */
147
148#define VGA_ST01_MDA 0x3ba
149#define VGA_ST01_CGA 0x3da
150
151#define VGA_MSR_WRITE 0x3c2
152#define VGA_MSR_READ 0x3cc
153#define VGA_MSR_MEM_EN (1<<1)
154#define VGA_MSR_CGA_MODE (1<<0)
155
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300156#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100157#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300158#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700159
160#define VGA_AR_INDEX 0x3c0
161#define VGA_AR_VID_EN (1<<5)
162#define VGA_AR_DATA_WRITE 0x3c0
163#define VGA_AR_DATA_READ 0x3c1
164
165#define VGA_GR_INDEX 0x3ce
166#define VGA_GR_DATA 0x3cf
167/* GR05 */
168#define VGA_GR_MEM_READ_MODE_SHIFT 3
169#define VGA_GR_MEM_READ_MODE_PLANE 1
170/* GR06 */
171#define VGA_GR_MEM_MODE_MASK 0xc
172#define VGA_GR_MEM_MODE_SHIFT 2
173#define VGA_GR_MEM_A0000_AFFFF 0
174#define VGA_GR_MEM_A0000_BFFFF 1
175#define VGA_GR_MEM_B0000_B7FFF 2
176#define VGA_GR_MEM_B0000_BFFFF 3
177
178#define VGA_DACMASK 0x3c6
179#define VGA_DACRX 0x3c7
180#define VGA_DACWX 0x3c8
181#define VGA_DACDATA 0x3c9
182
183#define VGA_CR_INDEX_MDA 0x3b4
184#define VGA_CR_DATA_MDA 0x3b5
185#define VGA_CR_INDEX_CGA 0x3d4
186#define VGA_CR_DATA_CGA 0x3d5
187
188/*
Brad Volkin351e3db2014-02-18 10:15:46 -0800189 * Instruction field definitions used by the command parser
190 */
191#define INSTR_CLIENT_SHIFT 29
192#define INSTR_CLIENT_MASK 0xE0000000
193#define INSTR_MI_CLIENT 0x0
194#define INSTR_BC_CLIENT 0x2
195#define INSTR_RC_CLIENT 0x3
196#define INSTR_SUBCLIENT_SHIFT 27
197#define INSTR_SUBCLIENT_MASK 0x18000000
198#define INSTR_MEDIA_SUBCLIENT 0x2
199
200/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700201 * Memory interface instructions used by the kernel
202 */
203#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
Brad Volkind4d48032014-02-18 10:15:54 -0800204/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
205#define MI_GLOBAL_GTT (1<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -0700206
207#define MI_NOOP MI_INSTR(0, 0)
208#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
209#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200210#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700211#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
212#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
213#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
214#define MI_FLUSH MI_INSTR(0x04, 0)
215#define MI_READ_FLUSH (1 << 0)
216#define MI_EXE_FLUSH (1 << 1)
217#define MI_NO_WRITE_FLUSH (1 << 2)
218#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
219#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800220#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Ben Widawsky0e792842013-12-16 20:50:37 -0800221#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
222#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
223#define MI_ARB_ENABLE (1<<0)
224#define MI_ARB_DISABLE (0<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700225#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800226#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
227#define MI_SUSPEND_FLUSH_EN (1<<0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400228#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200229#define MI_OVERLAY_CONTINUE (0x0<<21)
230#define MI_OVERLAY_ON (0x1<<21)
231#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700232#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500233#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700234#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500235#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200236/* IVB has funny definitions for which plane to flip. */
237#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
238#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
239#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
240#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
241#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
242#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
Ben Widawsky0e792842013-12-16 20:50:37 -0800243#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
244#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
245#define MI_SEMAPHORE_UPDATE (1<<21)
246#define MI_SEMAPHORE_COMPARE (1<<20)
247#define MI_SEMAPHORE_REGISTER (1<<18)
248#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
249#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
250#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
251#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
252#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
253#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
254#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
255#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
256#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
257#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
258#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
259#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
Daniel Vettera028c4b2014-03-15 00:08:56 +0100260#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
261#define MI_SEMAPHORE_SYNC_MASK (3<<16)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800262#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
263#define MI_MM_SPACE_GTT (1<<8)
264#define MI_MM_SPACE_PHYSICAL (0<<8)
265#define MI_SAVE_EXT_STATE_EN (1<<3)
266#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800267#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800268#define MI_RESTORE_INHIBIT (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700269#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
270#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
271#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
272#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000273/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
274 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
275 * simply ignores the register load under certain conditions.
276 * - One can actually load arbitrary many arbitrary registers: Simply issue x
277 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
278 */
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100279#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
280#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
Damien Lespiaub76bfeb2014-04-07 20:24:33 +0100281#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
Ben Widawsky0e792842013-12-16 20:50:37 -0800282#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
Chris Wilson71a77e02011-02-02 12:13:49 +0000283#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
Jesse Barnes9a289772012-10-26 09:42:42 -0700284#define MI_FLUSH_DW_STORE_INDEX (1<<21)
285#define MI_INVALIDATE_TLB (1<<18)
286#define MI_FLUSH_DW_OP_STOREDW (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800287#define MI_FLUSH_DW_OP_MASK (3<<14)
Brad Volkinb18b3962014-02-18 10:15:53 -0800288#define MI_FLUSH_DW_NOTIFY (1<<8)
Jesse Barnes9a289772012-10-26 09:42:42 -0700289#define MI_INVALIDATE_BSD (1<<7)
290#define MI_FLUSH_DW_USE_GTT (1<<2)
291#define MI_FLUSH_DW_USE_PPGTT (0<<2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700292#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100293#define MI_BATCH_NON_SECURE (1)
294/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
Ben Widawsky0e792842013-12-16 20:50:37 -0800295#define MI_BATCH_NON_SECURE_I965 (1<<8)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100296#define MI_BATCH_PPGTT_HSW (1<<8)
Ben Widawsky0e792842013-12-16 20:50:37 -0800297#define MI_BATCH_NON_SECURE_HSW (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700298#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson65f56872012-04-17 16:38:12 +0100299#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
Ben Widawsky1c7a0622013-11-02 21:07:12 -0700300#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
Ben Widawsky0e792842013-12-16 20:50:37 -0800301
Rodrigo Vivi94353732013-08-28 16:45:46 -0300302
303#define MI_PREDICATE_RESULT_2 (0x2214)
304#define LOWER_SLICE_ENABLED (1<<0)
305#define LOWER_SLICE_DISABLED (0<<0)
306
Jesse Barnes585fb112008-07-29 11:54:06 -0700307/*
308 * 3D instructions used by the kernel
309 */
310#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
311
312#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
313#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
314#define SC_UPDATE_SCISSOR (0x1<<1)
315#define SC_ENABLE_MASK (0x1<<0)
316#define SC_ENABLE (0x1<<0)
317#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
318#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
319#define SCI_YMIN_MASK (0xffff<<16)
320#define SCI_XMIN_MASK (0xffff<<0)
321#define SCI_YMAX_MASK (0xffff<<16)
322#define SCI_XMAX_MASK (0xffff<<0)
323#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
324#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
325#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
326#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
327#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
328#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
329#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
330#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
331#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
332#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
333#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
334#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
335#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
336#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
337#define BLT_DEPTH_8 (0<<24)
338#define BLT_DEPTH_16_565 (1<<24)
339#define BLT_DEPTH_16_1555 (2<<24)
340#define BLT_DEPTH_32 (3<<24)
341#define BLT_ROP_GXCOPY (0xcc<<16)
342#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
343#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
344#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
345#define ASYNC_FLIP (1<<22)
346#define DISPLAY_PLANE_A (0<<20)
347#define DISPLAY_PLANE_B (1<<20)
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200348#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200349#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
Brad Volkinf0a346b2014-02-18 10:15:52 -0800350#define PIPE_CONTROL_MMIO_WRITE (1<<23)
Brad Volkin114d4f72014-02-18 10:15:55 -0800351#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
Jesse Barnes8d315282011-10-16 10:23:31 +0200352#define PIPE_CONTROL_CS_STALL (1<<20)
Ben Widawskycc0f6392012-06-04 14:42:49 -0700353#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200354#define PIPE_CONTROL_QW_WRITE (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800355#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200356#define PIPE_CONTROL_DEPTH_STALL (1<<13)
357#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200358#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200359#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
360#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
361#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
362#define PIPE_CONTROL_NOTIFY (1<<8)
Jesse Barnes8d315282011-10-16 10:23:31 +0200363#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
364#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
365#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200366#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200367#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700368#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700369
Brad Volkin3a6fa982014-02-18 10:15:47 -0800370/*
371 * Commands used only by the command parser
372 */
373#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
374#define MI_ARB_CHECK MI_INSTR(0x05, 0)
375#define MI_RS_CONTROL MI_INSTR(0x06, 0)
376#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
377#define MI_PREDICATE MI_INSTR(0x0C, 0)
378#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
379#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
Brad Volkin9c640d12014-02-18 10:15:48 -0800380#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800381#define MI_URB_CLEAR MI_INSTR(0x19, 0)
382#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
383#define MI_CLFLUSH MI_INSTR(0x27, 0)
Brad Volkind4d48032014-02-18 10:15:54 -0800384#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
385#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800386#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
387#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
388#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
389#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
390#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
391#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
392
393#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
394#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
Brad Volkinf0a346b2014-02-18 10:15:52 -0800395#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
396#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800397#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
398#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
399#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
400 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
401#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
402 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
403#define GFX_OP_3DSTATE_SO_DECL_LIST \
404 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
405
406#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
407 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
408#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
409 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
410#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
411 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
412#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
413 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
414#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
415 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
416
417#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
418
419#define COLOR_BLT ((0x2<<29)|(0x40<<22))
420#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100421
422/*
Brad Volkin5947de92014-02-18 10:15:50 -0800423 * Registers used only by the command parser
424 */
425#define BCS_SWCTRL 0x22200
426
427#define HS_INVOCATION_COUNT 0x2300
428#define DS_INVOCATION_COUNT 0x2308
429#define IA_VERTICES_COUNT 0x2310
430#define IA_PRIMITIVES_COUNT 0x2318
431#define VS_INVOCATION_COUNT 0x2320
432#define GS_INVOCATION_COUNT 0x2328
433#define GS_PRIMITIVES_COUNT 0x2330
434#define CL_INVOCATION_COUNT 0x2338
435#define CL_PRIMITIVES_COUNT 0x2340
436#define PS_INVOCATION_COUNT 0x2348
437#define PS_DEPTH_COUNT 0x2350
438
439/* There are the 4 64-bit counter registers, one for each stream output */
440#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
441
Brad Volkin113a0472014-04-08 14:18:58 -0700442#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
443
444#define GEN7_3DPRIM_END_OFFSET 0x2420
445#define GEN7_3DPRIM_START_VERTEX 0x2430
446#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
447#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
448#define GEN7_3DPRIM_START_INSTANCE 0x243C
449#define GEN7_3DPRIM_BASE_VERTEX 0x2440
450
Kenneth Graunke180b8132014-03-25 22:52:03 -0700451#define OACONTROL 0x2360
452
Brad Volkin220375a2014-02-18 10:15:51 -0800453#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
454#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
455#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
456 _GEN7_PIPEA_DE_LOAD_SL, \
457 _GEN7_PIPEB_DE_LOAD_SL)
458
Brad Volkin5947de92014-02-18 10:15:50 -0800459/*
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100460 * Reset registers
461 */
462#define DEBUG_RESET_I830 0x6070
463#define DEBUG_RESET_FULL (1<<7)
464#define DEBUG_RESET_RENDER (1<<8)
465#define DEBUG_RESET_DISPLAY (1<<9)
466
Jesse Barnes57f350b2012-03-28 13:39:25 -0700467/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300468 * IOSF sideband
469 */
470#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
471#define IOSF_DEVFN_SHIFT 24
472#define IOSF_OPCODE_SHIFT 16
473#define IOSF_PORT_SHIFT 8
474#define IOSF_BYTE_ENABLES_SHIFT 4
475#define IOSF_BAR_SHIFT 1
476#define IOSF_SB_BUSY (1<<0)
Jesse Barnesf3419152013-11-04 11:52:44 -0800477#define IOSF_PORT_BUNIT 0x3
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300478#define IOSF_PORT_PUNIT 0x4
479#define IOSF_PORT_NC 0x11
480#define IOSF_PORT_DPIO 0x12
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300481#define IOSF_PORT_DPIO_2 0x1a
Jani Nikulae9f882a2013-08-27 15:12:14 +0300482#define IOSF_PORT_GPIO_NC 0x13
483#define IOSF_PORT_CCK 0x14
484#define IOSF_PORT_CCU 0xA9
485#define IOSF_PORT_GPS_CORE 0x48
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530486#define IOSF_PORT_FLISDSI 0x1B
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300487#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
488#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
489
Jesse Barnes30a970c2013-11-04 13:48:12 -0800490/* See configdb bunit SB addr map */
491#define BUNIT_REG_BISOC 0x11
492
Jesse Barnes30a970c2013-11-04 13:48:12 -0800493#define PUNIT_REG_DSPFREQ 0x36
494#define DSPFREQSTAT_SHIFT 30
495#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
496#define DSPFREQGUAR_SHIFT 14
497#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Imre Deaka30180a2014-03-04 19:23:02 +0200498
499/* See the PUNIT HAS v0.8 for the below bits */
500enum punit_power_well {
501 PUNIT_POWER_WELL_RENDER = 0,
502 PUNIT_POWER_WELL_MEDIA = 1,
503 PUNIT_POWER_WELL_DISP2D = 3,
504 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
505 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
506 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
507 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
508 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
509 PUNIT_POWER_WELL_DPIO_RX0 = 10,
510 PUNIT_POWER_WELL_DPIO_RX1 = 11,
511
512 PUNIT_POWER_WELL_NUM,
513};
514
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800515#define PUNIT_REG_PWRGT_CTRL 0x60
516#define PUNIT_REG_PWRGT_STATUS 0x61
Imre Deaka30180a2014-03-04 19:23:02 +0200517#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
518#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
519#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
520#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
521#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800522
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300523#define PUNIT_REG_GPU_LFM 0xd3
524#define PUNIT_REG_GPU_FREQ_REQ 0xd4
525#define PUNIT_REG_GPU_FREQ_STS 0xd8
Ville Syrjäläe8474402013-06-26 17:43:24 +0300526#define GENFREQSTATUS (1<<0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300527#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
528
529#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
530#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
531
Deepak S2b6b3a02014-05-27 15:59:30 +0530532#define PUNIT_GPU_STATUS_REG 0xdb
533#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
534#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
535#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
536#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
537
538#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
539#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
540#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
541
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300542#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
543#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
544#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
545#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
546#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
547#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
548#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
549#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
550#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
551#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
552
ymohanmabe4fc042013-08-27 23:40:56 +0300553/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +0800554#define CCK_FUSE_REG 0x8
555#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +0300556#define CCK_REG_DSI_PLL_FUSE 0x44
557#define CCK_REG_DSI_PLL_CONTROL 0x48
558#define DSI_PLL_VCO_EN (1 << 31)
559#define DSI_PLL_LDO_GATE (1 << 30)
560#define DSI_PLL_P1_POST_DIV_SHIFT 17
561#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
562#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
563#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
564#define DSI_PLL_MUX_MASK (3 << 9)
565#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
566#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
567#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
568#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
569#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
570#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
571#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
572#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
573#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
574#define DSI_PLL_LOCK (1 << 0)
575#define CCK_REG_DSI_PLL_DIVIDER 0x4c
576#define DSI_PLL_LFSR (1 << 31)
577#define DSI_PLL_FRACTION_EN (1 << 30)
578#define DSI_PLL_FRAC_COUNTER_SHIFT 27
579#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
580#define DSI_PLL_USYNC_CNT_SHIFT 18
581#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
582#define DSI_PLL_N1_DIV_SHIFT 16
583#define DSI_PLL_N1_DIV_MASK (3 << 16)
584#define DSI_PLL_M1_DIV_SHIFT 0
585#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800586#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
ymohanmabe4fc042013-08-27 23:40:56 +0300587
Ville Syrjälä0e767182014-04-25 20:14:31 +0300588/**
589 * DOC: DPIO
590 *
591 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
592 * ports. DPIO is the name given to such a display PHY. These PHYs
593 * don't follow the standard programming model using direct MMIO
594 * registers, and instead their registers must be accessed trough IOSF
595 * sideband. VLV has one such PHY for driving ports B and C, and CHV
596 * adds another PHY for driving port D. Each PHY responds to specific
597 * IOSF-SB port.
598 *
599 * Each display PHY is made up of one or two channels. Each channel
600 * houses a common lane part which contains the PLL and other common
601 * logic. CH0 common lane also contains the IOSF-SB logic for the
602 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
603 * must be running when any DPIO registers are accessed.
604 *
605 * In addition to having their own registers, the PHYs are also
606 * controlled through some dedicated signals from the display
607 * controller. These include PLL reference clock enable, PLL enable,
608 * and CRI clock selection, for example.
609 *
610 * Eeach channel also has two splines (also called data lanes), and
611 * each spline is made up of one Physical Access Coding Sub-Layer
612 * (PCS) block and two TX lanes. So each channel has two PCS blocks
613 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
614 * data/clock pairs depending on the output type.
615 *
616 * Additionally the PHY also contains an AUX lane with AUX blocks
617 * for each channel. This is used for DP AUX communication, but
618 * this fact isn't really relevant for the driver since AUX is
619 * controlled from the display controller side. No DPIO registers
620 * need to be accessed during AUX communication,
621 *
622 * Generally the common lane corresponds to the pipe and
623 * the spline (PCS/TX) correponds to the port.
624 *
625 * For dual channel PHY (VLV/CHV):
626 *
627 * pipe A == CMN/PLL/REF CH0
628 *
629 * pipe B == CMN/PLL/REF CH1
630 *
631 * port B == PCS/TX CH0
632 *
633 * port C == PCS/TX CH1
634 *
635 * This is especially important when we cross the streams
636 * ie. drive port B with pipe B, or port C with pipe A.
637 *
638 * For single channel PHY (CHV):
639 *
640 * pipe C == CMN/PLL/REF CH0
641 *
642 * port D == PCS/TX CH0
643 *
644 * Note: digital port B is DDI0, digital port C is DDI1,
645 * digital port D is DDI2
646 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300647/*
Ville Syrjälä0e767182014-04-25 20:14:31 +0300648 * Dual channel PHY (VLV/CHV)
649 * ---------------------------------
650 * | CH0 | CH1 |
651 * | CMN/PLL/REF | CMN/PLL/REF |
652 * |---------------|---------------| Display PHY
653 * | PCS01 | PCS23 | PCS01 | PCS23 |
654 * |-------|-------|-------|-------|
655 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
656 * ---------------------------------
657 * | DDI0 | DDI1 | DP/HDMI ports
658 * ---------------------------------
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200659 *
Ville Syrjälä0e767182014-04-25 20:14:31 +0300660 * Single channel PHY (CHV)
661 * -----------------
662 * | CH0 |
663 * | CMN/PLL/REF |
664 * |---------------| Display PHY
665 * | PCS01 | PCS23 |
666 * |-------|-------|
667 * |TX0|TX1|TX2|TX3|
668 * -----------------
669 * | DDI2 | DP/HDMI port
670 * -----------------
Jesse Barnes57f350b2012-03-28 13:39:25 -0700671 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300672#define DPIO_DEVFN 0
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300673
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200674#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700675#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
676#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
677#define DPIO_SFR_BYPASS (1<<1)
Jesse Barnes40e9cf62013-10-03 11:35:46 -0700678#define DPIO_CMNRST (1<<0)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700679
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800680#define DPIO_PHY(pipe) ((pipe) >> 1)
681#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
682
Daniel Vetter598fac62013-04-18 22:01:46 +0200683/*
684 * Per pipe/PLL DPIO regs
685 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800686#define _VLV_PLL_DW3_CH0 0x800c
Jesse Barnes57f350b2012-03-28 13:39:25 -0700687#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +0200688#define DPIO_POST_DIV_DAC 0
689#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
690#define DPIO_POST_DIV_LVDS1 2
691#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700692#define DPIO_K_SHIFT (24) /* 4 bits */
693#define DPIO_P1_SHIFT (21) /* 3 bits */
694#define DPIO_P2_SHIFT (16) /* 5 bits */
695#define DPIO_N_SHIFT (12) /* 4 bits */
696#define DPIO_ENABLE_CALIBRATION (1<<11)
697#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
698#define DPIO_M2DIV_MASK 0xff
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800699#define _VLV_PLL_DW3_CH1 0x802c
700#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700701
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800702#define _VLV_PLL_DW5_CH0 0x8014
Jesse Barnes57f350b2012-03-28 13:39:25 -0700703#define DPIO_REFSEL_OVERRIDE 27
704#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
705#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
706#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530707#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700708#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
709#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800710#define _VLV_PLL_DW5_CH1 0x8034
711#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700712
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800713#define _VLV_PLL_DW7_CH0 0x801c
714#define _VLV_PLL_DW7_CH1 0x803c
715#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700716
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800717#define _VLV_PLL_DW8_CH0 0x8040
718#define _VLV_PLL_DW8_CH1 0x8060
719#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200720
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800721#define VLV_PLL_DW9_BCAST 0xc044
722#define _VLV_PLL_DW9_CH0 0x8044
723#define _VLV_PLL_DW9_CH1 0x8064
724#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200725
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800726#define _VLV_PLL_DW10_CH0 0x8048
727#define _VLV_PLL_DW10_CH1 0x8068
728#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200729
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800730#define _VLV_PLL_DW11_CH0 0x804c
731#define _VLV_PLL_DW11_CH1 0x806c
732#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700733
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800734/* Spec for ref block start counts at DW10 */
735#define VLV_REF_DW13 0x80ac
Daniel Vetter598fac62013-04-18 22:01:46 +0200736
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800737#define VLV_CMN_DW0 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100738
Daniel Vetter598fac62013-04-18 22:01:46 +0200739/*
740 * Per DDI channel DPIO regs
741 */
742
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800743#define _VLV_PCS_DW0_CH0 0x8200
744#define _VLV_PCS_DW0_CH1 0x8400
Daniel Vetter598fac62013-04-18 22:01:46 +0200745#define DPIO_PCS_TX_LANE2_RESET (1<<16)
746#define DPIO_PCS_TX_LANE1_RESET (1<<7)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800747#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200748
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300749#define _VLV_PCS01_DW0_CH0 0x200
750#define _VLV_PCS23_DW0_CH0 0x400
751#define _VLV_PCS01_DW0_CH1 0x2600
752#define _VLV_PCS23_DW0_CH1 0x2800
753#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
754#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
755
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800756#define _VLV_PCS_DW1_CH0 0x8204
757#define _VLV_PCS_DW1_CH1 0x8404
Ville Syrjäläd2152b22014-04-28 14:15:24 +0300758#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
Daniel Vetter598fac62013-04-18 22:01:46 +0200759#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
760#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
761#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
762#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800763#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200764
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300765#define _VLV_PCS01_DW1_CH0 0x204
766#define _VLV_PCS23_DW1_CH0 0x404
767#define _VLV_PCS01_DW1_CH1 0x2604
768#define _VLV_PCS23_DW1_CH1 0x2804
769#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
770#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
771
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800772#define _VLV_PCS_DW8_CH0 0x8220
773#define _VLV_PCS_DW8_CH1 0x8420
Ville Syrjälä9197c882014-04-09 13:29:05 +0300774#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
775#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800776#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200777
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800778#define _VLV_PCS01_DW8_CH0 0x0220
779#define _VLV_PCS23_DW8_CH0 0x0420
780#define _VLV_PCS01_DW8_CH1 0x2620
781#define _VLV_PCS23_DW8_CH1 0x2820
782#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
783#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200784
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800785#define _VLV_PCS_DW9_CH0 0x8224
786#define _VLV_PCS_DW9_CH1 0x8424
787#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200788
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300789#define _CHV_PCS_DW10_CH0 0x8228
790#define _CHV_PCS_DW10_CH1 0x8428
791#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
792#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
793#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
794
Ville Syrjälä1966e592014-04-09 13:29:04 +0300795#define _VLV_PCS01_DW10_CH0 0x0228
796#define _VLV_PCS23_DW10_CH0 0x0428
797#define _VLV_PCS01_DW10_CH1 0x2628
798#define _VLV_PCS23_DW10_CH1 0x2828
799#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
800#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
801
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800802#define _VLV_PCS_DW11_CH0 0x822c
803#define _VLV_PCS_DW11_CH1 0x842c
804#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200805
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800806#define _VLV_PCS_DW12_CH0 0x8230
807#define _VLV_PCS_DW12_CH1 0x8430
808#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200809
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800810#define _VLV_PCS_DW14_CH0 0x8238
811#define _VLV_PCS_DW14_CH1 0x8438
812#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200813
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800814#define _VLV_PCS_DW23_CH0 0x825c
815#define _VLV_PCS_DW23_CH1 0x845c
816#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200817
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800818#define _VLV_TX_DW2_CH0 0x8288
819#define _VLV_TX_DW2_CH1 0x8488
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300820#define DPIO_SWING_MARGIN_SHIFT 16
821#define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT)
822#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800823#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200824
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800825#define _VLV_TX_DW3_CH0 0x828c
826#define _VLV_TX_DW3_CH1 0x848c
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300827/* The following bit for CHV phy */
828#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800829#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
830
831#define _VLV_TX_DW4_CH0 0x8290
832#define _VLV_TX_DW4_CH1 0x8490
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300833#define DPIO_SWING_DEEMPH9P5_SHIFT 24
834#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800835#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
836
837#define _VLV_TX3_DW4_CH0 0x690
838#define _VLV_TX3_DW4_CH1 0x2a90
839#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
840
841#define _VLV_TX_DW5_CH0 0x8294
842#define _VLV_TX_DW5_CH1 0x8494
Daniel Vetter598fac62013-04-18 22:01:46 +0200843#define DPIO_TX_OCALINIT_EN (1<<31)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800844#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200845
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800846#define _VLV_TX_DW11_CH0 0x82ac
847#define _VLV_TX_DW11_CH1 0x84ac
848#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200849
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800850#define _VLV_TX_DW14_CH0 0x82b8
851#define _VLV_TX_DW14_CH1 0x84b8
852#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530853
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300854/* CHV dpPhy registers */
855#define _CHV_PLL_DW0_CH0 0x8000
856#define _CHV_PLL_DW0_CH1 0x8180
857#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
858
859#define _CHV_PLL_DW1_CH0 0x8004
860#define _CHV_PLL_DW1_CH1 0x8184
861#define DPIO_CHV_N_DIV_SHIFT 8
862#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
863#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
864
865#define _CHV_PLL_DW2_CH0 0x8008
866#define _CHV_PLL_DW2_CH1 0x8188
867#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
868
869#define _CHV_PLL_DW3_CH0 0x800c
870#define _CHV_PLL_DW3_CH1 0x818c
871#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
872#define DPIO_CHV_FIRST_MOD (0 << 8)
873#define DPIO_CHV_SECOND_MOD (1 << 8)
874#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
875#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
876
877#define _CHV_PLL_DW6_CH0 0x8018
878#define _CHV_PLL_DW6_CH1 0x8198
879#define DPIO_CHV_GAIN_CTRL_SHIFT 16
880#define DPIO_CHV_INT_COEFF_SHIFT 8
881#define DPIO_CHV_PROP_COEFF_SHIFT 0
882#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
883
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +0300884#define _CHV_CMN_DW5_CH0 0x8114
885#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
886#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
887#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
888#define CHV_BUFRIGHTENA1_MASK (3 << 20)
889#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
890#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
891#define CHV_BUFLEFTENA1_FORCE (3 << 22)
892#define CHV_BUFLEFTENA1_MASK (3 << 22)
893
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300894#define _CHV_CMN_DW13_CH0 0x8134
895#define _CHV_CMN_DW0_CH1 0x8080
896#define DPIO_CHV_S1_DIV_SHIFT 21
897#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
898#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
899#define DPIO_CHV_K_DIV_SHIFT 4
900#define DPIO_PLL_FREQLOCK (1 << 1)
901#define DPIO_PLL_LOCK (1 << 0)
902#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
903
904#define _CHV_CMN_DW14_CH0 0x8138
905#define _CHV_CMN_DW1_CH1 0x8084
906#define DPIO_AFC_RECAL (1 << 14)
907#define DPIO_DCLKP_EN (1 << 13)
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +0300908#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
909#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
910#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
911#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
912#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
913#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
914#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
915#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300916#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
917
Ville Syrjälä9197c882014-04-09 13:29:05 +0300918#define _CHV_CMN_DW19_CH0 0x814c
919#define _CHV_CMN_DW6_CH1 0x8098
920#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
921#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
922
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300923#define CHV_CMN_DW30 0x8178
924#define DPIO_LRC_BYPASS (1 << 3)
925
926#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
927 (lane) * 0x200 + (offset))
928
Ville Syrjäläf72df8d2014-04-09 13:29:03 +0300929#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
930#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
931#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
932#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
933#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
934#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
935#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
936#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
937#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
938#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
939#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300940#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
941#define DPIO_FRC_LATENCY_SHFIT 8
942#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
943#define DPIO_UPAR_SHIFT 30
Jesse Barnes585fb112008-07-29 11:54:06 -0700944/*
Jesse Barnesde151cf2008-11-12 10:03:55 -0800945 * Fence registers
946 */
947#define FENCE_REG_830_0 0x2000
Eric Anholtdc529a42009-03-10 22:34:49 -0700948#define FENCE_REG_945_8 0x3000
Jesse Barnesde151cf2008-11-12 10:03:55 -0800949#define I830_FENCE_START_MASK 0x07f80000
950#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -0800951#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800952#define I830_FENCE_PITCH_SHIFT 4
953#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +0200954#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -0700955#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +0200956#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800957
958#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -0800959#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800960
961#define FENCE_REG_965_0 0x03000
962#define I965_FENCE_PITCH_SHIFT 2
963#define I965_FENCE_TILING_Y_SHIFT 1
964#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +0200965#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -0800966
Eric Anholt4e901fd2009-10-26 16:44:17 -0700967#define FENCE_REG_SANDYBRIDGE_0 0x100000
968#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +0300969#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -0700970
Deepak S2b6b3a02014-05-27 15:59:30 +0530971
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100972/* control register for cpu gtt access */
973#define TILECTL 0x101000
974#define TILECTL_SWZCTL (1 << 0)
975#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
976#define TILECTL_BACKSNOOP_DIS (1 << 3)
977
Jesse Barnesde151cf2008-11-12 10:03:55 -0800978/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700979 * Instruction and interrupt control regs
980 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700981#define PGTBL_ER 0x02024
Daniel Vetter333e9fe2010-08-02 16:24:01 +0200982#define RENDER_RING_BASE 0x02000
983#define BSD_RING_BASE 0x04000
984#define GEN6_BSD_RING_BASE 0x12000
Zhao Yakui845f74a2014-04-17 10:37:37 +0800985#define GEN8_BSD2_RING_BASE 0x1c000
Ben Widawsky1950de12013-05-28 19:22:20 -0700986#define VEBOX_RING_BASE 0x1a000
Chris Wilson549f7362010-10-19 11:19:32 +0100987#define BLT_RING_BASE 0x22000
Daniel Vetter3d281d82010-09-24 21:14:22 +0200988#define RING_TAIL(base) ((base)+0x30)
989#define RING_HEAD(base) ((base)+0x34)
990#define RING_START(base) ((base)+0x38)
991#define RING_CTL(base) ((base)+0x3c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000992#define RING_SYNC_0(base) ((base)+0x40)
993#define RING_SYNC_1(base) ((base)+0x44)
Ben Widawsky1950de12013-05-28 19:22:20 -0700994#define RING_SYNC_2(base) ((base)+0x48)
995#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
996#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
997#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
998#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
999#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1000#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1001#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1002#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1003#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1004#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1005#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1006#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ben Widawskyad776f82013-05-28 19:22:18 -07001007#define GEN6_NOSYNC 0
Chris Wilson8fd26852010-12-08 18:40:43 +00001008#define RING_MAX_IDLE(base) ((base)+0x54)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001009#define RING_HWS_PGA(base) ((base)+0x80)
1010#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
Imre Deak9e72b462014-05-05 15:13:55 +03001011
1012#define GEN7_WR_WATERMARK 0x4028
1013#define GEN7_GFX_PRIO_CTRL 0x402C
1014#define ARB_MODE 0x4030
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001015#define ARB_MODE_SWIZZLE_SNB (1<<4)
1016#define ARB_MODE_SWIZZLE_IVB (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03001017#define GEN7_GFX_PEND_TLB0 0x4034
1018#define GEN7_GFX_PEND_TLB1 0x4038
1019/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1020#define GEN7_LRA_LIMITS_BASE 0x403C
1021#define GEN7_LRA_LIMITS_REG_NUM 13
1022#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1023#define GEN7_GFX_MAX_REQ_COUNT 0x4074
1024
Ben Widawsky31a53362013-11-02 21:07:04 -07001025#define GAMTARBMODE 0x04a08
Ben Widawsky4afe8d32013-11-02 21:07:55 -07001026#define ARB_MODE_BWGTLB_DISABLE (1<<9)
Ben Widawsky31a53362013-11-02 21:07:04 -07001027#define ARB_MODE_SWIZZLE_BDW (1<<1)
Eric Anholt45930102011-05-06 17:12:35 -07001028#define RENDER_HWS_PGA_GEN7 (0x04080)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001029#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
Ben Widawsky828c7902013-10-16 09:21:30 -07001030#define RING_FAULT_GTTSEL_MASK (1<<11)
1031#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
1032#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
1033#define RING_FAULT_VALID (1<<0)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001034#define DONE_REG 0x40b0
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001035#define GEN8_PRIVATE_PAT 0x40e0
Eric Anholt45930102011-05-06 17:12:35 -07001036#define BSD_HWS_PGA_GEN7 (0x04180)
1037#define BLT_HWS_PGA_GEN7 (0x04280)
Ben Widawsky9a8a2212013-05-28 19:22:23 -07001038#define VEBOX_HWS_PGA_GEN7 (0x04380)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001039#define RING_ACTHD(base) ((base)+0x74)
Chris Wilson50877442014-03-21 12:41:53 +00001040#define RING_ACTHD_UDW(base) ((base)+0x5c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001041#define RING_NOPID(base) ((base)+0x94)
Chris Wilson0f468322011-01-04 17:35:21 +00001042#define RING_IMR(base) ((base)+0xa8)
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001043#define RING_TIMESTAMP(base) ((base)+0x358)
Jesse Barnes585fb112008-07-29 11:54:06 -07001044#define TAIL_ADDR 0x001FFFF8
1045#define HEAD_WRAP_COUNT 0xFFE00000
1046#define HEAD_WRAP_ONE 0x00200000
1047#define HEAD_ADDR 0x001FFFFC
1048#define RING_NR_PAGES 0x001FF000
1049#define RING_REPORT_MASK 0x00000006
1050#define RING_REPORT_64K 0x00000002
1051#define RING_REPORT_128K 0x00000004
1052#define RING_NO_REPORT 0x00000000
1053#define RING_VALID_MASK 0x00000001
1054#define RING_VALID 0x00000001
1055#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +01001056#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1057#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001058#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Imre Deak9e72b462014-05-05 15:13:55 +03001059
1060#define GEN7_TLB_RD_ADDR 0x4700
1061
Chris Wilson8168bd42010-11-11 17:54:52 +00001062#if 0
1063#define PRB0_TAIL 0x02030
1064#define PRB0_HEAD 0x02034
1065#define PRB0_START 0x02038
1066#define PRB0_CTL 0x0203c
Jesse Barnes585fb112008-07-29 11:54:06 -07001067#define PRB1_TAIL 0x02040 /* 915+ only */
1068#define PRB1_HEAD 0x02044 /* 915+ only */
1069#define PRB1_START 0x02048 /* 915+ only */
1070#define PRB1_CTL 0x0204c /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +00001071#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001072#define IPEIR_I965 0x02064
1073#define IPEHR_I965 0x02068
1074#define INSTDONE_I965 0x0206c
Ben Widawskyd53bd482012-08-22 11:32:14 -07001075#define GEN7_INSTDONE_1 0x0206c
1076#define GEN7_SC_INSTDONE 0x07100
1077#define GEN7_SAMPLER_INSTDONE 0x0e160
1078#define GEN7_ROW_INSTDONE 0x0e164
1079#define I915_NUM_INSTDONE_REG 4
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001080#define RING_IPEIR(base) ((base)+0x64)
1081#define RING_IPEHR(base) ((base)+0x68)
1082#define RING_INSTDONE(base) ((base)+0x6c)
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001083#define RING_INSTPS(base) ((base)+0x70)
1084#define RING_DMA_FADD(base) ((base)+0x78)
Ben Widawsky13ffadd2014-04-01 16:31:07 -07001085#define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001086#define RING_INSTPM(base) ((base)+0xc0)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301087#define RING_MI_MODE(base) ((base)+0x9c)
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001088#define INSTPS 0x02070 /* 965+ only */
1089#define INSTDONE1 0x0207c /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001090#define ACTHD_I965 0x02074
1091#define HWS_PGA 0x02080
1092#define HWS_ADDRESS_MASK 0xfffff000
1093#define HWS_START_ADDRESS_SHIFT 4
Jesse Barnes97f5ab62009-10-08 10:16:48 -07001094#define PWRCTXA 0x2088 /* 965GM+ only */
1095#define PWRCTX_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001096#define IPEIR 0x02088
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001097#define IPEHR 0x0208c
1098#define INSTDONE 0x02090
Jesse Barnes585fb112008-07-29 11:54:06 -07001099#define NOPID 0x02094
1100#define HWSTAM 0x02098
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001101#define DMA_FADD_I8XX 0x020d0
Chris Wilson94e39e22013-10-30 09:28:22 +00001102#define RING_BBSTATE(base) ((base)+0x110)
Ville Syrjälä3dda20a2013-12-10 21:44:43 +02001103#define RING_BBADDR(base) ((base)+0x140)
1104#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
Eric Anholt71cf39b2010-03-08 23:41:55 -08001105
Chris Wilsonf4068392010-10-27 20:36:41 +01001106#define ERROR_GEN6 0x040a0
Ben Widawsky71e172e2012-08-20 16:15:13 -07001107#define GEN7_ERR_INT 0x44040
Paulo Zanonide032bf2013-04-12 17:57:58 -03001108#define ERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03001109#define ERR_INT_MMIO_UNCLAIMED (1<<13)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001110#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
Paulo Zanoni86642812013-04-12 17:57:57 -03001111#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001112#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
Paulo Zanoni86642812013-04-12 17:57:57 -03001113#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001114#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001115#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03001116#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
Daniel Vetter7336df62013-07-09 22:59:16 +02001117#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Chris Wilsonf4068392010-10-27 20:36:41 +01001118
Paulo Zanoni3f1e1092013-02-18 19:00:21 -03001119#define FPGA_DBG 0x42300
1120#define FPGA_DBG_RM_NOCLAIM (1<<31)
1121
Chris Wilson0f3b6842013-01-15 12:05:55 +00001122#define DERRMR 0x44050
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07001123/* Note that HBLANK events are reserved on bdw+ */
Chris Wilsonffe74d72013-08-26 20:58:12 +01001124#define DERRMR_PIPEA_SCANLINE (1<<0)
1125#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1126#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1127#define DERRMR_PIPEA_VBLANK (1<<3)
1128#define DERRMR_PIPEA_HBLANK (1<<5)
1129#define DERRMR_PIPEB_SCANLINE (1<<8)
1130#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1131#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1132#define DERRMR_PIPEB_VBLANK (1<<11)
1133#define DERRMR_PIPEB_HBLANK (1<<13)
1134/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1135#define DERRMR_PIPEC_SCANLINE (1<<14)
1136#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1137#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1138#define DERRMR_PIPEC_VBLANK (1<<21)
1139#define DERRMR_PIPEC_HBLANK (1<<22)
1140
Chris Wilson0f3b6842013-01-15 12:05:55 +00001141
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001142/* GM45+ chicken bits -- debug workaround bits that may be required
1143 * for various sorts of correct behavior. The top 16 bits of each are
1144 * the enables for writing to the corresponding low bit.
1145 */
1146#define _3D_CHICKEN 0x02084
Daniel Vetter42839082012-12-14 23:38:28 +01001147#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001148#define _3D_CHICKEN2 0x0208c
1149/* Disables pipelining of read flushes past the SF-WIZ interface.
1150 * Required on all Ironlake steppings according to the B-Spec, but the
1151 * particular danger of not doing so is not specified.
1152 */
1153# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1154#define _3D_CHICKEN3 0x02090
Jesse Barnes87f80202012-10-02 17:43:41 -05001155#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Kenneth Graunke26b6e442012-10-07 08:51:07 -07001156#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02001157#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1158#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001159
Eric Anholt71cf39b2010-03-08 23:41:55 -08001160#define MI_MODE 0x0209c
1161# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -08001162# define MI_FLUSH_ENABLE (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +00001163# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301164# define MODE_IDLE (1 << 9)
Chris Wilson9991ae72014-04-02 16:36:07 +01001165# define STOP_RING (1 << 8)
Eric Anholt71cf39b2010-03-08 23:41:55 -08001166
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001167#define GEN6_GT_MODE 0x20d0
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02001168#define GEN7_GT_MODE 0x7008
Ville Syrjälä8d85d272014-02-04 21:59:15 +02001169#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1170#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1171#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1172#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1173#define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01001174#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001175
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001176#define GFX_MODE 0x02520
Jesse Barnesb095cd02011-08-12 15:28:32 -07001177#define GFX_MODE_GEN7 0x0229c
Daniel Vetter5eb719c2012-02-09 17:15:48 +01001178#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001179#define GFX_RUN_LIST_ENABLE (1<<15)
Chris Wilsonaa83e302014-03-21 17:18:54 +00001180#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001181#define GFX_SURFACE_FAULT_ENABLE (1<<12)
1182#define GFX_REPLAY_MODE (1<<11)
1183#define GFX_PSMI_GRANULARITY (1<<10)
1184#define GFX_PPGTT_ENABLE (1<<9)
1185
Daniel Vettera7e806d2012-07-11 16:27:55 +02001186#define VLV_DISPLAY_BASE 0x180000
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301187#define VLV_MIPI_BASE VLV_DISPLAY_BASE
Daniel Vettera7e806d2012-07-11 16:27:55 +02001188
Imre Deak9e72b462014-05-05 15:13:55 +03001189#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1190#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
Jesse Barnes585fb112008-07-29 11:54:06 -07001191#define SCPD0 0x0209c /* 915+ only */
1192#define IER 0x020a0
1193#define IIR 0x020a4
1194#define IMR 0x020a8
1195#define ISR 0x020ac
Ville Syrjälä07ec7ec2013-01-24 15:29:51 +02001196#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001197#define GINT_DIS (1<<22)
Jesse Barnes2d809572012-10-25 12:15:44 -07001198#define GCFG_DIS (1<<8)
Imre Deak9e72b462014-05-05 15:13:55 +03001199#define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
Ville Syrjäläff763012013-01-24 15:29:52 +02001200#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1201#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1202#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1203#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1204#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001205#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
Deepak S38807742014-05-23 21:00:15 +05301206#define VLV_PCBR_ADDR_SHIFT 12
1207
Ville Syrjälä90a72f82013-02-19 23:16:44 +02001208#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001209#define EIR 0x020b0
1210#define EMR 0x020b4
1211#define ESR 0x020b8
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001212#define GM45_ERROR_PAGE_TABLE (1<<5)
1213#define GM45_ERROR_MEM_PRIV (1<<4)
1214#define I915_ERROR_PAGE_TABLE (1<<4)
1215#define GM45_ERROR_CP_PRIV (1<<3)
1216#define I915_ERROR_MEMORY_REFRESH (1<<1)
1217#define I915_ERROR_INSTRUCTION (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001218#define INSTPM 0x020c0
Li Pengee980b82010-01-27 19:01:11 +08001219#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Ville Syrjälä32992542014-02-25 15:13:39 +02001220#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
Chris Wilson8692d00e2011-02-05 10:08:21 +00001221 will not assert AGPBUSY# and will only
1222 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -08001223#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Chris Wilson884020b2013-08-06 19:01:14 +01001224#define INSTPM_TLB_INVALIDATE (1<<9)
1225#define INSTPM_SYNC_FLUSH (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001226#define ACTHD 0x020c8
1227#define FW_BLC 0x020d8
Chris Wilson8692d00e2011-02-05 10:08:21 +00001228#define FW_BLC2 0x020dc
Jesse Barnes585fb112008-07-29 11:54:06 -07001229#define FW_BLC_SELF 0x020e0 /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +08001230#define FW_BLC_SELF_EN_MASK (1<<31)
1231#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1232#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001233#define MM_BURST_LENGTH 0x00700000
1234#define MM_FIFO_WATERMARK 0x0001F000
1235#define LM_BURST_LENGTH 0x00000700
1236#define LM_FIFO_WATERMARK 0x0000001F
Jesse Barnes585fb112008-07-29 11:54:06 -07001237#define MI_ARB_STATE 0x020e4 /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -07001238
1239/* Make render/texture TLB fetches lower priorty than associated data
1240 * fetches. This is not turned on by default
1241 */
1242#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1243
1244/* Isoch request wait on GTT enable (Display A/B/C streams).
1245 * Make isoch requests stall on the TLB update. May cause
1246 * display underruns (test mode only)
1247 */
1248#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1249
1250/* Block grant count for isoch requests when block count is
1251 * set to a finite value.
1252 */
1253#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1254#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1255#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1256#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1257#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1258
1259/* Enable render writes to complete in C2/C3/C4 power states.
1260 * If this isn't enabled, render writes are prevented in low
1261 * power states. That seems bad to me.
1262 */
1263#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1264
1265/* This acknowledges an async flip immediately instead
1266 * of waiting for 2TLB fetches.
1267 */
1268#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1269
1270/* Enables non-sequential data reads through arbiter
1271 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001272#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -07001273
1274/* Disable FSB snooping of cacheable write cycles from binner/render
1275 * command stream
1276 */
1277#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1278
1279/* Arbiter time slice for non-isoch streams */
1280#define MI_ARB_TIME_SLICE_MASK (7 << 5)
1281#define MI_ARB_TIME_SLICE_1 (0 << 5)
1282#define MI_ARB_TIME_SLICE_2 (1 << 5)
1283#define MI_ARB_TIME_SLICE_4 (2 << 5)
1284#define MI_ARB_TIME_SLICE_6 (3 << 5)
1285#define MI_ARB_TIME_SLICE_8 (4 << 5)
1286#define MI_ARB_TIME_SLICE_10 (5 << 5)
1287#define MI_ARB_TIME_SLICE_14 (6 << 5)
1288#define MI_ARB_TIME_SLICE_16 (7 << 5)
1289
1290/* Low priority grace period page size */
1291#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1292#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1293
1294/* Disable display A/B trickle feed */
1295#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1296
1297/* Set display plane priority */
1298#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1299#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1300
Ville Syrjälä54e472a2014-02-25 15:13:40 +02001301#define MI_STATE 0x020e4 /* gen2 only */
1302#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1303#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1304
Jesse Barnes585fb112008-07-29 11:54:06 -07001305#define CACHE_MODE_0 0x02120 /* 915+ only */
Daniel Vetter4358a372012-10-18 11:49:51 +02001306#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001307#define CM0_IZ_OPT_DISABLE (1<<6)
1308#define CM0_ZR_OPT_DISABLE (1<<5)
Daniel Vetter009be662012-04-11 20:42:42 +02001309#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001310#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1311#define CM0_COLOR_EVICT_DISABLE (1<<3)
1312#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1313#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1314#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001315#define GFX_FLSH_CNTL_GEN6 0x101008
1316#define GFX_FLSH_CNTL_EN (1<<0)
Jesse Barnes1afe3e92010-03-26 10:35:20 -07001317#define ECOSKPD 0x021d0
1318#define ECO_GATING_CX_ONLY (1<<3)
1319#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001320
Chia-I Wufe27c602014-01-28 13:29:33 +08001321#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
Akash Goel4e046322014-04-04 17:14:38 +05301322#define RC_OP_FLUSH_ENABLE (1<<0)
Chia-I Wufe27c602014-01-28 13:29:33 +08001323#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
Jesse Barnesfb046852012-03-28 13:39:26 -07001324#define CACHE_MODE_1 0x7004 /* IVB+ */
Damien Lespiau5d708682014-03-26 18:41:51 +00001325#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1326#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
Jesse Barnesfb046852012-03-28 13:39:26 -07001327
Jesse Barnes4efe0702011-01-18 11:25:41 -08001328#define GEN6_BLITTER_ECOSKPD 0x221d0
1329#define GEN6_BLITTER_LOCK_SHIFT 16
1330#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1331
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001332#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
1333#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001334#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001335
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001336#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
Chris Wilson12f55812012-07-05 17:14:01 +01001337#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1338#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1339#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1340#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001341
Ben Widawskycc609d52013-05-28 19:22:29 -07001342/* On modern GEN architectures interrupt control consists of two sets
1343 * of registers. The first set pertains to the ring generating the
1344 * interrupt. The second control is for the functional block generating the
1345 * interrupt. These are PM, GT, DE, etc.
1346 *
1347 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1348 * GT interrupt bits, so we don't need to duplicate the defines.
1349 *
1350 * These defines should cover us well from SNB->HSW with minor exceptions
1351 * it can also work on ILK.
1352 */
1353#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1354#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1355#define GT_BLT_USER_INTERRUPT (1 << 22)
1356#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1357#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001358#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Ben Widawskycc609d52013-05-28 19:22:29 -07001359#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1360#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1361#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1362#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1363#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1364#define GT_RENDER_USER_INTERRUPT (1 << 0)
1365
Ben Widawsky12638c52013-05-28 19:22:31 -07001366#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1367#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1368
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001369#define GT_PARITY_ERROR(dev) \
1370 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Dan Carpenter45f80d52013-09-24 10:57:35 +03001371 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001372
Ben Widawskycc609d52013-05-28 19:22:29 -07001373/* These are all the "old" interrupts */
1374#define ILK_BSD_USER_INTERRUPT (1<<5)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001375
1376#define I915_PM_INTERRUPT (1<<31)
1377#define I915_ISP_INTERRUPT (1<<22)
1378#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1379#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
1380#define I915_MIPIB_INTERRUPT (1<<19)
1381#define I915_MIPIA_INTERRUPT (1<<18)
Ben Widawskycc609d52013-05-28 19:22:29 -07001382#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1383#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001384#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1385#define I915_MASTER_ERROR_INTERRUPT (1<<15)
Ben Widawskycc609d52013-05-28 19:22:29 -07001386#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001387#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
Ben Widawskycc609d52013-05-28 19:22:29 -07001388#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001389#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
Ben Widawskycc609d52013-05-28 19:22:29 -07001390#define I915_HWB_OOM_INTERRUPT (1<<13)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001391#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
Ben Widawskycc609d52013-05-28 19:22:29 -07001392#define I915_SYNC_STATUS_INTERRUPT (1<<12)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001393#define I915_MISC_INTERRUPT (1<<11)
Ben Widawskycc609d52013-05-28 19:22:29 -07001394#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001395#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
Ben Widawskycc609d52013-05-28 19:22:29 -07001396#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001397#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
Ben Widawskycc609d52013-05-28 19:22:29 -07001398#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001399#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
Ben Widawskycc609d52013-05-28 19:22:29 -07001400#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1401#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1402#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1403#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1404#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001405#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1406#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
Ben Widawskycc609d52013-05-28 19:22:29 -07001407#define I915_DEBUG_INTERRUPT (1<<2)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001408#define I915_WINVALID_INTERRUPT (1<<1)
Ben Widawskycc609d52013-05-28 19:22:29 -07001409#define I915_USER_INTERRUPT (1<<1)
1410#define I915_ASLE_INTERRUPT (1<<0)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001411#define I915_BSD_USER_INTERRUPT (1<<25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001412
1413#define GEN6_BSD_RNCID 0x12198
1414
Ben Widawskya1e969e2012-04-14 18:41:32 -07001415#define GEN7_FF_THREAD_MODE 0x20a0
1416#define GEN7_FF_SCHED_MASK 0x0077070
Ben Widawskyab57fff2013-12-12 15:28:04 -08001417#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001418#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1419#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1420#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1421#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08001422#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001423#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1424#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1425#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1426#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1427#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1428#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1429#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1430#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1431
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001432/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001433 * Framebuffer compression (915+ only)
1434 */
1435
1436#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1437#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1438#define FBC_CONTROL 0x03208
1439#define FBC_CTL_EN (1<<31)
1440#define FBC_CTL_PERIODIC (1<<30)
1441#define FBC_CTL_INTERVAL_SHIFT (16)
1442#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +02001443#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -07001444#define FBC_CTL_STRIDE_SHIFT (5)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001445#define FBC_CTL_FENCENO_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001446#define FBC_COMMAND 0x0320c
1447#define FBC_CMD_COMPRESS (1<<0)
1448#define FBC_STATUS 0x03210
1449#define FBC_STAT_COMPRESSING (1<<31)
1450#define FBC_STAT_COMPRESSED (1<<30)
1451#define FBC_STAT_MODIFIED (1<<29)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001452#define FBC_STAT_CURRENT_LINE_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001453#define FBC_CONTROL2 0x03214
1454#define FBC_CTL_FENCE_DBL (0<<4)
1455#define FBC_CTL_IDLE_IMM (0<<2)
1456#define FBC_CTL_IDLE_FULL (1<<2)
1457#define FBC_CTL_IDLE_LINE (2<<2)
1458#define FBC_CTL_IDLE_DEBUG (3<<2)
1459#define FBC_CTL_CPU_FENCE (1<<1)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001460#define FBC_CTL_PLANE(plane) ((plane)<<0)
Ville Syrjäläf64f1722014-01-23 16:49:17 +02001461#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
Jesse Barnes80824002009-09-10 15:28:06 -07001462#define FBC_TAG 0x03300
Jesse Barnes585fb112008-07-29 11:54:06 -07001463
1464#define FBC_LL_SIZE (1536)
1465
Jesse Barnes74dff282009-09-14 15:39:40 -07001466/* Framebuffer compression for GM45+ */
1467#define DPFC_CB_BASE 0x3200
1468#define DPFC_CONTROL 0x3208
1469#define DPFC_CTL_EN (1<<31)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001470#define DPFC_CTL_PLANE(plane) ((plane)<<30)
1471#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
Jesse Barnes74dff282009-09-14 15:39:40 -07001472#define DPFC_CTL_FENCE_EN (1<<29)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001473#define IVB_DPFC_CTL_FENCE_EN (1<<28)
Chris Wilson9ce9d062011-07-08 12:22:40 +01001474#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -07001475#define DPFC_SR_EN (1<<10)
1476#define DPFC_CTL_LIMIT_1X (0<<6)
1477#define DPFC_CTL_LIMIT_2X (1<<6)
1478#define DPFC_CTL_LIMIT_4X (2<<6)
1479#define DPFC_RECOMP_CTL 0x320c
1480#define DPFC_RECOMP_STALL_EN (1<<27)
1481#define DPFC_RECOMP_STALL_WM_SHIFT (16)
1482#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1483#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1484#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1485#define DPFC_STATUS 0x3210
1486#define DPFC_INVAL_SEG_SHIFT (16)
1487#define DPFC_INVAL_SEG_MASK (0x07ff0000)
1488#define DPFC_COMP_SEG_SHIFT (0)
1489#define DPFC_COMP_SEG_MASK (0x000003ff)
1490#define DPFC_STATUS2 0x3214
1491#define DPFC_FENCE_YOFF 0x3218
1492#define DPFC_CHICKEN 0x3224
1493#define DPFC_HT_MODIFY (1<<31)
1494
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001495/* Framebuffer compression for Ironlake */
1496#define ILK_DPFC_CB_BASE 0x43200
1497#define ILK_DPFC_CONTROL 0x43208
1498/* The bit 28-8 is reserved */
1499#define DPFC_RESERVED (0x1FFFFF00)
1500#define ILK_DPFC_RECOMP_CTL 0x4320c
1501#define ILK_DPFC_STATUS 0x43210
1502#define ILK_DPFC_FENCE_YOFF 0x43218
1503#define ILK_DPFC_CHICKEN 0x43224
1504#define ILK_FBC_RT_BASE 0x2128
1505#define ILK_FBC_RT_VALID (1<<0)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001506#define SNB_FBC_FRONT_BUFFER (1<<1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001507
1508#define ILK_DISPLAY_CHICKEN1 0x42000
1509#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -04001510#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +08001511
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001512
Jesse Barnes585fb112008-07-29 11:54:06 -07001513/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001514 * Framebuffer compression for Sandybridge
1515 *
1516 * The following two registers are of type GTTMMADR
1517 */
1518#define SNB_DPFC_CTL_SA 0x100100
1519#define SNB_CPU_FENCE_ENABLE (1<<29)
1520#define DPFC_CPU_FENCE_OFFSET 0x100104
1521
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001522/* Framebuffer compression for Ivybridge */
1523#define IVB_FBC_RT_BASE 0x7020
1524
Paulo Zanoni42db64e2013-05-31 16:33:22 -03001525#define IPS_CTL 0x43408
1526#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001527
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03001528#define MSG_FBC_REND_STATE 0x50380
1529#define FBC_REND_NUKE (1<<2)
1530#define FBC_REND_CACHE_CLEAN (1<<1)
1531
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001532/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001533 * GPIO regs
1534 */
1535#define GPIOA 0x5010
1536#define GPIOB 0x5014
1537#define GPIOC 0x5018
1538#define GPIOD 0x501c
1539#define GPIOE 0x5020
1540#define GPIOF 0x5024
1541#define GPIOG 0x5028
1542#define GPIOH 0x502c
1543# define GPIO_CLOCK_DIR_MASK (1 << 0)
1544# define GPIO_CLOCK_DIR_IN (0 << 1)
1545# define GPIO_CLOCK_DIR_OUT (1 << 1)
1546# define GPIO_CLOCK_VAL_MASK (1 << 2)
1547# define GPIO_CLOCK_VAL_OUT (1 << 3)
1548# define GPIO_CLOCK_VAL_IN (1 << 4)
1549# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1550# define GPIO_DATA_DIR_MASK (1 << 8)
1551# define GPIO_DATA_DIR_IN (0 << 9)
1552# define GPIO_DATA_DIR_OUT (1 << 9)
1553# define GPIO_DATA_VAL_MASK (1 << 10)
1554# define GPIO_DATA_VAL_OUT (1 << 11)
1555# define GPIO_DATA_VAL_IN (1 << 12)
1556# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1557
Chris Wilsonf899fc62010-07-20 15:44:45 -07001558#define GMBUS0 0x5100 /* clock/port select */
1559#define GMBUS_RATE_100KHZ (0<<8)
1560#define GMBUS_RATE_50KHZ (1<<8)
1561#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1562#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1563#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1564#define GMBUS_PORT_DISABLED 0
1565#define GMBUS_PORT_SSC 1
1566#define GMBUS_PORT_VGADDC 2
1567#define GMBUS_PORT_PANEL 3
Ville Syrjäläc0c35322014-04-09 13:28:52 +03001568#define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */
Chris Wilsonf899fc62010-07-20 15:44:45 -07001569#define GMBUS_PORT_DPC 4 /* HDMIC */
1570#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
Daniel Kurtze4fd17a2012-03-28 02:36:12 +08001571#define GMBUS_PORT_DPD 6 /* HDMID */
1572#define GMBUS_PORT_RESERVED 7 /* 7 reserved */
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08001573#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
Chris Wilsonf899fc62010-07-20 15:44:45 -07001574#define GMBUS1 0x5104 /* command/status */
1575#define GMBUS_SW_CLR_INT (1<<31)
1576#define GMBUS_SW_RDY (1<<30)
1577#define GMBUS_ENT (1<<29) /* enable timeout */
1578#define GMBUS_CYCLE_NONE (0<<25)
1579#define GMBUS_CYCLE_WAIT (1<<25)
1580#define GMBUS_CYCLE_INDEX (2<<25)
1581#define GMBUS_CYCLE_STOP (4<<25)
1582#define GMBUS_BYTE_COUNT_SHIFT 16
1583#define GMBUS_SLAVE_INDEX_SHIFT 8
1584#define GMBUS_SLAVE_ADDR_SHIFT 1
1585#define GMBUS_SLAVE_READ (1<<0)
1586#define GMBUS_SLAVE_WRITE (0<<0)
1587#define GMBUS2 0x5108 /* status */
1588#define GMBUS_INUSE (1<<15)
1589#define GMBUS_HW_WAIT_PHASE (1<<14)
1590#define GMBUS_STALL_TIMEOUT (1<<13)
1591#define GMBUS_INT (1<<12)
1592#define GMBUS_HW_RDY (1<<11)
1593#define GMBUS_SATOER (1<<10)
1594#define GMBUS_ACTIVE (1<<9)
1595#define GMBUS3 0x510c /* data buffer bytes 3-0 */
1596#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1597#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1598#define GMBUS_NAK_EN (1<<3)
1599#define GMBUS_IDLE_EN (1<<2)
1600#define GMBUS_HW_WAIT_EN (1<<1)
1601#define GMBUS_HW_RDY_EN (1<<0)
1602#define GMBUS5 0x5120 /* byte index */
1603#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -08001604
Jesse Barnes585fb112008-07-29 11:54:06 -07001605/*
1606 * Clock control & power management
1607 */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001608#define DPLL_A_OFFSET 0x6014
1609#define DPLL_B_OFFSET 0x6018
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03001610#define CHV_DPLL_C_OFFSET 0x6030
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001611#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
1612 dev_priv->info.display_mmio_offset)
Jesse Barnes585fb112008-07-29 11:54:06 -07001613
1614#define VGA0 0x6000
1615#define VGA1 0x6004
1616#define VGA_PD 0x6010
1617#define VGA0_PD_P2_DIV_4 (1 << 7)
1618#define VGA0_PD_P1_DIV_2 (1 << 5)
1619#define VGA0_PD_P1_SHIFT 0
1620#define VGA0_PD_P1_MASK (0x1f << 0)
1621#define VGA1_PD_P2_DIV_4 (1 << 15)
1622#define VGA1_PD_P1_DIV_2 (1 << 13)
1623#define VGA1_PD_P1_SHIFT 8
1624#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001625#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02001626#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1627#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001628#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07001629#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001630#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07001631#define DPLL_VGA_MODE_DIS (1 << 28)
1632#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1633#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1634#define DPLL_MODE_MASK (3 << 26)
1635#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1636#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1637#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1638#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1639#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1640#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001641#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07001642#define DPLL_LOCK_VLV (1<<15)
Daniel Vetter598fac62013-04-18 22:01:46 +02001643#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001644#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001645#define DPLL_SSC_REF_CLOCK_CHV (1<<13)
Daniel Vetter598fac62013-04-18 22:01:46 +02001646#define DPLL_PORTC_READY_MASK (0xf << 4)
1647#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07001648
Jesse Barnes585fb112008-07-29 11:54:06 -07001649#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001650
1651/* Additional CHV pll/phy registers */
1652#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
1653#define DPLL_PORTD_READY_MASK (0xf)
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001654#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
1655#define PHY_COM_LANE_RESET_DEASSERT(phy, val) \
1656 ((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
1657#define PHY_COM_LANE_RESET_ASSERT(phy, val) \
1658 ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
1659#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
1660#define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
1661
Jesse Barnes585fb112008-07-29 11:54:06 -07001662/*
1663 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1664 * this field (only one bit may be set).
1665 */
1666#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1667#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001668#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07001669/* i830, required in DVO non-gang */
1670#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1671#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1672#define PLL_REF_INPUT_DREFCLK (0 << 13)
1673#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1674#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1675#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1676#define PLL_REF_INPUT_MASK (3 << 13)
1677#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001678/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08001679# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1680# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1681# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1682# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1683# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1684
Jesse Barnes585fb112008-07-29 11:54:06 -07001685/*
1686 * Parallel to Serial Load Pulse phase selection.
1687 * Selects the phase for the 10X DPLL clock for the PCIe
1688 * digital display port. The range is 4 to 13; 10 or more
1689 * is just a flip delay. The default is 6
1690 */
1691#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1692#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1693/*
1694 * SDVO multiplier for 945G/GM. Not used on 965.
1695 */
1696#define SDVO_MULTIPLIER_MASK 0x000000ff
1697#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1698#define SDVO_MULTIPLIER_SHIFT_VGA 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001699
1700#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
1701#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03001702#define CHV_DPLL_C_MD_OFFSET 0x603c
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001703#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
1704 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001705
Jesse Barnes585fb112008-07-29 11:54:06 -07001706/*
1707 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1708 *
1709 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1710 */
1711#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1712#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1713/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1714#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1715#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1716/*
1717 * SDVO/UDI pixel multiplier.
1718 *
1719 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1720 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1721 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1722 * dummy bytes in the datastream at an increased clock rate, with both sides of
1723 * the link knowing how many bytes are fill.
1724 *
1725 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1726 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1727 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1728 * through an SDVO command.
1729 *
1730 * This register field has values of multiplication factor minus 1, with
1731 * a maximum multiplier of 5 for SDVO.
1732 */
1733#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1734#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1735/*
1736 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1737 * This best be set to the default value (3) or the CRT won't work. No,
1738 * I don't entirely understand what this does...
1739 */
1740#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1741#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001742
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001743#define _FPA0 0x06040
1744#define _FPA1 0x06044
1745#define _FPB0 0x06048
1746#define _FPB1 0x0604c
1747#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1748#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07001749#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001750#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07001751#define FP_N_DIV_SHIFT 16
1752#define FP_M1_DIV_MASK 0x00003f00
1753#define FP_M1_DIV_SHIFT 8
1754#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001755#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07001756#define FP_M2_DIV_SHIFT 0
1757#define DPLL_TEST 0x606c
1758#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1759#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1760#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1761#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1762#define DPLLB_TEST_N_BYPASS (1 << 19)
1763#define DPLLB_TEST_M_BYPASS (1 << 18)
1764#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1765#define DPLLA_TEST_N_BYPASS (1 << 3)
1766#define DPLLA_TEST_M_BYPASS (1 << 2)
1767#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1768#define D_STATE 0x6104
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001769#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -07001770#define DSTATE_PLL_D3_OFF (1<<3)
1771#define DSTATE_GFX_CLOCK_GATING (1<<1)
1772#define DSTATE_DOT_CLOCK_GATING (1<<0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001773#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07001774# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1775# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1776# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1777# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1778# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1779# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1780# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1781# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1782# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1783# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1784# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1785# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1786# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1787# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1788# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1789# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1790# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1791# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1792# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1793# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1794# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1795# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1796# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1797# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1798# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1799# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1800# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1801# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001802/*
Jesse Barnes652c3932009-08-17 13:31:43 -07001803 * This bit must be set on the 830 to prevent hangs when turning off the
1804 * overlay scaler.
1805 */
1806# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1807# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1808# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1809# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1810# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1811
1812#define RENCLK_GATE_D1 0x6204
1813# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1814# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1815# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1816# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1817# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1818# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1819# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1820# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1821# define MAG_CLOCK_GATE_DISABLE (1 << 5)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001822/* This bit must be unset on 855,865 */
Jesse Barnes652c3932009-08-17 13:31:43 -07001823# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1824# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1825# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1826# define MECO_CLOCK_GATE_DISABLE (1 << 1)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001827/* This bit must be set on 855,865. */
Jesse Barnes652c3932009-08-17 13:31:43 -07001828# define SV_CLOCK_GATE_DISABLE (1 << 0)
1829# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1830# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1831# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1832# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1833# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1834# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1835# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1836# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1837# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1838# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1839# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1840# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1841# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1842# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1843# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1844# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1845# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1846
1847# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001848/* This bit must always be set on 965G/965GM */
Jesse Barnes652c3932009-08-17 13:31:43 -07001849# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1850# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1851# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1852# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1853# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1854# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001855/* This bit must always be set on 965G */
Jesse Barnes652c3932009-08-17 13:31:43 -07001856# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1857# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1858# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1859# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1860# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1861# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1862# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1863# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1864# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1865# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1866# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1867# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1868# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1869# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1870# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1871# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1872# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1873# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1874# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1875
1876#define RENCLK_GATE_D2 0x6208
1877#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1878#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1879#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03001880
1881#define VDECCLK_GATE_D 0x620C /* g4x only */
1882#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
1883
Jesse Barnes652c3932009-08-17 13:31:43 -07001884#define RAMCLK_GATE_D 0x6210 /* CRL only */
1885#define DEUC 0x6214 /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001886
Ville Syrjäläd88b2272013-01-24 15:29:48 +02001887#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
Jesse Barnesceb04242012-03-28 13:39:22 -07001888#define FW_CSPWRDWNEN (1<<15)
1889
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03001890#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1891
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08001892#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
1893#define CDCLK_FREQ_SHIFT 4
1894#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1895#define CZCLK_FREQ_MASK 0xf
1896#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
1897
Jesse Barnes585fb112008-07-29 11:54:06 -07001898/*
1899 * Palette regs
1900 */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001901#define PALETTE_A_OFFSET 0xa000
1902#define PALETTE_B_OFFSET 0xa800
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03001903#define CHV_PALETTE_C_OFFSET 0xc000
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001904#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
1905 dev_priv->info.display_mmio_offset)
Jesse Barnes585fb112008-07-29 11:54:06 -07001906
Eric Anholt673a3942008-07-30 12:06:12 -07001907/* MCH MMIO space */
1908
1909/*
1910 * MCHBAR mirror.
1911 *
1912 * This mirrors the MCHBAR MMIO space whose location is determined by
1913 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1914 * every way. It is not accessible from the CP register read instructions.
1915 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03001916 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
1917 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07001918 */
1919#define MCHBAR_MIRROR_BASE 0x10000
1920
Yuanhan Liu13982612010-12-15 15:42:31 +08001921#define MCHBAR_MIRROR_BASE_SNB 0x140000
1922
Chris Wilson3ebecd02013-04-12 19:10:13 +01001923/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ben Widawsky153b4b952013-10-22 22:05:09 -07001924#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01001925
Ville Syrjälä646b4262014-04-25 20:14:30 +03001926/* 915-945 and GM965 MCH register controlling DRAM channel access */
Eric Anholt673a3942008-07-30 12:06:12 -07001927#define DCC 0x10200
1928#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1929#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1930#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1931#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1932#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08001933#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Eric Anholt673a3942008-07-30 12:06:12 -07001934
Ville Syrjälä646b4262014-04-25 20:14:30 +03001935/* Pineview MCH register contains DDR3 setting */
Li Peng95534262010-05-18 18:58:44 +08001936#define CSHRDDR3CTL 0x101a8
1937#define CSHRDDR3CTL_DDR3 (1 << 2)
1938
Ville Syrjälä646b4262014-04-25 20:14:30 +03001939/* 965 MCH register controlling DRAM channel configuration */
Eric Anholt673a3942008-07-30 12:06:12 -07001940#define C0DRB3 0x10206
1941#define C1DRB3 0x10606
1942
Ville Syrjälä646b4262014-04-25 20:14:30 +03001943/* snb MCH registers for reading the DRAM channel configuration */
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001944#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1945#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1946#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1947#define MAD_DIMM_ECC_MASK (0x3 << 24)
1948#define MAD_DIMM_ECC_OFF (0x0 << 24)
1949#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1950#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1951#define MAD_DIMM_ECC_ON (0x3 << 24)
1952#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1953#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1954#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1955#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1956#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1957#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1958#define MAD_DIMM_A_SELECT (0x1 << 16)
1959/* DIMM sizes are in multiples of 256mb. */
1960#define MAD_DIMM_B_SIZE_SHIFT 8
1961#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1962#define MAD_DIMM_A_SIZE_SHIFT 0
1963#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1964
Ville Syrjälä646b4262014-04-25 20:14:30 +03001965/* snb MCH registers for priority tuning */
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01001966#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1967#define MCH_SSKPD_WM0_MASK 0x3f
1968#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001969
Jesse Barnesec013e72013-08-20 10:29:23 +01001970#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
1971
Keith Packardb11248d2009-06-11 22:28:56 -07001972/* Clocking configuration register */
1973#define CLKCFG 0x10c00
Shaohua Li7662c8b2009-06-26 11:23:55 +08001974#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07001975#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1976#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1977#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1978#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1979#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001980/* Note, below two are guess */
Keith Packardb11248d2009-06-11 22:28:56 -07001981#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001982#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07001983#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08001984#define CLKCFG_MEM_533 (1 << 4)
1985#define CLKCFG_MEM_667 (2 << 4)
1986#define CLKCFG_MEM_800 (3 << 4)
1987#define CLKCFG_MEM_MASK (7 << 4)
1988
Jesse Barnesea056c12010-09-10 10:02:13 -07001989#define TSC1 0x11001
1990#define TSE (1<<0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07001991#define TR1 0x11006
1992#define TSFS 0x11020
1993#define TSFS_SLOPE_MASK 0x0000ff00
1994#define TSFS_SLOPE_SHIFT 8
1995#define TSFS_INTR_MASK 0x000000ff
1996
Jesse Barnesf97108d2010-01-29 11:27:07 -08001997#define CRSTANDVID 0x11100
1998#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1999#define PXVFREQ_PX_MASK 0x7f000000
2000#define PXVFREQ_PX_SHIFT 24
2001#define VIDFREQ_BASE 0x11110
2002#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2003#define VIDFREQ2 0x11114
2004#define VIDFREQ3 0x11118
2005#define VIDFREQ4 0x1111c
2006#define VIDFREQ_P0_MASK 0x1f000000
2007#define VIDFREQ_P0_SHIFT 24
2008#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2009#define VIDFREQ_P0_CSCLK_SHIFT 20
2010#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2011#define VIDFREQ_P0_CRCLK_SHIFT 16
2012#define VIDFREQ_P1_MASK 0x00001f00
2013#define VIDFREQ_P1_SHIFT 8
2014#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2015#define VIDFREQ_P1_CSCLK_SHIFT 4
2016#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2017#define INTTOEXT_BASE_ILK 0x11300
2018#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2019#define INTTOEXT_MAP3_SHIFT 24
2020#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2021#define INTTOEXT_MAP2_SHIFT 16
2022#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2023#define INTTOEXT_MAP1_SHIFT 8
2024#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2025#define INTTOEXT_MAP0_SHIFT 0
2026#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2027#define MEMSWCTL 0x11170 /* Ironlake only */
2028#define MEMCTL_CMD_MASK 0xe000
2029#define MEMCTL_CMD_SHIFT 13
2030#define MEMCTL_CMD_RCLK_OFF 0
2031#define MEMCTL_CMD_RCLK_ON 1
2032#define MEMCTL_CMD_CHFREQ 2
2033#define MEMCTL_CMD_CHVID 3
2034#define MEMCTL_CMD_VMMOFF 4
2035#define MEMCTL_CMD_VMMON 5
2036#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2037 when command complete */
2038#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2039#define MEMCTL_FREQ_SHIFT 8
2040#define MEMCTL_SFCAVM (1<<7)
2041#define MEMCTL_TGT_VID_MASK 0x007f
2042#define MEMIHYST 0x1117c
2043#define MEMINTREN 0x11180 /* 16 bits */
2044#define MEMINT_RSEXIT_EN (1<<8)
2045#define MEMINT_CX_SUPR_EN (1<<7)
2046#define MEMINT_CONT_BUSY_EN (1<<6)
2047#define MEMINT_AVG_BUSY_EN (1<<5)
2048#define MEMINT_EVAL_CHG_EN (1<<4)
2049#define MEMINT_MON_IDLE_EN (1<<3)
2050#define MEMINT_UP_EVAL_EN (1<<2)
2051#define MEMINT_DOWN_EVAL_EN (1<<1)
2052#define MEMINT_SW_CMD_EN (1<<0)
2053#define MEMINTRSTR 0x11182 /* 16 bits */
2054#define MEM_RSEXIT_MASK 0xc000
2055#define MEM_RSEXIT_SHIFT 14
2056#define MEM_CONT_BUSY_MASK 0x3000
2057#define MEM_CONT_BUSY_SHIFT 12
2058#define MEM_AVG_BUSY_MASK 0x0c00
2059#define MEM_AVG_BUSY_SHIFT 10
2060#define MEM_EVAL_CHG_MASK 0x0300
2061#define MEM_EVAL_BUSY_SHIFT 8
2062#define MEM_MON_IDLE_MASK 0x00c0
2063#define MEM_MON_IDLE_SHIFT 6
2064#define MEM_UP_EVAL_MASK 0x0030
2065#define MEM_UP_EVAL_SHIFT 4
2066#define MEM_DOWN_EVAL_MASK 0x000c
2067#define MEM_DOWN_EVAL_SHIFT 2
2068#define MEM_SW_CMD_MASK 0x0003
2069#define MEM_INT_STEER_GFX 0
2070#define MEM_INT_STEER_CMR 1
2071#define MEM_INT_STEER_SMI 2
2072#define MEM_INT_STEER_SCI 3
2073#define MEMINTRSTS 0x11184
2074#define MEMINT_RSEXIT (1<<7)
2075#define MEMINT_CONT_BUSY (1<<6)
2076#define MEMINT_AVG_BUSY (1<<5)
2077#define MEMINT_EVAL_CHG (1<<4)
2078#define MEMINT_MON_IDLE (1<<3)
2079#define MEMINT_UP_EVAL (1<<2)
2080#define MEMINT_DOWN_EVAL (1<<1)
2081#define MEMINT_SW_CMD (1<<0)
2082#define MEMMODECTL 0x11190
2083#define MEMMODE_BOOST_EN (1<<31)
2084#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2085#define MEMMODE_BOOST_FREQ_SHIFT 24
2086#define MEMMODE_IDLE_MODE_MASK 0x00030000
2087#define MEMMODE_IDLE_MODE_SHIFT 16
2088#define MEMMODE_IDLE_MODE_EVAL 0
2089#define MEMMODE_IDLE_MODE_CONT 1
2090#define MEMMODE_HWIDLE_EN (1<<15)
2091#define MEMMODE_SWMODE_EN (1<<14)
2092#define MEMMODE_RCLK_GATE (1<<13)
2093#define MEMMODE_HW_UPDATE (1<<12)
2094#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2095#define MEMMODE_FSTART_SHIFT 8
2096#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2097#define MEMMODE_FMAX_SHIFT 4
2098#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2099#define RCBMAXAVG 0x1119c
2100#define MEMSWCTL2 0x1119e /* Cantiga only */
2101#define SWMEMCMD_RENDER_OFF (0 << 13)
2102#define SWMEMCMD_RENDER_ON (1 << 13)
2103#define SWMEMCMD_SWFREQ (2 << 13)
2104#define SWMEMCMD_TARVID (3 << 13)
2105#define SWMEMCMD_VRM_OFF (4 << 13)
2106#define SWMEMCMD_VRM_ON (5 << 13)
2107#define CMDSTS (1<<12)
2108#define SFCAVM (1<<11)
2109#define SWFREQ_MASK 0x0380 /* P0-7 */
2110#define SWFREQ_SHIFT 7
2111#define TARVID_MASK 0x001f
2112#define MEMSTAT_CTG 0x111a0
2113#define RCBMINAVG 0x111a0
2114#define RCUPEI 0x111b0
2115#define RCDNEI 0x111b4
Jesse Barnes88271da2011-01-05 12:01:24 -08002116#define RSTDBYCTL 0x111b8
2117#define RS1EN (1<<31)
2118#define RS2EN (1<<30)
2119#define RS3EN (1<<29)
2120#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2121#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2122#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2123#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2124#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2125#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2126#define RSX_STATUS_MASK (7<<20)
2127#define RSX_STATUS_ON (0<<20)
2128#define RSX_STATUS_RC1 (1<<20)
2129#define RSX_STATUS_RC1E (2<<20)
2130#define RSX_STATUS_RS1 (3<<20)
2131#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2132#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2133#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2134#define RSX_STATUS_RSVD2 (7<<20)
2135#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2136#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2137#define JRSC (1<<17) /* rsx coupled to cpu c-state */
2138#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2139#define RS1CONTSAV_MASK (3<<14)
2140#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2141#define RS1CONTSAV_RSVD (1<<14)
2142#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2143#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2144#define NORMSLEXLAT_MASK (3<<12)
2145#define SLOW_RS123 (0<<12)
2146#define SLOW_RS23 (1<<12)
2147#define SLOW_RS3 (2<<12)
2148#define NORMAL_RS123 (3<<12)
2149#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2150#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2151#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2152#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2153#define RS_CSTATE_MASK (3<<4)
2154#define RS_CSTATE_C367_RS1 (0<<4)
2155#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2156#define RS_CSTATE_RSVD (2<<4)
2157#define RS_CSTATE_C367_RS2 (3<<4)
2158#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2159#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002160#define VIDCTL 0x111c0
2161#define VIDSTS 0x111c8
2162#define VIDSTART 0x111cc /* 8 bits */
2163#define MEMSTAT_ILK 0x111f8
2164#define MEMSTAT_VID_MASK 0x7f00
2165#define MEMSTAT_VID_SHIFT 8
2166#define MEMSTAT_PSTATE_MASK 0x00f8
2167#define MEMSTAT_PSTATE_SHIFT 3
2168#define MEMSTAT_MON_ACTV (1<<2)
2169#define MEMSTAT_SRC_CTL_MASK 0x0003
2170#define MEMSTAT_SRC_CTL_CORE 0
2171#define MEMSTAT_SRC_CTL_TRB 1
2172#define MEMSTAT_SRC_CTL_THM 2
2173#define MEMSTAT_SRC_CTL_STDBY 3
2174#define RCPREVBSYTUPAVG 0x113b8
2175#define RCPREVBSYTDNAVG 0x113bc
Jesse Barnesea056c12010-09-10 10:02:13 -07002176#define PMMISC 0x11214
2177#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Jesse Barnes7648fa92010-05-20 14:28:11 -07002178#define SDEW 0x1124c
2179#define CSIEW0 0x11250
2180#define CSIEW1 0x11254
2181#define CSIEW2 0x11258
2182#define PEW 0x1125c
2183#define DEW 0x11270
2184#define MCHAFE 0x112c0
2185#define CSIEC 0x112e0
2186#define DMIEC 0x112e4
2187#define DDREC 0x112e8
2188#define PEG0EC 0x112ec
2189#define PEG1EC 0x112f0
2190#define GFXEC 0x112f4
2191#define RPPREVBSYTUPAVG 0x113b8
2192#define RPPREVBSYTDNAVG 0x113bc
2193#define ECR 0x11600
2194#define ECR_GPFE (1<<31)
2195#define ECR_IMONE (1<<30)
2196#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2197#define OGW0 0x11608
2198#define OGW1 0x1160c
2199#define EG0 0x11610
2200#define EG1 0x11614
2201#define EG2 0x11618
2202#define EG3 0x1161c
2203#define EG4 0x11620
2204#define EG5 0x11624
2205#define EG6 0x11628
2206#define EG7 0x1162c
2207#define PXW 0x11664
2208#define PXWL 0x11680
2209#define LCFUSE02 0x116c0
2210#define LCFUSE_HIV_MASK 0x000000ff
2211#define CSIPLL0 0x12c10
2212#define DDRMPLL1 0X12c20
Eric Anholt7d573822009-01-02 13:33:00 -08002213#define PEG_BAND_GAP_DATA 0x14d68
2214
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002215#define GEN6_GT_THREAD_STATUS_REG 0x13805c
2216#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2217#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
2218
Ben Widawsky153b4b952013-10-22 22:05:09 -07002219#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
2220#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2221#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002222
Jesse Barnes585fb112008-07-29 11:54:06 -07002223/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002224 * Logical Context regs
2225 */
2226#define CCID 0x2180
2227#define CCID_EN (1<<0)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002228/*
2229 * Notes on SNB/IVB/VLV context size:
2230 * - Power context is saved elsewhere (LLC or stolen)
2231 * - Ring/execlist context is saved on SNB, not on IVB
2232 * - Extended context size already includes render context size
2233 * - We always need to follow the extended context size.
2234 * SNB BSpec has comments indicating that we should use the
2235 * render context size instead if execlists are disabled, but
2236 * based on empirical testing that's just nonsense.
2237 * - Pipelined/VF state is saved on SNB/IVB respectively
2238 * - GT1 size just indicates how much of render context
2239 * doesn't need saving on GT1
2240 */
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002241#define CXT_SIZE 0x21a0
2242#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
2243#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
2244#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
2245#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
2246#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002247#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002248 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2249 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002250#define GEN7_CXT_SIZE 0x21a8
Ben Widawsky6a4ea122012-07-18 10:10:10 -07002251#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
2252#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002253#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
2254#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
2255#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
2256#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002257#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002258 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawskya0de80a2013-06-25 21:53:40 -07002259/* Haswell does have the CXT_SIZE register however it does not appear to be
2260 * valid. Now, docs explain in dwords what is in the context object. The full
2261 * size is 70720 bytes, however, the power context and execlist context will
2262 * never be saved (power context is stored elsewhere, and execlists don't work
2263 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
2264 */
2265#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
Ben Widawsky88976442013-11-02 21:07:05 -07002266/* Same as Haswell, but 72064 bytes now. */
2267#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2268
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002269
Jesse Barnese454a052013-09-26 17:55:58 -07002270#define VLV_CLK_CTL2 0x101104
2271#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2272
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002273/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002274 * Overlay regs
2275 */
2276
2277#define OVADD 0x30000
2278#define DOVSTA 0x30008
2279#define OC_BUF (0x3<<20)
2280#define OGAMC5 0x30010
2281#define OGAMC4 0x30014
2282#define OGAMC3 0x30018
2283#define OGAMC2 0x3001c
2284#define OGAMC1 0x30020
2285#define OGAMC0 0x30024
2286
2287/*
2288 * Display engine regs
2289 */
2290
Shuang He8bf1e9f2013-10-15 18:55:27 +01002291/* Pipe A CRC regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002292#define _PIPE_CRC_CTL_A 0x60050
Shuang He8bf1e9f2013-10-15 18:55:27 +01002293#define PIPE_CRC_ENABLE (1 << 31)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002294/* ivb+ source selection */
Shuang He8bf1e9f2013-10-15 18:55:27 +01002295#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2296#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2297#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002298/* ilk+ source selection */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002299#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2300#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2301#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2302/* embedded DP port on the north display block, reserved on ivb */
2303#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2304#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
Daniel Vetterb4437a42013-10-16 22:55:54 +02002305/* vlv source selection */
2306#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2307#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2308#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2309/* with DP port the pipe source is invalid */
2310#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2311#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2312#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2313/* gen3+ source selection */
2314#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2315#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2316#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2317/* with DP/TV port the pipe source is invalid */
2318#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2319#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2320#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2321#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2322#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2323/* gen2 doesn't have source selection bits */
Daniel Vetter52f843f2013-10-21 17:26:38 +02002324#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002325
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002326#define _PIPE_CRC_RES_1_A_IVB 0x60064
2327#define _PIPE_CRC_RES_2_A_IVB 0x60068
2328#define _PIPE_CRC_RES_3_A_IVB 0x6006c
2329#define _PIPE_CRC_RES_4_A_IVB 0x60070
2330#define _PIPE_CRC_RES_5_A_IVB 0x60074
2331
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002332#define _PIPE_CRC_RES_RED_A 0x60060
2333#define _PIPE_CRC_RES_GREEN_A 0x60064
2334#define _PIPE_CRC_RES_BLUE_A 0x60068
2335#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2336#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
Shuang He8bf1e9f2013-10-15 18:55:27 +01002337
2338/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002339#define _PIPE_CRC_RES_1_B_IVB 0x61064
2340#define _PIPE_CRC_RES_2_B_IVB 0x61068
2341#define _PIPE_CRC_RES_3_B_IVB 0x6106c
2342#define _PIPE_CRC_RES_4_B_IVB 0x61070
2343#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01002344
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002345#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002346#define PIPE_CRC_RES_1_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002347 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002348#define PIPE_CRC_RES_2_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002349 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002350#define PIPE_CRC_RES_3_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002351 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002352#define PIPE_CRC_RES_4_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002353 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002354#define PIPE_CRC_RES_5_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002355 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002356
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002357#define PIPE_CRC_RES_RED(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002358 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002359#define PIPE_CRC_RES_GREEN(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002360 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002361#define PIPE_CRC_RES_BLUE(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002362 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002363#define PIPE_CRC_RES_RES1_I915(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002364 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002365#define PIPE_CRC_RES_RES2_G4X(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002366 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002367
Jesse Barnes585fb112008-07-29 11:54:06 -07002368/* Pipe A timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002369#define _HTOTAL_A 0x60000
2370#define _HBLANK_A 0x60004
2371#define _HSYNC_A 0x60008
2372#define _VTOTAL_A 0x6000c
2373#define _VBLANK_A 0x60010
2374#define _VSYNC_A 0x60014
2375#define _PIPEASRC 0x6001c
2376#define _BCLRPAT_A 0x60020
2377#define _VSYNCSHIFT_A 0x60028
Jesse Barnes585fb112008-07-29 11:54:06 -07002378
2379/* Pipe B timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002380#define _HTOTAL_B 0x61000
2381#define _HBLANK_B 0x61004
2382#define _HSYNC_B 0x61008
2383#define _VTOTAL_B 0x6100c
2384#define _VBLANK_B 0x61010
2385#define _VSYNC_B 0x61014
2386#define _PIPEBSRC 0x6101c
2387#define _BCLRPAT_B 0x61020
2388#define _VSYNCSHIFT_B 0x61028
Daniel Vetter0529a0d2012-01-28 14:49:24 +01002389
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002390#define TRANSCODER_A_OFFSET 0x60000
2391#define TRANSCODER_B_OFFSET 0x61000
2392#define TRANSCODER_C_OFFSET 0x62000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03002393#define CHV_TRANSCODER_C_OFFSET 0x63000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002394#define TRANSCODER_EDP_OFFSET 0x6f000
2395
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002396#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2397 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2398 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002399
2400#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2401#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2402#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2403#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2404#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2405#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2406#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2407#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2408#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002409
Ben Widawskyed8546a2013-11-04 22:45:05 -08002410/* HSW+ eDP PSR registers */
2411#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
Ben Widawsky18b59922013-09-20 09:35:30 -07002412#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002413#define EDP_PSR_ENABLE (1<<31)
2414#define EDP_PSR_LINK_DISABLE (0<<27)
2415#define EDP_PSR_LINK_STANDBY (1<<27)
2416#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
2417#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
2418#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
2419#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
2420#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
2421#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2422#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2423#define EDP_PSR_TP1_TP2_SEL (0<<11)
2424#define EDP_PSR_TP1_TP3_SEL (1<<11)
2425#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2426#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2427#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2428#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2429#define EDP_PSR_TP1_TIME_500us (0<<4)
2430#define EDP_PSR_TP1_TIME_100us (1<<4)
2431#define EDP_PSR_TP1_TIME_2500us (2<<4)
2432#define EDP_PSR_TP1_TIME_0us (3<<4)
2433#define EDP_PSR_IDLE_FRAME_SHIFT 0
2434
Ben Widawsky18b59922013-09-20 09:35:30 -07002435#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2436#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002437#define EDP_PSR_DPCD_COMMAND 0x80060000
Ben Widawsky18b59922013-09-20 09:35:30 -07002438#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002439#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
Ben Widawsky18b59922013-09-20 09:35:30 -07002440#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2441#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2442#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002443
Ben Widawsky18b59922013-09-20 09:35:30 -07002444#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002445#define EDP_PSR_STATUS_STATE_MASK (7<<29)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002446#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2447#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2448#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2449#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2450#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2451#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2452#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2453#define EDP_PSR_STATUS_LINK_MASK (3<<26)
2454#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2455#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2456#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2457#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2458#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2459#define EDP_PSR_STATUS_COUNT_SHIFT 16
2460#define EDP_PSR_STATUS_COUNT_MASK 0xf
2461#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2462#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2463#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2464#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2465#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2466#define EDP_PSR_STATUS_IDLE_MASK 0xf
2467
Ben Widawsky18b59922013-09-20 09:35:30 -07002468#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002469#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002470
Ben Widawsky18b59922013-09-20 09:35:30 -07002471#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002472#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2473#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2474#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2475
Jesse Barnes585fb112008-07-29 11:54:06 -07002476/* VGA port control */
2477#define ADPA 0x61100
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002478#define PCH_ADPA 0xe1100
Daniel Vetter540a8952012-07-11 16:27:57 +02002479#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002480
Jesse Barnes585fb112008-07-29 11:54:06 -07002481#define ADPA_DAC_ENABLE (1<<31)
2482#define ADPA_DAC_DISABLE 0
2483#define ADPA_PIPE_SELECT_MASK (1<<30)
2484#define ADPA_PIPE_A_SELECT 0
2485#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07002486#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002487/* CPT uses bits 29:30 for pch transcoder select */
2488#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2489#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2490#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2491#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2492#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2493#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2494#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2495#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2496#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2497#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2498#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2499#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2500#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2501#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2502#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2503#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2504#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2505#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2506#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07002507#define ADPA_USE_VGA_HVPOLARITY (1<<15)
2508#define ADPA_SETS_HVPOLARITY 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002509#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07002510#define ADPA_VSYNC_CNTL_ENABLE 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002511#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07002512#define ADPA_HSYNC_CNTL_ENABLE 0
2513#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2514#define ADPA_VSYNC_ACTIVE_LOW 0
2515#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2516#define ADPA_HSYNC_ACTIVE_LOW 0
2517#define ADPA_DPMS_MASK (~(3<<10))
2518#define ADPA_DPMS_ON (0<<10)
2519#define ADPA_DPMS_SUSPEND (1<<10)
2520#define ADPA_DPMS_STANDBY (2<<10)
2521#define ADPA_DPMS_OFF (3<<10)
2522
Chris Wilson939fe4d2010-10-09 10:33:26 +01002523
Jesse Barnes585fb112008-07-29 11:54:06 -07002524/* Hotplug control (945+ only) */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002525#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01002526#define PORTB_HOTPLUG_INT_EN (1 << 29)
2527#define PORTC_HOTPLUG_INT_EN (1 << 28)
2528#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07002529#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2530#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2531#define TV_HOTPLUG_INT_EN (1 << 18)
2532#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05002533#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2534 PORTC_HOTPLUG_INT_EN | \
2535 PORTD_HOTPLUG_INT_EN | \
2536 SDVOC_HOTPLUG_INT_EN | \
2537 SDVOB_HOTPLUG_INT_EN | \
2538 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07002539#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08002540#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2541/* must use period 64 on GM45 according to docs */
2542#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2543#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2544#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2545#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2546#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2547#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2548#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2549#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2550#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2551#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2552#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2553#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002554
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002555#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02002556/*
2557 * HDMI/DP bits are gen4+
2558 *
2559 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2560 * Please check the detailed lore in the commit message for for experimental
2561 * evidence.
2562 */
Todd Previte232a6ee2014-01-23 00:13:41 -07002563#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2564#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2565#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2566/* VLV DP/HDMI bits again match Bspec */
2567#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2568#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2569#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01002570#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2571#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2572#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01002573/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07002574#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2575#define TV_HOTPLUG_INT_STATUS (1 << 10)
2576#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2577#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2578#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2579#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Daniel Vetter4aeebd72013-10-31 09:53:36 +01002580#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2581#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2582#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
Imre Deakbfbdb422014-01-16 19:56:53 +02002583#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2584
Chris Wilson084b6122012-05-11 18:01:33 +01002585/* SDVO is different across gen3/4 */
2586#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2587#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02002588/*
2589 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2590 * since reality corrobates that they're the same as on gen3. But keep these
2591 * bits here (and the comment!) to help any other lost wanderers back onto the
2592 * right tracks.
2593 */
Chris Wilson084b6122012-05-11 18:01:33 +01002594#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2595#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2596#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2597#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05002598#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2599 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2600 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2601 PORTB_HOTPLUG_INT_STATUS | \
2602 PORTC_HOTPLUG_INT_STATUS | \
2603 PORTD_HOTPLUG_INT_STATUS)
2604
Egbert Eiche5868a32013-02-28 04:17:12 -05002605#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2606 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2607 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2608 PORTB_HOTPLUG_INT_STATUS | \
2609 PORTC_HOTPLUG_INT_STATUS | \
2610 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07002611
Paulo Zanonic20cd312013-02-19 16:21:45 -03002612/* SDVO and HDMI port control.
2613 * The same register may be used for SDVO or HDMI */
2614#define GEN3_SDVOB 0x61140
2615#define GEN3_SDVOC 0x61160
2616#define GEN4_HDMIB GEN3_SDVOB
2617#define GEN4_HDMIC GEN3_SDVOC
Ville Syrjälä9418c1f2014-04-09 13:28:56 +03002618#define CHV_HDMID 0x6116C
Paulo Zanonic20cd312013-02-19 16:21:45 -03002619#define PCH_SDVOB 0xe1140
2620#define PCH_HDMIB PCH_SDVOB
2621#define PCH_HDMIC 0xe1150
2622#define PCH_HDMID 0xe1160
2623
Daniel Vetter84093602013-11-01 10:50:21 +01002624#define PORT_DFT_I9XX 0x61150
2625#define DC_BALANCE_RESET (1 << 25)
2626#define PORT_DFT2_G4X 0x61154
2627#define DC_BALANCE_RESET_VLV (1 << 31)
2628#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2629#define PIPE_B_SCRAMBLE_RESET (1 << 1)
2630#define PIPE_A_SCRAMBLE_RESET (1 << 0)
2631
Paulo Zanonic20cd312013-02-19 16:21:45 -03002632/* Gen 3 SDVO bits: */
2633#define SDVO_ENABLE (1 << 31)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002634#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2635#define SDVO_PIPE_SEL_MASK (1 << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002636#define SDVO_PIPE_B_SELECT (1 << 30)
2637#define SDVO_STALL_SELECT (1 << 29)
2638#define SDVO_INTERRUPT_ENABLE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002639/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002640 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07002641 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07002642 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2643 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002644#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07002645#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03002646#define SDVO_PHASE_SELECT_MASK (15 << 19)
2647#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2648#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2649#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2650#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2651#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2652#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002653/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002654#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2655 SDVO_INTERRUPT_ENABLE)
2656#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2657
2658/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002659#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03002660#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002661#define SDVO_ENCODING_SDVO (0 << 10)
2662#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002663#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2664#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002665#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002666#define SDVO_AUDIO_ENABLE (1 << 6)
2667/* VSYNC/HSYNC bits new with 965, default is to be set */
2668#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2669#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2670
2671/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002672#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002673#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2674
2675/* Gen 6 (CPT) SDVO/HDMI bits: */
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002676#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2677#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002678
Chon Ming Lee44f37d12014-04-09 13:28:21 +03002679/* CHV SDVO/HDMI bits: */
2680#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2681#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2682
Jesse Barnes585fb112008-07-29 11:54:06 -07002683
2684/* DVO port control */
2685#define DVOA 0x61120
2686#define DVOB 0x61140
2687#define DVOC 0x61160
2688#define DVO_ENABLE (1 << 31)
2689#define DVO_PIPE_B_SELECT (1 << 30)
2690#define DVO_PIPE_STALL_UNUSED (0 << 28)
2691#define DVO_PIPE_STALL (1 << 28)
2692#define DVO_PIPE_STALL_TV (2 << 28)
2693#define DVO_PIPE_STALL_MASK (3 << 28)
2694#define DVO_USE_VGA_SYNC (1 << 15)
2695#define DVO_DATA_ORDER_I740 (0 << 14)
2696#define DVO_DATA_ORDER_FP (1 << 14)
2697#define DVO_VSYNC_DISABLE (1 << 11)
2698#define DVO_HSYNC_DISABLE (1 << 10)
2699#define DVO_VSYNC_TRISTATE (1 << 9)
2700#define DVO_HSYNC_TRISTATE (1 << 8)
2701#define DVO_BORDER_ENABLE (1 << 7)
2702#define DVO_DATA_ORDER_GBRG (1 << 6)
2703#define DVO_DATA_ORDER_RGGB (0 << 6)
2704#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2705#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2706#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2707#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2708#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2709#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2710#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2711#define DVO_PRESERVE_MASK (0x7<<24)
2712#define DVOA_SRCDIM 0x61124
2713#define DVOB_SRCDIM 0x61144
2714#define DVOC_SRCDIM 0x61164
2715#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2716#define DVO_SRCDIM_VERTICAL_SHIFT 0
2717
2718/* LVDS port control */
2719#define LVDS 0x61180
2720/*
2721 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2722 * the DPLL semantics change when the LVDS is assigned to that pipe.
2723 */
2724#define LVDS_PORT_EN (1 << 31)
2725/* Selects pipe B for LVDS data. Must be set on pre-965. */
2726#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08002727#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07002728#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08002729/* LVDS dithering flag on 965/g4x platform */
2730#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08002731/* LVDS sync polarity flags. Set to invert (i.e. negative) */
2732#define LVDS_VSYNC_POLARITY (1 << 21)
2733#define LVDS_HSYNC_POLARITY (1 << 20)
2734
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08002735/* Enable border for unscaled (or aspect-scaled) display */
2736#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07002737/*
2738 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2739 * pixel.
2740 */
2741#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2742#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2743#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2744/*
2745 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2746 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2747 * on.
2748 */
2749#define LVDS_A3_POWER_MASK (3 << 6)
2750#define LVDS_A3_POWER_DOWN (0 << 6)
2751#define LVDS_A3_POWER_UP (3 << 6)
2752/*
2753 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2754 * is set.
2755 */
2756#define LVDS_CLKB_POWER_MASK (3 << 4)
2757#define LVDS_CLKB_POWER_DOWN (0 << 4)
2758#define LVDS_CLKB_POWER_UP (3 << 4)
2759/*
2760 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2761 * setting for whether we are in dual-channel mode. The B3 pair will
2762 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2763 */
2764#define LVDS_B0B3_POWER_MASK (3 << 2)
2765#define LVDS_B0B3_POWER_DOWN (0 << 2)
2766#define LVDS_B0B3_POWER_UP (3 << 2)
2767
David Härdeman3c17fe42010-09-24 21:44:32 +02002768/* Video Data Island Packet control */
2769#define VIDEO_DIP_DATA 0x61178
Paulo Zanoniadf00b22012-09-25 13:23:34 -03002770/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2771 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2772 * of the infoframe structure specified by CEA-861. */
2773#define VIDEO_DIP_DATA_SIZE 32
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002774#define VIDEO_DIP_VSC_DATA_SIZE 36
David Härdeman3c17fe42010-09-24 21:44:32 +02002775#define VIDEO_DIP_CTL 0x61170
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002776/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02002777#define VIDEO_DIP_ENABLE (1 << 31)
Ville Syrjälä822cdc52014-01-23 23:15:34 +02002778#define VIDEO_DIP_PORT(port) ((port) << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03002779#define VIDEO_DIP_PORT_MASK (3 << 29)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002780#define VIDEO_DIP_ENABLE_GCP (1 << 25)
David Härdeman3c17fe42010-09-24 21:44:32 +02002781#define VIDEO_DIP_ENABLE_AVI (1 << 21)
2782#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002783#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
David Härdeman3c17fe42010-09-24 21:44:32 +02002784#define VIDEO_DIP_ENABLE_SPD (8 << 21)
2785#define VIDEO_DIP_SELECT_AVI (0 << 19)
2786#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2787#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07002788#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02002789#define VIDEO_DIP_FREQ_ONCE (0 << 16)
2790#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2791#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03002792#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002793/* HSW and later: */
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002794#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2795#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002796#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002797#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2798#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002799#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02002800
Jesse Barnes585fb112008-07-29 11:54:06 -07002801/* Panel power sequencing */
2802#define PP_STATUS 0x61200
2803#define PP_ON (1 << 31)
2804/*
2805 * Indicates that all dependencies of the panel are on:
2806 *
2807 * - PLL enabled
2808 * - pipe enabled
2809 * - LVDS/DVOB/DVOC on
2810 */
2811#define PP_READY (1 << 30)
2812#define PP_SEQUENCE_NONE (0 << 28)
Keith Packard99ea7122011-11-01 19:57:50 -07002813#define PP_SEQUENCE_POWER_UP (1 << 28)
2814#define PP_SEQUENCE_POWER_DOWN (2 << 28)
2815#define PP_SEQUENCE_MASK (3 << 28)
2816#define PP_SEQUENCE_SHIFT 28
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002817#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002818#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07002819#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2820#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2821#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2822#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2823#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2824#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2825#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2826#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2827#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07002828#define PP_CONTROL 0x61204
2829#define POWER_TARGET_ON (1 << 0)
2830#define PP_ON_DELAYS 0x61208
2831#define PP_OFF_DELAYS 0x6120c
2832#define PP_DIVISOR 0x61210
2833
2834/* Panel fitting */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002835#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07002836#define PFIT_ENABLE (1 << 31)
2837#define PFIT_PIPE_MASK (3 << 29)
2838#define PFIT_PIPE_SHIFT 29
2839#define VERT_INTERP_DISABLE (0 << 10)
2840#define VERT_INTERP_BILINEAR (1 << 10)
2841#define VERT_INTERP_MASK (3 << 10)
2842#define VERT_AUTO_SCALE (1 << 9)
2843#define HORIZ_INTERP_DISABLE (0 << 6)
2844#define HORIZ_INTERP_BILINEAR (1 << 6)
2845#define HORIZ_INTERP_MASK (3 << 6)
2846#define HORIZ_AUTO_SCALE (1 << 5)
2847#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08002848#define PFIT_FILTER_FUZZY (0 << 24)
2849#define PFIT_SCALING_AUTO (0 << 26)
2850#define PFIT_SCALING_PROGRAMMED (1 << 26)
2851#define PFIT_SCALING_PILLAR (2 << 26)
2852#define PFIT_SCALING_LETTER (3 << 26)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002853#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08002854/* Pre-965 */
2855#define PFIT_VERT_SCALE_SHIFT 20
2856#define PFIT_VERT_SCALE_MASK 0xfff00000
2857#define PFIT_HORIZ_SCALE_SHIFT 4
2858#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2859/* 965+ */
2860#define PFIT_VERT_SCALE_SHIFT_965 16
2861#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2862#define PFIT_HORIZ_SCALE_SHIFT_965 0
2863#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2864
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002865#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07002866
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002867#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
2868#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
Jesse Barnes07bf1392013-10-31 18:55:50 +02002869#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2870 _VLV_BLC_PWM_CTL2_B)
2871
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002872#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
2873#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
Jesse Barnes07bf1392013-10-31 18:55:50 +02002874#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2875 _VLV_BLC_PWM_CTL_B)
2876
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002877#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
2878#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
Jesse Barnes07bf1392013-10-31 18:55:50 +02002879#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2880 _VLV_BLC_HIST_CTL_B)
2881
Jesse Barnes585fb112008-07-29 11:54:06 -07002882/* Backlight control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002883#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02002884#define BLM_PWM_ENABLE (1 << 31)
2885#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2886#define BLM_PIPE_SELECT (1 << 29)
2887#define BLM_PIPE_SELECT_IVB (3 << 29)
2888#define BLM_PIPE_A (0 << 29)
2889#define BLM_PIPE_B (1 << 29)
2890#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03002891#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
2892#define BLM_TRANSCODER_B BLM_PIPE_B
2893#define BLM_TRANSCODER_C BLM_PIPE_C
2894#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02002895#define BLM_PIPE(pipe) ((pipe) << 29)
2896#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
2897#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2898#define BLM_PHASE_IN_ENABLE (1 << 25)
2899#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2900#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2901#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2902#define BLM_PHASE_IN_COUNT_SHIFT (8)
2903#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2904#define BLM_PHASE_IN_INCR_SHIFT (0)
2905#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002906#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01002907/*
2908 * This is the most significant 15 bits of the number of backlight cycles in a
2909 * complete cycle of the modulated backlight control.
2910 *
2911 * The actual value is this field multiplied by two.
2912 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02002913#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2914#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2915#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002916/*
2917 * This is the number of cycles out of the backlight modulation cycle for which
2918 * the backlight is on.
2919 *
2920 * This field must be no greater than the number of cycles in the complete
2921 * backlight modulation cycle.
2922 */
2923#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2924#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02002925#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2926#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002927
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002928#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07002929
Daniel Vetter7cf41602012-06-05 10:07:09 +02002930/* New registers for PCH-split platforms. Safe where new bits show up, the
2931 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2932#define BLC_PWM_CPU_CTL2 0x48250
2933#define BLC_PWM_CPU_CTL 0x48254
2934
Paulo Zanonibe256dc2013-07-23 11:19:26 -03002935#define HSW_BLC_PWM2_CTL 0x48350
2936
Daniel Vetter7cf41602012-06-05 10:07:09 +02002937/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2938 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2939#define BLC_PWM_PCH_CTL1 0xc8250
Daniel Vetter4b4147c2012-07-11 00:31:06 +02002940#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02002941#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
2942#define BLM_PCH_POLARITY (1 << 29)
2943#define BLC_PWM_PCH_CTL2 0xc8254
2944
Paulo Zanonibe256dc2013-07-23 11:19:26 -03002945#define UTIL_PIN_CTL 0x48400
2946#define UTIL_PIN_ENABLE (1 << 31)
2947
2948#define PCH_GTC_CTL 0xe7000
2949#define PCH_GTC_ENABLE (1 << 31)
2950
Jesse Barnes585fb112008-07-29 11:54:06 -07002951/* TV port control */
2952#define TV_CTL 0x68000
Ville Syrjälä646b4262014-04-25 20:14:30 +03002953/* Enables the TV encoder */
Jesse Barnes585fb112008-07-29 11:54:06 -07002954# define TV_ENC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002955/* Sources the TV encoder input from pipe B instead of A. */
Jesse Barnes585fb112008-07-29 11:54:06 -07002956# define TV_ENC_PIPEB_SELECT (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002957/* Outputs composite video (DAC A only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07002958# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002959/* Outputs SVideo video (DAC B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07002960# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002961/* Outputs Component video (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07002962# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002963/* Outputs Composite and SVideo (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07002964# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2965# define TV_TRILEVEL_SYNC (1 << 21)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002966/* Enables slow sync generation (945GM only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07002967# define TV_SLOW_SYNC (1 << 20)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002968/* Selects 4x oversampling for 480i and 576p */
Jesse Barnes585fb112008-07-29 11:54:06 -07002969# define TV_OVERSAMPLE_4X (0 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002970/* Selects 2x oversampling for 720p and 1080i */
Jesse Barnes585fb112008-07-29 11:54:06 -07002971# define TV_OVERSAMPLE_2X (1 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002972/* Selects no oversampling for 1080p */
Jesse Barnes585fb112008-07-29 11:54:06 -07002973# define TV_OVERSAMPLE_NONE (2 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002974/* Selects 8x oversampling */
Jesse Barnes585fb112008-07-29 11:54:06 -07002975# define TV_OVERSAMPLE_8X (3 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002976/* Selects progressive mode rather than interlaced */
Jesse Barnes585fb112008-07-29 11:54:06 -07002977# define TV_PROGRESSIVE (1 << 17)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002978/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
Jesse Barnes585fb112008-07-29 11:54:06 -07002979# define TV_PAL_BURST (1 << 16)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002980/* Field for setting delay of Y compared to C */
Jesse Barnes585fb112008-07-29 11:54:06 -07002981# define TV_YC_SKEW_MASK (7 << 12)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002982/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002983# define TV_ENC_SDP_FIX (1 << 11)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002984/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002985 * Enables a fix for the 915GM only.
2986 *
2987 * Not sure what it does.
2988 */
2989# define TV_ENC_C0_FIX (1 << 10)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002990/* Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08002991# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07002992# define TV_FUSE_STATE_MASK (3 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002993/* Read-only state that reports all features enabled */
Jesse Barnes585fb112008-07-29 11:54:06 -07002994# define TV_FUSE_STATE_ENABLED (0 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002995/* Read-only state that reports that Macrovision is disabled in hardware*/
Jesse Barnes585fb112008-07-29 11:54:06 -07002996# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002997/* Read-only state that reports that TV-out is disabled in hardware. */
Jesse Barnes585fb112008-07-29 11:54:06 -07002998# define TV_FUSE_STATE_DISABLED (2 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002999/* Normal operation */
Jesse Barnes585fb112008-07-29 11:54:06 -07003000# define TV_TEST_MODE_NORMAL (0 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003001/* Encoder test pattern 1 - combo pattern */
Jesse Barnes585fb112008-07-29 11:54:06 -07003002# define TV_TEST_MODE_PATTERN_1 (1 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003003/* Encoder test pattern 2 - full screen vertical 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003004# define TV_TEST_MODE_PATTERN_2 (2 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003005/* Encoder test pattern 3 - full screen horizontal 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003006# define TV_TEST_MODE_PATTERN_3 (3 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003007/* Encoder test pattern 4 - random noise */
Jesse Barnes585fb112008-07-29 11:54:06 -07003008# define TV_TEST_MODE_PATTERN_4 (4 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003009/* Encoder test pattern 5 - linear color ramps */
Jesse Barnes585fb112008-07-29 11:54:06 -07003010# define TV_TEST_MODE_PATTERN_5 (5 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003011/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003012 * This test mode forces the DACs to 50% of full output.
3013 *
3014 * This is used for load detection in combination with TVDAC_SENSE_MASK
3015 */
3016# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3017# define TV_TEST_MODE_MASK (7 << 0)
3018
3019#define TV_DAC 0x68004
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01003020# define TV_DAC_SAVE 0x00ffff00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003021/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003022 * Reports that DAC state change logic has reported change (RO).
3023 *
3024 * This gets cleared when TV_DAC_STATE_EN is cleared
3025*/
3026# define TVDAC_STATE_CHG (1 << 31)
3027# define TVDAC_SENSE_MASK (7 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003028/* Reports that DAC A voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003029# define TVDAC_A_SENSE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003030/* Reports that DAC B voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003031# define TVDAC_B_SENSE (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003032/* Reports that DAC C voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003033# define TVDAC_C_SENSE (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003034/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003035 * Enables DAC state detection logic, for load-based TV detection.
3036 *
3037 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3038 * to off, for load detection to work.
3039 */
3040# define TVDAC_STATE_CHG_EN (1 << 27)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003041/* Sets the DAC A sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003042# define TVDAC_A_SENSE_CTL (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003043/* Sets the DAC B sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003044# define TVDAC_B_SENSE_CTL (1 << 25)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003045/* Sets the DAC C sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003046# define TVDAC_C_SENSE_CTL (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003047/* Overrides the ENC_ENABLE and DAC voltage levels */
Jesse Barnes585fb112008-07-29 11:54:06 -07003048# define DAC_CTL_OVERRIDE (1 << 7)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003049/* Sets the slew rate. Must be preserved in software */
Jesse Barnes585fb112008-07-29 11:54:06 -07003050# define ENC_TVDAC_SLEW_FAST (1 << 6)
3051# define DAC_A_1_3_V (0 << 4)
3052# define DAC_A_1_1_V (1 << 4)
3053# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08003054# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07003055# define DAC_B_1_3_V (0 << 2)
3056# define DAC_B_1_1_V (1 << 2)
3057# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08003058# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003059# define DAC_C_1_3_V (0 << 0)
3060# define DAC_C_1_1_V (1 << 0)
3061# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08003062# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003063
Ville Syrjälä646b4262014-04-25 20:14:30 +03003064/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003065 * CSC coefficients are stored in a floating point format with 9 bits of
3066 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3067 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3068 * -1 (0x3) being the only legal negative value.
3069 */
3070#define TV_CSC_Y 0x68010
3071# define TV_RY_MASK 0x07ff0000
3072# define TV_RY_SHIFT 16
3073# define TV_GY_MASK 0x00000fff
3074# define TV_GY_SHIFT 0
3075
3076#define TV_CSC_Y2 0x68014
3077# define TV_BY_MASK 0x07ff0000
3078# define TV_BY_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003079/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003080 * Y attenuation for component video.
3081 *
3082 * Stored in 1.9 fixed point.
3083 */
3084# define TV_AY_MASK 0x000003ff
3085# define TV_AY_SHIFT 0
3086
3087#define TV_CSC_U 0x68018
3088# define TV_RU_MASK 0x07ff0000
3089# define TV_RU_SHIFT 16
3090# define TV_GU_MASK 0x000007ff
3091# define TV_GU_SHIFT 0
3092
3093#define TV_CSC_U2 0x6801c
3094# define TV_BU_MASK 0x07ff0000
3095# define TV_BU_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003096/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003097 * U attenuation for component video.
3098 *
3099 * Stored in 1.9 fixed point.
3100 */
3101# define TV_AU_MASK 0x000003ff
3102# define TV_AU_SHIFT 0
3103
3104#define TV_CSC_V 0x68020
3105# define TV_RV_MASK 0x0fff0000
3106# define TV_RV_SHIFT 16
3107# define TV_GV_MASK 0x000007ff
3108# define TV_GV_SHIFT 0
3109
3110#define TV_CSC_V2 0x68024
3111# define TV_BV_MASK 0x07ff0000
3112# define TV_BV_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003113/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003114 * V attenuation for component video.
3115 *
3116 * Stored in 1.9 fixed point.
3117 */
3118# define TV_AV_MASK 0x000007ff
3119# define TV_AV_SHIFT 0
3120
3121#define TV_CLR_KNOBS 0x68028
Ville Syrjälä646b4262014-04-25 20:14:30 +03003122/* 2s-complement brightness adjustment */
Jesse Barnes585fb112008-07-29 11:54:06 -07003123# define TV_BRIGHTNESS_MASK 0xff000000
3124# define TV_BRIGHTNESS_SHIFT 24
Ville Syrjälä646b4262014-04-25 20:14:30 +03003125/* Contrast adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003126# define TV_CONTRAST_MASK 0x00ff0000
3127# define TV_CONTRAST_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003128/* Saturation adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003129# define TV_SATURATION_MASK 0x0000ff00
3130# define TV_SATURATION_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003131/* Hue adjustment, as an integer phase angle in degrees */
Jesse Barnes585fb112008-07-29 11:54:06 -07003132# define TV_HUE_MASK 0x000000ff
3133# define TV_HUE_SHIFT 0
3134
3135#define TV_CLR_LEVEL 0x6802c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003136/* Controls the DAC level for black */
Jesse Barnes585fb112008-07-29 11:54:06 -07003137# define TV_BLACK_LEVEL_MASK 0x01ff0000
3138# define TV_BLACK_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003139/* Controls the DAC level for blanking */
Jesse Barnes585fb112008-07-29 11:54:06 -07003140# define TV_BLANK_LEVEL_MASK 0x000001ff
3141# define TV_BLANK_LEVEL_SHIFT 0
3142
3143#define TV_H_CTL_1 0x68030
Ville Syrjälä646b4262014-04-25 20:14:30 +03003144/* Number of pixels in the hsync. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003145# define TV_HSYNC_END_MASK 0x1fff0000
3146# define TV_HSYNC_END_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003147/* Total number of pixels minus one in the line (display and blanking). */
Jesse Barnes585fb112008-07-29 11:54:06 -07003148# define TV_HTOTAL_MASK 0x00001fff
3149# define TV_HTOTAL_SHIFT 0
3150
3151#define TV_H_CTL_2 0x68034
Ville Syrjälä646b4262014-04-25 20:14:30 +03003152/* Enables the colorburst (needed for non-component color) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003153# define TV_BURST_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003154/* Offset of the colorburst from the start of hsync, in pixels minus one. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003155# define TV_HBURST_START_SHIFT 16
3156# define TV_HBURST_START_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003157/* Length of the colorburst */
Jesse Barnes585fb112008-07-29 11:54:06 -07003158# define TV_HBURST_LEN_SHIFT 0
3159# define TV_HBURST_LEN_MASK 0x0001fff
3160
3161#define TV_H_CTL_3 0x68038
Ville Syrjälä646b4262014-04-25 20:14:30 +03003162/* End of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003163# define TV_HBLANK_END_SHIFT 16
3164# define TV_HBLANK_END_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003165/* Start of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003166# define TV_HBLANK_START_SHIFT 0
3167# define TV_HBLANK_START_MASK 0x0001fff
3168
3169#define TV_V_CTL_1 0x6803c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003170/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003171# define TV_NBR_END_SHIFT 16
3172# define TV_NBR_END_MASK 0x07ff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003173/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003174# define TV_VI_END_F1_SHIFT 8
3175# define TV_VI_END_F1_MASK 0x00003f00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003176/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003177# define TV_VI_END_F2_SHIFT 0
3178# define TV_VI_END_F2_MASK 0x0000003f
3179
3180#define TV_V_CTL_2 0x68040
Ville Syrjälä646b4262014-04-25 20:14:30 +03003181/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003182# define TV_VSYNC_LEN_MASK 0x07ff0000
3183# define TV_VSYNC_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003184/* Offset of the start of vsync in field 1, measured in one less than the
Jesse Barnes585fb112008-07-29 11:54:06 -07003185 * number of half lines.
3186 */
3187# define TV_VSYNC_START_F1_MASK 0x00007f00
3188# define TV_VSYNC_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003189/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003190 * Offset of the start of vsync in field 2, measured in one less than the
3191 * number of half lines.
3192 */
3193# define TV_VSYNC_START_F2_MASK 0x0000007f
3194# define TV_VSYNC_START_F2_SHIFT 0
3195
3196#define TV_V_CTL_3 0x68044
Ville Syrjälä646b4262014-04-25 20:14:30 +03003197/* Enables generation of the equalization signal */
Jesse Barnes585fb112008-07-29 11:54:06 -07003198# define TV_EQUAL_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003199/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003200# define TV_VEQ_LEN_MASK 0x007f0000
3201# define TV_VEQ_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003202/* Offset of the start of equalization in field 1, measured in one less than
Jesse Barnes585fb112008-07-29 11:54:06 -07003203 * the number of half lines.
3204 */
3205# define TV_VEQ_START_F1_MASK 0x0007f00
3206# define TV_VEQ_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003207/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003208 * Offset of the start of equalization in field 2, measured in one less than
3209 * the number of half lines.
3210 */
3211# define TV_VEQ_START_F2_MASK 0x000007f
3212# define TV_VEQ_START_F2_SHIFT 0
3213
3214#define TV_V_CTL_4 0x68048
Ville Syrjälä646b4262014-04-25 20:14:30 +03003215/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003216 * Offset to start of vertical colorburst, measured in one less than the
3217 * number of lines from vertical start.
3218 */
3219# define TV_VBURST_START_F1_MASK 0x003f0000
3220# define TV_VBURST_START_F1_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003221/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003222 * Offset to the end of vertical colorburst, measured in one less than the
3223 * number of lines from the start of NBR.
3224 */
3225# define TV_VBURST_END_F1_MASK 0x000000ff
3226# define TV_VBURST_END_F1_SHIFT 0
3227
3228#define TV_V_CTL_5 0x6804c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003229/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003230 * Offset to start of vertical colorburst, measured in one less than the
3231 * number of lines from vertical start.
3232 */
3233# define TV_VBURST_START_F2_MASK 0x003f0000
3234# define TV_VBURST_START_F2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003235/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003236 * Offset to the end of vertical colorburst, measured in one less than the
3237 * number of lines from the start of NBR.
3238 */
3239# define TV_VBURST_END_F2_MASK 0x000000ff
3240# define TV_VBURST_END_F2_SHIFT 0
3241
3242#define TV_V_CTL_6 0x68050
Ville Syrjälä646b4262014-04-25 20:14:30 +03003243/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003244 * Offset to start of vertical colorburst, measured in one less than the
3245 * number of lines from vertical start.
3246 */
3247# define TV_VBURST_START_F3_MASK 0x003f0000
3248# define TV_VBURST_START_F3_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003249/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003250 * Offset to the end of vertical colorburst, measured in one less than the
3251 * number of lines from the start of NBR.
3252 */
3253# define TV_VBURST_END_F3_MASK 0x000000ff
3254# define TV_VBURST_END_F3_SHIFT 0
3255
3256#define TV_V_CTL_7 0x68054
Ville Syrjälä646b4262014-04-25 20:14:30 +03003257/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003258 * Offset to start of vertical colorburst, measured in one less than the
3259 * number of lines from vertical start.
3260 */
3261# define TV_VBURST_START_F4_MASK 0x003f0000
3262# define TV_VBURST_START_F4_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003263/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003264 * Offset to the end of vertical colorburst, measured in one less than the
3265 * number of lines from the start of NBR.
3266 */
3267# define TV_VBURST_END_F4_MASK 0x000000ff
3268# define TV_VBURST_END_F4_SHIFT 0
3269
3270#define TV_SC_CTL_1 0x68060
Ville Syrjälä646b4262014-04-25 20:14:30 +03003271/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003272# define TV_SC_DDA1_EN (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003273/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003274# define TV_SC_DDA2_EN (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003275/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003276# define TV_SC_DDA3_EN (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003277/* Sets the subcarrier DDA to reset frequency every other field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003278# define TV_SC_RESET_EVERY_2 (0 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003279/* Sets the subcarrier DDA to reset frequency every fourth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003280# define TV_SC_RESET_EVERY_4 (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003281/* Sets the subcarrier DDA to reset frequency every eighth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003282# define TV_SC_RESET_EVERY_8 (2 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003283/* Sets the subcarrier DDA to never reset the frequency */
Jesse Barnes585fb112008-07-29 11:54:06 -07003284# define TV_SC_RESET_NEVER (3 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003285/* Sets the peak amplitude of the colorburst.*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003286# define TV_BURST_LEVEL_MASK 0x00ff0000
3287# define TV_BURST_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003288/* Sets the increment of the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003289# define TV_SCDDA1_INC_MASK 0x00000fff
3290# define TV_SCDDA1_INC_SHIFT 0
3291
3292#define TV_SC_CTL_2 0x68064
Ville Syrjälä646b4262014-04-25 20:14:30 +03003293/* Sets the rollover for the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003294# define TV_SCDDA2_SIZE_MASK 0x7fff0000
3295# define TV_SCDDA2_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003296/* Sets the increent of the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003297# define TV_SCDDA2_INC_MASK 0x00007fff
3298# define TV_SCDDA2_INC_SHIFT 0
3299
3300#define TV_SC_CTL_3 0x68068
Ville Syrjälä646b4262014-04-25 20:14:30 +03003301/* Sets the rollover for the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003302# define TV_SCDDA3_SIZE_MASK 0x7fff0000
3303# define TV_SCDDA3_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003304/* Sets the increent of the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003305# define TV_SCDDA3_INC_MASK 0x00007fff
3306# define TV_SCDDA3_INC_SHIFT 0
3307
3308#define TV_WIN_POS 0x68070
Ville Syrjälä646b4262014-04-25 20:14:30 +03003309/* X coordinate of the display from the start of horizontal active */
Jesse Barnes585fb112008-07-29 11:54:06 -07003310# define TV_XPOS_MASK 0x1fff0000
3311# define TV_XPOS_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003312/* Y coordinate of the display from the start of vertical active (NBR) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003313# define TV_YPOS_MASK 0x00000fff
3314# define TV_YPOS_SHIFT 0
3315
3316#define TV_WIN_SIZE 0x68074
Ville Syrjälä646b4262014-04-25 20:14:30 +03003317/* Horizontal size of the display window, measured in pixels*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003318# define TV_XSIZE_MASK 0x1fff0000
3319# define TV_XSIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003320/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003321 * Vertical size of the display window, measured in pixels.
3322 *
3323 * Must be even for interlaced modes.
3324 */
3325# define TV_YSIZE_MASK 0x00000fff
3326# define TV_YSIZE_SHIFT 0
3327
3328#define TV_FILTER_CTL_1 0x68080
Ville Syrjälä646b4262014-04-25 20:14:30 +03003329/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003330 * Enables automatic scaling calculation.
3331 *
3332 * If set, the rest of the registers are ignored, and the calculated values can
3333 * be read back from the register.
3334 */
3335# define TV_AUTO_SCALE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003336/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003337 * Disables the vertical filter.
3338 *
3339 * This is required on modes more than 1024 pixels wide */
3340# define TV_V_FILTER_BYPASS (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003341/* Enables adaptive vertical filtering */
Jesse Barnes585fb112008-07-29 11:54:06 -07003342# define TV_VADAPT (1 << 28)
3343# define TV_VADAPT_MODE_MASK (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003344/* Selects the least adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003345# define TV_VADAPT_MODE_LEAST (0 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003346/* Selects the moderately adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003347# define TV_VADAPT_MODE_MODERATE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003348/* Selects the most adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003349# define TV_VADAPT_MODE_MOST (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003350/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003351 * Sets the horizontal scaling factor.
3352 *
3353 * This should be the fractional part of the horizontal scaling factor divided
3354 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3355 *
3356 * (src width - 1) / ((oversample * dest width) - 1)
3357 */
3358# define TV_HSCALE_FRAC_MASK 0x00003fff
3359# define TV_HSCALE_FRAC_SHIFT 0
3360
3361#define TV_FILTER_CTL_2 0x68084
Ville Syrjälä646b4262014-04-25 20:14:30 +03003362/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003363 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3364 *
3365 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3366 */
3367# define TV_VSCALE_INT_MASK 0x00038000
3368# define TV_VSCALE_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03003369/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003370 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3371 *
3372 * \sa TV_VSCALE_INT_MASK
3373 */
3374# define TV_VSCALE_FRAC_MASK 0x00007fff
3375# define TV_VSCALE_FRAC_SHIFT 0
3376
3377#define TV_FILTER_CTL_3 0x68088
Ville Syrjälä646b4262014-04-25 20:14:30 +03003378/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003379 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3380 *
3381 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3382 *
3383 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3384 */
3385# define TV_VSCALE_IP_INT_MASK 0x00038000
3386# define TV_VSCALE_IP_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03003387/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003388 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3389 *
3390 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3391 *
3392 * \sa TV_VSCALE_IP_INT_MASK
3393 */
3394# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3395# define TV_VSCALE_IP_FRAC_SHIFT 0
3396
3397#define TV_CC_CONTROL 0x68090
3398# define TV_CC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003399/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003400 * Specifies which field to send the CC data in.
3401 *
3402 * CC data is usually sent in field 0.
3403 */
3404# define TV_CC_FID_MASK (1 << 27)
3405# define TV_CC_FID_SHIFT 27
Ville Syrjälä646b4262014-04-25 20:14:30 +03003406/* Sets the horizontal position of the CC data. Usually 135. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003407# define TV_CC_HOFF_MASK 0x03ff0000
3408# define TV_CC_HOFF_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003409/* Sets the vertical position of the CC data. Usually 21 */
Jesse Barnes585fb112008-07-29 11:54:06 -07003410# define TV_CC_LINE_MASK 0x0000003f
3411# define TV_CC_LINE_SHIFT 0
3412
3413#define TV_CC_DATA 0x68094
3414# define TV_CC_RDY (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003415/* Second word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003416# define TV_CC_DATA_2_MASK 0x007f0000
3417# define TV_CC_DATA_2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003418/* First word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003419# define TV_CC_DATA_1_MASK 0x0000007f
3420# define TV_CC_DATA_1_SHIFT 0
3421
3422#define TV_H_LUMA_0 0x68100
3423#define TV_H_LUMA_59 0x681ec
3424#define TV_H_CHROMA_0 0x68200
3425#define TV_H_CHROMA_59 0x682ec
3426#define TV_V_LUMA_0 0x68300
3427#define TV_V_LUMA_42 0x683a8
3428#define TV_V_CHROMA_0 0x68400
3429#define TV_V_CHROMA_42 0x684a8
3430
Keith Packard040d87f2009-05-30 20:42:33 -07003431/* Display Port */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003432#define DP_A 0x64000 /* eDP */
Keith Packard040d87f2009-05-30 20:42:33 -07003433#define DP_B 0x64100
3434#define DP_C 0x64200
3435#define DP_D 0x64300
3436
3437#define DP_PORT_EN (1 << 31)
3438#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003439#define DP_PIPE_MASK (1 << 30)
Chon Ming Lee44f37d12014-04-09 13:28:21 +03003440#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
3441#define DP_PIPE_MASK_CHV (3 << 16)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003442
Keith Packard040d87f2009-05-30 20:42:33 -07003443/* Link training mode - select a suitable mode for each stage */
3444#define DP_LINK_TRAIN_PAT_1 (0 << 28)
3445#define DP_LINK_TRAIN_PAT_2 (1 << 28)
3446#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3447#define DP_LINK_TRAIN_OFF (3 << 28)
3448#define DP_LINK_TRAIN_MASK (3 << 28)
3449#define DP_LINK_TRAIN_SHIFT 28
3450
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003451/* CPT Link training mode */
3452#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3453#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3454#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3455#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3456#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3457#define DP_LINK_TRAIN_SHIFT_CPT 8
3458
Keith Packard040d87f2009-05-30 20:42:33 -07003459/* Signal voltages. These are mostly controlled by the other end */
3460#define DP_VOLTAGE_0_4 (0 << 25)
3461#define DP_VOLTAGE_0_6 (1 << 25)
3462#define DP_VOLTAGE_0_8 (2 << 25)
3463#define DP_VOLTAGE_1_2 (3 << 25)
3464#define DP_VOLTAGE_MASK (7 << 25)
3465#define DP_VOLTAGE_SHIFT 25
3466
3467/* Signal pre-emphasis levels, like voltages, the other end tells us what
3468 * they want
3469 */
3470#define DP_PRE_EMPHASIS_0 (0 << 22)
3471#define DP_PRE_EMPHASIS_3_5 (1 << 22)
3472#define DP_PRE_EMPHASIS_6 (2 << 22)
3473#define DP_PRE_EMPHASIS_9_5 (3 << 22)
3474#define DP_PRE_EMPHASIS_MASK (7 << 22)
3475#define DP_PRE_EMPHASIS_SHIFT 22
3476
3477/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02003478#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07003479#define DP_PORT_WIDTH_MASK (7 << 19)
3480
3481/* Mystic DPCD version 1.1 special mode */
3482#define DP_ENHANCED_FRAMING (1 << 18)
3483
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003484/* eDP */
3485#define DP_PLL_FREQ_270MHZ (0 << 16)
3486#define DP_PLL_FREQ_160MHZ (1 << 16)
3487#define DP_PLL_FREQ_MASK (3 << 16)
3488
Ville Syrjälä646b4262014-04-25 20:14:30 +03003489/* locked once port is enabled */
Keith Packard040d87f2009-05-30 20:42:33 -07003490#define DP_PORT_REVERSAL (1 << 15)
3491
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003492/* eDP */
3493#define DP_PLL_ENABLE (1 << 14)
3494
Ville Syrjälä646b4262014-04-25 20:14:30 +03003495/* sends the clock on lane 15 of the PEG for debug */
Keith Packard040d87f2009-05-30 20:42:33 -07003496#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3497
3498#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003499#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07003500
Ville Syrjälä646b4262014-04-25 20:14:30 +03003501/* limit RGB values to avoid confusing TVs */
Keith Packard040d87f2009-05-30 20:42:33 -07003502#define DP_COLOR_RANGE_16_235 (1 << 8)
3503
Ville Syrjälä646b4262014-04-25 20:14:30 +03003504/* Turn on the audio link */
Keith Packard040d87f2009-05-30 20:42:33 -07003505#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3506
Ville Syrjälä646b4262014-04-25 20:14:30 +03003507/* vs and hs sync polarity */
Keith Packard040d87f2009-05-30 20:42:33 -07003508#define DP_SYNC_VS_HIGH (1 << 4)
3509#define DP_SYNC_HS_HIGH (1 << 3)
3510
Ville Syrjälä646b4262014-04-25 20:14:30 +03003511/* A fantasy */
Keith Packard040d87f2009-05-30 20:42:33 -07003512#define DP_DETECTED (1 << 2)
3513
Ville Syrjälä646b4262014-04-25 20:14:30 +03003514/* The aux channel provides a way to talk to the
Keith Packard040d87f2009-05-30 20:42:33 -07003515 * signal sink for DDC etc. Max packet size supported
3516 * is 20 bytes in each direction, hence the 5 fixed
3517 * data registers
3518 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003519#define DPA_AUX_CH_CTL 0x64010
3520#define DPA_AUX_CH_DATA1 0x64014
3521#define DPA_AUX_CH_DATA2 0x64018
3522#define DPA_AUX_CH_DATA3 0x6401c
3523#define DPA_AUX_CH_DATA4 0x64020
3524#define DPA_AUX_CH_DATA5 0x64024
3525
Keith Packard040d87f2009-05-30 20:42:33 -07003526#define DPB_AUX_CH_CTL 0x64110
3527#define DPB_AUX_CH_DATA1 0x64114
3528#define DPB_AUX_CH_DATA2 0x64118
3529#define DPB_AUX_CH_DATA3 0x6411c
3530#define DPB_AUX_CH_DATA4 0x64120
3531#define DPB_AUX_CH_DATA5 0x64124
3532
3533#define DPC_AUX_CH_CTL 0x64210
3534#define DPC_AUX_CH_DATA1 0x64214
3535#define DPC_AUX_CH_DATA2 0x64218
3536#define DPC_AUX_CH_DATA3 0x6421c
3537#define DPC_AUX_CH_DATA4 0x64220
3538#define DPC_AUX_CH_DATA5 0x64224
3539
3540#define DPD_AUX_CH_CTL 0x64310
3541#define DPD_AUX_CH_DATA1 0x64314
3542#define DPD_AUX_CH_DATA2 0x64318
3543#define DPD_AUX_CH_DATA3 0x6431c
3544#define DPD_AUX_CH_DATA4 0x64320
3545#define DPD_AUX_CH_DATA5 0x64324
3546
3547#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3548#define DP_AUX_CH_CTL_DONE (1 << 30)
3549#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3550#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3551#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3552#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3553#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3554#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3555#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3556#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3557#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3558#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3559#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3560#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3561#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3562#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3563#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3564#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3565#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3566#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3567#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3568
3569/*
3570 * Computing GMCH M and N values for the Display Port link
3571 *
3572 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3573 *
3574 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3575 *
3576 * The GMCH value is used internally
3577 *
3578 * bytes_per_pixel is the number of bytes coming out of the plane,
3579 * which is after the LUTs, so we want the bytes for our color format.
3580 * For our current usage, this is always 3, one byte for R, G and B.
3581 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02003582#define _PIPEA_DATA_M_G4X 0x70050
3583#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07003584
3585/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003586#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02003587#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003588#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07003589
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003590#define DATA_LINK_M_N_MASK (0xffffff)
3591#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07003592
Daniel Vettere3b95f12013-05-03 11:49:49 +02003593#define _PIPEA_DATA_N_G4X 0x70054
3594#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07003595#define PIPE_GMCH_DATA_N_MASK (0xffffff)
3596
3597/*
3598 * Computing Link M and N values for the Display Port link
3599 *
3600 * Link M / N = pixel_clock / ls_clk
3601 *
3602 * (the DP spec calls pixel_clock the 'strm_clk')
3603 *
3604 * The Link value is transmitted in the Main Stream
3605 * Attributes and VB-ID.
3606 */
3607
Daniel Vettere3b95f12013-05-03 11:49:49 +02003608#define _PIPEA_LINK_M_G4X 0x70060
3609#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07003610#define PIPEA_DP_LINK_M_MASK (0xffffff)
3611
Daniel Vettere3b95f12013-05-03 11:49:49 +02003612#define _PIPEA_LINK_N_G4X 0x70064
3613#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07003614#define PIPEA_DP_LINK_N_MASK (0xffffff)
3615
Daniel Vettere3b95f12013-05-03 11:49:49 +02003616#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3617#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3618#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3619#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003620
Jesse Barnes585fb112008-07-29 11:54:06 -07003621/* Display & cursor control */
3622
3623/* Pipe A */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003624#define _PIPEADSL 0x70000
Paulo Zanoni837ba002012-05-04 17:18:14 -03003625#define DSL_LINEMASK_GEN2 0x00000fff
3626#define DSL_LINEMASK_GEN3 0x00001fff
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003627#define _PIPEACONF 0x70008
Chris Wilson5eddb702010-09-11 13:48:45 +01003628#define PIPECONF_ENABLE (1<<31)
3629#define PIPECONF_DISABLE 0
3630#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003631#define I965_PIPECONF_ACTIVE (1<<30)
Jani Nikulab6ec10b2013-08-27 15:12:15 +03003632#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
Chris Wilsonf47166d2012-03-22 15:00:50 +00003633#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01003634#define PIPECONF_SINGLE_WIDE 0
3635#define PIPECONF_PIPE_UNLOCKED 0
3636#define PIPECONF_PIPE_LOCKED (1<<25)
3637#define PIPECONF_PALETTE 0
3638#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07003639#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01003640#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03003641#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01003642/* Note that pre-gen3 does not support interlaced display directly. Panel
3643 * fitting must be disabled on pre-ilk for interlaced. */
3644#define PIPECONF_PROGRESSIVE (0 << 21)
3645#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3646#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3647#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3648#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3649/* Ironlake and later have a complete new set of values for interlaced. PFIT
3650 * means panel fitter required, PF means progressive fetch, DBL means power
3651 * saving pixel doubling. */
3652#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3653#define PIPECONF_INTERLACED_ILK (3 << 21)
3654#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3655#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02003656#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05303657#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
Jesse Barnes652c3932009-08-17 13:31:43 -07003658#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02003659#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003660#define PIPECONF_BPC_MASK (0x7 << 5)
3661#define PIPECONF_8BPC (0<<5)
3662#define PIPECONF_10BPC (1<<5)
3663#define PIPECONF_6BPC (2<<5)
3664#define PIPECONF_12BPC (3<<5)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07003665#define PIPECONF_DITHER_EN (1<<4)
3666#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3667#define PIPECONF_DITHER_TYPE_SP (0<<2)
3668#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3669#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3670#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003671#define _PIPEASTAT 0x70024
Jesse Barnes585fb112008-07-29 11:54:06 -07003672#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
Imre Deak579a9b02014-02-04 21:35:48 +02003673#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003674#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3675#define PIPE_CRC_DONE_ENABLE (1UL<<28)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003676#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
Jesse Barnes585fb112008-07-29 11:54:06 -07003677#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003678#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07003679#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3680#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3681#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3682#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02003683#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -07003684#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3685#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3686#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
Imre Deak10c59c52014-02-10 18:42:48 +02003687#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003688#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
Jesse Barnes585fb112008-07-29 11:54:06 -07003689#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3690#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003691#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnes585fb112008-07-29 11:54:06 -07003692#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003693#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07003694#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
Imre Deak579a9b02014-02-04 21:35:48 +02003695#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3696#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
Jesse Barnes585fb112008-07-29 11:54:06 -07003697#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3698#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003699#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07003700#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
Imre Deak579a9b02014-02-04 21:35:48 +02003701#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07003702#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3703#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3704#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3705#define PIPE_DPST_EVENT_STATUS (1UL<<7)
3706#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
Imre Deak10c59c52014-02-10 18:42:48 +02003707#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003708#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
Jesse Barnes585fb112008-07-29 11:54:06 -07003709#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3710#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
Imre Deak10c59c52014-02-10 18:42:48 +02003711#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003712#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
Jesse Barnes585fb112008-07-29 11:54:06 -07003713#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3714#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003715#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
Jesse Barnes585fb112008-07-29 11:54:06 -07003716#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003717#define PIPE_HBLANK_INT_STATUS (1UL<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003718#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3719
Imre Deak755e9012014-02-10 18:42:47 +02003720#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3721#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3722
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03003723#define PIPE_A_OFFSET 0x70000
3724#define PIPE_B_OFFSET 0x71000
3725#define PIPE_C_OFFSET 0x72000
3726#define CHV_PIPE_C_OFFSET 0x74000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003727/*
3728 * There's actually no pipe EDP. Some pipe registers have
3729 * simply shifted from the pipe to the transcoder, while
3730 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3731 * to access such registers in transcoder EDP.
3732 */
3733#define PIPE_EDP_OFFSET 0x7f000
3734
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003735#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3736 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3737 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003738
3739#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3740#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3741#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3742#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3743#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01003744
Paulo Zanoni756f85c2013-11-02 21:07:38 -07003745#define _PIPE_MISC_A 0x70030
3746#define _PIPE_MISC_B 0x71030
3747#define PIPEMISC_DITHER_BPC_MASK (7<<5)
3748#define PIPEMISC_DITHER_8_BPC (0<<5)
3749#define PIPEMISC_DITHER_10_BPC (1<<5)
3750#define PIPEMISC_DITHER_6_BPC (2<<5)
3751#define PIPEMISC_DITHER_12_BPC (3<<5)
3752#define PIPEMISC_DITHER_ENABLE (1<<4)
3753#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3754#define PIPEMISC_DITHER_TYPE_SP (0<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003755#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07003756
Ville Syrjäläb41fbda2013-01-24 15:29:41 +02003757#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
Jesse Barnes79831172012-06-20 10:53:12 -07003758#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003759#define PIPEB_HLINE_INT_EN (1<<28)
3760#define PIPEB_VBLANK_INT_EN (1<<27)
Imre Deak579a9b02014-02-04 21:35:48 +02003761#define SPRITED_FLIP_DONE_INT_EN (1<<26)
3762#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
3763#define PLANEB_FLIP_DONE_INT_EN (1<<24)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03003764#define PIPE_PSR_INT_EN (1<<22)
Jesse Barnes79831172012-06-20 10:53:12 -07003765#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003766#define PIPEA_HLINE_INT_EN (1<<20)
3767#define PIPEA_VBLANK_INT_EN (1<<19)
Imre Deak579a9b02014-02-04 21:35:48 +02003768#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
3769#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003770#define PLANEA_FLIPDONE_INT_EN (1<<16)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03003771#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
3772#define PIPEC_HLINE_INT_EN (1<<12)
3773#define PIPEC_VBLANK_INT_EN (1<<11)
3774#define SPRITEF_FLIPDONE_INT_EN (1<<10)
3775#define SPRITEE_FLIPDONE_INT_EN (1<<9)
3776#define PLANEC_FLIPDONE_INT_EN (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003777
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03003778#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3779#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
3780#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
3781#define PLANEC_INVALID_GTT_INT_EN (1<<25)
3782#define CURSORC_INVALID_GTT_INT_EN (1<<24)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003783#define CURSORB_INVALID_GTT_INT_EN (1<<23)
3784#define CURSORA_INVALID_GTT_INT_EN (1<<22)
3785#define SPRITED_INVALID_GTT_INT_EN (1<<21)
3786#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3787#define PLANEB_INVALID_GTT_INT_EN (1<<19)
3788#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3789#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3790#define PLANEA_INVALID_GTT_INT_EN (1<<16)
3791#define DPINVGTT_EN_MASK 0xff0000
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03003792#define DPINVGTT_EN_MASK_CHV 0xfff0000
3793#define SPRITEF_INVALID_GTT_STATUS (1<<11)
3794#define SPRITEE_INVALID_GTT_STATUS (1<<10)
3795#define PLANEC_INVALID_GTT_STATUS (1<<9)
3796#define CURSORC_INVALID_GTT_STATUS (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003797#define CURSORB_INVALID_GTT_STATUS (1<<7)
3798#define CURSORA_INVALID_GTT_STATUS (1<<6)
3799#define SPRITED_INVALID_GTT_STATUS (1<<5)
3800#define SPRITEC_INVALID_GTT_STATUS (1<<4)
3801#define PLANEB_INVALID_GTT_STATUS (1<<3)
3802#define SPRITEB_INVALID_GTT_STATUS (1<<2)
3803#define SPRITEA_INVALID_GTT_STATUS (1<<1)
3804#define PLANEA_INVALID_GTT_STATUS (1<<0)
3805#define DPINVGTT_STATUS_MASK 0xff
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03003806#define DPINVGTT_STATUS_MASK_CHV 0xfff
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003807
Jesse Barnes585fb112008-07-29 11:54:06 -07003808#define DSPARB 0x70030
3809#define DSPARB_CSTART_MASK (0x7f << 7)
3810#define DSPARB_CSTART_SHIFT 7
3811#define DSPARB_BSTART_MASK (0x7f)
3812#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08003813#define DSPARB_BEND_SHIFT 9 /* on 855 */
3814#define DSPARB_AEND_SHIFT 0
3815
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003816#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003817#define DSPFW_SR_SHIFT 23
Akshay Joshi0206e352011-08-16 15:34:10 -04003818#define DSPFW_SR_MASK (0x1ff<<23)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003819#define DSPFW_CURSORB_SHIFT 16
Zhao Yakuid4294342010-03-22 22:45:36 +08003820#define DSPFW_CURSORB_MASK (0x3f<<16)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003821#define DSPFW_PLANEB_SHIFT 8
Zhao Yakuid4294342010-03-22 22:45:36 +08003822#define DSPFW_PLANEB_MASK (0x7f<<8)
3823#define DSPFW_PLANEA_MASK (0x7f)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003824#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003825#define DSPFW_CURSORA_MASK 0x00003f00
Zhao Yakui21bd7702010-01-13 14:10:50 +00003826#define DSPFW_CURSORA_SHIFT 8
Zhao Yakuid4294342010-03-22 22:45:36 +08003827#define DSPFW_PLANEC_MASK (0x7f)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003828#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
Jesse Barnes0e442c62009-10-19 10:09:33 +09003829#define DSPFW_HPLL_SR_EN (1<<31)
3830#define DSPFW_CURSOR_SR_SHIFT 24
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003831#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Zhao Yakuid4294342010-03-22 22:45:36 +08003832#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3833#define DSPFW_HPLL_CURSOR_SHIFT 16
3834#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3835#define DSPFW_HPLL_SR_MASK (0x1ff)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003836#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
3837#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003838
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003839/* drain latency register values*/
3840#define DRAIN_LATENCY_PRECISION_32 32
3841#define DRAIN_LATENCY_PRECISION_16 16
Ville Syrjälä8f6d8ee2013-01-24 15:29:38 +02003842#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003843#define DDL_CURSORA_PRECISION_32 (1<<31)
3844#define DDL_CURSORA_PRECISION_16 (0<<31)
3845#define DDL_CURSORA_SHIFT 24
Ville Syrjäläc294c542014-04-09 13:28:13 +03003846#define DDL_SPRITEB_PRECISION_32 (1<<23)
3847#define DDL_SPRITEB_PRECISION_16 (0<<23)
3848#define DDL_SPRITEB_SHIFT 16
3849#define DDL_SPRITEA_PRECISION_32 (1<<15)
3850#define DDL_SPRITEA_PRECISION_16 (0<<15)
3851#define DDL_SPRITEA_SHIFT 8
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003852#define DDL_PLANEA_PRECISION_32 (1<<7)
3853#define DDL_PLANEA_PRECISION_16 (0<<7)
Ville Syrjäläc294c542014-04-09 13:28:13 +03003854#define DDL_PLANEA_SHIFT 0
3855
Ville Syrjälä8f6d8ee2013-01-24 15:29:38 +02003856#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003857#define DDL_CURSORB_PRECISION_32 (1<<31)
3858#define DDL_CURSORB_PRECISION_16 (0<<31)
3859#define DDL_CURSORB_SHIFT 24
Ville Syrjäläc294c542014-04-09 13:28:13 +03003860#define DDL_SPRITED_PRECISION_32 (1<<23)
3861#define DDL_SPRITED_PRECISION_16 (0<<23)
3862#define DDL_SPRITED_SHIFT 16
3863#define DDL_SPRITEC_PRECISION_32 (1<<15)
3864#define DDL_SPRITEC_PRECISION_16 (0<<15)
3865#define DDL_SPRITEC_SHIFT 8
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003866#define DDL_PLANEB_PRECISION_32 (1<<7)
3867#define DDL_PLANEB_PRECISION_16 (0<<7)
Ville Syrjäläc294c542014-04-09 13:28:13 +03003868#define DDL_PLANEB_SHIFT 0
3869
3870#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058)
3871#define DDL_CURSORC_PRECISION_32 (1<<31)
3872#define DDL_CURSORC_PRECISION_16 (0<<31)
3873#define DDL_CURSORC_SHIFT 24
3874#define DDL_SPRITEF_PRECISION_32 (1<<23)
3875#define DDL_SPRITEF_PRECISION_16 (0<<23)
3876#define DDL_SPRITEF_SHIFT 16
3877#define DDL_SPRITEE_PRECISION_32 (1<<15)
3878#define DDL_SPRITEE_PRECISION_16 (0<<15)
3879#define DDL_SPRITEE_SHIFT 8
3880#define DDL_PLANEC_PRECISION_32 (1<<7)
3881#define DDL_PLANEC_PRECISION_16 (0<<7)
3882#define DDL_PLANEC_SHIFT 0
Gajanan Bhat12a3c052012-03-28 13:39:30 -07003883
Shaohua Li7662c8b2009-06-26 11:23:55 +08003884/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09003885#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08003886#define I915_FIFO_LINE_SIZE 64
3887#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09003888
Jesse Barnesceb04242012-03-28 13:39:22 -07003889#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09003890#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08003891#define I965_FIFO_SIZE 512
3892#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08003893#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003894#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003895#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09003896
Jesse Barnesceb04242012-03-28 13:39:22 -07003897#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09003898#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08003899#define I915_MAX_WM 0x3f
3900
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003901#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3902#define PINEVIEW_FIFO_LINE_SIZE 64
3903#define PINEVIEW_MAX_WM 0x1ff
3904#define PINEVIEW_DFT_WM 0x3f
3905#define PINEVIEW_DFT_HPLLOFF_WM 0
3906#define PINEVIEW_GUARD_WM 10
3907#define PINEVIEW_CURSOR_FIFO 64
3908#define PINEVIEW_CURSOR_MAX_WM 0x3f
3909#define PINEVIEW_CURSOR_DFT_WM 0
3910#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08003911
Jesse Barnesceb04242012-03-28 13:39:22 -07003912#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003913#define I965_CURSOR_FIFO 64
3914#define I965_CURSOR_MAX_WM 32
3915#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003916
3917/* define the Watermark register on Ironlake */
3918#define WM0_PIPEA_ILK 0x45100
Ville Syrjälä1996d622013-10-09 19:18:07 +03003919#define WM0_PIPE_PLANE_MASK (0xffff<<16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003920#define WM0_PIPE_PLANE_SHIFT 16
Ville Syrjälä1996d622013-10-09 19:18:07 +03003921#define WM0_PIPE_SPRITE_MASK (0xff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003922#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03003923#define WM0_PIPE_CURSOR_MASK (0xff)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003924
3925#define WM0_PIPEB_ILK 0x45104
Jesse Barnesd6c892d2011-10-12 15:36:42 -07003926#define WM0_PIPEC_IVB 0x45200
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003927#define WM1_LP_ILK 0x45108
3928#define WM1_LP_SR_EN (1<<31)
3929#define WM1_LP_LATENCY_SHIFT 24
3930#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01003931#define WM1_LP_FBC_MASK (0xf<<20)
3932#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä416f4722013-11-02 21:07:46 -07003933#define WM1_LP_FBC_SHIFT_BDW 19
Ville Syrjälä1996d622013-10-09 19:18:07 +03003934#define WM1_LP_SR_MASK (0x7ff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003935#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03003936#define WM1_LP_CURSOR_MASK (0xff)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07003937#define WM2_LP_ILK 0x4510c
3938#define WM2_LP_EN (1<<31)
3939#define WM3_LP_ILK 0x45110
3940#define WM3_LP_EN (1<<31)
3941#define WM1S_LP_ILK 0x45120
Jesse Barnesb840d907f2011-12-13 13:19:38 -08003942#define WM2S_LP_IVB 0x45124
3943#define WM3S_LP_IVB 0x45128
Jesse Barnesdd8849c2010-09-09 11:58:02 -07003944#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003945
Paulo Zanonicca32e92013-05-31 11:45:06 -03003946#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3947 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3948 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3949
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003950/* Memory latency timer register */
3951#define MLTR_ILK 0x11222
Jesse Barnesb79d4992010-12-21 13:10:23 -08003952#define MLTR_WM1_SHIFT 0
3953#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003954/* the unit of memory self-refresh latency time is 0.5us */
3955#define ILK_SRLT_MASK 0x3f
3956
Yuanhan Liu13982612010-12-15 15:42:31 +08003957
3958/* the address where we get all kinds of latency value */
3959#define SSKPD 0x5d10
3960#define SSKPD_WM_MASK 0x3f
3961#define SSKPD_WM0_SHIFT 0
3962#define SSKPD_WM1_SHIFT 8
3963#define SSKPD_WM2_SHIFT 16
3964#define SSKPD_WM3_SHIFT 24
3965
Jesse Barnes585fb112008-07-29 11:54:06 -07003966/*
3967 * The two pipe frame counter registers are not synchronized, so
3968 * reading a stable value is somewhat tricky. The following code
3969 * should work:
3970 *
3971 * do {
3972 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3973 * PIPE_FRAME_HIGH_SHIFT;
3974 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3975 * PIPE_FRAME_LOW_SHIFT);
3976 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3977 * PIPE_FRAME_HIGH_SHIFT);
3978 * } while (high1 != high2);
3979 * frame = (high1 << 8) | low1;
3980 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03003981#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07003982#define PIPE_FRAME_HIGH_MASK 0x0000ffff
3983#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03003984#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07003985#define PIPE_FRAME_LOW_MASK 0xff000000
3986#define PIPE_FRAME_LOW_SHIFT 24
3987#define PIPE_PIXEL_MASK 0x00ffffff
3988#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08003989/* GM45+ just has to be different */
Rafael Barbalhoeb6008a2014-03-31 18:21:29 +03003990#define _PIPEA_FRMCOUNT_GM45 0x70040
3991#define _PIPEA_FLIPCOUNT_GM45 0x70044
3992#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03003993#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -07003994
3995/* Cursor A & B regs */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03003996#define _CURACNTR 0x70080
Jesse Barnes14b60392009-05-20 16:47:08 -04003997/* Old style CUR*CNTR flags (desktop 8xx) */
3998#define CURSOR_ENABLE 0x80000000
3999#define CURSOR_GAMMA_ENABLE 0x40000000
4000#define CURSOR_STRIDE_MASK 0x30000000
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004001#define CURSOR_PIPE_CSC_ENABLE (1<<24)
Jesse Barnes14b60392009-05-20 16:47:08 -04004002#define CURSOR_FORMAT_SHIFT 24
4003#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4004#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4005#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4006#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4007#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4008#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4009/* New style CUR*CNTR flags */
4010#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07004011#define CURSOR_MODE_DISABLE 0x00
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304012#define CURSOR_MODE_128_32B_AX 0x02
4013#define CURSOR_MODE_256_32B_AX 0x03
Jesse Barnes585fb112008-07-29 11:54:06 -07004014#define CURSOR_MODE_64_32B_AX 0x07
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304015#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4016#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
Jesse Barnes585fb112008-07-29 11:54:06 -07004017#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Jesse Barnes14b60392009-05-20 16:47:08 -04004018#define MCURSOR_PIPE_SELECT (1 << 28)
4019#define MCURSOR_PIPE_A 0x00
4020#define MCURSOR_PIPE_B (1 << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07004021#define MCURSOR_GAMMA_ENABLE (1 << 26)
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03004022#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004023#define _CURABASE 0x70084
4024#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07004025#define CURSOR_POS_MASK 0x007FF
4026#define CURSOR_POS_SIGN 0x8000
4027#define CURSOR_X_SHIFT 0
4028#define CURSOR_Y_SHIFT 16
Jesse Barnes14b60392009-05-20 16:47:08 -04004029#define CURSIZE 0x700a0
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004030#define _CURBCNTR 0x700c0
4031#define _CURBBASE 0x700c4
4032#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07004033
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004034#define _CURBCNTR_IVB 0x71080
4035#define _CURBBASE_IVB 0x71084
4036#define _CURBPOS_IVB 0x71088
4037
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004038#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4039 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4040 dev_priv->info.display_mmio_offset)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00004041
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004042#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4043#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4044#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4045
4046#define CURSOR_A_OFFSET 0x70080
4047#define CURSOR_B_OFFSET 0x700c0
4048#define CHV_CURSOR_C_OFFSET 0x700e0
4049#define IVB_CURSOR_B_OFFSET 0x71080
4050#define IVB_CURSOR_C_OFFSET 0x72080
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004051
Jesse Barnes585fb112008-07-29 11:54:06 -07004052/* Display A control */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004053#define _DSPACNTR 0x70180
Jesse Barnes585fb112008-07-29 11:54:06 -07004054#define DISPLAY_PLANE_ENABLE (1<<31)
4055#define DISPLAY_PLANE_DISABLE 0
4056#define DISPPLANE_GAMMA_ENABLE (1<<30)
4057#define DISPPLANE_GAMMA_DISABLE 0
4058#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004059#define DISPPLANE_YUV422 (0x0<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004060#define DISPPLANE_8BPP (0x2<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004061#define DISPPLANE_BGRA555 (0x3<<26)
4062#define DISPPLANE_BGRX555 (0x4<<26)
4063#define DISPPLANE_BGRX565 (0x5<<26)
4064#define DISPPLANE_BGRX888 (0x6<<26)
4065#define DISPPLANE_BGRA888 (0x7<<26)
4066#define DISPPLANE_RGBX101010 (0x8<<26)
4067#define DISPPLANE_RGBA101010 (0x9<<26)
4068#define DISPPLANE_BGRX101010 (0xa<<26)
4069#define DISPPLANE_RGBX161616 (0xc<<26)
4070#define DISPPLANE_RGBX888 (0xe<<26)
4071#define DISPPLANE_RGBA888 (0xf<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004072#define DISPPLANE_STEREO_ENABLE (1<<25)
4073#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004074#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb24e7172011-01-04 15:09:30 -08004075#define DISPPLANE_SEL_PIPE_SHIFT 24
4076#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004077#define DISPPLANE_SEL_PIPE_A 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08004078#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004079#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4080#define DISPPLANE_SRC_KEY_DISABLE 0
4081#define DISPPLANE_LINE_DOUBLE (1<<20)
4082#define DISPPLANE_NO_LINE_DOUBLE 0
4083#define DISPPLANE_STEREO_POLARITY_FIRST 0
4084#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004085#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07004086#define DISPPLANE_TILED (1<<10)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004087#define _DSPAADDR 0x70184
4088#define _DSPASTRIDE 0x70188
4089#define _DSPAPOS 0x7018C /* reserved */
4090#define _DSPASIZE 0x70190
4091#define _DSPASURF 0x7019C /* 965+ only */
4092#define _DSPATILEOFF 0x701A4 /* 965+ only */
4093#define _DSPAOFFSET 0x701A4 /* HSW */
4094#define _DSPASURFLIVE 0x701AC
Jesse Barnes585fb112008-07-29 11:54:06 -07004095
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004096#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4097#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4098#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4099#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4100#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4101#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4102#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
Daniel Vettere506a0c2012-07-05 12:17:29 +02004103#define DSPLINOFF(plane) DSPADDR(plane)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004104#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4105#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
Chris Wilson5eddb702010-09-11 13:48:45 +01004106
Armin Reese446f2542012-03-30 16:20:16 -07004107/* Display/Sprite base address macros */
4108#define DISP_BASEADDR_MASK (0xfffff000)
4109#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
4110#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
Armin Reese446f2542012-03-30 16:20:16 -07004111
Jesse Barnes585fb112008-07-29 11:54:06 -07004112/* VBIOS flags */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004113#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4114#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4115#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4116#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4117#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4118#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4119#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4120#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4121#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4122#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4123#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4124#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4125#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
Jesse Barnes585fb112008-07-29 11:54:06 -07004126
4127/* Pipe B */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004128#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4129#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4130#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004131#define _PIPEBFRAMEHIGH 0x71040
4132#define _PIPEBFRAMEPIXEL 0x71044
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004133#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4134#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08004135
Jesse Barnes585fb112008-07-29 11:54:06 -07004136
4137/* Display B control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004138#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
Jesse Barnes585fb112008-07-29 11:54:06 -07004139#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
4140#define DISPPLANE_ALPHA_TRANS_DISABLE 0
4141#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
4142#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004143#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4144#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4145#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4146#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4147#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4148#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4149#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4150#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07004151
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004152/* Sprite A control */
4153#define _DVSACNTR 0x72180
4154#define DVS_ENABLE (1<<31)
4155#define DVS_GAMMA_ENABLE (1<<30)
4156#define DVS_PIXFORMAT_MASK (3<<25)
4157#define DVS_FORMAT_YUV422 (0<<25)
4158#define DVS_FORMAT_RGBX101010 (1<<25)
4159#define DVS_FORMAT_RGBX888 (2<<25)
4160#define DVS_FORMAT_RGBX161616 (3<<25)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004161#define DVS_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004162#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08004163#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004164#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
4165#define DVS_YUV_ORDER_YUYV (0<<16)
4166#define DVS_YUV_ORDER_UYVY (1<<16)
4167#define DVS_YUV_ORDER_YVYU (2<<16)
4168#define DVS_YUV_ORDER_VYUY (3<<16)
4169#define DVS_DEST_KEY (1<<2)
4170#define DVS_TRICKLE_FEED_DISABLE (1<<14)
4171#define DVS_TILED (1<<10)
4172#define _DVSALINOFF 0x72184
4173#define _DVSASTRIDE 0x72188
4174#define _DVSAPOS 0x7218c
4175#define _DVSASIZE 0x72190
4176#define _DVSAKEYVAL 0x72194
4177#define _DVSAKEYMSK 0x72198
4178#define _DVSASURF 0x7219c
4179#define _DVSAKEYMAXVAL 0x721a0
4180#define _DVSATILEOFF 0x721a4
4181#define _DVSASURFLIVE 0x721ac
4182#define _DVSASCALE 0x72204
4183#define DVS_SCALE_ENABLE (1<<31)
4184#define DVS_FILTER_MASK (3<<29)
4185#define DVS_FILTER_MEDIUM (0<<29)
4186#define DVS_FILTER_ENHANCING (1<<29)
4187#define DVS_FILTER_SOFTENING (2<<29)
4188#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4189#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
4190#define _DVSAGAMC 0x72300
4191
4192#define _DVSBCNTR 0x73180
4193#define _DVSBLINOFF 0x73184
4194#define _DVSBSTRIDE 0x73188
4195#define _DVSBPOS 0x7318c
4196#define _DVSBSIZE 0x73190
4197#define _DVSBKEYVAL 0x73194
4198#define _DVSBKEYMSK 0x73198
4199#define _DVSBSURF 0x7319c
4200#define _DVSBKEYMAXVAL 0x731a0
4201#define _DVSBTILEOFF 0x731a4
4202#define _DVSBSURFLIVE 0x731ac
4203#define _DVSBSCALE 0x73204
4204#define _DVSBGAMC 0x73300
4205
4206#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4207#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4208#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4209#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4210#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08004211#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004212#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4213#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4214#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08004215#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4216#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004217#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004218
4219#define _SPRA_CTL 0x70280
4220#define SPRITE_ENABLE (1<<31)
4221#define SPRITE_GAMMA_ENABLE (1<<30)
4222#define SPRITE_PIXFORMAT_MASK (7<<25)
4223#define SPRITE_FORMAT_YUV422 (0<<25)
4224#define SPRITE_FORMAT_RGBX101010 (1<<25)
4225#define SPRITE_FORMAT_RGBX888 (2<<25)
4226#define SPRITE_FORMAT_RGBX161616 (3<<25)
4227#define SPRITE_FORMAT_YUV444 (4<<25)
4228#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004229#define SPRITE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004230#define SPRITE_SOURCE_KEY (1<<22)
4231#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
4232#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
4233#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
4234#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
4235#define SPRITE_YUV_ORDER_YUYV (0<<16)
4236#define SPRITE_YUV_ORDER_UYVY (1<<16)
4237#define SPRITE_YUV_ORDER_YVYU (2<<16)
4238#define SPRITE_YUV_ORDER_VYUY (3<<16)
4239#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
4240#define SPRITE_INT_GAMMA_ENABLE (1<<13)
4241#define SPRITE_TILED (1<<10)
4242#define SPRITE_DEST_KEY (1<<2)
4243#define _SPRA_LINOFF 0x70284
4244#define _SPRA_STRIDE 0x70288
4245#define _SPRA_POS 0x7028c
4246#define _SPRA_SIZE 0x70290
4247#define _SPRA_KEYVAL 0x70294
4248#define _SPRA_KEYMSK 0x70298
4249#define _SPRA_SURF 0x7029c
4250#define _SPRA_KEYMAX 0x702a0
4251#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01004252#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004253#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004254#define _SPRA_SCALE 0x70304
4255#define SPRITE_SCALE_ENABLE (1<<31)
4256#define SPRITE_FILTER_MASK (3<<29)
4257#define SPRITE_FILTER_MEDIUM (0<<29)
4258#define SPRITE_FILTER_ENHANCING (1<<29)
4259#define SPRITE_FILTER_SOFTENING (2<<29)
4260#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4261#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
4262#define _SPRA_GAMC 0x70400
4263
4264#define _SPRB_CTL 0x71280
4265#define _SPRB_LINOFF 0x71284
4266#define _SPRB_STRIDE 0x71288
4267#define _SPRB_POS 0x7128c
4268#define _SPRB_SIZE 0x71290
4269#define _SPRB_KEYVAL 0x71294
4270#define _SPRB_KEYMSK 0x71298
4271#define _SPRB_SURF 0x7129c
4272#define _SPRB_KEYMAX 0x712a0
4273#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01004274#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004275#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004276#define _SPRB_SCALE 0x71304
4277#define _SPRB_GAMC 0x71400
4278
4279#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4280#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4281#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4282#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
4283#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4284#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4285#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4286#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4287#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4288#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
Damien Lespiauc54173a2012-10-26 18:20:11 +01004289#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004290#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4291#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004292#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004293
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004294#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004295#define SP_ENABLE (1<<31)
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -08004296#define SP_GAMMA_ENABLE (1<<30)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004297#define SP_PIXFORMAT_MASK (0xf<<26)
4298#define SP_FORMAT_YUV422 (0<<26)
4299#define SP_FORMAT_BGR565 (5<<26)
4300#define SP_FORMAT_BGRX8888 (6<<26)
4301#define SP_FORMAT_BGRA8888 (7<<26)
4302#define SP_FORMAT_RGBX1010102 (8<<26)
4303#define SP_FORMAT_RGBA1010102 (9<<26)
4304#define SP_FORMAT_RGBX8888 (0xe<<26)
4305#define SP_FORMAT_RGBA8888 (0xf<<26)
4306#define SP_SOURCE_KEY (1<<22)
4307#define SP_YUV_BYTE_ORDER_MASK (3<<16)
4308#define SP_YUV_ORDER_YUYV (0<<16)
4309#define SP_YUV_ORDER_UYVY (1<<16)
4310#define SP_YUV_ORDER_YVYU (2<<16)
4311#define SP_YUV_ORDER_VYUY (3<<16)
4312#define SP_TILED (1<<10)
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004313#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4314#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4315#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4316#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4317#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4318#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4319#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4320#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4321#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4322#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
4323#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004324
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004325#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4326#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4327#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4328#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4329#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4330#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4331#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4332#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4333#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4334#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4335#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4336#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004337
4338#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
4339#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
4340#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
4341#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
4342#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
4343#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
4344#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
4345#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
4346#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4347#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4348#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4349#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
4350
Jesse Barnes585fb112008-07-29 11:54:06 -07004351/* VBIOS regs */
4352#define VGACNTRL 0x71400
4353# define VGA_DISP_DISABLE (1 << 31)
4354# define VGA_2X_MODE (1 << 30)
4355# define VGA_PIPE_B_SELECT (1 << 29)
4356
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02004357#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
4358
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004359/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004360
4361#define CPU_VGACNTRL 0x41000
4362
4363#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
4364#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
4365#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
4366#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
4367#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
4368#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
4369#define DIGITAL_PORTA_NO_DETECT (0 << 0)
4370#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
4371#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
4372
4373/* refresh rate hardware control */
4374#define RR_HW_CTL 0x45300
4375#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
4376#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
4377
4378#define FDI_PLL_BIOS_0 0x46000
Chris Wilson021357a2010-09-07 20:54:59 +01004379#define FDI_PLL_FB_CLOCK_MASK 0xff
Zhenyu Wangb9055052009-06-05 15:38:38 +08004380#define FDI_PLL_BIOS_1 0x46004
4381#define FDI_PLL_BIOS_2 0x46008
4382#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
4383#define DISPLAY_PORT_PLL_BIOS_1 0x46010
4384#define DISPLAY_PORT_PLL_BIOS_2 0x46014
4385
Eric Anholt8956c8b2010-03-18 13:21:14 -07004386#define PCH_3DCGDIS0 0x46020
4387# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
4388# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
4389
Eric Anholt06f37752010-12-14 10:06:46 -08004390#define PCH_3DCGDIS1 0x46024
4391# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
4392
Zhenyu Wangb9055052009-06-05 15:38:38 +08004393#define FDI_PLL_FREQ_CTL 0x46030
4394#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
4395#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
4396#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
4397
4398
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004399#define _PIPEA_DATA_M1 0x60030
Chris Wilson5eddb702010-09-11 13:48:45 +01004400#define PIPE_DATA_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004401#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01004402#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004403
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004404#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01004405#define PIPE_DATA_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004406#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01004407#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004408
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004409#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01004410#define PIPE_LINK_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004411#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01004412#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004413
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004414#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01004415#define PIPE_LINK_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004416#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01004417#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004418
4419/* PIPEB timing regs are same start from 0x61000 */
4420
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004421#define _PIPEB_DATA_M1 0x61030
4422#define _PIPEB_DATA_N1 0x61034
4423#define _PIPEB_DATA_M2 0x61038
4424#define _PIPEB_DATA_N2 0x6103c
4425#define _PIPEB_LINK_M1 0x61040
4426#define _PIPEB_LINK_N1 0x61044
4427#define _PIPEB_LINK_M2 0x61048
4428#define _PIPEB_LINK_N2 0x6104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08004429
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004430#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
4431#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
4432#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
4433#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
4434#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
4435#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
4436#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
4437#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004438
4439/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004440/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
4441#define _PFA_CTL_1 0x68080
4442#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08004443#define PF_ENABLE (1<<31)
Paulo Zanoni13888d72012-11-20 13:27:41 -02004444#define PF_PIPE_SEL_MASK_IVB (3<<29)
4445#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08004446#define PF_FILTER_MASK (3<<23)
4447#define PF_FILTER_PROGRAMMED (0<<23)
4448#define PF_FILTER_MED_3x3 (1<<23)
4449#define PF_FILTER_EDGE_ENHANCE (2<<23)
4450#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004451#define _PFA_WIN_SZ 0x68074
4452#define _PFB_WIN_SZ 0x68874
4453#define _PFA_WIN_POS 0x68070
4454#define _PFB_WIN_POS 0x68870
4455#define _PFA_VSCALE 0x68084
4456#define _PFB_VSCALE 0x68884
4457#define _PFA_HSCALE 0x68090
4458#define _PFB_HSCALE 0x68890
4459
4460#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4461#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4462#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4463#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4464#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004465
4466/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004467#define _LGC_PALETTE_A 0x4a000
4468#define _LGC_PALETTE_B 0x4a800
4469#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004470
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004471#define _GAMMA_MODE_A 0x4a480
4472#define _GAMMA_MODE_B 0x4ac80
4473#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4474#define GAMMA_MODE_MODE_MASK (3 << 0)
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02004475#define GAMMA_MODE_MODE_8BIT (0 << 0)
4476#define GAMMA_MODE_MODE_10BIT (1 << 0)
4477#define GAMMA_MODE_MODE_12BIT (2 << 0)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004478#define GAMMA_MODE_MODE_SPLIT (3 << 0)
4479
Zhenyu Wangb9055052009-06-05 15:38:38 +08004480/* interrupts */
4481#define DE_MASTER_IRQ_CONTROL (1 << 31)
4482#define DE_SPRITEB_FLIP_DONE (1 << 29)
4483#define DE_SPRITEA_FLIP_DONE (1 << 28)
4484#define DE_PLANEB_FLIP_DONE (1 << 27)
4485#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004486#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004487#define DE_PCU_EVENT (1 << 25)
4488#define DE_GTT_FAULT (1 << 24)
4489#define DE_POISON (1 << 23)
4490#define DE_PERFORM_COUNTER (1 << 22)
4491#define DE_PCH_EVENT (1 << 21)
4492#define DE_AUX_CHANNEL_A (1 << 20)
4493#define DE_DP_A_HOTPLUG (1 << 19)
4494#define DE_GSE (1 << 18)
4495#define DE_PIPEB_VBLANK (1 << 15)
4496#define DE_PIPEB_EVEN_FIELD (1 << 14)
4497#define DE_PIPEB_ODD_FIELD (1 << 13)
4498#define DE_PIPEB_LINE_COMPARE (1 << 12)
4499#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02004500#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004501#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4502#define DE_PIPEA_VBLANK (1 << 7)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004503#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004504#define DE_PIPEA_EVEN_FIELD (1 << 6)
4505#define DE_PIPEA_ODD_FIELD (1 << 5)
4506#define DE_PIPEA_LINE_COMPARE (1 << 4)
4507#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02004508#define DE_PIPEA_CRC_DONE (1 << 2)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004509#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004510#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004511#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004512
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004513/* More Ivybridge lolz */
Paulo Zanoni86642812013-04-12 17:57:57 -03004514#define DE_ERR_INT_IVB (1<<30)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004515#define DE_GSE_IVB (1<<29)
4516#define DE_PCH_EVENT_IVB (1<<28)
4517#define DE_DP_A_HOTPLUG_IVB (1<<27)
4518#define DE_AUX_CHANNEL_A_IVB (1<<26)
Chris Wilsonb615b572012-05-02 09:52:12 +01004519#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
4520#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
4521#define DE_PIPEC_VBLANK_IVB (1<<10)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004522#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004523#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004524#define DE_PIPEB_VBLANK_IVB (1<<5)
Chris Wilsonb615b572012-05-02 09:52:12 +01004525#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
4526#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004527#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004528#define DE_PIPEA_VBLANK_IVB (1<<0)
Paulo Zanonib5184212013-07-12 20:00:08 -03004529#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4530
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07004531#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
4532#define MASTER_INTERRUPT_ENABLE (1<<31)
4533
Zhenyu Wangb9055052009-06-05 15:38:38 +08004534#define DEISR 0x44000
4535#define DEIMR 0x44004
4536#define DEIIR 0x44008
4537#define DEIER 0x4400c
4538
Zhenyu Wangb9055052009-06-05 15:38:38 +08004539#define GTISR 0x44010
4540#define GTIMR 0x44014
4541#define GTIIR 0x44018
4542#define GTIER 0x4401c
4543
Ben Widawskyabd58f02013-11-02 21:07:09 -07004544#define GEN8_MASTER_IRQ 0x44200
4545#define GEN8_MASTER_IRQ_CONTROL (1<<31)
4546#define GEN8_PCU_IRQ (1<<30)
4547#define GEN8_DE_PCH_IRQ (1<<23)
4548#define GEN8_DE_MISC_IRQ (1<<22)
4549#define GEN8_DE_PORT_IRQ (1<<20)
4550#define GEN8_DE_PIPE_C_IRQ (1<<18)
4551#define GEN8_DE_PIPE_B_IRQ (1<<17)
4552#define GEN8_DE_PIPE_A_IRQ (1<<16)
Daniel Vetterc42664c2013-11-07 11:05:40 +01004553#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
Ben Widawskyabd58f02013-11-02 21:07:09 -07004554#define GEN8_GT_VECS_IRQ (1<<6)
Ben Widawsky09610212014-05-15 20:58:08 +03004555#define GEN8_GT_PM_IRQ (1<<4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004556#define GEN8_GT_VCS2_IRQ (1<<3)
4557#define GEN8_GT_VCS1_IRQ (1<<2)
4558#define GEN8_GT_BCS_IRQ (1<<1)
4559#define GEN8_GT_RCS_IRQ (1<<0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004560
4561#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
4562#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
4563#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
4564#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
4565
4566#define GEN8_BCS_IRQ_SHIFT 16
4567#define GEN8_RCS_IRQ_SHIFT 0
4568#define GEN8_VCS2_IRQ_SHIFT 16
4569#define GEN8_VCS1_IRQ_SHIFT 0
4570#define GEN8_VECS_IRQ_SHIFT 0
4571
4572#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
4573#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
4574#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
4575#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
Daniel Vetter38d83c962013-11-07 11:05:46 +01004576#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004577#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4578#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4579#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4580#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4581#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4582#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
Damien Lespiaud0e1f1c2014-04-08 01:22:44 +01004583#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004584#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4585#define GEN8_PIPE_VSYNC (1 << 1)
4586#define GEN8_PIPE_VBLANK (1 << 0)
Daniel Vetter30100f22013-11-07 14:49:24 +01004587#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4588 (GEN8_PIPE_CURSOR_FAULT | \
4589 GEN8_PIPE_SPRITE_FAULT | \
4590 GEN8_PIPE_PRIMARY_FAULT)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004591
4592#define GEN8_DE_PORT_ISR 0x44440
4593#define GEN8_DE_PORT_IMR 0x44444
4594#define GEN8_DE_PORT_IIR 0x44448
4595#define GEN8_DE_PORT_IER 0x4444c
Daniel Vetter6d766f02013-11-07 14:49:55 +01004596#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
4597#define GEN8_AUX_CHANNEL_A (1 << 0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004598
4599#define GEN8_DE_MISC_ISR 0x44460
4600#define GEN8_DE_MISC_IMR 0x44464
4601#define GEN8_DE_MISC_IIR 0x44468
4602#define GEN8_DE_MISC_IER 0x4446c
4603#define GEN8_DE_MISC_GSE (1 << 27)
4604
4605#define GEN8_PCU_ISR 0x444e0
4606#define GEN8_PCU_IMR 0x444e4
4607#define GEN8_PCU_IIR 0x444e8
4608#define GEN8_PCU_IER 0x444ec
4609
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004610#define ILK_DISPLAY_CHICKEN2 0x42004
Eric Anholt67e92af2010-11-06 14:53:33 -07004611/* Required on all Ironlake and Sandybridge according to the B-Spec. */
4612#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004613#define ILK_DPARB_GATE (1<<22)
4614#define ILK_VSDPFD_FULL (1<<21)
Damien Lespiaue3589902014-02-07 19:12:50 +00004615#define FUSE_STRAP 0x42014
4616#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
4617#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
4618#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
4619#define ILK_HDCP_DISABLE (1 << 25)
4620#define ILK_eDP_A_DISABLE (1 << 24)
4621#define HSW_CDCLK_LIMIT (1 << 24)
4622#define ILK_DESKTOP (1 << 23)
Yuanhan Liu13982612010-12-15 15:42:31 +08004623
Damien Lespiau231e54f2012-10-19 17:55:41 +01004624#define ILK_DSPCLK_GATE_D 0x42020
4625#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
4626#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
4627#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
4628#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
4629#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004630
Eric Anholt116ac8d2011-12-21 10:31:09 -08004631#define IVB_CHICKEN3 0x4200c
4632# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
4633# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
4634
Paulo Zanoni90a88642013-05-03 17:23:45 -03004635#define CHICKEN_PAR1_1 0x42080
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07004636#define DPA_MASK_VBLANK_SRD (1 << 15)
Paulo Zanoni90a88642013-05-03 17:23:45 -03004637#define FORCE_ARB_IDLE_PLANES (1 << 14)
4638
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07004639#define _CHICKEN_PIPESL_1_A 0x420b0
4640#define _CHICKEN_PIPESL_1_B 0x420b4
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02004641#define HSW_FBCQ_DIS (1 << 22)
4642#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07004643#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4644
Zhenyu Wang553bd142009-09-02 10:57:52 +08004645#define DISP_ARB_CTL 0x45000
4646#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004647#define DISP_FBC_WM_DIS (1<<15)
Ville Syrjäläac9545f2013-12-05 15:51:28 +02004648#define DISP_ARB_CTL2 0x45004
4649#define DISP_DATA_PARTITION_5_6 (1<<6)
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07004650#define GEN7_MSG_CTL 0x45010
4651#define WAIT_FOR_PCH_RESET_ACK (1<<1)
4652#define WAIT_FOR_PCH_FLR_ACK (1<<0)
Daniel Vetter6ba844b2014-01-22 23:39:30 +01004653#define HSW_NDE_RSTWRN_OPT 0x46408
4654#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
Zhenyu Wang553bd142009-09-02 10:57:52 +08004655
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004656/* GEN7 chicken */
Kenneth Graunked71de142012-02-08 12:53:52 -08004657#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
4658# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
Ben Widawskya75f3622013-11-02 21:07:59 -07004659#define COMMON_SLICE_CHICKEN2 0x7014
4660# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
Kenneth Graunked71de142012-02-08 12:53:52 -08004661
Ville Syrjälä031994e2014-01-22 21:32:46 +02004662#define GEN7_L3SQCREG1 0xB010
4663#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
4664
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004665#define GEN7_L3CNTLREG1 0xB01C
Chris Wilson1af84522014-02-14 22:34:43 +00004666#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
Jesse Barnesd0cf5ea2012-10-25 12:15:41 -07004667#define GEN7_L3AGDIS (1<<19)
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004668
4669#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
4670#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
4671
Jesse Barnes61939d92012-10-02 17:43:38 -05004672#define GEN7_L3SQCREG4 0xb034
4673#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
4674
Ben Widawsky63801f22013-12-12 17:26:03 -08004675/* GEN8 chicken */
4676#define HDC_CHICKEN0 0x7300
4677#define HDC_FORCE_NON_COHERENT (1<<4)
4678
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08004679/* WaCatErrorRejectionIssue */
4680#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
4681#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
4682
Francisco Jerezf3fc4882013-10-02 15:53:16 -07004683#define HSW_SCRATCH1 0xb038
4684#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4685
Zhenyu Wangb9055052009-06-05 15:38:38 +08004686/* PCH */
4687
Adam Jackson23e81d62012-06-06 15:45:44 -04004688/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08004689#define SDE_AUDIO_POWER_D (1 << 27)
4690#define SDE_AUDIO_POWER_C (1 << 26)
4691#define SDE_AUDIO_POWER_B (1 << 25)
4692#define SDE_AUDIO_POWER_SHIFT (25)
4693#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4694#define SDE_GMBUS (1 << 24)
4695#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4696#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4697#define SDE_AUDIO_HDCP_MASK (3 << 22)
4698#define SDE_AUDIO_TRANSB (1 << 21)
4699#define SDE_AUDIO_TRANSA (1 << 20)
4700#define SDE_AUDIO_TRANS_MASK (3 << 20)
4701#define SDE_POISON (1 << 19)
4702/* 18 reserved */
4703#define SDE_FDI_RXB (1 << 17)
4704#define SDE_FDI_RXA (1 << 16)
4705#define SDE_FDI_MASK (3 << 16)
4706#define SDE_AUXD (1 << 15)
4707#define SDE_AUXC (1 << 14)
4708#define SDE_AUXB (1 << 13)
4709#define SDE_AUX_MASK (7 << 13)
4710/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004711#define SDE_CRT_HOTPLUG (1 << 11)
4712#define SDE_PORTD_HOTPLUG (1 << 10)
4713#define SDE_PORTC_HOTPLUG (1 << 9)
4714#define SDE_PORTB_HOTPLUG (1 << 8)
4715#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05004716#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4717 SDE_SDVOB_HOTPLUG | \
4718 SDE_PORTB_HOTPLUG | \
4719 SDE_PORTC_HOTPLUG | \
4720 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08004721#define SDE_TRANSB_CRC_DONE (1 << 5)
4722#define SDE_TRANSB_CRC_ERR (1 << 4)
4723#define SDE_TRANSB_FIFO_UNDER (1 << 3)
4724#define SDE_TRANSA_CRC_DONE (1 << 2)
4725#define SDE_TRANSA_CRC_ERR (1 << 1)
4726#define SDE_TRANSA_FIFO_UNDER (1 << 0)
4727#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04004728
4729/* south display engine interrupt: CPT/PPT */
4730#define SDE_AUDIO_POWER_D_CPT (1 << 31)
4731#define SDE_AUDIO_POWER_C_CPT (1 << 30)
4732#define SDE_AUDIO_POWER_B_CPT (1 << 29)
4733#define SDE_AUDIO_POWER_SHIFT_CPT 29
4734#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4735#define SDE_AUXD_CPT (1 << 27)
4736#define SDE_AUXC_CPT (1 << 26)
4737#define SDE_AUXB_CPT (1 << 25)
4738#define SDE_AUX_MASK_CPT (7 << 25)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004739#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4740#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4741#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04004742#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01004743#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01004744#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01004745 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01004746 SDE_PORTD_HOTPLUG_CPT | \
4747 SDE_PORTC_HOTPLUG_CPT | \
4748 SDE_PORTB_HOTPLUG_CPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04004749#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03004750#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04004751#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4752#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4753#define SDE_FDI_RXC_CPT (1 << 8)
4754#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4755#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4756#define SDE_FDI_RXB_CPT (1 << 4)
4757#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4758#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4759#define SDE_FDI_RXA_CPT (1 << 0)
4760#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4761 SDE_AUDIO_CP_REQ_B_CPT | \
4762 SDE_AUDIO_CP_REQ_A_CPT)
4763#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4764 SDE_AUDIO_CP_CHG_B_CPT | \
4765 SDE_AUDIO_CP_CHG_A_CPT)
4766#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4767 SDE_FDI_RXB_CPT | \
4768 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004769
4770#define SDEISR 0xc4000
4771#define SDEIMR 0xc4004
4772#define SDEIIR 0xc4008
4773#define SDEIER 0xc400c
4774
Paulo Zanoni86642812013-04-12 17:57:57 -03004775#define SERR_INT 0xc4040
Paulo Zanonide032bf2013-04-12 17:57:58 -03004776#define SERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03004777#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
4778#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
4779#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
Daniel Vetter1dd246f2013-07-10 08:30:23 +02004780#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03004781
Zhenyu Wangb9055052009-06-05 15:38:38 +08004782/* digital port hotplug */
Keith Packard7fe0b972011-09-19 13:31:02 -07004783#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004784#define PORTD_HOTPLUG_ENABLE (1 << 20)
4785#define PORTD_PULSE_DURATION_2ms (0)
4786#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
4787#define PORTD_PULSE_DURATION_6ms (2 << 18)
4788#define PORTD_PULSE_DURATION_100ms (3 << 18)
Keith Packard7fe0b972011-09-19 13:31:02 -07004789#define PORTD_PULSE_DURATION_MASK (3 << 18)
Damien Lespiaub6965192012-12-13 16:08:59 +00004790#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
4791#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4792#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4793#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004794#define PORTC_HOTPLUG_ENABLE (1 << 12)
4795#define PORTC_PULSE_DURATION_2ms (0)
4796#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
4797#define PORTC_PULSE_DURATION_6ms (2 << 10)
4798#define PORTC_PULSE_DURATION_100ms (3 << 10)
Keith Packard7fe0b972011-09-19 13:31:02 -07004799#define PORTC_PULSE_DURATION_MASK (3 << 10)
Damien Lespiaub6965192012-12-13 16:08:59 +00004800#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
4801#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4802#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4803#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004804#define PORTB_HOTPLUG_ENABLE (1 << 4)
4805#define PORTB_PULSE_DURATION_2ms (0)
4806#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
4807#define PORTB_PULSE_DURATION_6ms (2 << 2)
4808#define PORTB_PULSE_DURATION_100ms (3 << 2)
Keith Packard7fe0b972011-09-19 13:31:02 -07004809#define PORTB_PULSE_DURATION_MASK (3 << 2)
Damien Lespiaub6965192012-12-13 16:08:59 +00004810#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
4811#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4812#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4813#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004814
4815#define PCH_GPIOA 0xc5010
4816#define PCH_GPIOB 0xc5014
4817#define PCH_GPIOC 0xc5018
4818#define PCH_GPIOD 0xc501c
4819#define PCH_GPIOE 0xc5020
4820#define PCH_GPIOF 0xc5024
4821
Eric Anholtf0217c42009-12-01 11:56:30 -08004822#define PCH_GMBUS0 0xc5100
4823#define PCH_GMBUS1 0xc5104
4824#define PCH_GMBUS2 0xc5108
4825#define PCH_GMBUS3 0xc510c
4826#define PCH_GMBUS4 0xc5110
4827#define PCH_GMBUS5 0xc5120
4828
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004829#define _PCH_DPLL_A 0xc6014
4830#define _PCH_DPLL_B 0xc6018
Daniel Vettere9a632a2013-06-05 13:34:13 +02004831#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004832
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004833#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00004834#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004835#define _PCH_FPA1 0xc6044
4836#define _PCH_FPB0 0xc6048
4837#define _PCH_FPB1 0xc604c
Daniel Vettere9a632a2013-06-05 13:34:13 +02004838#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4839#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004840
4841#define PCH_DPLL_TEST 0xc606c
4842
4843#define PCH_DREF_CONTROL 0xC6200
4844#define DREF_CONTROL_MASK 0x7fc3
4845#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4846#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
4847#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
4848#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
4849#define DREF_SSC_SOURCE_DISABLE (0<<11)
4850#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08004851#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004852#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
4853#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
4854#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08004855#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004856#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
4857#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08004858#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004859#define DREF_SSC4_DOWNSPREAD (0<<6)
4860#define DREF_SSC4_CENTERSPREAD (1<<6)
4861#define DREF_SSC1_DISABLE (0<<1)
4862#define DREF_SSC1_ENABLE (1<<1)
4863#define DREF_SSC4_DISABLE (0)
4864#define DREF_SSC4_ENABLE (1)
4865
4866#define PCH_RAWCLK_FREQ 0xc6204
4867#define FDL_TP1_TIMER_SHIFT 12
4868#define FDL_TP1_TIMER_MASK (3<<12)
4869#define FDL_TP2_TIMER_SHIFT 10
4870#define FDL_TP2_TIMER_MASK (3<<10)
4871#define RAWCLK_FREQ_MASK 0x3ff
4872
4873#define PCH_DPLL_TMR_CFG 0xc6208
4874
4875#define PCH_SSC4_PARMS 0xc6210
4876#define PCH_SSC4_AUX_PARMS 0xc6214
4877
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004878#define PCH_DPLL_SEL 0xc7000
Daniel Vetter11887392013-06-05 13:34:09 +02004879#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
4880#define TRANS_DPLLA_SEL(pipe) 0
4881#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004882
Zhenyu Wangb9055052009-06-05 15:38:38 +08004883/* transcoder */
4884
Daniel Vetter275f01b22013-05-03 11:49:47 +02004885#define _PCH_TRANS_HTOTAL_A 0xe0000
4886#define TRANS_HTOTAL_SHIFT 16
4887#define TRANS_HACTIVE_SHIFT 0
4888#define _PCH_TRANS_HBLANK_A 0xe0004
4889#define TRANS_HBLANK_END_SHIFT 16
4890#define TRANS_HBLANK_START_SHIFT 0
4891#define _PCH_TRANS_HSYNC_A 0xe0008
4892#define TRANS_HSYNC_END_SHIFT 16
4893#define TRANS_HSYNC_START_SHIFT 0
4894#define _PCH_TRANS_VTOTAL_A 0xe000c
4895#define TRANS_VTOTAL_SHIFT 16
4896#define TRANS_VACTIVE_SHIFT 0
4897#define _PCH_TRANS_VBLANK_A 0xe0010
4898#define TRANS_VBLANK_END_SHIFT 16
4899#define TRANS_VBLANK_START_SHIFT 0
4900#define _PCH_TRANS_VSYNC_A 0xe0014
4901#define TRANS_VSYNC_END_SHIFT 16
4902#define TRANS_VSYNC_START_SHIFT 0
4903#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08004904
Daniel Vettere3b95f12013-05-03 11:49:49 +02004905#define _PCH_TRANSA_DATA_M1 0xe0030
4906#define _PCH_TRANSA_DATA_N1 0xe0034
4907#define _PCH_TRANSA_DATA_M2 0xe0038
4908#define _PCH_TRANSA_DATA_N2 0xe003c
4909#define _PCH_TRANSA_LINK_M1 0xe0040
4910#define _PCH_TRANSA_LINK_N1 0xe0044
4911#define _PCH_TRANSA_LINK_M2 0xe0048
4912#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08004913
Jesse Barnesb055c8f2011-07-08 11:31:57 -07004914/* Per-transcoder DIP controls */
4915
4916#define _VIDEO_DIP_CTL_A 0xe0200
4917#define _VIDEO_DIP_DATA_A 0xe0208
4918#define _VIDEO_DIP_GCP_A 0xe0210
4919
4920#define _VIDEO_DIP_CTL_B 0xe1200
4921#define _VIDEO_DIP_DATA_B 0xe1208
4922#define _VIDEO_DIP_GCP_B 0xe1210
4923
4924#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4925#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4926#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4927
Ville Syrjäläb9064872013-01-24 15:29:31 +02004928#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4929#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4930#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07004931
Ville Syrjäläb9064872013-01-24 15:29:31 +02004932#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4933#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4934#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07004935
4936#define VLV_TVIDEO_DIP_CTL(pipe) \
4937 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4938#define VLV_TVIDEO_DIP_DATA(pipe) \
4939 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4940#define VLV_TVIDEO_DIP_GCP(pipe) \
4941 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4942
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03004943/* Haswell DIP controls */
4944#define HSW_VIDEO_DIP_CTL_A 0x60200
4945#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
4946#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
4947#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
4948#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
4949#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
4950#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
4951#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
4952#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
4953#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
4954#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
4955#define HSW_VIDEO_DIP_GCP_A 0x60210
4956
4957#define HSW_VIDEO_DIP_CTL_B 0x61200
4958#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
4959#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
4960#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
4961#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
4962#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
4963#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
4964#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
4965#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
4966#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
4967#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
4968#define HSW_VIDEO_DIP_GCP_B 0x61210
4969
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03004970#define HSW_TVIDEO_DIP_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004971 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03004972#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004973 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +01004974#define HSW_TVIDEO_DIP_VS_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004975 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03004976#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004977 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03004978#define HSW_TVIDEO_DIP_GCP(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004979 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03004980#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004981 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03004982
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03004983#define HSW_STEREO_3D_CTL_A 0x70020
4984#define S3D_ENABLE (1<<31)
4985#define HSW_STEREO_3D_CTL_B 0x71020
4986
4987#define HSW_STEREO_3D_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004988 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03004989
Daniel Vetter275f01b22013-05-03 11:49:47 +02004990#define _PCH_TRANS_HTOTAL_B 0xe1000
4991#define _PCH_TRANS_HBLANK_B 0xe1004
4992#define _PCH_TRANS_HSYNC_B 0xe1008
4993#define _PCH_TRANS_VTOTAL_B 0xe100c
4994#define _PCH_TRANS_VBLANK_B 0xe1010
4995#define _PCH_TRANS_VSYNC_B 0xe1014
4996#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08004997
Daniel Vetter275f01b22013-05-03 11:49:47 +02004998#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4999#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5000#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5001#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5002#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5003#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5004#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
5005 _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01005006
Daniel Vettere3b95f12013-05-03 11:49:49 +02005007#define _PCH_TRANSB_DATA_M1 0xe1030
5008#define _PCH_TRANSB_DATA_N1 0xe1034
5009#define _PCH_TRANSB_DATA_M2 0xe1038
5010#define _PCH_TRANSB_DATA_N2 0xe103c
5011#define _PCH_TRANSB_LINK_M1 0xe1040
5012#define _PCH_TRANSB_LINK_N1 0xe1044
5013#define _PCH_TRANSB_LINK_M2 0xe1048
5014#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005015
Daniel Vettere3b95f12013-05-03 11:49:49 +02005016#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5017#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5018#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5019#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5020#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5021#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5022#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5023#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005024
Daniel Vetterab9412b2013-05-03 11:49:46 +02005025#define _PCH_TRANSACONF 0xf0008
5026#define _PCH_TRANSBCONF 0xf1008
5027#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5028#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005029#define TRANS_DISABLE (0<<31)
5030#define TRANS_ENABLE (1<<31)
5031#define TRANS_STATE_MASK (1<<30)
5032#define TRANS_STATE_DISABLE (0<<30)
5033#define TRANS_STATE_ENABLE (1<<30)
5034#define TRANS_FSYNC_DELAY_HB1 (0<<27)
5035#define TRANS_FSYNC_DELAY_HB2 (1<<27)
5036#define TRANS_FSYNC_DELAY_HB3 (2<<27)
5037#define TRANS_FSYNC_DELAY_HB4 (3<<27)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02005038#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005039#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02005040#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02005041#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005042#define TRANS_8BPC (0<<5)
5043#define TRANS_10BPC (1<<5)
5044#define TRANS_6BPC (2<<5)
5045#define TRANS_12BPC (3<<5)
5046
Daniel Vetterce401412012-10-31 22:52:30 +01005047#define _TRANSA_CHICKEN1 0xf0060
5048#define _TRANSB_CHICKEN1 0xf1060
5049#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5050#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07005051#define _TRANSA_CHICKEN2 0xf0064
5052#define _TRANSB_CHICKEN2 0xf1064
5053#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03005054#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
5055#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
5056#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
5057#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
5058#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07005059
Jesse Barnes291427f2011-07-29 12:42:37 -07005060#define SOUTH_CHICKEN1 0xc2000
5061#define FDIA_PHASE_SYNC_SHIFT_OVR 19
5062#define FDIA_PHASE_SYNC_SHIFT_EN 18
Daniel Vetter01a415f2012-10-27 15:58:40 +02005063#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5064#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5065#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Jesse Barnes645c62a2011-05-11 09:49:31 -07005066#define SOUTH_CHICKEN2 0xc2004
Paulo Zanonidde86e22012-12-01 12:04:25 -02005067#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
5068#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
5069#define DPLS_EDP_PPS_FIX_DIS (1<<0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07005070
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005071#define _FDI_RXA_CHICKEN 0xc200c
5072#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08005073#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
5074#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005075#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005076
Jesse Barnes382b0932010-10-07 16:01:25 -07005077#define SOUTH_DSPCLK_GATE_D 0xc2020
Jesse Barnescd664072013-10-02 10:34:19 -07005078#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
Jesse Barnes382b0932010-10-07 16:01:25 -07005079#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
Jesse Barnescd664072013-10-02 10:34:19 -07005080#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02005081#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
Jesse Barnes382b0932010-10-07 16:01:25 -07005082
Zhenyu Wangb9055052009-06-05 15:38:38 +08005083/* CPU: FDI_TX */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005084#define _FDI_TXA_CTL 0x60100
5085#define _FDI_TXB_CTL 0x61100
5086#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005087#define FDI_TX_DISABLE (0<<31)
5088#define FDI_TX_ENABLE (1<<31)
5089#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
5090#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
5091#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
5092#define FDI_LINK_TRAIN_NONE (3<<28)
5093#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
5094#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
5095#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
5096#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
5097#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
5098#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
5099#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
5100#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005101/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
5102 SNB has different settings. */
5103/* SNB A-stepping */
5104#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5105#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5106#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5107#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5108/* SNB B-stepping */
5109#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
5110#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
5111#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
5112#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
5113#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005114#define FDI_DP_PORT_WIDTH_SHIFT 19
5115#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
5116#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005117#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005118/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005119#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07005120
5121/* Ivybridge has different bits for lolz */
5122#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
5123#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
5124#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
5125#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
5126
Zhenyu Wangb9055052009-06-05 15:38:38 +08005127/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07005128#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07005129#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005130#define FDI_SCRAMBLING_ENABLE (0<<7)
5131#define FDI_SCRAMBLING_DISABLE (1<<7)
5132
5133/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005134#define _FDI_RXA_CTL 0xf000c
5135#define _FDI_RXB_CTL 0xf100c
5136#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005137#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005138/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07005139#define FDI_FS_ERRC_ENABLE (1<<27)
5140#define FDI_FE_ERRC_ENABLE (1<<26)
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02005141#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005142#define FDI_8BPC (0<<16)
5143#define FDI_10BPC (1<<16)
5144#define FDI_6BPC (2<<16)
5145#define FDI_12BPC (3<<16)
Damien Lespiau3e683202012-12-11 18:48:29 +00005146#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005147#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
5148#define FDI_RX_PLL_ENABLE (1<<13)
5149#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
5150#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
5151#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
5152#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
5153#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01005154#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005155/* CPT */
5156#define FDI_AUTO_TRAINING (1<<10)
5157#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
5158#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
5159#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
5160#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
5161#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005162
Paulo Zanoni04945642012-11-01 21:00:59 -02005163#define _FDI_RXA_MISC 0xf0010
5164#define _FDI_RXB_MISC 0xf1010
5165#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
5166#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
5167#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
5168#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
5169#define FDI_RX_TP1_TO_TP2_48 (2<<20)
5170#define FDI_RX_TP1_TO_TP2_64 (3<<20)
5171#define FDI_RX_FDI_DELAY_90 (0x90<<0)
5172#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
5173
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005174#define _FDI_RXA_TUSIZE1 0xf0030
5175#define _FDI_RXA_TUSIZE2 0xf0038
5176#define _FDI_RXB_TUSIZE1 0xf1030
5177#define _FDI_RXB_TUSIZE2 0xf1038
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005178#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
5179#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005180
5181/* FDI_RX interrupt register format */
5182#define FDI_RX_INTER_LANE_ALIGN (1<<10)
5183#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
5184#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
5185#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
5186#define FDI_RX_FS_CODE_ERR (1<<6)
5187#define FDI_RX_FE_CODE_ERR (1<<5)
5188#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
5189#define FDI_RX_HDCP_LINK_FAIL (1<<3)
5190#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
5191#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
5192#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
5193
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005194#define _FDI_RXA_IIR 0xf0014
5195#define _FDI_RXA_IMR 0xf0018
5196#define _FDI_RXB_IIR 0xf1014
5197#define _FDI_RXB_IMR 0xf1018
5198#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
5199#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005200
5201#define FDI_PLL_CTL_1 0xfe000
5202#define FDI_PLL_CTL_2 0xfe004
5203
Zhenyu Wangb9055052009-06-05 15:38:38 +08005204#define PCH_LVDS 0xe1180
5205#define LVDS_DETECTED (1 << 1)
5206
Shobhit Kumar98364372012-06-15 11:55:14 -07005207/* vlv has 2 sets of panel control regs. */
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005208#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
5209#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
5210#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
Jani Nikulaa24c1442013-09-05 16:44:46 +03005211#define PANEL_PORT_SELECT_DPB_VLV (1 << 30)
5212#define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005213#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
5214#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
Shobhit Kumar98364372012-06-15 11:55:14 -07005215
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005216#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
5217#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
5218#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
5219#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
5220#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
Shobhit Kumar98364372012-06-15 11:55:14 -07005221
Jesse Barnes453c5422013-03-28 09:55:41 -07005222#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
5223#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
5224#define VLV_PIPE_PP_ON_DELAYS(pipe) \
5225 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
5226#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
5227 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
5228#define VLV_PIPE_PP_DIVISOR(pipe) \
5229 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
5230
Zhenyu Wangb9055052009-06-05 15:38:38 +08005231#define PCH_PP_STATUS 0xc7200
5232#define PCH_PP_CONTROL 0xc7204
Jesse Barnes4a655f02010-07-22 13:18:18 -07005233#define PANEL_UNLOCK_REGS (0xabcd << 16)
Keith Packard1c0ae802011-09-19 13:59:29 -07005234#define PANEL_UNLOCK_MASK (0xffff << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005235#define EDP_FORCE_VDD (1 << 3)
5236#define EDP_BLC_ENABLE (1 << 2)
5237#define PANEL_POWER_RESET (1 << 1)
5238#define PANEL_POWER_OFF (0 << 0)
5239#define PANEL_POWER_ON (1 << 0)
5240#define PCH_PP_ON_DELAYS 0xc7208
Keith Packardf01eca22011-09-28 16:48:10 -07005241#define PANEL_PORT_SELECT_MASK (3 << 30)
5242#define PANEL_PORT_SELECT_LVDS (0 << 30)
5243#define PANEL_PORT_SELECT_DPA (1 << 30)
Keith Packardf01eca22011-09-28 16:48:10 -07005244#define PANEL_PORT_SELECT_DPC (2 << 30)
5245#define PANEL_PORT_SELECT_DPD (3 << 30)
5246#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
5247#define PANEL_POWER_UP_DELAY_SHIFT 16
5248#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
5249#define PANEL_LIGHT_ON_DELAY_SHIFT 0
5250
Zhenyu Wangb9055052009-06-05 15:38:38 +08005251#define PCH_PP_OFF_DELAYS 0xc720c
Keith Packardf01eca22011-09-28 16:48:10 -07005252#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
5253#define PANEL_POWER_DOWN_DELAY_SHIFT 16
5254#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
5255#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
5256
Zhenyu Wangb9055052009-06-05 15:38:38 +08005257#define PCH_PP_DIVISOR 0xc7210
Keith Packardf01eca22011-09-28 16:48:10 -07005258#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
5259#define PP_REFERENCE_DIVIDER_SHIFT 8
5260#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
5261#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005262
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005263#define PCH_DP_B 0xe4100
5264#define PCH_DPB_AUX_CH_CTL 0xe4110
5265#define PCH_DPB_AUX_CH_DATA1 0xe4114
5266#define PCH_DPB_AUX_CH_DATA2 0xe4118
5267#define PCH_DPB_AUX_CH_DATA3 0xe411c
5268#define PCH_DPB_AUX_CH_DATA4 0xe4120
5269#define PCH_DPB_AUX_CH_DATA5 0xe4124
5270
5271#define PCH_DP_C 0xe4200
5272#define PCH_DPC_AUX_CH_CTL 0xe4210
5273#define PCH_DPC_AUX_CH_DATA1 0xe4214
5274#define PCH_DPC_AUX_CH_DATA2 0xe4218
5275#define PCH_DPC_AUX_CH_DATA3 0xe421c
5276#define PCH_DPC_AUX_CH_DATA4 0xe4220
5277#define PCH_DPC_AUX_CH_DATA5 0xe4224
5278
5279#define PCH_DP_D 0xe4300
5280#define PCH_DPD_AUX_CH_CTL 0xe4310
5281#define PCH_DPD_AUX_CH_DATA1 0xe4314
5282#define PCH_DPD_AUX_CH_DATA2 0xe4318
5283#define PCH_DPD_AUX_CH_DATA3 0xe431c
5284#define PCH_DPD_AUX_CH_DATA4 0xe4320
5285#define PCH_DPD_AUX_CH_DATA5 0xe4324
5286
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005287/* CPT */
5288#define PORT_TRANS_A_SEL_CPT 0
5289#define PORT_TRANS_B_SEL_CPT (1<<29)
5290#define PORT_TRANS_C_SEL_CPT (2<<29)
5291#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07005292#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetter19d8fe12012-07-02 13:26:27 +02005293#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
5294#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
Ville Syrjälä71485e02014-04-09 13:28:55 +03005295#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
5296#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005297
5298#define TRANS_DP_CTL_A 0xe0300
5299#define TRANS_DP_CTL_B 0xe1300
5300#define TRANS_DP_CTL_C 0xe2300
Daniel Vetter23670b322012-11-01 09:15:30 +01005301#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005302#define TRANS_DP_OUTPUT_ENABLE (1<<31)
5303#define TRANS_DP_PORT_SEL_B (0<<29)
5304#define TRANS_DP_PORT_SEL_C (1<<29)
5305#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08005306#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005307#define TRANS_DP_PORT_SEL_MASK (3<<29)
5308#define TRANS_DP_AUDIO_ONLY (1<<26)
5309#define TRANS_DP_ENH_FRAMING (1<<18)
5310#define TRANS_DP_8BPC (0<<9)
5311#define TRANS_DP_10BPC (1<<9)
5312#define TRANS_DP_6BPC (2<<9)
5313#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08005314#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005315#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
5316#define TRANS_DP_VSYNC_ACTIVE_LOW 0
5317#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
5318#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01005319#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005320
5321/* SNB eDP training params */
5322/* SNB A-stepping */
5323#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5324#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5325#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5326#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5327/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08005328#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
5329#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
5330#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
5331#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
5332#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005333#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
5334
Keith Packard1a2eb462011-11-16 16:26:07 -08005335/* IVB */
5336#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
5337#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
5338#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
5339#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
5340#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
5341#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
Imre Deak77fa4cb2013-08-23 23:50:23 +03005342#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
Keith Packard1a2eb462011-11-16 16:26:07 -08005343
5344/* legacy values */
5345#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
5346#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
5347#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
5348#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
5349#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
5350
5351#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
5352
Imre Deak9e72b462014-05-05 15:13:55 +03005353#define VLV_PMWGICZ 0x1300a4
5354
Zou Nan haicae58522010-11-09 17:17:32 +08005355#define FORCEWAKE 0xA18C
Jesse Barnes575155a2012-03-28 13:39:37 -07005356#define FORCEWAKE_VLV 0x1300b0
5357#define FORCEWAKE_ACK_VLV 0x1300b4
Jesse Barnesed5de392013-03-08 10:45:57 -08005358#define FORCEWAKE_MEDIA_VLV 0x1300b8
5359#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
Eugeni Dodonove7911c42012-07-02 11:51:04 -03005360#define FORCEWAKE_ACK_HSW 0x130044
Chris Wilsoneb43f4a2010-12-08 17:32:24 +00005361#define FORCEWAKE_ACK 0x130090
Jesse Barnesd62b4892013-03-08 10:45:53 -08005362#define VLV_GTLC_WAKE_CTRL 0x130090
Imre Deak981a5ae2014-04-14 20:24:22 +03005363#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
5364#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
5365#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
5366
Jesse Barnesd62b4892013-03-08 10:45:53 -08005367#define VLV_GTLC_PW_STATUS 0x130094
Imre Deak981a5ae2014-04-14 20:24:22 +03005368#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
5369#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
5370#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
5371#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
Keith Packard8d715f02011-11-18 20:39:01 -08005372#define FORCEWAKE_MT 0xa188 /* multi-threaded */
Chris Wilsonc5836c22012-10-17 12:09:55 +01005373#define FORCEWAKE_KERNEL 0x1
5374#define FORCEWAKE_USER 0x2
Keith Packard8d715f02011-11-18 20:39:01 -08005375#define FORCEWAKE_MT_ACK 0x130040
5376#define ECOBUS 0xa180
5377#define FORCEWAKE_MT_ENABLE (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03005378#define VLV_SPAREG2H 0xA194
Chris Wilson8fd26852010-12-08 18:40:43 +00005379
Ben Widawskydd202c62012-02-09 10:15:18 +01005380#define GTFIFODBG 0x120000
Ville Syrjälä90f256b2013-11-14 01:59:59 +02005381#define GT_FIFO_SBDROPERR (1<<6)
5382#define GT_FIFO_BLOBDROPERR (1<<5)
5383#define GT_FIFO_SB_READ_ABORTERR (1<<4)
5384#define GT_FIFO_DROPERR (1<<3)
Ben Widawskydd202c62012-02-09 10:15:18 +01005385#define GT_FIFO_OVFERR (1<<2)
5386#define GT_FIFO_IAWRERR (1<<1)
5387#define GT_FIFO_IARDERR (1<<0)
5388
Ville Syrjälä46520e22013-11-14 02:00:00 +02005389#define GTFIFOCTL 0x120008
5390#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
Chris Wilson957367202011-05-12 22:17:09 +01005391#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Chris Wilson91355832011-03-04 19:22:40 +00005392
Ben Widawsky05e21cc2013-07-04 11:02:04 -07005393#define HSW_IDICR 0x9008
5394#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
5395#define HSW_EDRAM_PRESENT 0x120010
5396
Daniel Vetter80e829f2012-03-31 11:21:57 +02005397#define GEN6_UCGCTL1 0x9400
Ville Syrjäläe4443e42014-04-09 13:28:41 +03005398# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
Daniel Vetter80e829f2012-03-31 11:21:57 +02005399# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02005400# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02005401
Eric Anholt406478d2011-11-07 16:07:04 -08005402#define GEN6_UCGCTL2 0x9404
Jesse Barnes0f846f82012-06-14 11:04:47 -07005403# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07005404# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08005405# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08005406# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08005407# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08005408
Imre Deak9e72b462014-05-05 15:13:55 +03005409#define GEN6_UCGCTL3 0x9408
5410
Jesse Barnese3f33d42012-06-14 11:04:50 -07005411#define GEN7_UCGCTL4 0x940c
5412#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
5413
Imre Deak9e72b462014-05-05 15:13:55 +03005414#define GEN6_RCGCTL1 0x9410
5415#define GEN6_RCGCTL2 0x9414
5416#define GEN6_RSTCTL 0x9420
5417
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02005418#define GEN8_UCGCTL6 0x9430
5419#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
5420
Imre Deak9e72b462014-05-05 15:13:55 +03005421#define GEN6_GFXPAUSE 0xA000
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08005422#define GEN6_RPNSWREQ 0xA008
Chris Wilson8fd26852010-12-08 18:40:43 +00005423#define GEN6_TURBO_DISABLE (1<<31)
5424#define GEN6_FREQUENCY(x) ((x)<<25)
Rodrigo Vivi92bd1bf2013-03-25 17:55:49 -03005425#define HSW_FREQUENCY(x) ((x)<<24)
Chris Wilson8fd26852010-12-08 18:40:43 +00005426#define GEN6_OFFSET(x) ((x)<<19)
5427#define GEN6_AGGRESSIVE_TURBO (0<<15)
5428#define GEN6_RC_VIDEO_FREQ 0xA00C
5429#define GEN6_RC_CONTROL 0xA090
5430#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
5431#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
5432#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
5433#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
5434#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
Jesse Barnes6b88f292013-11-15 09:32:12 -08005435#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
Jesse Barnes0a073b82013-04-17 15:54:58 -07005436#define GEN7_RC_CTL_TO_MODE (1<<28)
Chris Wilson8fd26852010-12-08 18:40:43 +00005437#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
5438#define GEN6_RC_CTL_HW_ENABLE (1<<31)
5439#define GEN6_RP_DOWN_TIMEOUT 0xA010
5440#define GEN6_RP_INTERRUPT_LIMITS 0xA014
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08005441#define GEN6_RPSTAT1 0xA01C
Jesse Barnesccab5c82011-01-18 15:49:25 -08005442#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08005443#define HSW_CAGF_SHIFT 7
Jesse Barnesccab5c82011-01-18 15:49:25 -08005444#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08005445#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Chris Wilson8fd26852010-12-08 18:40:43 +00005446#define GEN6_RP_CONTROL 0xA024
5447#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08005448#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
5449#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
5450#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
5451#define GEN6_RP_MEDIA_HW_MODE (1<<9)
5452#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00005453#define GEN6_RP_MEDIA_IS_GFX (1<<8)
5454#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08005455#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
5456#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
5457#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01005458#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
Jesse Barnesccab5c82011-01-18 15:49:25 -08005459#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Chris Wilson8fd26852010-12-08 18:40:43 +00005460#define GEN6_RP_UP_THRESHOLD 0xA02C
5461#define GEN6_RP_DOWN_THRESHOLD 0xA030
Jesse Barnesccab5c82011-01-18 15:49:25 -08005462#define GEN6_RP_CUR_UP_EI 0xA050
5463#define GEN6_CURICONT_MASK 0xffffff
5464#define GEN6_RP_CUR_UP 0xA054
5465#define GEN6_CURBSYTAVG_MASK 0xffffff
5466#define GEN6_RP_PREV_UP 0xA058
5467#define GEN6_RP_CUR_DOWN_EI 0xA05C
5468#define GEN6_CURIAVG_MASK 0xffffff
5469#define GEN6_RP_CUR_DOWN 0xA060
5470#define GEN6_RP_PREV_DOWN 0xA064
Chris Wilson8fd26852010-12-08 18:40:43 +00005471#define GEN6_RP_UP_EI 0xA068
5472#define GEN6_RP_DOWN_EI 0xA06C
5473#define GEN6_RP_IDLE_HYSTERSIS 0xA070
Imre Deak9e72b462014-05-05 15:13:55 +03005474#define GEN6_RPDEUHWTC 0xA080
5475#define GEN6_RPDEUC 0xA084
5476#define GEN6_RPDEUCSW 0xA088
Chris Wilson8fd26852010-12-08 18:40:43 +00005477#define GEN6_RC_STATE 0xA094
5478#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
5479#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
5480#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
5481#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
5482#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
5483#define GEN6_RC_SLEEP 0xA0B0
Imre Deak9e72b462014-05-05 15:13:55 +03005484#define GEN6_RCUBMABDTMR 0xA0B0
Chris Wilson8fd26852010-12-08 18:40:43 +00005485#define GEN6_RC1e_THRESHOLD 0xA0B4
5486#define GEN6_RC6_THRESHOLD 0xA0B8
5487#define GEN6_RC6p_THRESHOLD 0xA0BC
Imre Deak9e72b462014-05-05 15:13:55 +03005488#define VLV_RCEDATA 0xA0BC
Chris Wilson8fd26852010-12-08 18:40:43 +00005489#define GEN6_RC6pp_THRESHOLD 0xA0C0
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08005490#define GEN6_PMINTRMSK 0xA168
Deepak Sbaccd452014-05-15 20:58:09 +03005491#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
Imre Deak9e72b462014-05-05 15:13:55 +03005492#define VLV_PWRDWNUPCTL 0xA294
Chris Wilson8fd26852010-12-08 18:40:43 +00005493
5494#define GEN6_PMISR 0x44020
Ben Widawsky4912d042011-04-25 11:25:20 -07005495#define GEN6_PMIMR 0x44024 /* rps_lock */
Chris Wilson8fd26852010-12-08 18:40:43 +00005496#define GEN6_PMIIR 0x44028
5497#define GEN6_PMIER 0x4402C
5498#define GEN6_PM_MBOX_EVENT (1<<25)
5499#define GEN6_PM_THERMAL_EVENT (1<<24)
5500#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
5501#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
5502#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
5503#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
5504#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky48484052013-05-28 19:22:27 -07005505#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07005506 GEN6_PM_RP_DOWN_THRESHOLD | \
5507 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00005508
Imre Deak9e72b462014-05-05 15:13:55 +03005509#define GEN7_GT_SCRATCH_BASE 0x4F100
5510#define GEN7_GT_SCRATCH_REG_NUM 8
5511
Deepak S76c3552f2014-01-30 23:08:16 +05305512#define VLV_GTLC_SURVIVABILITY_REG 0x130098
5513#define VLV_GFX_CLK_STATUS_BIT (1<<3)
5514#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
5515
Ben Widawskycce66a22012-03-27 18:59:38 -07005516#define GEN6_GT_GFX_RC6_LOCKED 0x138104
Jesse Barnes49798eb2013-09-26 17:55:57 -07005517#define VLV_COUNTER_CONTROL 0x138104
5518#define VLV_COUNT_RANGE_HIGH (1<<15)
5519#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
5520#define VLV_RENDER_RC6_COUNT_EN (1<<0)
Ben Widawskycce66a22012-03-27 18:59:38 -07005521#define GEN6_GT_GFX_RC6 0x138108
Imre Deak9cc19be2014-04-14 20:24:24 +03005522#define VLV_GT_RENDER_RC6 0x138108
5523#define VLV_GT_MEDIA_RC6 0x13810C
5524
Ben Widawskycce66a22012-03-27 18:59:38 -07005525#define GEN6_GT_GFX_RC6p 0x13810C
5526#define GEN6_GT_GFX_RC6pp 0x138110
5527
Chris Wilson8fd26852010-12-08 18:40:43 +00005528#define GEN6_PCODE_MAILBOX 0x138124
5529#define GEN6_PCODE_READY (1<<31)
Jesse Barnesa6044e22010-12-20 11:34:20 -08005530#define GEN6_READ_OC_PARAMS 0xc
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07005531#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
5532#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
Ben Widawsky31643d52012-09-26 10:34:01 -07005533#define GEN6_PCODE_WRITE_RC6VIDS 0x4
5534#define GEN6_PCODE_READ_RC6VIDS 0x5
Paulo Zanoni515b2392013-09-10 19:36:37 -03005535#define GEN6_PCODE_READ_D_COMP 0x10
5536#define GEN6_PCODE_WRITE_D_COMP 0x11
Ben Widawsky7083e052013-02-01 16:41:14 -08005537#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5538#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Ben Widawsky2a114cc2013-11-02 21:07:47 -07005539#define DISPLAY_IPS_CONTROL 0x19
Chris Wilson8fd26852010-12-08 18:40:43 +00005540#define GEN6_PCODE_DATA 0x138128
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07005541#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01005542#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Chris Wilson8fd26852010-12-08 18:40:43 +00005543
Ben Widawsky4d855292011-12-12 19:34:16 -08005544#define GEN6_GT_CORE_STATUS 0x138060
5545#define GEN6_CORE_CPD_STATE_MASK (7<<4)
5546#define GEN6_RCn_MASK 7
5547#define GEN6_RC0 0
5548#define GEN6_RC3 2
5549#define GEN6_RC6 3
5550#define GEN6_RC7 4
5551
Ben Widawskye3689192012-05-25 16:56:22 -07005552#define GEN7_MISCCPCTL (0x9424)
5553#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
5554
5555/* IVYBRIDGE DPF */
5556#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07005557#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
Ben Widawskye3689192012-05-25 16:56:22 -07005558#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
5559#define GEN7_PARITY_ERROR_VALID (1<<13)
5560#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
5561#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
5562#define GEN7_PARITY_ERROR_ROW(reg) \
5563 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
5564#define GEN7_PARITY_ERROR_BANK(reg) \
5565 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
5566#define GEN7_PARITY_ERROR_SUBBANK(reg) \
5567 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
5568#define GEN7_L3CDERRST1_ENABLE (1<<7)
5569
Ben Widawskyb9524a12012-05-25 16:56:24 -07005570#define GEN7_L3LOG_BASE 0xB070
Ben Widawsky35a85ac2013-09-19 11:13:41 -07005571#define HSW_L3LOG_BASE_SLICE1 0xB270
Ben Widawskyb9524a12012-05-25 16:56:24 -07005572#define GEN7_L3LOG_SIZE 0x80
5573
Jesse Barnes12f33822012-10-25 12:15:45 -07005574#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
5575#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
5576#define GEN7_MAX_PS_THREAD_DEP (8<<12)
Ben Widawsky4c2e7a52013-11-02 21:08:00 -07005577#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
Jesse Barnes12f33822012-10-25 12:15:45 -07005578#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
5579
Kenneth Graunkec8966e12014-02-26 23:59:30 -08005580#define GEN8_ROW_CHICKEN 0xe4f0
5581#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
Kenneth Graunke1411e6a2014-02-26 23:59:31 -08005582#define STALL_DOP_GATING_DISABLE (1<<5)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08005583
Jesse Barnes8ab43972012-10-25 12:15:42 -07005584#define GEN7_ROW_CHICKEN2 0xe4f4
5585#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
5586#define DOP_CLOCK_GATING_DISABLE (1<<0)
5587
Francisco Jerezf3fc4882013-10-02 15:53:16 -07005588#define HSW_ROW_CHICKEN3 0xe49c
5589#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
5590
Ben Widawskyfd392b62013-11-04 22:52:39 -08005591#define HALF_SLICE_CHICKEN3 0xe184
5592#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
Ben Widawskybf663472013-11-02 21:07:57 -07005593#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
Ben Widawskyfd392b62013-11-04 22:52:39 -08005594
Damien Lespiau5c969aa2014-02-07 19:12:48 +00005595#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
Wu Fengguange0dac652011-09-05 14:25:34 +08005596#define INTEL_AUDIO_DEVCL 0x808629FB
5597#define INTEL_AUDIO_DEVBLC 0x80862801
5598#define INTEL_AUDIO_DEVCTG 0x80862802
5599
5600#define G4X_AUD_CNTL_ST 0x620B4
5601#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
5602#define G4X_ELDV_DEVCTG (1 << 14)
5603#define G4X_ELD_ADDR (0xf << 5)
5604#define G4X_ELD_ACK (1 << 4)
5605#define G4X_HDMIW_HDMIEDID 0x6210C
5606
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005607#define IBX_HDMIW_HDMIEDID_A 0xE2050
Wang Xingchao9b138a82012-08-09 16:52:18 +08005608#define IBX_HDMIW_HDMIEDID_B 0xE2150
5609#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5610 IBX_HDMIW_HDMIEDID_A, \
5611 IBX_HDMIW_HDMIEDID_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005612#define IBX_AUD_CNTL_ST_A 0xE20B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08005613#define IBX_AUD_CNTL_ST_B 0xE21B4
5614#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5615 IBX_AUD_CNTL_ST_A, \
5616 IBX_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005617#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
5618#define IBX_ELD_ADDRESS (0x1f << 5)
5619#define IBX_ELD_ACK (1 << 4)
5620#define IBX_AUD_CNTL_ST2 0xE20C0
5621#define IBX_ELD_VALIDB (1 << 0)
5622#define IBX_CP_READYB (1 << 1)
Wu Fengguange0dac652011-09-05 14:25:34 +08005623
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005624#define CPT_HDMIW_HDMIEDID_A 0xE5050
Wang Xingchao9b138a82012-08-09 16:52:18 +08005625#define CPT_HDMIW_HDMIEDID_B 0xE5150
5626#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5627 CPT_HDMIW_HDMIEDID_A, \
5628 CPT_HDMIW_HDMIEDID_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005629#define CPT_AUD_CNTL_ST_A 0xE50B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08005630#define CPT_AUD_CNTL_ST_B 0xE51B4
5631#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5632 CPT_AUD_CNTL_ST_A, \
5633 CPT_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005634#define CPT_AUD_CNTRL_ST2 0xE50C0
Wu Fengguange0dac652011-09-05 14:25:34 +08005635
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04005636#define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
5637#define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
5638#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5639 VLV_HDMIW_HDMIEDID_A, \
5640 VLV_HDMIW_HDMIEDID_B)
5641#define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
5642#define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
5643#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5644 VLV_AUD_CNTL_ST_A, \
5645 VLV_AUD_CNTL_ST_B)
5646#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
5647
Eric Anholtae662d32012-01-03 09:23:29 -08005648/* These are the 4 32-bit write offset registers for each stream
5649 * output buffer. It determines the offset from the
5650 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5651 */
5652#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
5653
Wu Fengguangb6daa022012-01-06 14:41:31 -06005654#define IBX_AUD_CONFIG_A 0xe2000
Wang Xingchao9b138a82012-08-09 16:52:18 +08005655#define IBX_AUD_CONFIG_B 0xe2100
5656#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5657 IBX_AUD_CONFIG_A, \
5658 IBX_AUD_CONFIG_B)
Wu Fengguangb6daa022012-01-06 14:41:31 -06005659#define CPT_AUD_CONFIG_A 0xe5000
Wang Xingchao9b138a82012-08-09 16:52:18 +08005660#define CPT_AUD_CONFIG_B 0xe5100
5661#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5662 CPT_AUD_CONFIG_A, \
5663 CPT_AUD_CONFIG_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04005664#define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
5665#define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
5666#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5667 VLV_AUD_CONFIG_A, \
5668 VLV_AUD_CONFIG_B)
5669
Wu Fengguangb6daa022012-01-06 14:41:31 -06005670#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
5671#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
5672#define AUD_CONFIG_UPPER_N_SHIFT 20
5673#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
5674#define AUD_CONFIG_LOWER_N_SHIFT 4
5675#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
5676#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03005677#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
5678#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
5679#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
5680#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
5681#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
5682#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
5683#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
5684#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
5685#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
5686#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
5687#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06005688#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
5689
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08005690/* HSW Audio */
5691#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
5692#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
5693#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5694 HSW_AUD_CONFIG_A, \
5695 HSW_AUD_CONFIG_B)
5696
5697#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
5698#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
5699#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5700 HSW_AUD_MISC_CTRL_A, \
5701 HSW_AUD_MISC_CTRL_B)
5702
5703#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
5704#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
5705#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5706 HSW_AUD_DIP_ELD_CTRL_ST_A, \
5707 HSW_AUD_DIP_ELD_CTRL_ST_B)
5708
5709/* Audio Digital Converter */
5710#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
5711#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
5712#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5713 HSW_AUD_DIG_CNVT_1, \
5714 HSW_AUD_DIG_CNVT_2)
Wang Xingchao9b138a82012-08-09 16:52:18 +08005715#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08005716
5717#define HSW_AUD_EDID_DATA_A 0x65050
5718#define HSW_AUD_EDID_DATA_B 0x65150
5719#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5720 HSW_AUD_EDID_DATA_A, \
5721 HSW_AUD_EDID_DATA_B)
5722
5723#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
5724#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
5725#define AUDIO_INACTIVE_C (1<<11)
5726#define AUDIO_INACTIVE_B (1<<7)
5727#define AUDIO_INACTIVE_A (1<<3)
5728#define AUDIO_OUTPUT_ENABLE_A (1<<2)
5729#define AUDIO_OUTPUT_ENABLE_B (1<<6)
5730#define AUDIO_OUTPUT_ENABLE_C (1<<10)
5731#define AUDIO_ELD_VALID_A (1<<0)
5732#define AUDIO_ELD_VALID_B (1<<4)
5733#define AUDIO_ELD_VALID_C (1<<8)
5734#define AUDIO_CP_READY_A (1<<1)
5735#define AUDIO_CP_READY_B (1<<5)
5736#define AUDIO_CP_READY_C (1<<9)
5737
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005738/* HSW Power Wells */
Paulo Zanonifa42e232013-01-25 16:59:11 -02005739#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
5740#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
5741#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
5742#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -03005743#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
5744#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005745#define HSW_PWR_WELL_CTL5 0x45410
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005746#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
5747#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005748#define HSW_PWR_WELL_FORCE_ON (1<<19)
5749#define HSW_PWR_WELL_CTL6 0x45414
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005750
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005751/* Per-pipe DDI Function Control */
Paulo Zanoniad80a812012-10-24 16:06:19 -02005752#define TRANS_DDI_FUNC_CTL_A 0x60400
5753#define TRANS_DDI_FUNC_CTL_B 0x61400
5754#define TRANS_DDI_FUNC_CTL_C 0x62400
5755#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005756#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
5757
Paulo Zanoniad80a812012-10-24 16:06:19 -02005758#define TRANS_DDI_FUNC_ENABLE (1<<31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005759/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Paulo Zanoniad80a812012-10-24 16:06:19 -02005760#define TRANS_DDI_PORT_MASK (7<<28)
5761#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
5762#define TRANS_DDI_PORT_NONE (0<<28)
5763#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
5764#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
5765#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
5766#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
5767#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
5768#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
5769#define TRANS_DDI_BPC_MASK (7<<20)
5770#define TRANS_DDI_BPC_8 (0<<20)
5771#define TRANS_DDI_BPC_10 (1<<20)
5772#define TRANS_DDI_BPC_6 (2<<20)
5773#define TRANS_DDI_BPC_12 (3<<20)
5774#define TRANS_DDI_PVSYNC (1<<17)
5775#define TRANS_DDI_PHSYNC (1<<16)
5776#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
5777#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
5778#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5779#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5780#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
5781#define TRANS_DDI_BFI_ENABLE (1<<4)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005782
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005783/* DisplayPort Transport Control */
5784#define DP_TP_CTL_A 0x64040
5785#define DP_TP_CTL_B 0x64140
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005786#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
5787#define DP_TP_CTL_ENABLE (1<<31)
5788#define DP_TP_CTL_MODE_SST (0<<27)
5789#define DP_TP_CTL_MODE_MST (1<<27)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005790#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005791#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005792#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
5793#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
5794#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005795#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
5796#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005797#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005798#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005799
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03005800/* DisplayPort Transport Status */
5801#define DP_TP_STATUS_A 0x64044
5802#define DP_TP_STATUS_B 0x64144
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005803#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005804#define DP_TP_STATUS_IDLE_DONE (1<<25)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03005805#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5806
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005807/* DDI Buffer Control */
5808#define DDI_BUF_CTL_A 0x64000
5809#define DDI_BUF_CTL_B 0x64100
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005810#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5811#define DDI_BUF_CTL_ENABLE (1<<31)
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07005812/* Haswell */
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005813#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005814#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005815#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005816#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005817#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005818#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005819#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
5820#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005821#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07005822/* Broadwell */
5823#define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */
5824#define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */
5825#define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */
5826#define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */
5827#define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */
5828#define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */
5829#define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */
5830#define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */
5831#define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005832#define DDI_BUF_EMP_MASK (0xf<<24)
Damien Lespiau876a8cd2012-12-11 18:48:30 +00005833#define DDI_BUF_PORT_REVERSAL (1<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005834#define DDI_BUF_IS_IDLE (1<<7)
Paulo Zanoni79935fc2012-11-20 13:27:40 -02005835#define DDI_A_4_LANES (1<<4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +02005836#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005837#define DDI_INIT_DISPLAY_DETECTED (1<<0)
5838
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03005839/* DDI Buffer Translations */
5840#define DDI_BUF_TRANS_A 0x64E00
5841#define DDI_BUF_TRANS_B 0x64E60
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005842#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03005843
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03005844/* Sideband Interface (SBI) is programmed indirectly, via
5845 * SBI_ADDR, which contains the register offset; and SBI_DATA,
5846 * which contains the payload */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005847#define SBI_ADDR 0xC6000
5848#define SBI_DATA 0xC6004
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03005849#define SBI_CTL_STAT 0xC6008
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02005850#define SBI_CTL_DEST_ICLK (0x0<<16)
5851#define SBI_CTL_DEST_MPHY (0x1<<16)
5852#define SBI_CTL_OP_IORD (0x2<<8)
5853#define SBI_CTL_OP_IOWR (0x3<<8)
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03005854#define SBI_CTL_OP_CRRD (0x6<<8)
5855#define SBI_CTL_OP_CRWR (0x7<<8)
5856#define SBI_RESPONSE_FAIL (0x1<<1)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005857#define SBI_RESPONSE_SUCCESS (0x0<<1)
5858#define SBI_BUSY (0x1<<0)
5859#define SBI_READY (0x0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03005860
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005861/* SBI offsets */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005862#define SBI_SSCDIVINTPHASE6 0x0600
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005863#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
5864#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
5865#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
5866#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005867#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005868#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005869#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005870#define SBI_SSCCTL6 0x060C
Paulo Zanonidde86e22012-12-01 12:04:25 -02005871#define SBI_SSCCTL_PATHALT (1<<3)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005872#define SBI_SSCCTL_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005873#define SBI_SSCAUXDIV6 0x0610
5874#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005875#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005876#define SBI_GEN0 0x1f00
5877#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03005878
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03005879/* LPT PIXCLK_GATE */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005880#define PIXCLK_GATE 0xC6020
Paulo Zanoni745ca3b2012-08-08 14:15:32 -03005881#define PIXCLK_GATE_UNGATE (1<<0)
5882#define PIXCLK_GATE_GATE (0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03005883
Eugeni Dodonove93ea062012-03-29 12:32:32 -03005884/* SPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005885#define SPLL_CTL 0x46020
Eugeni Dodonove93ea062012-03-29 12:32:32 -03005886#define SPLL_PLL_ENABLE (1<<31)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01005887#define SPLL_PLL_SSC (1<<28)
5888#define SPLL_PLL_NON_SSC (2<<28)
Jesse Barnes11578552014-01-21 12:42:10 -08005889#define SPLL_PLL_LCPLL (3<<28)
5890#define SPLL_PLL_REF_MASK (3<<28)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005891#define SPLL_PLL_FREQ_810MHz (0<<26)
5892#define SPLL_PLL_FREQ_1350MHz (1<<26)
Jesse Barnes11578552014-01-21 12:42:10 -08005893#define SPLL_PLL_FREQ_2700MHz (2<<26)
5894#define SPLL_PLL_FREQ_MASK (3<<26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03005895
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03005896/* WRPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005897#define WRPLL_CTL1 0x46040
5898#define WRPLL_CTL2 0x46060
5899#define WRPLL_PLL_ENABLE (1<<31)
5900#define WRPLL_PLL_SELECT_SSC (0x01<<28)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01005901#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03005902#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -03005903/* WRPLL divider programming */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005904#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
Jesse Barnes11578552014-01-21 12:42:10 -08005905#define WRPLL_DIVIDER_REF_MASK (0xff)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005906#define WRPLL_DIVIDER_POST(x) ((x)<<8)
Jesse Barnes11578552014-01-21 12:42:10 -08005907#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
5908#define WRPLL_DIVIDER_POST_SHIFT 8
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005909#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
Jesse Barnes11578552014-01-21 12:42:10 -08005910#define WRPLL_DIVIDER_FB_SHIFT 16
5911#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03005912
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005913/* Port clock selection */
5914#define PORT_CLK_SEL_A 0x46100
5915#define PORT_CLK_SEL_B 0x46104
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005916#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005917#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
5918#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
5919#define PORT_CLK_SEL_LCPLL_810 (2<<29)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005920#define PORT_CLK_SEL_SPLL (3<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005921#define PORT_CLK_SEL_WRPLL1 (4<<29)
5922#define PORT_CLK_SEL_WRPLL2 (5<<29)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005923#define PORT_CLK_SEL_NONE (7<<29)
Jesse Barnes11578552014-01-21 12:42:10 -08005924#define PORT_CLK_SEL_MASK (7<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005925
Paulo Zanonibb523fc2012-10-23 18:29:56 -02005926/* Transcoder clock selection */
5927#define TRANS_CLK_SEL_A 0x46140
5928#define TRANS_CLK_SEL_B 0x46144
5929#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
5930/* For each transcoder, we need to select the corresponding port clock */
5931#define TRANS_CLK_SEL_DISABLED (0x0<<29)
5932#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03005933
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005934#define TRANSA_MSA_MISC 0x60410
5935#define TRANSB_MSA_MISC 0x61410
5936#define TRANSC_MSA_MISC 0x62410
5937#define TRANS_EDP_MSA_MISC 0x6f410
5938#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
5939
Paulo Zanonic9809792012-10-23 18:30:00 -02005940#define TRANS_MSA_SYNC_CLK (1<<0)
5941#define TRANS_MSA_6_BPC (0<<5)
5942#define TRANS_MSA_8_BPC (1<<5)
5943#define TRANS_MSA_10_BPC (2<<5)
5944#define TRANS_MSA_12_BPC (3<<5)
5945#define TRANS_MSA_16_BPC (4<<5)
Paulo Zanonidae84792012-10-15 15:51:30 -03005946
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005947/* LCPLL Control */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005948#define LCPLL_CTL 0x130040
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005949#define LCPLL_PLL_DISABLE (1<<31)
5950#define LCPLL_PLL_LOCK (1<<30)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03005951#define LCPLL_CLK_FREQ_MASK (3<<26)
5952#define LCPLL_CLK_FREQ_450 (0<<26)
Paulo Zanonie39bf982013-11-02 21:07:36 -07005953#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
5954#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
5955#define LCPLL_CLK_FREQ_675_BDW (3<<26)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005956#define LCPLL_CD_CLOCK_DISABLE (1<<25)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005957#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03005958#define LCPLL_POWER_DOWN_ALLOW (1<<22)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03005959#define LCPLL_CD_SOURCE_FCLK (1<<21)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03005960#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
5961
5962#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5963#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
5964#define D_COMP_COMP_FORCE (1<<8)
5965#define D_COMP_COMP_DISABLE (1<<0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03005966
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03005967/* Pipe WM_LINETIME - watermark line time */
5968#define PIPE_WM_LINETIME_A 0x45270
5969#define PIPE_WM_LINETIME_B 0x45274
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005970#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5971 PIPE_WM_LINETIME_B)
5972#define PIPE_WM_LINETIME_MASK (0x1ff)
5973#define PIPE_WM_LINETIME_TIME(x) ((x))
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03005974#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005975#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03005976
5977/* SFUSE_STRAP */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005978#define SFUSE_STRAP 0xc2014
Damien Lespiau658ac4c2014-02-10 17:19:45 +00005979#define SFUSE_STRAP_FUSE_LOCK (1<<13)
5980#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03005981#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5982#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5983#define SFUSE_STRAP_DDID_DETECTED (1<<0)
5984
Paulo Zanoni801bcff2013-05-31 10:08:35 -03005985#define WM_MISC 0x45260
5986#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
5987
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03005988#define WM_DBG 0x45280
5989#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
5990#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
5991#define WM_DBG_DISALLOW_SPRITE (1<<2)
5992
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005993/* pipe CSC */
5994#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
5995#define _PIPE_A_CSC_COEFF_BY 0x49014
5996#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
5997#define _PIPE_A_CSC_COEFF_BU 0x4901c
5998#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
5999#define _PIPE_A_CSC_COEFF_BV 0x49024
6000#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjälä29a397b2013-04-19 12:23:02 +03006001#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
6002#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
6003#define CSC_MODE_YUV_TO_RGB (1 << 0)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006004#define _PIPE_A_CSC_PREOFF_HI 0x49030
6005#define _PIPE_A_CSC_PREOFF_ME 0x49034
6006#define _PIPE_A_CSC_PREOFF_LO 0x49038
6007#define _PIPE_A_CSC_POSTOFF_HI 0x49040
6008#define _PIPE_A_CSC_POSTOFF_ME 0x49044
6009#define _PIPE_A_CSC_POSTOFF_LO 0x49048
6010
6011#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
6012#define _PIPE_B_CSC_COEFF_BY 0x49114
6013#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
6014#define _PIPE_B_CSC_COEFF_BU 0x4911c
6015#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
6016#define _PIPE_B_CSC_COEFF_BV 0x49124
6017#define _PIPE_B_CSC_MODE 0x49128
6018#define _PIPE_B_CSC_PREOFF_HI 0x49130
6019#define _PIPE_B_CSC_PREOFF_ME 0x49134
6020#define _PIPE_B_CSC_PREOFF_LO 0x49138
6021#define _PIPE_B_CSC_POSTOFF_HI 0x49140
6022#define _PIPE_B_CSC_POSTOFF_ME 0x49144
6023#define _PIPE_B_CSC_POSTOFF_LO 0x49148
6024
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006025#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6026#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6027#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6028#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6029#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6030#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6031#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6032#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6033#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6034#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6035#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6036#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6037#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6038
Jani Nikula3230bf12013-08-27 15:12:16 +03006039/* VLV MIPI registers */
6040
6041#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
6042#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
6043#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
6044#define DPI_ENABLE (1 << 31) /* A + B */
6045#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
6046#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
6047#define DUAL_LINK_MODE_MASK (1 << 26)
6048#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
6049#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
6050#define DITHERING_ENABLE (1 << 25) /* A + B */
6051#define FLOPPED_HSTX (1 << 23)
6052#define DE_INVERT (1 << 19) /* XXX */
6053#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
6054#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
6055#define AFE_LATCHOUT (1 << 17)
6056#define LP_OUTPUT_HOLD (1 << 16)
6057#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
6058#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
6059#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
6060#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
6061#define CSB_SHIFT 9
6062#define CSB_MASK (3 << 9)
6063#define CSB_20MHZ (0 << 9)
6064#define CSB_10MHZ (1 << 9)
6065#define CSB_40MHZ (2 << 9)
6066#define BANDGAP_MASK (1 << 8)
6067#define BANDGAP_PNW_CIRCUIT (0 << 8)
6068#define BANDGAP_LNC_CIRCUIT (1 << 8)
6069#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
6070#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
6071#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
6072#define TEARING_EFFECT_SHIFT 2 /* A + B */
6073#define TEARING_EFFECT_MASK (3 << 2)
6074#define TEARING_EFFECT_OFF (0 << 2)
6075#define TEARING_EFFECT_DSI (1 << 2)
6076#define TEARING_EFFECT_GPIO (2 << 2)
6077#define LANE_CONFIGURATION_SHIFT 0
6078#define LANE_CONFIGURATION_MASK (3 << 0)
6079#define LANE_CONFIGURATION_4LANE (0 << 0)
6080#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
6081#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
6082
6083#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
6084#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
6085#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
6086#define TEARING_EFFECT_DELAY_SHIFT 0
6087#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
6088
6089/* XXX: all bits reserved */
6090#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
6091
6092/* MIPI DSI Controller and D-PHY registers */
6093
6094#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
6095#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
6096#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
6097#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
6098#define ULPS_STATE_MASK (3 << 1)
6099#define ULPS_STATE_ENTER (2 << 1)
6100#define ULPS_STATE_EXIT (1 << 1)
6101#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
6102#define DEVICE_READY (1 << 0)
6103
6104#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
6105#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
6106#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
6107#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
6108#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
6109#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
6110#define TEARING_EFFECT (1 << 31)
6111#define SPL_PKT_SENT_INTERRUPT (1 << 30)
6112#define GEN_READ_DATA_AVAIL (1 << 29)
6113#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
6114#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
6115#define RX_PROT_VIOLATION (1 << 26)
6116#define RX_INVALID_TX_LENGTH (1 << 25)
6117#define ACK_WITH_NO_ERROR (1 << 24)
6118#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
6119#define LP_RX_TIMEOUT (1 << 22)
6120#define HS_TX_TIMEOUT (1 << 21)
6121#define DPI_FIFO_UNDERRUN (1 << 20)
6122#define LOW_CONTENTION (1 << 19)
6123#define HIGH_CONTENTION (1 << 18)
6124#define TXDSI_VC_ID_INVALID (1 << 17)
6125#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
6126#define TXCHECKSUM_ERROR (1 << 15)
6127#define TXECC_MULTIBIT_ERROR (1 << 14)
6128#define TXECC_SINGLE_BIT_ERROR (1 << 13)
6129#define TXFALSE_CONTROL_ERROR (1 << 12)
6130#define RXDSI_VC_ID_INVALID (1 << 11)
6131#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
6132#define RXCHECKSUM_ERROR (1 << 9)
6133#define RXECC_MULTIBIT_ERROR (1 << 8)
6134#define RXECC_SINGLE_BIT_ERROR (1 << 7)
6135#define RXFALSE_CONTROL_ERROR (1 << 6)
6136#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
6137#define RX_LP_TX_SYNC_ERROR (1 << 4)
6138#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
6139#define RXEOT_SYNC_ERROR (1 << 2)
6140#define RXSOT_SYNC_ERROR (1 << 1)
6141#define RXSOT_ERROR (1 << 0)
6142
6143#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
6144#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
6145#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
6146#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
6147#define CMD_MODE_NOT_SUPPORTED (0 << 13)
6148#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
6149#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
6150#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
6151#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
6152#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
6153#define VID_MODE_FORMAT_MASK (0xf << 7)
6154#define VID_MODE_NOT_SUPPORTED (0 << 7)
6155#define VID_MODE_FORMAT_RGB565 (1 << 7)
6156#define VID_MODE_FORMAT_RGB666 (2 << 7)
6157#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
6158#define VID_MODE_FORMAT_RGB888 (4 << 7)
6159#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
6160#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
6161#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
6162#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
6163#define DATA_LANES_PRG_REG_SHIFT 0
6164#define DATA_LANES_PRG_REG_MASK (7 << 0)
6165
6166#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
6167#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
6168#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
6169#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
6170
6171#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
6172#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
6173#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
6174#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
6175
6176#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
6177#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
6178#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
6179#define TURN_AROUND_TIMEOUT_MASK 0x3f
6180
6181#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
6182#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
6183#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
6184#define DEVICE_RESET_TIMER_MASK 0xffff
6185
6186#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
6187#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
6188#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
6189#define VERTICAL_ADDRESS_SHIFT 16
6190#define VERTICAL_ADDRESS_MASK (0xffff << 16)
6191#define HORIZONTAL_ADDRESS_SHIFT 0
6192#define HORIZONTAL_ADDRESS_MASK 0xffff
6193
6194#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
6195#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
6196#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
6197#define DBI_FIFO_EMPTY_HALF (0 << 0)
6198#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
6199#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
6200
6201/* regs below are bits 15:0 */
6202#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
6203#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
6204#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
6205
6206#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
6207#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
6208#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
6209
6210#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
6211#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
6212#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
6213
6214#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
6215#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
6216#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
6217
6218#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
6219#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
6220#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
6221
6222#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
6223#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
6224#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
6225
6226#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
6227#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
6228#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
6229
6230#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
6231#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
6232#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
6233/* regs above are bits 15:0 */
6234
6235#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
6236#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
6237#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
6238#define DPI_LP_MODE (1 << 6)
6239#define BACKLIGHT_OFF (1 << 5)
6240#define BACKLIGHT_ON (1 << 4)
6241#define COLOR_MODE_OFF (1 << 3)
6242#define COLOR_MODE_ON (1 << 2)
6243#define TURN_ON (1 << 1)
6244#define SHUTDOWN (1 << 0)
6245
6246#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
6247#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
6248#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
6249#define COMMAND_BYTE_SHIFT 0
6250#define COMMAND_BYTE_MASK (0x3f << 0)
6251
6252#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
6253#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
6254#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
6255#define MASTER_INIT_TIMER_SHIFT 0
6256#define MASTER_INIT_TIMER_MASK (0xffff << 0)
6257
6258#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
6259#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
6260#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
6261#define MAX_RETURN_PKT_SIZE_SHIFT 0
6262#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
6263
6264#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
6265#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
6266#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
6267#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
6268#define DISABLE_VIDEO_BTA (1 << 3)
6269#define IP_TG_CONFIG (1 << 2)
6270#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
6271#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
6272#define VIDEO_MODE_BURST (3 << 0)
6273
6274#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
6275#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
6276#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
6277#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
6278#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
6279#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
6280#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
6281#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
6282#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
6283#define CLOCKSTOP (1 << 1)
6284#define EOT_DISABLE (1 << 0)
6285
6286#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
6287#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
6288#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
6289#define LP_BYTECLK_SHIFT 0
6290#define LP_BYTECLK_MASK (0xffff << 0)
6291
6292/* bits 31:0 */
6293#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
6294#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
6295#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
6296
6297/* bits 31:0 */
6298#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
6299#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
6300#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
6301
6302#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
6303#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
6304#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
6305#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
6306#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
6307#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
6308#define LONG_PACKET_WORD_COUNT_SHIFT 8
6309#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
6310#define SHORT_PACKET_PARAM_SHIFT 8
6311#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
6312#define VIRTUAL_CHANNEL_SHIFT 6
6313#define VIRTUAL_CHANNEL_MASK (3 << 6)
6314#define DATA_TYPE_SHIFT 0
6315#define DATA_TYPE_MASK (3f << 0)
6316/* data type values, see include/video/mipi_display.h */
6317
6318#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
6319#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
6320#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
6321#define DPI_FIFO_EMPTY (1 << 28)
6322#define DBI_FIFO_EMPTY (1 << 27)
6323#define LP_CTRL_FIFO_EMPTY (1 << 26)
6324#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
6325#define LP_CTRL_FIFO_FULL (1 << 24)
6326#define HS_CTRL_FIFO_EMPTY (1 << 18)
6327#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
6328#define HS_CTRL_FIFO_FULL (1 << 16)
6329#define LP_DATA_FIFO_EMPTY (1 << 10)
6330#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
6331#define LP_DATA_FIFO_FULL (1 << 8)
6332#define HS_DATA_FIFO_EMPTY (1 << 2)
6333#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
6334#define HS_DATA_FIFO_FULL (1 << 0)
6335
6336#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
6337#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
6338#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
6339#define DBI_HS_LP_MODE_MASK (1 << 0)
6340#define DBI_LP_MODE (1 << 0)
6341#define DBI_HS_MODE (0 << 0)
6342
6343#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
6344#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
6345#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
6346#define EXIT_ZERO_COUNT_SHIFT 24
6347#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
6348#define TRAIL_COUNT_SHIFT 16
6349#define TRAIL_COUNT_MASK (0x1f << 16)
6350#define CLK_ZERO_COUNT_SHIFT 8
6351#define CLK_ZERO_COUNT_MASK (0xff << 8)
6352#define PREPARE_COUNT_SHIFT 0
6353#define PREPARE_COUNT_MASK (0x3f << 0)
6354
6355/* bits 31:0 */
6356#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
6357#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
6358#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
6359
6360#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
6361#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
6362#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
6363#define LP_HS_SSW_CNT_SHIFT 16
6364#define LP_HS_SSW_CNT_MASK (0xffff << 16)
6365#define HS_LP_PWR_SW_CNT_SHIFT 0
6366#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
6367
6368#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
6369#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
6370#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
6371#define STOP_STATE_STALL_COUNTER_SHIFT 0
6372#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
6373
6374#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
6375#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
6376#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
6377#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
6378#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
6379#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
6380#define RX_CONTENTION_DETECTED (1 << 0)
6381
6382/* XXX: only pipe A ?!? */
6383#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
6384#define DBI_TYPEC_ENABLE (1 << 31)
6385#define DBI_TYPEC_WIP (1 << 30)
6386#define DBI_TYPEC_OPTION_SHIFT 28
6387#define DBI_TYPEC_OPTION_MASK (3 << 28)
6388#define DBI_TYPEC_FREQ_SHIFT 24
6389#define DBI_TYPEC_FREQ_MASK (0xf << 24)
6390#define DBI_TYPEC_OVERRIDE (1 << 8)
6391#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
6392#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
6393
6394
6395/* MIPI adapter registers */
6396
6397#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
6398#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
6399#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
6400#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
6401#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
6402#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
6403#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
6404#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
6405#define READ_REQUEST_PRIORITY_SHIFT 3
6406#define READ_REQUEST_PRIORITY_MASK (3 << 3)
6407#define READ_REQUEST_PRIORITY_LOW (0 << 3)
6408#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
6409#define RGB_FLIP_TO_BGR (1 << 2)
6410
6411#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
6412#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
6413#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
6414#define DATA_MEM_ADDRESS_SHIFT 5
6415#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
6416#define DATA_VALID (1 << 0)
6417
6418#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
6419#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
6420#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
6421#define DATA_LENGTH_SHIFT 0
6422#define DATA_LENGTH_MASK (0xfffff << 0)
6423
6424#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
6425#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
6426#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
6427#define COMMAND_MEM_ADDRESS_SHIFT 5
6428#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
6429#define AUTO_PWG_ENABLE (1 << 2)
6430#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
6431#define COMMAND_VALID (1 << 0)
6432
6433#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
6434#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
6435#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
6436#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
6437#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
6438
6439#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
6440#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
6441#define MIPI_READ_DATA_RETURN(pipe, n) \
6442 (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
6443
6444#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
6445#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
6446#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
6447#define READ_DATA_VALID(n) (1 << (n))
6448
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006449/* For UMS only (deprecated): */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00006450#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
6451#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
6452#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
6453#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
6454#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
6455#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006456
Jesse Barnes585fb112008-07-29 11:54:06 -07006457#endif /* _I915_REG_H_ */