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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
Ralf Baechle010b8532006-01-29 18:42:08 +00005 * Copyright (C) 1994 - 2006 Ralf Baechle
Ralf Baechle41943182005-05-05 16:45:59 +00006 * Copyright (C) 2003, 2004 Maciej W. Rozycki
Ralf Baechle70342282013-01-22 12:59:30 +01007 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010017#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/stddef.h>
Paul Gortmaker73bc2562011-07-23 16:30:40 -040019#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Ralf Baechle57599062007-02-18 19:07:31 +000021#include <asm/bugs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/cpu.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020023#include <asm/cpu-type.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <asm/fpu.h>
25#include <asm/mipsregs.h>
Paul Burtona5e9a692014-01-27 15:23:10 +000026#include <asm/msa.h>
David Daney654f57b2008-09-23 00:07:16 -070027#include <asm/watch.h>
Paul Gortmaker06372a62011-07-23 16:26:41 -040028#include <asm/elf.h>
Chris Dearmana074f0e2009-07-10 01:51:27 -070029#include <asm/spram.h>
David Daney949e51b2010-10-14 11:32:33 -070030#include <asm/uaccess.h>
31
Paul Gortmaker078a55f2013-06-18 13:38:59 +000032static int mips_fpu_disabled;
Kevin Cernekee0103d232010-05-02 14:43:52 -070033
34static int __init fpu_disable(char *s)
35{
36 cpu_data[0].options &= ~MIPS_CPU_FPU;
37 mips_fpu_disabled = 1;
38
39 return 1;
40}
41
42__setup("nofpu", fpu_disable);
43
Paul Gortmaker078a55f2013-06-18 13:38:59 +000044int mips_dsp_disabled;
Kevin Cernekee0103d232010-05-02 14:43:52 -070045
46static int __init dsp_disable(char *s)
47{
Steven J. Hillee80f7c72012-08-03 10:26:04 -050048 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
Kevin Cernekee0103d232010-05-02 14:43:52 -070049 mips_dsp_disabled = 1;
50
51 return 1;
52}
53
54__setup("nodsp", dsp_disable);
55
Marc St-Jean9267a302007-06-14 15:55:31 -060056static inline void check_errata(void)
57{
58 struct cpuinfo_mips *c = &current_cpu_data;
59
Ralf Baechle69f24d12013-09-17 10:25:47 +020060 switch (current_cpu_type()) {
Marc St-Jean9267a302007-06-14 15:55:31 -060061 case CPU_34K:
62 /*
63 * Erratum "RPS May Cause Incorrect Instruction Execution"
64 * This code only handles VPE0, any SMP/SMTC/RTOS code
65 * making use of VPE1 will be responsable for that VPE.
66 */
67 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
68 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
69 break;
70 default:
71 break;
72 }
73}
74
Linus Torvalds1da177e2005-04-16 15:20:36 -070075void __init check_bugs32(void)
76{
Marc St-Jean9267a302007-06-14 15:55:31 -060077 check_errata();
Linus Torvalds1da177e2005-04-16 15:20:36 -070078}
79
80/*
81 * Probe whether cpu has config register by trying to play with
82 * alternate cache bit and see whether it matters.
83 * It's used by cpu_probe to distinguish between R3000A and R3081.
84 */
85static inline int cpu_has_confreg(void)
86{
87#ifdef CONFIG_CPU_R3000
88 extern unsigned long r3k_cache_size(unsigned long);
89 unsigned long size1, size2;
90 unsigned long cfg = read_c0_conf();
91
92 size1 = r3k_cache_size(ST0_ISC);
93 write_c0_conf(cfg ^ R30XX_CONF_AC);
94 size2 = r3k_cache_size(ST0_ISC);
95 write_c0_conf(cfg);
96 return size1 != size2;
97#else
98 return 0;
99#endif
100}
101
Robert Millanc094c992011-04-18 11:37:55 -0700102static inline void set_elf_platform(int cpu, const char *plat)
103{
104 if (cpu == 0)
105 __elf_platform = plat;
106}
107
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108/*
109 * Get the FPU Implementation/Revision.
110 */
111static inline unsigned long cpu_get_fpu_id(void)
112{
113 unsigned long tmp, fpu_id;
114
115 tmp = read_c0_status();
Paul Burton597ce172013-11-22 13:12:07 +0000116 __enable_fpu(FPU_AS_IS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 fpu_id = read_32bit_cp1_register(CP1_REVISION);
118 write_c0_status(tmp);
119 return fpu_id;
120}
121
122/*
123 * Check the CPU has an FPU the official way.
124 */
125static inline int __cpu_has_fpu(void)
126{
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100127 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128}
129
Paul Burtona5e9a692014-01-27 15:23:10 +0000130static inline unsigned long cpu_get_msa_id(void)
131{
132 unsigned long status, conf5, msa_id;
133
134 status = read_c0_status();
135 __enable_fpu(FPU_64BIT);
136 conf5 = read_c0_config5();
137 enable_msa();
138 msa_id = read_msa_ir();
139 write_c0_config5(conf5);
140 write_c0_status(status);
141 return msa_id;
142}
143
Guenter Roeck91dfc422010-02-02 08:52:20 -0800144static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
145{
146#ifdef __NEED_VMBITS_PROBE
David Daney5b7efa82010-02-08 12:27:00 -0800147 write_c0_entryhi(0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800148 back_to_back_c0_hazard();
David Daney5b7efa82010-02-08 12:27:00 -0800149 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800150#endif
151}
152
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000153static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
Steven J. Hilla96102b2012-12-07 04:31:36 +0000154{
155 switch (isa) {
156 case MIPS_CPU_ISA_M64R2:
157 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
158 case MIPS_CPU_ISA_M64R1:
159 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
160 case MIPS_CPU_ISA_V:
161 c->isa_level |= MIPS_CPU_ISA_V;
162 case MIPS_CPU_ISA_IV:
163 c->isa_level |= MIPS_CPU_ISA_IV;
164 case MIPS_CPU_ISA_III:
Ralf Baechle1990e542013-06-26 17:06:34 +0200165 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
Steven J. Hilla96102b2012-12-07 04:31:36 +0000166 break;
167
168 case MIPS_CPU_ISA_M32R2:
169 c->isa_level |= MIPS_CPU_ISA_M32R2;
170 case MIPS_CPU_ISA_M32R1:
171 c->isa_level |= MIPS_CPU_ISA_M32R1;
172 case MIPS_CPU_ISA_II:
173 c->isa_level |= MIPS_CPU_ISA_II;
Steven J. Hilla96102b2012-12-07 04:31:36 +0000174 break;
175 }
176}
177
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000178static char unknown_isa[] = KERN_ERR \
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100179 "Unsupported ISA type, c0.config0: %d.";
180
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000181static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
182{
183 unsigned int config6;
James Hogand83b0e82014-01-22 16:19:40 +0000184
185 /* It's implementation dependent how the FTLB can be enabled */
186 switch (c->cputype) {
187 case CPU_PROAPTIV:
188 case CPU_P5600:
189 /* proAptiv & related cores use Config6 to enable the FTLB */
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000190 config6 = read_c0_config6();
191 if (enable)
192 /* Enable FTLB */
193 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
194 else
195 /* Disable FTLB */
196 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
197 back_to_back_c0_hazard();
James Hogand83b0e82014-01-22 16:19:40 +0000198 break;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000199 }
200}
201
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100202static inline unsigned int decode_config0(struct cpuinfo_mips *c)
203{
204 unsigned int config0;
205 int isa;
206
207 config0 = read_c0_config();
208
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000209 /*
210 * Look for Standard TLB or Dual VTLB and FTLB
211 */
212 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
213 (((config0 & MIPS_CONF_MT) >> 7) == 4))
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100214 c->options |= MIPS_CPU_TLB;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000215
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100216 isa = (config0 & MIPS_CONF_AT) >> 13;
217 switch (isa) {
218 case 0:
219 switch ((config0 & MIPS_CONF_AR) >> 10) {
220 case 0:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000221 set_isa(c, MIPS_CPU_ISA_M32R1);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100222 break;
223 case 1:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000224 set_isa(c, MIPS_CPU_ISA_M32R2);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100225 break;
226 default:
227 goto unknown;
228 }
229 break;
230 case 2:
231 switch ((config0 & MIPS_CONF_AR) >> 10) {
232 case 0:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000233 set_isa(c, MIPS_CPU_ISA_M64R1);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100234 break;
235 case 1:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000236 set_isa(c, MIPS_CPU_ISA_M64R2);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100237 break;
238 default:
239 goto unknown;
240 }
241 break;
242 default:
243 goto unknown;
244 }
245
246 return config0 & MIPS_CONF_M;
247
248unknown:
249 panic(unknown_isa, config0);
250}
251
252static inline unsigned int decode_config1(struct cpuinfo_mips *c)
253{
254 unsigned int config1;
255
256 config1 = read_c0_config1();
257
258 if (config1 & MIPS_CONF1_MD)
259 c->ases |= MIPS_ASE_MDMX;
260 if (config1 & MIPS_CONF1_WR)
261 c->options |= MIPS_CPU_WATCH;
262 if (config1 & MIPS_CONF1_CA)
263 c->ases |= MIPS_ASE_MIPS16;
264 if (config1 & MIPS_CONF1_EP)
265 c->options |= MIPS_CPU_EJTAG;
266 if (config1 & MIPS_CONF1_FP) {
267 c->options |= MIPS_CPU_FPU;
268 c->options |= MIPS_CPU_32FPR;
269 }
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000270 if (cpu_has_tlb) {
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100271 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000272 c->tlbsizevtlb = c->tlbsize;
273 c->tlbsizeftlbsets = 0;
274 }
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100275
276 return config1 & MIPS_CONF_M;
277}
278
279static inline unsigned int decode_config2(struct cpuinfo_mips *c)
280{
281 unsigned int config2;
282
283 config2 = read_c0_config2();
284
285 if (config2 & MIPS_CONF2_SL)
286 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
287
288 return config2 & MIPS_CONF_M;
289}
290
291static inline unsigned int decode_config3(struct cpuinfo_mips *c)
292{
293 unsigned int config3;
294
295 config3 = read_c0_config3();
296
Steven J. Hillb2ab4f02012-09-13 16:47:58 -0500297 if (config3 & MIPS_CONF3_SM) {
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100298 c->ases |= MIPS_ASE_SMARTMIPS;
Steven J. Hillb2ab4f02012-09-13 16:47:58 -0500299 c->options |= MIPS_CPU_RIXI;
300 }
301 if (config3 & MIPS_CONF3_RXI)
302 c->options |= MIPS_CPU_RIXI;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100303 if (config3 & MIPS_CONF3_DSP)
304 c->ases |= MIPS_ASE_DSP;
Steven J. Hillee80f7c72012-08-03 10:26:04 -0500305 if (config3 & MIPS_CONF3_DSP2P)
306 c->ases |= MIPS_ASE_DSP2P;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100307 if (config3 & MIPS_CONF3_VINT)
308 c->options |= MIPS_CPU_VINT;
309 if (config3 & MIPS_CONF3_VEIC)
310 c->options |= MIPS_CPU_VEIC;
311 if (config3 & MIPS_CONF3_MT)
312 c->ases |= MIPS_ASE_MIPSMT;
313 if (config3 & MIPS_CONF3_ULRI)
314 c->options |= MIPS_CPU_ULRI;
Steven J. Hillf8fa4812012-12-07 03:51:35 +0000315 if (config3 & MIPS_CONF3_ISA)
316 c->options |= MIPS_CPU_MICROMIPS;
David Daney1e7decd2013-02-16 23:42:43 +0100317 if (config3 & MIPS_CONF3_VZ)
318 c->ases |= MIPS_ASE_VZ;
Steven J. Hill4a0156f2013-11-14 16:12:24 +0000319 if (config3 & MIPS_CONF3_SC)
320 c->options |= MIPS_CPU_SEGMENTS;
Paul Burtona5e9a692014-01-27 15:23:10 +0000321 if (config3 & MIPS_CONF3_MSA)
322 c->ases |= MIPS_ASE_MSA;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100323
324 return config3 & MIPS_CONF_M;
325}
326
327static inline unsigned int decode_config4(struct cpuinfo_mips *c)
328{
329 unsigned int config4;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000330 unsigned int newcf4;
331 unsigned int mmuextdef;
332 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100333
334 config4 = read_c0_config4();
335
Leonid Yegoshin1745c1e2013-11-14 16:12:23 +0000336 if (cpu_has_tlb) {
337 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
338 c->options |= MIPS_CPU_TLBINV;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000339 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
340 switch (mmuextdef) {
341 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
342 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
343 c->tlbsizevtlb = c->tlbsize;
344 break;
345 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
346 c->tlbsizevtlb +=
347 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
348 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
349 c->tlbsize = c->tlbsizevtlb;
350 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
351 /* fall through */
352 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
353 newcf4 = (config4 & ~ftlb_page) |
354 (page_size_ftlb(mmuextdef) <<
355 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
356 write_c0_config4(newcf4);
357 back_to_back_c0_hazard();
358 config4 = read_c0_config4();
359 if (config4 != newcf4) {
360 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
361 PAGE_SIZE, config4);
362 /* Switch FTLB off */
363 set_ftlb_enable(c, 0);
364 break;
365 }
366 c->tlbsizeftlbsets = 1 <<
367 ((config4 & MIPS_CONF4_FTLBSETS) >>
368 MIPS_CONF4_FTLBSETS_SHIFT);
369 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
370 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
371 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
372 break;
373 }
Leonid Yegoshin1745c1e2013-11-14 16:12:23 +0000374 }
375
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100376 c->kscratch_mask = (config4 >> 16) & 0xff;
377
378 return config4 & MIPS_CONF_M;
379}
380
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200381static inline unsigned int decode_config5(struct cpuinfo_mips *c)
382{
383 unsigned int config5;
384
385 config5 = read_c0_config5();
386 config5 &= ~MIPS_CONF5_UFR;
387 write_c0_config5(config5);
388
Markos Chandras49016742014-01-09 16:04:51 +0000389 if (config5 & MIPS_CONF5_EVA)
390 c->options |= MIPS_CPU_EVA;
391
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200392 return config5 & MIPS_CONF_M;
393}
394
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000395static void decode_configs(struct cpuinfo_mips *c)
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100396{
397 int ok;
398
399 /* MIPS32 or MIPS64 compliant CPU. */
400 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
401 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
402
403 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
404
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000405 /* Enable FTLB if present */
406 set_ftlb_enable(c, 1);
407
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100408 ok = decode_config0(c); /* Read Config registers. */
Ralf Baechle70342282013-01-22 12:59:30 +0100409 BUG_ON(!ok); /* Arch spec violation! */
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100410 if (ok)
411 ok = decode_config1(c);
412 if (ok)
413 ok = decode_config2(c);
414 if (ok)
415 ok = decode_config3(c);
416 if (ok)
417 ok = decode_config4(c);
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200418 if (ok)
419 ok = decode_config5(c);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100420
421 mips_probe_watch_registers(c);
422
Paul Burton0ee958e2014-01-15 10:31:53 +0000423#ifndef CONFIG_MIPS_CPS
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100424 if (cpu_has_mips_r2)
425 c->core = read_c0_ebase() & 0x3ff;
Paul Burton0ee958e2014-01-15 10:31:53 +0000426#endif
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100427}
428
Ralf Baechle02cf2112005-10-01 13:06:32 +0100429#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 | MIPS_CPU_COUNTER)
431
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000432static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433{
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100434 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 case PRID_IMP_R2000:
436 c->cputype = CPU_R2000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000437 __cpu_name[cpu] = "R2000";
Ralf Baechle02cf2112005-10-01 13:06:32 +0100438 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500439 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440 if (__cpu_has_fpu())
441 c->options |= MIPS_CPU_FPU;
442 c->tlbsize = 64;
443 break;
444 case PRID_IMP_R3000:
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100445 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000446 if (cpu_has_confreg()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 c->cputype = CPU_R3081E;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000448 __cpu_name[cpu] = "R3081";
449 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 c->cputype = CPU_R3000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000451 __cpu_name[cpu] = "R3000A";
452 }
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000453 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 c->cputype = CPU_R3000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000455 __cpu_name[cpu] = "R3000";
456 }
Ralf Baechle02cf2112005-10-01 13:06:32 +0100457 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500458 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 if (__cpu_has_fpu())
460 c->options |= MIPS_CPU_FPU;
461 c->tlbsize = 64;
462 break;
463 case PRID_IMP_R4000:
464 if (read_c0_config() & CONF_SC) {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100465 if ((c->processor_id & PRID_REV_MASK) >=
466 PRID_REV_R4400) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467 c->cputype = CPU_R4400PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000468 __cpu_name[cpu] = "R4400PC";
469 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 c->cputype = CPU_R4000PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000471 __cpu_name[cpu] = "R4000PC";
472 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 } else {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100474 int cca = read_c0_config() & CONF_CM_CMASK;
475 int mc;
476
477 /*
478 * SC and MC versions can't be reliably told apart,
479 * but only the latter support coherent caching
480 * modes so assume the firmware has set the KSEG0
481 * coherency attribute reasonably (if uncached, we
482 * assume SC).
483 */
484 switch (cca) {
485 case CONF_CM_CACHABLE_CE:
486 case CONF_CM_CACHABLE_COW:
487 case CONF_CM_CACHABLE_CUW:
488 mc = 1;
489 break;
490 default:
491 mc = 0;
492 break;
493 }
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100494 if ((c->processor_id & PRID_REV_MASK) >=
495 PRID_REV_R4400) {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100496 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
497 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000498 } else {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100499 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
500 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000501 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 }
503
Steven J. Hilla96102b2012-12-07 04:31:36 +0000504 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500506 MIPS_CPU_WATCH | MIPS_CPU_VCE |
507 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 c->tlbsize = 48;
509 break;
510 case PRID_IMP_VR41XX:
Yoichi Yuasa9f91e502013-02-21 15:38:19 +0900511 set_isa(c, MIPS_CPU_ISA_III);
512 c->options = R4K_OPTS;
513 c->tlbsize = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 switch (c->processor_id & 0xf0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 case PRID_REV_VR4111:
516 c->cputype = CPU_VR4111;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000517 __cpu_name[cpu] = "NEC VR4111";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 case PRID_REV_VR4121:
520 c->cputype = CPU_VR4121;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000521 __cpu_name[cpu] = "NEC VR4121";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522 break;
523 case PRID_REV_VR4122:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000524 if ((c->processor_id & 0xf) < 0x3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 c->cputype = CPU_VR4122;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000526 __cpu_name[cpu] = "NEC VR4122";
527 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 c->cputype = CPU_VR4181A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000529 __cpu_name[cpu] = "NEC VR4181A";
530 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531 break;
532 case PRID_REV_VR4130:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000533 if ((c->processor_id & 0xf) < 0x4) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 c->cputype = CPU_VR4131;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000535 __cpu_name[cpu] = "NEC VR4131";
536 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 c->cputype = CPU_VR4133;
Yoichi Yuasa9f91e502013-02-21 15:38:19 +0900538 c->options |= MIPS_CPU_LLSC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000539 __cpu_name[cpu] = "NEC VR4133";
540 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 break;
542 default:
543 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
544 c->cputype = CPU_VR41XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000545 __cpu_name[cpu] = "NEC Vr41xx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546 break;
547 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548 break;
549 case PRID_IMP_R4300:
550 c->cputype = CPU_R4300;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000551 __cpu_name[cpu] = "R4300";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000552 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500554 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555 c->tlbsize = 32;
556 break;
557 case PRID_IMP_R4600:
558 c->cputype = CPU_R4600;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000559 __cpu_name[cpu] = "R4600";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000560 set_isa(c, MIPS_CPU_ISA_III);
Thiemo Seufer075e7502005-07-27 21:48:12 +0000561 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
562 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 c->tlbsize = 48;
564 break;
565 #if 0
Steven J. Hill03751e72012-05-10 23:21:18 -0500566 case PRID_IMP_R4650:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 /*
568 * This processor doesn't have an MMU, so it's not
569 * "real easy" to run Linux on it. It is left purely
570 * for documentation. Commented out because it shares
571 * it's c0_prid id number with the TX3900.
572 */
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000573 c->cputype = CPU_R4650;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000574 __cpu_name[cpu] = "R4650";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000575 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
Steven J. Hill03751e72012-05-10 23:21:18 -0500577 c->tlbsize = 48;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 break;
579 #endif
580 case PRID_IMP_TX39:
Ralf Baechle02cf2112005-10-01 13:06:32 +0100581 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582
583 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
584 c->cputype = CPU_TX3927;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000585 __cpu_name[cpu] = "TX3927";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 c->tlbsize = 64;
587 } else {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100588 switch (c->processor_id & PRID_REV_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589 case PRID_REV_TX3912:
590 c->cputype = CPU_TX3912;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000591 __cpu_name[cpu] = "TX3912";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 c->tlbsize = 32;
593 break;
594 case PRID_REV_TX3922:
595 c->cputype = CPU_TX3922;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000596 __cpu_name[cpu] = "TX3922";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 c->tlbsize = 64;
598 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599 }
600 }
601 break;
602 case PRID_IMP_R4700:
603 c->cputype = CPU_R4700;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000604 __cpu_name[cpu] = "R4700";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000605 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500607 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608 c->tlbsize = 48;
609 break;
610 case PRID_IMP_TX49:
611 c->cputype = CPU_TX49XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000612 __cpu_name[cpu] = "R49XX";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000613 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 c->options = R4K_OPTS | MIPS_CPU_LLSC;
615 if (!(c->processor_id & 0x08))
616 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
617 c->tlbsize = 48;
618 break;
619 case PRID_IMP_R5000:
620 c->cputype = CPU_R5000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000621 __cpu_name[cpu] = "R5000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000622 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500624 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 c->tlbsize = 48;
626 break;
627 case PRID_IMP_R5432:
628 c->cputype = CPU_R5432;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000629 __cpu_name[cpu] = "R5432";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000630 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500632 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 c->tlbsize = 48;
634 break;
635 case PRID_IMP_R5500:
636 c->cputype = CPU_R5500;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000637 __cpu_name[cpu] = "R5500";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000638 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500640 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 c->tlbsize = 48;
642 break;
643 case PRID_IMP_NEVADA:
644 c->cputype = CPU_NEVADA;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000645 __cpu_name[cpu] = "Nevada";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000646 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500648 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 c->tlbsize = 48;
650 break;
651 case PRID_IMP_R6000:
652 c->cputype = CPU_R6000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000653 __cpu_name[cpu] = "R6000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000654 set_isa(c, MIPS_CPU_ISA_II);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500656 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 c->tlbsize = 32;
658 break;
659 case PRID_IMP_R6000A:
660 c->cputype = CPU_R6000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000661 __cpu_name[cpu] = "R6000A";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000662 set_isa(c, MIPS_CPU_ISA_II);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500664 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 c->tlbsize = 32;
666 break;
667 case PRID_IMP_RM7000:
668 c->cputype = CPU_RM7000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000669 __cpu_name[cpu] = "RM7000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000670 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500672 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 /*
Ralf Baechle70342282013-01-22 12:59:30 +0100674 * Undocumented RM7000: Bit 29 in the info register of
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 * the RM7000 v2.0 indicates if the TLB has 48 or 64
676 * entries.
677 *
Ralf Baechle70342282013-01-22 12:59:30 +0100678 * 29 1 => 64 entry JTLB
679 * 0 => 48 entry JTLB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 */
681 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
682 break;
683 case PRID_IMP_RM9000:
684 c->cputype = CPU_RM9000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000685 __cpu_name[cpu] = "RM9000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000686 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500688 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 /*
690 * Bit 29 in the info register of the RM9000
691 * indicates if the TLB has 48 or 64 entries.
692 *
Ralf Baechle70342282013-01-22 12:59:30 +0100693 * 29 1 => 64 entry JTLB
694 * 0 => 48 entry JTLB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 */
696 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
697 break;
698 case PRID_IMP_R8000:
699 c->cputype = CPU_R8000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000700 __cpu_name[cpu] = "RM8000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000701 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500703 MIPS_CPU_FPU | MIPS_CPU_32FPR |
704 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
706 break;
707 case PRID_IMP_R10000:
708 c->cputype = CPU_R10000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000709 __cpu_name[cpu] = "R10000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000710 set_isa(c, MIPS_CPU_ISA_IV);
Ralf Baechle8b366122005-11-22 17:53:59 +0000711 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500712 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500714 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715 c->tlbsize = 64;
716 break;
717 case PRID_IMP_R12000:
718 c->cputype = CPU_R12000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000719 __cpu_name[cpu] = "R12000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000720 set_isa(c, MIPS_CPU_ISA_IV);
Ralf Baechle8b366122005-11-22 17:53:59 +0000721 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500722 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500724 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725 c->tlbsize = 64;
726 break;
Kumba44d921b2006-05-16 22:23:59 -0400727 case PRID_IMP_R14000:
728 c->cputype = CPU_R14000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000729 __cpu_name[cpu] = "R14000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000730 set_isa(c, MIPS_CPU_ISA_IV);
Kumba44d921b2006-05-16 22:23:59 -0400731 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500732 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Kumba44d921b2006-05-16 22:23:59 -0400733 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500734 MIPS_CPU_LLSC;
Kumba44d921b2006-05-16 22:23:59 -0400735 c->tlbsize = 64;
736 break;
Huacai Chen26859192014-02-16 16:01:18 +0800737 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
Robert Millan5aac1e82011-04-16 11:29:29 -0700738 switch (c->processor_id & PRID_REV_MASK) {
739 case PRID_REV_LOONGSON2E:
Huacai Chenc579d312014-03-21 18:44:00 +0800740 c->cputype = CPU_LOONGSON2;
741 __cpu_name[cpu] = "ICT Loongson-2";
Robert Millan5aac1e82011-04-16 11:29:29 -0700742 set_elf_platform(cpu, "loongson2e");
743 break;
744 case PRID_REV_LOONGSON2F:
Huacai Chenc579d312014-03-21 18:44:00 +0800745 c->cputype = CPU_LOONGSON2;
746 __cpu_name[cpu] = "ICT Loongson-2";
Robert Millan5aac1e82011-04-16 11:29:29 -0700747 set_elf_platform(cpu, "loongson2f");
748 break;
Huacai Chenc579d312014-03-21 18:44:00 +0800749 case PRID_REV_LOONGSON3A:
750 c->cputype = CPU_LOONGSON3;
751 __cpu_name[cpu] = "ICT Loongson-3";
752 set_elf_platform(cpu, "loongson3a");
753 break;
Robert Millan5aac1e82011-04-16 11:29:29 -0700754 }
755
Steven J. Hilla96102b2012-12-07 04:31:36 +0000756 set_isa(c, MIPS_CPU_ISA_III);
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800757 c->options = R4K_OPTS |
758 MIPS_CPU_FPU | MIPS_CPU_LLSC |
759 MIPS_CPU_32FPR;
760 c->tlbsize = 64;
761 break;
Huacai Chen26859192014-02-16 16:01:18 +0800762 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100763 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100765 c->cputype = CPU_LOONGSON1;
Ralf Baechleb4672d32005-12-08 14:04:24 +0000766
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100767 switch (c->processor_id & PRID_REV_MASK) {
768 case PRID_REV_LOONGSON1B:
769 __cpu_name[cpu] = "Loongson 1B";
Ralf Baechleb4672d32005-12-08 14:04:24 +0000770 break;
Ralf Baechleb4672d32005-12-08 14:04:24 +0000771 }
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100772
Ralf Baechle41943182005-05-05 16:45:59 +0000773 break;
Ralf Baechle41943182005-05-05 16:45:59 +0000774 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775}
776
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000777static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778{
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100779 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 case PRID_IMP_4KC:
781 c->cputype = CPU_4KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000782 __cpu_name[cpu] = "MIPS 4Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 break;
784 case PRID_IMP_4KEC:
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000785 case PRID_IMP_4KECR2:
786 c->cputype = CPU_4KEC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000787 __cpu_name[cpu] = "MIPS 4KEc";
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000788 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789 case PRID_IMP_4KSC:
Ralf Baechle8afcb5d2005-10-04 15:01:26 +0100790 case PRID_IMP_4KSD:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791 c->cputype = CPU_4KSC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000792 __cpu_name[cpu] = "MIPS 4KSc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 break;
794 case PRID_IMP_5KC:
795 c->cputype = CPU_5KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000796 __cpu_name[cpu] = "MIPS 5Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 break;
Leonid Yegoshin78d48032012-07-06 21:56:01 +0200798 case PRID_IMP_5KE:
799 c->cputype = CPU_5KE;
800 __cpu_name[cpu] = "MIPS 5KE";
801 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 case PRID_IMP_20KC:
803 c->cputype = CPU_20KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000804 __cpu_name[cpu] = "MIPS 20Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805 break;
806 case PRID_IMP_24K:
807 c->cputype = CPU_24K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000808 __cpu_name[cpu] = "MIPS 24Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 break;
John Crispin42f3cae2013-01-11 22:44:10 +0100810 case PRID_IMP_24KE:
811 c->cputype = CPU_24K;
812 __cpu_name[cpu] = "MIPS 24KEc";
813 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 case PRID_IMP_25KF:
815 c->cputype = CPU_25KF;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000816 __cpu_name[cpu] = "MIPS 25Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 break;
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000818 case PRID_IMP_34K:
819 c->cputype = CPU_34K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000820 __cpu_name[cpu] = "MIPS 34Kc";
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000821 break;
Chris Dearmanc6209532006-05-02 14:08:46 +0100822 case PRID_IMP_74K:
823 c->cputype = CPU_74K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000824 __cpu_name[cpu] = "MIPS 74Kc";
Chris Dearmanc6209532006-05-02 14:08:46 +0100825 break;
Steven J. Hill113c62d2012-07-06 23:56:00 +0200826 case PRID_IMP_M14KC:
827 c->cputype = CPU_M14KC;
828 __cpu_name[cpu] = "MIPS M14Kc";
829 break;
Steven J. Hillf8fa4812012-12-07 03:51:35 +0000830 case PRID_IMP_M14KEC:
831 c->cputype = CPU_M14KEC;
832 __cpu_name[cpu] = "MIPS M14KEc";
833 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100834 case PRID_IMP_1004K:
835 c->cputype = CPU_1004K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000836 __cpu_name[cpu] = "MIPS 1004Kc";
Ralf Baechle39b8d522008-04-28 17:14:26 +0100837 break;
Steven J. Hill006a8512012-06-26 04:11:03 +0000838 case PRID_IMP_1074K:
Steven J. Hill442e14a2014-01-17 15:03:50 -0600839 c->cputype = CPU_1074K;
Steven J. Hill006a8512012-06-26 04:11:03 +0000840 __cpu_name[cpu] = "MIPS 1074Kc";
841 break;
Leonid Yegoshinb5f065e2013-11-20 10:46:02 +0000842 case PRID_IMP_INTERAPTIV_UP:
843 c->cputype = CPU_INTERAPTIV;
844 __cpu_name[cpu] = "MIPS interAptiv";
845 break;
846 case PRID_IMP_INTERAPTIV_MP:
847 c->cputype = CPU_INTERAPTIV;
848 __cpu_name[cpu] = "MIPS interAptiv (multi)";
849 break;
Leonid Yegoshinb0d4d302013-11-14 16:12:28 +0000850 case PRID_IMP_PROAPTIV_UP:
851 c->cputype = CPU_PROAPTIV;
852 __cpu_name[cpu] = "MIPS proAptiv";
853 break;
854 case PRID_IMP_PROAPTIV_MP:
855 c->cputype = CPU_PROAPTIV;
856 __cpu_name[cpu] = "MIPS proAptiv (multi)";
857 break;
James Hogan829dcc02014-01-22 16:19:39 +0000858 case PRID_IMP_P5600:
859 c->cputype = CPU_P5600;
860 __cpu_name[cpu] = "MIPS P5600";
861 break;
Leonid Yegoshin9943ed92014-03-04 13:34:44 +0000862 case PRID_IMP_M5150:
863 c->cputype = CPU_M5150;
864 __cpu_name[cpu] = "MIPS M5150";
865 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866 }
Chris Dearman0b6d4972007-09-13 12:32:02 +0100867
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000868 decode_configs(c);
869
Chris Dearman0b6d4972007-09-13 12:32:02 +0100870 spram_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871}
872
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000873static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874{
Ralf Baechle41943182005-05-05 16:45:59 +0000875 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100876 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877 case PRID_IMP_AU1_REV1:
878 case PRID_IMP_AU1_REV2:
Manuel Lauss270717a2009-03-25 17:49:28 +0100879 c->cputype = CPU_ALCHEMY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880 switch ((c->processor_id >> 24) & 0xff) {
881 case 0:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000882 __cpu_name[cpu] = "Au1000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 break;
884 case 1:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000885 __cpu_name[cpu] = "Au1500";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 break;
887 case 2:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000888 __cpu_name[cpu] = "Au1100";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889 break;
890 case 3:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000891 __cpu_name[cpu] = "Au1550";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 break;
Pete Popove3ad1c22005-03-01 06:33:16 +0000893 case 4:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000894 __cpu_name[cpu] = "Au1200";
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100895 if ((c->processor_id & PRID_REV_MASK) == 2)
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000896 __cpu_name[cpu] = "Au1250";
Manuel Lauss237cfee2007-12-06 09:07:55 +0100897 break;
898 case 5:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000899 __cpu_name[cpu] = "Au1210";
Pete Popove3ad1c22005-03-01 06:33:16 +0000900 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 default:
Manuel Lauss270717a2009-03-25 17:49:28 +0100902 __cpu_name[cpu] = "Au1xxx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903 break;
904 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 break;
906 }
907}
908
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000909static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910{
Ralf Baechle41943182005-05-05 16:45:59 +0000911 decode_configs(c);
Ralf Baechle02cf2112005-10-01 13:06:32 +0100912
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100913 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 case PRID_IMP_SB1:
915 c->cputype = CPU_SB1;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000916 __cpu_name[cpu] = "SiByte SB1";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917 /* FPU in pass1 is known to have issues. */
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100918 if ((c->processor_id & PRID_REV_MASK) < 0x02)
Ralf Baechle010b8532006-01-29 18:42:08 +0000919 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 break;
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700921 case PRID_IMP_SB1A:
922 c->cputype = CPU_SB1A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000923 __cpu_name[cpu] = "SiByte SB1A";
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700924 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 }
926}
927
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000928static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929{
Ralf Baechle41943182005-05-05 16:45:59 +0000930 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100931 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932 case PRID_IMP_SR71000:
933 c->cputype = CPU_SR71000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000934 __cpu_name[cpu] = "Sandcraft SR71000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935 c->scache.ways = 8;
936 c->tlbsize = 64;
937 break;
938 }
939}
940
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000941static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
Pete Popovbdf21b12005-07-14 17:47:57 +0000942{
943 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100944 switch (c->processor_id & PRID_IMP_MASK) {
Pete Popovbdf21b12005-07-14 17:47:57 +0000945 case PRID_IMP_PR4450:
946 c->cputype = CPU_PR4450;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000947 __cpu_name[cpu] = "Philips PR4450";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000948 set_isa(c, MIPS_CPU_ISA_M32R1);
Pete Popovbdf21b12005-07-14 17:47:57 +0000949 break;
Pete Popovbdf21b12005-07-14 17:47:57 +0000950 }
951}
952
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000953static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200954{
955 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100956 switch (c->processor_id & PRID_IMP_MASK) {
Kevin Cernekee190fca32010-11-23 10:26:45 -0800957 case PRID_IMP_BMIPS32_REV4:
958 case PRID_IMP_BMIPS32_REV8:
Kevin Cernekee602977b2010-10-16 14:22:30 -0700959 c->cputype = CPU_BMIPS32;
960 __cpu_name[cpu] = "Broadcom BMIPS32";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700961 set_elf_platform(cpu, "bmips32");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200962 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700963 case PRID_IMP_BMIPS3300:
964 case PRID_IMP_BMIPS3300_ALT:
965 case PRID_IMP_BMIPS3300_BUG:
966 c->cputype = CPU_BMIPS3300;
967 __cpu_name[cpu] = "Broadcom BMIPS3300";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700968 set_elf_platform(cpu, "bmips3300");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200969 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700970 case PRID_IMP_BMIPS43XX: {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100971 int rev = c->processor_id & PRID_REV_MASK;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700972
973 if (rev >= PRID_REV_BMIPS4380_LO &&
974 rev <= PRID_REV_BMIPS4380_HI) {
975 c->cputype = CPU_BMIPS4380;
976 __cpu_name[cpu] = "Broadcom BMIPS4380";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700977 set_elf_platform(cpu, "bmips4380");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700978 } else {
979 c->cputype = CPU_BMIPS4350;
980 __cpu_name[cpu] = "Broadcom BMIPS4350";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700981 set_elf_platform(cpu, "bmips4350");
Maxime Bizon0de663e2009-08-18 13:23:37 +0100982 }
983 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200984 }
Kevin Cernekee602977b2010-10-16 14:22:30 -0700985 case PRID_IMP_BMIPS5000:
986 c->cputype = CPU_BMIPS5000;
987 __cpu_name[cpu] = "Broadcom BMIPS5000";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700988 set_elf_platform(cpu, "bmips5000");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700989 c->options |= MIPS_CPU_ULRI;
990 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700991 }
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200992}
993
David Daney0dd47812008-12-11 15:33:26 -0800994static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
995{
996 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100997 switch (c->processor_id & PRID_IMP_MASK) {
David Daney0dd47812008-12-11 15:33:26 -0800998 case PRID_IMP_CAVIUM_CN38XX:
999 case PRID_IMP_CAVIUM_CN31XX:
1000 case PRID_IMP_CAVIUM_CN30XX:
David Daney6f329462010-02-10 15:12:48 -08001001 c->cputype = CPU_CAVIUM_OCTEON;
1002 __cpu_name[cpu] = "Cavium Octeon";
1003 goto platform;
David Daney0dd47812008-12-11 15:33:26 -08001004 case PRID_IMP_CAVIUM_CN58XX:
1005 case PRID_IMP_CAVIUM_CN56XX:
1006 case PRID_IMP_CAVIUM_CN50XX:
1007 case PRID_IMP_CAVIUM_CN52XX:
David Daney6f329462010-02-10 15:12:48 -08001008 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1009 __cpu_name[cpu] = "Cavium Octeon+";
1010platform:
Robert Millanc094c992011-04-18 11:37:55 -07001011 set_elf_platform(cpu, "octeon");
David Daney0dd47812008-12-11 15:33:26 -08001012 break;
David Daneya1431b62011-09-24 02:29:54 +02001013 case PRID_IMP_CAVIUM_CN61XX:
David Daney0e56b382010-10-07 16:03:45 -07001014 case PRID_IMP_CAVIUM_CN63XX:
David Daneya1431b62011-09-24 02:29:54 +02001015 case PRID_IMP_CAVIUM_CN66XX:
1016 case PRID_IMP_CAVIUM_CN68XX:
David Daneyaf04bb82013-07-29 15:07:01 -07001017 case PRID_IMP_CAVIUM_CNF71XX:
David Daney0e56b382010-10-07 16:03:45 -07001018 c->cputype = CPU_CAVIUM_OCTEON2;
1019 __cpu_name[cpu] = "Cavium Octeon II";
Robert Millanc094c992011-04-18 11:37:55 -07001020 set_elf_platform(cpu, "octeon2");
David Daney0e56b382010-10-07 16:03:45 -07001021 break;
David Daneyaf04bb82013-07-29 15:07:01 -07001022 case PRID_IMP_CAVIUM_CN70XX:
1023 case PRID_IMP_CAVIUM_CN78XX:
1024 c->cputype = CPU_CAVIUM_OCTEON3;
1025 __cpu_name[cpu] = "Cavium Octeon III";
1026 set_elf_platform(cpu, "octeon3");
1027 break;
David Daney0dd47812008-12-11 15:33:26 -08001028 default:
1029 printk(KERN_INFO "Unknown Octeon chip!\n");
1030 c->cputype = CPU_UNKNOWN;
1031 break;
1032 }
1033}
1034
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001035static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1036{
1037 decode_configs(c);
1038 /* JZRISC does not implement the CP0 counter. */
1039 c->options &= ~MIPS_CPU_COUNTER;
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001040 switch (c->processor_id & PRID_IMP_MASK) {
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001041 case PRID_IMP_JZRISC:
1042 c->cputype = CPU_JZRISC;
1043 __cpu_name[cpu] = "Ingenic JZRISC";
1044 break;
1045 default:
1046 panic("Unknown Ingenic Processor ID!");
1047 break;
1048 }
1049}
1050
Jayachandran Ca7117c62011-05-11 12:04:58 +05301051static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1052{
1053 decode_configs(c);
1054
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001055 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
Manuel Lauss809f36c2011-11-01 20:03:30 +01001056 c->cputype = CPU_ALCHEMY;
1057 __cpu_name[cpu] = "Au1300";
1058 /* following stuff is not for Alchemy */
1059 return;
1060 }
1061
Ralf Baechle70342282013-01-22 12:59:30 +01001062 c->options = (MIPS_CPU_TLB |
1063 MIPS_CPU_4KEX |
Jayachandran Ca7117c62011-05-11 12:04:58 +05301064 MIPS_CPU_COUNTER |
Ralf Baechle70342282013-01-22 12:59:30 +01001065 MIPS_CPU_DIVEC |
1066 MIPS_CPU_WATCH |
1067 MIPS_CPU_EJTAG |
Jayachandran Ca7117c62011-05-11 12:04:58 +05301068 MIPS_CPU_LLSC);
1069
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001070 switch (c->processor_id & PRID_IMP_MASK) {
Jayachandran C4ca86a22013-08-11 14:43:54 +05301071 case PRID_IMP_NETLOGIC_XLP2XX:
Jayachandran C8907c552013-12-21 16:52:20 +05301072 case PRID_IMP_NETLOGIC_XLP9XX:
Jayachandran C4ca86a22013-08-11 14:43:54 +05301073 c->cputype = CPU_XLP;
1074 __cpu_name[cpu] = "Broadcom XLPII";
1075 break;
1076
Jayachandran C2aa54b22011-11-16 00:21:29 +00001077 case PRID_IMP_NETLOGIC_XLP8XX:
1078 case PRID_IMP_NETLOGIC_XLP3XX:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001079 c->cputype = CPU_XLP;
1080 __cpu_name[cpu] = "Netlogic XLP";
1081 break;
1082
Jayachandran Ca7117c62011-05-11 12:04:58 +05301083 case PRID_IMP_NETLOGIC_XLR732:
1084 case PRID_IMP_NETLOGIC_XLR716:
1085 case PRID_IMP_NETLOGIC_XLR532:
1086 case PRID_IMP_NETLOGIC_XLR308:
1087 case PRID_IMP_NETLOGIC_XLR532C:
1088 case PRID_IMP_NETLOGIC_XLR516C:
1089 case PRID_IMP_NETLOGIC_XLR508C:
1090 case PRID_IMP_NETLOGIC_XLR308C:
1091 c->cputype = CPU_XLR;
1092 __cpu_name[cpu] = "Netlogic XLR";
1093 break;
1094
1095 case PRID_IMP_NETLOGIC_XLS608:
1096 case PRID_IMP_NETLOGIC_XLS408:
1097 case PRID_IMP_NETLOGIC_XLS404:
1098 case PRID_IMP_NETLOGIC_XLS208:
1099 case PRID_IMP_NETLOGIC_XLS204:
1100 case PRID_IMP_NETLOGIC_XLS108:
1101 case PRID_IMP_NETLOGIC_XLS104:
1102 case PRID_IMP_NETLOGIC_XLS616B:
1103 case PRID_IMP_NETLOGIC_XLS608B:
1104 case PRID_IMP_NETLOGIC_XLS416B:
1105 case PRID_IMP_NETLOGIC_XLS412B:
1106 case PRID_IMP_NETLOGIC_XLS408B:
1107 case PRID_IMP_NETLOGIC_XLS404B:
1108 c->cputype = CPU_XLR;
1109 __cpu_name[cpu] = "Netlogic XLS";
1110 break;
1111
1112 default:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001113 pr_info("Unknown Netlogic chip id [%02x]!\n",
Jayachandran Ca7117c62011-05-11 12:04:58 +05301114 c->processor_id);
1115 c->cputype = CPU_XLR;
1116 break;
1117 }
1118
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001119 if (c->cputype == CPU_XLP) {
Steven J. Hilla96102b2012-12-07 04:31:36 +00001120 set_isa(c, MIPS_CPU_ISA_M64R2);
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001121 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1122 /* This will be updated again after all threads are woken up */
1123 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1124 } else {
Steven J. Hilla96102b2012-12-07 04:31:36 +00001125 set_isa(c, MIPS_CPU_ISA_M64R1);
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001126 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1127 }
Jayachandran C7777b932013-06-11 14:41:35 +00001128 c->kscratch_mask = 0xf;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301129}
1130
David Daney949e51b2010-10-14 11:32:33 -07001131#ifdef CONFIG_64BIT
1132/* For use by uaccess.h */
1133u64 __ua_limit;
1134EXPORT_SYMBOL(__ua_limit);
1135#endif
1136
Ralf Baechle9966db252007-10-11 23:46:17 +01001137const char *__cpu_name[NR_CPUS];
David Daney874fd3b2010-01-28 16:52:12 -08001138const char *__elf_platform;
Ralf Baechle9966db252007-10-11 23:46:17 +01001139
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001140void cpu_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141{
1142 struct cpuinfo_mips *c = &current_cpu_data;
Ralf Baechle9966db252007-10-11 23:46:17 +01001143 unsigned int cpu = smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144
Ralf Baechle70342282013-01-22 12:59:30 +01001145 c->processor_id = PRID_IMP_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 c->fpu_id = FPIR_IMP_NONE;
1147 c->cputype = CPU_UNKNOWN;
1148
1149 c->processor_id = read_c0_prid();
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001150 switch (c->processor_id & PRID_COMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 case PRID_COMP_LEGACY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001152 cpu_probe_legacy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153 break;
1154 case PRID_COMP_MIPS:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001155 cpu_probe_mips(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 break;
1157 case PRID_COMP_ALCHEMY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001158 cpu_probe_alchemy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159 break;
1160 case PRID_COMP_SIBYTE:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001161 cpu_probe_sibyte(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001162 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001163 case PRID_COMP_BROADCOM:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001164 cpu_probe_broadcom(c, cpu);
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001165 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166 case PRID_COMP_SANDCRAFT:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001167 cpu_probe_sandcraft(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168 break;
Daniel Lairda92b0582008-03-06 09:07:18 +00001169 case PRID_COMP_NXP:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001170 cpu_probe_nxp(c, cpu);
Ralf Baechlea3dddd52006-03-11 08:18:41 +00001171 break;
David Daney0dd47812008-12-11 15:33:26 -08001172 case PRID_COMP_CAVIUM:
1173 cpu_probe_cavium(c, cpu);
1174 break;
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001175 case PRID_COMP_INGENIC:
1176 cpu_probe_ingenic(c, cpu);
1177 break;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301178 case PRID_COMP_NETLOGIC:
1179 cpu_probe_netlogic(c, cpu);
1180 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 }
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001182
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001183 BUG_ON(!__cpu_name[cpu]);
1184 BUG_ON(c->cputype == CPU_UNKNOWN);
1185
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001186 /*
1187 * Platform code can force the cpu type to optimize code
1188 * generation. In that case be sure the cpu type is correctly
1189 * manually setup otherwise it could trigger some nasty bugs.
1190 */
1191 BUG_ON(current_cpu_type() != c->cputype);
1192
Kevin Cernekee0103d232010-05-02 14:43:52 -07001193 if (mips_fpu_disabled)
1194 c->options &= ~MIPS_CPU_FPU;
1195
1196 if (mips_dsp_disabled)
Steven J. Hillee80f7c72012-08-03 10:26:04 -05001197 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
Kevin Cernekee0103d232010-05-02 14:43:52 -07001198
Ralf Baechle41943182005-05-05 16:45:59 +00001199 if (c->options & MIPS_CPU_FPU) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200 c->fpu_id = cpu_get_fpu_id();
Ralf Baechle41943182005-05-05 16:45:59 +00001201
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00001202 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1203 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
Ralf Baechle41943182005-05-05 16:45:59 +00001204 if (c->fpu_id & MIPS_FPIR_3D)
1205 c->ases |= MIPS_ASE_MIPS3D;
1206 }
1207 }
Ralf Baechle9966db252007-10-11 23:46:17 +01001208
Al Cooperda4b62c2012-07-13 16:44:51 -04001209 if (cpu_has_mips_r2) {
Ralf Baechlef6771db2007-11-08 18:02:29 +00001210 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
Al Cooperda4b62c2012-07-13 16:44:51 -04001211 /* R2 has Performance Counter Interrupt indicator */
1212 c->options |= MIPS_CPU_PCI;
1213 }
Ralf Baechlef6771db2007-11-08 18:02:29 +00001214 else
1215 c->srsets = 1;
Guenter Roeck91dfc422010-02-02 08:52:20 -08001216
Paul Burtona8ad1362014-01-28 14:28:43 +00001217 if (cpu_has_msa) {
Paul Burtona5e9a692014-01-27 15:23:10 +00001218 c->msa_id = cpu_get_msa_id();
Paul Burtona8ad1362014-01-28 14:28:43 +00001219 WARN(c->msa_id & MSA_IR_WRPF,
1220 "Vector register partitioning unimplemented!");
1221 }
Paul Burtona5e9a692014-01-27 15:23:10 +00001222
Guenter Roeck91dfc422010-02-02 08:52:20 -08001223 cpu_probe_vmbits(c);
David Daney949e51b2010-10-14 11:32:33 -07001224
1225#ifdef CONFIG_64BIT
1226 if (cpu == 0)
1227 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1228#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229}
1230
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001231void cpu_report(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232{
1233 struct cpuinfo_mips *c = &current_cpu_data;
1234
Leonid Yegoshind9f897c2013-10-07 10:43:32 +01001235 pr_info("CPU%d revision is: %08x (%s)\n",
1236 smp_processor_id(), c->processor_id, cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 if (c->options & MIPS_CPU_FPU)
Ralf Baechle9966db252007-10-11 23:46:17 +01001238 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
Paul Burtona5e9a692014-01-27 15:23:10 +00001239 if (cpu_has_msa)
1240 pr_info("MSA revision is: %08x\n", c->msa_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241}