Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Processor capabilities determination functions. |
| 3 | * |
| 4 | * Copyright (C) xxxx the Anonymous |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/init.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/ptrace.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 17 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/stddef.h> |
Paul Gortmaker | 73bc256 | 2011-07-23 16:30:40 -0400 | [diff] [blame] | 19 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
Ralf Baechle | 5759906 | 2007-02-18 19:07:31 +0000 | [diff] [blame] | 21 | #include <asm/bugs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/cpu.h> |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 23 | #include <asm/cpu-type.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <asm/fpu.h> |
| 25 | #include <asm/mipsregs.h> |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 26 | #include <asm/msa.h> |
David Daney | 654f57b | 2008-09-23 00:07:16 -0700 | [diff] [blame] | 27 | #include <asm/watch.h> |
Paul Gortmaker | 06372a6 | 2011-07-23 16:26:41 -0400 | [diff] [blame] | 28 | #include <asm/elf.h> |
Chris Dearman | a074f0e | 2009-07-10 01:51:27 -0700 | [diff] [blame] | 29 | #include <asm/spram.h> |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 30 | #include <asm/uaccess.h> |
| 31 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 32 | static int mips_fpu_disabled; |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 33 | |
| 34 | static int __init fpu_disable(char *s) |
| 35 | { |
| 36 | cpu_data[0].options &= ~MIPS_CPU_FPU; |
| 37 | mips_fpu_disabled = 1; |
| 38 | |
| 39 | return 1; |
| 40 | } |
| 41 | |
| 42 | __setup("nofpu", fpu_disable); |
| 43 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 44 | int mips_dsp_disabled; |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 45 | |
| 46 | static int __init dsp_disable(char *s) |
| 47 | { |
Steven J. Hill | ee80f7c7 | 2012-08-03 10:26:04 -0500 | [diff] [blame] | 48 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 49 | mips_dsp_disabled = 1; |
| 50 | |
| 51 | return 1; |
| 52 | } |
| 53 | |
| 54 | __setup("nodsp", dsp_disable); |
| 55 | |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 56 | static inline void check_errata(void) |
| 57 | { |
| 58 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 59 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 60 | switch (current_cpu_type()) { |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 61 | case CPU_34K: |
| 62 | /* |
| 63 | * Erratum "RPS May Cause Incorrect Instruction Execution" |
| 64 | * This code only handles VPE0, any SMP/SMTC/RTOS code |
| 65 | * making use of VPE1 will be responsable for that VPE. |
| 66 | */ |
| 67 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) |
| 68 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); |
| 69 | break; |
| 70 | default: |
| 71 | break; |
| 72 | } |
| 73 | } |
| 74 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | void __init check_bugs32(void) |
| 76 | { |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 77 | check_errata(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | /* |
| 81 | * Probe whether cpu has config register by trying to play with |
| 82 | * alternate cache bit and see whether it matters. |
| 83 | * It's used by cpu_probe to distinguish between R3000A and R3081. |
| 84 | */ |
| 85 | static inline int cpu_has_confreg(void) |
| 86 | { |
| 87 | #ifdef CONFIG_CPU_R3000 |
| 88 | extern unsigned long r3k_cache_size(unsigned long); |
| 89 | unsigned long size1, size2; |
| 90 | unsigned long cfg = read_c0_conf(); |
| 91 | |
| 92 | size1 = r3k_cache_size(ST0_ISC); |
| 93 | write_c0_conf(cfg ^ R30XX_CONF_AC); |
| 94 | size2 = r3k_cache_size(ST0_ISC); |
| 95 | write_c0_conf(cfg); |
| 96 | return size1 != size2; |
| 97 | #else |
| 98 | return 0; |
| 99 | #endif |
| 100 | } |
| 101 | |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 102 | static inline void set_elf_platform(int cpu, const char *plat) |
| 103 | { |
| 104 | if (cpu == 0) |
| 105 | __elf_platform = plat; |
| 106 | } |
| 107 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | /* |
| 109 | * Get the FPU Implementation/Revision. |
| 110 | */ |
| 111 | static inline unsigned long cpu_get_fpu_id(void) |
| 112 | { |
| 113 | unsigned long tmp, fpu_id; |
| 114 | |
| 115 | tmp = read_c0_status(); |
Paul Burton | 597ce17 | 2013-11-22 13:12:07 +0000 | [diff] [blame] | 116 | __enable_fpu(FPU_AS_IS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | fpu_id = read_32bit_cp1_register(CP1_REVISION); |
| 118 | write_c0_status(tmp); |
| 119 | return fpu_id; |
| 120 | } |
| 121 | |
| 122 | /* |
| 123 | * Check the CPU has an FPU the official way. |
| 124 | */ |
| 125 | static inline int __cpu_has_fpu(void) |
| 126 | { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 127 | return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | } |
| 129 | |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 130 | static inline unsigned long cpu_get_msa_id(void) |
| 131 | { |
| 132 | unsigned long status, conf5, msa_id; |
| 133 | |
| 134 | status = read_c0_status(); |
| 135 | __enable_fpu(FPU_64BIT); |
| 136 | conf5 = read_c0_config5(); |
| 137 | enable_msa(); |
| 138 | msa_id = read_msa_ir(); |
| 139 | write_c0_config5(conf5); |
| 140 | write_c0_status(status); |
| 141 | return msa_id; |
| 142 | } |
| 143 | |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 144 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
| 145 | { |
| 146 | #ifdef __NEED_VMBITS_PROBE |
David Daney | 5b7efa8 | 2010-02-08 12:27:00 -0800 | [diff] [blame] | 147 | write_c0_entryhi(0x3fffffffffffe000ULL); |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 148 | back_to_back_c0_hazard(); |
David Daney | 5b7efa8 | 2010-02-08 12:27:00 -0800 | [diff] [blame] | 149 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 150 | #endif |
| 151 | } |
| 152 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 153 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 154 | { |
| 155 | switch (isa) { |
| 156 | case MIPS_CPU_ISA_M64R2: |
| 157 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; |
| 158 | case MIPS_CPU_ISA_M64R1: |
| 159 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; |
| 160 | case MIPS_CPU_ISA_V: |
| 161 | c->isa_level |= MIPS_CPU_ISA_V; |
| 162 | case MIPS_CPU_ISA_IV: |
| 163 | c->isa_level |= MIPS_CPU_ISA_IV; |
| 164 | case MIPS_CPU_ISA_III: |
Ralf Baechle | 1990e54 | 2013-06-26 17:06:34 +0200 | [diff] [blame] | 165 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 166 | break; |
| 167 | |
| 168 | case MIPS_CPU_ISA_M32R2: |
| 169 | c->isa_level |= MIPS_CPU_ISA_M32R2; |
| 170 | case MIPS_CPU_ISA_M32R1: |
| 171 | c->isa_level |= MIPS_CPU_ISA_M32R1; |
| 172 | case MIPS_CPU_ISA_II: |
| 173 | c->isa_level |= MIPS_CPU_ISA_II; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 174 | break; |
| 175 | } |
| 176 | } |
| 177 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 178 | static char unknown_isa[] = KERN_ERR \ |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 179 | "Unsupported ISA type, c0.config0: %d."; |
| 180 | |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 181 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) |
| 182 | { |
| 183 | unsigned int config6; |
James Hogan | d83b0e8 | 2014-01-22 16:19:40 +0000 | [diff] [blame] | 184 | |
| 185 | /* It's implementation dependent how the FTLB can be enabled */ |
| 186 | switch (c->cputype) { |
| 187 | case CPU_PROAPTIV: |
| 188 | case CPU_P5600: |
| 189 | /* proAptiv & related cores use Config6 to enable the FTLB */ |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 190 | config6 = read_c0_config6(); |
| 191 | if (enable) |
| 192 | /* Enable FTLB */ |
| 193 | write_c0_config6(config6 | MIPS_CONF6_FTLBEN); |
| 194 | else |
| 195 | /* Disable FTLB */ |
| 196 | write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); |
| 197 | back_to_back_c0_hazard(); |
James Hogan | d83b0e8 | 2014-01-22 16:19:40 +0000 | [diff] [blame] | 198 | break; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 199 | } |
| 200 | } |
| 201 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 202 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
| 203 | { |
| 204 | unsigned int config0; |
| 205 | int isa; |
| 206 | |
| 207 | config0 = read_c0_config(); |
| 208 | |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 209 | /* |
| 210 | * Look for Standard TLB or Dual VTLB and FTLB |
| 211 | */ |
| 212 | if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || |
| 213 | (((config0 & MIPS_CONF_MT) >> 7) == 4)) |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 214 | c->options |= MIPS_CPU_TLB; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 215 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 216 | isa = (config0 & MIPS_CONF_AT) >> 13; |
| 217 | switch (isa) { |
| 218 | case 0: |
| 219 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
| 220 | case 0: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 221 | set_isa(c, MIPS_CPU_ISA_M32R1); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 222 | break; |
| 223 | case 1: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 224 | set_isa(c, MIPS_CPU_ISA_M32R2); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 225 | break; |
| 226 | default: |
| 227 | goto unknown; |
| 228 | } |
| 229 | break; |
| 230 | case 2: |
| 231 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
| 232 | case 0: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 233 | set_isa(c, MIPS_CPU_ISA_M64R1); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 234 | break; |
| 235 | case 1: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 236 | set_isa(c, MIPS_CPU_ISA_M64R2); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 237 | break; |
| 238 | default: |
| 239 | goto unknown; |
| 240 | } |
| 241 | break; |
| 242 | default: |
| 243 | goto unknown; |
| 244 | } |
| 245 | |
| 246 | return config0 & MIPS_CONF_M; |
| 247 | |
| 248 | unknown: |
| 249 | panic(unknown_isa, config0); |
| 250 | } |
| 251 | |
| 252 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) |
| 253 | { |
| 254 | unsigned int config1; |
| 255 | |
| 256 | config1 = read_c0_config1(); |
| 257 | |
| 258 | if (config1 & MIPS_CONF1_MD) |
| 259 | c->ases |= MIPS_ASE_MDMX; |
| 260 | if (config1 & MIPS_CONF1_WR) |
| 261 | c->options |= MIPS_CPU_WATCH; |
| 262 | if (config1 & MIPS_CONF1_CA) |
| 263 | c->ases |= MIPS_ASE_MIPS16; |
| 264 | if (config1 & MIPS_CONF1_EP) |
| 265 | c->options |= MIPS_CPU_EJTAG; |
| 266 | if (config1 & MIPS_CONF1_FP) { |
| 267 | c->options |= MIPS_CPU_FPU; |
| 268 | c->options |= MIPS_CPU_32FPR; |
| 269 | } |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 270 | if (cpu_has_tlb) { |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 271 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 272 | c->tlbsizevtlb = c->tlbsize; |
| 273 | c->tlbsizeftlbsets = 0; |
| 274 | } |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 275 | |
| 276 | return config1 & MIPS_CONF_M; |
| 277 | } |
| 278 | |
| 279 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) |
| 280 | { |
| 281 | unsigned int config2; |
| 282 | |
| 283 | config2 = read_c0_config2(); |
| 284 | |
| 285 | if (config2 & MIPS_CONF2_SL) |
| 286 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; |
| 287 | |
| 288 | return config2 & MIPS_CONF_M; |
| 289 | } |
| 290 | |
| 291 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) |
| 292 | { |
| 293 | unsigned int config3; |
| 294 | |
| 295 | config3 = read_c0_config3(); |
| 296 | |
Steven J. Hill | b2ab4f0 | 2012-09-13 16:47:58 -0500 | [diff] [blame] | 297 | if (config3 & MIPS_CONF3_SM) { |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 298 | c->ases |= MIPS_ASE_SMARTMIPS; |
Steven J. Hill | b2ab4f0 | 2012-09-13 16:47:58 -0500 | [diff] [blame] | 299 | c->options |= MIPS_CPU_RIXI; |
| 300 | } |
| 301 | if (config3 & MIPS_CONF3_RXI) |
| 302 | c->options |= MIPS_CPU_RIXI; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 303 | if (config3 & MIPS_CONF3_DSP) |
| 304 | c->ases |= MIPS_ASE_DSP; |
Steven J. Hill | ee80f7c7 | 2012-08-03 10:26:04 -0500 | [diff] [blame] | 305 | if (config3 & MIPS_CONF3_DSP2P) |
| 306 | c->ases |= MIPS_ASE_DSP2P; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 307 | if (config3 & MIPS_CONF3_VINT) |
| 308 | c->options |= MIPS_CPU_VINT; |
| 309 | if (config3 & MIPS_CONF3_VEIC) |
| 310 | c->options |= MIPS_CPU_VEIC; |
| 311 | if (config3 & MIPS_CONF3_MT) |
| 312 | c->ases |= MIPS_ASE_MIPSMT; |
| 313 | if (config3 & MIPS_CONF3_ULRI) |
| 314 | c->options |= MIPS_CPU_ULRI; |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 315 | if (config3 & MIPS_CONF3_ISA) |
| 316 | c->options |= MIPS_CPU_MICROMIPS; |
David Daney | 1e7decd | 2013-02-16 23:42:43 +0100 | [diff] [blame] | 317 | if (config3 & MIPS_CONF3_VZ) |
| 318 | c->ases |= MIPS_ASE_VZ; |
Steven J. Hill | 4a0156f | 2013-11-14 16:12:24 +0000 | [diff] [blame] | 319 | if (config3 & MIPS_CONF3_SC) |
| 320 | c->options |= MIPS_CPU_SEGMENTS; |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 321 | if (config3 & MIPS_CONF3_MSA) |
| 322 | c->ases |= MIPS_ASE_MSA; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 323 | |
| 324 | return config3 & MIPS_CONF_M; |
| 325 | } |
| 326 | |
| 327 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) |
| 328 | { |
| 329 | unsigned int config4; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 330 | unsigned int newcf4; |
| 331 | unsigned int mmuextdef; |
| 332 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 333 | |
| 334 | config4 = read_c0_config4(); |
| 335 | |
Leonid Yegoshin | 1745c1e | 2013-11-14 16:12:23 +0000 | [diff] [blame] | 336 | if (cpu_has_tlb) { |
| 337 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) |
| 338 | c->options |= MIPS_CPU_TLBINV; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 339 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
| 340 | switch (mmuextdef) { |
| 341 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: |
| 342 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; |
| 343 | c->tlbsizevtlb = c->tlbsize; |
| 344 | break; |
| 345 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: |
| 346 | c->tlbsizevtlb += |
| 347 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> |
| 348 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; |
| 349 | c->tlbsize = c->tlbsizevtlb; |
| 350 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; |
| 351 | /* fall through */ |
| 352 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: |
| 353 | newcf4 = (config4 & ~ftlb_page) | |
| 354 | (page_size_ftlb(mmuextdef) << |
| 355 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); |
| 356 | write_c0_config4(newcf4); |
| 357 | back_to_back_c0_hazard(); |
| 358 | config4 = read_c0_config4(); |
| 359 | if (config4 != newcf4) { |
| 360 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", |
| 361 | PAGE_SIZE, config4); |
| 362 | /* Switch FTLB off */ |
| 363 | set_ftlb_enable(c, 0); |
| 364 | break; |
| 365 | } |
| 366 | c->tlbsizeftlbsets = 1 << |
| 367 | ((config4 & MIPS_CONF4_FTLBSETS) >> |
| 368 | MIPS_CONF4_FTLBSETS_SHIFT); |
| 369 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> |
| 370 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; |
| 371 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; |
| 372 | break; |
| 373 | } |
Leonid Yegoshin | 1745c1e | 2013-11-14 16:12:23 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 376 | c->kscratch_mask = (config4 >> 16) & 0xff; |
| 377 | |
| 378 | return config4 & MIPS_CONF_M; |
| 379 | } |
| 380 | |
Ralf Baechle | 8b8a7634 | 2013-09-19 11:15:49 +0200 | [diff] [blame] | 381 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) |
| 382 | { |
| 383 | unsigned int config5; |
| 384 | |
| 385 | config5 = read_c0_config5(); |
| 386 | config5 &= ~MIPS_CONF5_UFR; |
| 387 | write_c0_config5(config5); |
| 388 | |
Markos Chandras | 4901674 | 2014-01-09 16:04:51 +0000 | [diff] [blame] | 389 | if (config5 & MIPS_CONF5_EVA) |
| 390 | c->options |= MIPS_CPU_EVA; |
| 391 | |
Ralf Baechle | 8b8a7634 | 2013-09-19 11:15:49 +0200 | [diff] [blame] | 392 | return config5 & MIPS_CONF_M; |
| 393 | } |
| 394 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 395 | static void decode_configs(struct cpuinfo_mips *c) |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 396 | { |
| 397 | int ok; |
| 398 | |
| 399 | /* MIPS32 or MIPS64 compliant CPU. */ |
| 400 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
| 401 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; |
| 402 | |
| 403 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
| 404 | |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 405 | /* Enable FTLB if present */ |
| 406 | set_ftlb_enable(c, 1); |
| 407 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 408 | ok = decode_config0(c); /* Read Config registers. */ |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 409 | BUG_ON(!ok); /* Arch spec violation! */ |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 410 | if (ok) |
| 411 | ok = decode_config1(c); |
| 412 | if (ok) |
| 413 | ok = decode_config2(c); |
| 414 | if (ok) |
| 415 | ok = decode_config3(c); |
| 416 | if (ok) |
| 417 | ok = decode_config4(c); |
Ralf Baechle | 8b8a7634 | 2013-09-19 11:15:49 +0200 | [diff] [blame] | 418 | if (ok) |
| 419 | ok = decode_config5(c); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 420 | |
| 421 | mips_probe_watch_registers(c); |
| 422 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 423 | #ifndef CONFIG_MIPS_CPS |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 424 | if (cpu_has_mips_r2) |
| 425 | c->core = read_c0_ebase() & 0x3ff; |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 426 | #endif |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 427 | } |
| 428 | |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 429 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | | MIPS_CPU_COUNTER) |
| 431 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 432 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 434 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | case PRID_IMP_R2000: |
| 436 | c->cputype = CPU_R2000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 437 | __cpu_name[cpu] = "R2000"; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 438 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 439 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | if (__cpu_has_fpu()) |
| 441 | c->options |= MIPS_CPU_FPU; |
| 442 | c->tlbsize = 64; |
| 443 | break; |
| 444 | case PRID_IMP_R3000: |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 445 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 446 | if (cpu_has_confreg()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | c->cputype = CPU_R3081E; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 448 | __cpu_name[cpu] = "R3081"; |
| 449 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | c->cputype = CPU_R3000A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 451 | __cpu_name[cpu] = "R3000A"; |
| 452 | } |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 453 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | c->cputype = CPU_R3000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 455 | __cpu_name[cpu] = "R3000"; |
| 456 | } |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 457 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 458 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | if (__cpu_has_fpu()) |
| 460 | c->options |= MIPS_CPU_FPU; |
| 461 | c->tlbsize = 64; |
| 462 | break; |
| 463 | case PRID_IMP_R4000: |
| 464 | if (read_c0_config() & CONF_SC) { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 465 | if ((c->processor_id & PRID_REV_MASK) >= |
| 466 | PRID_REV_R4400) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | c->cputype = CPU_R4400PC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 468 | __cpu_name[cpu] = "R4400PC"; |
| 469 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 470 | c->cputype = CPU_R4000PC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 471 | __cpu_name[cpu] = "R4000PC"; |
| 472 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | } else { |
Maciej W. Rozycki | 7f177a5 | 2013-09-23 14:01:53 +0100 | [diff] [blame] | 474 | int cca = read_c0_config() & CONF_CM_CMASK; |
| 475 | int mc; |
| 476 | |
| 477 | /* |
| 478 | * SC and MC versions can't be reliably told apart, |
| 479 | * but only the latter support coherent caching |
| 480 | * modes so assume the firmware has set the KSEG0 |
| 481 | * coherency attribute reasonably (if uncached, we |
| 482 | * assume SC). |
| 483 | */ |
| 484 | switch (cca) { |
| 485 | case CONF_CM_CACHABLE_CE: |
| 486 | case CONF_CM_CACHABLE_COW: |
| 487 | case CONF_CM_CACHABLE_CUW: |
| 488 | mc = 1; |
| 489 | break; |
| 490 | default: |
| 491 | mc = 0; |
| 492 | break; |
| 493 | } |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 494 | if ((c->processor_id & PRID_REV_MASK) >= |
| 495 | PRID_REV_R4400) { |
Maciej W. Rozycki | 7f177a5 | 2013-09-23 14:01:53 +0100 | [diff] [blame] | 496 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
| 497 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 498 | } else { |
Maciej W. Rozycki | 7f177a5 | 2013-09-23 14:01:53 +0100 | [diff] [blame] | 499 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
| 500 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 501 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | } |
| 503 | |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 504 | set_isa(c, MIPS_CPU_ISA_III); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 506 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
| 507 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | c->tlbsize = 48; |
| 509 | break; |
| 510 | case PRID_IMP_VR41XX: |
Yoichi Yuasa | 9f91e50 | 2013-02-21 15:38:19 +0900 | [diff] [blame] | 511 | set_isa(c, MIPS_CPU_ISA_III); |
| 512 | c->options = R4K_OPTS; |
| 513 | c->tlbsize = 32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | switch (c->processor_id & 0xf0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | case PRID_REV_VR4111: |
| 516 | c->cputype = CPU_VR4111; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 517 | __cpu_name[cpu] = "NEC VR4111"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 519 | case PRID_REV_VR4121: |
| 520 | c->cputype = CPU_VR4121; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 521 | __cpu_name[cpu] = "NEC VR4121"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | break; |
| 523 | case PRID_REV_VR4122: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 524 | if ((c->processor_id & 0xf) < 0x3) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | c->cputype = CPU_VR4122; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 526 | __cpu_name[cpu] = "NEC VR4122"; |
| 527 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 528 | c->cputype = CPU_VR4181A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 529 | __cpu_name[cpu] = "NEC VR4181A"; |
| 530 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | break; |
| 532 | case PRID_REV_VR4130: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 533 | if ((c->processor_id & 0xf) < 0x4) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | c->cputype = CPU_VR4131; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 535 | __cpu_name[cpu] = "NEC VR4131"; |
| 536 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 537 | c->cputype = CPU_VR4133; |
Yoichi Yuasa | 9f91e50 | 2013-02-21 15:38:19 +0900 | [diff] [blame] | 538 | c->options |= MIPS_CPU_LLSC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 539 | __cpu_name[cpu] = "NEC VR4133"; |
| 540 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | break; |
| 542 | default: |
| 543 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); |
| 544 | c->cputype = CPU_VR41XX; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 545 | __cpu_name[cpu] = "NEC Vr41xx"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 546 | break; |
| 547 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | break; |
| 549 | case PRID_IMP_R4300: |
| 550 | c->cputype = CPU_R4300; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 551 | __cpu_name[cpu] = "R4300"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 552 | set_isa(c, MIPS_CPU_ISA_III); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 554 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | c->tlbsize = 32; |
| 556 | break; |
| 557 | case PRID_IMP_R4600: |
| 558 | c->cputype = CPU_R4600; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 559 | __cpu_name[cpu] = "R4600"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 560 | set_isa(c, MIPS_CPU_ISA_III); |
Thiemo Seufer | 075e750 | 2005-07-27 21:48:12 +0000 | [diff] [blame] | 561 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 562 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | c->tlbsize = 48; |
| 564 | break; |
| 565 | #if 0 |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 566 | case PRID_IMP_R4650: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 567 | /* |
| 568 | * This processor doesn't have an MMU, so it's not |
| 569 | * "real easy" to run Linux on it. It is left purely |
| 570 | * for documentation. Commented out because it shares |
| 571 | * it's c0_prid id number with the TX3900. |
| 572 | */ |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 573 | c->cputype = CPU_R4650; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 574 | __cpu_name[cpu] = "R4650"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 575 | set_isa(c, MIPS_CPU_ISA_III); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 576 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 577 | c->tlbsize = 48; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 578 | break; |
| 579 | #endif |
| 580 | case PRID_IMP_TX39: |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 581 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | |
| 583 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { |
| 584 | c->cputype = CPU_TX3927; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 585 | __cpu_name[cpu] = "TX3927"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 586 | c->tlbsize = 64; |
| 587 | } else { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 588 | switch (c->processor_id & PRID_REV_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 589 | case PRID_REV_TX3912: |
| 590 | c->cputype = CPU_TX3912; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 591 | __cpu_name[cpu] = "TX3912"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | c->tlbsize = 32; |
| 593 | break; |
| 594 | case PRID_REV_TX3922: |
| 595 | c->cputype = CPU_TX3922; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 596 | __cpu_name[cpu] = "TX3922"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | c->tlbsize = 64; |
| 598 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | } |
| 600 | } |
| 601 | break; |
| 602 | case PRID_IMP_R4700: |
| 603 | c->cputype = CPU_R4700; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 604 | __cpu_name[cpu] = "R4700"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 605 | set_isa(c, MIPS_CPU_ISA_III); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 607 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | c->tlbsize = 48; |
| 609 | break; |
| 610 | case PRID_IMP_TX49: |
| 611 | c->cputype = CPU_TX49XX; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 612 | __cpu_name[cpu] = "R49XX"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 613 | set_isa(c, MIPS_CPU_ISA_III); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
| 615 | if (!(c->processor_id & 0x08)) |
| 616 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; |
| 617 | c->tlbsize = 48; |
| 618 | break; |
| 619 | case PRID_IMP_R5000: |
| 620 | c->cputype = CPU_R5000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 621 | __cpu_name[cpu] = "R5000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 622 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 624 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | c->tlbsize = 48; |
| 626 | break; |
| 627 | case PRID_IMP_R5432: |
| 628 | c->cputype = CPU_R5432; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 629 | __cpu_name[cpu] = "R5432"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 630 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 632 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | c->tlbsize = 48; |
| 634 | break; |
| 635 | case PRID_IMP_R5500: |
| 636 | c->cputype = CPU_R5500; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 637 | __cpu_name[cpu] = "R5500"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 638 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 640 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 641 | c->tlbsize = 48; |
| 642 | break; |
| 643 | case PRID_IMP_NEVADA: |
| 644 | c->cputype = CPU_NEVADA; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 645 | __cpu_name[cpu] = "Nevada"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 646 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 648 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 649 | c->tlbsize = 48; |
| 650 | break; |
| 651 | case PRID_IMP_R6000: |
| 652 | c->cputype = CPU_R6000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 653 | __cpu_name[cpu] = "R6000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 654 | set_isa(c, MIPS_CPU_ISA_II); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 655 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 656 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 657 | c->tlbsize = 32; |
| 658 | break; |
| 659 | case PRID_IMP_R6000A: |
| 660 | c->cputype = CPU_R6000A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 661 | __cpu_name[cpu] = "R6000A"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 662 | set_isa(c, MIPS_CPU_ISA_II); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 664 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | c->tlbsize = 32; |
| 666 | break; |
| 667 | case PRID_IMP_RM7000: |
| 668 | c->cputype = CPU_RM7000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 669 | __cpu_name[cpu] = "RM7000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 670 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 671 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 672 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 673 | /* |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 674 | * Undocumented RM7000: Bit 29 in the info register of |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
| 676 | * entries. |
| 677 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 678 | * 29 1 => 64 entry JTLB |
| 679 | * 0 => 48 entry JTLB |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | */ |
| 681 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
| 682 | break; |
| 683 | case PRID_IMP_RM9000: |
| 684 | c->cputype = CPU_RM9000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 685 | __cpu_name[cpu] = "RM9000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 686 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 687 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 688 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 689 | /* |
| 690 | * Bit 29 in the info register of the RM9000 |
| 691 | * indicates if the TLB has 48 or 64 entries. |
| 692 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 693 | * 29 1 => 64 entry JTLB |
| 694 | * 0 => 48 entry JTLB |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 695 | */ |
| 696 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
| 697 | break; |
| 698 | case PRID_IMP_R8000: |
| 699 | c->cputype = CPU_R8000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 700 | __cpu_name[cpu] = "RM8000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 701 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 703 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 704 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
| 706 | break; |
| 707 | case PRID_IMP_R10000: |
| 708 | c->cputype = CPU_R10000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 709 | __cpu_name[cpu] = "R10000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 710 | set_isa(c, MIPS_CPU_ISA_IV); |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 711 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 712 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 714 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 715 | c->tlbsize = 64; |
| 716 | break; |
| 717 | case PRID_IMP_R12000: |
| 718 | c->cputype = CPU_R12000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 719 | __cpu_name[cpu] = "R12000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 720 | set_isa(c, MIPS_CPU_ISA_IV); |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 721 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 722 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 723 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 724 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 725 | c->tlbsize = 64; |
| 726 | break; |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 727 | case PRID_IMP_R14000: |
| 728 | c->cputype = CPU_R14000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 729 | __cpu_name[cpu] = "R14000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 730 | set_isa(c, MIPS_CPU_ISA_IV); |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 731 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 732 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 733 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 734 | MIPS_CPU_LLSC; |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 735 | c->tlbsize = 64; |
| 736 | break; |
Huacai Chen | 2685919 | 2014-02-16 16:01:18 +0800 | [diff] [blame] | 737 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 738 | switch (c->processor_id & PRID_REV_MASK) { |
| 739 | case PRID_REV_LOONGSON2E: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame^] | 740 | c->cputype = CPU_LOONGSON2; |
| 741 | __cpu_name[cpu] = "ICT Loongson-2"; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 742 | set_elf_platform(cpu, "loongson2e"); |
| 743 | break; |
| 744 | case PRID_REV_LOONGSON2F: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame^] | 745 | c->cputype = CPU_LOONGSON2; |
| 746 | __cpu_name[cpu] = "ICT Loongson-2"; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 747 | set_elf_platform(cpu, "loongson2f"); |
| 748 | break; |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame^] | 749 | case PRID_REV_LOONGSON3A: |
| 750 | c->cputype = CPU_LOONGSON3; |
| 751 | __cpu_name[cpu] = "ICT Loongson-3"; |
| 752 | set_elf_platform(cpu, "loongson3a"); |
| 753 | break; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 754 | } |
| 755 | |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 756 | set_isa(c, MIPS_CPU_ISA_III); |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 757 | c->options = R4K_OPTS | |
| 758 | MIPS_CPU_FPU | MIPS_CPU_LLSC | |
| 759 | MIPS_CPU_32FPR; |
| 760 | c->tlbsize = 64; |
| 761 | break; |
Huacai Chen | 2685919 | 2014-02-16 16:01:18 +0800 | [diff] [blame] | 762 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 763 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 765 | c->cputype = CPU_LOONGSON1; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 766 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 767 | switch (c->processor_id & PRID_REV_MASK) { |
| 768 | case PRID_REV_LOONGSON1B: |
| 769 | __cpu_name[cpu] = "Loongson 1B"; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 770 | break; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 771 | } |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 772 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 773 | break; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 774 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | } |
| 776 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 777 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 779 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | case PRID_IMP_4KC: |
| 781 | c->cputype = CPU_4KC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 782 | __cpu_name[cpu] = "MIPS 4Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | break; |
| 784 | case PRID_IMP_4KEC: |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 785 | case PRID_IMP_4KECR2: |
| 786 | c->cputype = CPU_4KEC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 787 | __cpu_name[cpu] = "MIPS 4KEc"; |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 788 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | case PRID_IMP_4KSC: |
Ralf Baechle | 8afcb5d | 2005-10-04 15:01:26 +0100 | [diff] [blame] | 790 | case PRID_IMP_4KSD: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 791 | c->cputype = CPU_4KSC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 792 | __cpu_name[cpu] = "MIPS 4KSc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | break; |
| 794 | case PRID_IMP_5KC: |
| 795 | c->cputype = CPU_5KC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 796 | __cpu_name[cpu] = "MIPS 5Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | break; |
Leonid Yegoshin | 78d4803 | 2012-07-06 21:56:01 +0200 | [diff] [blame] | 798 | case PRID_IMP_5KE: |
| 799 | c->cputype = CPU_5KE; |
| 800 | __cpu_name[cpu] = "MIPS 5KE"; |
| 801 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | case PRID_IMP_20KC: |
| 803 | c->cputype = CPU_20KC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 804 | __cpu_name[cpu] = "MIPS 20Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 805 | break; |
| 806 | case PRID_IMP_24K: |
| 807 | c->cputype = CPU_24K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 808 | __cpu_name[cpu] = "MIPS 24Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 809 | break; |
John Crispin | 42f3cae | 2013-01-11 22:44:10 +0100 | [diff] [blame] | 810 | case PRID_IMP_24KE: |
| 811 | c->cputype = CPU_24K; |
| 812 | __cpu_name[cpu] = "MIPS 24KEc"; |
| 813 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | case PRID_IMP_25KF: |
| 815 | c->cputype = CPU_25KF; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 816 | __cpu_name[cpu] = "MIPS 25Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 817 | break; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 818 | case PRID_IMP_34K: |
| 819 | c->cputype = CPU_34K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 820 | __cpu_name[cpu] = "MIPS 34Kc"; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 821 | break; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 822 | case PRID_IMP_74K: |
| 823 | c->cputype = CPU_74K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 824 | __cpu_name[cpu] = "MIPS 74Kc"; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 825 | break; |
Steven J. Hill | 113c62d | 2012-07-06 23:56:00 +0200 | [diff] [blame] | 826 | case PRID_IMP_M14KC: |
| 827 | c->cputype = CPU_M14KC; |
| 828 | __cpu_name[cpu] = "MIPS M14Kc"; |
| 829 | break; |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 830 | case PRID_IMP_M14KEC: |
| 831 | c->cputype = CPU_M14KEC; |
| 832 | __cpu_name[cpu] = "MIPS M14KEc"; |
| 833 | break; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 834 | case PRID_IMP_1004K: |
| 835 | c->cputype = CPU_1004K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 836 | __cpu_name[cpu] = "MIPS 1004Kc"; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 837 | break; |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 838 | case PRID_IMP_1074K: |
Steven J. Hill | 442e14a | 2014-01-17 15:03:50 -0600 | [diff] [blame] | 839 | c->cputype = CPU_1074K; |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 840 | __cpu_name[cpu] = "MIPS 1074Kc"; |
| 841 | break; |
Leonid Yegoshin | b5f065e | 2013-11-20 10:46:02 +0000 | [diff] [blame] | 842 | case PRID_IMP_INTERAPTIV_UP: |
| 843 | c->cputype = CPU_INTERAPTIV; |
| 844 | __cpu_name[cpu] = "MIPS interAptiv"; |
| 845 | break; |
| 846 | case PRID_IMP_INTERAPTIV_MP: |
| 847 | c->cputype = CPU_INTERAPTIV; |
| 848 | __cpu_name[cpu] = "MIPS interAptiv (multi)"; |
| 849 | break; |
Leonid Yegoshin | b0d4d30 | 2013-11-14 16:12:28 +0000 | [diff] [blame] | 850 | case PRID_IMP_PROAPTIV_UP: |
| 851 | c->cputype = CPU_PROAPTIV; |
| 852 | __cpu_name[cpu] = "MIPS proAptiv"; |
| 853 | break; |
| 854 | case PRID_IMP_PROAPTIV_MP: |
| 855 | c->cputype = CPU_PROAPTIV; |
| 856 | __cpu_name[cpu] = "MIPS proAptiv (multi)"; |
| 857 | break; |
James Hogan | 829dcc0 | 2014-01-22 16:19:39 +0000 | [diff] [blame] | 858 | case PRID_IMP_P5600: |
| 859 | c->cputype = CPU_P5600; |
| 860 | __cpu_name[cpu] = "MIPS P5600"; |
| 861 | break; |
Leonid Yegoshin | 9943ed9 | 2014-03-04 13:34:44 +0000 | [diff] [blame] | 862 | case PRID_IMP_M5150: |
| 863 | c->cputype = CPU_M5150; |
| 864 | __cpu_name[cpu] = "MIPS M5150"; |
| 865 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 866 | } |
Chris Dearman | 0b6d497 | 2007-09-13 12:32:02 +0100 | [diff] [blame] | 867 | |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 868 | decode_configs(c); |
| 869 | |
Chris Dearman | 0b6d497 | 2007-09-13 12:32:02 +0100 | [diff] [blame] | 870 | spram_config(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | } |
| 872 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 873 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 874 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 875 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 876 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 877 | case PRID_IMP_AU1_REV1: |
| 878 | case PRID_IMP_AU1_REV2: |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 879 | c->cputype = CPU_ALCHEMY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 880 | switch ((c->processor_id >> 24) & 0xff) { |
| 881 | case 0: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 882 | __cpu_name[cpu] = "Au1000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 883 | break; |
| 884 | case 1: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 885 | __cpu_name[cpu] = "Au1500"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | break; |
| 887 | case 2: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 888 | __cpu_name[cpu] = "Au1100"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | break; |
| 890 | case 3: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 891 | __cpu_name[cpu] = "Au1550"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 892 | break; |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 893 | case 4: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 894 | __cpu_name[cpu] = "Au1200"; |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 895 | if ((c->processor_id & PRID_REV_MASK) == 2) |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 896 | __cpu_name[cpu] = "Au1250"; |
Manuel Lauss | 237cfee | 2007-12-06 09:07:55 +0100 | [diff] [blame] | 897 | break; |
| 898 | case 5: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 899 | __cpu_name[cpu] = "Au1210"; |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 900 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 901 | default: |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 902 | __cpu_name[cpu] = "Au1xxx"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | break; |
| 904 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 905 | break; |
| 906 | } |
| 907 | } |
| 908 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 909 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 911 | decode_configs(c); |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 912 | |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 913 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 914 | case PRID_IMP_SB1: |
| 915 | c->cputype = CPU_SB1; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 916 | __cpu_name[cpu] = "SiByte SB1"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 917 | /* FPU in pass1 is known to have issues. */ |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 918 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 919 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 920 | break; |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 921 | case PRID_IMP_SB1A: |
| 922 | c->cputype = CPU_SB1A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 923 | __cpu_name[cpu] = "SiByte SB1A"; |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 924 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 925 | } |
| 926 | } |
| 927 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 928 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 929 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 930 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 931 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 932 | case PRID_IMP_SR71000: |
| 933 | c->cputype = CPU_SR71000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 934 | __cpu_name[cpu] = "Sandcraft SR71000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 935 | c->scache.ways = 8; |
| 936 | c->tlbsize = 64; |
| 937 | break; |
| 938 | } |
| 939 | } |
| 940 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 941 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 942 | { |
| 943 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 944 | switch (c->processor_id & PRID_IMP_MASK) { |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 945 | case PRID_IMP_PR4450: |
| 946 | c->cputype = CPU_PR4450; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 947 | __cpu_name[cpu] = "Philips PR4450"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 948 | set_isa(c, MIPS_CPU_ISA_M32R1); |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 949 | break; |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 950 | } |
| 951 | } |
| 952 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 953 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 954 | { |
| 955 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 956 | switch (c->processor_id & PRID_IMP_MASK) { |
Kevin Cernekee | 190fca3 | 2010-11-23 10:26:45 -0800 | [diff] [blame] | 957 | case PRID_IMP_BMIPS32_REV4: |
| 958 | case PRID_IMP_BMIPS32_REV8: |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 959 | c->cputype = CPU_BMIPS32; |
| 960 | __cpu_name[cpu] = "Broadcom BMIPS32"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 961 | set_elf_platform(cpu, "bmips32"); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 962 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 963 | case PRID_IMP_BMIPS3300: |
| 964 | case PRID_IMP_BMIPS3300_ALT: |
| 965 | case PRID_IMP_BMIPS3300_BUG: |
| 966 | c->cputype = CPU_BMIPS3300; |
| 967 | __cpu_name[cpu] = "Broadcom BMIPS3300"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 968 | set_elf_platform(cpu, "bmips3300"); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 969 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 970 | case PRID_IMP_BMIPS43XX: { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 971 | int rev = c->processor_id & PRID_REV_MASK; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 972 | |
| 973 | if (rev >= PRID_REV_BMIPS4380_LO && |
| 974 | rev <= PRID_REV_BMIPS4380_HI) { |
| 975 | c->cputype = CPU_BMIPS4380; |
| 976 | __cpu_name[cpu] = "Broadcom BMIPS4380"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 977 | set_elf_platform(cpu, "bmips4380"); |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 978 | } else { |
| 979 | c->cputype = CPU_BMIPS4350; |
| 980 | __cpu_name[cpu] = "Broadcom BMIPS4350"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 981 | set_elf_platform(cpu, "bmips4350"); |
Maxime Bizon | 0de663e | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 982 | } |
| 983 | break; |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 984 | } |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 985 | case PRID_IMP_BMIPS5000: |
| 986 | c->cputype = CPU_BMIPS5000; |
| 987 | __cpu_name[cpu] = "Broadcom BMIPS5000"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 988 | set_elf_platform(cpu, "bmips5000"); |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 989 | c->options |= MIPS_CPU_ULRI; |
| 990 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 991 | } |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 992 | } |
| 993 | |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 994 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
| 995 | { |
| 996 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 997 | switch (c->processor_id & PRID_IMP_MASK) { |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 998 | case PRID_IMP_CAVIUM_CN38XX: |
| 999 | case PRID_IMP_CAVIUM_CN31XX: |
| 1000 | case PRID_IMP_CAVIUM_CN30XX: |
David Daney | 6f32946 | 2010-02-10 15:12:48 -0800 | [diff] [blame] | 1001 | c->cputype = CPU_CAVIUM_OCTEON; |
| 1002 | __cpu_name[cpu] = "Cavium Octeon"; |
| 1003 | goto platform; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1004 | case PRID_IMP_CAVIUM_CN58XX: |
| 1005 | case PRID_IMP_CAVIUM_CN56XX: |
| 1006 | case PRID_IMP_CAVIUM_CN50XX: |
| 1007 | case PRID_IMP_CAVIUM_CN52XX: |
David Daney | 6f32946 | 2010-02-10 15:12:48 -0800 | [diff] [blame] | 1008 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
| 1009 | __cpu_name[cpu] = "Cavium Octeon+"; |
| 1010 | platform: |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 1011 | set_elf_platform(cpu, "octeon"); |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1012 | break; |
David Daney | a1431b6 | 2011-09-24 02:29:54 +0200 | [diff] [blame] | 1013 | case PRID_IMP_CAVIUM_CN61XX: |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 1014 | case PRID_IMP_CAVIUM_CN63XX: |
David Daney | a1431b6 | 2011-09-24 02:29:54 +0200 | [diff] [blame] | 1015 | case PRID_IMP_CAVIUM_CN66XX: |
| 1016 | case PRID_IMP_CAVIUM_CN68XX: |
David Daney | af04bb8 | 2013-07-29 15:07:01 -0700 | [diff] [blame] | 1017 | case PRID_IMP_CAVIUM_CNF71XX: |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 1018 | c->cputype = CPU_CAVIUM_OCTEON2; |
| 1019 | __cpu_name[cpu] = "Cavium Octeon II"; |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 1020 | set_elf_platform(cpu, "octeon2"); |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 1021 | break; |
David Daney | af04bb8 | 2013-07-29 15:07:01 -0700 | [diff] [blame] | 1022 | case PRID_IMP_CAVIUM_CN70XX: |
| 1023 | case PRID_IMP_CAVIUM_CN78XX: |
| 1024 | c->cputype = CPU_CAVIUM_OCTEON3; |
| 1025 | __cpu_name[cpu] = "Cavium Octeon III"; |
| 1026 | set_elf_platform(cpu, "octeon3"); |
| 1027 | break; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1028 | default: |
| 1029 | printk(KERN_INFO "Unknown Octeon chip!\n"); |
| 1030 | c->cputype = CPU_UNKNOWN; |
| 1031 | break; |
| 1032 | } |
| 1033 | } |
| 1034 | |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 1035 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
| 1036 | { |
| 1037 | decode_configs(c); |
| 1038 | /* JZRISC does not implement the CP0 counter. */ |
| 1039 | c->options &= ~MIPS_CPU_COUNTER; |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1040 | switch (c->processor_id & PRID_IMP_MASK) { |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 1041 | case PRID_IMP_JZRISC: |
| 1042 | c->cputype = CPU_JZRISC; |
| 1043 | __cpu_name[cpu] = "Ingenic JZRISC"; |
| 1044 | break; |
| 1045 | default: |
| 1046 | panic("Unknown Ingenic Processor ID!"); |
| 1047 | break; |
| 1048 | } |
| 1049 | } |
| 1050 | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1051 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
| 1052 | { |
| 1053 | decode_configs(c); |
| 1054 | |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1055 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { |
Manuel Lauss | 809f36c | 2011-11-01 20:03:30 +0100 | [diff] [blame] | 1056 | c->cputype = CPU_ALCHEMY; |
| 1057 | __cpu_name[cpu] = "Au1300"; |
| 1058 | /* following stuff is not for Alchemy */ |
| 1059 | return; |
| 1060 | } |
| 1061 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1062 | c->options = (MIPS_CPU_TLB | |
| 1063 | MIPS_CPU_4KEX | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1064 | MIPS_CPU_COUNTER | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1065 | MIPS_CPU_DIVEC | |
| 1066 | MIPS_CPU_WATCH | |
| 1067 | MIPS_CPU_EJTAG | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1068 | MIPS_CPU_LLSC); |
| 1069 | |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1070 | switch (c->processor_id & PRID_IMP_MASK) { |
Jayachandran C | 4ca86a2 | 2013-08-11 14:43:54 +0530 | [diff] [blame] | 1071 | case PRID_IMP_NETLOGIC_XLP2XX: |
Jayachandran C | 8907c55 | 2013-12-21 16:52:20 +0530 | [diff] [blame] | 1072 | case PRID_IMP_NETLOGIC_XLP9XX: |
Jayachandran C | 4ca86a2 | 2013-08-11 14:43:54 +0530 | [diff] [blame] | 1073 | c->cputype = CPU_XLP; |
| 1074 | __cpu_name[cpu] = "Broadcom XLPII"; |
| 1075 | break; |
| 1076 | |
Jayachandran C | 2aa54b2 | 2011-11-16 00:21:29 +0000 | [diff] [blame] | 1077 | case PRID_IMP_NETLOGIC_XLP8XX: |
| 1078 | case PRID_IMP_NETLOGIC_XLP3XX: |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1079 | c->cputype = CPU_XLP; |
| 1080 | __cpu_name[cpu] = "Netlogic XLP"; |
| 1081 | break; |
| 1082 | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1083 | case PRID_IMP_NETLOGIC_XLR732: |
| 1084 | case PRID_IMP_NETLOGIC_XLR716: |
| 1085 | case PRID_IMP_NETLOGIC_XLR532: |
| 1086 | case PRID_IMP_NETLOGIC_XLR308: |
| 1087 | case PRID_IMP_NETLOGIC_XLR532C: |
| 1088 | case PRID_IMP_NETLOGIC_XLR516C: |
| 1089 | case PRID_IMP_NETLOGIC_XLR508C: |
| 1090 | case PRID_IMP_NETLOGIC_XLR308C: |
| 1091 | c->cputype = CPU_XLR; |
| 1092 | __cpu_name[cpu] = "Netlogic XLR"; |
| 1093 | break; |
| 1094 | |
| 1095 | case PRID_IMP_NETLOGIC_XLS608: |
| 1096 | case PRID_IMP_NETLOGIC_XLS408: |
| 1097 | case PRID_IMP_NETLOGIC_XLS404: |
| 1098 | case PRID_IMP_NETLOGIC_XLS208: |
| 1099 | case PRID_IMP_NETLOGIC_XLS204: |
| 1100 | case PRID_IMP_NETLOGIC_XLS108: |
| 1101 | case PRID_IMP_NETLOGIC_XLS104: |
| 1102 | case PRID_IMP_NETLOGIC_XLS616B: |
| 1103 | case PRID_IMP_NETLOGIC_XLS608B: |
| 1104 | case PRID_IMP_NETLOGIC_XLS416B: |
| 1105 | case PRID_IMP_NETLOGIC_XLS412B: |
| 1106 | case PRID_IMP_NETLOGIC_XLS408B: |
| 1107 | case PRID_IMP_NETLOGIC_XLS404B: |
| 1108 | c->cputype = CPU_XLR; |
| 1109 | __cpu_name[cpu] = "Netlogic XLS"; |
| 1110 | break; |
| 1111 | |
| 1112 | default: |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1113 | pr_info("Unknown Netlogic chip id [%02x]!\n", |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1114 | c->processor_id); |
| 1115 | c->cputype = CPU_XLR; |
| 1116 | break; |
| 1117 | } |
| 1118 | |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1119 | if (c->cputype == CPU_XLP) { |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1120 | set_isa(c, MIPS_CPU_ISA_M64R2); |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1121 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); |
| 1122 | /* This will be updated again after all threads are woken up */ |
| 1123 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; |
| 1124 | } else { |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1125 | set_isa(c, MIPS_CPU_ISA_M64R1); |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1126 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
| 1127 | } |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1128 | c->kscratch_mask = 0xf; |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1129 | } |
| 1130 | |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 1131 | #ifdef CONFIG_64BIT |
| 1132 | /* For use by uaccess.h */ |
| 1133 | u64 __ua_limit; |
| 1134 | EXPORT_SYMBOL(__ua_limit); |
| 1135 | #endif |
| 1136 | |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1137 | const char *__cpu_name[NR_CPUS]; |
David Daney | 874fd3b | 2010-01-28 16:52:12 -0800 | [diff] [blame] | 1138 | const char *__elf_platform; |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1139 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1140 | void cpu_probe(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1141 | { |
| 1142 | struct cpuinfo_mips *c = ¤t_cpu_data; |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1143 | unsigned int cpu = smp_processor_id(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1144 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1145 | c->processor_id = PRID_IMP_UNKNOWN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | c->fpu_id = FPIR_IMP_NONE; |
| 1147 | c->cputype = CPU_UNKNOWN; |
| 1148 | |
| 1149 | c->processor_id = read_c0_prid(); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1150 | switch (c->processor_id & PRID_COMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1151 | case PRID_COMP_LEGACY: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1152 | cpu_probe_legacy(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1153 | break; |
| 1154 | case PRID_COMP_MIPS: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1155 | cpu_probe_mips(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | break; |
| 1157 | case PRID_COMP_ALCHEMY: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1158 | cpu_probe_alchemy(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1159 | break; |
| 1160 | case PRID_COMP_SIBYTE: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1161 | cpu_probe_sibyte(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | break; |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1163 | case PRID_COMP_BROADCOM: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1164 | cpu_probe_broadcom(c, cpu); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1165 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | case PRID_COMP_SANDCRAFT: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1167 | cpu_probe_sandcraft(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | break; |
Daniel Laird | a92b058 | 2008-03-06 09:07:18 +0000 | [diff] [blame] | 1169 | case PRID_COMP_NXP: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1170 | cpu_probe_nxp(c, cpu); |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 1171 | break; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1172 | case PRID_COMP_CAVIUM: |
| 1173 | cpu_probe_cavium(c, cpu); |
| 1174 | break; |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 1175 | case PRID_COMP_INGENIC: |
| 1176 | cpu_probe_ingenic(c, cpu); |
| 1177 | break; |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1178 | case PRID_COMP_NETLOGIC: |
| 1179 | cpu_probe_netlogic(c, cpu); |
| 1180 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | } |
Franck Bui-Huu | dec8b1c | 2007-10-08 16:11:51 +0200 | [diff] [blame] | 1182 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1183 | BUG_ON(!__cpu_name[cpu]); |
| 1184 | BUG_ON(c->cputype == CPU_UNKNOWN); |
| 1185 | |
Franck Bui-Huu | dec8b1c | 2007-10-08 16:11:51 +0200 | [diff] [blame] | 1186 | /* |
| 1187 | * Platform code can force the cpu type to optimize code |
| 1188 | * generation. In that case be sure the cpu type is correctly |
| 1189 | * manually setup otherwise it could trigger some nasty bugs. |
| 1190 | */ |
| 1191 | BUG_ON(current_cpu_type() != c->cputype); |
| 1192 | |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 1193 | if (mips_fpu_disabled) |
| 1194 | c->options &= ~MIPS_CPU_FPU; |
| 1195 | |
| 1196 | if (mips_dsp_disabled) |
Steven J. Hill | ee80f7c7 | 2012-08-03 10:26:04 -0500 | [diff] [blame] | 1197 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 1198 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1199 | if (c->options & MIPS_CPU_FPU) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | c->fpu_id = cpu_get_fpu_id(); |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1201 | |
Deng-Cheng Zhu | adb3789 | 2013-04-01 18:14:28 +0000 | [diff] [blame] | 1202 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
| 1203 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1204 | if (c->fpu_id & MIPS_FPIR_3D) |
| 1205 | c->ases |= MIPS_ASE_MIPS3D; |
| 1206 | } |
| 1207 | } |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1208 | |
Al Cooper | da4b62c | 2012-07-13 16:44:51 -0400 | [diff] [blame] | 1209 | if (cpu_has_mips_r2) { |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 1210 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
Al Cooper | da4b62c | 2012-07-13 16:44:51 -0400 | [diff] [blame] | 1211 | /* R2 has Performance Counter Interrupt indicator */ |
| 1212 | c->options |= MIPS_CPU_PCI; |
| 1213 | } |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 1214 | else |
| 1215 | c->srsets = 1; |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 1216 | |
Paul Burton | a8ad136 | 2014-01-28 14:28:43 +0000 | [diff] [blame] | 1217 | if (cpu_has_msa) { |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 1218 | c->msa_id = cpu_get_msa_id(); |
Paul Burton | a8ad136 | 2014-01-28 14:28:43 +0000 | [diff] [blame] | 1219 | WARN(c->msa_id & MSA_IR_WRPF, |
| 1220 | "Vector register partitioning unimplemented!"); |
| 1221 | } |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 1222 | |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 1223 | cpu_probe_vmbits(c); |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 1224 | |
| 1225 | #ifdef CONFIG_64BIT |
| 1226 | if (cpu == 0) |
| 1227 | __ua_limit = ~((1ull << cpu_vmbits) - 1); |
| 1228 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | } |
| 1230 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1231 | void cpu_report(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1232 | { |
| 1233 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1234 | |
Leonid Yegoshin | d9f897c | 2013-10-07 10:43:32 +0100 | [diff] [blame] | 1235 | pr_info("CPU%d revision is: %08x (%s)\n", |
| 1236 | smp_processor_id(), c->processor_id, cpu_name_string()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1237 | if (c->options & MIPS_CPU_FPU) |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1238 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 1239 | if (cpu_has_msa) |
| 1240 | pr_info("MSA revision is: %08x\n", c->msa_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1241 | } |