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gerrit-public.fairphone.software / kernel / msm-4.9 / c9d96df207a2caadfb521c7b6108ef9172f5bf55 / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 2a3abf822378aba4294fab8583167aca2d1fb765 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]14
15/ {
16 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]17 gpio0 = &gpio1;
18 gpio1 = &gpio2;
19 gpio2 = &gpio3;
20 gpio3 = &gpio4;
21 gpio4 = &gpio5;
22 gpio5 = &gpio6;
23 gpio6 = &gpio7;
Sascha Hauer80fa0582013-06-25 15:51:57 +0200[diff] [blame]24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 spi0 = &ecspi1;
33 spi1 = &ecspi2;
34 spi2 = &ecspi3;
35 spi3 = &ecspi4;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]36 };
37
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
41 #address-cells = <1>;
42 #size-cells = <1>;
43 interrupt-controller;
44 reg = <0x00a01000 0x1000>,
45 <0x00a00100 0x100>;
46 };
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
55 };
56
57 ckih1 {
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
60 };
61
62 osc {
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
65 };
66 };
67
68 soc {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
73 ranges;
74
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]75 dma_apbh: dma-apbh@00110000 {
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
80 #dma-cells = <1>;
81 dma-channels = <4>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]82 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]83 };
84
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]85 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]86 compatible = "fsl,imx6q-gpmi-nand";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
Shawn Guoc7aa12a2013-07-16 17:13:00 +0800[diff] [blame]91 interrupts = <0 15 0x04>;
92 interrupt-names = "bch";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]97 dmas = <&dma_apbh 0>;
98 dma-names = "rx-tx";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]99 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]100 };
101
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]102 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]103 compatible = "arm,cortex-a9-twd-timer";
104 reg = <0x00a00600 0x20>;
105 interrupts = <1 13 0xf01>;
Shawn Guo2bb4b702013-04-03 23:50:09 +0800[diff] [blame]106 clocks = <&clks 15>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]107 };
108
109 L2: l2-cache@00a02000 {
110 compatible = "arm,pl310-cache";
111 reg = <0x00a02000 0x1000>;
112 interrupts = <0 92 0x04>;
113 cache-unified;
114 cache-level = <2>;
Dirk Behme5a5ca562013-04-26 10:13:55 +0200[diff] [blame]115 arm,tag-latency = <4 2 3>;
116 arm,data-latency = <4 2 3>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]117 };
118
Dirk Behme218abe62013-02-15 15:10:01 +0100[diff] [blame]119 pmu {
120 compatible = "arm,cortex-a9-pmu";
121 interrupts = <0 94 0x04>;
122 };
123
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]124 aips-bus@02000000 { /* AIPS1 */
125 compatible = "fsl,aips-bus", "simple-bus";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 reg = <0x02000000 0x100000>;
129 ranges;
130
131 spba-bus@02000000 {
132 compatible = "fsl,spba-bus", "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 reg = <0x02000000 0x40000>;
136 ranges;
137
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]138 spdif: spdif@02004000 {
Fabio Estevamc9d96df2013-09-02 23:51:41 -0300[diff] [blame^]139 compatible = "fsl,imx35-spdif";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]140 reg = <0x02004000 0x4000>;
141 interrupts = <0 52 0x04>;
Fabio Estevamc9d96df2013-09-02 23:51:41 -0300[diff] [blame^]142 dmas = <&sdma 14 18 0>,
143 <&sdma 15 18 0>;
144 dma-names = "rx", "tx";
145 clocks = <&clks 197>, <&clks 3>,
146 <&clks 197>, <&clks 107>,
147 <&clks 0>, <&clks 118>,
148 <&clks 62>, <&clks 139>,
149 <&clks 0>;
150 clock-names = "core", "rxtx0",
151 "rxtx1", "rxtx2",
152 "rxtx3", "rxtx4",
153 "rxtx5", "rxtx6",
154 "rxtx7";
155 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]156 };
157
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]158 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02008000 0x4000>;
163 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]164 clocks = <&clks 112>, <&clks 112>;
165 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]166 status = "disabled";
167 };
168
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]169 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
173 reg = <0x0200c000 0x4000>;
174 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]175 clocks = <&clks 113>, <&clks 113>;
176 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]177 status = "disabled";
178 };
179
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]180 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
184 reg = <0x02010000 0x4000>;
185 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]186 clocks = <&clks 114>, <&clks 114>;
187 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]188 status = "disabled";
189 };
190
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]191 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]192 #address-cells = <1>;
193 #size-cells = <0>;
194 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
195 reg = <0x02014000 0x4000>;
196 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]197 clocks = <&clks 115>, <&clks 115>;
198 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]199 status = "disabled";
200 };
201
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]202 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]203 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
204 reg = <0x02020000 0x4000>;
205 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]206 clocks = <&clks 160>, <&clks 161>;
207 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]208 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
209 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]210 status = "disabled";
211 };
212
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]213 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]214 reg = <0x02024000 0x4000>;
215 interrupts = <0 51 0x04>;
216 };
217
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]218 ssi1: ssi@02028000 {
219 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]220 reg = <0x02028000 0x4000>;
221 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]222 clocks = <&clks 178>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]223 dmas = <&sdma 37 1 0>,
224 <&sdma 38 1 0>;
225 dma-names = "rx", "tx";
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <38 37>;
228 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]229 };
230
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]231 ssi2: ssi@0202c000 {
232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]233 reg = <0x0202c000 0x4000>;
234 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]235 clocks = <&clks 179>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]236 dmas = <&sdma 41 1 0>,
237 <&sdma 42 1 0>;
238 dma-names = "rx", "tx";
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]239 fsl,fifo-depth = <15>;
240 fsl,ssi-dma-events = <42 41>;
241 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]242 };
243
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]244 ssi3: ssi@02030000 {
245 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]246 reg = <0x02030000 0x4000>;
247 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]248 clocks = <&clks 180>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]249 dmas = <&sdma 45 1 0>,
250 <&sdma 46 1 0>;
251 dma-names = "rx", "tx";
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]252 fsl,fifo-depth = <15>;
253 fsl,ssi-dma-events = <46 45>;
254 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]255 };
256
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]257 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]258 reg = <0x02034000 0x4000>;
259 interrupts = <0 50 0x04>;
260 };
261
262 spba@0203c000 {
263 reg = <0x0203c000 0x4000>;
264 };
265 };
266
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]267 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]268 reg = <0x02040000 0x3c000>;
269 interrupts = <0 3 0x04 0 12 0x04>;
270 };
271
272 aipstz@0207c000 { /* AIPSTZ1 */
273 reg = <0x0207c000 0x4000>;
274 };
275
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]276 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]277 #pwm-cells = <2>;
278 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]279 reg = <0x02080000 0x4000>;
280 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]281 clocks = <&clks 62>, <&clks 145>;
282 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]283 };
284
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]285 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]286 #pwm-cells = <2>;
287 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]288 reg = <0x02084000 0x4000>;
289 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]290 clocks = <&clks 62>, <&clks 146>;
291 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]292 };
293
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]294 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]295 #pwm-cells = <2>;
296 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]297 reg = <0x02088000 0x4000>;
298 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]299 clocks = <&clks 62>, <&clks 147>;
300 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]301 };
302
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]303 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]304 #pwm-cells = <2>;
305 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]306 reg = <0x0208c000 0x4000>;
307 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]308 clocks = <&clks 62>, <&clks 148>;
309 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]310 };
311
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]312 can1: flexcan@02090000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]313 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]314 reg = <0x02090000 0x4000>;
315 interrupts = <0 110 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]316 clocks = <&clks 108>, <&clks 109>;
317 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]318 };
319
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]320 can2: flexcan@02094000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]321 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]322 reg = <0x02094000 0x4000>;
323 interrupts = <0 111 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]324 clocks = <&clks 110>, <&clks 111>;
325 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]326 };
327
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]328 gpt: gpt@02098000 {
Sascha Hauer97b108f2013-06-25 15:51:47 +0200[diff] [blame]329 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]330 reg = <0x02098000 0x4000>;
331 interrupts = <0 55 0x04>;
Sascha Hauer4efccad2013-03-14 13:09:01 +0100[diff] [blame]332 clocks = <&clks 119>, <&clks 120>;
333 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]334 };
335
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]336 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]338 reg = <0x0209c000 0x4000>;
339 interrupts = <0 66 0x04 0 67 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]343 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]344 };
345
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]346 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]348 reg = <0x020a0000 0x4000>;
349 interrupts = <0 68 0x04 0 69 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]353 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 };
355
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]356 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]358 reg = <0x020a4000 0x4000>;
359 interrupts = <0 70 0x04 0 71 0x04>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]363 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]364 };
365
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]366 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]367 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]368 reg = <0x020a8000 0x4000>;
369 interrupts = <0 72 0x04 0 73 0x04>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]373 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]374 };
375
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]376 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]377 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]378 reg = <0x020ac000 0x4000>;
379 interrupts = <0 74 0x04 0 75 0x04>;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]383 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]384 };
385
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]386 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]387 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]388 reg = <0x020b0000 0x4000>;
389 interrupts = <0 76 0x04 0 77 0x04>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]393 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]394 };
395
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]396 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]397 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]398 reg = <0x020b4000 0x4000>;
399 interrupts = <0 78 0x04 0 79 0x04>;
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]403 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]404 };
405
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]406 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]407 reg = <0x020b8000 0x4000>;
408 interrupts = <0 82 0x04>;
409 };
410
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]411 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]412 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
413 reg = <0x020bc000 0x4000>;
414 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]415 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]416 };
417
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]418 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]419 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
420 reg = <0x020c0000 0x4000>;
421 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]422 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]423 status = "disabled";
424 };
425
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]426 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]427 compatible = "fsl,imx6q-ccm";
428 reg = <0x020c4000 0x4000>;
429 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]430 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]431 };
432
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]433 anatop: anatop@020c8000 {
434 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]435 reg = <0x020c8000 0x1000>;
436 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]437
438 regulator-1p1@110 {
439 compatible = "fsl,anatop-regulator";
440 regulator-name = "vdd1p1";
441 regulator-min-microvolt = <800000>;
442 regulator-max-microvolt = <1375000>;
443 regulator-always-on;
444 anatop-reg-offset = <0x110>;
445 anatop-vol-bit-shift = <8>;
446 anatop-vol-bit-width = <5>;
447 anatop-min-bit-val = <4>;
448 anatop-min-voltage = <800000>;
449 anatop-max-voltage = <1375000>;
450 };
451
452 regulator-3p0@120 {
453 compatible = "fsl,anatop-regulator";
454 regulator-name = "vdd3p0";
455 regulator-min-microvolt = <2800000>;
456 regulator-max-microvolt = <3150000>;
457 regulator-always-on;
458 anatop-reg-offset = <0x120>;
459 anatop-vol-bit-shift = <8>;
460 anatop-vol-bit-width = <5>;
461 anatop-min-bit-val = <0>;
462 anatop-min-voltage = <2625000>;
463 anatop-max-voltage = <3400000>;
464 };
465
466 regulator-2p5@130 {
467 compatible = "fsl,anatop-regulator";
468 regulator-name = "vdd2p5";
469 regulator-min-microvolt = <2000000>;
470 regulator-max-microvolt = <2750000>;
471 regulator-always-on;
472 anatop-reg-offset = <0x130>;
473 anatop-vol-bit-shift = <8>;
474 anatop-vol-bit-width = <5>;
475 anatop-min-bit-val = <0>;
476 anatop-min-voltage = <2000000>;
477 anatop-max-voltage = <2750000>;
478 };
479
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]480 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]481 compatible = "fsl,anatop-regulator";
482 regulator-name = "cpu";
483 regulator-min-microvolt = <725000>;
484 regulator-max-microvolt = <1450000>;
485 regulator-always-on;
486 anatop-reg-offset = <0x140>;
487 anatop-vol-bit-shift = <0>;
488 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]489 anatop-delay-reg-offset = <0x170>;
490 anatop-delay-bit-shift = <24>;
491 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]492 anatop-min-bit-val = <1>;
493 anatop-min-voltage = <725000>;
494 anatop-max-voltage = <1450000>;
495 };
496
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]497 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]498 compatible = "fsl,anatop-regulator";
499 regulator-name = "vddpu";
500 regulator-min-microvolt = <725000>;
501 regulator-max-microvolt = <1450000>;
502 regulator-always-on;
503 anatop-reg-offset = <0x140>;
504 anatop-vol-bit-shift = <9>;
505 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]506 anatop-delay-reg-offset = <0x170>;
507 anatop-delay-bit-shift = <26>;
508 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]509 anatop-min-bit-val = <1>;
510 anatop-min-voltage = <725000>;
511 anatop-max-voltage = <1450000>;
512 };
513
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]514 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]515 compatible = "fsl,anatop-regulator";
516 regulator-name = "vddsoc";
517 regulator-min-microvolt = <725000>;
518 regulator-max-microvolt = <1450000>;
519 regulator-always-on;
520 anatop-reg-offset = <0x140>;
521 anatop-vol-bit-shift = <18>;
522 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]523 anatop-delay-reg-offset = <0x170>;
524 anatop-delay-bit-shift = <28>;
525 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]526 anatop-min-bit-val = <1>;
527 anatop-min-voltage = <725000>;
528 anatop-max-voltage = <1450000>;
529 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]530 };
531
Shawn Guo3fe63732013-07-16 21:16:36 +0800[diff] [blame]532 tempmon: tempmon {
533 compatible = "fsl,imx6q-tempmon";
534 interrupts = <0 49 0x04>;
535 fsl,tempmon = <&anatop>;
536 fsl,tempmon-data = <&ocotp>;
537 };
538
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]539 usbphy1: usbphy@020c9000 {
540 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]541 reg = <0x020c9000 0x1000>;
542 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]543 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]544 };
545
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]546 usbphy2: usbphy@020ca000 {
547 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]548 reg = <0x020ca000 0x1000>;
549 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]550 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]551 };
552
553 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]554 compatible = "fsl,sec-v4.0-mon", "simple-bus";
555 #address-cells = <1>;
556 #size-cells = <1>;
557 ranges = <0 0x020cc000 0x4000>;
558
559 snvs-rtc-lp@34 {
560 compatible = "fsl,sec-v4.0-mon-rtc-lp";
561 reg = <0x34 0x58>;
562 interrupts = <0 19 0x04 0 20 0x04>;
563 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]564 };
565
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]566 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]567 reg = <0x020d0000 0x4000>;
568 interrupts = <0 56 0x04>;
569 };
570
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]571 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]572 reg = <0x020d4000 0x4000>;
573 interrupts = <0 57 0x04>;
574 };
575
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]576 src: src@020d8000 {
Philipp Zabelbd3d9242013-03-28 17:35:22 +0100[diff] [blame]577 compatible = "fsl,imx6q-src", "fsl,imx51-src";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]578 reg = <0x020d8000 0x4000>;
579 interrupts = <0 91 0x04 0 96 0x04>;
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]580 #reset-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]581 };
582
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]583 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]584 compatible = "fsl,imx6q-gpc";
585 reg = <0x020dc000 0x4000>;
586 interrupts = <0 89 0x04 0 90 0x04>;
587 };
588
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]589 gpr: iomuxc-gpr@020e0000 {
590 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
591 reg = <0x020e0000 0x38>;
592 };
593
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]594 iomuxc: iomuxc@020e0000 {
595 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
596 reg = <0x020e0000 0x4000>;
597
598 audmux {
599 pinctrl_audmux_1: audmux-1 {
600 fsl,pins = <
601 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
602 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
603 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
604 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
605 >;
606 };
607
608 pinctrl_audmux_2: audmux-2 {
609 fsl,pins = <
610 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
611 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
612 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
613 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
614 >;
615 };
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]616
617 pinctrl_audmux_3: audmux-3 {
618 fsl,pins = <
619 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
620 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
621 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
622 >;
623 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]624 };
625
626 ecspi1 {
627 pinctrl_ecspi1_1: ecspi1grp-1 {
628 fsl,pins = <
629 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
630 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
631 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
632 >;
633 };
634
635 pinctrl_ecspi1_2: ecspi1grp-2 {
636 fsl,pins = <
637 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
638 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
639 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
640 >;
641 };
642 };
643
644 ecspi3 {
645 pinctrl_ecspi3_1: ecspi3grp-1 {
646 fsl,pins = <
647 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
648 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
649 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
650 >;
651 };
652 };
653
654 enet {
655 pinctrl_enet_1: enetgrp-1 {
656 fsl,pins = <
657 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
658 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
659 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
660 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
661 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
662 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
663 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
664 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
665 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
666 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
667 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
668 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
669 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
670 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
671 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
672 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
673 >;
674 };
675
676 pinctrl_enet_2: enetgrp-2 {
677 fsl,pins = <
678 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
679 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
680 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
681 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
682 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
683 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
684 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
685 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
686 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
687 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
688 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
689 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
690 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
691 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
692 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
693 >;
694 };
695
696 pinctrl_enet_3: enetgrp-3 {
697 fsl,pins = <
698 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
699 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
700 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
701 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
702 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
703 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
704 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
705 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
706 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
707 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
708 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
709 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
710 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
711 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
712 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
713 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
714 >;
715 };
716 };
717
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]718 esai {
719 pinctrl_esai_1: esaigrp-1 {
720 fsl,pins = <
721 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
722 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
723 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
724 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
725 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
726 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
727 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
728 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
729 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
730 >;
731 };
732
733 pinctrl_esai_2: esaigrp-2 {
734 fsl,pins = <
735 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
736 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
737 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
738 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
739 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
740 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
741 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
742 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
743 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
744 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
745 >;
746 };
747 };
748
749 flexcan1 {
750 pinctrl_flexcan1_1: flexcan1grp-1 {
751 fsl,pins = <
752 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
753 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
754 >;
755 };
756
757 pinctrl_flexcan1_2: flexcan1grp-2 {
758 fsl,pins = <
759 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
760 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
761 >;
762 };
763 };
764
765 flexcan2 {
766 pinctrl_flexcan2_1: flexcan2grp-1 {
767 fsl,pins = <
768 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
769 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
770 >;
771 };
772 };
773
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]774 gpmi-nand {
775 pinctrl_gpmi_nand_1: gpmi-nand-1 {
776 fsl,pins = <
777 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
778 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
779 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
780 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
781 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
782 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
783 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
784 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
785 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
786 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
787 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
788 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
789 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
790 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
791 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
792 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
793 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
794 >;
795 };
796 };
797
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]798 hdmi_hdcp {
799 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
800 fsl,pins = <
801 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
802 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
803 >;
804 };
805
806 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
807 fsl,pins = <
808 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
809 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
810 >;
811 };
812
813 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
814 fsl,pins = <
815 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
816 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
817 >;
818 };
819 };
820
821 hdmi_cec {
822 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
823 fsl,pins = <
824 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
825 >;
826 };
827
828 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
829 fsl,pins = <
830 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
831 >;
832 };
833 };
834
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]835 i2c1 {
836 pinctrl_i2c1_1: i2c1grp-1 {
837 fsl,pins = <
838 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
839 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
840 >;
841 };
842
843 pinctrl_i2c1_2: i2c1grp-2 {
844 fsl,pins = <
845 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
846 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
847 >;
848 };
849 };
850
851 i2c2 {
852 pinctrl_i2c2_1: i2c2grp-1 {
853 fsl,pins = <
854 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
855 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
856 >;
857 };
858
859 pinctrl_i2c2_2: i2c2grp-2 {
860 fsl,pins = <
861 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
862 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
863 >;
864 };
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]865
866 pinctrl_i2c2_3: i2c2grp-3 {
867 fsl,pins = <
868 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
869 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
870 >;
871 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]872 };
873
874 i2c3 {
875 pinctrl_i2c3_1: i2c3grp-1 {
876 fsl,pins = <
877 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
878 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
879 >;
880 };
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]881
882 pinctrl_i2c3_2: i2c3grp-2 {
883 fsl,pins = <
884 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
885 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
886 >;
887 };
888
889 pinctrl_i2c3_3: i2c3grp-3 {
890 fsl,pins = <
891 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
892 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
893 >;
894 };
895
896 pinctrl_i2c3_4: i2c3grp-4 {
897 fsl,pins = <
898 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
899 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
900 >;
901 };
902 };
903
904 ipu1 {
905 pinctrl_ipu1_1: ipu1grp-1 {
906 fsl,pins = <
907 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
908 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
909 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
910 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
911 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
912 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
913 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
914 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
915 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
916 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
917 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
918 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
919 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
920 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
921 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
922 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
923 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
924 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
925 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
926 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
927 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
928 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
929 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
930 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
931 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
932 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
933 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
934 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
935 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
936 >;
937 };
938
939 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
940 fsl,pins = <
941 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
942 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
943 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
944 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
945 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
946 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
947 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
948 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
949 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
950 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
951 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
952 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
953 >;
954 };
955
956 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
957 fsl,pins = <
958 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
959 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
960 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
961 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
962 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
963 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
964 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
965 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
966 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
967 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
968 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
969 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
970 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
971 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
972 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
973 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
974 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
975 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
976 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
977 >;
978 };
979 };
980
981 mlb {
982 pinctrl_mlb_1: mlbgrp-1 {
983 fsl,pins = <
984 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
985 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
986 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
987 >;
988 };
989
990 pinctrl_mlb_2: mlbgrp-2 {
991 fsl,pins = <
992 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
993 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
994 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
995 >;
996 };
997 };
998
999 pwm0 {
1000 pinctrl_pwm0_1: pwm0grp-1 {
1001 fsl,pins = <
1002 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
1003 >;
1004 };
1005 };
1006
1007 pwm3 {
1008 pinctrl_pwm3_1: pwm3grp-1 {
1009 fsl,pins = <
1010 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1011 >;
1012 };
1013 };
1014
1015 spdif {
1016 pinctrl_spdif_1: spdifgrp-1 {
1017 fsl,pins = <
1018 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1019 >;
1020 };
1021
1022 pinctrl_spdif_2: spdifgrp-2 {
1023 fsl,pins = <
1024 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1025 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1026 >;
1027 };
Fabio Estevamc9d96df2013-09-02 23:51:41 -0300[diff] [blame^]1028
1029 pinctrl_spdif_3: spdifgrp-3 {
1030 fsl,pins = <
1031 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
1032 >;
1033 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]1034 };
1035
1036 uart1 {
1037 pinctrl_uart1_1: uart1grp-1 {
1038 fsl,pins = <
1039 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1040 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1041 >;
1042 };
1043 };
1044
1045 uart2 {
1046 pinctrl_uart2_1: uart2grp-1 {
1047 fsl,pins = <
1048 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1049 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1050 >;
1051 };
1052
1053 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1054 fsl,pins = <
1055 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1056 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1057 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1058 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1059 >;
1060 };
1061 };
1062
Huang Shijiec2797982013-07-12 15:56:11 +0800[diff] [blame]1063 uart3 {
1064 pinctrl_uart3_1: uart3grp-1 {
1065 fsl,pins = <
1066 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1067 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1068 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1069 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1070 >;
1071 };
Fabio Estevam5ff883412013-07-12 09:49:31 -0300[diff] [blame]1072
1073 pinctrl_uart3_2: uart3grp-2 {
1074 fsl,pins = <
1075 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1076 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1077 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1078 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1079 >;
1080 };
Huang Shijiec2797982013-07-12 15:56:11 +0800[diff] [blame]1081 };
1082
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]1083 uart4 {
1084 pinctrl_uart4_1: uart4grp-1 {
1085 fsl,pins = <
1086 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1087 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1088 >;
1089 };
1090 };
1091
1092 usbotg {
1093 pinctrl_usbotg_1: usbotggrp-1 {
1094 fsl,pins = <
1095 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1096 >;
1097 };
1098
1099 pinctrl_usbotg_2: usbotggrp-2 {
1100 fsl,pins = <
1101 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1102 >;
1103 };
1104 };
1105
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]1106 usbh2 {
1107 pinctrl_usbh2_1: usbh2grp-1 {
1108 fsl,pins = <
1109 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1110 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1111 >;
1112 };
1113
1114 pinctrl_usbh2_2: usbh2grp-2 {
1115 fsl,pins = <
1116 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1117 >;
1118 };
1119 };
1120
1121 usbh3 {
1122 pinctrl_usbh3_1: usbh3grp-1 {
1123 fsl,pins = <
1124 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1125 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1126 >;
1127 };
1128
1129 pinctrl_usbh3_2: usbh3grp-2 {
1130 fsl,pins = <
1131 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1132 >;
1133 };
1134 };
1135
Fabio Estevam26c3b652013-07-12 09:49:30 -0300[diff] [blame]1136 usdhc1 {
1137 pinctrl_usdhc1_1: usdhc1grp-1 {
1138 fsl,pins = <
1139 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1140 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1141 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1142 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1143 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1144 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1145 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1146 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1147 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1148 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1149 >;
1150 };
1151
1152 pinctrl_usdhc1_2: usdhc1grp-2 {
1153 fsl,pins = <
1154 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1155 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1156 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1157 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1158 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1159 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1160 >;
1161 };
1162 };
1163
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]1164 usdhc2 {
1165 pinctrl_usdhc2_1: usdhc2grp-1 {
1166 fsl,pins = <
1167 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1168 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1169 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1170 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1171 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1172 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1173 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1174 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1175 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1176 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1177 >;
1178 };
1179
1180 pinctrl_usdhc2_2: usdhc2grp-2 {
1181 fsl,pins = <
1182 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1183 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1184 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1185 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1186 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1187 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1188 >;
1189 };
1190 };
1191
1192 usdhc3 {
1193 pinctrl_usdhc3_1: usdhc3grp-1 {
1194 fsl,pins = <
1195 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1196 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1197 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1198 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1199 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1200 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1201 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1202 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1203 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1204 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1205 >;
1206 };
1207
1208 pinctrl_usdhc3_2: usdhc3grp-2 {
1209 fsl,pins = <
1210 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1211 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1212 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1213 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1214 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1215 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1216 >;
1217 };
1218 };
1219
1220 usdhc4 {
1221 pinctrl_usdhc4_1: usdhc4grp-1 {
1222 fsl,pins = <
1223 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1224 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1225 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1226 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1227 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1228 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1229 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1230 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1231 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1232 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1233 >;
1234 };
1235
1236 pinctrl_usdhc4_2: usdhc4grp-2 {
1237 fsl,pins = <
1238 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1239 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1240 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1241 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1242 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1243 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1244 >;
1245 };
1246 };
1247
1248 weim {
1249 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1250 fsl,pins = <
1251 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1252 >;
1253 };
1254
1255 pinctrl_weim_nor_1: weim_norgrp-1 {
1256 fsl,pins = <
1257 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1258 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1259 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1260 /* data */
1261 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1262 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1263 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1264 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1265 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1266 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1267 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1268 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1269 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1270 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1271 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1272 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1273 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1274 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1275 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1276 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1277 /* address */
1278 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1279 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1280 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1281 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1282 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1283 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1284 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1285 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1286 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1287 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1288 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1289 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1290 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1291 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1292 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1293 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1294 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1295 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1296 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1297 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1298 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1299 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1300 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1301 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1302 >;
1303 };
1304 };
1305 };
1306
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]1307 ldb: ldb@020e0008 {
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1311 gpr = <&gpr>;
1312 status = "disabled";
1313
1314 lvds-channel@0 {
1315 reg = <0>;
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]1316 status = "disabled";
1317 };
1318
1319 lvds-channel@1 {
1320 reg = <1>;
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]1321 status = "disabled";
1322 };
1323 };
1324
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1325 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1326 reg = <0x020e4000 0x4000>;
1327 interrupts = <0 124 0x04>;
1328 };
1329
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1330 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1331 reg = <0x020e8000 0x4000>;
1332 interrupts = <0 125 0x04>;
1333 };
1334
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1335 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1336 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1337 reg = <0x020ec000 0x4000>;
1338 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1339 clocks = <&clks 155>, <&clks 155>;
1340 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]1341 #dma-cells = <3>;
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]1342 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1343 };
1344 };
1345
1346 aips-bus@02100000 { /* AIPS2 */
1347 compatible = "fsl,aips-bus", "simple-bus";
1348 #address-cells = <1>;
1349 #size-cells = <1>;
1350 reg = <0x02100000 0x100000>;
1351 ranges;
1352
1353 caam@02100000 {
1354 reg = <0x02100000 0x40000>;
1355 interrupts = <0 105 0x04 0 106 0x04>;
1356 };
1357
1358 aipstz@0217c000 { /* AIPSTZ2 */
1359 reg = <0x0217c000 0x4000>;
1360 };
1361
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1362 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1363 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1364 reg = <0x02184000 0x200>;
1365 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1366 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1367 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1368 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1369 status = "disabled";
1370 };
1371
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1372 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1373 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1374 reg = <0x02184200 0x200>;
1375 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1376 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1377 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1378 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1379 status = "disabled";
1380 };
1381
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1382 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1383 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1384 reg = <0x02184400 0x200>;
1385 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1386 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1387 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1388 status = "disabled";
1389 };
1390
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1391 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1392 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1393 reg = <0x02184600 0x200>;
1394 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1395 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1396 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1397 status = "disabled";
1398 };
1399
Shawn Guo60984bd2013-04-28 09:59:54 +0800[diff] [blame]1400 usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1401 #index-cells = <1>;
1402 compatible = "fsl,imx6q-usbmisc";
1403 reg = <0x02184800 0x200>;
1404 clocks = <&clks 162>;
1405 };
1406
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1407 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1408 compatible = "fsl,imx6q-fec";
1409 reg = <0x02188000 0x4000>;
1410 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]1411 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]1412 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1413 status = "disabled";
1414 };
1415
1416 mlb@0218c000 {
1417 reg = <0x0218c000 0x4000>;
1418 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1419 };
1420
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1421 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1422 compatible = "fsl,imx6q-usdhc";
1423 reg = <0x02190000 0x4000>;
1424 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1425 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1426 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1427 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1428 status = "disabled";
1429 };
1430
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1431 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1432 compatible = "fsl,imx6q-usdhc";
1433 reg = <0x02194000 0x4000>;
1434 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1435 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1436 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1437 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1438 status = "disabled";
1439 };
1440
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1441 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1442 compatible = "fsl,imx6q-usdhc";
1443 reg = <0x02198000 0x4000>;
1444 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1445 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1446 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1447 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1448 status = "disabled";
1449 };
1450
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1451 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1452 compatible = "fsl,imx6q-usdhc";
1453 reg = <0x0219c000 0x4000>;
1454 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1455 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1456 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1457 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1458 status = "disabled";
1459 };
1460
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1461 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1462 #address-cells = <1>;
1463 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1464 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1465 reg = <0x021a0000 0x4000>;
1466 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1467 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1468 status = "disabled";
1469 };
1470
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1471 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1472 #address-cells = <1>;
1473 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1474 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1475 reg = <0x021a4000 0x4000>;
1476 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1477 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1478 status = "disabled";
1479 };
1480
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1481 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1482 #address-cells = <1>;
1483 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1484 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1485 reg = <0x021a8000 0x4000>;
1486 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1487 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1488 status = "disabled";
1489 };
1490
1491 romcp@021ac000 {
1492 reg = <0x021ac000 0x4000>;
1493 };
1494
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1495 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1496 compatible = "fsl,imx6q-mmdc";
1497 reg = <0x021b0000 0x4000>;
1498 };
1499
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1500 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1501 reg = <0x021b4000 0x4000>;
1502 };
1503
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]1504 weim: weim@021b8000 {
1505 compatible = "fsl,imx6q-weim";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1506 reg = <0x021b8000 0x4000>;
1507 interrupts = <0 14 0x04>;
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]1508 clocks = <&clks 196>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1509 };
1510
Shawn Guo3fe63732013-07-16 21:16:36 +0800[diff] [blame]1511 ocotp: ocotp@021bc000 {
1512 compatible = "fsl,imx6q-ocotp", "syscon";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1513 reg = <0x021bc000 0x4000>;
1514 };
1515
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1516 tzasc@021d0000 { /* TZASC1 */
1517 reg = <0x021d0000 0x4000>;
1518 interrupts = <0 108 0x04>;
1519 };
1520
1521 tzasc@021d4000 { /* TZASC2 */
1522 reg = <0x021d4000 0x4000>;
1523 interrupts = <0 109 0x04>;
1524 };
1525
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1526 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]1527 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1528 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]1529 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1530 };
1531
1532 mipi@021dc000 { /* MIPI-CSI */
1533 reg = <0x021dc000 0x4000>;
1534 };
1535
1536 mipi@021e0000 { /* MIPI-DSI */
1537 reg = <0x021e0000 0x4000>;
1538 };
1539
1540 vdoa@021e4000 {
1541 reg = <0x021e4000 0x4000>;
1542 interrupts = <0 18 0x04>;
1543 };
1544
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1545 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1546 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1547 reg = <0x021e8000 0x4000>;
1548 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1549 clocks = <&clks 160>, <&clks 161>;
1550 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1551 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1552 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1553 status = "disabled";
1554 };
1555
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1556 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1557 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1558 reg = <0x021ec000 0x4000>;
1559 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1560 clocks = <&clks 160>, <&clks 161>;
1561 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1562 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1563 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1564 status = "disabled";
1565 };
1566
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1567 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1568 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1569 reg = <0x021f0000 0x4000>;
1570 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1571 clocks = <&clks 160>, <&clks 161>;
1572 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1573 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1574 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1575 status = "disabled";
1576 };
1577
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1578 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1579 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1580 reg = <0x021f4000 0x4000>;
1581 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1582 clocks = <&clks 160>, <&clks 161>;
1583 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1584 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1585 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1586 status = "disabled";
1587 };
1588 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]1589
1590 ipu1: ipu@02400000 {
1591 #crtc-cells = <1>;
1592 compatible = "fsl,imx6q-ipu";
1593 reg = <0x02400000 0x400000>;
1594 interrupts = <0 6 0x4 0 5 0x4>;
1595 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1596 clock-names = "bus", "di0", "di1";
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]1597 resets = <&src 2>;
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]1598 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1599 };
1600};