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Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
Ben Hutchingsf7a6d2c2013-08-29 23:32:48 +01002 * Driver for Solarflare network controllers and boards
Ben Hutchings8ceee662008-04-27 12:55:59 +01003 * Copyright 2005-2006 Fen Systems Ltd.
Ben Hutchingsf7a6d2c2013-08-29 23:32:48 +01004 * Copyright 2005-2013 Solarflare Communications Inc.
Ben Hutchings8ceee662008-04-27 12:55:59 +01005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11/* Common definitions for all Efx net driver code */
12
13#ifndef EFX_NET_DRIVER_H
14#define EFX_NET_DRIVER_H
15
Ben Hutchings8ceee662008-04-27 12:55:59 +010016#include <linux/netdevice.h>
17#include <linux/etherdevice.h>
18#include <linux/ethtool.h>
19#include <linux/if_vlan.h>
Steve Hodgson90d683a2010-06-01 11:19:39 +000020#include <linux/timer.h>
Ben Hutchings68e7f452009-04-29 08:05:08 +000021#include <linux/mdio.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010022#include <linux/list.h>
23#include <linux/pci.h>
24#include <linux/device.h>
25#include <linux/highmem.h>
26#include <linux/workqueue.h>
Ben Hutchingscd2d5b52012-02-14 00:48:07 +000027#include <linux/mutex.h>
David S. Miller10ed61c2010-09-21 16:11:06 -070028#include <linux/vmalloc.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010029#include <linux/i2c.h>
Ben Hutchings45a3fd52012-11-28 04:38:14 +000030#include <linux/mtd/mtd.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010031
32#include "enum.h"
33#include "bitfield.h"
Ben Hutchingsadd72472012-11-08 01:46:53 +000034#include "filter.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010035
Ben Hutchings8ceee662008-04-27 12:55:59 +010036/**************************************************************************
37 *
38 * Build definitions
39 *
40 **************************************************************************/
Ben Hutchingsc5d5f5f2010-06-23 11:30:26 +000041
Ben Hutchings8127d662013-08-29 19:19:29 +010042#define EFX_DRIVER_VERSION "4.0"
Ben Hutchings8ceee662008-04-27 12:55:59 +010043
Ben Hutchings5f3f9d62011-11-04 22:29:14 +000044#ifdef DEBUG
Ben Hutchings8ceee662008-04-27 12:55:59 +010045#define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
46#define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
47#else
48#define EFX_BUG_ON_PARANOID(x) do {} while (0)
49#define EFX_WARN_ON_PARANOID(x) do {} while (0)
50#endif
51
Ben Hutchings8ceee662008-04-27 12:55:59 +010052/**************************************************************************
53 *
54 * Efx data structures
55 *
56 **************************************************************************/
57
Ben Hutchingsa16e5b22012-02-14 00:40:12 +000058#define EFX_MAX_CHANNELS 32U
Ben Hutchings8ceee662008-04-27 12:55:59 +010059#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
Ben Hutchingscd2d5b52012-02-14 00:48:07 +000060#define EFX_EXTRA_CHANNEL_IOV 0
Stuart Hodgson7c236c42012-09-03 11:09:36 +010061#define EFX_EXTRA_CHANNEL_PTP 1
62#define EFX_MAX_EXTRA_CHANNELS 2U
Ben Hutchings8ceee662008-04-27 12:55:59 +010063
Ben Hutchingsa4900ac2010-04-28 09:30:43 +000064/* Checksum generation is a per-queue option in hardware, so each
65 * queue visible to the networking core is backed by two hardware TX
66 * queues. */
Ben Hutchings94b274b2011-01-10 21:18:20 +000067#define EFX_MAX_TX_TC 2
68#define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
69#define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
70#define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
71#define EFX_TXQ_TYPES 4
72#define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
Ben Hutchings60ac1062008-09-01 12:44:59 +010073
Ben Hutchings85740cdf2013-01-29 23:33:15 +000074/* Maximum possible MTU the driver supports */
75#define EFX_MAX_MTU (9 * 1024)
76
Ben Hutchings950c54d2013-05-13 12:01:22 +000077/* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
78 * and should be a multiple of the cache line size.
79 */
80#define EFX_RX_USR_BUF_SIZE (2048 - 256)
81
82/* If possible, we should ensure cache line alignment at start and end
83 * of every buffer. Otherwise, we just need to ensure 4-byte
84 * alignment of the network header.
85 */
86#if NET_IP_ALIGN == 0
87#define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
88#else
89#define EFX_RX_BUF_ALIGNMENT 4
90#endif
Ben Hutchings85740cdf2013-01-29 23:33:15 +000091
Stuart Hodgson7c236c42012-09-03 11:09:36 +010092/* Forward declare Precision Time Protocol (PTP) support structure. */
93struct efx_ptp_data;
Daniel Pieczko9ec06592013-11-21 17:11:25 +000094struct hwtstamp_config;
Stuart Hodgson7c236c42012-09-03 11:09:36 +010095
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +010096struct efx_self_tests;
97
Ben Hutchings8ceee662008-04-27 12:55:59 +010098/**
Ben Hutchingscaa75582012-09-19 00:31:42 +010099 * struct efx_buffer - A general-purpose DMA buffer
100 * @addr: host base address of the buffer
Ben Hutchings8ceee662008-04-27 12:55:59 +0100101 * @dma_addr: DMA base address of the buffer
102 * @len: Buffer length, in bytes
Ben Hutchings8ceee662008-04-27 12:55:59 +0100103 *
Ben Hutchingscaa75582012-09-19 00:31:42 +0100104 * The NIC uses these buffers for its interrupt status registers and
105 * MAC stats dumps.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100106 */
Ben Hutchingscaa75582012-09-19 00:31:42 +0100107struct efx_buffer {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100108 void *addr;
109 dma_addr_t dma_addr;
110 unsigned int len;
Ben Hutchingscaa75582012-09-19 00:31:42 +0100111};
112
113/**
114 * struct efx_special_buffer - DMA buffer entered into buffer table
115 * @buf: Standard &struct efx_buffer
116 * @index: Buffer index within controller;s buffer table
117 * @entries: Number of buffer table entries
118 *
119 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
120 * Event and descriptor rings are addressed via one or more buffer
121 * table entries (and so can be physically non-contiguous, although we
122 * currently do not take advantage of that). On Falcon and Siena we
123 * have to take care of allocating and initialising the entries
124 * ourselves. On later hardware this is managed by the firmware and
125 * @index and @entries are left as 0.
126 */
127struct efx_special_buffer {
128 struct efx_buffer buf;
Ben Hutchings5bbe2f42012-02-13 23:14:23 +0000129 unsigned int index;
130 unsigned int entries;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100131};
132
133/**
Ben Hutchings7668ff92012-05-17 20:52:20 +0100134 * struct efx_tx_buffer - buffer state for a TX descriptor
135 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
136 * freed when descriptor completes
Ben Hutchingsf7251a92012-05-17 18:40:54 +0100137 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be
138 * freed when descriptor completes.
Ben Hutchingsba8977b2013-01-08 23:43:19 +0000139 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100140 * @dma_addr: DMA address of the fragment.
Ben Hutchings7668ff92012-05-17 20:52:20 +0100141 * @flags: Flags for allocation and DMA mapping type
Ben Hutchings8ceee662008-04-27 12:55:59 +0100142 * @len: Length of this fragment.
143 * This field is zero when the queue slot is empty.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100144 * @unmap_len: Length of this fragment to unmap
Alexandre Rames2acdb922013-10-31 12:42:32 +0000145 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
146 * Only valid if @unmap_len != 0.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100147 */
148struct efx_tx_buffer {
Ben Hutchings7668ff92012-05-17 20:52:20 +0100149 union {
150 const struct sk_buff *skb;
Ben Hutchingsf7251a92012-05-17 18:40:54 +0100151 void *heap_buf;
Ben Hutchings7668ff92012-05-17 20:52:20 +0100152 };
Ben Hutchingsba8977b2013-01-08 23:43:19 +0000153 union {
154 efx_qword_t option;
155 dma_addr_t dma_addr;
156 };
Ben Hutchings7668ff92012-05-17 20:52:20 +0100157 unsigned short flags;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100158 unsigned short len;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100159 unsigned short unmap_len;
Alexandre Rames2acdb922013-10-31 12:42:32 +0000160 unsigned short dma_offset;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100161};
Ben Hutchings7668ff92012-05-17 20:52:20 +0100162#define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
163#define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
Ben Hutchingsf7251a92012-05-17 18:40:54 +0100164#define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */
Ben Hutchings7668ff92012-05-17 20:52:20 +0100165#define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
Ben Hutchingsba8977b2013-01-08 23:43:19 +0000166#define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
Ben Hutchings8ceee662008-04-27 12:55:59 +0100167
168/**
169 * struct efx_tx_queue - An Efx TX queue
170 *
171 * This is a ring buffer of TX fragments.
172 * Since the TX completion path always executes on the same
173 * CPU and the xmit path can operate on different CPUs,
174 * performance is increased by ensuring that the completion
175 * path and the xmit path operate on different cache lines.
176 * This is particularly important if the xmit path is always
177 * executing on one CPU which is different from the completion
178 * path. There is also a cache line for members which are
179 * read but not written on the fast path.
180 *
181 * @efx: The associated Efx NIC
182 * @queue: DMA queue number
Ben Hutchings8ceee662008-04-27 12:55:59 +0100183 * @channel: The associated channel
Ben Hutchingsc04bfc62010-12-10 01:24:16 +0000184 * @core_txq: The networking core TX queue structure
Ben Hutchings8ceee662008-04-27 12:55:59 +0100185 * @buffer: The software buffer ring
Ben Hutchingsf7251a92012-05-17 18:40:54 +0100186 * @tsoh_page: Array of pages of TSO header buffers
Ben Hutchings8ceee662008-04-27 12:55:59 +0100187 * @txd: The hardware descriptor ring
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000188 * @ptr_mask: The size of the ring minus 1.
Ben Hutchings183233b2013-06-28 21:47:12 +0100189 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
190 * Size of the region is efx_piobuf_size.
191 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
Ben Hutchings94b274b2011-01-10 21:18:20 +0000192 * @initialised: Has hardware queue been initialised?
Ben Hutchings8ceee662008-04-27 12:55:59 +0100193 * @read_count: Current read pointer.
194 * This is the number of buffers that have been removed from both rings.
Ben Hutchingscd385572010-11-15 23:53:11 +0000195 * @old_write_count: The value of @write_count when last checked.
196 * This is here for performance reasons. The xmit path will
197 * only get the up-to-date value of @write_count if this
198 * variable indicates that the queue is empty. This is to
199 * avoid cache-line ping-pong between the xmit path and the
200 * completion path.
Ben Hutchings02e12162013-04-27 01:55:21 +0100201 * @merge_events: Number of TX merged completion events
Ben Hutchings8ceee662008-04-27 12:55:59 +0100202 * @insert_count: Current insert pointer
203 * This is the number of buffers that have been added to the
204 * software ring.
205 * @write_count: Current write pointer
206 * This is the number of buffers that have been added to the
207 * hardware ring.
208 * @old_read_count: The value of read_count when last checked.
209 * This is here for performance reasons. The xmit path will
210 * only get the up-to-date value of read_count if this
211 * variable indicates that the queue is full. This is to
212 * avoid cache-line ping-pong between the xmit path and the
213 * completion path.
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100214 * @tso_bursts: Number of times TSO xmit invoked by kernel
215 * @tso_long_headers: Number of packets with headers too long for standard
216 * blocks
217 * @tso_packets: Number of packets via the TSO xmit path
Ben Hutchingscd385572010-11-15 23:53:11 +0000218 * @pushes: Number of times the TX push feature has been used
Jon Cooperee45fd92013-09-02 18:24:29 +0100219 * @pio_packets: Number of times the TX PIO feature has been used
Ben Hutchingscd385572010-11-15 23:53:11 +0000220 * @empty_read_count: If the completion path has seen the queue as empty
221 * and the transmission path has not yet checked this, the value of
222 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100223 */
224struct efx_tx_queue {
225 /* Members which don't change on the fast path */
226 struct efx_nic *efx ____cacheline_aligned_in_smp;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000227 unsigned queue;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100228 struct efx_channel *channel;
Ben Hutchingsc04bfc62010-12-10 01:24:16 +0000229 struct netdev_queue *core_txq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100230 struct efx_tx_buffer *buffer;
Ben Hutchingsf7251a92012-05-17 18:40:54 +0100231 struct efx_buffer *tsoh_page;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100232 struct efx_special_buffer txd;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000233 unsigned int ptr_mask;
Ben Hutchings183233b2013-06-28 21:47:12 +0100234 void __iomem *piobuf;
235 unsigned int piobuf_offset;
Ben Hutchings94b274b2011-01-10 21:18:20 +0000236 bool initialised;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100237
238 /* Members used mainly on the completion path */
239 unsigned int read_count ____cacheline_aligned_in_smp;
Ben Hutchingscd385572010-11-15 23:53:11 +0000240 unsigned int old_write_count;
Ben Hutchings02e12162013-04-27 01:55:21 +0100241 unsigned int merge_events;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100242
243 /* Members used only on the xmit path */
244 unsigned int insert_count ____cacheline_aligned_in_smp;
245 unsigned int write_count;
246 unsigned int old_read_count;
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100247 unsigned int tso_bursts;
248 unsigned int tso_long_headers;
249 unsigned int tso_packets;
Ben Hutchingscd385572010-11-15 23:53:11 +0000250 unsigned int pushes;
Jon Cooperee45fd92013-09-02 18:24:29 +0100251 unsigned int pio_packets;
Ben Hutchingscd385572010-11-15 23:53:11 +0000252
253 /* Members shared between paths and sometimes updated */
254 unsigned int empty_read_count ____cacheline_aligned_in_smp;
255#define EFX_EMPTY_COUNT_VALID 0x80000000
Daniel Pieczko525d9e82012-10-02 13:36:18 +0100256 atomic_t flush_outstanding;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100257};
258
259/**
260 * struct efx_rx_buffer - An Efx RX data buffer
261 * @dma_addr: DMA base address of the buffer
Alexandre Rames97d48a12013-01-11 12:26:21 +0000262 * @page: The associated page buffer.
Ben Hutchingsdb339562011-08-26 18:05:11 +0100263 * Will be %NULL if the buffer slot is currently free.
Ben Hutchingsb74e3e82013-01-29 23:33:15 +0000264 * @page_offset: If pending: offset in @page of DMA base address.
265 * If completed: offset in @page of Ethernet header.
Ben Hutchings80c2e712013-01-23 21:52:13 +0000266 * @len: If pending: length for DMA descriptor.
267 * If completed: received length, excluding hash prefix.
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000268 * @flags: Flags for buffer and packet state. These are only set on the
269 * first buffer of a scattered packet.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100270 */
271struct efx_rx_buffer {
272 dma_addr_t dma_addr;
Alexandre Rames97d48a12013-01-11 12:26:21 +0000273 struct page *page;
Ben Hutchingsb590ace2013-01-10 23:51:54 +0000274 u16 page_offset;
275 u16 len;
Ben Hutchingsdb339562011-08-26 18:05:11 +0100276 u16 flags;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100277};
Ben Hutchings179ea7f2013-03-07 16:31:17 +0000278#define EFX_RX_BUF_LAST_IN_PAGE 0x0001
Ben Hutchingsdb339562011-08-26 18:05:11 +0100279#define EFX_RX_PKT_CSUMMED 0x0002
280#define EFX_RX_PKT_DISCARD 0x0004
Ben Hutchingsd07df8e2013-05-16 18:38:11 +0100281#define EFX_RX_PKT_TCP 0x0040
Ben Hutchings3dced742013-04-27 01:55:18 +0100282#define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
Ben Hutchings8ceee662008-04-27 12:55:59 +0100283
284/**
Steve Hodgson62b330b2010-06-01 11:20:53 +0000285 * struct efx_rx_page_state - Page-based rx buffer state
286 *
287 * Inserted at the start of every page allocated for receive buffers.
288 * Used to facilitate sharing dma mappings between recycled rx buffers
289 * and those passed up to the kernel.
290 *
291 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
292 * When refcnt falls to zero, the page is unmapped for dma
293 * @dma_addr: The dma address of this page.
294 */
295struct efx_rx_page_state {
296 unsigned refcnt;
297 dma_addr_t dma_addr;
298
299 unsigned int __pad[0] ____cacheline_aligned;
300};
301
302/**
Ben Hutchings8ceee662008-04-27 12:55:59 +0100303 * struct efx_rx_queue - An Efx RX queue
304 * @efx: The associated Efx NIC
Stuart Hodgson79d68b32012-07-16 17:08:33 +0100305 * @core_index: Index of network core RX queue. Will be >= 0 iff this
306 * is associated with a real RX queue.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100307 * @buffer: The software buffer ring
308 * @rxd: The hardware descriptor ring
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000309 * @ptr_mask: The size of the ring minus 1.
Ben Hutchingsd8aec742013-05-27 16:52:54 +0100310 * @refill_enabled: Enable refill whenever fill level is low
Ben Hutchings9f2cb712012-02-08 00:11:20 +0000311 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
312 * @rxq_flush_pending.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100313 * @added_count: Number of buffers added to the receive queue.
314 * @notified_count: Number of buffers given to NIC (<= @added_count).
315 * @removed_count: Number of buffers removed from the receive queue.
Jon Coopere8c68c02013-03-08 10:18:28 +0000316 * @scatter_n: Used by NIC specific receive code.
317 * @scatter_len: Used by NIC specific receive code.
Daniel Pieczko27689352013-02-13 10:54:41 +0000318 * @page_ring: The ring to store DMA mapped pages for reuse.
319 * @page_add: Counter to calculate the write pointer for the recycle ring.
320 * @page_remove: Counter to calculate the read pointer for the recycle ring.
321 * @page_recycle_count: The number of pages that have been recycled.
322 * @page_recycle_failed: The number of pages that couldn't be recycled because
323 * the kernel still held a reference to them.
324 * @page_recycle_full: The number of pages that were released because the
325 * recycle ring was full.
326 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100327 * @max_fill: RX descriptor maximum fill level (<= ring size)
328 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
329 * (<= @max_fill)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100330 * @min_fill: RX descriptor minimum non-zero fill level.
331 * This records the minimum fill level observed when a ring
332 * refill was triggered.
Daniel Pieczko27689352013-02-13 10:54:41 +0000333 * @recycle_count: RX buffer recycle counter.
Steve Hodgson90d683a2010-06-01 11:19:39 +0000334 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
Ben Hutchings8ceee662008-04-27 12:55:59 +0100335 */
336struct efx_rx_queue {
337 struct efx_nic *efx;
Stuart Hodgson79d68b32012-07-16 17:08:33 +0100338 int core_index;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100339 struct efx_rx_buffer *buffer;
340 struct efx_special_buffer rxd;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000341 unsigned int ptr_mask;
Ben Hutchingsd8aec742013-05-27 16:52:54 +0100342 bool refill_enabled;
Ben Hutchings9f2cb712012-02-08 00:11:20 +0000343 bool flush_pending;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100344
Ben Hutchings9bc2fc92013-01-29 23:33:14 +0000345 unsigned int added_count;
346 unsigned int notified_count;
347 unsigned int removed_count;
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000348 unsigned int scatter_n;
Jon Coopere8c68c02013-03-08 10:18:28 +0000349 unsigned int scatter_len;
Daniel Pieczko27689352013-02-13 10:54:41 +0000350 struct page **page_ring;
351 unsigned int page_add;
352 unsigned int page_remove;
353 unsigned int page_recycle_count;
354 unsigned int page_recycle_failed;
355 unsigned int page_recycle_full;
356 unsigned int page_ptr_mask;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100357 unsigned int max_fill;
358 unsigned int fast_fill_trigger;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100359 unsigned int min_fill;
360 unsigned int min_overfill;
Daniel Pieczko27689352013-02-13 10:54:41 +0000361 unsigned int recycle_count;
Steve Hodgson90d683a2010-06-01 11:19:39 +0000362 struct timer_list slow_fill;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100363 unsigned int slow_fill_count;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100364};
365
Ben Hutchings8ceee662008-04-27 12:55:59 +0100366enum efx_rx_alloc_method {
367 RX_ALLOC_METHOD_AUTO = 0,
368 RX_ALLOC_METHOD_SKB = 1,
369 RX_ALLOC_METHOD_PAGE = 2,
370};
371
Jon Cooperbd9a2652013-11-18 12:54:41 +0000372enum efx_sync_events_state {
373 SYNC_EVENTS_DISABLED = 0,
374 SYNC_EVENTS_QUIESCENT,
375 SYNC_EVENTS_REQUESTED,
376 SYNC_EVENTS_VALID,
377};
378
Ben Hutchings8ceee662008-04-27 12:55:59 +0100379/**
380 * struct efx_channel - An Efx channel
381 *
382 * A channel comprises an event queue, at least one TX queue, at least
383 * one RX queue, and an associated tasklet for processing the event
384 * queue.
385 *
386 * @efx: Associated Efx NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100387 * @channel: Channel instance number
Ben Hutchings7f967c02012-02-13 23:45:02 +0000388 * @type: Channel type definition
Ben Hutchingsbe3fc092012-10-08 18:21:51 +0100389 * @eventq_init: Event queue initialised flag
Ben Hutchings8ceee662008-04-27 12:55:59 +0100390 * @enabled: Channel enabled indicator
391 * @irq: IRQ number (MSI and MSI-X only)
Ben Hutchings0d86ebd2009-10-23 08:32:13 +0000392 * @irq_moderation: IRQ moderation value (in hardware ticks)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100393 * @napi_dev: Net device used with NAPI
394 * @napi_str: NAPI control structure
Ben Hutchings8ceee662008-04-27 12:55:59 +0100395 * @eventq: Event queue buffer
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000396 * @eventq_mask: Event queue pointer mask
Ben Hutchings8ceee662008-04-27 12:55:59 +0100397 * @eventq_read_ptr: Event queue read pointer
Ben Hutchingsdd407812012-02-28 23:40:21 +0000398 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000399 * @irq_count: Number of IRQs since last adaptive moderation decision
400 * @irq_mod_score: IRQ moderation score
Ben Hutchings8ceee662008-04-27 12:55:59 +0100401 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
Ben Hutchings8ceee662008-04-27 12:55:59 +0100402 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
403 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000404 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
Ben Hutchings8ceee662008-04-27 12:55:59 +0100405 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
406 * @n_rx_overlength: Count of RX_OVERLENGTH errors
407 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000408 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
409 * lack of descriptors
Ben Hutchings8127d662013-08-29 19:19:29 +0100410 * @n_rx_merge_events: Number of RX merged completion events
411 * @n_rx_merge_packets: Number of RX packets completed by merged events
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000412 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
413 * __efx_rx_packet(), or zero if there is none
414 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
415 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
Ben Hutchings8313aca2010-09-10 06:41:57 +0000416 * @rx_queue: RX queue for this channel
Ben Hutchings8313aca2010-09-10 06:41:57 +0000417 * @tx_queue: TX queues for this channel
Jon Cooperbd9a2652013-11-18 12:54:41 +0000418 * @sync_events_state: Current state of sync events on this channel
419 * @sync_timestamp_major: Major part of the last ptp sync event
420 * @sync_timestamp_minor: Minor part of the last ptp sync event
Ben Hutchings8ceee662008-04-27 12:55:59 +0100421 */
422struct efx_channel {
423 struct efx_nic *efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100424 int channel;
Ben Hutchings7f967c02012-02-13 23:45:02 +0000425 const struct efx_channel_type *type;
Ben Hutchingsbe3fc092012-10-08 18:21:51 +0100426 bool eventq_init;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100427 bool enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100428 int irq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100429 unsigned int irq_moderation;
430 struct net_device *napi_dev;
431 struct napi_struct napi_str;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100432 struct efx_special_buffer eventq;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000433 unsigned int eventq_mask;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100434 unsigned int eventq_read_ptr;
Ben Hutchingsdd407812012-02-28 23:40:21 +0000435 int event_test_cpu;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100436
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000437 unsigned int irq_count;
438 unsigned int irq_mod_score;
Ben Hutchings64d8ad62011-01-05 00:50:41 +0000439#ifdef CONFIG_RFS_ACCEL
440 unsigned int rfs_filters_added;
441#endif
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000442
Ben Hutchings8ceee662008-04-27 12:55:59 +0100443 unsigned n_rx_tobe_disc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100444 unsigned n_rx_ip_hdr_chksum_err;
445 unsigned n_rx_tcp_udp_chksum_err;
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000446 unsigned n_rx_mcast_mismatch;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100447 unsigned n_rx_frm_trunc;
448 unsigned n_rx_overlength;
449 unsigned n_skbuff_leaks;
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000450 unsigned int n_rx_nodesc_trunc;
Ben Hutchings8127d662013-08-29 19:19:29 +0100451 unsigned int n_rx_merge_events;
452 unsigned int n_rx_merge_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100453
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000454 unsigned int rx_pkt_n_frags;
455 unsigned int rx_pkt_index;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100456
Ben Hutchings8313aca2010-09-10 06:41:57 +0000457 struct efx_rx_queue rx_queue;
Ben Hutchings94b274b2011-01-10 21:18:20 +0000458 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
Jon Cooperbd9a2652013-11-18 12:54:41 +0000459
460 enum efx_sync_events_state sync_events_state;
461 u32 sync_timestamp_major;
462 u32 sync_timestamp_minor;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100463};
464
Ben Hutchings7f967c02012-02-13 23:45:02 +0000465/**
Ben Hutchingsd8291182012-10-05 23:35:41 +0100466 * struct efx_msi_context - Context for each MSI
467 * @efx: The associated NIC
468 * @index: Index of the channel/IRQ
469 * @name: Name of the channel/IRQ
470 *
471 * Unlike &struct efx_channel, this is never reallocated and is always
472 * safe for the IRQ handler to access.
473 */
474struct efx_msi_context {
475 struct efx_nic *efx;
476 unsigned int index;
477 char name[IFNAMSIZ + 6];
478};
479
480/**
Ben Hutchings7f967c02012-02-13 23:45:02 +0000481 * struct efx_channel_type - distinguishes traffic and extra channels
482 * @handle_no_channel: Handle failure to allocate an extra channel
483 * @pre_probe: Set up extra state prior to initialisation
484 * @post_remove: Tear down extra state after finalisation, if allocated.
485 * May be called on channels that have not been probed.
486 * @get_name: Generate the channel's name (used for its IRQ handler)
487 * @copy: Copy the channel state prior to reallocation. May be %NULL if
488 * reallocation is not supported.
Stuart Hodgsonc31e5f92012-07-18 09:52:11 +0100489 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
Ben Hutchings7f967c02012-02-13 23:45:02 +0000490 * @keep_eventq: Flag for whether event queue should be kept initialised
491 * while the device is stopped
492 */
493struct efx_channel_type {
494 void (*handle_no_channel)(struct efx_nic *);
495 int (*pre_probe)(struct efx_channel *);
Stuart Hodgsonc31e5f92012-07-18 09:52:11 +0100496 void (*post_remove)(struct efx_channel *);
Ben Hutchings7f967c02012-02-13 23:45:02 +0000497 void (*get_name)(struct efx_channel *, char *buf, size_t len);
498 struct efx_channel *(*copy)(const struct efx_channel *);
Ben Hutchings4a74dc62013-03-05 20:13:54 +0000499 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
Ben Hutchings7f967c02012-02-13 23:45:02 +0000500 bool keep_eventq;
501};
502
Ben Hutchings398468e2009-11-23 16:03:45 +0000503enum efx_led_mode {
504 EFX_LED_OFF = 0,
505 EFX_LED_ON = 1,
506 EFX_LED_DEFAULT = 2
507};
508
Ben Hutchingsc4593022009-11-23 16:08:17 +0000509#define STRING_TABLE_LOOKUP(val, member) \
510 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
511
Ben Hutchings18e83e42012-01-05 19:05:20 +0000512extern const char *const efx_loopback_mode_names[];
Ben Hutchingsc4593022009-11-23 16:08:17 +0000513extern const unsigned int efx_loopback_mode_max;
514#define LOOPBACK_MODE(efx) \
515 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
516
Ben Hutchings18e83e42012-01-05 19:05:20 +0000517extern const char *const efx_reset_type_names[];
Ben Hutchingsc4593022009-11-23 16:08:17 +0000518extern const unsigned int efx_reset_type_max;
519#define RESET_TYPE(type) \
520 STRING_TABLE_LOOKUP(type, efx_reset_type)
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100521
Ben Hutchings8ceee662008-04-27 12:55:59 +0100522enum efx_int_mode {
523 /* Be careful if altering to correct macro below */
524 EFX_INT_MODE_MSIX = 0,
525 EFX_INT_MODE_MSI = 1,
526 EFX_INT_MODE_LEGACY = 2,
527 EFX_INT_MODE_MAX /* Insert any new items before this */
528};
529#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
530
Ben Hutchings8ceee662008-04-27 12:55:59 +0100531enum nic_state {
Ben Hutchingsf16aeea2012-07-27 19:31:16 +0100532 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
533 STATE_READY = 1, /* hardware ready and netdev registered */
534 STATE_DISABLED = 2, /* device disabled due to hardware errors */
Alexandre Rames626950d2013-01-14 17:20:22 +0000535 STATE_RECOVERY = 3, /* device recovering from PCI error */
Ben Hutchings8ceee662008-04-27 12:55:59 +0100536};
537
Ben Hutchings8ceee662008-04-27 12:55:59 +0100538/* Forward declaration */
539struct efx_nic;
540
541/* Pseudo bit-mask flow control field */
David S. Millerb56269462011-05-17 17:53:22 -0400542#define EFX_FC_RX FLOW_CTRL_RX
543#define EFX_FC_TX FLOW_CTRL_TX
544#define EFX_FC_AUTO 4
Ben Hutchings8ceee662008-04-27 12:55:59 +0100545
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800546/**
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000547 * struct efx_link_state - Current state of the link
548 * @up: Link is up
549 * @fd: Link is full-duplex
550 * @fc: Actual flow control flags
551 * @speed: Link speed (Mbps)
552 */
553struct efx_link_state {
554 bool up;
555 bool fd;
David S. Millerb56269462011-05-17 17:53:22 -0400556 u8 fc;
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000557 unsigned int speed;
558};
559
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000560static inline bool efx_link_state_equal(const struct efx_link_state *left,
561 const struct efx_link_state *right)
562{
563 return left->up == right->up && left->fd == right->fd &&
564 left->fc == right->fc && left->speed == right->speed;
565}
566
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000567/**
Ben Hutchings8ceee662008-04-27 12:55:59 +0100568 * struct efx_phy_operations - Efx PHY operations table
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000569 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
570 * efx->loopback_modes.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100571 * @init: Initialise PHY
572 * @fini: Shut down PHY
573 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000574 * @poll: Update @link_state and report whether it changed.
575 * Serialised by the mac_lock.
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800576 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
577 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000578 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800579 * (only needed where AN bit is set in mmds)
Ben Hutchings4f16c072010-02-03 09:30:50 +0000580 * @test_alive: Test that PHY is 'alive' (online)
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000581 * @test_name: Get the name of a PHY-specific test/result
Ben Hutchings4f16c072010-02-03 09:30:50 +0000582 * @run_tests: Run tests and record results as appropriate (offline).
Ben Hutchings17967212008-12-26 13:47:25 -0800583 * Flags are the ethtool tests flags.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100584 */
585struct efx_phy_operations {
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000586 int (*probe) (struct efx_nic *efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100587 int (*init) (struct efx_nic *efx);
588 void (*fini) (struct efx_nic *efx);
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000589 void (*remove) (struct efx_nic *efx);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000590 int (*reconfigure) (struct efx_nic *efx);
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000591 bool (*poll) (struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800592 void (*get_settings) (struct efx_nic *efx,
593 struct ethtool_cmd *ecmd);
594 int (*set_settings) (struct efx_nic *efx,
595 struct ethtool_cmd *ecmd);
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000596 void (*set_npage_adv) (struct efx_nic *efx, u32);
Ben Hutchings4f16c072010-02-03 09:30:50 +0000597 int (*test_alive) (struct efx_nic *efx);
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000598 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
Ben Hutchings17967212008-12-26 13:47:25 -0800599 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
Stuart Hodgsonc087bd22012-05-01 18:50:43 +0100600 int (*get_module_eeprom) (struct efx_nic *efx,
601 struct ethtool_eeprom *ee,
602 u8 *data);
603 int (*get_module_info) (struct efx_nic *efx,
604 struct ethtool_modinfo *modinfo);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100605};
606
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100607/**
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000608 * enum efx_phy_mode - PHY operating mode flags
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100609 * @PHY_MODE_NORMAL: on and should pass traffic
610 * @PHY_MODE_TX_DISABLED: on with TX disabled
Ben Hutchings3e133c42008-11-04 20:34:56 +0000611 * @PHY_MODE_LOW_POWER: set to low power through MDIO
612 * @PHY_MODE_OFF: switched off through external control
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100613 * @PHY_MODE_SPECIAL: on but will not pass traffic
614 */
615enum efx_phy_mode {
616 PHY_MODE_NORMAL = 0,
617 PHY_MODE_TX_DISABLED = 1,
Ben Hutchings3e133c42008-11-04 20:34:56 +0000618 PHY_MODE_LOW_POWER = 2,
619 PHY_MODE_OFF = 4,
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100620 PHY_MODE_SPECIAL = 8,
621};
622
623static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
624{
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100625 return !!(mode & ~PHY_MODE_TX_DISABLED);
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100626}
627
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000628/**
629 * struct efx_hw_stat_desc - Description of a hardware statistic
630 * @name: Name of the statistic as visible through ethtool, or %NULL if
631 * it should not be exposed
632 * @dma_width: Width in bits (0 for non-DMA statistics)
633 * @offset: Offset within stats (ignored for non-DMA statistics)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100634 */
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000635struct efx_hw_stat_desc {
636 const char *name;
637 u16 dma_width;
638 u16 offset;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100639};
640
641/* Number of bits used in a multicast filter hash address */
642#define EFX_MCAST_HASH_BITS 8
643
644/* Number of (single-bit) entries in a multicast filter hash */
645#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
646
647/* An Efx multicast filter hash */
648union efx_multicast_hash {
649 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
650 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
651};
652
Ben Hutchingscd2d5b52012-02-14 00:48:07 +0000653struct efx_vf;
654struct vfdi_status;
Ben Hutchings64eebcf2010-09-20 08:43:07 +0000655
Ben Hutchings8ceee662008-04-27 12:55:59 +0100656/**
657 * struct efx_nic - an Efx NIC
658 * @name: Device name (net device name or bus id before net device registered)
659 * @pci_dev: The PCI device
660 * @type: Controller type attributes
661 * @legacy_irq: IRQ number
Ben Hutchings8d9853d2008-07-18 19:01:20 +0100662 * @workqueue: Workqueue for port reconfigures and the HW monitor.
663 * Work items do not hold and must not acquire RTNL.
Ben Hutchings6977dc62008-12-26 13:44:39 -0800664 * @workqueue_name: Name of workqueue
Ben Hutchings8ceee662008-04-27 12:55:59 +0100665 * @reset_work: Scheduled reset workitem
Ben Hutchings8ceee662008-04-27 12:55:59 +0100666 * @membase_phys: Memory BAR value as physical address
667 * @membase: Memory BAR value
Ben Hutchings8ceee662008-04-27 12:55:59 +0100668 * @interrupt_mode: Interrupt mode
Ben Hutchingscc180b62011-12-08 19:51:47 +0000669 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000670 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
671 * @irq_rx_moderation: IRQ moderation time for RX event queues
Ben Hutchings62776d02010-06-23 11:30:07 +0000672 * @msg_enable: Log message enable flags
Ben Hutchingsf16aeea2012-07-27 19:31:16 +0100673 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
Ben Hutchingsa7d529a2011-06-24 20:46:31 +0100674 * @reset_pending: Bitmask for pending resets
Ben Hutchings8ceee662008-04-27 12:55:59 +0100675 * @tx_queue: TX DMA queues
676 * @rx_queue: RX DMA queues
677 * @channel: Channels
Ben Hutchingsd8291182012-10-05 23:35:41 +0100678 * @msi_context: Context for each MSI
Ben Hutchings7f967c02012-02-13 23:45:02 +0000679 * @extra_channel_types: Types of extra (non-traffic) channels that
680 * should be allocated for this NIC
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000681 * @rxq_entries: Size of receive queues requested by user.
682 * @txq_entries: Size of transmit queues requested by user.
Ben Hutchings14bf7182012-05-22 01:27:58 +0100683 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
684 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
Ben Hutchings28e47c42012-02-15 01:58:49 +0000685 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
686 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
687 * @sram_lim_qw: Qword address limit of SRAM
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000688 * @next_buffer_table: First available buffer table id
Neil Turton28b581a2008-12-12 21:41:06 -0800689 * @n_channels: Number of channels in use
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000690 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
691 * @n_tx_channels: Number of channels used for TX
Andrew Rybchenko2ec03012013-11-16 11:02:27 +0400692 * @rx_ip_align: RX DMA address offset to have IP header aligned in
693 * in accordance with NET_IP_ALIGN
Ben Hutchings272baee2013-01-29 23:33:14 +0000694 * @rx_dma_len: Current maximum RX DMA length
Ben Hutchings8ceee662008-04-27 12:55:59 +0100695 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000696 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
697 * for use in sk_buff::truesize
Jon Cooper43a37392012-10-18 15:49:54 +0100698 * @rx_prefix_size: Size of RX prefix before packet data
699 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
700 * (valid only if @rx_prefix_size != 0; always negative)
Ben Hutchings3dced742013-04-27 01:55:18 +0100701 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
702 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
Jon Cooperbd9a2652013-11-18 12:54:41 +0000703 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
704 * (valid only if channel->sync_timestamps_enabled; always negative)
Ben Hutchings78d41892010-12-02 13:47:56 +0000705 * @rx_hash_key: Toeplitz hash key for RSS
Ben Hutchings765c9f42010-06-30 05:06:28 +0000706 * @rx_indir_table: Indirection table for RSS
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000707 * @rx_scatter: Scatter mode enabled for receives
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000708 * @int_error_count: Number of internal errors seen recently
709 * @int_error_expire: Time at which error count will be expired
Ben Hutchingsd8291182012-10-05 23:35:41 +0100710 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
711 * acknowledge but do nothing else.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100712 * @irq_status: Interrupt status buffer
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000713 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000714 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
Ben Hutchingsdd407812012-02-28 23:40:21 +0000715 * @selftest_work: Work item for asynchronous self-test
Ben Hutchings76884832009-11-29 15:10:44 +0000716 * @mtd_list: List of MTDs attached to the NIC
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300717 * @nic_data: Hardware dependent state
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100718 * @mcdi: Management-Controller-to-Driver Interface state
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100719 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
Ben Hutchingse4abce82011-05-16 18:51:24 +0100720 * efx_monitor() and efx_reconfigure_port()
Ben Hutchings8ceee662008-04-27 12:55:59 +0100721 * @port_enabled: Port enabled indicator.
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000722 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
723 * efx_mac_work() with kernel interfaces. Safe to read under any
724 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
725 * be held to modify it.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100726 * @port_initialized: Port initialized?
727 * @net_dev: Operating system network device. Consider holding the rtnl lock
Ben Hutchings8ceee662008-04-27 12:55:59 +0100728 * @stats_buffer: DMA buffer for statistics
Ben Hutchings8ceee662008-04-27 12:55:59 +0100729 * @phy_type: PHY type
Ben Hutchings8ceee662008-04-27 12:55:59 +0100730 * @phy_op: PHY interface
731 * @phy_data: PHY private data (including PHY-specific stats)
Ben Hutchings68e7f452009-04-29 08:05:08 +0000732 * @mdio: PHY MDIO interface
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000733 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100734 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000735 * @link_advertising: Autonegotiation advertising flags
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000736 * @link_state: Current state of the link
Ben Hutchings8ceee662008-04-27 12:55:59 +0100737 * @n_link_state_changes: Number of times the link has changed state
Ben Hutchings964e6132012-11-19 23:08:22 +0000738 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
739 * Protected by @mac_lock.
740 * @multicast_hash: Multicast hash table for Falcon-arch.
741 * Protected by @mac_lock.
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800742 * @wanted_fc: Wanted flow control flags
Steve Hodgsona606f432011-05-23 12:18:45 +0100743 * @fc_disable: When non-zero flow control is disabled. Typically used to
744 * ensure that network back pressure doesn't delay dma queue flushes.
745 * Serialised by the rtnl lock.
Ben Hutchings8be4f3e2009-11-25 16:12:16 +0000746 * @mac_work: Work item for changing MAC promiscuity and multicast hash
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100747 * @loopback_mode: Loopback status
748 * @loopback_modes: Supported loopback mode bitmask
749 * @loopback_selftest: Offline self-test private state
Ben Hutchings6d661ce2012-10-27 00:33:30 +0100750 * @filter_lock: Filter table lock
751 * @filter_state: Architecture-dependent filter table state
752 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
753 * indexed by filter ID
754 * @rps_expire_index: Next index to check for expiry in @rps_flow_id
Alexandre Rames3881d8a2013-06-10 11:03:21 +0100755 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
Ben Hutchings9f2cb712012-02-08 00:11:20 +0000756 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
757 * Decremented when the efx_flush_rx_queue() is called.
758 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
759 * completed (either success or failure). Not used when MCDI is used to
760 * flush receive queues.
761 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
Ben Hutchingscd2d5b52012-02-14 00:48:07 +0000762 * @vf: Array of &struct efx_vf objects.
763 * @vf_count: Number of VFs intended to be enabled.
764 * @vf_init_count: Number of VFs that have been fully initialised.
765 * @vi_scale: log2 number of vnics per VF.
766 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
767 * @vfdi_status: Common VFDI status page to be dmad to VF address space.
768 * @local_addr_list: List of local addresses. Protected by %local_lock.
769 * @local_page_list: List of DMA addressable pages used to broadcast
770 * %local_addr_list. Protected by %local_lock.
771 * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
772 * @peer_work: Work item to broadcast peer addresses to VMs.
Stuart Hodgson7c236c42012-09-03 11:09:36 +0100773 * @ptp_data: PTP state data
Ben Hutchingsab28c122010-12-06 22:53:15 +0000774 * @monitor_work: Hardware monitor workitem
775 * @biu_lock: BIU (bus interface unit) lock
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000776 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
777 * field is used by efx_test_interrupts() to verify that an
778 * interrupt has occurred.
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000779 * @stats_lock: Statistics update lock. Must be held when calling
780 * efx_nic_type::{update,start,stop}_stats.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100781 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000782 * This is stored in the private area of the &struct net_device.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100783 */
784struct efx_nic {
Ben Hutchingsab28c122010-12-06 22:53:15 +0000785 /* The following fields should be written very rarely */
786
Ben Hutchings8ceee662008-04-27 12:55:59 +0100787 char name[IFNAMSIZ];
788 struct pci_dev *pci_dev;
Ben Hutchings66020412013-06-10 18:03:17 +0100789 unsigned int port_num;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100790 const struct efx_nic_type *type;
791 int legacy_irq;
Alexandre Ramesb28405b2013-03-21 16:41:43 +0000792 bool eeh_disabled_legacy_irq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100793 struct workqueue_struct *workqueue;
Ben Hutchings6977dc62008-12-26 13:44:39 -0800794 char workqueue_name[16];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100795 struct work_struct reset_work;
Ben Hutchings086ea352008-05-16 21:17:06 +0100796 resource_size_t membase_phys;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100797 void __iomem *membase;
Ben Hutchingsab28c122010-12-06 22:53:15 +0000798
Ben Hutchings8ceee662008-04-27 12:55:59 +0100799 enum efx_int_mode interrupt_mode;
Ben Hutchingscc180b62011-12-08 19:51:47 +0000800 unsigned int timer_quantum_ns;
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000801 bool irq_rx_adaptive;
802 unsigned int irq_rx_moderation;
Ben Hutchings62776d02010-06-23 11:30:07 +0000803 u32 msg_enable;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100804
Ben Hutchings8ceee662008-04-27 12:55:59 +0100805 enum nic_state state;
Ben Hutchingsa7d529a2011-06-24 20:46:31 +0100806 unsigned long reset_pending;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100807
Ben Hutchings8313aca2010-09-10 06:41:57 +0000808 struct efx_channel *channel[EFX_MAX_CHANNELS];
Ben Hutchingsd8291182012-10-05 23:35:41 +0100809 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
Ben Hutchings7f967c02012-02-13 23:45:02 +0000810 const struct efx_channel_type *
811 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100812
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000813 unsigned rxq_entries;
814 unsigned txq_entries;
Ben Hutchings14bf7182012-05-22 01:27:58 +0100815 unsigned int txq_stop_thresh;
816 unsigned int txq_wake_thresh;
817
Ben Hutchings28e47c42012-02-15 01:58:49 +0000818 unsigned tx_dc_base;
819 unsigned rx_dc_base;
820 unsigned sram_lim_qw;
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000821 unsigned next_buffer_table;
Ben Hutchingsb1057982012-09-19 00:56:47 +0100822
823 unsigned int max_channels;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000824 unsigned n_channels;
825 unsigned n_rx_channels;
Ben Hutchingscd2d5b52012-02-14 00:48:07 +0000826 unsigned rss_spread;
Ben Hutchings97653432011-01-12 18:26:56 +0000827 unsigned tx_channel_offset;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000828 unsigned n_tx_channels;
Andrew Rybchenko2ec03012013-11-16 11:02:27 +0400829 unsigned int rx_ip_align;
Ben Hutchings272baee2013-01-29 23:33:14 +0000830 unsigned int rx_dma_len;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100831 unsigned int rx_buffer_order;
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000832 unsigned int rx_buffer_truesize;
Daniel Pieczko1648a232013-02-13 10:54:41 +0000833 unsigned int rx_page_buf_step;
Daniel Pieczko27689352013-02-13 10:54:41 +0000834 unsigned int rx_bufs_per_page;
Daniel Pieczko1648a232013-02-13 10:54:41 +0000835 unsigned int rx_pages_per_batch;
Jon Cooper43a37392012-10-18 15:49:54 +0100836 unsigned int rx_prefix_size;
837 int rx_packet_hash_offset;
Ben Hutchings3dced742013-04-27 01:55:18 +0100838 int rx_packet_len_offset;
Jon Cooperbd9a2652013-11-18 12:54:41 +0000839 int rx_packet_ts_offset;
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000840 u8 rx_hash_key[40];
Ben Hutchings765c9f42010-06-30 05:06:28 +0000841 u32 rx_indir_table[128];
Ben Hutchings85740cdf2013-01-29 23:33:15 +0000842 bool rx_scatter;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100843
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000844 unsigned int_error_count;
845 unsigned long int_error_expire;
846
Ben Hutchingsd8291182012-10-05 23:35:41 +0100847 bool irq_soft_enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100848 struct efx_buffer irq_status;
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000849 unsigned irq_zero_count;
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000850 unsigned irq_level;
Ben Hutchingsdd407812012-02-28 23:40:21 +0000851 struct delayed_work selftest_work;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100852
Ben Hutchings76884832009-11-29 15:10:44 +0000853#ifdef CONFIG_SFC_MTD
854 struct list_head mtd_list;
855#endif
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100856
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000857 void *nic_data;
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100858 struct efx_mcdi_data *mcdi;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100859
860 struct mutex mac_lock;
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800861 struct work_struct mac_work;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100862 bool port_enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100863
Jon Cooper74cd60a2013-09-16 14:18:51 +0100864 bool mc_bist_for_other_fn;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100865 bool port_initialized;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100866 struct net_device *net_dev;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100867
Ben Hutchings8ceee662008-04-27 12:55:59 +0100868 struct efx_buffer stats_buffer;
Jon Cooperf8f3b5a2013-09-30 17:36:50 +0100869 u64 rx_nodesc_drops_total;
870 u64 rx_nodesc_drops_while_down;
871 bool rx_nodesc_drops_prev_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100872
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000873 unsigned int phy_type;
stephen hemminger6c8c2512011-04-14 05:50:12 +0000874 const struct efx_phy_operations *phy_op;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100875 void *phy_data;
Ben Hutchings68e7f452009-04-29 08:05:08 +0000876 struct mdio_if_info mdio;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000877 unsigned int mdio_bus;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100878 enum efx_phy_mode phy_mode;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100879
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000880 u32 link_advertising;
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000881 struct efx_link_state link_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100882 unsigned int n_link_state_changes;
883
Ben Hutchings964e6132012-11-19 23:08:22 +0000884 bool unicast_filter;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100885 union efx_multicast_hash multicast_hash;
David S. Millerb56269462011-05-17 17:53:22 -0400886 u8 wanted_fc;
Steve Hodgsona606f432011-05-23 12:18:45 +0100887 unsigned fc_disable;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100888
889 atomic_t rx_reset;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100890 enum efx_loopback_mode loopback_mode;
Ben Hutchingse58f69f2009-11-29 15:08:41 +0000891 u64 loopback_modes;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100892
893 void *loopback_selftest;
Ben Hutchings64eebcf2010-09-20 08:43:07 +0000894
Ben Hutchings6d661ce2012-10-27 00:33:30 +0100895 spinlock_t filter_lock;
896 void *filter_state;
897#ifdef CONFIG_RFS_ACCEL
898 u32 *rps_flow_id;
899 unsigned int rps_expire_index;
900#endif
Ben Hutchingsab28c122010-12-06 22:53:15 +0000901
Alexandre Rames3881d8a2013-06-10 11:03:21 +0100902 atomic_t active_queues;
Ben Hutchings9f2cb712012-02-08 00:11:20 +0000903 atomic_t rxq_flush_pending;
904 atomic_t rxq_flush_outstanding;
905 wait_queue_head_t flush_wq;
906
Ben Hutchingscd2d5b52012-02-14 00:48:07 +0000907#ifdef CONFIG_SFC_SRIOV
908 struct efx_channel *vfdi_channel;
909 struct efx_vf *vf;
910 unsigned vf_count;
911 unsigned vf_init_count;
912 unsigned vi_scale;
913 unsigned vf_buftbl_base;
914 struct efx_buffer vfdi_status;
915 struct list_head local_addr_list;
916 struct list_head local_page_list;
917 struct mutex local_lock;
918 struct work_struct peer_work;
919#endif
920
Stuart Hodgson7c236c42012-09-03 11:09:36 +0100921 struct efx_ptp_data *ptp_data;
Stuart Hodgson7c236c42012-09-03 11:09:36 +0100922
Ben Hutchingsab28c122010-12-06 22:53:15 +0000923 /* The following fields may be written more often */
924
925 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
926 spinlock_t biu_lock;
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000927 int last_irq_cpu;
Ben Hutchingsab28c122010-12-06 22:53:15 +0000928 spinlock_t stats_lock;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100929};
930
Ben Hutchings55668612008-05-16 21:16:10 +0100931static inline int efx_dev_registered(struct efx_nic *efx)
932{
933 return efx->net_dev->reg_state == NETREG_REGISTERED;
934}
935
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000936static inline unsigned int efx_port_num(struct efx_nic *efx)
937{
Ben Hutchings66020412013-06-10 18:03:17 +0100938 return efx->port_num;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000939}
940
Ben Hutchings45a3fd52012-11-28 04:38:14 +0000941struct efx_mtd_partition {
942 struct list_head node;
943 struct mtd_info mtd;
944 const char *dev_type_name;
945 const char *type_name;
946 char name[IFNAMSIZ + 20];
947};
948
Ben Hutchings8ceee662008-04-27 12:55:59 +0100949/**
950 * struct efx_nic_type - Efx device type definition
Ben Hutchingsb1057982012-09-19 00:56:47 +0100951 * @mem_map_size: Get memory BAR mapped size
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000952 * @probe: Probe the controller
953 * @remove: Free resources allocated by probe()
954 * @init: Initialise the controller
Ben Hutchings28e47c42012-02-15 01:58:49 +0000955 * @dimension_resources: Dimension controller resources (buffer table,
956 * and VIs once the available interrupt resources are clear)
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000957 * @fini: Shut down the controller
958 * @monitor: Periodic function for polling link state and hardware monitor
Ben Hutchings0e2a9c72011-06-24 20:50:07 +0100959 * @map_reset_reason: Map ethtool reset reason to a reset method
960 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000961 * @reset: Reset the controller hardware and possibly the PHY. This will
962 * be called while the controller is uninitialised.
963 * @probe_port: Probe the MAC and PHY
964 * @remove_port: Free resources allocated by probe_port()
Ben Hutchings40641ed2010-12-02 13:47:45 +0000965 * @handle_global_event: Handle a "global" event (may be %NULL)
Ben Hutchingse42c3d82013-05-27 16:52:54 +0100966 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000967 * @prepare_flush: Prepare the hardware for flushing the DMA queues
Ben Hutchingse42c3d82013-05-27 16:52:54 +0100968 * (for Falcon architecture)
969 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
970 * architecture)
Ben Hutchingscd0ecc92012-12-14 21:52:56 +0000971 * @describe_stats: Describe statistics for ethtool
972 * @update_stats: Update statistics not provided by event handling.
973 * Either argument may be %NULL.
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000974 * @start_stats: Start the regular fetching of statistics
Jon Cooperf8f3b5a2013-09-30 17:36:50 +0100975 * @pull_stats: Pull stats from the NIC and wait until they arrive.
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000976 * @stop_stats: Stop the regular fetching of statistics
Ben Hutchings06629f02009-11-29 03:43:43 +0000977 * @set_id_led: Set state of identifying LED or revert to automatic function
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000978 * @push_irq_moderation: Apply interrupt moderation value
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000979 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
Ben Hutchings9dd3a132012-09-13 01:11:25 +0100980 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
Ben Hutchings30b81cd2011-09-13 19:47:48 +0100981 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
982 * to the hardware. Serialised by the mac_lock.
Ben Hutchings710b2082011-09-03 00:15:00 +0100983 * @check_mac_fault: Check MAC fault state. True if fault present.
Ben Hutchings89c758f2009-11-29 03:43:07 +0000984 * @get_wol: Get WoL configuration from driver state
985 * @set_wol: Push WoL configuration to the NIC
986 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
Ben Hutchings86094f72013-08-21 19:51:04 +0100987 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +0100988 * expected to reset the NIC.
Ben Hutchings0aa3fba2009-11-29 03:43:33 +0000989 * @test_nvram: Test validity of NVRAM contents
Ben Hutchingsf3ad5002012-09-18 02:33:56 +0100990 * @mcdi_request: Send an MCDI request with the given header and SDU.
991 * The SDU length may be any value from 0 up to the protocol-
992 * defined maximum, but its buffer will be padded to a multiple
993 * of 4 bytes.
994 * @mcdi_poll_response: Test whether an MCDI response is available.
995 * @mcdi_read_response: Read the MCDI response PDU. The offset will
996 * be a multiple of 4. The length may not be, but the buffer
997 * will be padded so it is safe to round up.
998 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
999 * return an appropriate error code for aborting any current
1000 * request; otherwise return 0.
Ben Hutchings86094f72013-08-21 19:51:04 +01001001 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1002 * be separately enabled after this.
1003 * @irq_test_generate: Generate a test IRQ
1004 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1005 * queue must be separately disabled before this.
1006 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1007 * a pointer to the &struct efx_msi_context for the channel.
1008 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1009 * is a pointer to the &struct efx_nic.
1010 * @tx_probe: Allocate resources for TX queue
1011 * @tx_init: Initialise TX queue on the NIC
1012 * @tx_remove: Free resources for TX queue
1013 * @tx_write: Write TX descriptors and doorbell
1014 * @rx_push_indir_table: Write RSS indirection table to the NIC
1015 * @rx_probe: Allocate resources for RX queue
1016 * @rx_init: Initialise RX queue on the NIC
1017 * @rx_remove: Free resources for RX queue
1018 * @rx_write: Write RX descriptors and doorbell
1019 * @rx_defer_refill: Generate a refill reminder event
1020 * @ev_probe: Allocate resources for event queue
1021 * @ev_init: Initialise event queue on the NIC
1022 * @ev_fini: Deinitialise event queue on the NIC
1023 * @ev_remove: Free resources for event queue
1024 * @ev_process: Process events for a queue, up to the given NAPI quota
1025 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1026 * @ev_test_generate: Generate a test event
Ben Hutchingsadd72472012-11-08 01:46:53 +00001027 * @filter_table_probe: Probe filter capabilities and set up filter software state
1028 * @filter_table_restore: Restore filters removed from hardware
1029 * @filter_table_remove: Remove filters from hardware and tear down software state
1030 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1031 * @filter_insert: add or replace a filter
1032 * @filter_remove_safe: remove a filter by ID, carefully
1033 * @filter_get_safe: retrieve a filter by ID, carefully
1034 * @filter_clear_rx: remove RX filters by priority
1035 * @filter_count_rx_used: Get the number of filters in use at a given priority
1036 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1037 * @filter_get_rx_ids: Get list of RX filters at a given priority
1038 * @filter_rfs_insert: Add or replace a filter for RFS. This must be
1039 * atomic. The hardware change may be asynchronous but should
1040 * not be delayed for long. It may fail if this can't be done
1041 * atomically.
1042 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1043 * This must check whether the specified table entry is used by RFS
1044 * and that rps_may_expire_flow() returns true for it.
Ben Hutchings45a3fd52012-11-28 04:38:14 +00001045 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1046 * using efx_mtd_add()
1047 * @mtd_rename: Set an MTD partition name using the net device name
1048 * @mtd_read: Read from an MTD partition
1049 * @mtd_erase: Erase part of an MTD partition
1050 * @mtd_write: Write to an MTD partition
1051 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1052 * also notifies the driver that a writer has finished using this
1053 * partition.
Daniel Pieczko9ec06592013-11-21 17:11:25 +00001054 * @ptp_write_host_time: Send host time to MC as part of sync protocol
Jon Cooperbd9a2652013-11-18 12:54:41 +00001055 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1056 * timestamping, possibly only temporarily for the purposes of a reset.
Daniel Pieczko9ec06592013-11-21 17:11:25 +00001057 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1058 * and tx_type will already have been validated but this operation
1059 * must validate and update rx_filter.
Ben Hutchingsdaeda632009-11-28 05:36:04 +00001060 * @revision: Hardware architecture revision
Ben Hutchings8ceee662008-04-27 12:55:59 +01001061 * @txd_ptr_tbl_base: TX descriptor ring base address
1062 * @rxd_ptr_tbl_base: RX descriptor ring base address
1063 * @buf_tbl_base: Buffer table base address
1064 * @evq_ptr_tbl_base: Event queue pointer table base address
1065 * @evq_rptr_tbl_base: Event queue read-pointer table base address
Ben Hutchings8ceee662008-04-27 12:55:59 +01001066 * @max_dma_mask: Maximum possible DMA mask
Jon Cooper43a37392012-10-18 15:49:54 +01001067 * @rx_prefix_size: Size of RX prefix before packet data
1068 * @rx_hash_offset: Offset of RX flow hash within prefix
Jon Cooperbd9a2652013-11-18 12:54:41 +00001069 * @rx_ts_offset: Offset of timestamp within prefix
Ben Hutchings85740cdf2013-01-29 23:33:15 +00001070 * @rx_buffer_padding: Size of padding at end of RX packet
Jon Coopere8c68c02013-03-08 10:18:28 +00001071 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1072 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
Ben Hutchings8ceee662008-04-27 12:55:59 +01001073 * @max_interrupt_mode: Highest capability interrupt mode supported
1074 * from &enum efx_init_mode.
Ben Hutchingscc180b62011-12-08 19:51:47 +00001075 * @timer_period_max: Maximum period of interrupt timer (in ticks)
Ben Hutchingsc383b532009-11-29 15:11:02 +00001076 * @offload_features: net_device feature flags for protocol offload
1077 * features implemented in hardware
Ben Hutchingsdf2cd8a2012-09-19 00:56:18 +01001078 * @mcdi_max_ver: Maximum MCDI version supported
Daniel Pieczko9ec06592013-11-21 17:11:25 +00001079 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
Ben Hutchings8ceee662008-04-27 12:55:59 +01001080 */
1081struct efx_nic_type {
Ben Hutchingsb1057982012-09-19 00:56:47 +01001082 unsigned int (*mem_map_size)(struct efx_nic *efx);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +00001083 int (*probe)(struct efx_nic *efx);
1084 void (*remove)(struct efx_nic *efx);
1085 int (*init)(struct efx_nic *efx);
Ben Hutchingsc15eed22013-08-29 00:45:48 +01001086 int (*dimension_resources)(struct efx_nic *efx);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +00001087 void (*fini)(struct efx_nic *efx);
1088 void (*monitor)(struct efx_nic *efx);
Ben Hutchings0e2a9c72011-06-24 20:50:07 +01001089 enum reset_type (*map_reset_reason)(enum reset_type reason);
1090 int (*map_reset_flags)(u32 *flags);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +00001091 int (*reset)(struct efx_nic *efx, enum reset_type method);
1092 int (*probe_port)(struct efx_nic *efx);
1093 void (*remove_port)(struct efx_nic *efx);
Ben Hutchings40641ed2010-12-02 13:47:45 +00001094 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
Ben Hutchingse42c3d82013-05-27 16:52:54 +01001095 int (*fini_dmaq)(struct efx_nic *efx);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +00001096 void (*prepare_flush)(struct efx_nic *efx);
Ben Hutchingsd5e8cc62012-09-06 16:52:31 +01001097 void (*finish_flush)(struct efx_nic *efx);
Ben Hutchingscd0ecc92012-12-14 21:52:56 +00001098 size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1099 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1100 struct rtnl_link_stats64 *core_stats);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +00001101 void (*start_stats)(struct efx_nic *efx);
Jon Cooperf8f3b5a2013-09-30 17:36:50 +01001102 void (*pull_stats)(struct efx_nic *efx);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +00001103 void (*stop_stats)(struct efx_nic *efx);
Ben Hutchings06629f02009-11-29 03:43:43 +00001104 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +00001105 void (*push_irq_moderation)(struct efx_channel *channel);
Ben Hutchingsd3245b22009-11-29 03:42:41 +00001106 int (*reconfigure_port)(struct efx_nic *efx);
Ben Hutchings9dd3a132012-09-13 01:11:25 +01001107 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
Ben Hutchings710b2082011-09-03 00:15:00 +01001108 int (*reconfigure_mac)(struct efx_nic *efx);
1109 bool (*check_mac_fault)(struct efx_nic *efx);
Ben Hutchings89c758f2009-11-29 03:43:07 +00001110 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1111 int (*set_wol)(struct efx_nic *efx, u32 type);
1112 void (*resume_wol)(struct efx_nic *efx);
Ben Hutchingsd4f2cec2012-07-04 03:58:33 +01001113 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
Ben Hutchings0aa3fba2009-11-29 03:43:33 +00001114 int (*test_nvram)(struct efx_nic *efx);
Ben Hutchingsf3ad5002012-09-18 02:33:56 +01001115 void (*mcdi_request)(struct efx_nic *efx,
1116 const efx_dword_t *hdr, size_t hdr_len,
1117 const efx_dword_t *sdu, size_t sdu_len);
1118 bool (*mcdi_poll_response)(struct efx_nic *efx);
1119 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1120 size_t pdu_offset, size_t pdu_len);
1121 int (*mcdi_poll_reboot)(struct efx_nic *efx);
Ben Hutchings86094f72013-08-21 19:51:04 +01001122 void (*irq_enable_master)(struct efx_nic *efx);
1123 void (*irq_test_generate)(struct efx_nic *efx);
1124 void (*irq_disable_non_ev)(struct efx_nic *efx);
1125 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1126 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1127 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1128 void (*tx_init)(struct efx_tx_queue *tx_queue);
1129 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1130 void (*tx_write)(struct efx_tx_queue *tx_queue);
1131 void (*rx_push_indir_table)(struct efx_nic *efx);
1132 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1133 void (*rx_init)(struct efx_rx_queue *rx_queue);
1134 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1135 void (*rx_write)(struct efx_rx_queue *rx_queue);
1136 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1137 int (*ev_probe)(struct efx_channel *channel);
Jon Cooper261e4d92013-04-15 18:51:54 +01001138 int (*ev_init)(struct efx_channel *channel);
Ben Hutchings86094f72013-08-21 19:51:04 +01001139 void (*ev_fini)(struct efx_channel *channel);
1140 void (*ev_remove)(struct efx_channel *channel);
1141 int (*ev_process)(struct efx_channel *channel, int quota);
1142 void (*ev_read_ack)(struct efx_channel *channel);
1143 void (*ev_test_generate)(struct efx_channel *channel);
Ben Hutchingsadd72472012-11-08 01:46:53 +00001144 int (*filter_table_probe)(struct efx_nic *efx);
1145 void (*filter_table_restore)(struct efx_nic *efx);
1146 void (*filter_table_remove)(struct efx_nic *efx);
1147 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1148 s32 (*filter_insert)(struct efx_nic *efx,
1149 struct efx_filter_spec *spec, bool replace);
1150 int (*filter_remove_safe)(struct efx_nic *efx,
1151 enum efx_filter_priority priority,
1152 u32 filter_id);
1153 int (*filter_get_safe)(struct efx_nic *efx,
1154 enum efx_filter_priority priority,
1155 u32 filter_id, struct efx_filter_spec *);
1156 void (*filter_clear_rx)(struct efx_nic *efx,
1157 enum efx_filter_priority priority);
1158 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1159 enum efx_filter_priority priority);
1160 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1161 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1162 enum efx_filter_priority priority,
1163 u32 *buf, u32 size);
1164#ifdef CONFIG_RFS_ACCEL
1165 s32 (*filter_rfs_insert)(struct efx_nic *efx,
1166 struct efx_filter_spec *spec);
1167 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1168 unsigned int index);
1169#endif
Ben Hutchings45a3fd52012-11-28 04:38:14 +00001170#ifdef CONFIG_SFC_MTD
1171 int (*mtd_probe)(struct efx_nic *efx);
1172 void (*mtd_rename)(struct efx_mtd_partition *part);
1173 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1174 size_t *retlen, u8 *buffer);
1175 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1176 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1177 size_t *retlen, const u8 *buffer);
1178 int (*mtd_sync)(struct mtd_info *mtd);
1179#endif
Laurence Evans977a5d52013-03-07 11:46:58 +00001180 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
Jon Cooperbd9a2652013-11-18 12:54:41 +00001181 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
Daniel Pieczko9ec06592013-11-21 17:11:25 +00001182 int (*ptp_set_ts_config)(struct efx_nic *efx,
1183 struct hwtstamp_config *init);
Steve Hodgsonb895d732009-11-28 05:35:00 +00001184
Ben Hutchingsdaeda632009-11-28 05:36:04 +00001185 int revision;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001186 unsigned int txd_ptr_tbl_base;
1187 unsigned int rxd_ptr_tbl_base;
1188 unsigned int buf_tbl_base;
1189 unsigned int evq_ptr_tbl_base;
1190 unsigned int evq_rptr_tbl_base;
Ben Hutchings9bbd7d92008-05-16 21:18:48 +01001191 u64 max_dma_mask;
Jon Cooper43a37392012-10-18 15:49:54 +01001192 unsigned int rx_prefix_size;
1193 unsigned int rx_hash_offset;
Jon Cooperbd9a2652013-11-18 12:54:41 +00001194 unsigned int rx_ts_offset;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001195 unsigned int rx_buffer_padding;
Ben Hutchings85740cdf2013-01-29 23:33:15 +00001196 bool can_rx_scatter;
Jon Coopere8c68c02013-03-08 10:18:28 +00001197 bool always_rx_scatter;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001198 unsigned int max_interrupt_mode;
Ben Hutchingscc180b62011-12-08 19:51:47 +00001199 unsigned int timer_period_max;
Michał Mirosławc8f44af2011-11-15 15:29:55 +00001200 netdev_features_t offload_features;
Ben Hutchingsdf2cd8a2012-09-19 00:56:18 +01001201 int mcdi_max_ver;
Ben Hutchingsadd72472012-11-08 01:46:53 +00001202 unsigned int max_rx_ip_filters;
Daniel Pieczko9ec06592013-11-21 17:11:25 +00001203 u32 hwtstamp_filters;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001204};
1205
1206/**************************************************************************
1207 *
1208 * Prototypes and inline functions
1209 *
1210 *************************************************************************/
1211
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +00001212static inline struct efx_channel *
1213efx_get_channel(struct efx_nic *efx, unsigned index)
1214{
1215 EFX_BUG_ON_PARANOID(index >= efx->n_channels);
Ben Hutchings8313aca2010-09-10 06:41:57 +00001216 return efx->channel[index];
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +00001217}
1218
Ben Hutchings8ceee662008-04-27 12:55:59 +01001219/* Iterate over all used channels */
1220#define efx_for_each_channel(_channel, _efx) \
Ben Hutchings8313aca2010-09-10 06:41:57 +00001221 for (_channel = (_efx)->channel[0]; \
1222 _channel; \
1223 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1224 (_efx)->channel[_channel->channel + 1] : NULL)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001225
Ben Hutchings7f967c02012-02-13 23:45:02 +00001226/* Iterate over all used channels in reverse */
1227#define efx_for_each_channel_rev(_channel, _efx) \
1228 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1229 _channel; \
1230 _channel = _channel->channel ? \
1231 (_efx)->channel[_channel->channel - 1] : NULL)
1232
Ben Hutchings97653432011-01-12 18:26:56 +00001233static inline struct efx_tx_queue *
1234efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1235{
1236 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
1237 type >= EFX_TXQ_TYPES);
1238 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1239}
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +00001240
Ben Hutchings525da902011-02-07 23:04:38 +00001241static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1242{
1243 return channel->channel - channel->efx->tx_channel_offset <
1244 channel->efx->n_tx_channels;
1245}
1246
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +00001247static inline struct efx_tx_queue *
1248efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1249{
Ben Hutchings525da902011-02-07 23:04:38 +00001250 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
1251 type >= EFX_TXQ_TYPES);
1252 return &channel->tx_queue[type];
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +00001253}
Ben Hutchings8ceee662008-04-27 12:55:59 +01001254
Ben Hutchings94b274b2011-01-10 21:18:20 +00001255static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1256{
1257 return !(tx_queue->efx->net_dev->num_tc < 2 &&
1258 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1259}
1260
Ben Hutchings8ceee662008-04-27 12:55:59 +01001261/* Iterate over all TX queues belonging to a channel */
1262#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
Ben Hutchings525da902011-02-07 23:04:38 +00001263 if (!efx_channel_has_tx_queues(_channel)) \
1264 ; \
1265 else \
1266 for (_tx_queue = (_channel)->tx_queue; \
Ben Hutchings94b274b2011-01-10 21:18:20 +00001267 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1268 efx_tx_queue_used(_tx_queue); \
Ben Hutchings525da902011-02-07 23:04:38 +00001269 _tx_queue++)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001270
Ben Hutchings94b274b2011-01-10 21:18:20 +00001271/* Iterate over all possible TX queues belonging to a channel */
1272#define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
Ben Hutchings73e00262012-02-23 00:45:50 +00001273 if (!efx_channel_has_tx_queues(_channel)) \
1274 ; \
1275 else \
1276 for (_tx_queue = (_channel)->tx_queue; \
1277 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1278 _tx_queue++)
Ben Hutchings94b274b2011-01-10 21:18:20 +00001279
Ben Hutchings525da902011-02-07 23:04:38 +00001280static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1281{
Stuart Hodgson79d68b32012-07-16 17:08:33 +01001282 return channel->rx_queue.core_index >= 0;
Ben Hutchings525da902011-02-07 23:04:38 +00001283}
1284
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +00001285static inline struct efx_rx_queue *
1286efx_channel_get_rx_queue(struct efx_channel *channel)
1287{
Ben Hutchings525da902011-02-07 23:04:38 +00001288 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
1289 return &channel->rx_queue;
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +00001290}
1291
Ben Hutchings8ceee662008-04-27 12:55:59 +01001292/* Iterate over all RX queues belonging to a channel */
1293#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
Ben Hutchings525da902011-02-07 23:04:38 +00001294 if (!efx_channel_has_rx_queue(_channel)) \
1295 ; \
1296 else \
1297 for (_rx_queue = &(_channel)->rx_queue; \
1298 _rx_queue; \
1299 _rx_queue = NULL)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001300
Ben Hutchingsba1e8a32010-09-10 06:41:36 +00001301static inline struct efx_channel *
1302efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1303{
Ben Hutchings8313aca2010-09-10 06:41:57 +00001304 return container_of(rx_queue, struct efx_channel, rx_queue);
Ben Hutchingsba1e8a32010-09-10 06:41:36 +00001305}
1306
1307static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1308{
Ben Hutchings8313aca2010-09-10 06:41:57 +00001309 return efx_rx_queue_channel(rx_queue)->channel;
Ben Hutchingsba1e8a32010-09-10 06:41:36 +00001310}
1311
Ben Hutchings8ceee662008-04-27 12:55:59 +01001312/* Returns a pointer to the specified receive buffer in the RX
1313 * descriptor queue.
1314 */
1315static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1316 unsigned int index)
1317{
Eric Dumazet807540b2010-09-23 05:40:09 +00001318 return &rx_queue->buffer[index];
Ben Hutchings8ceee662008-04-27 12:55:59 +01001319}
1320
Ben Hutchings8ceee662008-04-27 12:55:59 +01001321
1322/**
1323 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1324 *
1325 * This calculates the maximum frame length that will be used for a
1326 * given MTU. The frame length will be equal to the MTU plus a
1327 * constant amount of header space and padding. This is the quantity
1328 * that the net driver will program into the MAC as the maximum frame
1329 * length.
1330 *
Ben Hutchings754c6532010-02-03 09:31:57 +00001331 * The 10G MAC requires 8-byte alignment on the frame
Ben Hutchings8ceee662008-04-27 12:55:59 +01001332 * length, so we round up to the nearest 8.
Ben Hutchingscc117632009-08-26 08:17:59 +00001333 *
1334 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1335 * XGMII cycle). If the frame length reaches the maximum value in the
1336 * same cycle, the XMAC can miss the IPG altogether. We work around
1337 * this by adding a further 16 bytes.
Ben Hutchings8ceee662008-04-27 12:55:59 +01001338 */
1339#define EFX_MAX_FRAME_LEN(mtu) \
Ben Hutchingscc117632009-08-26 08:17:59 +00001340 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001341
Stuart Hodgson7c236c42012-09-03 11:09:36 +01001342static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1343{
1344 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1345}
1346static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1347{
1348 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1349}
Ben Hutchings8ceee662008-04-27 12:55:59 +01001350
1351#endif /* EFX_NET_DRIVER_H */