blob: fc26cb4c9ba3fa256257752fd66fc75a25e1bbee [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnesc1c7af62009-09-10 15:28:03 -070027#include <linux/module.h>
28#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080030#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070032#include <linux/vgaarb.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080033#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070037#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100038#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080039
40#include "drm_crtc_helper.h"
41
Zhenyu Wang32f9d652009-07-24 01:00:32 +080042#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
Jesse Barnes79e53942008-11-07 14:24:08 -080044bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080045static void intel_update_watermarks(struct drm_device *dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +020046static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010047static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080048
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080071typedef struct intel_limit intel_limit_t;
72struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080073 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080075 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
Jesse Barnes79e53942008-11-07 14:24:08 -080078
Jesse Barnes2377b742010-07-07 14:06:43 -070079/* FDI */
80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
Ma Lingd4906092009-03-18 20:13:27 +080082static bool
83intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080088
Keith Packarda4fc5ed2009-04-07 16:16:42 -070089static bool
90intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080092static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -050093intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -070095
Chris Wilson021357a2010-09-07 20:54:59 +010096static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
Chris Wilson8b99e682010-10-13 09:59:17 +010099 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100104}
105
Keith Packarde4b36692009-06-05 19:22:17 -0700106static const intel_limit_t intel_limits_i8xx_dvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800117 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700118};
119
120static const intel_limit_t intel_limits_i8xx_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800131 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700132};
Eric Anholt273e27c2011-03-30 13:01:10 -0700133
Keith Packarde4b36692009-06-05 19:22:17 -0700134static const intel_limit_t intel_limits_i9xx_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800145 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700146};
147
148static const intel_limit_t intel_limits_i9xx_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800159 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700160};
161
Eric Anholt273e27c2011-03-30 13:01:10 -0700162
Keith Packarde4b36692009-06-05 19:22:17 -0700163static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800175 },
Ma Lingd4906092009-03-18 20:13:27 +0800176 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700177};
178
179static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800190 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700191};
192
193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800204 },
Ma Lingd4906092009-03-18 20:13:27 +0800205 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700206};
207
208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800219 },
Ma Lingd4906092009-03-18 20:13:27 +0800220 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700221};
222
223static const intel_limit_t intel_limits_g4x_display_port = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700234 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700235};
236
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500237static const intel_limit_t intel_limits_pineview_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800250 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700251};
252
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500253static const intel_limit_t intel_limits_pineview_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800264 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700265};
266
Eric Anholt273e27c2011-03-30 13:01:10 -0700267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800272static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800283 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700284};
285
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800286static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800297 .find_pll = intel_g4x_find_best_PLL,
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800311 .find_pll = intel_g4x_find_best_PLL,
312};
313
Eric Anholt273e27c2011-03-30 13:01:10 -0700314/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800326 .find_pll = intel_g4x_find_best_PLL,
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800340 .find_pll = intel_g4x_find_best_PLL,
341};
342
343static const intel_limit_t intel_limits_ironlake_display_port = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
Zhao Yakui45476682009-12-31 16:06:04 +0800354 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800355};
356
Chris Wilson1b894b52010-12-14 20:04:54 +0000357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800359{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800362 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000368 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000373 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800381 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800382 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800383
384 return limit;
385}
386
Ma Ling044c7c42009-03-18 20:13:23 +0800387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700397 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800398 else
399 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700400 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700403 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700405 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700407 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800408 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700409 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800410
411 return limit;
412}
413
Chris Wilson1b894b52010-12-14 20:04:54 +0000414static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800415{
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
Eric Anholtbad720f2009-10-22 16:11:14 -0700419 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000420 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800421 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800422 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500423 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500425 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800426 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500427 limit = &intel_limits_pineview_sdvo;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700435 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800436 else
Keith Packarde4b36692009-06-05 19:22:17 -0700437 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800438 }
439 return limit;
440}
441
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500442/* m1 is reserved as 0 in Pineview, n is a ring counter */
443static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800444{
Shaohua Li21778322009-02-23 15:19:16 +0800445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449}
450
451static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800455 return;
456 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
Jesse Barnes79e53942008-11-07 14:24:08 -0800463/**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100466bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800467{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800471
Chris Wilson4ef69c72010-09-09 15:14:28 +0100472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800477}
478
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800479#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800480/**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
Chris Wilson1b894b52010-12-14 20:04:54 +0000485static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800488{
Jesse Barnes79e53942008-11-07 14:24:08 -0800489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512}
513
Ma Lingd4906092009-03-18 20:13:27 +0800514static bool
515intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
Jesse Barnes79e53942008-11-07 14:24:08 -0800518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800522 int err = target;
523
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800525 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
Zhao Yakui42158662009-11-20 11:24:18 +0800546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800557 int this_err;
558
Shaohua Li21778322009-02-23 15:19:16 +0800559 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575}
576
Ma Lingd4906092009-03-18 20:13:27 +0800577static bool
578intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580{
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800591 int lvds_reg;
592
Eric Anholtc619eed2010-01-28 16:45:52 -0800593 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200611 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200613 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
Shaohua Li21778322009-02-23 15:19:16 +0800622 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800625 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000626
627 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800638 return found;
639}
Ma Lingd4906092009-03-18 20:13:27 +0800640
Zhenyu Wang2c072452009-06-05 15:38:42 +0800641static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500642intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800644{
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800647
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664}
665
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700666/* DisplayPort has only two frequencies, 162MHz and 270MHz */
667static bool
668intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670{
Chris Wilson5eddb702010-09-11 13:48:45 +0100671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700691}
692
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700693/**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800702{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700703 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800704 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700705
Chris Wilson300387c2010-09-05 20:25:43 +0100706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700722 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700726 DRM_DEBUG_KMS("vblank wait timed out\n");
727}
728
Keith Packardab7ad7f2010-10-03 00:33:06 -0700729/*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100744 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700745 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100746void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700749
Keith Packardab7ad7f2010-10-03 00:33:06 -0700750 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +0100751 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700752
Keith Packardab7ad7f2010-10-03 00:33:06 -0700753 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
Keith Packardab7ad7f2010-10-03 00:33:06 -0700756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
Chris Wilson58e10eb2010-10-03 10:56:11 +0100759 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -0700760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
Chris Wilson58e10eb2010-10-03 10:56:11 +0100764 last_line = I915_READ(reg) & DSL_LINEMASK;
Keith Packardab7ad7f2010-10-03 00:33:06 -0700765 mdelay(5);
Chris Wilson58e10eb2010-10-03 10:56:11 +0100766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -0700767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800771}
772
Jesse Barnesb24e7172011-01-04 15:09:30 -0800773static const char *state_string(bool enabled)
774{
775 return enabled ? "on" : "off";
776}
777
778/* Only for pre-ILK configs */
779static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781{
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792}
793#define assert_pll_enabled(d, p) assert_pll(d, p, true)
794#define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
Jesse Barnes040484a2011-01-03 12:14:26 -0800796/* For ILK+ */
797static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799{
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810}
811#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816{
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827}
828#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833{
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844}
845#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850{
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861}
862
863static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872}
873
Jesse Barnesea0760c2011-01-04 15:09:32 -0800874static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876{
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800900 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -0800901}
902
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800903static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800905{
906 int reg;
907 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800908 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -0800909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800915 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800916}
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800917#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800919
920static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922{
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800930 plane_name(plane));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800931}
932
933static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935{
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
Jesse Barnes19ec1352011-02-02 12:28:02 -0800940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
Jesse Barnesb24e7172011-01-04 15:09:30 -0800944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800953 }
954}
955
Jesse Barnes92f25842011-01-04 15:09:34 -0800956static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957{
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965}
966
967static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969{
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -0800980}
981
Keith Packardf0575e92011-07-25 22:12:43 -0700982static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
983 int reg, u32 port_sel, u32 val)
984{
985 if ((val & DP_PORT_EN) == 0)
986 return false;
987
988 if (HAS_PCH_CPT(dev_priv->dev)) {
989 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
990 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
991 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
992 return false;
993 } else {
994 if ((val & DP_PIPE_MASK) != (pipe << 30))
995 return false;
996 }
997 return true;
998}
999
Jesse Barnes291906f2011-02-02 12:28:03 -08001000static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001001 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001002{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001003 u32 val = I915_READ(reg);
Keith Packardf0575e92011-07-25 22:12:43 -07001004 WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001005 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001006 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001007}
1008
1009static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, int reg)
1011{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001012 u32 val = I915_READ(reg);
1013 WARN(HDMI_PIPE_ENABLED(val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001014 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001015 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001016}
1017
1018static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe)
1020{
1021 int reg;
1022 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001023
Keith Packardf0575e92011-07-25 22:12:43 -07001024 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1025 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1026 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001027
1028 reg = PCH_ADPA;
1029 val = I915_READ(reg);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001030 WARN(ADPA_PIPE_ENABLED(val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001031 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001032 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001033
1034 reg = PCH_LVDS;
1035 val = I915_READ(reg);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001036 WARN(LVDS_PIPE_ENABLED(val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001037 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001038 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001039
1040 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1041 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1042 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1043}
1044
Jesse Barnesb24e7172011-01-04 15:09:30 -08001045/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001046 * intel_enable_pll - enable a PLL
1047 * @dev_priv: i915 private structure
1048 * @pipe: pipe PLL to enable
1049 *
1050 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1051 * make sure the PLL reg is writable first though, since the panel write
1052 * protect mechanism may be enabled.
1053 *
1054 * Note! This is for pre-ILK only.
1055 */
1056static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1057{
1058 int reg;
1059 u32 val;
1060
1061 /* No really, not for ILK+ */
1062 BUG_ON(dev_priv->info->gen >= 5);
1063
1064 /* PLL is protected by panel, make sure we can write it */
1065 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1066 assert_panel_unlocked(dev_priv, pipe);
1067
1068 reg = DPLL(pipe);
1069 val = I915_READ(reg);
1070 val |= DPLL_VCO_ENABLE;
1071
1072 /* We do this three times for luck */
1073 I915_WRITE(reg, val);
1074 POSTING_READ(reg);
1075 udelay(150); /* wait for warmup */
1076 I915_WRITE(reg, val);
1077 POSTING_READ(reg);
1078 udelay(150); /* wait for warmup */
1079 I915_WRITE(reg, val);
1080 POSTING_READ(reg);
1081 udelay(150); /* wait for warmup */
1082}
1083
1084/**
1085 * intel_disable_pll - disable a PLL
1086 * @dev_priv: i915 private structure
1087 * @pipe: pipe PLL to disable
1088 *
1089 * Disable the PLL for @pipe, making sure the pipe is off first.
1090 *
1091 * Note! This is for pre-ILK only.
1092 */
1093static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1094{
1095 int reg;
1096 u32 val;
1097
1098 /* Don't disable pipe A or pipe A PLLs if needed */
1099 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1100 return;
1101
1102 /* Make sure the pipe isn't still relying on us */
1103 assert_pipe_disabled(dev_priv, pipe);
1104
1105 reg = DPLL(pipe);
1106 val = I915_READ(reg);
1107 val &= ~DPLL_VCO_ENABLE;
1108 I915_WRITE(reg, val);
1109 POSTING_READ(reg);
1110}
1111
1112/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001113 * intel_enable_pch_pll - enable PCH PLL
1114 * @dev_priv: i915 private structure
1115 * @pipe: pipe PLL to enable
1116 *
1117 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1118 * drives the transcoder clock.
1119 */
1120static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1121 enum pipe pipe)
1122{
1123 int reg;
1124 u32 val;
1125
1126 /* PCH only available on ILK+ */
1127 BUG_ON(dev_priv->info->gen < 5);
1128
1129 /* PCH refclock must be enabled first */
1130 assert_pch_refclk_enabled(dev_priv);
1131
1132 reg = PCH_DPLL(pipe);
1133 val = I915_READ(reg);
1134 val |= DPLL_VCO_ENABLE;
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(200);
1138}
1139
1140static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1141 enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145
1146 /* PCH only available on ILK+ */
1147 BUG_ON(dev_priv->info->gen < 5);
1148
1149 /* Make sure transcoder isn't still depending on us */
1150 assert_transcoder_disabled(dev_priv, pipe);
1151
1152 reg = PCH_DPLL(pipe);
1153 val = I915_READ(reg);
1154 val &= ~DPLL_VCO_ENABLE;
1155 I915_WRITE(reg, val);
1156 POSTING_READ(reg);
1157 udelay(200);
1158}
1159
Jesse Barnes040484a2011-01-03 12:14:26 -08001160static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162{
1163 int reg;
1164 u32 val;
1165
1166 /* PCH only available on ILK+ */
1167 BUG_ON(dev_priv->info->gen < 5);
1168
1169 /* Make sure PCH DPLL is enabled */
1170 assert_pch_pll_enabled(dev_priv, pipe);
1171
1172 /* FDI must be feeding us bits for PCH ports */
1173 assert_fdi_tx_enabled(dev_priv, pipe);
1174 assert_fdi_rx_enabled(dev_priv, pipe);
1175
1176 reg = TRANSCONF(pipe);
1177 val = I915_READ(reg);
1178 /*
1179 * make the BPC in transcoder be consistent with
1180 * that in pipeconf reg.
1181 */
1182 val &= ~PIPE_BPC_MASK;
1183 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1184 I915_WRITE(reg, val | TRANS_ENABLE);
1185 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1186 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1187}
1188
1189static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191{
1192 int reg;
1193 u32 val;
1194
1195 /* FDI relies on the transcoder */
1196 assert_fdi_tx_disabled(dev_priv, pipe);
1197 assert_fdi_rx_disabled(dev_priv, pipe);
1198
Jesse Barnes291906f2011-02-02 12:28:03 -08001199 /* Ports must be off as well */
1200 assert_pch_ports_disabled(dev_priv, pipe);
1201
Jesse Barnes040484a2011-01-03 12:14:26 -08001202 reg = TRANSCONF(pipe);
1203 val = I915_READ(reg);
1204 val &= ~TRANS_ENABLE;
1205 I915_WRITE(reg, val);
1206 /* wait for PCH transcoder off, transcoder state */
1207 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1208 DRM_ERROR("failed to disable transcoder\n");
1209}
1210
Jesse Barnes92f25842011-01-04 15:09:34 -08001211/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001212 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001213 * @dev_priv: i915 private structure
1214 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001215 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001216 *
1217 * Enable @pipe, making sure that various hardware specific requirements
1218 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1219 *
1220 * @pipe should be %PIPE_A or %PIPE_B.
1221 *
1222 * Will wait until the pipe is actually running (i.e. first vblank) before
1223 * returning.
1224 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001225static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1226 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001227{
1228 int reg;
1229 u32 val;
1230
1231 /*
1232 * A pipe without a PLL won't actually be able to drive bits from
1233 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1234 * need the check.
1235 */
1236 if (!HAS_PCH_SPLIT(dev_priv->dev))
1237 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001238 else {
1239 if (pch_port) {
1240 /* if driving the PCH, we need FDI enabled */
1241 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1242 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1243 }
1244 /* FIXME: assert CPU port conditions for SNB+ */
1245 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246
1247 reg = PIPECONF(pipe);
1248 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001249 if (val & PIPECONF_ENABLE)
1250 return;
1251
1252 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001253 intel_wait_for_vblank(dev_priv->dev, pipe);
1254}
1255
1256/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001257 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001258 * @dev_priv: i915 private structure
1259 * @pipe: pipe to disable
1260 *
1261 * Disable @pipe, making sure that various hardware specific requirements
1262 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1263 *
1264 * @pipe should be %PIPE_A or %PIPE_B.
1265 *
1266 * Will wait until the pipe has shut down before returning.
1267 */
1268static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1269 enum pipe pipe)
1270{
1271 int reg;
1272 u32 val;
1273
1274 /*
1275 * Make sure planes won't keep trying to pump pixels to us,
1276 * or we might hang the display.
1277 */
1278 assert_planes_disabled(dev_priv, pipe);
1279
1280 /* Don't disable pipe A or pipe A PLLs if needed */
1281 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1282 return;
1283
1284 reg = PIPECONF(pipe);
1285 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001286 if ((val & PIPECONF_ENABLE) == 0)
1287 return;
1288
1289 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001290 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1291}
1292
1293/**
1294 * intel_enable_plane - enable a display plane on a given pipe
1295 * @dev_priv: i915 private structure
1296 * @plane: plane to enable
1297 * @pipe: pipe being fed
1298 *
1299 * Enable @plane on @pipe, making sure that @pipe is running first.
1300 */
1301static void intel_enable_plane(struct drm_i915_private *dev_priv,
1302 enum plane plane, enum pipe pipe)
1303{
1304 int reg;
1305 u32 val;
1306
1307 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1308 assert_pipe_enabled(dev_priv, pipe);
1309
1310 reg = DSPCNTR(plane);
1311 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001312 if (val & DISPLAY_PLANE_ENABLE)
1313 return;
1314
1315 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001316 intel_wait_for_vblank(dev_priv->dev, pipe);
1317}
1318
1319/*
1320 * Plane regs are double buffered, going from enabled->disabled needs a
1321 * trigger in order to latch. The display address reg provides this.
1322 */
1323static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1324 enum plane plane)
1325{
1326 u32 reg = DSPADDR(plane);
1327 I915_WRITE(reg, I915_READ(reg));
1328}
1329
1330/**
1331 * intel_disable_plane - disable a display plane
1332 * @dev_priv: i915 private structure
1333 * @plane: plane to disable
1334 * @pipe: pipe consuming the data
1335 *
1336 * Disable @plane; should be an independent operation.
1337 */
1338static void intel_disable_plane(struct drm_i915_private *dev_priv,
1339 enum plane plane, enum pipe pipe)
1340{
1341 int reg;
1342 u32 val;
1343
1344 reg = DSPCNTR(plane);
1345 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001346 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1347 return;
1348
1349 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001350 intel_flush_display_plane(dev_priv, plane);
1351 intel_wait_for_vblank(dev_priv->dev, pipe);
1352}
1353
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001354static void disable_pch_dp(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001355 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001356{
1357 u32 val = I915_READ(reg);
Keith Packardf0575e92011-07-25 22:12:43 -07001358 if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1359 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001360 I915_WRITE(reg, val & ~DP_PORT_EN);
Keith Packardf0575e92011-07-25 22:12:43 -07001361 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001362}
1363
1364static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1365 enum pipe pipe, int reg)
1366{
1367 u32 val = I915_READ(reg);
Keith Packardf0575e92011-07-25 22:12:43 -07001368 if (HDMI_PIPE_ENABLED(val, pipe)) {
1369 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1370 reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001371 I915_WRITE(reg, val & ~PORT_ENABLE);
Keith Packardf0575e92011-07-25 22:12:43 -07001372 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001373}
1374
1375/* Disable any ports connected to this transcoder */
1376static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1377 enum pipe pipe)
1378{
1379 u32 reg, val;
1380
1381 val = I915_READ(PCH_PP_CONTROL);
1382 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1383
Keith Packardf0575e92011-07-25 22:12:43 -07001384 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1385 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1386 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001387
1388 reg = PCH_ADPA;
1389 val = I915_READ(reg);
1390 if (ADPA_PIPE_ENABLED(val, pipe))
1391 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1392
1393 reg = PCH_LVDS;
1394 val = I915_READ(reg);
1395 if (LVDS_PIPE_ENABLED(val, pipe)) {
1396 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1397 POSTING_READ(reg);
1398 udelay(100);
1399 }
1400
1401 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1402 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1403 disable_pch_hdmi(dev_priv, pipe, HDMID);
1404}
1405
Jesse Barnes80824002009-09-10 15:28:06 -07001406static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1407{
1408 struct drm_device *dev = crtc->dev;
1409 struct drm_i915_private *dev_priv = dev->dev_private;
1410 struct drm_framebuffer *fb = crtc->fb;
1411 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001412 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes80824002009-09-10 15:28:06 -07001413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1414 int plane, i;
1415 u32 fbc_ctl, fbc_ctl2;
1416
Chris Wilsonbed4a672010-09-11 10:47:47 +01001417 if (fb->pitch == dev_priv->cfb_pitch &&
Chris Wilson05394f32010-11-08 19:18:58 +00001418 obj->fence_reg == dev_priv->cfb_fence &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001419 intel_crtc->plane == dev_priv->cfb_plane &&
1420 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1421 return;
1422
1423 i8xx_disable_fbc(dev);
1424
Jesse Barnes80824002009-09-10 15:28:06 -07001425 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1426
1427 if (fb->pitch < dev_priv->cfb_pitch)
1428 dev_priv->cfb_pitch = fb->pitch;
1429
1430 /* FBC_CTL wants 64B units */
1431 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001432 dev_priv->cfb_fence = obj->fence_reg;
Jesse Barnes80824002009-09-10 15:28:06 -07001433 dev_priv->cfb_plane = intel_crtc->plane;
1434 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1435
1436 /* Clear old tags */
1437 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1438 I915_WRITE(FBC_TAG + (i * 4), 0);
1439
1440 /* Set it up... */
1441 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
Chris Wilson05394f32010-11-08 19:18:58 +00001442 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes80824002009-09-10 15:28:06 -07001443 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1444 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1445 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1446
1447 /* enable it... */
1448 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
Jesse Barnesee25df22010-02-06 10:41:53 -08001449 if (IS_I945GM(dev))
Priit Laes49677902010-03-02 11:37:00 +02001450 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
Jesse Barnes80824002009-09-10 15:28:06 -07001451 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1452 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
Chris Wilson05394f32010-11-08 19:18:58 +00001453 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes80824002009-09-10 15:28:06 -07001454 fbc_ctl |= dev_priv->cfb_fence;
1455 I915_WRITE(FBC_CONTROL, fbc_ctl);
1456
Zhao Yakui28c97732009-10-09 11:39:41 +08001457 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
Chris Wilson5eddb702010-09-11 13:48:45 +01001458 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
Jesse Barnes80824002009-09-10 15:28:06 -07001459}
1460
1461void i8xx_disable_fbc(struct drm_device *dev)
1462{
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 u32 fbc_ctl;
1465
1466 /* Disable compression */
1467 fbc_ctl = I915_READ(FBC_CONTROL);
Chris Wilsona5cad622010-09-22 13:15:10 +01001468 if ((fbc_ctl & FBC_CTL_EN) == 0)
1469 return;
1470
Jesse Barnes80824002009-09-10 15:28:06 -07001471 fbc_ctl &= ~FBC_CTL_EN;
1472 I915_WRITE(FBC_CONTROL, fbc_ctl);
1473
1474 /* Wait for compressing bit to clear */
Chris Wilson481b6af2010-08-23 17:43:35 +01001475 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
Chris Wilson913d8d12010-08-07 11:01:35 +01001476 DRM_DEBUG_KMS("FBC idle timed out\n");
1477 return;
Jesse Barnes9517a922010-05-21 09:40:45 -07001478 }
Jesse Barnes80824002009-09-10 15:28:06 -07001479
Zhao Yakui28c97732009-10-09 11:39:41 +08001480 DRM_DEBUG_KMS("disabled FBC\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001481}
1482
Adam Jacksonee5382a2010-04-23 11:17:39 -04001483static bool i8xx_fbc_enabled(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001484{
Jesse Barnes80824002009-09-10 15:28:06 -07001485 struct drm_i915_private *dev_priv = dev->dev_private;
1486
1487 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1488}
1489
Jesse Barnes74dff282009-09-14 15:39:40 -07001490static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1491{
1492 struct drm_device *dev = crtc->dev;
1493 struct drm_i915_private *dev_priv = dev->dev_private;
1494 struct drm_framebuffer *fb = crtc->fb;
1495 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001496 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes74dff282009-09-14 15:39:40 -07001497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001498 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Jesse Barnes74dff282009-09-14 15:39:40 -07001499 unsigned long stall_watermark = 200;
1500 u32 dpfc_ctl;
1501
Chris Wilsonbed4a672010-09-11 10:47:47 +01001502 dpfc_ctl = I915_READ(DPFC_CONTROL);
1503 if (dpfc_ctl & DPFC_CTL_EN) {
1504 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
Chris Wilson05394f32010-11-08 19:18:58 +00001505 dev_priv->cfb_fence == obj->fence_reg &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001506 dev_priv->cfb_plane == intel_crtc->plane &&
1507 dev_priv->cfb_y == crtc->y)
1508 return;
1509
1510 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001511 intel_wait_for_vblank(dev, intel_crtc->pipe);
1512 }
1513
Jesse Barnes74dff282009-09-14 15:39:40 -07001514 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001515 dev_priv->cfb_fence = obj->fence_reg;
Jesse Barnes74dff282009-09-14 15:39:40 -07001516 dev_priv->cfb_plane = intel_crtc->plane;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001517 dev_priv->cfb_y = crtc->y;
Jesse Barnes74dff282009-09-14 15:39:40 -07001518
1519 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
Chris Wilson05394f32010-11-08 19:18:58 +00001520 if (obj->tiling_mode != I915_TILING_NONE) {
Jesse Barnes74dff282009-09-14 15:39:40 -07001521 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1522 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1523 } else {
1524 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1525 }
1526
Jesse Barnes74dff282009-09-14 15:39:40 -07001527 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1528 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1529 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1530 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1531
1532 /* enable it... */
1533 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1534
Zhao Yakui28c97732009-10-09 11:39:41 +08001535 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
Jesse Barnes74dff282009-09-14 15:39:40 -07001536}
1537
1538void g4x_disable_fbc(struct drm_device *dev)
1539{
1540 struct drm_i915_private *dev_priv = dev->dev_private;
1541 u32 dpfc_ctl;
1542
1543 /* Disable compression */
1544 dpfc_ctl = I915_READ(DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001545 if (dpfc_ctl & DPFC_CTL_EN) {
1546 dpfc_ctl &= ~DPFC_CTL_EN;
1547 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
Jesse Barnes74dff282009-09-14 15:39:40 -07001548
Chris Wilsonbed4a672010-09-11 10:47:47 +01001549 DRM_DEBUG_KMS("disabled FBC\n");
1550 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001551}
1552
Adam Jacksonee5382a2010-04-23 11:17:39 -04001553static bool g4x_fbc_enabled(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001554{
Jesse Barnes74dff282009-09-14 15:39:40 -07001555 struct drm_i915_private *dev_priv = dev->dev_private;
1556
1557 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1558}
1559
Jesse Barnes4efe0702011-01-18 11:25:41 -08001560static void sandybridge_blit_fbc_update(struct drm_device *dev)
1561{
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 u32 blt_ecoskpd;
1564
1565 /* Make sure blitter notifies FBC of writes */
Ben Widawskyfcca7922011-04-25 11:23:07 -07001566 gen6_gt_force_wake_get(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001567 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1568 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1569 GEN6_BLITTER_LOCK_SHIFT;
1570 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1571 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1572 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1573 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1574 GEN6_BLITTER_LOCK_SHIFT);
1575 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1576 POSTING_READ(GEN6_BLITTER_ECOSKPD);
Ben Widawskyfcca7922011-04-25 11:23:07 -07001577 gen6_gt_force_wake_put(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001578}
1579
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001580static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1581{
1582 struct drm_device *dev = crtc->dev;
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 struct drm_framebuffer *fb = crtc->fb;
1585 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001586 struct drm_i915_gem_object *obj = intel_fb->obj;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001588 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001589 unsigned long stall_watermark = 200;
1590 u32 dpfc_ctl;
1591
Chris Wilsonbed4a672010-09-11 10:47:47 +01001592 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1593 if (dpfc_ctl & DPFC_CTL_EN) {
1594 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
Chris Wilson05394f32010-11-08 19:18:58 +00001595 dev_priv->cfb_fence == obj->fence_reg &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001596 dev_priv->cfb_plane == intel_crtc->plane &&
Chris Wilson05394f32010-11-08 19:18:58 +00001597 dev_priv->cfb_offset == obj->gtt_offset &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001598 dev_priv->cfb_y == crtc->y)
1599 return;
1600
1601 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001602 intel_wait_for_vblank(dev, intel_crtc->pipe);
1603 }
1604
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001605 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001606 dev_priv->cfb_fence = obj->fence_reg;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001607 dev_priv->cfb_plane = intel_crtc->plane;
Chris Wilson05394f32010-11-08 19:18:58 +00001608 dev_priv->cfb_offset = obj->gtt_offset;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001609 dev_priv->cfb_y = crtc->y;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001610
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001611 dpfc_ctl &= DPFC_RESERVED;
1612 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
Chris Wilson05394f32010-11-08 19:18:58 +00001613 if (obj->tiling_mode != I915_TILING_NONE) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001614 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1615 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1616 } else {
1617 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1618 }
1619
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001620 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
Chris Wilson05394f32010-11-08 19:18:58 +00001624 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001625 /* enable it... */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001626 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001627
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001628 if (IS_GEN6(dev)) {
1629 I915_WRITE(SNB_DPFC_CTL_SA,
1630 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1631 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001632 sandybridge_blit_fbc_update(dev);
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001633 }
1634
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001635 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1636}
1637
1638void ironlake_disable_fbc(struct drm_device *dev)
1639{
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 u32 dpfc_ctl;
1642
1643 /* Disable compression */
1644 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001645 if (dpfc_ctl & DPFC_CTL_EN) {
1646 dpfc_ctl &= ~DPFC_CTL_EN;
1647 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001648
Chris Wilsonbed4a672010-09-11 10:47:47 +01001649 DRM_DEBUG_KMS("disabled FBC\n");
1650 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001651}
1652
1653static bool ironlake_fbc_enabled(struct drm_device *dev)
1654{
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1658}
1659
Adam Jacksonee5382a2010-04-23 11:17:39 -04001660bool intel_fbc_enabled(struct drm_device *dev)
1661{
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664 if (!dev_priv->display.fbc_enabled)
1665 return false;
1666
1667 return dev_priv->display.fbc_enabled(dev);
1668}
1669
1670void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671{
1672 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1673
1674 if (!dev_priv->display.enable_fbc)
1675 return;
1676
1677 dev_priv->display.enable_fbc(crtc, interval);
1678}
1679
1680void intel_disable_fbc(struct drm_device *dev)
1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 if (!dev_priv->display.disable_fbc)
1685 return;
1686
1687 dev_priv->display.disable_fbc(dev);
1688}
1689
Jesse Barnes80824002009-09-10 15:28:06 -07001690/**
1691 * intel_update_fbc - enable/disable FBC as needed
Chris Wilsonbed4a672010-09-11 10:47:47 +01001692 * @dev: the drm_device
Jesse Barnes80824002009-09-10 15:28:06 -07001693 *
1694 * Set up the framebuffer compression hardware at mode set time. We
1695 * enable it if possible:
1696 * - plane A only (on pre-965)
1697 * - no pixel mulitply/line duplication
1698 * - no alpha buffer discard
1699 * - no dual wide
1700 * - framebuffer <= 2048 in width, 1536 in height
1701 *
1702 * We can't assume that any compression will take place (worst case),
1703 * so the compressed buffer has to be the same size as the uncompressed
1704 * one. It also must reside (along with the line length buffer) in
1705 * stolen memory.
1706 *
1707 * We need to enable/disable FBC on a global basis.
1708 */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001709static void intel_update_fbc(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001710{
Jesse Barnes80824002009-09-10 15:28:06 -07001711 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001712 struct drm_crtc *crtc = NULL, *tmp_crtc;
1713 struct intel_crtc *intel_crtc;
1714 struct drm_framebuffer *fb;
Jesse Barnes80824002009-09-10 15:28:06 -07001715 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001716 struct drm_i915_gem_object *obj;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001717
1718 DRM_DEBUG_KMS("\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001719
1720 if (!i915_powersave)
1721 return;
1722
Adam Jacksonee5382a2010-04-23 11:17:39 -04001723 if (!I915_HAS_FBC(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07001724 return;
1725
Jesse Barnes80824002009-09-10 15:28:06 -07001726 /*
1727 * If FBC is already on, we just have to verify that we can
1728 * keep it that way...
1729 * Need to disable if:
Jesse Barnes9c928d12010-07-23 15:20:00 -07001730 * - more than one pipe is active
Jesse Barnes80824002009-09-10 15:28:06 -07001731 * - changing FBC params (stride, fence, mode)
1732 * - new fb is too large to fit in compressed buffer
1733 * - going to an unsupported config (interlace, pixel multiply, etc.)
1734 */
Jesse Barnes9c928d12010-07-23 15:20:00 -07001735 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsond2102462011-01-24 17:43:27 +00001736 if (tmp_crtc->enabled && tmp_crtc->fb) {
Chris Wilsonbed4a672010-09-11 10:47:47 +01001737 if (crtc) {
1738 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1739 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1740 goto out_disable;
1741 }
1742 crtc = tmp_crtc;
1743 }
Jesse Barnes9c928d12010-07-23 15:20:00 -07001744 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001745
1746 if (!crtc || crtc->fb == NULL) {
1747 DRM_DEBUG_KMS("no output, disabling\n");
1748 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001749 goto out_disable;
1750 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001751
1752 intel_crtc = to_intel_crtc(crtc);
1753 fb = crtc->fb;
1754 intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001755 obj = intel_fb->obj;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001756
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001757 if (!i915_enable_fbc) {
1758 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1759 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1760 goto out_disable;
1761 }
Chris Wilson05394f32010-11-08 19:18:58 +00001762 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001763 DRM_DEBUG_KMS("framebuffer too large, disabling "
Chris Wilson5eddb702010-09-11 13:48:45 +01001764 "compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001765 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001766 goto out_disable;
1767 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001768 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1769 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001770 DRM_DEBUG_KMS("mode incompatible with compression, "
Chris Wilson5eddb702010-09-11 13:48:45 +01001771 "disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001772 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
Jesse Barnes80824002009-09-10 15:28:06 -07001773 goto out_disable;
1774 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001775 if ((crtc->mode.hdisplay > 2048) ||
1776 (crtc->mode.vdisplay > 1536)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001777 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001778 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
Jesse Barnes80824002009-09-10 15:28:06 -07001779 goto out_disable;
1780 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001781 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001782 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001783 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
Jesse Barnes80824002009-09-10 15:28:06 -07001784 goto out_disable;
1785 }
Chris Wilson05394f32010-11-08 19:18:58 +00001786 if (obj->tiling_mode != I915_TILING_X) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001787 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001788 dev_priv->no_fbc_reason = FBC_NOT_TILED;
Jesse Barnes80824002009-09-10 15:28:06 -07001789 goto out_disable;
1790 }
1791
Jason Wesselc924b932010-08-05 09:22:32 -05001792 /* If the kernel debugger is active, always disable compression */
1793 if (in_dbg_master())
1794 goto out_disable;
1795
Chris Wilsonbed4a672010-09-11 10:47:47 +01001796 intel_enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07001797 return;
1798
1799out_disable:
Jesse Barnes80824002009-09-10 15:28:06 -07001800 /* Multiple disables should be harmless */
Chris Wilsona9394062010-05-27 13:18:16 +01001801 if (intel_fbc_enabled(dev)) {
1802 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
Adam Jacksonee5382a2010-04-23 11:17:39 -04001803 intel_disable_fbc(dev);
Chris Wilsona9394062010-05-27 13:18:16 +01001804 }
Jesse Barnes80824002009-09-10 15:28:06 -07001805}
1806
Chris Wilson127bd2a2010-07-23 23:32:05 +01001807int
Chris Wilson48b956c2010-09-14 12:50:34 +01001808intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001809 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001810 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001811{
Chris Wilsonce453d82011-02-21 14:43:56 +00001812 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001813 u32 alignment;
1814 int ret;
1815
Chris Wilson05394f32010-11-08 19:18:58 +00001816 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001817 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001818 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1819 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001820 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001821 alignment = 4 * 1024;
1822 else
1823 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001824 break;
1825 case I915_TILING_X:
1826 /* pin() will align the object as required by fence */
1827 alignment = 0;
1828 break;
1829 case I915_TILING_Y:
1830 /* FIXME: Is this true? */
1831 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1832 return -EINVAL;
1833 default:
1834 BUG();
1835 }
1836
Chris Wilsonce453d82011-02-21 14:43:56 +00001837 dev_priv->mm.interruptible = false;
Daniel Vetter75e9e912010-11-04 17:11:09 +01001838 ret = i915_gem_object_pin(obj, alignment, true);
Chris Wilson48b956c2010-09-14 12:50:34 +01001839 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001840 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001841
Chris Wilson48b956c2010-09-14 12:50:34 +01001842 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1843 if (ret)
1844 goto err_unpin;
Chris Wilson72133422010-09-13 23:56:38 +01001845
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001846 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1847 * fence, whereas 965+ only requires a fence if using
1848 * framebuffer compression. For simplicity, we always install
1849 * a fence as the cost is not that onerous.
1850 */
Chris Wilson05394f32010-11-08 19:18:58 +00001851 if (obj->tiling_mode != I915_TILING_NONE) {
Chris Wilsonce453d82011-02-21 14:43:56 +00001852 ret = i915_gem_object_get_fence(obj, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001853 if (ret)
1854 goto err_unpin;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001855 }
1856
Chris Wilsonce453d82011-02-21 14:43:56 +00001857 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001858 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001859
1860err_unpin:
1861 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001862err_interruptible:
1863 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001864 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001865}
1866
Jesse Barnes81255562010-08-02 12:07:50 -07001867/* Assume fb object is pinned & idle & fenced and just update base pointers */
1868static int
1869intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
Jason Wessel21c74a82010-10-13 14:09:44 -05001870 int x, int y, enum mode_set_atomic state)
Jesse Barnes81255562010-08-02 12:07:50 -07001871{
1872 struct drm_device *dev = crtc->dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1875 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001876 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001877 int plane = intel_crtc->plane;
1878 unsigned long Start, Offset;
Jesse Barnes81255562010-08-02 12:07:50 -07001879 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01001880 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07001881
1882 switch (plane) {
1883 case 0:
1884 case 1:
1885 break;
1886 default:
1887 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1888 return -EINVAL;
1889 }
1890
1891 intel_fb = to_intel_framebuffer(fb);
1892 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001893
Chris Wilson5eddb702010-09-11 13:48:45 +01001894 reg = DSPCNTR(plane);
1895 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07001896 /* Mask out pixel format bits in case we change it */
1897 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1898 switch (fb->bits_per_pixel) {
1899 case 8:
1900 dspcntr |= DISPPLANE_8BPP;
1901 break;
1902 case 16:
1903 if (fb->depth == 15)
1904 dspcntr |= DISPPLANE_15_16BPP;
1905 else
1906 dspcntr |= DISPPLANE_16BPP;
1907 break;
1908 case 24:
1909 case 32:
1910 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1911 break;
1912 default:
1913 DRM_ERROR("Unknown color depth\n");
1914 return -EINVAL;
1915 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001916 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00001917 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07001918 dspcntr |= DISPPLANE_TILED;
1919 else
1920 dspcntr &= ~DISPPLANE_TILED;
1921 }
1922
Chris Wilson4e6cfef2010-08-08 13:20:19 +01001923 if (HAS_PCH_SPLIT(dev))
Jesse Barnes81255562010-08-02 12:07:50 -07001924 /* must disable */
1925 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1926
Chris Wilson5eddb702010-09-11 13:48:45 +01001927 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07001928
Chris Wilson05394f32010-11-08 19:18:58 +00001929 Start = obj->gtt_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07001930 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1931
Chris Wilson4e6cfef2010-08-08 13:20:19 +01001932 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1933 Start, Offset, x, y, fb->pitch);
Chris Wilson5eddb702010-09-11 13:48:45 +01001934 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001935 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson5eddb702010-09-11 13:48:45 +01001936 I915_WRITE(DSPSURF(plane), Start);
1937 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1938 I915_WRITE(DSPADDR(plane), Offset);
1939 } else
1940 I915_WRITE(DSPADDR(plane), Start + Offset);
1941 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07001942
Chris Wilsonbed4a672010-09-11 10:47:47 +01001943 intel_update_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02001944 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07001945
1946 return 0;
1947}
1948
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001949static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001950intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1951 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08001952{
1953 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08001954 struct drm_i915_master_private *master_priv;
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001956 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08001957
1958 /* no fb bound */
1959 if (!crtc->fb) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001960 DRM_DEBUG_KMS("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001961 return 0;
1962 }
1963
Chris Wilson265db952010-09-20 15:41:01 +01001964 switch (intel_crtc->plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001965 case 0:
1966 case 1:
1967 break;
1968 default:
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001969 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001970 }
1971
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001972 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01001973 ret = intel_pin_and_fence_fb_obj(dev,
1974 to_intel_framebuffer(crtc->fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001975 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001976 if (ret != 0) {
1977 mutex_unlock(&dev->struct_mutex);
1978 return ret;
1979 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001980
Chris Wilson265db952010-09-20 15:41:01 +01001981 if (old_fb) {
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01001982 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00001983 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
Chris Wilson265db952010-09-20 15:41:01 +01001984
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01001985 wait_event(dev_priv->pending_flip_queue,
Chris Wilson01eec722011-02-11 20:47:45 +00001986 atomic_read(&dev_priv->mm.wedged) ||
Chris Wilson05394f32010-11-08 19:18:58 +00001987 atomic_read(&obj->pending_flip) == 0);
Chris Wilson85345512010-11-13 09:49:11 +00001988
1989 /* Big Hammer, we also need to ensure that any pending
1990 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1991 * current scanout is retired before unpinning the old
1992 * framebuffer.
Chris Wilson01eec722011-02-11 20:47:45 +00001993 *
1994 * This should only fail upon a hung GPU, in which case we
1995 * can safely continue.
Chris Wilson85345512010-11-13 09:49:11 +00001996 */
Chris Wilsonce453d82011-02-21 14:43:56 +00001997 ret = i915_gem_object_flush_gpu(obj);
Chris Wilson01eec722011-02-11 20:47:45 +00001998 (void) ret;
Chris Wilson265db952010-09-20 15:41:01 +01001999 }
2000
Jason Wessel21c74a82010-10-13 14:09:44 -05002001 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2002 LEAVE_ATOMIC_MODE_SET);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002003 if (ret) {
Chris Wilson265db952010-09-20 15:41:01 +01002004 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002005 mutex_unlock(&dev->struct_mutex);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002006 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002007 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002008
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002009 if (old_fb) {
2010 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson265db952010-09-20 15:41:01 +01002011 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002012 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002013
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002014 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002015
2016 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002017 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002018
2019 master_priv = dev->primary->master->driver_priv;
2020 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002021 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002022
Chris Wilson265db952010-09-20 15:41:01 +01002023 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002024 master_priv->sarea_priv->pipeB_x = x;
2025 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002026 } else {
2027 master_priv->sarea_priv->pipeA_x = x;
2028 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002029 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002030
2031 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002032}
2033
Chris Wilson5eddb702010-09-11 13:48:45 +01002034static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002035{
2036 struct drm_device *dev = crtc->dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 u32 dpa_ctl;
2039
Zhao Yakui28c97732009-10-09 11:39:41 +08002040 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002041 dpa_ctl = I915_READ(DP_A);
2042 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2043
2044 if (clock < 200000) {
2045 u32 temp;
2046 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2047 /* workaround for 160Mhz:
2048 1) program 0x4600c bits 15:0 = 0x8124
2049 2) program 0x46010 bit 0 = 1
2050 3) program 0x46034 bit 24 = 1
2051 4) program 0x64000 bit 14 = 1
2052 */
2053 temp = I915_READ(0x4600c);
2054 temp &= 0xffff0000;
2055 I915_WRITE(0x4600c, temp | 0x8124);
2056
2057 temp = I915_READ(0x46010);
2058 I915_WRITE(0x46010, temp | 1);
2059
2060 temp = I915_READ(0x46034);
2061 I915_WRITE(0x46034, temp | (1 << 24));
2062 } else {
2063 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2064 }
2065 I915_WRITE(DP_A, dpa_ctl);
2066
Chris Wilson5eddb702010-09-11 13:48:45 +01002067 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002068 udelay(500);
2069}
2070
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002071static void intel_fdi_normal_train(struct drm_crtc *crtc)
2072{
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2076 int pipe = intel_crtc->pipe;
2077 u32 reg, temp;
2078
2079 /* enable normal train */
2080 reg = FDI_TX_CTL(pipe);
2081 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002082 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002083 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2084 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002085 } else {
2086 temp &= ~FDI_LINK_TRAIN_NONE;
2087 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002088 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002089 I915_WRITE(reg, temp);
2090
2091 reg = FDI_RX_CTL(pipe);
2092 temp = I915_READ(reg);
2093 if (HAS_PCH_CPT(dev)) {
2094 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2095 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2096 } else {
2097 temp &= ~FDI_LINK_TRAIN_NONE;
2098 temp |= FDI_LINK_TRAIN_NONE;
2099 }
2100 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2101
2102 /* wait one idle pattern time */
2103 POSTING_READ(reg);
2104 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002105
2106 /* IVB wants error correction enabled */
2107 if (IS_IVYBRIDGE(dev))
2108 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2109 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002110}
2111
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002112/* The FDI link training functions for ILK/Ibexpeak. */
2113static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2114{
2115 struct drm_device *dev = crtc->dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2118 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002119 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002120 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002121
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002122 /* FDI needs bits from pipe & plane first */
2123 assert_pipe_enabled(dev_priv, pipe);
2124 assert_plane_enabled(dev_priv, plane);
2125
Adam Jacksone1a44742010-06-25 15:32:14 -04002126 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2127 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002128 reg = FDI_RX_IMR(pipe);
2129 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002130 temp &= ~FDI_RX_SYMBOL_LOCK;
2131 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002132 I915_WRITE(reg, temp);
2133 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002134 udelay(150);
2135
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002136 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002137 reg = FDI_TX_CTL(pipe);
2138 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002139 temp &= ~(7 << 19);
2140 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002141 temp &= ~FDI_LINK_TRAIN_NONE;
2142 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002143 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002144
Chris Wilson5eddb702010-09-11 13:48:45 +01002145 reg = FDI_RX_CTL(pipe);
2146 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002147 temp &= ~FDI_LINK_TRAIN_NONE;
2148 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002149 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2150
2151 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002152 udelay(150);
2153
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002154 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002155 if (HAS_PCH_IBX(dev)) {
2156 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2157 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2158 FDI_RX_PHASE_SYNC_POINTER_EN);
2159 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002160
Chris Wilson5eddb702010-09-11 13:48:45 +01002161 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002162 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002163 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002164 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2165
2166 if ((temp & FDI_RX_BIT_LOCK)) {
2167 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002168 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002169 break;
2170 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002171 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002172 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002173 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002174
2175 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002176 reg = FDI_TX_CTL(pipe);
2177 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002178 temp &= ~FDI_LINK_TRAIN_NONE;
2179 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002180 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002181
Chris Wilson5eddb702010-09-11 13:48:45 +01002182 reg = FDI_RX_CTL(pipe);
2183 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002184 temp &= ~FDI_LINK_TRAIN_NONE;
2185 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002186 I915_WRITE(reg, temp);
2187
2188 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002189 udelay(150);
2190
Chris Wilson5eddb702010-09-11 13:48:45 +01002191 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002192 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002193 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002194 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2195
2196 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002197 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002198 DRM_DEBUG_KMS("FDI train 2 done.\n");
2199 break;
2200 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002201 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002202 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002203 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002204
2205 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002206
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002207}
2208
Chris Wilson311bd682011-01-13 19:06:50 +00002209static const int snb_b_fdi_train_param [] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002210 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2211 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2212 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2213 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2214};
2215
2216/* The FDI link training functions for SNB/Cougarpoint. */
2217static void gen6_fdi_link_train(struct drm_crtc *crtc)
2218{
2219 struct drm_device *dev = crtc->dev;
2220 struct drm_i915_private *dev_priv = dev->dev_private;
2221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2222 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002223 u32 reg, temp, i;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002224
Adam Jacksone1a44742010-06-25 15:32:14 -04002225 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2226 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002227 reg = FDI_RX_IMR(pipe);
2228 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002229 temp &= ~FDI_RX_SYMBOL_LOCK;
2230 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002231 I915_WRITE(reg, temp);
2232
2233 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002234 udelay(150);
2235
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002236 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002237 reg = FDI_TX_CTL(pipe);
2238 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002239 temp &= ~(7 << 19);
2240 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002241 temp &= ~FDI_LINK_TRAIN_NONE;
2242 temp |= FDI_LINK_TRAIN_PATTERN_1;
2243 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2244 /* SNB-B */
2245 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002246 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002247
Chris Wilson5eddb702010-09-11 13:48:45 +01002248 reg = FDI_RX_CTL(pipe);
2249 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002250 if (HAS_PCH_CPT(dev)) {
2251 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2252 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2253 } else {
2254 temp &= ~FDI_LINK_TRAIN_NONE;
2255 temp |= FDI_LINK_TRAIN_PATTERN_1;
2256 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002257 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2258
2259 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002260 udelay(150);
2261
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002262 for (i = 0; i < 4; i++ ) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002263 reg = FDI_TX_CTL(pipe);
2264 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002265 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2266 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002267 I915_WRITE(reg, temp);
2268
2269 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002270 udelay(500);
2271
Chris Wilson5eddb702010-09-11 13:48:45 +01002272 reg = FDI_RX_IIR(pipe);
2273 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002274 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2275
2276 if (temp & FDI_RX_BIT_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002277 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002278 DRM_DEBUG_KMS("FDI train 1 done.\n");
2279 break;
2280 }
2281 }
2282 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002283 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002284
2285 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002286 reg = FDI_TX_CTL(pipe);
2287 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002288 temp &= ~FDI_LINK_TRAIN_NONE;
2289 temp |= FDI_LINK_TRAIN_PATTERN_2;
2290 if (IS_GEN6(dev)) {
2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292 /* SNB-B */
2293 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2294 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002295 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002296
Chris Wilson5eddb702010-09-11 13:48:45 +01002297 reg = FDI_RX_CTL(pipe);
2298 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002299 if (HAS_PCH_CPT(dev)) {
2300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2301 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2302 } else {
2303 temp &= ~FDI_LINK_TRAIN_NONE;
2304 temp |= FDI_LINK_TRAIN_PATTERN_2;
2305 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002306 I915_WRITE(reg, temp);
2307
2308 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002309 udelay(150);
2310
2311 for (i = 0; i < 4; i++ ) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002312 reg = FDI_TX_CTL(pipe);
2313 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002314 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2315 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002316 I915_WRITE(reg, temp);
2317
2318 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002319 udelay(500);
2320
Chris Wilson5eddb702010-09-11 13:48:45 +01002321 reg = FDI_RX_IIR(pipe);
2322 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002323 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2324
2325 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002326 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002327 DRM_DEBUG_KMS("FDI train 2 done.\n");
2328 break;
2329 }
2330 }
2331 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002332 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002333
2334 DRM_DEBUG_KMS("FDI train done.\n");
2335}
2336
Jesse Barnes357555c2011-04-28 15:09:55 -07002337/* Manual link training for Ivy Bridge A0 parts */
2338static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2339{
2340 struct drm_device *dev = crtc->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343 int pipe = intel_crtc->pipe;
2344 u32 reg, temp, i;
2345
2346 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2347 for train result */
2348 reg = FDI_RX_IMR(pipe);
2349 temp = I915_READ(reg);
2350 temp &= ~FDI_RX_SYMBOL_LOCK;
2351 temp &= ~FDI_RX_BIT_LOCK;
2352 I915_WRITE(reg, temp);
2353
2354 POSTING_READ(reg);
2355 udelay(150);
2356
2357 /* enable CPU FDI TX and PCH FDI RX */
2358 reg = FDI_TX_CTL(pipe);
2359 temp = I915_READ(reg);
2360 temp &= ~(7 << 19);
2361 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2362 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2363 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2364 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2365 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2366 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2367
2368 reg = FDI_RX_CTL(pipe);
2369 temp = I915_READ(reg);
2370 temp &= ~FDI_LINK_TRAIN_AUTO;
2371 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2372 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2373 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2374
2375 POSTING_READ(reg);
2376 udelay(150);
2377
2378 for (i = 0; i < 4; i++ ) {
2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
2381 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2382 temp |= snb_b_fdi_train_param[i];
2383 I915_WRITE(reg, temp);
2384
2385 POSTING_READ(reg);
2386 udelay(500);
2387
2388 reg = FDI_RX_IIR(pipe);
2389 temp = I915_READ(reg);
2390 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392 if (temp & FDI_RX_BIT_LOCK ||
2393 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2394 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2395 DRM_DEBUG_KMS("FDI train 1 done.\n");
2396 break;
2397 }
2398 }
2399 if (i == 4)
2400 DRM_ERROR("FDI train 1 fail!\n");
2401
2402 /* Train 2 */
2403 reg = FDI_TX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2406 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2407 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2408 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2409 I915_WRITE(reg, temp);
2410
2411 reg = FDI_RX_CTL(pipe);
2412 temp = I915_READ(reg);
2413 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2415 I915_WRITE(reg, temp);
2416
2417 POSTING_READ(reg);
2418 udelay(150);
2419
2420 for (i = 0; i < 4; i++ ) {
2421 reg = FDI_TX_CTL(pipe);
2422 temp = I915_READ(reg);
2423 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2424 temp |= snb_b_fdi_train_param[i];
2425 I915_WRITE(reg, temp);
2426
2427 POSTING_READ(reg);
2428 udelay(500);
2429
2430 reg = FDI_RX_IIR(pipe);
2431 temp = I915_READ(reg);
2432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433
2434 if (temp & FDI_RX_SYMBOL_LOCK) {
2435 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2436 DRM_DEBUG_KMS("FDI train 2 done.\n");
2437 break;
2438 }
2439 }
2440 if (i == 4)
2441 DRM_ERROR("FDI train 2 fail!\n");
2442
2443 DRM_DEBUG_KMS("FDI train done.\n");
2444}
2445
2446static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002447{
2448 struct drm_device *dev = crtc->dev;
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002452 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002453
Jesse Barnesc64e3112010-09-10 11:27:03 -07002454 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002455 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2456 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002457
Jesse Barnes0e23b992010-09-10 11:10:00 -07002458 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002459 reg = FDI_RX_CTL(pipe);
2460 temp = I915_READ(reg);
2461 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002462 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002463 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2464 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2465
2466 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002467 udelay(200);
2468
2469 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002470 temp = I915_READ(reg);
2471 I915_WRITE(reg, temp | FDI_PCDCLK);
2472
2473 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002474 udelay(200);
2475
2476 /* Enable CPU FDI TX PLL, always on for Ironlake */
Chris Wilson5eddb702010-09-11 13:48:45 +01002477 reg = FDI_TX_CTL(pipe);
2478 temp = I915_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002479 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002480 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2481
2482 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002483 udelay(100);
2484 }
2485}
2486
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002487static void ironlake_fdi_disable(struct drm_crtc *crtc)
2488{
2489 struct drm_device *dev = crtc->dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2492 int pipe = intel_crtc->pipe;
2493 u32 reg, temp;
2494
2495 /* disable CPU FDI tx and PCH FDI rx */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2499 POSTING_READ(reg);
2500
2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~(0x7 << 16);
2504 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2505 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
2508 udelay(100);
2509
2510 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002511 if (HAS_PCH_IBX(dev)) {
2512 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002513 I915_WRITE(FDI_RX_CHICKEN(pipe),
2514 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002515 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2516 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002517
2518 /* still set train pattern 1 */
2519 reg = FDI_TX_CTL(pipe);
2520 temp = I915_READ(reg);
2521 temp &= ~FDI_LINK_TRAIN_NONE;
2522 temp |= FDI_LINK_TRAIN_PATTERN_1;
2523 I915_WRITE(reg, temp);
2524
2525 reg = FDI_RX_CTL(pipe);
2526 temp = I915_READ(reg);
2527 if (HAS_PCH_CPT(dev)) {
2528 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2529 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2530 } else {
2531 temp &= ~FDI_LINK_TRAIN_NONE;
2532 temp |= FDI_LINK_TRAIN_PATTERN_1;
2533 }
2534 /* BPC in FDI rx is consistent with that in PIPECONF */
2535 temp &= ~(0x07 << 16);
2536 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2537 I915_WRITE(reg, temp);
2538
2539 POSTING_READ(reg);
2540 udelay(100);
2541}
2542
Chris Wilson6b383a72010-09-13 13:54:26 +01002543/*
2544 * When we disable a pipe, we need to clear any pending scanline wait events
2545 * to avoid hanging the ring, which we assume we are waiting on.
2546 */
2547static void intel_clear_scanline_wait(struct drm_device *dev)
2548{
2549 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8168bd42010-11-11 17:54:52 +00002550 struct intel_ring_buffer *ring;
Chris Wilson6b383a72010-09-13 13:54:26 +01002551 u32 tmp;
2552
2553 if (IS_GEN2(dev))
2554 /* Can't break the hang on i8xx */
2555 return;
2556
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002557 ring = LP_RING(dev_priv);
Chris Wilson8168bd42010-11-11 17:54:52 +00002558 tmp = I915_READ_CTL(ring);
2559 if (tmp & RING_WAIT)
2560 I915_WRITE_CTL(ring, tmp);
Chris Wilson6b383a72010-09-13 13:54:26 +01002561}
2562
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002563static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2564{
Chris Wilson05394f32010-11-08 19:18:58 +00002565 struct drm_i915_gem_object *obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002566 struct drm_i915_private *dev_priv;
2567
2568 if (crtc->fb == NULL)
2569 return;
2570
Chris Wilson05394f32010-11-08 19:18:58 +00002571 obj = to_intel_framebuffer(crtc->fb)->obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002572 dev_priv = crtc->dev->dev_private;
2573 wait_event(dev_priv->pending_flip_queue,
Chris Wilson05394f32010-11-08 19:18:58 +00002574 atomic_read(&obj->pending_flip) == 0);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002575}
2576
Jesse Barnes040484a2011-01-03 12:14:26 -08002577static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2578{
2579 struct drm_device *dev = crtc->dev;
2580 struct drm_mode_config *mode_config = &dev->mode_config;
2581 struct intel_encoder *encoder;
2582
2583 /*
2584 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2585 * must be driven by its own crtc; no sharing is possible.
2586 */
2587 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2588 if (encoder->base.crtc != crtc)
2589 continue;
2590
2591 switch (encoder->type) {
2592 case INTEL_OUTPUT_EDP:
2593 if (!intel_encoder_is_pch_edp(&encoder->base))
2594 return false;
2595 continue;
2596 }
2597 }
2598
2599 return true;
2600}
2601
Jesse Barnesf67a5592011-01-05 10:31:48 -08002602/*
2603 * Enable PCH resources required for PCH ports:
2604 * - PCH PLLs
2605 * - FDI training & RX/TX
2606 * - update transcoder timings
2607 * - DP transcoding bits
2608 * - transcoder
2609 */
2610static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002611{
2612 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002616 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002617
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002618 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07002619 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002620
Jesse Barnes92f25842011-01-04 15:09:34 -08002621 intel_enable_pch_pll(dev_priv, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002622
2623 if (HAS_PCH_CPT(dev)) {
2624 /* Be sure PCH DPLL SEL is set */
2625 temp = I915_READ(PCH_DPLL_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002626 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002627 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002628 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002629 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2630 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002631 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002632
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08002633 /* set transcoder timing, panel must allow it */
2634 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01002635 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2636 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2637 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2638
2639 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2640 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2641 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002642
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002643 intel_fdi_normal_train(crtc);
2644
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002645 /* For PCH DP, enable TRANS_DP_CTL */
2646 if (HAS_PCH_CPT(dev) &&
2647 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002648 reg = TRANS_DP_CTL(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08002651 TRANS_DP_SYNC_MASK |
2652 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01002653 temp |= (TRANS_DP_OUTPUT_ENABLE |
2654 TRANS_DP_ENH_FRAMING);
Eric Anholt220cad32010-11-18 09:32:58 +08002655 temp |= TRANS_DP_8BPC;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002656
2657 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002658 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002659 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002660 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002661
2662 switch (intel_trans_dp_port_sel(crtc)) {
2663 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01002664 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002665 break;
2666 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01002667 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002668 break;
2669 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01002670 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002671 break;
2672 default:
2673 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002674 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002675 break;
2676 }
2677
Chris Wilson5eddb702010-09-11 13:48:45 +01002678 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002679 }
2680
Jesse Barnes040484a2011-01-03 12:14:26 -08002681 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002682}
2683
2684static void ironlake_crtc_enable(struct drm_crtc *crtc)
2685{
2686 struct drm_device *dev = crtc->dev;
2687 struct drm_i915_private *dev_priv = dev->dev_private;
2688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2689 int pipe = intel_crtc->pipe;
2690 int plane = intel_crtc->plane;
2691 u32 temp;
2692 bool is_pch_port;
2693
2694 if (intel_crtc->active)
2695 return;
2696
2697 intel_crtc->active = true;
2698 intel_update_watermarks(dev);
2699
2700 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2701 temp = I915_READ(PCH_LVDS);
2702 if ((temp & LVDS_PORT_EN) == 0)
2703 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2704 }
2705
2706 is_pch_port = intel_crtc_driving_pch(crtc);
2707
2708 if (is_pch_port)
Jesse Barnes357555c2011-04-28 15:09:55 -07002709 ironlake_fdi_pll_enable(crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002710 else
2711 ironlake_fdi_disable(crtc);
2712
2713 /* Enable panel fitting for LVDS */
2714 if (dev_priv->pch_pf_size &&
2715 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2716 /* Force use of hard-coded filter coefficients
2717 * as some pre-programmed values are broken,
2718 * e.g. x201.
2719 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002720 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2721 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2722 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002723 }
2724
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02002725 /*
2726 * On ILK+ LUT must be loaded before the pipe is running but with
2727 * clocks enabled
2728 */
2729 intel_crtc_load_lut(crtc);
2730
Jesse Barnesf67a5592011-01-05 10:31:48 -08002731 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2732 intel_enable_plane(dev_priv, plane, pipe);
2733
2734 if (is_pch_port)
2735 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002736
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01002737 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01002738 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01002739 mutex_unlock(&dev->struct_mutex);
2740
Chris Wilson6b383a72010-09-13 13:54:26 +01002741 intel_crtc_update_cursor(crtc, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002742}
2743
2744static void ironlake_crtc_disable(struct drm_crtc *crtc)
2745{
2746 struct drm_device *dev = crtc->dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2749 int pipe = intel_crtc->pipe;
2750 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002751 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002752
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002753 if (!intel_crtc->active)
2754 return;
2755
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002756 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002757 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01002758 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01002759
Jesse Barnesb24e7172011-01-04 15:09:30 -08002760 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002761
2762 if (dev_priv->cfb_plane == plane &&
2763 dev_priv->display.disable_fbc)
2764 dev_priv->display.disable_fbc(dev);
2765
Jesse Barnesb24e7172011-01-04 15:09:30 -08002766 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002767
Jesse Barnes6be4a602010-09-10 10:26:01 -07002768 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002769 I915_WRITE(PF_CTL(pipe), 0);
2770 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002771
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002772 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002773
Jesse Barnes47a05ec2011-02-07 13:46:40 -08002774 /* This is a horrible layering violation; we should be doing this in
2775 * the connector/encoder ->prepare instead, but we don't always have
2776 * enough information there about the config to know whether it will
2777 * actually be necessary or just cause undesired flicker.
2778 */
2779 intel_disable_pch_ports(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002780
Jesse Barnes040484a2011-01-03 12:14:26 -08002781 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002782
Jesse Barnes6be4a602010-09-10 10:26:01 -07002783 if (HAS_PCH_CPT(dev)) {
2784 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01002785 reg = TRANS_DP_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08002788 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01002789 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002790
2791 /* disable DPLL_SEL */
2792 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002793 switch (pipe) {
2794 case 0:
2795 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2796 break;
2797 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07002798 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002799 break;
2800 case 2:
2801 /* FIXME: manage transcoder PLLs? */
2802 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2803 break;
2804 default:
2805 BUG(); /* wtf */
2806 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07002807 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002808 }
2809
2810 /* disable PCH DPLL */
Jesse Barnes92f25842011-01-04 15:09:34 -08002811 intel_disable_pch_pll(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002812
2813 /* Switch from PCDclk to Rawclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002817
2818 /* Disable CPU FDI TX PLL */
Chris Wilson5eddb702010-09-11 13:48:45 +01002819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002824 udelay(100);
2825
Chris Wilson5eddb702010-09-11 13:48:45 +01002826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002829
2830 /* Wait for the clocks to turn off. */
Chris Wilson5eddb702010-09-11 13:48:45 +01002831 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002832 udelay(100);
Chris Wilson6b383a72010-09-13 13:54:26 +01002833
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002834 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01002835 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01002836
2837 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01002838 intel_update_fbc(dev);
2839 intel_clear_scanline_wait(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01002840 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002841}
2842
2843static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2844{
2845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2846 int pipe = intel_crtc->pipe;
2847 int plane = intel_crtc->plane;
2848
Zhenyu Wang2c072452009-06-05 15:38:42 +08002849 /* XXX: When our outputs are all unaware of DPMS modes other than off
2850 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2851 */
2852 switch (mode) {
2853 case DRM_MODE_DPMS_ON:
2854 case DRM_MODE_DPMS_STANDBY:
2855 case DRM_MODE_DPMS_SUSPEND:
Chris Wilson868dc582010-08-07 11:01:31 +01002856 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002857 ironlake_crtc_enable(crtc);
Chris Wilson868dc582010-08-07 11:01:31 +01002858 break;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002859
Zhenyu Wang2c072452009-06-05 15:38:42 +08002860 case DRM_MODE_DPMS_OFF:
Chris Wilson868dc582010-08-07 11:01:31 +01002861 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002862 ironlake_crtc_disable(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002863 break;
2864 }
2865}
2866
Daniel Vetter02e792f2009-09-15 22:57:34 +02002867static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2868{
Daniel Vetter02e792f2009-09-15 22:57:34 +02002869 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01002870 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00002871 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02002872
Chris Wilson23f09ce2010-08-12 13:53:37 +01002873 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00002874 dev_priv->mm.interruptible = false;
2875 (void) intel_overlay_switch_off(intel_crtc->overlay);
2876 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01002877 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02002878 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02002879
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01002880 /* Let userspace switch the overlay on again. In most cases userspace
2881 * has to recompute where to put it anyway.
2882 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002883}
2884
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002885static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08002886{
2887 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002888 struct drm_i915_private *dev_priv = dev->dev_private;
2889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2890 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07002891 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08002892
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002893 if (intel_crtc->active)
2894 return;
2895
2896 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01002897 intel_update_watermarks(dev);
2898
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08002899 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002900 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002901 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002902
2903 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01002904 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002905
2906 /* Give the overlay scaler a chance to enable if it's on this pipe */
2907 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01002908 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002909}
2910
2911static void i9xx_crtc_disable(struct drm_crtc *crtc)
2912{
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2916 int pipe = intel_crtc->pipe;
2917 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002918
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002919 if (!intel_crtc->active)
2920 return;
2921
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002922 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002923 intel_crtc_wait_for_pending_flips(crtc);
2924 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002925 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01002926 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002927
2928 if (dev_priv->cfb_plane == plane &&
2929 dev_priv->display.disable_fbc)
2930 dev_priv->display.disable_fbc(dev);
2931
Jesse Barnesb24e7172011-01-04 15:09:30 -08002932 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002933 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08002934 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002935
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002936 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01002937 intel_update_fbc(dev);
2938 intel_update_watermarks(dev);
2939 intel_clear_scanline_wait(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002940}
2941
2942static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2943{
Jesse Barnes79e53942008-11-07 14:24:08 -08002944 /* XXX: When our outputs are all unaware of DPMS modes other than off
2945 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2946 */
2947 switch (mode) {
2948 case DRM_MODE_DPMS_ON:
2949 case DRM_MODE_DPMS_STANDBY:
2950 case DRM_MODE_DPMS_SUSPEND:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002951 i9xx_crtc_enable(crtc);
2952 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08002953 case DRM_MODE_DPMS_OFF:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002954 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08002955 break;
2956 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002957}
2958
2959/**
2960 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08002961 */
2962static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2963{
2964 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07002965 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002966 struct drm_i915_master_private *master_priv;
2967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2968 int pipe = intel_crtc->pipe;
2969 bool enabled;
2970
Chris Wilson032d2a02010-09-06 16:17:22 +01002971 if (intel_crtc->dpms_mode == mode)
2972 return;
2973
Chris Wilsondebcadd2010-08-07 11:01:33 +01002974 intel_crtc->dpms_mode = mode;
Chris Wilsondebcadd2010-08-07 11:01:33 +01002975
Jesse Barnese70236a2009-09-21 10:42:27 -07002976 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002977
2978 if (!dev->primary->master)
2979 return;
2980
2981 master_priv = dev->primary->master->driver_priv;
2982 if (!master_priv->sarea_priv)
2983 return;
2984
2985 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2986
2987 switch (pipe) {
2988 case 0:
2989 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2990 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2991 break;
2992 case 1:
2993 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2994 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2995 break;
2996 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002997 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08002998 break;
2999 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003000}
3001
Chris Wilsoncdd59982010-09-08 16:30:16 +01003002static void intel_crtc_disable(struct drm_crtc *crtc)
3003{
3004 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3005 struct drm_device *dev = crtc->dev;
3006
3007 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3008
3009 if (crtc->fb) {
3010 mutex_lock(&dev->struct_mutex);
3011 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3012 mutex_unlock(&dev->struct_mutex);
3013 }
3014}
3015
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003016/* Prepare for a mode set.
3017 *
3018 * Note we could be a lot smarter here. We need to figure out which outputs
3019 * will be enabled, which disabled (in short, how the config will changes)
3020 * and perform the minimum necessary steps to accomplish that, e.g. updating
3021 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3022 * panel fitting is in the proper state, etc.
3023 */
3024static void i9xx_crtc_prepare(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003025{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003026 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003027}
3028
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003029static void i9xx_crtc_commit(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003030{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003031 i9xx_crtc_enable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003032}
3033
3034static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3035{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003036 ironlake_crtc_disable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003037}
3038
3039static void ironlake_crtc_commit(struct drm_crtc *crtc)
3040{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003041 ironlake_crtc_enable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003042}
3043
3044void intel_encoder_prepare (struct drm_encoder *encoder)
3045{
3046 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3047 /* lvds has its own version of prepare see intel_lvds_prepare */
3048 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3049}
3050
3051void intel_encoder_commit (struct drm_encoder *encoder)
3052{
3053 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3054 /* lvds has its own version of commit see intel_lvds_commit */
3055 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3056}
3057
Chris Wilsonea5b2132010-08-04 13:50:23 +01003058void intel_encoder_destroy(struct drm_encoder *encoder)
3059{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003060 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003061
Chris Wilsonea5b2132010-08-04 13:50:23 +01003062 drm_encoder_cleanup(encoder);
3063 kfree(intel_encoder);
3064}
3065
Jesse Barnes79e53942008-11-07 14:24:08 -08003066static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3067 struct drm_display_mode *mode,
3068 struct drm_display_mode *adjusted_mode)
3069{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003070 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003071
Eric Anholtbad720f2009-10-22 16:11:14 -07003072 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003073 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003074 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3075 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003076 }
Chris Wilson89749352010-09-12 18:25:19 +01003077
3078 /* XXX some encoders set the crtcinfo, others don't.
3079 * Obviously we need some form of conflict resolution here...
3080 */
3081 if (adjusted_mode->crtc_htotal == 0)
3082 drm_mode_set_crtcinfo(adjusted_mode, 0);
3083
Jesse Barnes79e53942008-11-07 14:24:08 -08003084 return true;
3085}
3086
Jesse Barnese70236a2009-09-21 10:42:27 -07003087static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003088{
Jesse Barnese70236a2009-09-21 10:42:27 -07003089 return 400000;
3090}
Jesse Barnes79e53942008-11-07 14:24:08 -08003091
Jesse Barnese70236a2009-09-21 10:42:27 -07003092static int i915_get_display_clock_speed(struct drm_device *dev)
3093{
3094 return 333000;
3095}
Jesse Barnes79e53942008-11-07 14:24:08 -08003096
Jesse Barnese70236a2009-09-21 10:42:27 -07003097static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3098{
3099 return 200000;
3100}
Jesse Barnes79e53942008-11-07 14:24:08 -08003101
Jesse Barnese70236a2009-09-21 10:42:27 -07003102static int i915gm_get_display_clock_speed(struct drm_device *dev)
3103{
3104 u16 gcfgc = 0;
3105
3106 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3107
3108 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003109 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003110 else {
3111 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3112 case GC_DISPLAY_CLOCK_333_MHZ:
3113 return 333000;
3114 default:
3115 case GC_DISPLAY_CLOCK_190_200_MHZ:
3116 return 190000;
3117 }
3118 }
3119}
Jesse Barnes79e53942008-11-07 14:24:08 -08003120
Jesse Barnese70236a2009-09-21 10:42:27 -07003121static int i865_get_display_clock_speed(struct drm_device *dev)
3122{
3123 return 266000;
3124}
3125
3126static int i855_get_display_clock_speed(struct drm_device *dev)
3127{
3128 u16 hpllcc = 0;
3129 /* Assume that the hardware is in the high speed state. This
3130 * should be the default.
3131 */
3132 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3133 case GC_CLOCK_133_200:
3134 case GC_CLOCK_100_200:
3135 return 200000;
3136 case GC_CLOCK_166_250:
3137 return 250000;
3138 case GC_CLOCK_100_133:
3139 return 133000;
3140 }
3141
3142 /* Shouldn't happen */
3143 return 0;
3144}
3145
3146static int i830_get_display_clock_speed(struct drm_device *dev)
3147{
3148 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003149}
3150
Zhenyu Wang2c072452009-06-05 15:38:42 +08003151struct fdi_m_n {
3152 u32 tu;
3153 u32 gmch_m;
3154 u32 gmch_n;
3155 u32 link_m;
3156 u32 link_n;
3157};
3158
3159static void
3160fdi_reduce_ratio(u32 *num, u32 *den)
3161{
3162 while (*num > 0xffffff || *den > 0xffffff) {
3163 *num >>= 1;
3164 *den >>= 1;
3165 }
3166}
3167
Zhenyu Wang2c072452009-06-05 15:38:42 +08003168static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003169ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3170 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003171{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003172 m_n->tu = 64; /* default size */
3173
Chris Wilson22ed1112010-12-04 01:01:29 +00003174 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3175 m_n->gmch_m = bits_per_pixel * pixel_clock;
3176 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003177 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3178
Chris Wilson22ed1112010-12-04 01:01:29 +00003179 m_n->link_m = pixel_clock;
3180 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003181 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3182}
3183
3184
Shaohua Li7662c8b2009-06-26 11:23:55 +08003185struct intel_watermark_params {
3186 unsigned long fifo_size;
3187 unsigned long max_wm;
3188 unsigned long default_wm;
3189 unsigned long guard_size;
3190 unsigned long cacheline_size;
3191};
3192
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003193/* Pineview has different values for various configs */
Chris Wilsond2102462011-01-24 17:43:27 +00003194static const struct intel_watermark_params pineview_display_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003195 PINEVIEW_DISPLAY_FIFO,
3196 PINEVIEW_MAX_WM,
3197 PINEVIEW_DFT_WM,
3198 PINEVIEW_GUARD_WM,
3199 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003200};
Chris Wilsond2102462011-01-24 17:43:27 +00003201static const struct intel_watermark_params pineview_display_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003202 PINEVIEW_DISPLAY_FIFO,
3203 PINEVIEW_MAX_WM,
3204 PINEVIEW_DFT_HPLLOFF_WM,
3205 PINEVIEW_GUARD_WM,
3206 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003207};
Chris Wilsond2102462011-01-24 17:43:27 +00003208static const struct intel_watermark_params pineview_cursor_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003209 PINEVIEW_CURSOR_FIFO,
3210 PINEVIEW_CURSOR_MAX_WM,
3211 PINEVIEW_CURSOR_DFT_WM,
3212 PINEVIEW_CURSOR_GUARD_WM,
3213 PINEVIEW_FIFO_LINE_SIZE,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003214};
Chris Wilsond2102462011-01-24 17:43:27 +00003215static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003216 PINEVIEW_CURSOR_FIFO,
3217 PINEVIEW_CURSOR_MAX_WM,
3218 PINEVIEW_CURSOR_DFT_WM,
3219 PINEVIEW_CURSOR_GUARD_WM,
3220 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003221};
Chris Wilsond2102462011-01-24 17:43:27 +00003222static const struct intel_watermark_params g4x_wm_info = {
Jesse Barnes0e442c62009-10-19 10:09:33 +09003223 G4X_FIFO_SIZE,
3224 G4X_MAX_WM,
3225 G4X_MAX_WM,
3226 2,
3227 G4X_FIFO_LINE_SIZE,
3228};
Chris Wilsond2102462011-01-24 17:43:27 +00003229static const struct intel_watermark_params g4x_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003230 I965_CURSOR_FIFO,
3231 I965_CURSOR_MAX_WM,
3232 I965_CURSOR_DFT_WM,
3233 2,
3234 G4X_FIFO_LINE_SIZE,
3235};
Chris Wilsond2102462011-01-24 17:43:27 +00003236static const struct intel_watermark_params i965_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003237 I965_CURSOR_FIFO,
3238 I965_CURSOR_MAX_WM,
3239 I965_CURSOR_DFT_WM,
3240 2,
3241 I915_FIFO_LINE_SIZE,
3242};
Chris Wilsond2102462011-01-24 17:43:27 +00003243static const struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003244 I945_FIFO_SIZE,
3245 I915_MAX_WM,
3246 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003247 2,
3248 I915_FIFO_LINE_SIZE
3249};
Chris Wilsond2102462011-01-24 17:43:27 +00003250static const struct intel_watermark_params i915_wm_info = {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003251 I915_FIFO_SIZE,
3252 I915_MAX_WM,
3253 1,
3254 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003255 I915_FIFO_LINE_SIZE
3256};
Chris Wilsond2102462011-01-24 17:43:27 +00003257static const struct intel_watermark_params i855_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003258 I855GM_FIFO_SIZE,
3259 I915_MAX_WM,
3260 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003261 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003262 I830_FIFO_LINE_SIZE
3263};
Chris Wilsond2102462011-01-24 17:43:27 +00003264static const struct intel_watermark_params i830_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003265 I830_FIFO_SIZE,
3266 I915_MAX_WM,
3267 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003268 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003269 I830_FIFO_LINE_SIZE
3270};
3271
Chris Wilsond2102462011-01-24 17:43:27 +00003272static const struct intel_watermark_params ironlake_display_wm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003273 ILK_DISPLAY_FIFO,
3274 ILK_DISPLAY_MAXWM,
3275 ILK_DISPLAY_DFTWM,
3276 2,
3277 ILK_FIFO_LINE_SIZE
3278};
Chris Wilsond2102462011-01-24 17:43:27 +00003279static const struct intel_watermark_params ironlake_cursor_wm_info = {
Zhao Yakuic936f442010-06-12 14:32:26 +08003280 ILK_CURSOR_FIFO,
3281 ILK_CURSOR_MAXWM,
3282 ILK_CURSOR_DFTWM,
3283 2,
3284 ILK_FIFO_LINE_SIZE
3285};
Chris Wilsond2102462011-01-24 17:43:27 +00003286static const struct intel_watermark_params ironlake_display_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003287 ILK_DISPLAY_SR_FIFO,
3288 ILK_DISPLAY_MAX_SRWM,
3289 ILK_DISPLAY_DFT_SRWM,
3290 2,
3291 ILK_FIFO_LINE_SIZE
3292};
Chris Wilsond2102462011-01-24 17:43:27 +00003293static const struct intel_watermark_params ironlake_cursor_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003294 ILK_CURSOR_SR_FIFO,
3295 ILK_CURSOR_MAX_SRWM,
3296 ILK_CURSOR_DFT_SRWM,
3297 2,
3298 ILK_FIFO_LINE_SIZE
3299};
3300
Chris Wilsond2102462011-01-24 17:43:27 +00003301static const struct intel_watermark_params sandybridge_display_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003302 SNB_DISPLAY_FIFO,
3303 SNB_DISPLAY_MAXWM,
3304 SNB_DISPLAY_DFTWM,
3305 2,
3306 SNB_FIFO_LINE_SIZE
3307};
Chris Wilsond2102462011-01-24 17:43:27 +00003308static const struct intel_watermark_params sandybridge_cursor_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003309 SNB_CURSOR_FIFO,
3310 SNB_CURSOR_MAXWM,
3311 SNB_CURSOR_DFTWM,
3312 2,
3313 SNB_FIFO_LINE_SIZE
3314};
Chris Wilsond2102462011-01-24 17:43:27 +00003315static const struct intel_watermark_params sandybridge_display_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003316 SNB_DISPLAY_SR_FIFO,
3317 SNB_DISPLAY_MAX_SRWM,
3318 SNB_DISPLAY_DFT_SRWM,
3319 2,
3320 SNB_FIFO_LINE_SIZE
3321};
Chris Wilsond2102462011-01-24 17:43:27 +00003322static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003323 SNB_CURSOR_SR_FIFO,
3324 SNB_CURSOR_MAX_SRWM,
3325 SNB_CURSOR_DFT_SRWM,
3326 2,
3327 SNB_FIFO_LINE_SIZE
3328};
3329
3330
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003331/**
3332 * intel_calculate_wm - calculate watermark level
3333 * @clock_in_khz: pixel clock
3334 * @wm: chip FIFO params
3335 * @pixel_size: display pixel size
3336 * @latency_ns: memory latency for the platform
3337 *
3338 * Calculate the watermark level (the level at which the display plane will
3339 * start fetching from memory again). Each chip has a different display
3340 * FIFO size and allocation, so the caller needs to figure that out and pass
3341 * in the correct intel_watermark_params structure.
3342 *
3343 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3344 * on the pixel size. When it reaches the watermark level, it'll start
3345 * fetching FIFO line sized based chunks from memory until the FIFO fills
3346 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3347 * will occur, and a display engine hang could result.
3348 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003349static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
Chris Wilsond2102462011-01-24 17:43:27 +00003350 const struct intel_watermark_params *wm,
3351 int fifo_size,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003352 int pixel_size,
3353 unsigned long latency_ns)
3354{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003355 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003356
Jesse Barnesd6604672009-09-11 12:25:56 -07003357 /*
3358 * Note: we need to make sure we don't overflow for various clock &
3359 * latency values.
3360 * clocks go from a few thousand to several hundred thousand.
3361 * latency is usually a few thousand
3362 */
3363 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3364 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01003365 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003366
Joe Perchesbbb0aef2011-04-17 20:35:52 -07003367 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003368
Chris Wilsond2102462011-01-24 17:43:27 +00003369 wm_size = fifo_size - (entries_required + wm->guard_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003370
Joe Perchesbbb0aef2011-04-17 20:35:52 -07003371 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003372
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003373 /* Don't promote wm_size to unsigned... */
3374 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003375 wm_size = wm->max_wm;
Chris Wilsonc3add4b2010-09-08 09:14:08 +01003376 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003377 wm_size = wm->default_wm;
3378 return wm_size;
3379}
3380
3381struct cxsr_latency {
3382 int is_desktop;
Li Peng95534262010-05-18 18:58:44 +08003383 int is_ddr3;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003384 unsigned long fsb_freq;
3385 unsigned long mem_freq;
3386 unsigned long display_sr;
3387 unsigned long display_hpll_disable;
3388 unsigned long cursor_sr;
3389 unsigned long cursor_hpll_disable;
3390};
3391
Chris Wilson403c89f2010-08-04 15:25:31 +01003392static const struct cxsr_latency cxsr_latency_table[] = {
Li Peng95534262010-05-18 18:58:44 +08003393 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3394 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3395 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3396 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3397 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003398
Li Peng95534262010-05-18 18:58:44 +08003399 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3400 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3401 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3402 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3403 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003404
Li Peng95534262010-05-18 18:58:44 +08003405 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3406 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3407 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3408 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3409 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003410
Li Peng95534262010-05-18 18:58:44 +08003411 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3412 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3413 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3414 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3415 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003416
Li Peng95534262010-05-18 18:58:44 +08003417 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3418 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3419 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3420 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3421 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003422
Li Peng95534262010-05-18 18:58:44 +08003423 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3424 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3425 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3426 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3427 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003428};
3429
Chris Wilson403c89f2010-08-04 15:25:31 +01003430static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3431 int is_ddr3,
3432 int fsb,
3433 int mem)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003434{
Chris Wilson403c89f2010-08-04 15:25:31 +01003435 const struct cxsr_latency *latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003436 int i;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003437
3438 if (fsb == 0 || mem == 0)
3439 return NULL;
3440
3441 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3442 latency = &cxsr_latency_table[i];
3443 if (is_desktop == latency->is_desktop &&
Li Peng95534262010-05-18 18:58:44 +08003444 is_ddr3 == latency->is_ddr3 &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303445 fsb == latency->fsb_freq && mem == latency->mem_freq)
3446 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003447 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303448
Zhao Yakui28c97732009-10-09 11:39:41 +08003449 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303450
3451 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003452}
3453
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003454static void pineview_disable_cxsr(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003455{
3456 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003457
3458 /* deactivate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003459 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003460}
3461
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07003462/*
3463 * Latency for FIFO fetches is dependent on several factors:
3464 * - memory configuration (speed, channels)
3465 * - chipset
3466 * - current MCH state
3467 * It can be fairly high in some situations, so here we assume a fairly
3468 * pessimal value. It's a tradeoff between extra memory fetches (if we
3469 * set this value too high, the FIFO will fetch frequently to stay full)
3470 * and power consumption (set it too low to save power and we might see
3471 * FIFO underruns and display "flicker").
3472 *
3473 * A value of 5us seems to be a good balance; safe for very low end
3474 * platforms but not overly aggressive on lower latency configs.
3475 */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003476static const int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003477
Jesse Barnese70236a2009-09-21 10:42:27 -07003478static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003479{
3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 uint32_t dsparb = I915_READ(DSPARB);
3482 int size;
3483
Chris Wilson8de9b312010-07-19 19:59:52 +01003484 size = dsparb & 0x7f;
3485 if (plane)
3486 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003487
Zhao Yakui28c97732009-10-09 11:39:41 +08003488 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003489 plane ? "B" : "A", size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003490
3491 return size;
3492}
Shaohua Li7662c8b2009-06-26 11:23:55 +08003493
Jesse Barnese70236a2009-09-21 10:42:27 -07003494static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3495{
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 uint32_t dsparb = I915_READ(DSPARB);
3498 int size;
3499
Chris Wilson8de9b312010-07-19 19:59:52 +01003500 size = dsparb & 0x1ff;
3501 if (plane)
3502 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
Jesse Barnese70236a2009-09-21 10:42:27 -07003503 size >>= 1; /* Convert to cachelines */
3504
Zhao Yakui28c97732009-10-09 11:39:41 +08003505 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003506 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003507
3508 return size;
3509}
3510
3511static int i845_get_fifo_size(struct drm_device *dev, int plane)
3512{
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3514 uint32_t dsparb = I915_READ(DSPARB);
3515 int size;
3516
3517 size = dsparb & 0x7f;
3518 size >>= 2; /* Convert to cachelines */
3519
Zhao Yakui28c97732009-10-09 11:39:41 +08003520 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003521 plane ? "B" : "A",
3522 size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003523
3524 return size;
3525}
3526
3527static int i830_get_fifo_size(struct drm_device *dev, int plane)
3528{
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 uint32_t dsparb = I915_READ(DSPARB);
3531 int size;
3532
3533 size = dsparb & 0x7f;
3534 size >>= 1; /* Convert to cachelines */
3535
Zhao Yakui28c97732009-10-09 11:39:41 +08003536 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003537 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003538
3539 return size;
3540}
3541
Chris Wilsond2102462011-01-24 17:43:27 +00003542static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3543{
3544 struct drm_crtc *crtc, *enabled = NULL;
3545
3546 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3547 if (crtc->enabled && crtc->fb) {
3548 if (enabled)
3549 return NULL;
3550 enabled = crtc;
3551 }
3552 }
3553
3554 return enabled;
3555}
3556
3557static void pineview_update_wm(struct drm_device *dev)
Zhao Yakuid4294342010-03-22 22:45:36 +08003558{
3559 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003560 struct drm_crtc *crtc;
Chris Wilson403c89f2010-08-04 15:25:31 +01003561 const struct cxsr_latency *latency;
Zhao Yakuid4294342010-03-22 22:45:36 +08003562 u32 reg;
3563 unsigned long wm;
Zhao Yakuid4294342010-03-22 22:45:36 +08003564
Chris Wilson403c89f2010-08-04 15:25:31 +01003565 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
Li Peng95534262010-05-18 18:58:44 +08003566 dev_priv->fsb_freq, dev_priv->mem_freq);
Zhao Yakuid4294342010-03-22 22:45:36 +08003567 if (!latency) {
3568 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3569 pineview_disable_cxsr(dev);
3570 return;
3571 }
3572
Chris Wilsond2102462011-01-24 17:43:27 +00003573 crtc = single_enabled_crtc(dev);
3574 if (crtc) {
3575 int clock = crtc->mode.clock;
3576 int pixel_size = crtc->fb->bits_per_pixel / 8;
Zhao Yakuid4294342010-03-22 22:45:36 +08003577
3578 /* Display SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003579 wm = intel_calculate_wm(clock, &pineview_display_wm,
3580 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003581 pixel_size, latency->display_sr);
3582 reg = I915_READ(DSPFW1);
3583 reg &= ~DSPFW_SR_MASK;
3584 reg |= wm << DSPFW_SR_SHIFT;
3585 I915_WRITE(DSPFW1, reg);
3586 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3587
3588 /* cursor SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003589 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3590 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003591 pixel_size, latency->cursor_sr);
3592 reg = I915_READ(DSPFW3);
3593 reg &= ~DSPFW_CURSOR_SR_MASK;
3594 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3595 I915_WRITE(DSPFW3, reg);
3596
3597 /* Display HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003598 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3599 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003600 pixel_size, latency->display_hpll_disable);
3601 reg = I915_READ(DSPFW3);
3602 reg &= ~DSPFW_HPLL_SR_MASK;
3603 reg |= wm & DSPFW_HPLL_SR_MASK;
3604 I915_WRITE(DSPFW3, reg);
3605
3606 /* cursor HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003607 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3608 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003609 pixel_size, latency->cursor_hpll_disable);
3610 reg = I915_READ(DSPFW3);
3611 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3612 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3613 I915_WRITE(DSPFW3, reg);
3614 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3615
3616 /* activate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003617 I915_WRITE(DSPFW3,
3618 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
Zhao Yakuid4294342010-03-22 22:45:36 +08003619 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3620 } else {
3621 pineview_disable_cxsr(dev);
3622 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3623 }
3624}
3625
Chris Wilson417ae142011-01-19 15:04:42 +00003626static bool g4x_compute_wm0(struct drm_device *dev,
3627 int plane,
3628 const struct intel_watermark_params *display,
3629 int display_latency_ns,
3630 const struct intel_watermark_params *cursor,
3631 int cursor_latency_ns,
3632 int *plane_wm,
3633 int *cursor_wm)
Jesse Barnes652c3932009-08-17 13:31:43 -07003634{
Chris Wilson417ae142011-01-19 15:04:42 +00003635 struct drm_crtc *crtc;
3636 int htotal, hdisplay, clock, pixel_size;
3637 int line_time_us, line_count;
3638 int entries, tlb_miss;
Jesse Barnes652c3932009-08-17 13:31:43 -07003639
Chris Wilson417ae142011-01-19 15:04:42 +00003640 crtc = intel_get_crtc_for_plane(dev, plane);
Chris Wilson5c72d062011-04-13 09:28:23 +01003641 if (crtc->fb == NULL || !crtc->enabled) {
3642 *cursor_wm = cursor->guard_size;
3643 *plane_wm = display->guard_size;
Chris Wilson417ae142011-01-19 15:04:42 +00003644 return false;
Chris Wilson5c72d062011-04-13 09:28:23 +01003645 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003646
Chris Wilson417ae142011-01-19 15:04:42 +00003647 htotal = crtc->mode.htotal;
3648 hdisplay = crtc->mode.hdisplay;
3649 clock = crtc->mode.clock;
3650 pixel_size = crtc->fb->bits_per_pixel / 8;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003651
Chris Wilson417ae142011-01-19 15:04:42 +00003652 /* Use the small buffer method to calculate plane watermark */
3653 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3654 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3655 if (tlb_miss > 0)
3656 entries += tlb_miss;
3657 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3658 *plane_wm = entries + display->guard_size;
3659 if (*plane_wm > (int)display->max_wm)
3660 *plane_wm = display->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003661
Chris Wilson417ae142011-01-19 15:04:42 +00003662 /* Use the large buffer method to calculate cursor watermark */
3663 line_time_us = ((htotal * 1000) / clock);
3664 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3665 entries = line_count * 64 * pixel_size;
3666 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3667 if (tlb_miss > 0)
3668 entries += tlb_miss;
3669 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3670 *cursor_wm = entries + cursor->guard_size;
3671 if (*cursor_wm > (int)cursor->max_wm)
3672 *cursor_wm = (int)cursor->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003673
Chris Wilson417ae142011-01-19 15:04:42 +00003674 return true;
3675}
Jesse Barnes0e442c62009-10-19 10:09:33 +09003676
Chris Wilson417ae142011-01-19 15:04:42 +00003677/*
3678 * Check the wm result.
3679 *
3680 * If any calculated watermark values is larger than the maximum value that
3681 * can be programmed into the associated watermark register, that watermark
3682 * must be disabled.
3683 */
3684static bool g4x_check_srwm(struct drm_device *dev,
3685 int display_wm, int cursor_wm,
3686 const struct intel_watermark_params *display,
3687 const struct intel_watermark_params *cursor)
3688{
3689 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3690 display_wm, cursor_wm);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003691
Chris Wilson417ae142011-01-19 15:04:42 +00003692 if (display_wm > display->max_wm) {
Joe Perchesbbb0aef2011-04-17 20:35:52 -07003693 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
Chris Wilson417ae142011-01-19 15:04:42 +00003694 display_wm, display->max_wm);
3695 return false;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003696 }
3697
Chris Wilson417ae142011-01-19 15:04:42 +00003698 if (cursor_wm > cursor->max_wm) {
Joe Perchesbbb0aef2011-04-17 20:35:52 -07003699 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
Chris Wilson417ae142011-01-19 15:04:42 +00003700 cursor_wm, cursor->max_wm);
3701 return false;
3702 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003703
Chris Wilson417ae142011-01-19 15:04:42 +00003704 if (!(display_wm || cursor_wm)) {
3705 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3706 return false;
3707 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003708
Chris Wilson417ae142011-01-19 15:04:42 +00003709 return true;
3710}
3711
3712static bool g4x_compute_srwm(struct drm_device *dev,
Chris Wilsond2102462011-01-24 17:43:27 +00003713 int plane,
3714 int latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00003715 const struct intel_watermark_params *display,
3716 const struct intel_watermark_params *cursor,
3717 int *display_wm, int *cursor_wm)
3718{
Chris Wilsond2102462011-01-24 17:43:27 +00003719 struct drm_crtc *crtc;
3720 int hdisplay, htotal, pixel_size, clock;
Chris Wilson417ae142011-01-19 15:04:42 +00003721 unsigned long line_time_us;
3722 int line_count, line_size;
3723 int small, large;
3724 int entries;
3725
3726 if (!latency_ns) {
3727 *display_wm = *cursor_wm = 0;
3728 return false;
3729 }
3730
Chris Wilsond2102462011-01-24 17:43:27 +00003731 crtc = intel_get_crtc_for_plane(dev, plane);
3732 hdisplay = crtc->mode.hdisplay;
3733 htotal = crtc->mode.htotal;
3734 clock = crtc->mode.clock;
3735 pixel_size = crtc->fb->bits_per_pixel / 8;
3736
Chris Wilson417ae142011-01-19 15:04:42 +00003737 line_time_us = (htotal * 1000) / clock;
3738 line_count = (latency_ns / line_time_us + 1000) / 1000;
3739 line_size = hdisplay * pixel_size;
3740
3741 /* Use the minimum of the small and large buffer method for primary */
3742 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3743 large = line_count * line_size;
3744
3745 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3746 *display_wm = entries + display->guard_size;
3747
3748 /* calculate the self-refresh watermark for display cursor */
3749 entries = line_count * pixel_size * 64;
3750 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3751 *cursor_wm = entries + cursor->guard_size;
3752
3753 return g4x_check_srwm(dev,
3754 *display_wm, *cursor_wm,
3755 display, cursor);
3756}
3757
Yuanhan Liu7ccb4a52011-03-18 07:37:35 +00003758#define single_plane_enabled(mask) is_power_of_2(mask)
Chris Wilsond2102462011-01-24 17:43:27 +00003759
3760static void g4x_update_wm(struct drm_device *dev)
Chris Wilson417ae142011-01-19 15:04:42 +00003761{
3762 static const int sr_latency_ns = 12000;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00003765 int plane_sr, cursor_sr;
3766 unsigned int enabled = 0;
Chris Wilson417ae142011-01-19 15:04:42 +00003767
3768 if (g4x_compute_wm0(dev, 0,
3769 &g4x_wm_info, latency_ns,
3770 &g4x_cursor_wm_info, latency_ns,
3771 &planea_wm, &cursora_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00003772 enabled |= 1;
Chris Wilson417ae142011-01-19 15:04:42 +00003773
3774 if (g4x_compute_wm0(dev, 1,
3775 &g4x_wm_info, latency_ns,
3776 &g4x_cursor_wm_info, latency_ns,
3777 &planeb_wm, &cursorb_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00003778 enabled |= 2;
Chris Wilson417ae142011-01-19 15:04:42 +00003779
3780 plane_sr = cursor_sr = 0;
Chris Wilsond2102462011-01-24 17:43:27 +00003781 if (single_plane_enabled(enabled) &&
3782 g4x_compute_srwm(dev, ffs(enabled) - 1,
3783 sr_latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00003784 &g4x_wm_info,
3785 &g4x_cursor_wm_info,
3786 &plane_sr, &cursor_sr))
3787 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3788 else
3789 I915_WRITE(FW_BLC_SELF,
3790 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3791
Chris Wilson308977a2011-02-02 10:41:20 +00003792 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3793 planea_wm, cursora_wm,
3794 planeb_wm, cursorb_wm,
3795 plane_sr, cursor_sr);
Chris Wilson417ae142011-01-19 15:04:42 +00003796
3797 I915_WRITE(DSPFW1,
3798 (plane_sr << DSPFW_SR_SHIFT) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003799 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
Chris Wilson417ae142011-01-19 15:04:42 +00003800 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3801 planea_wm);
3802 I915_WRITE(DSPFW2,
3803 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003804 (cursora_wm << DSPFW_CURSORA_SHIFT));
3805 /* HPLL off in SR has some issues on G4x... disable it */
Chris Wilson417ae142011-01-19 15:04:42 +00003806 I915_WRITE(DSPFW3,
3807 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003808 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Jesse Barnes652c3932009-08-17 13:31:43 -07003809}
3810
Chris Wilsond2102462011-01-24 17:43:27 +00003811static void i965_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003812{
3813 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003814 struct drm_crtc *crtc;
3815 int srwm = 1;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003816 int cursor_sr = 16;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003817
Jesse Barnes1dc75462009-10-19 10:08:17 +09003818 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00003819 crtc = single_enabled_crtc(dev);
3820 if (crtc) {
Jesse Barnes1dc75462009-10-19 10:08:17 +09003821 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003822 static const int sr_latency_ns = 12000;
Chris Wilsond2102462011-01-24 17:43:27 +00003823 int clock = crtc->mode.clock;
3824 int htotal = crtc->mode.htotal;
3825 int hdisplay = crtc->mode.hdisplay;
3826 int pixel_size = crtc->fb->bits_per_pixel / 8;
3827 unsigned long line_time_us;
3828 int entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003829
Chris Wilsond2102462011-01-24 17:43:27 +00003830 line_time_us = ((htotal * 1000) / clock);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003831
3832 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00003833 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3834 pixel_size * hdisplay;
3835 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
Chris Wilsond2102462011-01-24 17:43:27 +00003836 srwm = I965_FIFO_SIZE - entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003837 if (srwm < 0)
3838 srwm = 1;
Zhao Yakui1b07e042010-06-12 14:32:24 +08003839 srwm &= 0x1ff;
Chris Wilson308977a2011-02-02 10:41:20 +00003840 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3841 entries, srwm);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003842
Chris Wilsond2102462011-01-24 17:43:27 +00003843 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Chris Wilson5eddb702010-09-11 13:48:45 +01003844 pixel_size * 64;
Chris Wilsond2102462011-01-24 17:43:27 +00003845 entries = DIV_ROUND_UP(entries,
Chris Wilson8de9b312010-07-19 19:59:52 +01003846 i965_cursor_wm_info.cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003847 cursor_sr = i965_cursor_wm_info.fifo_size -
Chris Wilsond2102462011-01-24 17:43:27 +00003848 (entries + i965_cursor_wm_info.guard_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003849
3850 if (cursor_sr > i965_cursor_wm_info.max_wm)
3851 cursor_sr = i965_cursor_wm_info.max_wm;
3852
3853 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3854 "cursor %d\n", srwm, cursor_sr);
3855
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003856 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003857 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05303858 } else {
3859 /* Turn off self refresh if both pipes are enabled */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003860 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003861 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3862 & ~FW_BLC_SELF_EN);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003863 }
3864
3865 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3866 srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003867
3868 /* 965 has limitations... */
Chris Wilson417ae142011-01-19 15:04:42 +00003869 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3870 (8 << 16) | (8 << 8) | (8 << 0));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003871 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003872 /* update cursor SR watermark */
3873 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003874}
3875
Chris Wilsond2102462011-01-24 17:43:27 +00003876static void i9xx_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003877{
3878 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003879 const struct intel_watermark_params *wm_info;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003880 uint32_t fwater_lo;
3881 uint32_t fwater_hi;
Chris Wilsond2102462011-01-24 17:43:27 +00003882 int cwm, srwm = 1;
3883 int fifo_size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003884 int planea_wm, planeb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00003885 struct drm_crtc *crtc, *enabled = NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003886
Chris Wilson72557b42011-01-31 10:29:55 +00003887 if (IS_I945GM(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00003888 wm_info = &i945_wm_info;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003889 else if (!IS_GEN2(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00003890 wm_info = &i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003891 else
Chris Wilsond2102462011-01-24 17:43:27 +00003892 wm_info = &i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003893
Chris Wilsond2102462011-01-24 17:43:27 +00003894 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3895 crtc = intel_get_crtc_for_plane(dev, 0);
3896 if (crtc->enabled && crtc->fb) {
3897 planea_wm = intel_calculate_wm(crtc->mode.clock,
3898 wm_info, fifo_size,
3899 crtc->fb->bits_per_pixel / 8,
3900 latency_ns);
3901 enabled = crtc;
3902 } else
3903 planea_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003904
Chris Wilsond2102462011-01-24 17:43:27 +00003905 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3906 crtc = intel_get_crtc_for_plane(dev, 1);
3907 if (crtc->enabled && crtc->fb) {
3908 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3909 wm_info, fifo_size,
3910 crtc->fb->bits_per_pixel / 8,
3911 latency_ns);
3912 if (enabled == NULL)
3913 enabled = crtc;
3914 else
3915 enabled = NULL;
3916 } else
3917 planeb_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003918
Zhao Yakui28c97732009-10-09 11:39:41 +08003919 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003920
3921 /*
3922 * Overlay gets an aggressive default since video jitter is bad.
3923 */
3924 cwm = 2;
3925
Alexander Lam18b21902011-01-03 13:28:56 -05003926 /* Play safe and disable self-refresh before adjusting watermarks. */
3927 if (IS_I945G(dev) || IS_I945GM(dev))
3928 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3929 else if (IS_I915GM(dev))
3930 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3931
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003932 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00003933 if (HAS_FW_BLC(dev) && enabled) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003934 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003935 static const int sr_latency_ns = 6000;
Chris Wilsond2102462011-01-24 17:43:27 +00003936 int clock = enabled->mode.clock;
3937 int htotal = enabled->mode.htotal;
3938 int hdisplay = enabled->mode.hdisplay;
3939 int pixel_size = enabled->fb->bits_per_pixel / 8;
3940 unsigned long line_time_us;
3941 int entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003942
Chris Wilsond2102462011-01-24 17:43:27 +00003943 line_time_us = (htotal * 1000) / clock;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003944
3945 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00003946 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3947 pixel_size * hdisplay;
3948 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3949 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3950 srwm = wm_info->fifo_size - entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003951 if (srwm < 0)
3952 srwm = 1;
Li Pengee980b82010-01-27 19:01:11 +08003953
3954 if (IS_I945G(dev) || IS_I945GM(dev))
Alexander Lam18b21902011-01-03 13:28:56 -05003955 I915_WRITE(FW_BLC_SELF,
3956 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3957 else if (IS_I915GM(dev))
Li Pengee980b82010-01-27 19:01:11 +08003958 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003959 }
3960
Zhao Yakui28c97732009-10-09 11:39:41 +08003961 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01003962 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003963
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003964 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3965 fwater_hi = (cwm & 0x1f);
3966
3967 /* Set request length to 8 cachelines per fetch */
3968 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3969 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003970
3971 I915_WRITE(FW_BLC, fwater_lo);
3972 I915_WRITE(FW_BLC2, fwater_hi);
Alexander Lam18b21902011-01-03 13:28:56 -05003973
Chris Wilsond2102462011-01-24 17:43:27 +00003974 if (HAS_FW_BLC(dev)) {
3975 if (enabled) {
3976 if (IS_I945G(dev) || IS_I945GM(dev))
3977 I915_WRITE(FW_BLC_SELF,
3978 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3979 else if (IS_I915GM(dev))
3980 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3981 DRM_DEBUG_KMS("memory self refresh enabled\n");
3982 } else
3983 DRM_DEBUG_KMS("memory self refresh disabled\n");
3984 }
Shaohua Li7662c8b2009-06-26 11:23:55 +08003985}
3986
Chris Wilsond2102462011-01-24 17:43:27 +00003987static void i830_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003988{
3989 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003990 struct drm_crtc *crtc;
3991 uint32_t fwater_lo;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003992 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003993
Chris Wilsond2102462011-01-24 17:43:27 +00003994 crtc = single_enabled_crtc(dev);
3995 if (crtc == NULL)
3996 return;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003997
Chris Wilsond2102462011-01-24 17:43:27 +00003998 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3999 dev_priv->display.get_fifo_size(dev, 0),
4000 crtc->fb->bits_per_pixel / 8,
4001 latency_ns);
4002 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesf3601322009-07-22 12:54:59 -07004003 fwater_lo |= (3<<8) | planea_wm;
4004
Zhao Yakui28c97732009-10-09 11:39:41 +08004005 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004006
4007 I915_WRITE(FW_BLC, fwater_lo);
4008}
4009
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004010#define ILK_LP0_PLANE_LATENCY 700
Zhao Yakuic936f442010-06-12 14:32:26 +08004011#define ILK_LP0_CURSOR_LATENCY 1300
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004012
Jesse Barnesb79d4992010-12-21 13:10:23 -08004013/*
4014 * Check the wm result.
4015 *
4016 * If any calculated watermark values is larger than the maximum value that
4017 * can be programmed into the associated watermark register, that watermark
4018 * must be disabled.
4019 */
4020static bool ironlake_check_srwm(struct drm_device *dev, int level,
4021 int fbc_wm, int display_wm, int cursor_wm,
4022 const struct intel_watermark_params *display,
4023 const struct intel_watermark_params *cursor)
4024{
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026
4027 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4028 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4029
4030 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4031 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4032 fbc_wm, SNB_FBC_MAX_SRWM, level);
4033
4034 /* fbc has it's own way to disable FBC WM */
4035 I915_WRITE(DISP_ARB_CTL,
4036 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4037 return false;
4038 }
4039
4040 if (display_wm > display->max_wm) {
4041 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4042 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4043 return false;
4044 }
4045
4046 if (cursor_wm > cursor->max_wm) {
4047 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4048 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4049 return false;
4050 }
4051
4052 if (!(fbc_wm || display_wm || cursor_wm)) {
4053 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4054 return false;
4055 }
4056
4057 return true;
4058}
4059
4060/*
4061 * Compute watermark values of WM[1-3],
4062 */
Chris Wilsond2102462011-01-24 17:43:27 +00004063static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4064 int latency_ns,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004065 const struct intel_watermark_params *display,
4066 const struct intel_watermark_params *cursor,
4067 int *fbc_wm, int *display_wm, int *cursor_wm)
4068{
Chris Wilsond2102462011-01-24 17:43:27 +00004069 struct drm_crtc *crtc;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004070 unsigned long line_time_us;
Chris Wilsond2102462011-01-24 17:43:27 +00004071 int hdisplay, htotal, pixel_size, clock;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004072 int line_count, line_size;
4073 int small, large;
4074 int entries;
4075
4076 if (!latency_ns) {
4077 *fbc_wm = *display_wm = *cursor_wm = 0;
4078 return false;
4079 }
4080
Chris Wilsond2102462011-01-24 17:43:27 +00004081 crtc = intel_get_crtc_for_plane(dev, plane);
4082 hdisplay = crtc->mode.hdisplay;
4083 htotal = crtc->mode.htotal;
4084 clock = crtc->mode.clock;
4085 pixel_size = crtc->fb->bits_per_pixel / 8;
4086
Jesse Barnesb79d4992010-12-21 13:10:23 -08004087 line_time_us = (htotal * 1000) / clock;
4088 line_count = (latency_ns / line_time_us + 1000) / 1000;
4089 line_size = hdisplay * pixel_size;
4090
4091 /* Use the minimum of the small and large buffer method for primary */
4092 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4093 large = line_count * line_size;
4094
4095 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4096 *display_wm = entries + display->guard_size;
4097
4098 /*
4099 * Spec says:
4100 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4101 */
4102 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4103
4104 /* calculate the self-refresh watermark for display cursor */
4105 entries = line_count * pixel_size * 64;
4106 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4107 *cursor_wm = entries + cursor->guard_size;
4108
4109 return ironlake_check_srwm(dev, level,
4110 *fbc_wm, *display_wm, *cursor_wm,
4111 display, cursor);
4112}
4113
Chris Wilsond2102462011-01-24 17:43:27 +00004114static void ironlake_update_wm(struct drm_device *dev)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004115{
4116 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004117 int fbc_wm, plane_wm, cursor_wm;
4118 unsigned int enabled;
Zhao Yakuic936f442010-06-12 14:32:26 +08004119
Chris Wilson4ed765f2010-09-11 10:46:47 +01004120 enabled = 0;
Chris Wilson9f405102011-05-12 22:17:14 +01004121 if (g4x_compute_wm0(dev, 0,
4122 &ironlake_display_wm_info,
4123 ILK_LP0_PLANE_LATENCY,
4124 &ironlake_cursor_wm_info,
4125 ILK_LP0_CURSOR_LATENCY,
4126 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004127 I915_WRITE(WM0_PIPEA_ILK,
4128 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4129 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4130 " plane %d, " "cursor: %d\n",
4131 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004132 enabled |= 1;
Zhao Yakuic936f442010-06-12 14:32:26 +08004133 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004134
Chris Wilson9f405102011-05-12 22:17:14 +01004135 if (g4x_compute_wm0(dev, 1,
4136 &ironlake_display_wm_info,
4137 ILK_LP0_PLANE_LATENCY,
4138 &ironlake_cursor_wm_info,
4139 ILK_LP0_CURSOR_LATENCY,
4140 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004141 I915_WRITE(WM0_PIPEB_ILK,
4142 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4143 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4144 " plane %d, cursor: %d\n",
4145 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004146 enabled |= 2;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004147 }
4148
4149 /*
4150 * Calculate and update the self-refresh watermark only when one
4151 * display plane is used.
4152 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004153 I915_WRITE(WM3_LP_ILK, 0);
4154 I915_WRITE(WM2_LP_ILK, 0);
4155 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004156
Chris Wilsond2102462011-01-24 17:43:27 +00004157 if (!single_plane_enabled(enabled))
Jesse Barnesb79d4992010-12-21 13:10:23 -08004158 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004159 enabled = ffs(enabled) - 1;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004160
Jesse Barnesb79d4992010-12-21 13:10:23 -08004161 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004162 if (!ironlake_compute_srwm(dev, 1, enabled,
4163 ILK_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004164 &ironlake_display_srwm_info,
4165 &ironlake_cursor_srwm_info,
4166 &fbc_wm, &plane_wm, &cursor_wm))
4167 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004168
Jesse Barnesb79d4992010-12-21 13:10:23 -08004169 I915_WRITE(WM1_LP_ILK,
4170 WM1_LP_SR_EN |
4171 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4172 (fbc_wm << WM1_LP_FBC_SHIFT) |
4173 (plane_wm << WM1_LP_SR_SHIFT) |
4174 cursor_wm);
Chris Wilson4ed765f2010-09-11 10:46:47 +01004175
Jesse Barnesb79d4992010-12-21 13:10:23 -08004176 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004177 if (!ironlake_compute_srwm(dev, 2, enabled,
4178 ILK_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004179 &ironlake_display_srwm_info,
4180 &ironlake_cursor_srwm_info,
4181 &fbc_wm, &plane_wm, &cursor_wm))
4182 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004183
Jesse Barnesb79d4992010-12-21 13:10:23 -08004184 I915_WRITE(WM2_LP_ILK,
4185 WM2_LP_EN |
4186 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4187 (fbc_wm << WM1_LP_FBC_SHIFT) |
4188 (plane_wm << WM1_LP_SR_SHIFT) |
4189 cursor_wm);
Yuanhan Liu13982612010-12-15 15:42:31 +08004190
4191 /*
Jesse Barnesb79d4992010-12-21 13:10:23 -08004192 * WM3 is unsupported on ILK, probably because we don't have latency
4193 * data for that power state
Yuanhan Liu13982612010-12-15 15:42:31 +08004194 */
Yuanhan Liu13982612010-12-15 15:42:31 +08004195}
4196
Chris Wilsond2102462011-01-24 17:43:27 +00004197static void sandybridge_update_wm(struct drm_device *dev)
Yuanhan Liu13982612010-12-15 15:42:31 +08004198{
4199 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004200 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
Chris Wilsond2102462011-01-24 17:43:27 +00004201 int fbc_wm, plane_wm, cursor_wm;
4202 unsigned int enabled;
Yuanhan Liu13982612010-12-15 15:42:31 +08004203
4204 enabled = 0;
Chris Wilson9f405102011-05-12 22:17:14 +01004205 if (g4x_compute_wm0(dev, 0,
4206 &sandybridge_display_wm_info, latency,
4207 &sandybridge_cursor_wm_info, latency,
4208 &plane_wm, &cursor_wm)) {
Yuanhan Liu13982612010-12-15 15:42:31 +08004209 I915_WRITE(WM0_PIPEA_ILK,
4210 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4211 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4212 " plane %d, " "cursor: %d\n",
4213 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004214 enabled |= 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004215 }
4216
Chris Wilson9f405102011-05-12 22:17:14 +01004217 if (g4x_compute_wm0(dev, 1,
4218 &sandybridge_display_wm_info, latency,
4219 &sandybridge_cursor_wm_info, latency,
4220 &plane_wm, &cursor_wm)) {
Yuanhan Liu13982612010-12-15 15:42:31 +08004221 I915_WRITE(WM0_PIPEB_ILK,
4222 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4223 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4224 " plane %d, cursor: %d\n",
4225 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004226 enabled |= 2;
Yuanhan Liu13982612010-12-15 15:42:31 +08004227 }
4228
4229 /*
4230 * Calculate and update the self-refresh watermark only when one
4231 * display plane is used.
4232 *
4233 * SNB support 3 levels of watermark.
4234 *
4235 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4236 * and disabled in the descending order
4237 *
4238 */
4239 I915_WRITE(WM3_LP_ILK, 0);
4240 I915_WRITE(WM2_LP_ILK, 0);
4241 I915_WRITE(WM1_LP_ILK, 0);
4242
Chris Wilsond2102462011-01-24 17:43:27 +00004243 if (!single_plane_enabled(enabled))
Yuanhan Liu13982612010-12-15 15:42:31 +08004244 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004245 enabled = ffs(enabled) - 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004246
4247 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004248 if (!ironlake_compute_srwm(dev, 1, enabled,
4249 SNB_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004250 &sandybridge_display_srwm_info,
4251 &sandybridge_cursor_srwm_info,
4252 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004253 return;
4254
4255 I915_WRITE(WM1_LP_ILK,
4256 WM1_LP_SR_EN |
4257 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4258 (fbc_wm << WM1_LP_FBC_SHIFT) |
4259 (plane_wm << WM1_LP_SR_SHIFT) |
4260 cursor_wm);
4261
4262 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004263 if (!ironlake_compute_srwm(dev, 2, enabled,
4264 SNB_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004265 &sandybridge_display_srwm_info,
4266 &sandybridge_cursor_srwm_info,
4267 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004268 return;
4269
4270 I915_WRITE(WM2_LP_ILK,
4271 WM2_LP_EN |
4272 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4273 (fbc_wm << WM1_LP_FBC_SHIFT) |
4274 (plane_wm << WM1_LP_SR_SHIFT) |
4275 cursor_wm);
4276
4277 /* WM3 */
Chris Wilsond2102462011-01-24 17:43:27 +00004278 if (!ironlake_compute_srwm(dev, 3, enabled,
4279 SNB_READ_WM3_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004280 &sandybridge_display_srwm_info,
4281 &sandybridge_cursor_srwm_info,
4282 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004283 return;
4284
4285 I915_WRITE(WM3_LP_ILK,
4286 WM3_LP_EN |
4287 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4288 (fbc_wm << WM1_LP_FBC_SHIFT) |
4289 (plane_wm << WM1_LP_SR_SHIFT) |
4290 cursor_wm);
4291}
4292
Shaohua Li7662c8b2009-06-26 11:23:55 +08004293/**
4294 * intel_update_watermarks - update FIFO watermark values based on current modes
4295 *
4296 * Calculate watermark values for the various WM regs based on current mode
4297 * and plane configuration.
4298 *
4299 * There are several cases to deal with here:
4300 * - normal (i.e. non-self-refresh)
4301 * - self-refresh (SR) mode
4302 * - lines are large relative to FIFO size (buffer can hold up to 2)
4303 * - lines are small relative to FIFO size (buffer can hold more than 2
4304 * lines), so need to account for TLB latency
4305 *
4306 * The normal calculation is:
4307 * watermark = dotclock * bytes per pixel * latency
4308 * where latency is platform & configuration dependent (we assume pessimal
4309 * values here).
4310 *
4311 * The SR calculation is:
4312 * watermark = (trunc(latency/line time)+1) * surface width *
4313 * bytes per pixel
4314 * where
4315 * line time = htotal / dotclock
Zhao Yakuifa143212010-06-12 14:32:23 +08004316 * surface width = hdisplay for normal plane and 64 for cursor
Shaohua Li7662c8b2009-06-26 11:23:55 +08004317 * and latency is assumed to be high, as above.
4318 *
4319 * The final value programmed to the register should always be rounded up,
4320 * and include an extra 2 entries to account for clock crossings.
4321 *
4322 * We don't use the sprite, so we can ignore that. And on Crestline we have
4323 * to set the non-SR watermarks to 8.
Chris Wilson5eddb702010-09-11 13:48:45 +01004324 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004325static void intel_update_watermarks(struct drm_device *dev)
4326{
Jesse Barnese70236a2009-09-21 10:42:27 -07004327 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004328
Chris Wilsond2102462011-01-24 17:43:27 +00004329 if (dev_priv->display.update_wm)
4330 dev_priv->display.update_wm(dev);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004331}
4332
Chris Wilsona7615032011-01-12 17:04:08 +00004333static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4334{
Keith Packard435793d2011-07-12 14:56:22 -07004335 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4336 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004337}
4338
Eric Anholtf564048e2011-03-30 13:01:02 -07004339static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4340 struct drm_display_mode *mode,
4341 struct drm_display_mode *adjusted_mode,
4342 int x, int y,
4343 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004344{
4345 struct drm_device *dev = crtc->dev;
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004349 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004350 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004351 intel_clock_t clock, reduced_clock;
Chris Wilson5eddb702010-09-11 13:48:45 +01004352 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Jesse Barnes652c3932009-08-17 13:31:43 -07004353 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004354 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004355 struct drm_mode_config *mode_config = &dev->mode_config;
Chris Wilson5eddb702010-09-11 13:48:45 +01004356 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004357 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004358 int ret;
Eric Anholtfae14982011-03-30 13:01:09 -07004359 u32 temp;
Bryan Freedaa9b5002011-01-12 13:43:19 -08004360 u32 lvds_sync = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08004361
Chris Wilson5eddb702010-09-11 13:48:45 +01004362 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4363 if (encoder->base.crtc != crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08004364 continue;
4365
Chris Wilson5eddb702010-09-11 13:48:45 +01004366 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004367 case INTEL_OUTPUT_LVDS:
4368 is_lvds = true;
4369 break;
4370 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004371 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004372 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004373 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004374 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004375 break;
4376 case INTEL_OUTPUT_DVO:
4377 is_dvo = true;
4378 break;
4379 case INTEL_OUTPUT_TVOUT:
4380 is_tv = true;
4381 break;
4382 case INTEL_OUTPUT_ANALOG:
4383 is_crt = true;
4384 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004385 case INTEL_OUTPUT_DISPLAYPORT:
4386 is_dp = true;
4387 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004388 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004389
Eric Anholtc751ce42010-03-25 11:48:48 -07004390 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004391 }
4392
Chris Wilsona7615032011-01-12 17:04:08 +00004393 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004394 refclk = dev_priv->lvds_ssc_freq * 1000;
Zhao Yakui28c97732009-10-09 11:39:41 +08004395 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004396 refclk / 1000);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004397 } else if (!IS_GEN2(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004398 refclk = 96000;
4399 } else {
4400 refclk = 48000;
4401 }
4402
Ma Lingd4906092009-03-18 20:13:27 +08004403 /*
4404 * Returns a set of divisors for the desired target clock with the given
4405 * refclk, or FALSE. The returned values represent the clock equation:
4406 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4407 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004408 limit = intel_limit(crtc, refclk);
Ma Lingd4906092009-03-18 20:13:27 +08004409 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004410 if (!ok) {
4411 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004412 return -EINVAL;
4413 }
4414
4415 /* Ensure that the cursor is valid for the new mode before changing... */
4416 intel_crtc_update_cursor(crtc, true);
4417
4418 if (is_lvds && dev_priv->lvds_downclock_avail) {
4419 has_reduced_clock = limit->find_pll(limit, crtc,
4420 dev_priv->lvds_downclock,
4421 refclk,
4422 &reduced_clock);
4423 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4424 /*
4425 * If the different P is found, it means that we can't
4426 * switch the display clock by using the FP0/FP1.
4427 * In such case we will disable the LVDS downclock
4428 * feature.
4429 */
4430 DRM_DEBUG_KMS("Different P is found for "
4431 "LVDS clock/downclock\n");
4432 has_reduced_clock = 0;
4433 }
4434 }
4435 /* SDVO TV has fixed PLL values depend on its clock range,
4436 this mirrors vbios setting. */
4437 if (is_sdvo && is_tv) {
4438 if (adjusted_mode->clock >= 100000
4439 && adjusted_mode->clock < 140500) {
4440 clock.p1 = 2;
4441 clock.p2 = 10;
4442 clock.n = 3;
4443 clock.m1 = 16;
4444 clock.m2 = 8;
4445 } else if (adjusted_mode->clock >= 140500
4446 && adjusted_mode->clock <= 200000) {
4447 clock.p1 = 1;
4448 clock.p2 = 10;
4449 clock.n = 6;
4450 clock.m1 = 12;
4451 clock.m2 = 8;
4452 }
4453 }
4454
Eric Anholtf564048e2011-03-30 13:01:02 -07004455 if (IS_PINEVIEW(dev)) {
4456 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4457 if (has_reduced_clock)
4458 fp2 = (1 << reduced_clock.n) << 16 |
4459 reduced_clock.m1 << 8 | reduced_clock.m2;
4460 } else {
4461 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4462 if (has_reduced_clock)
4463 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4464 reduced_clock.m2;
4465 }
4466
Eric Anholt929c77f2011-03-30 13:01:04 -07004467 dpll = DPLL_VGA_MODE_DIS;
Eric Anholtf564048e2011-03-30 13:01:02 -07004468
4469 if (!IS_GEN2(dev)) {
4470 if (is_lvds)
4471 dpll |= DPLLB_MODE_LVDS;
4472 else
4473 dpll |= DPLLB_MODE_DAC_SERIAL;
4474 if (is_sdvo) {
4475 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4476 if (pixel_multiplier > 1) {
4477 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4478 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Eric Anholtf564048e2011-03-30 13:01:02 -07004479 }
4480 dpll |= DPLL_DVO_HIGH_SPEED;
4481 }
Eric Anholt929c77f2011-03-30 13:01:04 -07004482 if (is_dp)
Eric Anholtf564048e2011-03-30 13:01:02 -07004483 dpll |= DPLL_DVO_HIGH_SPEED;
4484
4485 /* compute bitmask from p1 value */
4486 if (IS_PINEVIEW(dev))
4487 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4488 else {
4489 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholtf564048e2011-03-30 13:01:02 -07004490 if (IS_G4X(dev) && has_reduced_clock)
4491 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4492 }
4493 switch (clock.p2) {
4494 case 5:
4495 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4496 break;
4497 case 7:
4498 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4499 break;
4500 case 10:
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4502 break;
4503 case 14:
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4505 break;
4506 }
Eric Anholt929c77f2011-03-30 13:01:04 -07004507 if (INTEL_INFO(dev)->gen >= 4)
Eric Anholtf564048e2011-03-30 13:01:02 -07004508 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4509 } else {
4510 if (is_lvds) {
4511 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 } else {
4513 if (clock.p1 == 2)
4514 dpll |= PLL_P1_DIVIDE_BY_TWO;
4515 else
4516 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4517 if (clock.p2 == 4)
4518 dpll |= PLL_P2_DIVIDE_BY_4;
4519 }
4520 }
4521
4522 if (is_sdvo && is_tv)
4523 dpll |= PLL_REF_INPUT_TVCLKINBC;
4524 else if (is_tv)
4525 /* XXX: just matching BIOS for now */
4526 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4527 dpll |= 3;
4528 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4529 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4530 else
4531 dpll |= PLL_REF_INPUT_DREFCLK;
4532
4533 /* setup pipeconf */
4534 pipeconf = I915_READ(PIPECONF(pipe));
4535
4536 /* Set up the display plane register */
4537 dspcntr = DISPPLANE_GAMMA_ENABLE;
4538
4539 /* Ironlake's plane is forced to pipe, bit 24 is to
4540 enable color space conversion */
Eric Anholt929c77f2011-03-30 13:01:04 -07004541 if (pipe == 0)
4542 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4543 else
4544 dspcntr |= DISPPLANE_SEL_PIPE_B;
Eric Anholtf564048e2011-03-30 13:01:02 -07004545
4546 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4547 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4548 * core speed.
4549 *
4550 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4551 * pipe == 0 check?
4552 */
4553 if (mode->clock >
4554 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4555 pipeconf |= PIPECONF_DOUBLE_WIDE;
4556 else
4557 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4558 }
4559
Eric Anholt929c77f2011-03-30 13:01:04 -07004560 dpll |= DPLL_VCO_ENABLE;
Eric Anholtf564048e2011-03-30 13:01:02 -07004561
4562 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4563 drm_mode_debug_printmodeline(mode);
4564
Eric Anholtfae14982011-03-30 13:01:09 -07004565 I915_WRITE(FP0(pipe), fp);
4566 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
Eric Anholtf564048e2011-03-30 13:01:02 -07004567
Eric Anholtfae14982011-03-30 13:01:09 -07004568 POSTING_READ(DPLL(pipe));
Eric Anholtc713bb02011-03-30 13:01:05 -07004569 udelay(150);
Eric Anholtf564048e2011-03-30 13:01:02 -07004570
Eric Anholtf564048e2011-03-30 13:01:02 -07004571 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4572 * This is an exception to the general rule that mode_set doesn't turn
4573 * things on.
4574 */
4575 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07004576 temp = I915_READ(LVDS);
Eric Anholtf564048e2011-03-30 13:01:02 -07004577 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4578 if (pipe == 1) {
Eric Anholt929c77f2011-03-30 13:01:04 -07004579 temp |= LVDS_PIPEB_SELECT;
Eric Anholtf564048e2011-03-30 13:01:02 -07004580 } else {
Eric Anholt929c77f2011-03-30 13:01:04 -07004581 temp &= ~LVDS_PIPEB_SELECT;
Eric Anholtf564048e2011-03-30 13:01:02 -07004582 }
4583 /* set the corresponsding LVDS_BORDER bit */
4584 temp |= dev_priv->lvds_border_bits;
4585 /* Set the B0-B3 data pairs corresponding to whether we're going to
4586 * set the DPLLs for dual-channel mode or not.
4587 */
4588 if (clock.p2 == 7)
4589 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4590 else
4591 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4592
4593 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4594 * appropriately here, but we need to look more thoroughly into how
4595 * panels behave in the two modes.
4596 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004597 /* set the dithering flag on LVDS as needed */
4598 if (INTEL_INFO(dev)->gen >= 4) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004599 if (dev_priv->lvds_dither)
4600 temp |= LVDS_ENABLE_DITHER;
4601 else
4602 temp &= ~LVDS_ENABLE_DITHER;
4603 }
4604 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4605 lvds_sync |= LVDS_HSYNC_POLARITY;
4606 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4607 lvds_sync |= LVDS_VSYNC_POLARITY;
4608 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4609 != lvds_sync) {
4610 char flags[2] = "-+";
4611 DRM_INFO("Changing LVDS panel from "
4612 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4613 flags[!(temp & LVDS_HSYNC_POLARITY)],
4614 flags[!(temp & LVDS_VSYNC_POLARITY)],
4615 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4616 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4617 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4618 temp |= lvds_sync;
4619 }
Eric Anholtfae14982011-03-30 13:01:09 -07004620 I915_WRITE(LVDS, temp);
Eric Anholtf564048e2011-03-30 13:01:02 -07004621 }
4622
Eric Anholt929c77f2011-03-30 13:01:04 -07004623 if (is_dp) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004624 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholtf564048e2011-03-30 13:01:02 -07004625 }
4626
Eric Anholtfae14982011-03-30 13:01:09 -07004627 I915_WRITE(DPLL(pipe), dpll);
Eric Anholtf564048e2011-03-30 13:01:02 -07004628
Eric Anholtc713bb02011-03-30 13:01:05 -07004629 /* Wait for the clocks to stabilize. */
Eric Anholtfae14982011-03-30 13:01:09 -07004630 POSTING_READ(DPLL(pipe));
Eric Anholtc713bb02011-03-30 13:01:05 -07004631 udelay(150);
Eric Anholtf564048e2011-03-30 13:01:02 -07004632
Eric Anholtc713bb02011-03-30 13:01:05 -07004633 if (INTEL_INFO(dev)->gen >= 4) {
4634 temp = 0;
4635 if (is_sdvo) {
4636 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4637 if (temp > 1)
4638 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4639 else
4640 temp = 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07004641 }
Eric Anholtc713bb02011-03-30 13:01:05 -07004642 I915_WRITE(DPLL_MD(pipe), temp);
4643 } else {
4644 /* The pixel multiplier can only be updated once the
4645 * DPLL is enabled and the clocks are stable.
4646 *
4647 * So write it again.
4648 */
Eric Anholtfae14982011-03-30 13:01:09 -07004649 I915_WRITE(DPLL(pipe), dpll);
Eric Anholtf564048e2011-03-30 13:01:02 -07004650 }
4651
4652 intel_crtc->lowfreq_avail = false;
4653 if (is_lvds && has_reduced_clock && i915_powersave) {
Eric Anholtfae14982011-03-30 13:01:09 -07004654 I915_WRITE(FP1(pipe), fp2);
Eric Anholtf564048e2011-03-30 13:01:02 -07004655 intel_crtc->lowfreq_avail = true;
4656 if (HAS_PIPE_CXSR(dev)) {
4657 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4658 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4659 }
4660 } else {
Eric Anholtfae14982011-03-30 13:01:09 -07004661 I915_WRITE(FP1(pipe), fp);
Eric Anholtf564048e2011-03-30 13:01:02 -07004662 if (HAS_PIPE_CXSR(dev)) {
4663 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4664 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4665 }
4666 }
4667
4668 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4669 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4670 /* the chip adds 2 halflines automatically */
4671 adjusted_mode->crtc_vdisplay -= 1;
4672 adjusted_mode->crtc_vtotal -= 1;
4673 adjusted_mode->crtc_vblank_start -= 1;
4674 adjusted_mode->crtc_vblank_end -= 1;
4675 adjusted_mode->crtc_vsync_end -= 1;
4676 adjusted_mode->crtc_vsync_start -= 1;
4677 } else
4678 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4679
4680 I915_WRITE(HTOTAL(pipe),
4681 (adjusted_mode->crtc_hdisplay - 1) |
4682 ((adjusted_mode->crtc_htotal - 1) << 16));
4683 I915_WRITE(HBLANK(pipe),
4684 (adjusted_mode->crtc_hblank_start - 1) |
4685 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4686 I915_WRITE(HSYNC(pipe),
4687 (adjusted_mode->crtc_hsync_start - 1) |
4688 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4689
4690 I915_WRITE(VTOTAL(pipe),
4691 (adjusted_mode->crtc_vdisplay - 1) |
4692 ((adjusted_mode->crtc_vtotal - 1) << 16));
4693 I915_WRITE(VBLANK(pipe),
4694 (adjusted_mode->crtc_vblank_start - 1) |
4695 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4696 I915_WRITE(VSYNC(pipe),
4697 (adjusted_mode->crtc_vsync_start - 1) |
4698 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4699
4700 /* pipesrc and dspsize control the size that is scaled from,
4701 * which should always be the user's requested size.
4702 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004703 I915_WRITE(DSPSIZE(plane),
4704 ((mode->vdisplay - 1) << 16) |
4705 (mode->hdisplay - 1));
4706 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004707 I915_WRITE(PIPESRC(pipe),
4708 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4709
Eric Anholtf564048e2011-03-30 13:01:02 -07004710 I915_WRITE(PIPECONF(pipe), pipeconf);
4711 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07004712 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf564048e2011-03-30 13:01:02 -07004713
4714 intel_wait_for_vblank(dev, pipe);
4715
Eric Anholtf564048e2011-03-30 13:01:02 -07004716 I915_WRITE(DSPCNTR(plane), dspcntr);
4717 POSTING_READ(DSPCNTR(plane));
Keith Packardefc29242011-06-06 17:12:49 -07004718 intel_enable_plane(dev_priv, plane, pipe);
Eric Anholtf564048e2011-03-30 13:01:02 -07004719
4720 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4721
4722 intel_update_watermarks(dev);
4723
Eric Anholtf564048e2011-03-30 13:01:02 -07004724 return ret;
4725}
4726
4727static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4728 struct drm_display_mode *mode,
4729 struct drm_display_mode *adjusted_mode,
4730 int x, int y,
4731 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004732{
4733 struct drm_device *dev = crtc->dev;
4734 struct drm_i915_private *dev_priv = dev->dev_private;
4735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4736 int pipe = intel_crtc->pipe;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004737 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08004738 int refclk, num_connectors = 0;
4739 intel_clock_t clock, reduced_clock;
4740 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Eric Anholta07d6782011-03-30 13:01:08 -07004741 bool ok, has_reduced_clock = false, is_sdvo = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004742 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4743 struct intel_encoder *has_edp_encoder = NULL;
4744 struct drm_mode_config *mode_config = &dev->mode_config;
4745 struct intel_encoder *encoder;
4746 const intel_limit_t *limit;
4747 int ret;
4748 struct fdi_m_n m_n = {0};
Eric Anholtfae14982011-03-30 13:01:09 -07004749 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08004750 u32 lvds_sync = 0;
Eric Anholt8febb292011-03-30 13:01:07 -07004751 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
Jesse Barnes79e53942008-11-07 14:24:08 -08004752
Jesse Barnes79e53942008-11-07 14:24:08 -08004753 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4754 if (encoder->base.crtc != crtc)
4755 continue;
4756
4757 switch (encoder->type) {
4758 case INTEL_OUTPUT_LVDS:
4759 is_lvds = true;
4760 break;
4761 case INTEL_OUTPUT_SDVO:
4762 case INTEL_OUTPUT_HDMI:
4763 is_sdvo = true;
4764 if (encoder->needs_tv_clock)
4765 is_tv = true;
4766 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004767 case INTEL_OUTPUT_TVOUT:
4768 is_tv = true;
4769 break;
4770 case INTEL_OUTPUT_ANALOG:
4771 is_crt = true;
4772 break;
4773 case INTEL_OUTPUT_DISPLAYPORT:
4774 is_dp = true;
4775 break;
4776 case INTEL_OUTPUT_EDP:
4777 has_edp_encoder = encoder;
4778 break;
4779 }
4780
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004781 num_connectors++;
4782 }
4783
Jesse Barnes79e53942008-11-07 14:24:08 -08004784 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004785 refclk = dev_priv->lvds_ssc_freq * 1000;
Jesse Barnes79e53942008-11-07 14:24:08 -08004786 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004787 refclk / 1000);
Eric Anholta07d6782011-03-30 13:01:08 -07004788 } else {
Jesse Barnes79e53942008-11-07 14:24:08 -08004789 refclk = 96000;
Eric Anholt8febb292011-03-30 13:01:07 -07004790 if (!has_edp_encoder ||
4791 intel_encoder_is_pch_edp(&has_edp_encoder->base))
Jesse Barnes79e53942008-11-07 14:24:08 -08004792 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08004793 }
4794
4795 /*
4796 * Returns a set of divisors for the desired target clock with the given
4797 * refclk, or FALSE. The returned values represent the clock equation:
4798 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4799 */
4800 limit = intel_limit(crtc, refclk);
4801 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4802 if (!ok) {
4803 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08004804 return -EINVAL;
4805 }
4806
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004807 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01004808 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004809
Zhao Yakuiddc90032010-01-06 22:05:56 +08004810 if (is_lvds && dev_priv->lvds_downclock_avail) {
4811 has_reduced_clock = limit->find_pll(limit, crtc,
Chris Wilson5eddb702010-09-11 13:48:45 +01004812 dev_priv->lvds_downclock,
4813 refclk,
4814 &reduced_clock);
Zhao Yakui18f9ed12009-11-20 03:24:16 +00004815 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4816 /*
4817 * If the different P is found, it means that we can't
4818 * switch the display clock by using the FP0/FP1.
4819 * In such case we will disable the LVDS downclock
4820 * feature.
4821 */
4822 DRM_DEBUG_KMS("Different P is found for "
Chris Wilson5eddb702010-09-11 13:48:45 +01004823 "LVDS clock/downclock\n");
Zhao Yakui18f9ed12009-11-20 03:24:16 +00004824 has_reduced_clock = 0;
4825 }
Jesse Barnes652c3932009-08-17 13:31:43 -07004826 }
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004827 /* SDVO TV has fixed PLL values depend on its clock range,
4828 this mirrors vbios setting. */
4829 if (is_sdvo && is_tv) {
4830 if (adjusted_mode->clock >= 100000
Chris Wilson5eddb702010-09-11 13:48:45 +01004831 && adjusted_mode->clock < 140500) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004832 clock.p1 = 2;
4833 clock.p2 = 10;
4834 clock.n = 3;
4835 clock.m1 = 16;
4836 clock.m2 = 8;
4837 } else if (adjusted_mode->clock >= 140500
Chris Wilson5eddb702010-09-11 13:48:45 +01004838 && adjusted_mode->clock <= 200000) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004839 clock.p1 = 1;
4840 clock.p2 = 10;
4841 clock.n = 6;
4842 clock.m1 = 12;
4843 clock.m2 = 8;
4844 }
4845 }
4846
Zhenyu Wang2c072452009-06-05 15:38:42 +08004847 /* FDI link */
Eric Anholt8febb292011-03-30 13:01:07 -07004848 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4849 lane = 0;
4850 /* CPU eDP doesn't require FDI link, so just set DP M/N
4851 according to current link config */
4852 if (has_edp_encoder &&
4853 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4854 target_clock = mode->clock;
4855 intel_edp_link_config(has_edp_encoder,
4856 &lane, &link_bw);
4857 } else {
4858 /* [e]DP over FDI requires target mode clock
4859 instead of link clock */
4860 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004861 target_clock = mode->clock;
Eric Anholt8febb292011-03-30 13:01:07 -07004862 else
4863 target_clock = adjusted_mode->clock;
Chris Wilson021357a2010-09-07 20:54:59 +01004864
Eric Anholt8febb292011-03-30 13:01:07 -07004865 /* FDI is a binary signal running at ~2.7GHz, encoding
4866 * each output octet as 10 bits. The actual frequency
4867 * is stored as a divider into a 100MHz clock, and the
4868 * mode pixel clock is stored in units of 1KHz.
4869 * Hence the bw of each lane in terms of the mode signal
4870 * is:
4871 */
4872 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004873 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08004874
Eric Anholt8febb292011-03-30 13:01:07 -07004875 /* determine panel color depth */
4876 temp = I915_READ(PIPECONF(pipe));
4877 temp &= ~PIPE_BPC_MASK;
4878 if (is_lvds) {
4879 /* the BPC will be 6 if it is 18-bit LVDS panel */
4880 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4881 temp |= PIPE_8BPC;
4882 else
4883 temp |= PIPE_6BPC;
4884 } else if (has_edp_encoder) {
4885 switch (dev_priv->edp.bpp/3) {
4886 case 8:
4887 temp |= PIPE_8BPC;
4888 break;
4889 case 10:
4890 temp |= PIPE_10BPC;
4891 break;
4892 case 6:
4893 temp |= PIPE_6BPC;
4894 break;
4895 case 12:
4896 temp |= PIPE_12BPC;
4897 break;
4898 }
4899 } else
4900 temp |= PIPE_8BPC;
4901 I915_WRITE(PIPECONF(pipe), temp);
4902
4903 switch (temp & PIPE_BPC_MASK) {
4904 case PIPE_8BPC:
4905 bpp = 24;
4906 break;
4907 case PIPE_10BPC:
4908 bpp = 30;
4909 break;
4910 case PIPE_6BPC:
4911 bpp = 18;
4912 break;
4913 case PIPE_12BPC:
4914 bpp = 36;
4915 break;
4916 default:
4917 DRM_ERROR("unknown pipe bpc value\n");
4918 bpp = 24;
4919 }
4920
4921 if (!lane) {
4922 /*
4923 * Account for spread spectrum to avoid
4924 * oversubscribing the link. Max center spread
4925 * is 2.5%; use 5% for safety's sake.
4926 */
4927 u32 bps = target_clock * bpp * 21 / 20;
4928 lane = bps / (link_bw * 8) + 1;
4929 }
4930
4931 intel_crtc->fdi_lanes = lane;
4932
4933 if (pixel_multiplier > 1)
4934 link_bw *= pixel_multiplier;
4935 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4936
Zhenyu Wangc038e512009-10-19 15:43:48 +08004937 /* Ironlake: try to setup display ref clock before DPLL
4938 * enabling. This is only under driver's control after
4939 * PCH B stepping, previous chipset stepping should be
4940 * ignoring this setting.
4941 */
Eric Anholt8febb292011-03-30 13:01:07 -07004942 temp = I915_READ(PCH_DREF_CONTROL);
4943 /* Always enable nonspread source */
4944 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4945 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4946 temp &= ~DREF_SSC_SOURCE_MASK;
4947 temp |= DREF_SSC_SOURCE_ENABLE;
4948 I915_WRITE(PCH_DREF_CONTROL, temp);
Chris Wilsonfc9a2222011-02-17 17:14:34 +00004949
Eric Anholt8febb292011-03-30 13:01:07 -07004950 POSTING_READ(PCH_DREF_CONTROL);
4951 udelay(200);
Chris Wilsonfc9a2222011-02-17 17:14:34 +00004952
Eric Anholt8febb292011-03-30 13:01:07 -07004953 if (has_edp_encoder) {
4954 if (intel_panel_use_ssc(dev_priv)) {
4955 temp |= DREF_SSC1_ENABLE;
Chris Wilsonfc9a2222011-02-17 17:14:34 +00004956 I915_WRITE(PCH_DREF_CONTROL, temp);
Eric Anholt8febb292011-03-30 13:01:07 -07004957
Chris Wilsonfc9a2222011-02-17 17:14:34 +00004958 POSTING_READ(PCH_DREF_CONTROL);
4959 udelay(200);
4960 }
Eric Anholt8febb292011-03-30 13:01:07 -07004961 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4962
4963 /* Enable CPU source on CPU attached eDP */
4964 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4965 if (intel_panel_use_ssc(dev_priv))
4966 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4967 else
4968 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4969 } else {
4970 /* Enable SSC on PCH eDP if needed */
4971 if (intel_panel_use_ssc(dev_priv)) {
4972 DRM_ERROR("enabling SSC on PCH\n");
4973 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4974 }
4975 }
4976 I915_WRITE(PCH_DREF_CONTROL, temp);
4977 POSTING_READ(PCH_DREF_CONTROL);
4978 udelay(200);
Chris Wilsonfc9a2222011-02-17 17:14:34 +00004979 }
Zhenyu Wangc038e512009-10-19 15:43:48 +08004980
Eric Anholta07d6782011-03-30 13:01:08 -07004981 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4982 if (has_reduced_clock)
4983 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4984 reduced_clock.m2;
Jesse Barnes79e53942008-11-07 14:24:08 -08004985
Chris Wilsonc1858122010-12-03 21:35:48 +00004986 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07004987 factor = 21;
4988 if (is_lvds) {
4989 if ((intel_panel_use_ssc(dev_priv) &&
4990 dev_priv->lvds_ssc_freq == 100) ||
4991 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4992 factor = 25;
4993 } else if (is_sdvo && is_tv)
4994 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00004995
Eric Anholt8febb292011-03-30 13:01:07 -07004996 if (clock.m1 < factor * clock.n)
4997 fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00004998
Chris Wilson5eddb702010-09-11 13:48:45 +01004999 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005000
Eric Anholta07d6782011-03-30 13:01:08 -07005001 if (is_lvds)
5002 dpll |= DPLLB_MODE_LVDS;
5003 else
5004 dpll |= DPLLB_MODE_DAC_SERIAL;
5005 if (is_sdvo) {
5006 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5007 if (pixel_multiplier > 1) {
5008 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08005009 }
Eric Anholta07d6782011-03-30 13:01:08 -07005010 dpll |= DPLL_DVO_HIGH_SPEED;
5011 }
5012 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5013 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08005014
Eric Anholta07d6782011-03-30 13:01:08 -07005015 /* compute bitmask from p1 value */
5016 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5017 /* also FPA1 */
5018 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5019
5020 switch (clock.p2) {
5021 case 5:
5022 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5023 break;
5024 case 7:
5025 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5026 break;
5027 case 10:
5028 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5029 break;
5030 case 14:
5031 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5032 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005033 }
5034
5035 if (is_sdvo && is_tv)
5036 dpll |= PLL_REF_INPUT_TVCLKINBC;
5037 else if (is_tv)
5038 /* XXX: just matching BIOS for now */
5039 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5040 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00005041 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Jesse Barnes79e53942008-11-07 14:24:08 -08005042 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5043 else
5044 dpll |= PLL_REF_INPUT_DREFCLK;
5045
5046 /* setup pipeconf */
Chris Wilson5eddb702010-09-11 13:48:45 +01005047 pipeconf = I915_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005048
5049 /* Set up the display plane register */
5050 dspcntr = DISPPLANE_GAMMA_ENABLE;
5051
Zhao Yakui28c97732009-10-09 11:39:41 +08005052 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
Jesse Barnes79e53942008-11-07 14:24:08 -08005053 drm_mode_debug_printmodeline(mode);
5054
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005055 /* PCH eDP needs FDI, but CPU eDP does not */
5056 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Eric Anholtfae14982011-03-30 13:01:09 -07005057 I915_WRITE(PCH_FP0(pipe), fp);
5058 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01005059
Eric Anholtfae14982011-03-30 13:01:09 -07005060 POSTING_READ(PCH_DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005061 udelay(150);
5062 }
5063
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005064 /* enable transcoder DPLL */
5065 if (HAS_PCH_CPT(dev)) {
5066 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005067 switch (pipe) {
5068 case 0:
Chris Wilson5eddb702010-09-11 13:48:45 +01005069 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005070 break;
5071 case 1:
Chris Wilson5eddb702010-09-11 13:48:45 +01005072 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005073 break;
5074 case 2:
5075 /* FIXME: manage transcoder PLLs? */
5076 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5077 break;
5078 default:
5079 BUG();
5080 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005081 I915_WRITE(PCH_DPLL_SEL, temp);
Chris Wilson5eddb702010-09-11 13:48:45 +01005082
5083 POSTING_READ(PCH_DPLL_SEL);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005084 udelay(150);
5085 }
5086
Jesse Barnes79e53942008-11-07 14:24:08 -08005087 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5088 * This is an exception to the general rule that mode_set doesn't turn
5089 * things on.
5090 */
5091 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07005092 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01005093 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005094 if (pipe == 1) {
5095 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01005096 temp |= PORT_TRANS_B_SEL_CPT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005097 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005098 temp |= LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005099 } else {
5100 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01005101 temp &= ~PORT_TRANS_SEL_MASK;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005102 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005103 temp &= ~LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005104 }
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08005105 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01005106 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08005107 /* Set the B0-B3 data pairs corresponding to whether we're going to
5108 * set the DPLLs for dual-channel mode or not.
5109 */
5110 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01005111 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08005112 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005113 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08005114
5115 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5116 * appropriately here, but we need to look more thoroughly into how
5117 * panels behave in the two modes.
5118 */
Bryan Freedaa9b5002011-01-12 13:43:19 -08005119 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5120 lvds_sync |= LVDS_HSYNC_POLARITY;
5121 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5122 lvds_sync |= LVDS_VSYNC_POLARITY;
5123 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5124 != lvds_sync) {
5125 char flags[2] = "-+";
5126 DRM_INFO("Changing LVDS panel from "
5127 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5128 flags[!(temp & LVDS_HSYNC_POLARITY)],
5129 flags[!(temp & LVDS_VSYNC_POLARITY)],
5130 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5131 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5132 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5133 temp |= lvds_sync;
5134 }
Eric Anholtfae14982011-03-30 13:01:09 -07005135 I915_WRITE(PCH_LVDS, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005136 }
Jesse Barnes434ed092010-09-07 14:48:06 -07005137
5138 /* set the dithering flag and clear for anything other than a panel. */
Eric Anholt8febb292011-03-30 13:01:07 -07005139 pipeconf &= ~PIPECONF_DITHER_EN;
5140 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5141 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5142 pipeconf |= PIPECONF_DITHER_EN;
5143 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
Jesse Barnes434ed092010-09-07 14:48:06 -07005144 }
5145
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005146 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005147 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholt8febb292011-03-30 13:01:07 -07005148 } else {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005149 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005150 I915_WRITE(TRANSDATA_M1(pipe), 0);
5151 I915_WRITE(TRANSDATA_N1(pipe), 0);
5152 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5153 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005154 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005155
Eric Anholt8febb292011-03-30 13:01:07 -07005156 if (!has_edp_encoder ||
5157 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Eric Anholtfae14982011-03-30 13:01:09 -07005158 I915_WRITE(PCH_DPLL(pipe), dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01005159
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005160 /* Wait for the clocks to stabilize. */
Eric Anholtfae14982011-03-30 13:01:09 -07005161 POSTING_READ(PCH_DPLL(pipe));
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005162 udelay(150);
5163
Eric Anholt8febb292011-03-30 13:01:07 -07005164 /* The pixel multiplier can only be updated once the
5165 * DPLL is enabled and the clocks are stable.
5166 *
5167 * So write it again.
5168 */
Eric Anholtfae14982011-03-30 13:01:09 -07005169 I915_WRITE(PCH_DPLL(pipe), dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08005170 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005171
Chris Wilson5eddb702010-09-11 13:48:45 +01005172 intel_crtc->lowfreq_avail = false;
Jesse Barnes652c3932009-08-17 13:31:43 -07005173 if (is_lvds && has_reduced_clock && i915_powersave) {
Eric Anholtfae14982011-03-30 13:01:09 -07005174 I915_WRITE(PCH_FP1(pipe), fp2);
Jesse Barnes652c3932009-08-17 13:31:43 -07005175 intel_crtc->lowfreq_avail = true;
5176 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005177 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005178 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5179 }
5180 } else {
Eric Anholtfae14982011-03-30 13:01:09 -07005181 I915_WRITE(PCH_FP1(pipe), fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07005182 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005183 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005184 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5185 }
5186 }
5187
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005188 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5189 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5190 /* the chip adds 2 halflines automatically */
5191 adjusted_mode->crtc_vdisplay -= 1;
5192 adjusted_mode->crtc_vtotal -= 1;
5193 adjusted_mode->crtc_vblank_start -= 1;
5194 adjusted_mode->crtc_vblank_end -= 1;
5195 adjusted_mode->crtc_vsync_end -= 1;
5196 adjusted_mode->crtc_vsync_start -= 1;
5197 } else
5198 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5199
Chris Wilson5eddb702010-09-11 13:48:45 +01005200 I915_WRITE(HTOTAL(pipe),
5201 (adjusted_mode->crtc_hdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005202 ((adjusted_mode->crtc_htotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005203 I915_WRITE(HBLANK(pipe),
5204 (adjusted_mode->crtc_hblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005205 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005206 I915_WRITE(HSYNC(pipe),
5207 (adjusted_mode->crtc_hsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005208 ((adjusted_mode->crtc_hsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005209
5210 I915_WRITE(VTOTAL(pipe),
5211 (adjusted_mode->crtc_vdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005212 ((adjusted_mode->crtc_vtotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005213 I915_WRITE(VBLANK(pipe),
5214 (adjusted_mode->crtc_vblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005215 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005216 I915_WRITE(VSYNC(pipe),
5217 (adjusted_mode->crtc_vsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005218 ((adjusted_mode->crtc_vsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005219
Eric Anholt8febb292011-03-30 13:01:07 -07005220 /* pipesrc controls the size that is scaled from, which should
5221 * always be the user's requested size.
Jesse Barnes79e53942008-11-07 14:24:08 -08005222 */
Chris Wilson5eddb702010-09-11 13:48:45 +01005223 I915_WRITE(PIPESRC(pipe),
5224 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08005225
Eric Anholt8febb292011-03-30 13:01:07 -07005226 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5227 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5228 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5229 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005230
Eric Anholt8febb292011-03-30 13:01:07 -07005231 if (has_edp_encoder &&
5232 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5233 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005234 }
5235
Chris Wilson5eddb702010-09-11 13:48:45 +01005236 I915_WRITE(PIPECONF(pipe), pipeconf);
5237 POSTING_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005238
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005239 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005240
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01005241 if (IS_GEN5(dev)) {
Zhenyu Wang553bd142009-09-02 10:57:52 +08005242 /* enable address swizzle for tiling buffer */
5243 temp = I915_READ(DISP_ARB_CTL);
5244 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5245 }
5246
Chris Wilson5eddb702010-09-11 13:48:45 +01005247 I915_WRITE(DSPCNTR(plane), dspcntr);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005248 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08005249
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005250 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005251
5252 intel_update_watermarks(dev);
5253
Chris Wilson1f803ee2009-06-06 09:45:59 +01005254 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005255}
5256
Eric Anholtf564048e2011-03-30 13:01:02 -07005257static int intel_crtc_mode_set(struct drm_crtc *crtc,
5258 struct drm_display_mode *mode,
5259 struct drm_display_mode *adjusted_mode,
5260 int x, int y,
5261 struct drm_framebuffer *old_fb)
5262{
5263 struct drm_device *dev = crtc->dev;
5264 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt0b701d22011-03-30 13:01:03 -07005265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07005267 int ret;
5268
Eric Anholt0b701d22011-03-30 13:01:03 -07005269 drm_vblank_pre_modeset(dev, pipe);
5270
Eric Anholtf564048e2011-03-30 13:01:02 -07005271 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5272 x, y, old_fb);
5273
Jesse Barnes79e53942008-11-07 14:24:08 -08005274 drm_vblank_post_modeset(dev, pipe);
5275
5276 return ret;
5277}
5278
5279/** Loads the palette/gamma unit for the CRTC with the prepared values */
5280void intel_crtc_load_lut(struct drm_crtc *crtc)
5281{
5282 struct drm_device *dev = crtc->dev;
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005285 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005286 int i;
5287
5288 /* The clocks have to be on to load the palette. */
5289 if (!crtc->enabled)
5290 return;
5291
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005292 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07005293 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005294 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005295
Jesse Barnes79e53942008-11-07 14:24:08 -08005296 for (i = 0; i < 256; i++) {
5297 I915_WRITE(palreg + 4 * i,
5298 (intel_crtc->lut_r[i] << 16) |
5299 (intel_crtc->lut_g[i] << 8) |
5300 intel_crtc->lut_b[i]);
5301 }
5302}
5303
Chris Wilson560b85b2010-08-07 11:01:38 +01005304static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5305{
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 bool visible = base != 0;
5310 u32 cntl;
5311
5312 if (intel_crtc->cursor_visible == visible)
5313 return;
5314
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005315 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01005316 if (visible) {
5317 /* On these chipsets we can only modify the base whilst
5318 * the cursor is disabled.
5319 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005320 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005321
5322 cntl &= ~(CURSOR_FORMAT_MASK);
5323 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5324 cntl |= CURSOR_ENABLE |
5325 CURSOR_GAMMA_ENABLE |
5326 CURSOR_FORMAT_ARGB;
5327 } else
5328 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005329 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005330
5331 intel_crtc->cursor_visible = visible;
5332}
5333
5334static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5335{
5336 struct drm_device *dev = crtc->dev;
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5339 int pipe = intel_crtc->pipe;
5340 bool visible = base != 0;
5341
5342 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08005343 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01005344 if (base) {
5345 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5346 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5347 cntl |= pipe << 28; /* Connect to correct pipe */
5348 } else {
5349 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5350 cntl |= CURSOR_MODE_DISABLE;
5351 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005352 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005353
5354 intel_crtc->cursor_visible = visible;
5355 }
5356 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005357 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005358}
5359
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005360/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005361static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5362 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005363{
5364 struct drm_device *dev = crtc->dev;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5367 int pipe = intel_crtc->pipe;
5368 int x = intel_crtc->cursor_x;
5369 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01005370 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005371 bool visible;
5372
5373 pos = 0;
5374
Chris Wilson6b383a72010-09-13 13:54:26 +01005375 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005376 base = intel_crtc->cursor_addr;
5377 if (x > (int) crtc->fb->width)
5378 base = 0;
5379
5380 if (y > (int) crtc->fb->height)
5381 base = 0;
5382 } else
5383 base = 0;
5384
5385 if (x < 0) {
5386 if (x + intel_crtc->cursor_width < 0)
5387 base = 0;
5388
5389 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5390 x = -x;
5391 }
5392 pos |= x << CURSOR_X_SHIFT;
5393
5394 if (y < 0) {
5395 if (y + intel_crtc->cursor_height < 0)
5396 base = 0;
5397
5398 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5399 y = -y;
5400 }
5401 pos |= y << CURSOR_Y_SHIFT;
5402
5403 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01005404 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005405 return;
5406
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005407 I915_WRITE(CURPOS(pipe), pos);
Chris Wilson560b85b2010-08-07 11:01:38 +01005408 if (IS_845G(dev) || IS_I865G(dev))
5409 i845_update_cursor(crtc, base);
5410 else
5411 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005412
5413 if (visible)
5414 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5415}
5416
Jesse Barnes79e53942008-11-07 14:24:08 -08005417static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00005418 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08005419 uint32_t handle,
5420 uint32_t width, uint32_t height)
5421{
5422 struct drm_device *dev = crtc->dev;
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00005425 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005426 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005427 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005428
Zhao Yakui28c97732009-10-09 11:39:41 +08005429 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08005430
5431 /* if we want to turn off the cursor ignore width and height */
5432 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005433 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005434 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00005435 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10005436 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005437 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08005438 }
5439
5440 /* Currently we only support 64x64 cursors */
5441 if (width != 64 || height != 64) {
5442 DRM_ERROR("we currently only support 64x64 cursors\n");
5443 return -EINVAL;
5444 }
5445
Chris Wilson05394f32010-11-08 19:18:58 +00005446 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00005447 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08005448 return -ENOENT;
5449
Chris Wilson05394f32010-11-08 19:18:58 +00005450 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005451 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10005452 ret = -ENOMEM;
5453 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005454 }
5455
Dave Airlie71acb5e2008-12-30 20:31:46 +10005456 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005457 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005458 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00005459 if (obj->tiling_mode) {
5460 DRM_ERROR("cursor cannot be tiled\n");
5461 ret = -EINVAL;
5462 goto fail_locked;
5463 }
5464
Chris Wilson05394f32010-11-08 19:18:58 +00005465 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005466 if (ret) {
5467 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005468 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005469 }
Chris Wilsone7b526b2010-06-02 08:30:48 +01005470
Chris Wilson05394f32010-11-08 19:18:58 +00005471 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
Chris Wilsone7b526b2010-06-02 08:30:48 +01005472 if (ret) {
5473 DRM_ERROR("failed to move cursor bo into the GTT\n");
5474 goto fail_unpin;
5475 }
5476
Chris Wilsond9e86c02010-11-10 16:40:20 +00005477 ret = i915_gem_object_put_fence(obj);
5478 if (ret) {
5479 DRM_ERROR("failed to move cursor bo into the GTT\n");
5480 goto fail_unpin;
5481 }
5482
Chris Wilson05394f32010-11-08 19:18:58 +00005483 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005484 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005485 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00005486 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005487 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5488 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005489 if (ret) {
5490 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005491 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005492 }
Chris Wilson05394f32010-11-08 19:18:58 +00005493 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005494 }
5495
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005496 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04005497 I915_WRITE(CURSIZE, (height << 12) | width);
5498
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005499 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005500 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005501 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00005502 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10005503 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5504 } else
5505 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00005506 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005507 }
Jesse Barnes80824002009-09-10 15:28:06 -07005508
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005509 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005510
5511 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00005512 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005513 intel_crtc->cursor_width = width;
5514 intel_crtc->cursor_height = height;
5515
Chris Wilson6b383a72010-09-13 13:54:26 +01005516 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005517
Jesse Barnes79e53942008-11-07 14:24:08 -08005518 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005519fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00005520 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005521fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10005522 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00005523fail:
Chris Wilson05394f32010-11-08 19:18:58 +00005524 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10005525 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005526}
5527
5528static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5529{
Jesse Barnes79e53942008-11-07 14:24:08 -08005530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005531
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005532 intel_crtc->cursor_x = x;
5533 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07005534
Chris Wilson6b383a72010-09-13 13:54:26 +01005535 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08005536
5537 return 0;
5538}
5539
5540/** Sets the color ramps on behalf of RandR */
5541void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5542 u16 blue, int regno)
5543{
5544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5545
5546 intel_crtc->lut_r[regno] = red >> 8;
5547 intel_crtc->lut_g[regno] = green >> 8;
5548 intel_crtc->lut_b[regno] = blue >> 8;
5549}
5550
Dave Airlieb8c00ac2009-10-06 13:54:01 +10005551void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5552 u16 *blue, int regno)
5553{
5554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5555
5556 *red = intel_crtc->lut_r[regno] << 8;
5557 *green = intel_crtc->lut_g[regno] << 8;
5558 *blue = intel_crtc->lut_b[regno] << 8;
5559}
5560
Jesse Barnes79e53942008-11-07 14:24:08 -08005561static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01005562 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08005563{
James Simmons72034252010-08-03 01:33:19 +01005564 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08005565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005566
James Simmons72034252010-08-03 01:33:19 +01005567 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005568 intel_crtc->lut_r[i] = red[i] >> 8;
5569 intel_crtc->lut_g[i] = green[i] >> 8;
5570 intel_crtc->lut_b[i] = blue[i] >> 8;
5571 }
5572
5573 intel_crtc_load_lut(crtc);
5574}
5575
5576/**
5577 * Get a pipe with a simple mode set on it for doing load-based monitor
5578 * detection.
5579 *
5580 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07005581 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08005582 *
Eric Anholtc751ce42010-03-25 11:48:48 -07005583 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08005584 * configured for it. In the future, it could choose to temporarily disable
5585 * some outputs to free up a pipe for its use.
5586 *
5587 * \return crtc, or NULL if no pipes are available.
5588 */
5589
5590/* VESA 640x480x72Hz mode to set on the pipe */
5591static struct drm_display_mode load_detect_mode = {
5592 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5593 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5594};
5595
Chris Wilsond2dff872011-04-19 08:36:26 +01005596static struct drm_framebuffer *
5597intel_framebuffer_create(struct drm_device *dev,
5598 struct drm_mode_fb_cmd *mode_cmd,
5599 struct drm_i915_gem_object *obj)
5600{
5601 struct intel_framebuffer *intel_fb;
5602 int ret;
5603
5604 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5605 if (!intel_fb) {
5606 drm_gem_object_unreference_unlocked(&obj->base);
5607 return ERR_PTR(-ENOMEM);
5608 }
5609
5610 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5611 if (ret) {
5612 drm_gem_object_unreference_unlocked(&obj->base);
5613 kfree(intel_fb);
5614 return ERR_PTR(ret);
5615 }
5616
5617 return &intel_fb->base;
5618}
5619
5620static u32
5621intel_framebuffer_pitch_for_width(int width, int bpp)
5622{
5623 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5624 return ALIGN(pitch, 64);
5625}
5626
5627static u32
5628intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5629{
5630 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5631 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5632}
5633
5634static struct drm_framebuffer *
5635intel_framebuffer_create_for_mode(struct drm_device *dev,
5636 struct drm_display_mode *mode,
5637 int depth, int bpp)
5638{
5639 struct drm_i915_gem_object *obj;
5640 struct drm_mode_fb_cmd mode_cmd;
5641
5642 obj = i915_gem_alloc_object(dev,
5643 intel_framebuffer_size_for_mode(mode, bpp));
5644 if (obj == NULL)
5645 return ERR_PTR(-ENOMEM);
5646
5647 mode_cmd.width = mode->hdisplay;
5648 mode_cmd.height = mode->vdisplay;
5649 mode_cmd.depth = depth;
5650 mode_cmd.bpp = bpp;
5651 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5652
5653 return intel_framebuffer_create(dev, &mode_cmd, obj);
5654}
5655
5656static struct drm_framebuffer *
5657mode_fits_in_fbdev(struct drm_device *dev,
5658 struct drm_display_mode *mode)
5659{
5660 struct drm_i915_private *dev_priv = dev->dev_private;
5661 struct drm_i915_gem_object *obj;
5662 struct drm_framebuffer *fb;
5663
5664 if (dev_priv->fbdev == NULL)
5665 return NULL;
5666
5667 obj = dev_priv->fbdev->ifb.obj;
5668 if (obj == NULL)
5669 return NULL;
5670
5671 fb = &dev_priv->fbdev->ifb.base;
5672 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5673 fb->bits_per_pixel))
5674 return NULL;
5675
5676 if (obj->base.size < mode->vdisplay * fb->pitch)
5677 return NULL;
5678
5679 return fb;
5680}
5681
Chris Wilson71731882011-04-19 23:10:58 +01005682bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5683 struct drm_connector *connector,
5684 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01005685 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08005686{
5687 struct intel_crtc *intel_crtc;
5688 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01005689 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005690 struct drm_crtc *crtc = NULL;
5691 struct drm_device *dev = encoder->dev;
Chris Wilsond2dff872011-04-19 08:36:26 +01005692 struct drm_framebuffer *old_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08005693 int i = -1;
5694
Chris Wilsond2dff872011-04-19 08:36:26 +01005695 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5696 connector->base.id, drm_get_connector_name(connector),
5697 encoder->base.id, drm_get_encoder_name(encoder));
5698
Jesse Barnes79e53942008-11-07 14:24:08 -08005699 /*
5700 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01005701 *
Jesse Barnes79e53942008-11-07 14:24:08 -08005702 * - if the connector already has an assigned crtc, use it (but make
5703 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01005704 *
Jesse Barnes79e53942008-11-07 14:24:08 -08005705 * - try to find the first unused crtc that can drive this connector,
5706 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08005707 */
5708
5709 /* See if we already have a CRTC for this connector */
5710 if (encoder->crtc) {
5711 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01005712
Jesse Barnes79e53942008-11-07 14:24:08 -08005713 intel_crtc = to_intel_crtc(crtc);
Chris Wilson8261b192011-04-19 23:18:09 +01005714 old->dpms_mode = intel_crtc->dpms_mode;
5715 old->load_detect_temp = false;
5716
5717 /* Make sure the crtc and connector are running */
Jesse Barnes79e53942008-11-07 14:24:08 -08005718 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
Chris Wilson64927112011-04-20 07:25:26 +01005719 struct drm_encoder_helper_funcs *encoder_funcs;
5720 struct drm_crtc_helper_funcs *crtc_funcs;
5721
Jesse Barnes79e53942008-11-07 14:24:08 -08005722 crtc_funcs = crtc->helper_private;
5723 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
Chris Wilson64927112011-04-20 07:25:26 +01005724
5725 encoder_funcs = encoder->helper_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005726 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5727 }
Chris Wilson8261b192011-04-19 23:18:09 +01005728
Chris Wilson71731882011-04-19 23:10:58 +01005729 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005730 }
5731
5732 /* Find an unused one (if possible) */
5733 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5734 i++;
5735 if (!(encoder->possible_crtcs & (1 << i)))
5736 continue;
5737 if (!possible_crtc->enabled) {
5738 crtc = possible_crtc;
5739 break;
5740 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005741 }
5742
5743 /*
5744 * If we didn't find an unused CRTC, don't use any.
5745 */
5746 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01005747 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5748 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005749 }
5750
5751 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005752 connector->encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005753
5754 intel_crtc = to_intel_crtc(crtc);
Chris Wilson8261b192011-04-19 23:18:09 +01005755 old->dpms_mode = intel_crtc->dpms_mode;
5756 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01005757 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005758
Chris Wilson64927112011-04-20 07:25:26 +01005759 if (!mode)
5760 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08005761
Chris Wilsond2dff872011-04-19 08:36:26 +01005762 old_fb = crtc->fb;
5763
5764 /* We need a framebuffer large enough to accommodate all accesses
5765 * that the plane may generate whilst we perform load detection.
5766 * We can not rely on the fbcon either being present (we get called
5767 * during its initialisation to detect all boot displays, or it may
5768 * not even exist) or that it is large enough to satisfy the
5769 * requested mode.
5770 */
5771 crtc->fb = mode_fits_in_fbdev(dev, mode);
5772 if (crtc->fb == NULL) {
5773 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5774 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5775 old->release_fb = crtc->fb;
5776 } else
5777 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5778 if (IS_ERR(crtc->fb)) {
5779 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5780 crtc->fb = old_fb;
5781 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005782 }
Chris Wilsond2dff872011-04-19 08:36:26 +01005783
5784 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01005785 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01005786 if (old->release_fb)
5787 old->release_fb->funcs->destroy(old->release_fb);
5788 crtc->fb = old_fb;
Chris Wilson64927112011-04-20 07:25:26 +01005789 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005790 }
Chris Wilson71731882011-04-19 23:10:58 +01005791
Jesse Barnes79e53942008-11-07 14:24:08 -08005792 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005793 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005794
Chris Wilson71731882011-04-19 23:10:58 +01005795 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005796}
5797
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005798void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
Chris Wilson8261b192011-04-19 23:18:09 +01005799 struct drm_connector *connector,
5800 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08005801{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005802 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005803 struct drm_device *dev = encoder->dev;
5804 struct drm_crtc *crtc = encoder->crtc;
5805 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5806 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5807
Chris Wilsond2dff872011-04-19 08:36:26 +01005808 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5809 connector->base.id, drm_get_connector_name(connector),
5810 encoder->base.id, drm_get_encoder_name(encoder));
5811
Chris Wilson8261b192011-04-19 23:18:09 +01005812 if (old->load_detect_temp) {
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005813 connector->encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005814 drm_helper_disable_unused_functions(dev);
Chris Wilsond2dff872011-04-19 08:36:26 +01005815
5816 if (old->release_fb)
5817 old->release_fb->funcs->destroy(old->release_fb);
5818
Chris Wilson0622a532011-04-21 09:32:11 +01005819 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08005820 }
5821
Eric Anholtc751ce42010-03-25 11:48:48 -07005822 /* Switch crtc and encoder back off if necessary */
Chris Wilson0622a532011-04-21 09:32:11 +01005823 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5824 encoder_funcs->dpms(encoder, old->dpms_mode);
Chris Wilson8261b192011-04-19 23:18:09 +01005825 crtc_funcs->dpms(crtc, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08005826 }
5827}
5828
5829/* Returns the clock of the currently programmed mode of the given pipe. */
5830static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5831{
5832 struct drm_i915_private *dev_priv = dev->dev_private;
5833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5834 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08005835 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005836 u32 fp;
5837 intel_clock_t clock;
5838
5839 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01005840 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005841 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01005842 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005843
5844 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005845 if (IS_PINEVIEW(dev)) {
5846 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5847 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08005848 } else {
5849 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5850 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5851 }
5852
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005853 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005854 if (IS_PINEVIEW(dev))
5855 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5856 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08005857 else
5858 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08005859 DPLL_FPA01_P1_POST_DIV_SHIFT);
5860
5861 switch (dpll & DPLL_MODE_MASK) {
5862 case DPLLB_MODE_DAC_SERIAL:
5863 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5864 5 : 10;
5865 break;
5866 case DPLLB_MODE_LVDS:
5867 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5868 7 : 14;
5869 break;
5870 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08005871 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08005872 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5873 return 0;
5874 }
5875
5876 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08005877 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005878 } else {
5879 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5880
5881 if (is_lvds) {
5882 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5883 DPLL_FPA01_P1_POST_DIV_SHIFT);
5884 clock.p2 = 14;
5885
5886 if ((dpll & PLL_REF_INPUT_MASK) ==
5887 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5888 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08005889 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005890 } else
Shaohua Li21778322009-02-23 15:19:16 +08005891 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005892 } else {
5893 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5894 clock.p1 = 2;
5895 else {
5896 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5897 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5898 }
5899 if (dpll & PLL_P2_DIVIDE_BY_4)
5900 clock.p2 = 4;
5901 else
5902 clock.p2 = 2;
5903
Shaohua Li21778322009-02-23 15:19:16 +08005904 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005905 }
5906 }
5907
5908 /* XXX: It would be nice to validate the clocks, but we can't reuse
5909 * i830PllIsValid() because it relies on the xf86_config connector
5910 * configuration being accurate, which it isn't necessarily.
5911 */
5912
5913 return clock.dot;
5914}
5915
5916/** Returns the currently programmed mode of the given pipe. */
5917struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5918 struct drm_crtc *crtc)
5919{
Jesse Barnes548f2452011-02-17 10:40:53 -08005920 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5922 int pipe = intel_crtc->pipe;
5923 struct drm_display_mode *mode;
Jesse Barnes548f2452011-02-17 10:40:53 -08005924 int htot = I915_READ(HTOTAL(pipe));
5925 int hsync = I915_READ(HSYNC(pipe));
5926 int vtot = I915_READ(VTOTAL(pipe));
5927 int vsync = I915_READ(VSYNC(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005928
5929 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5930 if (!mode)
5931 return NULL;
5932
5933 mode->clock = intel_crtc_clock_get(dev, crtc);
5934 mode->hdisplay = (htot & 0xffff) + 1;
5935 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5936 mode->hsync_start = (hsync & 0xffff) + 1;
5937 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5938 mode->vdisplay = (vtot & 0xffff) + 1;
5939 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5940 mode->vsync_start = (vsync & 0xffff) + 1;
5941 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5942
5943 drm_mode_set_name(mode);
5944 drm_mode_set_crtcinfo(mode, 0);
5945
5946 return mode;
5947}
5948
Jesse Barnes652c3932009-08-17 13:31:43 -07005949#define GPU_IDLE_TIMEOUT 500 /* ms */
5950
5951/* When this timer fires, we've been idle for awhile */
5952static void intel_gpu_idle_timer(unsigned long arg)
5953{
5954 struct drm_device *dev = (struct drm_device *)arg;
5955 drm_i915_private_t *dev_priv = dev->dev_private;
5956
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005957 if (!list_empty(&dev_priv->mm.active_list)) {
5958 /* Still processing requests, so just re-arm the timer. */
5959 mod_timer(&dev_priv->idle_timer, jiffies +
5960 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5961 return;
5962 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005963
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005964 dev_priv->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07005965 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07005966}
5967
Jesse Barnes652c3932009-08-17 13:31:43 -07005968#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5969
5970static void intel_crtc_idle_timer(unsigned long arg)
5971{
5972 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5973 struct drm_crtc *crtc = &intel_crtc->base;
5974 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005975 struct intel_framebuffer *intel_fb;
5976
5977 intel_fb = to_intel_framebuffer(crtc->fb);
5978 if (intel_fb && intel_fb->obj->active) {
5979 /* The framebuffer is still being accessed by the GPU. */
5980 mod_timer(&intel_crtc->idle_timer, jiffies +
5981 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5982 return;
5983 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005984
Jesse Barnes652c3932009-08-17 13:31:43 -07005985 intel_crtc->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07005986 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07005987}
5988
Daniel Vetter3dec0092010-08-20 21:40:52 +02005989static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07005990{
5991 struct drm_device *dev = crtc->dev;
5992 drm_i915_private_t *dev_priv = dev->dev_private;
5993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005995 int dpll_reg = DPLL(pipe);
5996 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07005997
Eric Anholtbad720f2009-10-22 16:11:14 -07005998 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005999 return;
6000
6001 if (!dev_priv->lvds_downclock_avail)
6002 return;
6003
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006004 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006005 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006006 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006007
6008 /* Unlock panel regs */
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006009 I915_WRITE(PP_CONTROL,
6010 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07006011
6012 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6013 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006014 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006015
Jesse Barnes652c3932009-08-17 13:31:43 -07006016 dpll = I915_READ(dpll_reg);
6017 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08006018 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006019
6020 /* ...and lock them again */
6021 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6022 }
6023
6024 /* Schedule downclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02006025 mod_timer(&intel_crtc->idle_timer, jiffies +
6026 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07006027}
6028
6029static void intel_decrease_pllclock(struct drm_crtc *crtc)
6030{
6031 struct drm_device *dev = crtc->dev;
6032 drm_i915_private_t *dev_priv = dev->dev_private;
6033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6034 int pipe = intel_crtc->pipe;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006035 int dpll_reg = DPLL(pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006036 int dpll = I915_READ(dpll_reg);
6037
Eric Anholtbad720f2009-10-22 16:11:14 -07006038 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006039 return;
6040
6041 if (!dev_priv->lvds_downclock_avail)
6042 return;
6043
6044 /*
6045 * Since this is called by a timer, we should never get here in
6046 * the manual case.
6047 */
6048 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006049 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006050
6051 /* Unlock panel regs */
Jesse Barnes4a655f02010-07-22 13:18:18 -07006052 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6053 PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07006054
6055 dpll |= DISPLAY_RATE_SELECT_FPA1;
6056 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006057 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006058 dpll = I915_READ(dpll_reg);
6059 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08006060 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006061
6062 /* ...and lock them again */
6063 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6064 }
6065
6066}
6067
6068/**
6069 * intel_idle_update - adjust clocks for idleness
6070 * @work: work struct
6071 *
6072 * Either the GPU or display (or both) went idle. Check the busy status
6073 * here and adjust the CRTC and GPU clocks as necessary.
6074 */
6075static void intel_idle_update(struct work_struct *work)
6076{
6077 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6078 idle_work);
6079 struct drm_device *dev = dev_priv->dev;
6080 struct drm_crtc *crtc;
6081 struct intel_crtc *intel_crtc;
6082
6083 if (!i915_powersave)
6084 return;
6085
6086 mutex_lock(&dev->struct_mutex);
6087
Jesse Barnes7648fa92010-05-20 14:28:11 -07006088 i915_update_gfx_val(dev_priv);
6089
Jesse Barnes652c3932009-08-17 13:31:43 -07006090 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6091 /* Skip inactive CRTCs */
6092 if (!crtc->fb)
6093 continue;
6094
6095 intel_crtc = to_intel_crtc(crtc);
6096 if (!intel_crtc->busy)
6097 intel_decrease_pllclock(crtc);
6098 }
6099
Li Peng45ac22c2010-06-12 23:38:35 +08006100
Jesse Barnes652c3932009-08-17 13:31:43 -07006101 mutex_unlock(&dev->struct_mutex);
6102}
6103
6104/**
6105 * intel_mark_busy - mark the GPU and possibly the display busy
6106 * @dev: drm device
6107 * @obj: object we're operating on
6108 *
6109 * Callers can use this function to indicate that the GPU is busy processing
6110 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6111 * buffer), we'll also mark the display as busy, so we know to increase its
6112 * clock frequency.
6113 */
Chris Wilson05394f32010-11-08 19:18:58 +00006114void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07006115{
6116 drm_i915_private_t *dev_priv = dev->dev_private;
6117 struct drm_crtc *crtc = NULL;
6118 struct intel_framebuffer *intel_fb;
6119 struct intel_crtc *intel_crtc;
6120
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08006121 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6122 return;
6123
Alexander Lam18b21902011-01-03 13:28:56 -05006124 if (!dev_priv->busy)
Chris Wilson28cf7982009-11-30 01:08:56 +00006125 dev_priv->busy = true;
Alexander Lam18b21902011-01-03 13:28:56 -05006126 else
Chris Wilson28cf7982009-11-30 01:08:56 +00006127 mod_timer(&dev_priv->idle_timer, jiffies +
6128 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07006129
6130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6131 if (!crtc->fb)
6132 continue;
6133
6134 intel_crtc = to_intel_crtc(crtc);
6135 intel_fb = to_intel_framebuffer(crtc->fb);
6136 if (intel_fb->obj == obj) {
6137 if (!intel_crtc->busy) {
6138 /* Non-busy -> busy, upclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02006139 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006140 intel_crtc->busy = true;
6141 } else {
6142 /* Busy -> busy, put off timer */
6143 mod_timer(&intel_crtc->idle_timer, jiffies +
6144 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6145 }
6146 }
6147 }
6148}
6149
Jesse Barnes79e53942008-11-07 14:24:08 -08006150static void intel_crtc_destroy(struct drm_crtc *crtc)
6151{
6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006153 struct drm_device *dev = crtc->dev;
6154 struct intel_unpin_work *work;
6155 unsigned long flags;
6156
6157 spin_lock_irqsave(&dev->event_lock, flags);
6158 work = intel_crtc->unpin_work;
6159 intel_crtc->unpin_work = NULL;
6160 spin_unlock_irqrestore(&dev->event_lock, flags);
6161
6162 if (work) {
6163 cancel_work_sync(&work->work);
6164 kfree(work);
6165 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006166
6167 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006168
Jesse Barnes79e53942008-11-07 14:24:08 -08006169 kfree(intel_crtc);
6170}
6171
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006172static void intel_unpin_work_fn(struct work_struct *__work)
6173{
6174 struct intel_unpin_work *work =
6175 container_of(__work, struct intel_unpin_work, work);
6176
6177 mutex_lock(&work->dev->struct_mutex);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08006178 i915_gem_object_unpin(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00006179 drm_gem_object_unreference(&work->pending_flip_obj->base);
6180 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006181
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006182 mutex_unlock(&work->dev->struct_mutex);
6183 kfree(work);
6184}
6185
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006186static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01006187 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006188{
6189 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00006192 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006193 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006194 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006195 unsigned long flags;
6196
6197 /* Ignore early vblank irqs */
6198 if (intel_crtc == NULL)
6199 return;
6200
Mario Kleiner49b14a52010-12-09 07:00:07 +01006201 do_gettimeofday(&tnow);
6202
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006203 spin_lock_irqsave(&dev->event_lock, flags);
6204 work = intel_crtc->unpin_work;
6205 if (work == NULL || !work->pending) {
6206 spin_unlock_irqrestore(&dev->event_lock, flags);
6207 return;
6208 }
6209
6210 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006211
6212 if (work->event) {
6213 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006214 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006215
6216 /* Called before vblank count and timestamps have
6217 * been updated for the vblank interval of flip
6218 * completion? Need to increment vblank count and
6219 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01006220 * to account for this. We assume this happened if we
6221 * get called over 0.9 frame durations after the last
6222 * timestamped vblank.
6223 *
6224 * This calculation can not be used with vrefresh rates
6225 * below 5Hz (10Hz to be on the safe side) without
6226 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006227 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01006228 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6229 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006230 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006231 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6232 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006233 }
6234
Mario Kleiner49b14a52010-12-09 07:00:07 +01006235 e->event.tv_sec = tvbl.tv_sec;
6236 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006237
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006238 list_add_tail(&e->base.link,
6239 &e->base.file_priv->event_list);
6240 wake_up_interruptible(&e->base.file_priv->event_wait);
6241 }
6242
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006243 drm_vblank_put(dev, intel_crtc->pipe);
6244
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006245 spin_unlock_irqrestore(&dev->event_lock, flags);
6246
Chris Wilson05394f32010-11-08 19:18:58 +00006247 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00006248
Chris Wilsone59f2ba2010-10-07 17:28:15 +01006249 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00006250 &obj->pending_flip.counter);
6251 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01006252 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006253
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006254 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07006255
6256 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006257}
6258
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006259void intel_finish_page_flip(struct drm_device *dev, int pipe)
6260{
6261 drm_i915_private_t *dev_priv = dev->dev_private;
6262 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6263
Mario Kleiner49b14a52010-12-09 07:00:07 +01006264 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006265}
6266
6267void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6268{
6269 drm_i915_private_t *dev_priv = dev->dev_private;
6270 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6271
Mario Kleiner49b14a52010-12-09 07:00:07 +01006272 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006273}
6274
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006275void intel_prepare_page_flip(struct drm_device *dev, int plane)
6276{
6277 drm_i915_private_t *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc =
6279 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6280 unsigned long flags;
6281
6282 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08006283 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006284 if ((++intel_crtc->unpin_work->pending) > 1)
6285 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08006286 } else {
6287 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6288 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006289 spin_unlock_irqrestore(&dev->event_lock, flags);
6290}
6291
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006292static int intel_gen2_queue_flip(struct drm_device *dev,
6293 struct drm_crtc *crtc,
6294 struct drm_framebuffer *fb,
6295 struct drm_i915_gem_object *obj)
6296{
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299 unsigned long offset;
6300 u32 flip_mask;
6301 int ret;
6302
6303 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6304 if (ret)
6305 goto out;
6306
6307 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6308 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6309
6310 ret = BEGIN_LP_RING(6);
6311 if (ret)
6312 goto out;
6313
6314 /* Can't queue multiple flips, so wait for the previous
6315 * one to finish before executing the next.
6316 */
6317 if (intel_crtc->plane)
6318 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6319 else
6320 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6321 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6322 OUT_RING(MI_NOOP);
6323 OUT_RING(MI_DISPLAY_FLIP |
6324 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6325 OUT_RING(fb->pitch);
6326 OUT_RING(obj->gtt_offset + offset);
6327 OUT_RING(MI_NOOP);
6328 ADVANCE_LP_RING();
6329out:
6330 return ret;
6331}
6332
6333static int intel_gen3_queue_flip(struct drm_device *dev,
6334 struct drm_crtc *crtc,
6335 struct drm_framebuffer *fb,
6336 struct drm_i915_gem_object *obj)
6337{
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6340 unsigned long offset;
6341 u32 flip_mask;
6342 int ret;
6343
6344 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6345 if (ret)
6346 goto out;
6347
6348 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6349 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6350
6351 ret = BEGIN_LP_RING(6);
6352 if (ret)
6353 goto out;
6354
6355 if (intel_crtc->plane)
6356 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6357 else
6358 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6359 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6360 OUT_RING(MI_NOOP);
6361 OUT_RING(MI_DISPLAY_FLIP_I915 |
6362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6363 OUT_RING(fb->pitch);
6364 OUT_RING(obj->gtt_offset + offset);
6365 OUT_RING(MI_NOOP);
6366
6367 ADVANCE_LP_RING();
6368out:
6369 return ret;
6370}
6371
6372static int intel_gen4_queue_flip(struct drm_device *dev,
6373 struct drm_crtc *crtc,
6374 struct drm_framebuffer *fb,
6375 struct drm_i915_gem_object *obj)
6376{
6377 struct drm_i915_private *dev_priv = dev->dev_private;
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379 uint32_t pf, pipesrc;
6380 int ret;
6381
6382 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6383 if (ret)
6384 goto out;
6385
6386 ret = BEGIN_LP_RING(4);
6387 if (ret)
6388 goto out;
6389
6390 /* i965+ uses the linear or tiled offsets from the
6391 * Display Registers (which do not change across a page-flip)
6392 * so we need only reprogram the base address.
6393 */
6394 OUT_RING(MI_DISPLAY_FLIP |
6395 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6396 OUT_RING(fb->pitch);
6397 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6398
6399 /* XXX Enabling the panel-fitter across page-flip is so far
6400 * untested on non-native modes, so ignore it for now.
6401 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6402 */
6403 pf = 0;
6404 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6405 OUT_RING(pf | pipesrc);
6406 ADVANCE_LP_RING();
6407out:
6408 return ret;
6409}
6410
6411static int intel_gen6_queue_flip(struct drm_device *dev,
6412 struct drm_crtc *crtc,
6413 struct drm_framebuffer *fb,
6414 struct drm_i915_gem_object *obj)
6415{
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418 uint32_t pf, pipesrc;
6419 int ret;
6420
6421 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6422 if (ret)
6423 goto out;
6424
6425 ret = BEGIN_LP_RING(4);
6426 if (ret)
6427 goto out;
6428
6429 OUT_RING(MI_DISPLAY_FLIP |
6430 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6431 OUT_RING(fb->pitch | obj->tiling_mode);
6432 OUT_RING(obj->gtt_offset);
6433
6434 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6435 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6436 OUT_RING(pf | pipesrc);
6437 ADVANCE_LP_RING();
6438out:
6439 return ret;
6440}
6441
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006442/*
6443 * On gen7 we currently use the blit ring because (in early silicon at least)
6444 * the render ring doesn't give us interrpts for page flip completion, which
6445 * means clients will hang after the first flip is queued. Fortunately the
6446 * blit ring generates interrupts properly, so use it instead.
6447 */
6448static int intel_gen7_queue_flip(struct drm_device *dev,
6449 struct drm_crtc *crtc,
6450 struct drm_framebuffer *fb,
6451 struct drm_i915_gem_object *obj)
6452{
6453 struct drm_i915_private *dev_priv = dev->dev_private;
6454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6455 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6456 int ret;
6457
6458 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6459 if (ret)
6460 goto out;
6461
6462 ret = intel_ring_begin(ring, 4);
6463 if (ret)
6464 goto out;
6465
6466 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6467 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6468 intel_ring_emit(ring, (obj->gtt_offset));
6469 intel_ring_emit(ring, (MI_NOOP));
6470 intel_ring_advance(ring);
6471out:
6472 return ret;
6473}
6474
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006475static int intel_default_queue_flip(struct drm_device *dev,
6476 struct drm_crtc *crtc,
6477 struct drm_framebuffer *fb,
6478 struct drm_i915_gem_object *obj)
6479{
6480 return -ENODEV;
6481}
6482
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006483static int intel_crtc_page_flip(struct drm_crtc *crtc,
6484 struct drm_framebuffer *fb,
6485 struct drm_pending_vblank_event *event)
6486{
6487 struct drm_device *dev = crtc->dev;
6488 struct drm_i915_private *dev_priv = dev->dev_private;
6489 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00006490 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006493 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01006494 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006495
6496 work = kzalloc(sizeof *work, GFP_KERNEL);
6497 if (work == NULL)
6498 return -ENOMEM;
6499
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006500 work->event = event;
6501 work->dev = crtc->dev;
6502 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08006503 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006504 INIT_WORK(&work->work, intel_unpin_work_fn);
6505
6506 /* We borrow the event spin lock for protecting unpin_work */
6507 spin_lock_irqsave(&dev->event_lock, flags);
6508 if (intel_crtc->unpin_work) {
6509 spin_unlock_irqrestore(&dev->event_lock, flags);
6510 kfree(work);
Chris Wilson468f0b42010-05-27 13:18:13 +01006511
6512 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006513 return -EBUSY;
6514 }
6515 intel_crtc->unpin_work = work;
6516 spin_unlock_irqrestore(&dev->event_lock, flags);
6517
6518 intel_fb = to_intel_framebuffer(fb);
6519 obj = intel_fb->obj;
6520
Chris Wilson468f0b42010-05-27 13:18:13 +01006521 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006522
Jesse Barnes75dfca82010-02-10 15:09:44 -08006523 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00006524 drm_gem_object_reference(&work->old_fb_obj->base);
6525 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006526
6527 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01006528
6529 ret = drm_vblank_get(dev, intel_crtc->pipe);
6530 if (ret)
6531 goto cleanup_objs;
6532
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006533 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006534
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006535 work->enable_stall_check = true;
6536
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006537 /* Block clients from rendering to the new back buffer until
6538 * the flip occurs and the object is no longer visible.
6539 */
Chris Wilson05394f32010-11-08 19:18:58 +00006540 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006541
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006542 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6543 if (ret)
6544 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006545
6546 mutex_unlock(&dev->struct_mutex);
6547
Jesse Barnese5510fa2010-07-01 16:48:37 -07006548 trace_i915_flip_request(intel_crtc->plane, obj);
6549
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006550 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01006551
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006552cleanup_pending:
6553 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilson96b099f2010-06-07 14:03:04 +01006554cleanup_objs:
Chris Wilson05394f32010-11-08 19:18:58 +00006555 drm_gem_object_unreference(&work->old_fb_obj->base);
6556 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01006557 mutex_unlock(&dev->struct_mutex);
6558
6559 spin_lock_irqsave(&dev->event_lock, flags);
6560 intel_crtc->unpin_work = NULL;
6561 spin_unlock_irqrestore(&dev->event_lock, flags);
6562
6563 kfree(work);
6564
6565 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006566}
6567
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006568static void intel_sanitize_modesetting(struct drm_device *dev,
6569 int pipe, int plane)
6570{
6571 struct drm_i915_private *dev_priv = dev->dev_private;
6572 u32 reg, val;
6573
6574 if (HAS_PCH_SPLIT(dev))
6575 return;
6576
6577 /* Who knows what state these registers were left in by the BIOS or
6578 * grub?
6579 *
6580 * If we leave the registers in a conflicting state (e.g. with the
6581 * display plane reading from the other pipe than the one we intend
6582 * to use) then when we attempt to teardown the active mode, we will
6583 * not disable the pipes and planes in the correct order -- leaving
6584 * a plane reading from a disabled pipe and possibly leading to
6585 * undefined behaviour.
6586 */
6587
6588 reg = DSPCNTR(plane);
6589 val = I915_READ(reg);
6590
6591 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6592 return;
6593 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6594 return;
6595
6596 /* This display plane is active and attached to the other CPU pipe. */
6597 pipe = !pipe;
6598
6599 /* Disable the plane and wait for it to stop reading from the pipe. */
Jesse Barnesb24e7172011-01-04 15:09:30 -08006600 intel_disable_plane(dev_priv, plane, pipe);
6601 intel_disable_pipe(dev_priv, pipe);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006602}
Jesse Barnes79e53942008-11-07 14:24:08 -08006603
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006604static void intel_crtc_reset(struct drm_crtc *crtc)
6605{
6606 struct drm_device *dev = crtc->dev;
6607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6608
6609 /* Reset flags back to the 'unknown' status so that they
6610 * will be correctly set on the initial modeset.
6611 */
6612 intel_crtc->dpms_mode = -1;
6613
6614 /* We need to fix up any BIOS configuration that conflicts with
6615 * our expectations.
6616 */
6617 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6618}
6619
6620static struct drm_crtc_helper_funcs intel_helper_funcs = {
6621 .dpms = intel_crtc_dpms,
6622 .mode_fixup = intel_crtc_mode_fixup,
6623 .mode_set = intel_crtc_mode_set,
6624 .mode_set_base = intel_pipe_set_base,
6625 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6626 .load_lut = intel_crtc_load_lut,
6627 .disable = intel_crtc_disable,
6628};
6629
6630static const struct drm_crtc_funcs intel_crtc_funcs = {
6631 .reset = intel_crtc_reset,
6632 .cursor_set = intel_crtc_cursor_set,
6633 .cursor_move = intel_crtc_cursor_move,
6634 .gamma_set = intel_crtc_gamma_set,
6635 .set_config = drm_crtc_helper_set_config,
6636 .destroy = intel_crtc_destroy,
6637 .page_flip = intel_crtc_page_flip,
6638};
6639
Hannes Ederb358d0a2008-12-18 21:18:47 +01006640static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08006641{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006642 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006643 struct intel_crtc *intel_crtc;
6644 int i;
6645
6646 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6647 if (intel_crtc == NULL)
6648 return;
6649
6650 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6651
6652 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08006653 for (i = 0; i < 256; i++) {
6654 intel_crtc->lut_r[i] = i;
6655 intel_crtc->lut_g[i] = i;
6656 intel_crtc->lut_b[i] = i;
6657 }
6658
Jesse Barnes80824002009-09-10 15:28:06 -07006659 /* Swap pipes & planes for FBC on pre-965 */
6660 intel_crtc->pipe = pipe;
6661 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01006662 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006663 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01006664 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07006665 }
6666
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006667 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6668 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6669 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6670 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6671
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00006672 intel_crtc_reset(&intel_crtc->base);
Chris Wilson04dbff52011-02-10 17:38:35 +00006673 intel_crtc->active = true; /* force the pipe off on setup_init_config */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07006674
6675 if (HAS_PCH_SPLIT(dev)) {
6676 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6677 intel_helper_funcs.commit = ironlake_crtc_commit;
6678 } else {
6679 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6680 intel_helper_funcs.commit = i9xx_crtc_commit;
6681 }
6682
Jesse Barnes79e53942008-11-07 14:24:08 -08006683 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6684
Jesse Barnes652c3932009-08-17 13:31:43 -07006685 intel_crtc->busy = false;
6686
6687 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6688 (unsigned long)intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006689}
6690
Carl Worth08d7b3d2009-04-29 14:43:54 -07006691int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00006692 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07006693{
6694 drm_i915_private_t *dev_priv = dev->dev_private;
6695 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02006696 struct drm_mode_object *drmmode_obj;
6697 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006698
6699 if (!dev_priv) {
6700 DRM_ERROR("called with no initialization\n");
6701 return -EINVAL;
6702 }
6703
Daniel Vetterc05422d2009-08-11 16:05:30 +02006704 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6705 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07006706
Daniel Vetterc05422d2009-08-11 16:05:30 +02006707 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07006708 DRM_ERROR("no such CRTC id\n");
6709 return -EINVAL;
6710 }
6711
Daniel Vetterc05422d2009-08-11 16:05:30 +02006712 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6713 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006714
Daniel Vetterc05422d2009-08-11 16:05:30 +02006715 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006716}
6717
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08006718static int intel_encoder_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08006719{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006720 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006721 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006722 int entry = 0;
6723
Chris Wilson4ef69c72010-09-09 15:14:28 +01006724 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6725 if (type_mask & encoder->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08006726 index_mask |= (1 << entry);
6727 entry++;
6728 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01006729
Jesse Barnes79e53942008-11-07 14:24:08 -08006730 return index_mask;
6731}
6732
Chris Wilson4d302442010-12-14 19:21:29 +00006733static bool has_edp_a(struct drm_device *dev)
6734{
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736
6737 if (!IS_MOBILE(dev))
6738 return false;
6739
6740 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6741 return false;
6742
6743 if (IS_GEN5(dev) &&
6744 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6745 return false;
6746
6747 return true;
6748}
6749
Jesse Barnes79e53942008-11-07 14:24:08 -08006750static void intel_setup_outputs(struct drm_device *dev)
6751{
Eric Anholt725e30a2009-01-22 13:01:02 -08006752 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006753 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006754 bool dpd_is_edp = false;
Chris Wilsonc5d1b512010-11-29 18:00:23 +00006755 bool has_lvds = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006756
Zhenyu Wang541998a2009-06-05 15:38:44 +08006757 if (IS_MOBILE(dev) && !IS_I830(dev))
Chris Wilsonc5d1b512010-11-29 18:00:23 +00006758 has_lvds = intel_lvds_init(dev);
6759 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6760 /* disable the panel fitter on everything but LVDS */
6761 I915_WRITE(PFIT_CONTROL, 0);
6762 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006763
Eric Anholtbad720f2009-10-22 16:11:14 -07006764 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006765 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006766
Chris Wilson4d302442010-12-14 19:21:29 +00006767 if (has_edp_a(dev))
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006768 intel_dp_init(dev, DP_A);
6769
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006770 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6771 intel_dp_init(dev, PCH_DP_D);
6772 }
6773
6774 intel_crt_init(dev);
6775
6776 if (HAS_PCH_SPLIT(dev)) {
6777 int found;
6778
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006779 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08006780 /* PCH SDVOB multiplex with HDMIB */
6781 found = intel_sdvo_init(dev, PCH_SDVOB);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006782 if (!found)
6783 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006784 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6785 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006786 }
6787
6788 if (I915_READ(HDMIC) & PORT_DETECTED)
6789 intel_hdmi_init(dev, HDMIC);
6790
6791 if (I915_READ(HDMID) & PORT_DETECTED)
6792 intel_hdmi_init(dev, HDMID);
6793
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006794 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6795 intel_dp_init(dev, PCH_DP_C);
6796
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006797 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006798 intel_dp_init(dev, PCH_DP_D);
6799
Zhenyu Wang103a1962009-11-27 11:44:36 +08006800 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08006801 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08006802
Eric Anholt725e30a2009-01-22 13:01:02 -08006803 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006804 DRM_DEBUG_KMS("probing SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006805 found = intel_sdvo_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006806 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6807 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006808 intel_hdmi_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006809 }
Ma Ling27185ae2009-08-24 13:50:23 +08006810
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006811 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6812 DRM_DEBUG_KMS("probing DP_B\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006813 intel_dp_init(dev, DP_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006814 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006815 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006816
6817 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006818
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006819 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6820 DRM_DEBUG_KMS("probing SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006821 found = intel_sdvo_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006822 }
Ma Ling27185ae2009-08-24 13:50:23 +08006823
6824 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6825
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006826 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6827 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006828 intel_hdmi_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006829 }
6830 if (SUPPORTS_INTEGRATED_DP(dev)) {
6831 DRM_DEBUG_KMS("probing DP_C\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006832 intel_dp_init(dev, DP_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006833 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006834 }
Ma Ling27185ae2009-08-24 13:50:23 +08006835
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006836 if (SUPPORTS_INTEGRATED_DP(dev) &&
6837 (I915_READ(DP_D) & DP_DETECTED)) {
6838 DRM_DEBUG_KMS("probing DP_D\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006839 intel_dp_init(dev, DP_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006840 }
Eric Anholtbad720f2009-10-22 16:11:14 -07006841 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006842 intel_dvo_init(dev);
6843
Zhenyu Wang103a1962009-11-27 11:44:36 +08006844 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006845 intel_tv_init(dev);
6846
Chris Wilson4ef69c72010-09-09 15:14:28 +01006847 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6848 encoder->base.possible_crtcs = encoder->crtc_mask;
6849 encoder->base.possible_clones =
6850 intel_encoder_clones(dev, encoder->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08006851 }
Chris Wilson47356eb2011-01-11 17:06:04 +00006852
6853 intel_panel_setup_backlight(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01006854
6855 /* disable all the possible outputs/crtcs before entering KMS mode */
6856 drm_helper_disable_unused_functions(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006857}
6858
6859static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6860{
6861 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08006862
6863 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006864 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08006865
6866 kfree(intel_fb);
6867}
6868
6869static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00006870 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006871 unsigned int *handle)
6872{
6873 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006874 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006875
Chris Wilson05394f32010-11-08 19:18:58 +00006876 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08006877}
6878
6879static const struct drm_framebuffer_funcs intel_fb_funcs = {
6880 .destroy = intel_user_framebuffer_destroy,
6881 .create_handle = intel_user_framebuffer_create_handle,
6882};
6883
Dave Airlie38651672010-03-30 05:34:13 +00006884int intel_framebuffer_init(struct drm_device *dev,
6885 struct intel_framebuffer *intel_fb,
6886 struct drm_mode_fb_cmd *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00006887 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08006888{
Jesse Barnes79e53942008-11-07 14:24:08 -08006889 int ret;
6890
Chris Wilson05394f32010-11-08 19:18:58 +00006891 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01006892 return -EINVAL;
6893
6894 if (mode_cmd->pitch & 63)
6895 return -EINVAL;
6896
6897 switch (mode_cmd->bpp) {
6898 case 8:
6899 case 16:
6900 case 24:
6901 case 32:
6902 break;
6903 default:
6904 return -EINVAL;
6905 }
6906
Jesse Barnes79e53942008-11-07 14:24:08 -08006907 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6908 if (ret) {
6909 DRM_ERROR("framebuffer init failed %d\n", ret);
6910 return ret;
6911 }
6912
6913 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08006914 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006915 return 0;
6916}
6917
Jesse Barnes79e53942008-11-07 14:24:08 -08006918static struct drm_framebuffer *
6919intel_user_framebuffer_create(struct drm_device *dev,
6920 struct drm_file *filp,
6921 struct drm_mode_fb_cmd *mode_cmd)
6922{
Chris Wilson05394f32010-11-08 19:18:58 +00006923 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006924
Chris Wilson05394f32010-11-08 19:18:58 +00006925 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006926 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006927 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08006928
Chris Wilsond2dff872011-04-19 08:36:26 +01006929 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08006930}
6931
Jesse Barnes79e53942008-11-07 14:24:08 -08006932static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08006933 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00006934 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08006935};
6936
Chris Wilson05394f32010-11-08 19:18:58 +00006937static struct drm_i915_gem_object *
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006938intel_alloc_context_page(struct drm_device *dev)
Chris Wilson9ea8d052010-01-04 18:57:56 +00006939{
Chris Wilson05394f32010-11-08 19:18:58 +00006940 struct drm_i915_gem_object *ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00006941 int ret;
6942
Ben Widawsky2c34b852011-03-19 18:14:26 -07006943 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6944
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006945 ctx = i915_gem_alloc_object(dev, 4096);
6946 if (!ctx) {
Chris Wilson9ea8d052010-01-04 18:57:56 +00006947 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6948 return NULL;
6949 }
6950
Daniel Vetter75e9e912010-11-04 17:11:09 +01006951 ret = i915_gem_object_pin(ctx, 4096, true);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006952 if (ret) {
6953 DRM_ERROR("failed to pin power context: %d\n", ret);
6954 goto err_unref;
6955 }
6956
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006957 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006958 if (ret) {
6959 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6960 goto err_unpin;
6961 }
Chris Wilson9ea8d052010-01-04 18:57:56 +00006962
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006963 return ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00006964
6965err_unpin:
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006966 i915_gem_object_unpin(ctx);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006967err_unref:
Chris Wilson05394f32010-11-08 19:18:58 +00006968 drm_gem_object_unreference(&ctx->base);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006969 mutex_unlock(&dev->struct_mutex);
6970 return NULL;
6971}
6972
Jesse Barnes7648fa92010-05-20 14:28:11 -07006973bool ironlake_set_drps(struct drm_device *dev, u8 val)
6974{
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6976 u16 rgvswctl;
6977
6978 rgvswctl = I915_READ16(MEMSWCTL);
6979 if (rgvswctl & MEMCTL_CMD_STS) {
6980 DRM_DEBUG("gpu busy, RCS change rejected\n");
6981 return false; /* still busy with another command */
6982 }
6983
6984 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6985 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6986 I915_WRITE16(MEMSWCTL, rgvswctl);
6987 POSTING_READ16(MEMSWCTL);
6988
6989 rgvswctl |= MEMCTL_CMD_STS;
6990 I915_WRITE16(MEMSWCTL, rgvswctl);
6991
6992 return true;
6993}
6994
Jesse Barnesf97108d2010-01-29 11:27:07 -08006995void ironlake_enable_drps(struct drm_device *dev)
6996{
6997 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07006998 u32 rgvmodectl = I915_READ(MEMMODECTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006999 u8 fmax, fmin, fstart, vstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08007000
Jesse Barnesea056c12010-09-10 10:02:13 -07007001 /* Enable temp reporting */
7002 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7003 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7004
Jesse Barnesf97108d2010-01-29 11:27:07 -08007005 /* 100ms RC evaluation intervals */
7006 I915_WRITE(RCUPEI, 100000);
7007 I915_WRITE(RCDNEI, 100000);
7008
7009 /* Set max/min thresholds to 90ms and 80ms respectively */
7010 I915_WRITE(RCBMAXAVG, 90000);
7011 I915_WRITE(RCBMINAVG, 80000);
7012
7013 I915_WRITE(MEMIHYST, 1);
7014
7015 /* Set up min, max, and cur for interrupt handling */
7016 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7017 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7018 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7019 MEMMODE_FSTART_SHIFT;
Jesse Barnes7648fa92010-05-20 14:28:11 -07007020
Jesse Barnesf97108d2010-01-29 11:27:07 -08007021 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7022 PXVFREQ_PX_SHIFT;
7023
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07007024 dev_priv->fmax = fmax; /* IPS callback will increase this */
Jesse Barnes7648fa92010-05-20 14:28:11 -07007025 dev_priv->fstart = fstart;
7026
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07007027 dev_priv->max_delay = fstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08007028 dev_priv->min_delay = fmin;
7029 dev_priv->cur_delay = fstart;
7030
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07007031 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7032 fmax, fmin, fstart);
Jesse Barnes7648fa92010-05-20 14:28:11 -07007033
Jesse Barnesf97108d2010-01-29 11:27:07 -08007034 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7035
7036 /*
7037 * Interrupts will be enabled in ironlake_irq_postinstall
7038 */
7039
7040 I915_WRITE(VIDSTART, vstart);
7041 POSTING_READ(VIDSTART);
7042
7043 rgvmodectl |= MEMMODE_SWMODE_EN;
7044 I915_WRITE(MEMMODECTL, rgvmodectl);
7045
Chris Wilson481b6af2010-08-23 17:43:35 +01007046 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
Chris Wilson913d8d12010-08-07 11:01:35 +01007047 DRM_ERROR("stuck trying to change perf mode\n");
Jesse Barnesf97108d2010-01-29 11:27:07 -08007048 msleep(1);
7049
Jesse Barnes7648fa92010-05-20 14:28:11 -07007050 ironlake_set_drps(dev, fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007051
Jesse Barnes7648fa92010-05-20 14:28:11 -07007052 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7053 I915_READ(0x112e0);
7054 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7055 dev_priv->last_count2 = I915_READ(0x112f4);
7056 getrawmonotonic(&dev_priv->last_time2);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007057}
7058
7059void ironlake_disable_drps(struct drm_device *dev)
7060{
7061 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07007062 u16 rgvswctl = I915_READ16(MEMSWCTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007063
7064 /* Ack interrupts, disable EFC interrupt */
7065 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7066 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7067 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7068 I915_WRITE(DEIIR, DE_PCU_EVENT);
7069 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7070
7071 /* Go back to the starting frequency */
Jesse Barnes7648fa92010-05-20 14:28:11 -07007072 ironlake_set_drps(dev, dev_priv->fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007073 msleep(1);
7074 rgvswctl |= MEMCTL_CMD_STS;
7075 I915_WRITE(MEMSWCTL, rgvswctl);
7076 msleep(1);
7077
7078}
7079
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007080void gen6_set_rps(struct drm_device *dev, u8 val)
7081{
7082 struct drm_i915_private *dev_priv = dev->dev_private;
7083 u32 swreq;
7084
7085 swreq = (val & 0x3ff) << 25;
7086 I915_WRITE(GEN6_RPNSWREQ, swreq);
7087}
7088
7089void gen6_disable_rps(struct drm_device *dev)
7090{
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092
7093 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7094 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7095 I915_WRITE(GEN6_PMIER, 0);
Ben Widawsky4912d042011-04-25 11:25:20 -07007096
7097 spin_lock_irq(&dev_priv->rps_lock);
7098 dev_priv->pm_iir = 0;
7099 spin_unlock_irq(&dev_priv->rps_lock);
7100
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007101 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7102}
7103
Jesse Barnes7648fa92010-05-20 14:28:11 -07007104static unsigned long intel_pxfreq(u32 vidfreq)
7105{
7106 unsigned long freq;
7107 int div = (vidfreq & 0x3f0000) >> 16;
7108 int post = (vidfreq & 0x3000) >> 12;
7109 int pre = (vidfreq & 0x7);
7110
7111 if (!pre)
7112 return 0;
7113
7114 freq = ((div * 133333) / ((1<<post) * pre));
7115
7116 return freq;
7117}
7118
7119void intel_init_emon(struct drm_device *dev)
7120{
7121 struct drm_i915_private *dev_priv = dev->dev_private;
7122 u32 lcfuse;
7123 u8 pxw[16];
7124 int i;
7125
7126 /* Disable to program */
7127 I915_WRITE(ECR, 0);
7128 POSTING_READ(ECR);
7129
7130 /* Program energy weights for various events */
7131 I915_WRITE(SDEW, 0x15040d00);
7132 I915_WRITE(CSIEW0, 0x007f0000);
7133 I915_WRITE(CSIEW1, 0x1e220004);
7134 I915_WRITE(CSIEW2, 0x04000004);
7135
7136 for (i = 0; i < 5; i++)
7137 I915_WRITE(PEW + (i * 4), 0);
7138 for (i = 0; i < 3; i++)
7139 I915_WRITE(DEW + (i * 4), 0);
7140
7141 /* Program P-state weights to account for frequency power adjustment */
7142 for (i = 0; i < 16; i++) {
7143 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7144 unsigned long freq = intel_pxfreq(pxvidfreq);
7145 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7146 PXVFREQ_PX_SHIFT;
7147 unsigned long val;
7148
7149 val = vid * vid;
7150 val *= (freq / 1000);
7151 val *= 255;
7152 val /= (127*127*900);
7153 if (val > 0xff)
7154 DRM_ERROR("bad pxval: %ld\n", val);
7155 pxw[i] = val;
7156 }
7157 /* Render standby states get 0 weight */
7158 pxw[14] = 0;
7159 pxw[15] = 0;
7160
7161 for (i = 0; i < 4; i++) {
7162 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7163 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7164 I915_WRITE(PXW + (i * 4), val);
7165 }
7166
7167 /* Adjust magic regs to magic values (more experimental results) */
7168 I915_WRITE(OGW0, 0);
7169 I915_WRITE(OGW1, 0);
7170 I915_WRITE(EG0, 0x00007f00);
7171 I915_WRITE(EG1, 0x0000000e);
7172 I915_WRITE(EG2, 0x000e0000);
7173 I915_WRITE(EG3, 0x68000300);
7174 I915_WRITE(EG4, 0x42000000);
7175 I915_WRITE(EG5, 0x00140031);
7176 I915_WRITE(EG6, 0);
7177 I915_WRITE(EG7, 0);
7178
7179 for (i = 0; i < 8; i++)
7180 I915_WRITE(PXWL + (i * 4), 0);
7181
7182 /* Enable PMON + select events */
7183 I915_WRITE(ECR, 0x80000019);
7184
7185 lcfuse = I915_READ(LCFUSE02);
7186
7187 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7188}
7189
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007190void gen6_enable_rps(struct drm_i915_private *dev_priv)
Chris Wilson8fd26852010-12-08 18:40:43 +00007191{
Jesse Barnesa6044e22010-12-20 11:34:20 -08007192 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7193 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
Jesse Barnes7df87212011-03-30 14:08:56 -07007194 u32 pcu_mbox, rc6_mask = 0;
Jesse Barnesa6044e22010-12-20 11:34:20 -08007195 int cur_freq, min_freq, max_freq;
Chris Wilson8fd26852010-12-08 18:40:43 +00007196 int i;
7197
7198 /* Here begins a magic sequence of register writes to enable
7199 * auto-downclocking.
7200 *
7201 * Perhaps there might be some value in exposing these to
7202 * userspace...
7203 */
7204 I915_WRITE(GEN6_RC_STATE, 0);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01007205 mutex_lock(&dev_priv->dev->struct_mutex);
Ben Widawskyfcca7922011-04-25 11:23:07 -07007206 gen6_gt_force_wake_get(dev_priv);
Chris Wilson8fd26852010-12-08 18:40:43 +00007207
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007208 /* disable the counters and set deterministic thresholds */
Chris Wilson8fd26852010-12-08 18:40:43 +00007209 I915_WRITE(GEN6_RC_CONTROL, 0);
7210
7211 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7212 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7213 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7214 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7215 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7216
7217 for (i = 0; i < I915_NUM_RINGS; i++)
7218 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7219
7220 I915_WRITE(GEN6_RC_SLEEP, 0);
7221 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7222 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7223 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7224 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7225
Jesse Barnes7df87212011-03-30 14:08:56 -07007226 if (i915_enable_rc6)
7227 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7228 GEN6_RC_CTL_RC6_ENABLE;
7229
Chris Wilson8fd26852010-12-08 18:40:43 +00007230 I915_WRITE(GEN6_RC_CONTROL,
Jesse Barnes7df87212011-03-30 14:08:56 -07007231 rc6_mask |
Chris Wilson9c3d2f72010-12-17 10:54:26 +00007232 GEN6_RC_CTL_EI_MODE(1) |
Chris Wilson8fd26852010-12-08 18:40:43 +00007233 GEN6_RC_CTL_HW_ENABLE);
7234
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007235 I915_WRITE(GEN6_RPNSWREQ,
Chris Wilson8fd26852010-12-08 18:40:43 +00007236 GEN6_FREQUENCY(10) |
7237 GEN6_OFFSET(0) |
7238 GEN6_AGGRESSIVE_TURBO);
7239 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7240 GEN6_FREQUENCY(12));
7241
7242 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7243 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7244 18 << 24 |
7245 6 << 16);
Jesse Barnesccab5c82011-01-18 15:49:25 -08007246 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7247 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00007248 I915_WRITE(GEN6_RP_UP_EI, 100000);
Jesse Barnesccab5c82011-01-18 15:49:25 -08007249 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00007250 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7251 I915_WRITE(GEN6_RP_CONTROL,
7252 GEN6_RP_MEDIA_TURBO |
7253 GEN6_RP_USE_NORMAL_FREQ |
7254 GEN6_RP_MEDIA_IS_GFX |
7255 GEN6_RP_ENABLE |
Jesse Barnesccab5c82011-01-18 15:49:25 -08007256 GEN6_RP_UP_BUSY_AVG |
7257 GEN6_RP_DOWN_IDLE_CONT);
Chris Wilson8fd26852010-12-08 18:40:43 +00007258
7259 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7260 500))
7261 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7262
7263 I915_WRITE(GEN6_PCODE_DATA, 0);
7264 I915_WRITE(GEN6_PCODE_MAILBOX,
7265 GEN6_PCODE_READY |
7266 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7267 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7268 500))
7269 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7270
Jesse Barnesa6044e22010-12-20 11:34:20 -08007271 min_freq = (rp_state_cap & 0xff0000) >> 16;
7272 max_freq = rp_state_cap & 0xff;
7273 cur_freq = (gt_perf_status & 0xff00) >> 8;
7274
7275 /* Check for overclock support */
7276 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7277 500))
7278 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7279 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7280 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7281 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7282 500))
7283 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7284 if (pcu_mbox & (1<<31)) { /* OC supported */
7285 max_freq = pcu_mbox & 0xff;
Jesse Barnese281fca2011-03-18 10:32:07 -07007286 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
Jesse Barnesa6044e22010-12-20 11:34:20 -08007287 }
7288
7289 /* In units of 100MHz */
7290 dev_priv->max_delay = max_freq;
7291 dev_priv->min_delay = min_freq;
7292 dev_priv->cur_delay = cur_freq;
7293
Chris Wilson8fd26852010-12-08 18:40:43 +00007294 /* requires MSI enabled */
7295 I915_WRITE(GEN6_PMIER,
7296 GEN6_PM_MBOX_EVENT |
7297 GEN6_PM_THERMAL_EVENT |
7298 GEN6_PM_RP_DOWN_TIMEOUT |
7299 GEN6_PM_RP_UP_THRESHOLD |
7300 GEN6_PM_RP_DOWN_THRESHOLD |
7301 GEN6_PM_RP_UP_EI_EXPIRED |
7302 GEN6_PM_RP_DOWN_EI_EXPIRED);
Ben Widawsky4912d042011-04-25 11:25:20 -07007303 spin_lock_irq(&dev_priv->rps_lock);
7304 WARN_ON(dev_priv->pm_iir != 0);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007305 I915_WRITE(GEN6_PMIMR, 0);
Ben Widawsky4912d042011-04-25 11:25:20 -07007306 spin_unlock_irq(&dev_priv->rps_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007307 /* enable all PM interrupts */
7308 I915_WRITE(GEN6_PMINTRMSK, 0);
Chris Wilson8fd26852010-12-08 18:40:43 +00007309
Ben Widawskyfcca7922011-04-25 11:23:07 -07007310 gen6_gt_force_wake_put(dev_priv);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01007311 mutex_unlock(&dev_priv->dev->struct_mutex);
Chris Wilson8fd26852010-12-08 18:40:43 +00007312}
7313
Jesse Barnes6067aae2011-04-28 15:04:31 -07007314static void ironlake_init_clock_gating(struct drm_device *dev)
7315{
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7318
7319 /* Required for FBC */
7320 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7321 DPFCRUNIT_CLOCK_GATE_DISABLE |
7322 DPFDUNIT_CLOCK_GATE_DISABLE;
7323 /* Required for CxSR */
7324 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7325
7326 I915_WRITE(PCH_3DCGDIS0,
7327 MARIUNIT_CLOCK_GATE_DISABLE |
7328 SVSMUNIT_CLOCK_GATE_DISABLE);
7329 I915_WRITE(PCH_3DCGDIS1,
7330 VFMUNIT_CLOCK_GATE_DISABLE);
7331
7332 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7333
7334 /*
Jesse Barnes6067aae2011-04-28 15:04:31 -07007335 * According to the spec the following bits should be set in
7336 * order to enable memory self-refresh
7337 * The bit 22/21 of 0x42004
7338 * The bit 5 of 0x42020
7339 * The bit 15 of 0x45000
7340 */
7341 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7342 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7343 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7344 I915_WRITE(ILK_DSPCLK_GATE,
7345 (I915_READ(ILK_DSPCLK_GATE) |
7346 ILK_DPARB_CLK_GATE));
7347 I915_WRITE(DISP_ARB_CTL,
7348 (I915_READ(DISP_ARB_CTL) |
7349 DISP_FBC_WM_DIS));
7350 I915_WRITE(WM3_LP_ILK, 0);
7351 I915_WRITE(WM2_LP_ILK, 0);
7352 I915_WRITE(WM1_LP_ILK, 0);
7353
7354 /*
7355 * Based on the document from hardware guys the following bits
7356 * should be set unconditionally in order to enable FBC.
7357 * The bit 22 of 0x42000
7358 * The bit 22 of 0x42004
7359 * The bit 7,8,9 of 0x42020.
7360 */
7361 if (IS_IRONLAKE_M(dev)) {
7362 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7363 I915_READ(ILK_DISPLAY_CHICKEN1) |
7364 ILK_FBCQ_DIS);
7365 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7366 I915_READ(ILK_DISPLAY_CHICKEN2) |
7367 ILK_DPARB_GATE);
7368 I915_WRITE(ILK_DSPCLK_GATE,
7369 I915_READ(ILK_DSPCLK_GATE) |
7370 ILK_DPFC_DIS1 |
7371 ILK_DPFC_DIS2 |
7372 ILK_CLK_FBC);
7373 }
7374
7375 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7376 I915_READ(ILK_DISPLAY_CHICKEN2) |
7377 ILK_ELPIN_409_SELECT);
7378 I915_WRITE(_3D_CHICKEN2,
7379 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7380 _3D_CHICKEN2_WM_READ_PIPELINED);
7381}
7382
7383static void gen6_init_clock_gating(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07007384{
7385 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007386 int pipe;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007387 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7388
7389 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Jesse Barnes652c3932009-08-17 13:31:43 -07007390
Jesse Barnes6067aae2011-04-28 15:04:31 -07007391 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7392 I915_READ(ILK_DISPLAY_CHICKEN2) |
7393 ILK_ELPIN_409_SELECT);
Eric Anholt8956c8b2010-03-18 13:21:14 -07007394
Jesse Barnes6067aae2011-04-28 15:04:31 -07007395 I915_WRITE(WM3_LP_ILK, 0);
7396 I915_WRITE(WM2_LP_ILK, 0);
7397 I915_WRITE(WM1_LP_ILK, 0);
Eric Anholt8956c8b2010-03-18 13:21:14 -07007398
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007399 /*
Jesse Barnes6067aae2011-04-28 15:04:31 -07007400 * According to the spec the following bits should be
7401 * set in order to enable memory self-refresh and fbc:
7402 * The bit21 and bit22 of 0x42000
7403 * The bit21 and bit22 of 0x42004
7404 * The bit5 and bit7 of 0x42020
7405 * The bit14 of 0x70180
7406 * The bit14 of 0x71180
Jesse Barnes382b0932010-10-07 16:01:25 -07007407 */
Jesse Barnes6067aae2011-04-28 15:04:31 -07007408 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7409 I915_READ(ILK_DISPLAY_CHICKEN1) |
7410 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7411 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7412 I915_READ(ILK_DISPLAY_CHICKEN2) |
7413 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7414 I915_WRITE(ILK_DSPCLK_GATE,
7415 I915_READ(ILK_DSPCLK_GATE) |
7416 ILK_DPARB_CLK_GATE |
7417 ILK_DPFD_CLK_GATE);
Jesse Barnes382b0932010-10-07 16:01:25 -07007418
Jesse Barnes6067aae2011-04-28 15:04:31 -07007419 for_each_pipe(pipe)
7420 I915_WRITE(DSPCNTR(pipe),
7421 I915_READ(DSPCNTR(pipe)) |
7422 DISPPLANE_TRICKLE_FEED_DISABLE);
7423}
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007424
Jesse Barnes28963a32011-05-11 09:42:30 -07007425static void ivybridge_init_clock_gating(struct drm_device *dev)
7426{
7427 struct drm_i915_private *dev_priv = dev->dev_private;
7428 int pipe;
7429 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
Jesse Barnes652c3932009-08-17 13:31:43 -07007430
Jesse Barnes28963a32011-05-11 09:42:30 -07007431 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007432
Jesse Barnes28963a32011-05-11 09:42:30 -07007433 I915_WRITE(WM3_LP_ILK, 0);
7434 I915_WRITE(WM2_LP_ILK, 0);
7435 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007436
Jesse Barnes28963a32011-05-11 09:42:30 -07007437 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
Eric Anholtde6e2ea2010-11-06 14:53:32 -07007438
Jesse Barnes28963a32011-05-11 09:42:30 -07007439 for_each_pipe(pipe)
7440 I915_WRITE(DSPCNTR(pipe),
7441 I915_READ(DSPCNTR(pipe)) |
7442 DISPPLANE_TRICKLE_FEED_DISABLE);
7443}
Eric Anholt67e92af2010-11-06 14:53:33 -07007444
Jesse Barnes6067aae2011-04-28 15:04:31 -07007445static void g4x_init_clock_gating(struct drm_device *dev)
7446{
7447 struct drm_i915_private *dev_priv = dev->dev_private;
7448 uint32_t dspclk_gate;
Chris Wilson8fd26852010-12-08 18:40:43 +00007449
Jesse Barnes6067aae2011-04-28 15:04:31 -07007450 I915_WRITE(RENCLK_GATE_D1, 0);
7451 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7452 GS_UNIT_CLOCK_GATE_DISABLE |
7453 CL_UNIT_CLOCK_GATE_DISABLE);
7454 I915_WRITE(RAMCLK_GATE_D, 0);
7455 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7456 OVRUNIT_CLOCK_GATE_DISABLE |
7457 OVCUNIT_CLOCK_GATE_DISABLE;
7458 if (IS_GM45(dev))
7459 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7460 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7461}
Yuanhan Liu13982612010-12-15 15:42:31 +08007462
Jesse Barnes6067aae2011-04-28 15:04:31 -07007463static void crestline_init_clock_gating(struct drm_device *dev)
7464{
7465 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liu13982612010-12-15 15:42:31 +08007466
Jesse Barnes6067aae2011-04-28 15:04:31 -07007467 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7468 I915_WRITE(RENCLK_GATE_D2, 0);
7469 I915_WRITE(DSPCLK_GATE_D, 0);
7470 I915_WRITE(RAMCLK_GATE_D, 0);
7471 I915_WRITE16(DEUC, 0);
7472}
Jesse Barnes652c3932009-08-17 13:31:43 -07007473
Jesse Barnes6067aae2011-04-28 15:04:31 -07007474static void broadwater_init_clock_gating(struct drm_device *dev)
7475{
7476 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07007477
Jesse Barnes6067aae2011-04-28 15:04:31 -07007478 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7479 I965_RCC_CLOCK_GATE_DISABLE |
7480 I965_RCPB_CLOCK_GATE_DISABLE |
7481 I965_ISC_CLOCK_GATE_DISABLE |
7482 I965_FBC_CLOCK_GATE_DISABLE);
7483 I915_WRITE(RENCLK_GATE_D2, 0);
7484}
Jesse Barnes652c3932009-08-17 13:31:43 -07007485
Jesse Barnes6067aae2011-04-28 15:04:31 -07007486static void gen3_init_clock_gating(struct drm_device *dev)
7487{
7488 struct drm_i915_private *dev_priv = dev->dev_private;
7489 u32 dstate = I915_READ(D_STATE);
7490
7491 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7492 DSTATE_DOT_CLOCK_GATING;
7493 I915_WRITE(D_STATE, dstate);
7494}
7495
7496static void i85x_init_clock_gating(struct drm_device *dev)
7497{
7498 struct drm_i915_private *dev_priv = dev->dev_private;
7499
7500 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7501}
7502
7503static void i830_init_clock_gating(struct drm_device *dev)
7504{
7505 struct drm_i915_private *dev_priv = dev->dev_private;
7506
7507 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes652c3932009-08-17 13:31:43 -07007508}
7509
Jesse Barnes645c62a2011-05-11 09:49:31 -07007510static void ibx_init_clock_gating(struct drm_device *dev)
7511{
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513
7514 /*
7515 * On Ibex Peak and Cougar Point, we need to disable clock
7516 * gating for the panel power sequencer or it will fail to
7517 * start up when no ports are active.
7518 */
7519 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7520}
7521
7522static void cpt_init_clock_gating(struct drm_device *dev)
7523{
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525
7526 /*
7527 * On Ibex Peak and Cougar Point, we need to disable clock
7528 * gating for the panel power sequencer or it will fail to
7529 * start up when no ports are active.
7530 */
7531 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7532 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7533 DPLS_EDP_PPS_FIX_DIS);
Jesse Barnes79e53942008-11-07 14:24:08 -08007534}
7535
Chris Wilsonac668082011-02-09 16:15:32 +00007536static void ironlake_teardown_rc6(struct drm_device *dev)
Chris Wilson0cdab212010-12-05 17:27:06 +00007537{
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539
7540 if (dev_priv->renderctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00007541 i915_gem_object_unpin(dev_priv->renderctx);
7542 drm_gem_object_unreference(&dev_priv->renderctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00007543 dev_priv->renderctx = NULL;
7544 }
7545
7546 if (dev_priv->pwrctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00007547 i915_gem_object_unpin(dev_priv->pwrctx);
7548 drm_gem_object_unreference(&dev_priv->pwrctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00007549 dev_priv->pwrctx = NULL;
7550 }
7551}
7552
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007553static void ironlake_disable_rc6(struct drm_device *dev)
7554{
7555 struct drm_i915_private *dev_priv = dev->dev_private;
7556
Chris Wilsonac668082011-02-09 16:15:32 +00007557 if (I915_READ(PWRCTXA)) {
7558 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7559 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7560 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7561 50);
7562
7563 I915_WRITE(PWRCTXA, 0);
7564 POSTING_READ(PWRCTXA);
7565
7566 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7567 POSTING_READ(RSTDBYCTL);
7568 }
7569
Chris Wilson99507302011-02-24 09:42:52 +00007570 ironlake_teardown_rc6(dev);
Chris Wilsonac668082011-02-09 16:15:32 +00007571}
7572
7573static int ironlake_setup_rc6(struct drm_device *dev)
7574{
7575 struct drm_i915_private *dev_priv = dev->dev_private;
7576
7577 if (dev_priv->renderctx == NULL)
7578 dev_priv->renderctx = intel_alloc_context_page(dev);
7579 if (!dev_priv->renderctx)
7580 return -ENOMEM;
7581
7582 if (dev_priv->pwrctx == NULL)
7583 dev_priv->pwrctx = intel_alloc_context_page(dev);
7584 if (!dev_priv->pwrctx) {
7585 ironlake_teardown_rc6(dev);
7586 return -ENOMEM;
7587 }
7588
7589 return 0;
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007590}
7591
7592void ironlake_enable_rc6(struct drm_device *dev)
7593{
7594 struct drm_i915_private *dev_priv = dev->dev_private;
7595 int ret;
7596
Chris Wilsonac668082011-02-09 16:15:32 +00007597 /* rc6 disabled by default due to repeated reports of hanging during
7598 * boot and resume.
7599 */
7600 if (!i915_enable_rc6)
7601 return;
7602
Ben Widawsky2c34b852011-03-19 18:14:26 -07007603 mutex_lock(&dev->struct_mutex);
Chris Wilsonac668082011-02-09 16:15:32 +00007604 ret = ironlake_setup_rc6(dev);
Ben Widawsky2c34b852011-03-19 18:14:26 -07007605 if (ret) {
7606 mutex_unlock(&dev->struct_mutex);
Chris Wilsonac668082011-02-09 16:15:32 +00007607 return;
Ben Widawsky2c34b852011-03-19 18:14:26 -07007608 }
Chris Wilsonac668082011-02-09 16:15:32 +00007609
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007610 /*
7611 * GPU can automatically power down the render unit if given a page
7612 * to save state.
7613 */
7614 ret = BEGIN_LP_RING(6);
7615 if (ret) {
Chris Wilsonac668082011-02-09 16:15:32 +00007616 ironlake_teardown_rc6(dev);
Ben Widawsky2c34b852011-03-19 18:14:26 -07007617 mutex_unlock(&dev->struct_mutex);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007618 return;
7619 }
Chris Wilsonac668082011-02-09 16:15:32 +00007620
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007621 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7622 OUT_RING(MI_SET_CONTEXT);
7623 OUT_RING(dev_priv->renderctx->gtt_offset |
7624 MI_MM_SPACE_GTT |
7625 MI_SAVE_EXT_STATE_EN |
7626 MI_RESTORE_EXT_STATE_EN |
7627 MI_RESTORE_INHIBIT);
7628 OUT_RING(MI_SUSPEND_FLUSH);
7629 OUT_RING(MI_NOOP);
7630 OUT_RING(MI_FLUSH);
7631 ADVANCE_LP_RING();
7632
Ben Widawsky4a246cf2011-03-19 18:14:28 -07007633 /*
7634 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7635 * does an implicit flush, combined with MI_FLUSH above, it should be
7636 * safe to assume that renderctx is valid
7637 */
7638 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7639 if (ret) {
7640 DRM_ERROR("failed to enable ironlake power power savings\n");
7641 ironlake_teardown_rc6(dev);
7642 mutex_unlock(&dev->struct_mutex);
7643 return;
7644 }
7645
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007646 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7647 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
Ben Widawsky2c34b852011-03-19 18:14:26 -07007648 mutex_unlock(&dev->struct_mutex);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007649}
7650
Jesse Barnes645c62a2011-05-11 09:49:31 -07007651void intel_init_clock_gating(struct drm_device *dev)
7652{
7653 struct drm_i915_private *dev_priv = dev->dev_private;
7654
7655 dev_priv->display.init_clock_gating(dev);
7656
7657 if (dev_priv->display.init_pch_clock_gating)
7658 dev_priv->display.init_pch_clock_gating(dev);
7659}
Chris Wilsonac668082011-02-09 16:15:32 +00007660
Jesse Barnese70236a2009-09-21 10:42:27 -07007661/* Set up chip specific display functions */
7662static void intel_init_display(struct drm_device *dev)
7663{
7664 struct drm_i915_private *dev_priv = dev->dev_private;
7665
7666 /* We always want a DPMS function */
Eric Anholtf564048e2011-03-30 13:01:02 -07007667 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007668 dev_priv->display.dpms = ironlake_crtc_dpms;
Eric Anholtf564048e2011-03-30 13:01:02 -07007669 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7670 } else {
Jesse Barnese70236a2009-09-21 10:42:27 -07007671 dev_priv->display.dpms = i9xx_crtc_dpms;
Eric Anholtf564048e2011-03-30 13:01:02 -07007672 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7673 }
Jesse Barnese70236a2009-09-21 10:42:27 -07007674
Adam Jacksonee5382a2010-04-23 11:17:39 -04007675 if (I915_HAS_FBC(dev)) {
Yuanhan Liu9c04f012010-12-15 15:42:32 +08007676 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08007677 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7678 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7679 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7680 } else if (IS_GM45(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07007681 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7682 dev_priv->display.enable_fbc = g4x_enable_fbc;
7683 dev_priv->display.disable_fbc = g4x_disable_fbc;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007684 } else if (IS_CRESTLINE(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007685 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7686 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7687 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7688 }
Jesse Barnes74dff282009-09-14 15:39:40 -07007689 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07007690 }
7691
7692 /* Returns the core display clock speed */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007693 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07007694 dev_priv->display.get_display_clock_speed =
7695 i945_get_display_clock_speed;
7696 else if (IS_I915G(dev))
7697 dev_priv->display.get_display_clock_speed =
7698 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007699 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007700 dev_priv->display.get_display_clock_speed =
7701 i9xx_misc_get_display_clock_speed;
7702 else if (IS_I915GM(dev))
7703 dev_priv->display.get_display_clock_speed =
7704 i915gm_get_display_clock_speed;
7705 else if (IS_I865G(dev))
7706 dev_priv->display.get_display_clock_speed =
7707 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02007708 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007709 dev_priv->display.get_display_clock_speed =
7710 i855_get_display_clock_speed;
7711 else /* 852, 830 */
7712 dev_priv->display.get_display_clock_speed =
7713 i830_get_display_clock_speed;
7714
7715 /* For FIFO watermark updates */
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007716 if (HAS_PCH_SPLIT(dev)) {
Jesse Barnes645c62a2011-05-11 09:49:31 -07007717 if (HAS_PCH_IBX(dev))
7718 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7719 else if (HAS_PCH_CPT(dev))
7720 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7721
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01007722 if (IS_GEN5(dev)) {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007723 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7724 dev_priv->display.update_wm = ironlake_update_wm;
7725 else {
7726 DRM_DEBUG_KMS("Failed to get proper latency. "
7727 "Disable CxSR\n");
7728 dev_priv->display.update_wm = NULL;
7729 }
Jesse Barnes674cf962011-04-28 14:27:04 -07007730 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007731 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
Yuanhan Liu13982612010-12-15 15:42:31 +08007732 } else if (IS_GEN6(dev)) {
7733 if (SNB_READ_WM0_LATENCY()) {
7734 dev_priv->display.update_wm = sandybridge_update_wm;
7735 } else {
7736 DRM_DEBUG_KMS("Failed to read display plane latency. "
7737 "Disable CxSR\n");
7738 dev_priv->display.update_wm = NULL;
7739 }
Jesse Barnes674cf962011-04-28 14:27:04 -07007740 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007741 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
Jesse Barnes357555c2011-04-28 15:09:55 -07007742 } else if (IS_IVYBRIDGE(dev)) {
7743 /* FIXME: detect B0+ stepping and use auto training */
7744 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Jesse Barnesfe100d42011-04-28 14:29:45 -07007745 if (SNB_READ_WM0_LATENCY()) {
7746 dev_priv->display.update_wm = sandybridge_update_wm;
7747 } else {
7748 DRM_DEBUG_KMS("Failed to read display plane latency. "
7749 "Disable CxSR\n");
7750 dev_priv->display.update_wm = NULL;
7751 }
Jesse Barnes28963a32011-05-11 09:42:30 -07007752 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007753
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007754 } else
7755 dev_priv->display.update_wm = NULL;
7756 } else if (IS_PINEVIEW(dev)) {
Zhao Yakuid4294342010-03-22 22:45:36 +08007757 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
Li Peng95534262010-05-18 18:58:44 +08007758 dev_priv->is_ddr3,
Zhao Yakuid4294342010-03-22 22:45:36 +08007759 dev_priv->fsb_freq,
7760 dev_priv->mem_freq)) {
7761 DRM_INFO("failed to find known CxSR latency "
Li Peng95534262010-05-18 18:58:44 +08007762 "(found ddr%s fsb freq %d, mem freq %d), "
Zhao Yakuid4294342010-03-22 22:45:36 +08007763 "disabling CxSR\n",
Li Peng95534262010-05-18 18:58:44 +08007764 (dev_priv->is_ddr3 == 1) ? "3": "2",
Zhao Yakuid4294342010-03-22 22:45:36 +08007765 dev_priv->fsb_freq, dev_priv->mem_freq);
7766 /* Disable CxSR and never update its watermark again */
7767 pineview_disable_cxsr(dev);
7768 dev_priv->display.update_wm = NULL;
7769 } else
7770 dev_priv->display.update_wm = pineview_update_wm;
Jason Stubbs95e0ee92011-05-28 14:26:48 +10007771 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007772 } else if (IS_G4X(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007773 dev_priv->display.update_wm = g4x_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007774 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7775 } else if (IS_GEN4(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007776 dev_priv->display.update_wm = i965_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007777 if (IS_CRESTLINE(dev))
7778 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7779 else if (IS_BROADWATER(dev))
7780 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7781 } else if (IS_GEN3(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007782 dev_priv->display.update_wm = i9xx_update_wm;
7783 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007784 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7785 } else if (IS_I865G(dev)) {
7786 dev_priv->display.update_wm = i830_update_wm;
7787 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7788 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Adam Jackson8f4695e2010-04-16 18:20:57 -04007789 } else if (IS_I85X(dev)) {
7790 dev_priv->display.update_wm = i9xx_update_wm;
7791 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007792 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
Jesse Barnese70236a2009-09-21 10:42:27 -07007793 } else {
Adam Jackson8f4695e2010-04-16 18:20:57 -04007794 dev_priv->display.update_wm = i830_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007795 dev_priv->display.init_clock_gating = i830_init_clock_gating;
Adam Jackson8f4695e2010-04-16 18:20:57 -04007796 if (IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007797 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7798 else
7799 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07007800 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007801
7802 /* Default just returns -ENODEV to indicate unsupported */
7803 dev_priv->display.queue_flip = intel_default_queue_flip;
7804
7805 switch (INTEL_INFO(dev)->gen) {
7806 case 2:
7807 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7808 break;
7809
7810 case 3:
7811 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7812 break;
7813
7814 case 4:
7815 case 5:
7816 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7817 break;
7818
7819 case 6:
7820 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7821 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007822 case 7:
7823 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7824 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007825 }
Jesse Barnese70236a2009-09-21 10:42:27 -07007826}
7827
Jesse Barnesb690e962010-07-19 13:53:12 -07007828/*
7829 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7830 * resume, or other times. This quirk makes sure that's the case for
7831 * affected systems.
7832 */
7833static void quirk_pipea_force (struct drm_device *dev)
7834{
7835 struct drm_i915_private *dev_priv = dev->dev_private;
7836
7837 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7838 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7839}
7840
Keith Packard435793d2011-07-12 14:56:22 -07007841/*
7842 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7843 */
7844static void quirk_ssc_force_disable(struct drm_device *dev)
7845{
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7848}
7849
Jesse Barnesb690e962010-07-19 13:53:12 -07007850struct intel_quirk {
7851 int device;
7852 int subsystem_vendor;
7853 int subsystem_device;
7854 void (*hook)(struct drm_device *dev);
7855};
7856
7857struct intel_quirk intel_quirks[] = {
7858 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7859 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7860 /* HP Mini needs pipe A force quirk (LP: #322104) */
7861 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7862
7863 /* Thinkpad R31 needs pipe A force quirk */
7864 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7865 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7866 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7867
7868 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7869 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7870 /* ThinkPad X40 needs pipe A force quirk */
7871
7872 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7873 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7874
7875 /* 855 & before need to leave pipe A & dpll A up */
7876 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7877 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07007878
7879 /* Lenovo U160 cannot use SSC on LVDS */
7880 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Jesse Barnesb690e962010-07-19 13:53:12 -07007881};
7882
7883static void intel_init_quirks(struct drm_device *dev)
7884{
7885 struct pci_dev *d = dev->pdev;
7886 int i;
7887
7888 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7889 struct intel_quirk *q = &intel_quirks[i];
7890
7891 if (d->device == q->device &&
7892 (d->subsystem_vendor == q->subsystem_vendor ||
7893 q->subsystem_vendor == PCI_ANY_ID) &&
7894 (d->subsystem_device == q->subsystem_device ||
7895 q->subsystem_device == PCI_ANY_ID))
7896 q->hook(dev);
7897 }
7898}
7899
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007900/* Disable the VGA plane that we never use */
7901static void i915_disable_vga(struct drm_device *dev)
7902{
7903 struct drm_i915_private *dev_priv = dev->dev_private;
7904 u8 sr1;
7905 u32 vga_reg;
7906
7907 if (HAS_PCH_SPLIT(dev))
7908 vga_reg = CPU_VGACNTRL;
7909 else
7910 vga_reg = VGACNTRL;
7911
7912 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7913 outb(1, VGA_SR_INDEX);
7914 sr1 = inb(VGA_SR_DATA);
7915 outb(sr1 | 1<<5, VGA_SR_DATA);
7916 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7917 udelay(300);
7918
7919 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7920 POSTING_READ(vga_reg);
7921}
7922
Jesse Barnes79e53942008-11-07 14:24:08 -08007923void intel_modeset_init(struct drm_device *dev)
7924{
Jesse Barnes652c3932009-08-17 13:31:43 -07007925 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007926 int i;
7927
7928 drm_mode_config_init(dev);
7929
7930 dev->mode_config.min_width = 0;
7931 dev->mode_config.min_height = 0;
7932
7933 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7934
Jesse Barnesb690e962010-07-19 13:53:12 -07007935 intel_init_quirks(dev);
7936
Jesse Barnese70236a2009-09-21 10:42:27 -07007937 intel_init_display(dev);
7938
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007939 if (IS_GEN2(dev)) {
7940 dev->mode_config.max_width = 2048;
7941 dev->mode_config.max_height = 2048;
7942 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07007943 dev->mode_config.max_width = 4096;
7944 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08007945 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007946 dev->mode_config.max_width = 8192;
7947 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08007948 }
Chris Wilson35c30472010-12-22 14:07:12 +00007949 dev->mode_config.fb_base = dev->agp->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08007950
Zhao Yakui28c97732009-10-09 11:39:41 +08007951 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10007952 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08007953
Dave Airliea3524f12010-06-06 18:59:41 +10007954 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007955 intel_crtc_init(dev, i);
7956 }
7957
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007958 /* Just disable it once at startup */
7959 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007960 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007961
Jesse Barnes645c62a2011-05-11 09:49:31 -07007962 intel_init_clock_gating(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007963
Jesse Barnes7648fa92010-05-20 14:28:11 -07007964 if (IS_IRONLAKE_M(dev)) {
Jesse Barnesf97108d2010-01-29 11:27:07 -08007965 ironlake_enable_drps(dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07007966 intel_init_emon(dev);
7967 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08007968
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007969 if (IS_GEN6(dev))
7970 gen6_enable_rps(dev_priv);
7971
Jesse Barnes652c3932009-08-17 13:31:43 -07007972 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7973 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7974 (unsigned long)dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01007975}
7976
7977void intel_modeset_gem_init(struct drm_device *dev)
7978{
7979 if (IS_IRONLAKE_M(dev))
7980 ironlake_enable_rc6(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02007981
7982 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007983}
7984
7985void intel_modeset_cleanup(struct drm_device *dev)
7986{
Jesse Barnes652c3932009-08-17 13:31:43 -07007987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 struct drm_crtc *crtc;
7989 struct intel_crtc *intel_crtc;
7990
Keith Packardf87ea762010-10-03 19:36:26 -07007991 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007992 mutex_lock(&dev->struct_mutex);
7993
Jesse Barnes723bfd72010-10-07 16:01:13 -07007994 intel_unregister_dsm_handler();
7995
7996
Jesse Barnes652c3932009-08-17 13:31:43 -07007997 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7998 /* Skip inactive CRTCs */
7999 if (!crtc->fb)
8000 continue;
8001
8002 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02008003 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008004 }
8005
Jesse Barnese70236a2009-09-21 10:42:27 -07008006 if (dev_priv->display.disable_fbc)
8007 dev_priv->display.disable_fbc(dev);
8008
Jesse Barnesf97108d2010-01-29 11:27:07 -08008009 if (IS_IRONLAKE_M(dev))
8010 ironlake_disable_drps(dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008011 if (IS_GEN6(dev))
8012 gen6_disable_rps(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -08008013
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008014 if (IS_IRONLAKE_M(dev))
8015 ironlake_disable_rc6(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00008016
Kristian Høgsberg69341a52009-11-11 12:19:17 -05008017 mutex_unlock(&dev->struct_mutex);
8018
Daniel Vetter6c0d93502010-08-20 18:26:46 +02008019 /* Disable the irq before mode object teardown, for the irq might
8020 * enqueue unpin/hotplug work. */
8021 drm_irq_uninstall(dev);
8022 cancel_work_sync(&dev_priv->hotplug_work);
8023
Daniel Vetter3dec0092010-08-20 21:40:52 +02008024 /* Shut off idle work before the crtcs get freed. */
8025 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8026 intel_crtc = to_intel_crtc(crtc);
8027 del_timer_sync(&intel_crtc->idle_timer);
8028 }
8029 del_timer_sync(&dev_priv->idle_timer);
8030 cancel_work_sync(&dev_priv->idle_work);
8031
Jesse Barnes79e53942008-11-07 14:24:08 -08008032 drm_mode_config_cleanup(dev);
8033}
8034
Dave Airlie28d52042009-09-21 14:33:58 +10008035/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08008036 * Return which encoder is currently attached for connector.
8037 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01008038struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08008039{
Chris Wilsondf0e9242010-09-09 16:20:55 +01008040 return &intel_attached_encoder(connector)->base;
8041}
Jesse Barnes79e53942008-11-07 14:24:08 -08008042
Chris Wilsondf0e9242010-09-09 16:20:55 +01008043void intel_connector_attach_encoder(struct intel_connector *connector,
8044 struct intel_encoder *encoder)
8045{
8046 connector->encoder = encoder;
8047 drm_mode_connector_attach_encoder(&connector->base,
8048 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08008049}
Dave Airlie28d52042009-09-21 14:33:58 +10008050
8051/*
8052 * set vga decode state - true == enable VGA decode
8053 */
8054int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8055{
8056 struct drm_i915_private *dev_priv = dev->dev_private;
8057 u16 gmch_ctrl;
8058
8059 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8060 if (state)
8061 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8062 else
8063 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8064 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8065 return 0;
8066}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008067
8068#ifdef CONFIG_DEBUG_FS
8069#include <linux/seq_file.h>
8070
8071struct intel_display_error_state {
8072 struct intel_cursor_error_state {
8073 u32 control;
8074 u32 position;
8075 u32 base;
8076 u32 size;
8077 } cursor[2];
8078
8079 struct intel_pipe_error_state {
8080 u32 conf;
8081 u32 source;
8082
8083 u32 htotal;
8084 u32 hblank;
8085 u32 hsync;
8086 u32 vtotal;
8087 u32 vblank;
8088 u32 vsync;
8089 } pipe[2];
8090
8091 struct intel_plane_error_state {
8092 u32 control;
8093 u32 stride;
8094 u32 size;
8095 u32 pos;
8096 u32 addr;
8097 u32 surface;
8098 u32 tile_offset;
8099 } plane[2];
8100};
8101
8102struct intel_display_error_state *
8103intel_display_capture_error_state(struct drm_device *dev)
8104{
8105 drm_i915_private_t *dev_priv = dev->dev_private;
8106 struct intel_display_error_state *error;
8107 int i;
8108
8109 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8110 if (error == NULL)
8111 return NULL;
8112
8113 for (i = 0; i < 2; i++) {
8114 error->cursor[i].control = I915_READ(CURCNTR(i));
8115 error->cursor[i].position = I915_READ(CURPOS(i));
8116 error->cursor[i].base = I915_READ(CURBASE(i));
8117
8118 error->plane[i].control = I915_READ(DSPCNTR(i));
8119 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8120 error->plane[i].size = I915_READ(DSPSIZE(i));
8121 error->plane[i].pos= I915_READ(DSPPOS(i));
8122 error->plane[i].addr = I915_READ(DSPADDR(i));
8123 if (INTEL_INFO(dev)->gen >= 4) {
8124 error->plane[i].surface = I915_READ(DSPSURF(i));
8125 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8126 }
8127
8128 error->pipe[i].conf = I915_READ(PIPECONF(i));
8129 error->pipe[i].source = I915_READ(PIPESRC(i));
8130 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8131 error->pipe[i].hblank = I915_READ(HBLANK(i));
8132 error->pipe[i].hsync = I915_READ(HSYNC(i));
8133 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8134 error->pipe[i].vblank = I915_READ(VBLANK(i));
8135 error->pipe[i].vsync = I915_READ(VSYNC(i));
8136 }
8137
8138 return error;
8139}
8140
8141void
8142intel_display_print_error_state(struct seq_file *m,
8143 struct drm_device *dev,
8144 struct intel_display_error_state *error)
8145{
8146 int i;
8147
8148 for (i = 0; i < 2; i++) {
8149 seq_printf(m, "Pipe [%d]:\n", i);
8150 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8151 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8152 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8153 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8154 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8155 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8156 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8157 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8158
8159 seq_printf(m, "Plane [%d]:\n", i);
8160 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8161 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8162 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8163 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8164 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8165 if (INTEL_INFO(dev)->gen >= 4) {
8166 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8167 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8168 }
8169
8170 seq_printf(m, "Cursor [%d]:\n", i);
8171 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8172 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8173 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8174 }
8175}
8176#endif