Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dsi.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #define DSS_SUBSYS_NAME "DSI" |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mutex.h> |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 30 | #include <linux/semaphore.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 31 | #include <linux/seq_file.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/regulator/consumer.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 34 | #include <linux/wait.h> |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 35 | #include <linux/workqueue.h> |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 36 | #include <linux/sched.h> |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 37 | #include <linux/slab.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 38 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 39 | #include <video/omapdss.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 40 | #include <plat/clock.h> |
| 41 | |
| 42 | #include "dss.h" |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 43 | #include "dss_features.h" |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 44 | |
| 45 | /*#define VERBOSE_IRQ*/ |
| 46 | #define DSI_CATCH_MISSING_TE |
| 47 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 48 | struct dsi_reg { u16 idx; }; |
| 49 | |
| 50 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) |
| 51 | |
| 52 | #define DSI_SZ_REGS SZ_1K |
| 53 | /* DSI Protocol Engine */ |
| 54 | |
| 55 | #define DSI_REVISION DSI_REG(0x0000) |
| 56 | #define DSI_SYSCONFIG DSI_REG(0x0010) |
| 57 | #define DSI_SYSSTATUS DSI_REG(0x0014) |
| 58 | #define DSI_IRQSTATUS DSI_REG(0x0018) |
| 59 | #define DSI_IRQENABLE DSI_REG(0x001C) |
| 60 | #define DSI_CTRL DSI_REG(0x0040) |
| 61 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
| 62 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) |
| 63 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) |
| 64 | #define DSI_CLK_CTRL DSI_REG(0x0054) |
| 65 | #define DSI_TIMING1 DSI_REG(0x0058) |
| 66 | #define DSI_TIMING2 DSI_REG(0x005C) |
| 67 | #define DSI_VM_TIMING1 DSI_REG(0x0060) |
| 68 | #define DSI_VM_TIMING2 DSI_REG(0x0064) |
| 69 | #define DSI_VM_TIMING3 DSI_REG(0x0068) |
| 70 | #define DSI_CLK_TIMING DSI_REG(0x006C) |
| 71 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) |
| 72 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) |
| 73 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) |
| 74 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) |
| 75 | #define DSI_VM_TIMING4 DSI_REG(0x0080) |
| 76 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) |
| 77 | #define DSI_VM_TIMING5 DSI_REG(0x0088) |
| 78 | #define DSI_VM_TIMING6 DSI_REG(0x008C) |
| 79 | #define DSI_VM_TIMING7 DSI_REG(0x0090) |
| 80 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) |
| 81 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) |
| 82 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) |
| 83 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) |
| 84 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) |
| 85 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) |
| 86 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) |
| 87 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) |
| 88 | |
| 89 | /* DSIPHY_SCP */ |
| 90 | |
| 91 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) |
| 92 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) |
| 93 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) |
| 94 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 95 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 96 | |
| 97 | /* DSI_PLL_CTRL_SCP */ |
| 98 | |
| 99 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) |
| 100 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) |
| 101 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) |
| 102 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) |
| 103 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) |
| 104 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 105 | #define REG_GET(dsidev, idx, start, end) \ |
| 106 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 107 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 108 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ |
| 109 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 110 | |
| 111 | /* Global interrupts */ |
| 112 | #define DSI_IRQ_VC0 (1 << 0) |
| 113 | #define DSI_IRQ_VC1 (1 << 1) |
| 114 | #define DSI_IRQ_VC2 (1 << 2) |
| 115 | #define DSI_IRQ_VC3 (1 << 3) |
| 116 | #define DSI_IRQ_WAKEUP (1 << 4) |
| 117 | #define DSI_IRQ_RESYNC (1 << 5) |
| 118 | #define DSI_IRQ_PLL_LOCK (1 << 7) |
| 119 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) |
| 120 | #define DSI_IRQ_PLL_RECALL (1 << 9) |
| 121 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) |
| 122 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) |
| 123 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) |
| 124 | #define DSI_IRQ_TE_TRIGGER (1 << 16) |
| 125 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) |
| 126 | #define DSI_IRQ_SYNC_LOST (1 << 18) |
| 127 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) |
| 128 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) |
| 129 | #define DSI_IRQ_ERROR_MASK \ |
| 130 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ |
| 131 | DSI_IRQ_TA_TIMEOUT) |
| 132 | #define DSI_IRQ_CHANNEL_MASK 0xf |
| 133 | |
| 134 | /* Virtual channel interrupts */ |
| 135 | #define DSI_VC_IRQ_CS (1 << 0) |
| 136 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) |
| 137 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) |
| 138 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) |
| 139 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) |
| 140 | #define DSI_VC_IRQ_BTA (1 << 5) |
| 141 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) |
| 142 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) |
| 143 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) |
| 144 | #define DSI_VC_IRQ_ERROR_MASK \ |
| 145 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ |
| 146 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ |
| 147 | DSI_VC_IRQ_FIFO_TX_UDF) |
| 148 | |
| 149 | /* ComplexIO interrupts */ |
| 150 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) |
| 151 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) |
| 152 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 153 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
| 154 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 155 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
| 156 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) |
| 157 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 158 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
| 159 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 160 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
| 161 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) |
| 162 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 163 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
| 164 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 165 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
| 166 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) |
| 167 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 168 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
| 169 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 170 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
| 171 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) |
| 172 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) |
| 173 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) |
| 174 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) |
| 175 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 176 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
| 177 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) |
| 178 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) |
| 179 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 180 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
| 181 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 182 | #define DSI_CIO_IRQ_ERROR_MASK \ |
| 183 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 184 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
| 185 | DSI_CIO_IRQ_ERRSYNCESC5 | \ |
| 186 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ |
| 187 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ |
| 188 | DSI_CIO_IRQ_ERRESC5 | \ |
| 189 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ |
| 190 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ |
| 191 | DSI_CIO_IRQ_ERRCONTROL5 | \ |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 192 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
| 193 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 194 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
| 195 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ |
| 196 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 197 | |
| 198 | #define DSI_DT_DCS_SHORT_WRITE_0 0x05 |
| 199 | #define DSI_DT_DCS_SHORT_WRITE_1 0x15 |
| 200 | #define DSI_DT_DCS_READ 0x06 |
| 201 | #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 |
| 202 | #define DSI_DT_NULL_PACKET 0x09 |
| 203 | #define DSI_DT_DCS_LONG_WRITE 0x39 |
| 204 | |
| 205 | #define DSI_DT_RX_ACK_WITH_ERR 0x02 |
| 206 | #define DSI_DT_RX_DCS_LONG_READ 0x1c |
| 207 | #define DSI_DT_RX_SHORT_READ_1 0x21 |
| 208 | #define DSI_DT_RX_SHORT_READ_2 0x22 |
| 209 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 210 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
| 211 | |
| 212 | #define DSI_MAX_NR_ISRS 2 |
| 213 | |
| 214 | struct dsi_isr_data { |
| 215 | omap_dsi_isr_t isr; |
| 216 | void *arg; |
| 217 | u32 mask; |
| 218 | }; |
| 219 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 220 | enum fifo_size { |
| 221 | DSI_FIFO_SIZE_0 = 0, |
| 222 | DSI_FIFO_SIZE_32 = 1, |
| 223 | DSI_FIFO_SIZE_64 = 2, |
| 224 | DSI_FIFO_SIZE_96 = 3, |
| 225 | DSI_FIFO_SIZE_128 = 4, |
| 226 | }; |
| 227 | |
| 228 | enum dsi_vc_mode { |
| 229 | DSI_VC_MODE_L4 = 0, |
| 230 | DSI_VC_MODE_VP, |
| 231 | }; |
| 232 | |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 233 | enum dsi_lane { |
| 234 | DSI_CLK_P = 1 << 0, |
| 235 | DSI_CLK_N = 1 << 1, |
| 236 | DSI_DATA1_P = 1 << 2, |
| 237 | DSI_DATA1_N = 1 << 3, |
| 238 | DSI_DATA2_P = 1 << 4, |
| 239 | DSI_DATA2_N = 1 << 5, |
| 240 | }; |
| 241 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 242 | struct dsi_update_region { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 243 | u16 x, y, w, h; |
| 244 | struct omap_dss_device *device; |
| 245 | }; |
| 246 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 247 | struct dsi_irq_stats { |
| 248 | unsigned long last_reset; |
| 249 | unsigned irq_count; |
| 250 | unsigned dsi_irqs[32]; |
| 251 | unsigned vc_irqs[4][32]; |
| 252 | unsigned cio_irqs[32]; |
| 253 | }; |
| 254 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 255 | struct dsi_isr_tables { |
| 256 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; |
| 257 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; |
| 258 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; |
| 259 | }; |
| 260 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 261 | struct dsi_data { |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 262 | struct platform_device *pdev; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 263 | void __iomem *base; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 264 | int irq; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 265 | |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 266 | void (*dsi_mux_pads)(bool enable); |
| 267 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 268 | struct dsi_clock_info current_cinfo; |
| 269 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 270 | bool vdds_dsi_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 271 | struct regulator *vdds_dsi_reg; |
| 272 | |
| 273 | struct { |
| 274 | enum dsi_vc_mode mode; |
| 275 | struct omap_dss_device *dssdev; |
| 276 | enum fifo_size fifo_size; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 277 | int vc_id; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 278 | } vc[4]; |
| 279 | |
| 280 | struct mutex lock; |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 281 | struct semaphore bus_lock; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 282 | |
| 283 | unsigned pll_locked; |
| 284 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 285 | spinlock_t irq_lock; |
| 286 | struct dsi_isr_tables isr_tables; |
| 287 | /* space for a copy used by the interrupt handler */ |
| 288 | struct dsi_isr_tables isr_tables_copy; |
| 289 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 290 | int update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 291 | struct dsi_update_region update_region; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 292 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 293 | bool te_enabled; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 294 | bool ulps_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 295 | |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 296 | struct workqueue_struct *workqueue; |
| 297 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 298 | void (*framedone_callback)(int, void *); |
| 299 | void *framedone_data; |
| 300 | |
| 301 | struct delayed_work framedone_timeout_work; |
| 302 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 303 | #ifdef DSI_CATCH_MISSING_TE |
| 304 | struct timer_list te_timer; |
| 305 | #endif |
| 306 | |
| 307 | unsigned long cache_req_pck; |
| 308 | unsigned long cache_clk_freq; |
| 309 | struct dsi_clock_info cache_cinfo; |
| 310 | |
| 311 | u32 errors; |
| 312 | spinlock_t errors_lock; |
| 313 | #ifdef DEBUG |
| 314 | ktime_t perf_setup_time; |
| 315 | ktime_t perf_start_time; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 316 | #endif |
| 317 | int debug_read; |
| 318 | int debug_write; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 319 | |
| 320 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 321 | spinlock_t irq_stats_lock; |
| 322 | struct dsi_irq_stats irq_stats; |
| 323 | #endif |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 324 | /* DSI PLL Parameter Ranges */ |
| 325 | unsigned long regm_max, regn_max; |
| 326 | unsigned long regm_dispc_max, regm_dsi_max; |
| 327 | unsigned long fint_min, fint_max; |
| 328 | unsigned long lpdiv_max; |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 329 | |
| 330 | unsigned scp_clk_refcount; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 331 | }; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 332 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 333 | static struct platform_device *dsi_pdev_map[MAX_NUM_DSI]; |
| 334 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 335 | #ifdef DEBUG |
| 336 | static unsigned int dsi_perf; |
| 337 | module_param_named(dsi_perf, dsi_perf, bool, 0644); |
| 338 | #endif |
| 339 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 340 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) |
| 341 | { |
| 342 | return dev_get_drvdata(&dsidev->dev); |
| 343 | } |
| 344 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 345 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) |
| 346 | { |
| 347 | return dsi_pdev_map[dssdev->phy.dsi.module]; |
| 348 | } |
| 349 | |
| 350 | struct platform_device *dsi_get_dsidev_from_id(int module) |
| 351 | { |
| 352 | return dsi_pdev_map[module]; |
| 353 | } |
| 354 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 355 | static int dsi_get_dsidev_id(struct platform_device *dsidev) |
| 356 | { |
| 357 | /* TEMP: Pass 0 as the dsi module index till the time the dsi platform |
| 358 | * device names aren't changed to the form "omapdss_dsi.0", |
| 359 | * "omapdss_dsi.1" and so on */ |
| 360 | BUG_ON(dsidev->id != -1); |
| 361 | |
| 362 | return 0; |
| 363 | } |
| 364 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 365 | static inline void dsi_write_reg(struct platform_device *dsidev, |
| 366 | const struct dsi_reg idx, u32 val) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 367 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 368 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 369 | |
| 370 | __raw_writel(val, dsi->base + idx.idx); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 371 | } |
| 372 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 373 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
| 374 | const struct dsi_reg idx) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 375 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 376 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 377 | |
| 378 | return __raw_readl(dsi->base + idx.idx); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | |
| 382 | void dsi_save_context(void) |
| 383 | { |
| 384 | } |
| 385 | |
| 386 | void dsi_restore_context(void) |
| 387 | { |
| 388 | } |
| 389 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 390 | void dsi_bus_lock(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 391 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 392 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 393 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 394 | |
| 395 | down(&dsi->bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 396 | } |
| 397 | EXPORT_SYMBOL(dsi_bus_lock); |
| 398 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 399 | void dsi_bus_unlock(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 400 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 401 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 402 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 403 | |
| 404 | up(&dsi->bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 405 | } |
| 406 | EXPORT_SYMBOL(dsi_bus_unlock); |
| 407 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 408 | static bool dsi_bus_is_locked(struct platform_device *dsidev) |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 409 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 410 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 411 | |
| 412 | return dsi->bus_lock.count == 0; |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 413 | } |
| 414 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 415 | static void dsi_completion_handler(void *data, u32 mask) |
| 416 | { |
| 417 | complete((struct completion *)data); |
| 418 | } |
| 419 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 420 | static inline int wait_for_bit_change(struct platform_device *dsidev, |
| 421 | const struct dsi_reg idx, int bitnum, int value) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 422 | { |
| 423 | int t = 100000; |
| 424 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 425 | while (REG_GET(dsidev, idx, bitnum, bitnum) != value) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 426 | if (--t == 0) |
| 427 | return !value; |
| 428 | } |
| 429 | |
| 430 | return value; |
| 431 | } |
| 432 | |
| 433 | #ifdef DEBUG |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 434 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 435 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 436 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 437 | dsi->perf_setup_time = ktime_get(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 438 | } |
| 439 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 440 | static void dsi_perf_mark_start(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 441 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 442 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 443 | dsi->perf_start_time = ktime_get(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 444 | } |
| 445 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 446 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 447 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 448 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 449 | ktime_t t, setup_time, trans_time; |
| 450 | u32 total_bytes; |
| 451 | u32 setup_us, trans_us, total_us; |
| 452 | |
| 453 | if (!dsi_perf) |
| 454 | return; |
| 455 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 456 | t = ktime_get(); |
| 457 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 458 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 459 | setup_us = (u32)ktime_to_us(setup_time); |
| 460 | if (setup_us == 0) |
| 461 | setup_us = 1; |
| 462 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 463 | trans_time = ktime_sub(t, dsi->perf_start_time); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 464 | trans_us = (u32)ktime_to_us(trans_time); |
| 465 | if (trans_us == 0) |
| 466 | trans_us = 1; |
| 467 | |
| 468 | total_us = setup_us + trans_us; |
| 469 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 470 | total_bytes = dsi->update_region.w * |
| 471 | dsi->update_region.h * |
| 472 | dsi->update_region.device->ctrl.pixel_size / 8; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 473 | |
Tomi Valkeinen | 1bbb275 | 2010-01-11 16:41:10 +0200 | [diff] [blame] | 474 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
| 475 | "%u bytes, %u kbytes/sec\n", |
| 476 | name, |
| 477 | setup_us, |
| 478 | trans_us, |
| 479 | total_us, |
| 480 | 1000*1000 / total_us, |
| 481 | total_bytes, |
| 482 | total_bytes * 1000 / total_us); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 483 | } |
| 484 | #else |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 485 | #define dsi_perf_mark_setup(x) |
| 486 | #define dsi_perf_mark_start(x) |
| 487 | #define dsi_perf_show(x, y) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 488 | #endif |
| 489 | |
| 490 | static void print_irq_status(u32 status) |
| 491 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 492 | if (status == 0) |
| 493 | return; |
| 494 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 495 | #ifndef VERBOSE_IRQ |
| 496 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
| 497 | return; |
| 498 | #endif |
| 499 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); |
| 500 | |
| 501 | #define PIS(x) \ |
| 502 | if (status & DSI_IRQ_##x) \ |
| 503 | printk(#x " "); |
| 504 | #ifdef VERBOSE_IRQ |
| 505 | PIS(VC0); |
| 506 | PIS(VC1); |
| 507 | PIS(VC2); |
| 508 | PIS(VC3); |
| 509 | #endif |
| 510 | PIS(WAKEUP); |
| 511 | PIS(RESYNC); |
| 512 | PIS(PLL_LOCK); |
| 513 | PIS(PLL_UNLOCK); |
| 514 | PIS(PLL_RECALL); |
| 515 | PIS(COMPLEXIO_ERR); |
| 516 | PIS(HS_TX_TIMEOUT); |
| 517 | PIS(LP_RX_TIMEOUT); |
| 518 | PIS(TE_TRIGGER); |
| 519 | PIS(ACK_TRIGGER); |
| 520 | PIS(SYNC_LOST); |
| 521 | PIS(LDO_POWER_GOOD); |
| 522 | PIS(TA_TIMEOUT); |
| 523 | #undef PIS |
| 524 | |
| 525 | printk("\n"); |
| 526 | } |
| 527 | |
| 528 | static void print_irq_status_vc(int channel, u32 status) |
| 529 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 530 | if (status == 0) |
| 531 | return; |
| 532 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 533 | #ifndef VERBOSE_IRQ |
| 534 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
| 535 | return; |
| 536 | #endif |
| 537 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); |
| 538 | |
| 539 | #define PIS(x) \ |
| 540 | if (status & DSI_VC_IRQ_##x) \ |
| 541 | printk(#x " "); |
| 542 | PIS(CS); |
| 543 | PIS(ECC_CORR); |
| 544 | #ifdef VERBOSE_IRQ |
| 545 | PIS(PACKET_SENT); |
| 546 | #endif |
| 547 | PIS(FIFO_TX_OVF); |
| 548 | PIS(FIFO_RX_OVF); |
| 549 | PIS(BTA); |
| 550 | PIS(ECC_NO_CORR); |
| 551 | PIS(FIFO_TX_UDF); |
| 552 | PIS(PP_BUSY_CHANGE); |
| 553 | #undef PIS |
| 554 | printk("\n"); |
| 555 | } |
| 556 | |
| 557 | static void print_irq_status_cio(u32 status) |
| 558 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 559 | if (status == 0) |
| 560 | return; |
| 561 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 562 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
| 563 | |
| 564 | #define PIS(x) \ |
| 565 | if (status & DSI_CIO_IRQ_##x) \ |
| 566 | printk(#x " "); |
| 567 | PIS(ERRSYNCESC1); |
| 568 | PIS(ERRSYNCESC2); |
| 569 | PIS(ERRSYNCESC3); |
| 570 | PIS(ERRESC1); |
| 571 | PIS(ERRESC2); |
| 572 | PIS(ERRESC3); |
| 573 | PIS(ERRCONTROL1); |
| 574 | PIS(ERRCONTROL2); |
| 575 | PIS(ERRCONTROL3); |
| 576 | PIS(STATEULPS1); |
| 577 | PIS(STATEULPS2); |
| 578 | PIS(STATEULPS3); |
| 579 | PIS(ERRCONTENTIONLP0_1); |
| 580 | PIS(ERRCONTENTIONLP1_1); |
| 581 | PIS(ERRCONTENTIONLP0_2); |
| 582 | PIS(ERRCONTENTIONLP1_2); |
| 583 | PIS(ERRCONTENTIONLP0_3); |
| 584 | PIS(ERRCONTENTIONLP1_3); |
| 585 | PIS(ULPSACTIVENOT_ALL0); |
| 586 | PIS(ULPSACTIVENOT_ALL1); |
| 587 | #undef PIS |
| 588 | |
| 589 | printk("\n"); |
| 590 | } |
| 591 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 592 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 593 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
| 594 | u32 *vcstatus, u32 ciostatus) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 595 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 596 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 597 | int i; |
| 598 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 599 | spin_lock(&dsi->irq_stats_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 600 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 601 | dsi->irq_stats.irq_count++; |
| 602 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 603 | |
| 604 | for (i = 0; i < 4; ++i) |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 605 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 606 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 607 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 608 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 609 | spin_unlock(&dsi->irq_stats_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 610 | } |
| 611 | #else |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 612 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 613 | #endif |
| 614 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 615 | static int debug_irq; |
| 616 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 617 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, |
| 618 | u32 *vcstatus, u32 ciostatus) |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 619 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 620 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 621 | int i; |
| 622 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 623 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
| 624 | DSSERR("DSI error, irqstatus %x\n", irqstatus); |
| 625 | print_irq_status(irqstatus); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 626 | spin_lock(&dsi->errors_lock); |
| 627 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; |
| 628 | spin_unlock(&dsi->errors_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 629 | } else if (debug_irq) { |
| 630 | print_irq_status(irqstatus); |
| 631 | } |
| 632 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 633 | for (i = 0; i < 4; ++i) { |
| 634 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
| 635 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", |
| 636 | i, vcstatus[i]); |
| 637 | print_irq_status_vc(i, vcstatus[i]); |
| 638 | } else if (debug_irq) { |
| 639 | print_irq_status_vc(i, vcstatus[i]); |
| 640 | } |
| 641 | } |
| 642 | |
| 643 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
| 644 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); |
| 645 | print_irq_status_cio(ciostatus); |
| 646 | } else if (debug_irq) { |
| 647 | print_irq_status_cio(ciostatus); |
| 648 | } |
| 649 | } |
| 650 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 651 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
| 652 | unsigned isr_array_size, u32 irqstatus) |
| 653 | { |
| 654 | struct dsi_isr_data *isr_data; |
| 655 | int i; |
| 656 | |
| 657 | for (i = 0; i < isr_array_size; i++) { |
| 658 | isr_data = &isr_array[i]; |
| 659 | if (isr_data->isr && isr_data->mask & irqstatus) |
| 660 | isr_data->isr(isr_data->arg, irqstatus); |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, |
| 665 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) |
| 666 | { |
| 667 | int i; |
| 668 | |
| 669 | dsi_call_isrs(isr_tables->isr_table, |
| 670 | ARRAY_SIZE(isr_tables->isr_table), |
| 671 | irqstatus); |
| 672 | |
| 673 | for (i = 0; i < 4; ++i) { |
| 674 | if (vcstatus[i] == 0) |
| 675 | continue; |
| 676 | dsi_call_isrs(isr_tables->isr_table_vc[i], |
| 677 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), |
| 678 | vcstatus[i]); |
| 679 | } |
| 680 | |
| 681 | if (ciostatus != 0) |
| 682 | dsi_call_isrs(isr_tables->isr_table_cio, |
| 683 | ARRAY_SIZE(isr_tables->isr_table_cio), |
| 684 | ciostatus); |
| 685 | } |
| 686 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 687 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
| 688 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 689 | struct platform_device *dsidev; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 690 | struct dsi_data *dsi; |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 691 | u32 irqstatus, vcstatus[4], ciostatus; |
| 692 | int i; |
| 693 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 694 | dsidev = (struct platform_device *) arg; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 695 | dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 696 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 697 | spin_lock(&dsi->irq_lock); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 698 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 699 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 700 | |
| 701 | /* IRQ is not for us */ |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 702 | if (!irqstatus) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 703 | spin_unlock(&dsi->irq_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 704 | return IRQ_NONE; |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 705 | } |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 706 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 707 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 708 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 709 | dsi_read_reg(dsidev, DSI_IRQSTATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 710 | |
| 711 | for (i = 0; i < 4; ++i) { |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 712 | if ((irqstatus & (1 << i)) == 0) { |
| 713 | vcstatus[i] = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 714 | continue; |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 715 | } |
| 716 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 717 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 718 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 719 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 720 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 721 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 725 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 726 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 727 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 728 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 729 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 730 | } else { |
| 731 | ciostatus = 0; |
| 732 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 733 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 734 | #ifdef DSI_CATCH_MISSING_TE |
| 735 | if (irqstatus & DSI_IRQ_TE_TRIGGER) |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 736 | del_timer(&dsi->te_timer); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 737 | #endif |
| 738 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 739 | /* make a copy and unlock, so that isrs can unregister |
| 740 | * themselves */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 741 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
| 742 | sizeof(dsi->isr_tables)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 743 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 744 | spin_unlock(&dsi->irq_lock); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 745 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 746 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 747 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 748 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 749 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 750 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 751 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 752 | return IRQ_HANDLED; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 753 | } |
| 754 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 755 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 756 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, |
| 757 | struct dsi_isr_data *isr_array, |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 758 | unsigned isr_array_size, u32 default_mask, |
| 759 | const struct dsi_reg enable_reg, |
| 760 | const struct dsi_reg status_reg) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 761 | { |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 762 | struct dsi_isr_data *isr_data; |
| 763 | u32 mask; |
| 764 | u32 old_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 765 | int i; |
| 766 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 767 | mask = default_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 768 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 769 | for (i = 0; i < isr_array_size; i++) { |
| 770 | isr_data = &isr_array[i]; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 771 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 772 | if (isr_data->isr == NULL) |
| 773 | continue; |
| 774 | |
| 775 | mask |= isr_data->mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 776 | } |
| 777 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 778 | old_mask = dsi_read_reg(dsidev, enable_reg); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 779 | /* clear the irqstatus for newly enabled irqs */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 780 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); |
| 781 | dsi_write_reg(dsidev, enable_reg, mask); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 782 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 783 | /* flush posted writes */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 784 | dsi_read_reg(dsidev, enable_reg); |
| 785 | dsi_read_reg(dsidev, status_reg); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 786 | } |
| 787 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 788 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 789 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 790 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 791 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 792 | u32 mask = DSI_IRQ_ERROR_MASK; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 793 | #ifdef DSI_CATCH_MISSING_TE |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 794 | mask |= DSI_IRQ_TE_TRIGGER; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 795 | #endif |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 796 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, |
| 797 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 798 | DSI_IRQENABLE, DSI_IRQSTATUS); |
| 799 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 800 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 801 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 802 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 803 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 804 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 805 | |
| 806 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], |
| 807 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 808 | DSI_VC_IRQ_ERROR_MASK, |
| 809 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); |
| 810 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 811 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 812 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 813 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 814 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 815 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 816 | |
| 817 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, |
| 818 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 819 | DSI_CIO_IRQ_ERROR_MASK, |
| 820 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); |
| 821 | } |
| 822 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 823 | static void _dsi_initialize_irq(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 824 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 825 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 826 | unsigned long flags; |
| 827 | int vc; |
| 828 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 829 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 830 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 831 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 832 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 833 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 834 | for (vc = 0; vc < 4; ++vc) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 835 | _omap_dsi_set_irqs_vc(dsidev, vc); |
| 836 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 837 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 838 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 839 | } |
| 840 | |
| 841 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 842 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 843 | { |
| 844 | struct dsi_isr_data *isr_data; |
| 845 | int free_idx; |
| 846 | int i; |
| 847 | |
| 848 | BUG_ON(isr == NULL); |
| 849 | |
| 850 | /* check for duplicate entry and find a free slot */ |
| 851 | free_idx = -1; |
| 852 | for (i = 0; i < isr_array_size; i++) { |
| 853 | isr_data = &isr_array[i]; |
| 854 | |
| 855 | if (isr_data->isr == isr && isr_data->arg == arg && |
| 856 | isr_data->mask == mask) { |
| 857 | return -EINVAL; |
| 858 | } |
| 859 | |
| 860 | if (isr_data->isr == NULL && free_idx == -1) |
| 861 | free_idx = i; |
| 862 | } |
| 863 | |
| 864 | if (free_idx == -1) |
| 865 | return -EBUSY; |
| 866 | |
| 867 | isr_data = &isr_array[free_idx]; |
| 868 | isr_data->isr = isr; |
| 869 | isr_data->arg = arg; |
| 870 | isr_data->mask = mask; |
| 871 | |
| 872 | return 0; |
| 873 | } |
| 874 | |
| 875 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 876 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 877 | { |
| 878 | struct dsi_isr_data *isr_data; |
| 879 | int i; |
| 880 | |
| 881 | for (i = 0; i < isr_array_size; i++) { |
| 882 | isr_data = &isr_array[i]; |
| 883 | if (isr_data->isr != isr || isr_data->arg != arg || |
| 884 | isr_data->mask != mask) |
| 885 | continue; |
| 886 | |
| 887 | isr_data->isr = NULL; |
| 888 | isr_data->arg = NULL; |
| 889 | isr_data->mask = 0; |
| 890 | |
| 891 | return 0; |
| 892 | } |
| 893 | |
| 894 | return -EINVAL; |
| 895 | } |
| 896 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 897 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, |
| 898 | void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 899 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 900 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 901 | unsigned long flags; |
| 902 | int r; |
| 903 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 904 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 905 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 906 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
| 907 | ARRAY_SIZE(dsi->isr_tables.isr_table)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 908 | |
| 909 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 910 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 911 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 912 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 913 | |
| 914 | return r; |
| 915 | } |
| 916 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 917 | static int dsi_unregister_isr(struct platform_device *dsidev, |
| 918 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 919 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 920 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 921 | unsigned long flags; |
| 922 | int r; |
| 923 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 924 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 925 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 926 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
| 927 | ARRAY_SIZE(dsi->isr_tables.isr_table)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 928 | |
| 929 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 930 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 931 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 932 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 933 | |
| 934 | return r; |
| 935 | } |
| 936 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 937 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, |
| 938 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 939 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 940 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 941 | unsigned long flags; |
| 942 | int r; |
| 943 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 944 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 945 | |
| 946 | r = _dsi_register_isr(isr, arg, mask, |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 947 | dsi->isr_tables.isr_table_vc[channel], |
| 948 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 949 | |
| 950 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 951 | _omap_dsi_set_irqs_vc(dsidev, channel); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 952 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 953 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 954 | |
| 955 | return r; |
| 956 | } |
| 957 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 958 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, |
| 959 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 960 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 961 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 962 | unsigned long flags; |
| 963 | int r; |
| 964 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 965 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 966 | |
| 967 | r = _dsi_unregister_isr(isr, arg, mask, |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 968 | dsi->isr_tables.isr_table_vc[channel], |
| 969 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 970 | |
| 971 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 972 | _omap_dsi_set_irqs_vc(dsidev, channel); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 973 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 974 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 975 | |
| 976 | return r; |
| 977 | } |
| 978 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 979 | static int dsi_register_isr_cio(struct platform_device *dsidev, |
| 980 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 981 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 982 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 983 | unsigned long flags; |
| 984 | int r; |
| 985 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 986 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 987 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 988 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
| 989 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 990 | |
| 991 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 992 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 993 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 994 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 995 | |
| 996 | return r; |
| 997 | } |
| 998 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 999 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, |
| 1000 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1001 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1002 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1003 | unsigned long flags; |
| 1004 | int r; |
| 1005 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1006 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1007 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1008 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
| 1009 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1010 | |
| 1011 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1012 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1013 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1014 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1015 | |
| 1016 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1017 | } |
| 1018 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1019 | static u32 dsi_get_errors(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1020 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1021 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1022 | unsigned long flags; |
| 1023 | u32 e; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1024 | spin_lock_irqsave(&dsi->errors_lock, flags); |
| 1025 | e = dsi->errors; |
| 1026 | dsi->errors = 0; |
| 1027 | spin_unlock_irqrestore(&dsi->errors_lock, flags); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1028 | return e; |
| 1029 | } |
| 1030 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1031 | /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1032 | static inline void enable_clocks(bool enable) |
| 1033 | { |
| 1034 | if (enable) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1035 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1036 | else |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1037 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1038 | } |
| 1039 | |
| 1040 | /* source clock for DSI PLL. this could also be PCLKFREE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1041 | static inline void dsi_enable_pll_clock(struct platform_device *dsidev, |
| 1042 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1043 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1044 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1045 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1046 | if (enable) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1047 | dss_clk_enable(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1048 | else |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1049 | dss_clk_disable(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1050 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1051 | if (enable && dsi->pll_locked) { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1052 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1053 | DSSERR("cannot lock PLL when enabling clocks\n"); |
| 1054 | } |
| 1055 | } |
| 1056 | |
| 1057 | #ifdef DEBUG |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1058 | static void _dsi_print_reset_status(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1059 | { |
| 1060 | u32 l; |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1061 | int b0, b1, b2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1062 | |
| 1063 | if (!dss_debug) |
| 1064 | return; |
| 1065 | |
| 1066 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 1067 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 1068 | * I/O. */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1069 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1070 | |
| 1071 | printk(KERN_DEBUG "DSI resets: "); |
| 1072 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1073 | l = dsi_read_reg(dsidev, DSI_PLL_STATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1074 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
| 1075 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1076 | l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1077 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
| 1078 | |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1079 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
| 1080 | b0 = 28; |
| 1081 | b1 = 27; |
| 1082 | b2 = 26; |
| 1083 | } else { |
| 1084 | b0 = 24; |
| 1085 | b1 = 25; |
| 1086 | b2 = 26; |
| 1087 | } |
| 1088 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1089 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1090 | printk("PHY (%x%x%x, %d, %d, %d)\n", |
| 1091 | FLD_GET(l, b0, b0), |
| 1092 | FLD_GET(l, b1, b1), |
| 1093 | FLD_GET(l, b2, b2), |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1094 | FLD_GET(l, 29, 29), |
| 1095 | FLD_GET(l, 30, 30), |
| 1096 | FLD_GET(l, 31, 31)); |
| 1097 | } |
| 1098 | #else |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1099 | #define _dsi_print_reset_status(x) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1100 | #endif |
| 1101 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1102 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1103 | { |
| 1104 | DSSDBG("dsi_if_enable(%d)\n", enable); |
| 1105 | |
| 1106 | enable = enable ? 1 : 0; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1107 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1108 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1109 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1110 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
| 1111 | return -EIO; |
| 1112 | } |
| 1113 | |
| 1114 | return 0; |
| 1115 | } |
| 1116 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1117 | unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1118 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1119 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1120 | |
| 1121 | return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1122 | } |
| 1123 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1124 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1125 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1126 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1127 | |
| 1128 | return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1129 | } |
| 1130 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1131 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1132 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1133 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1134 | |
| 1135 | return dsi->current_cinfo.clkin4ddr / 16; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1136 | } |
| 1137 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1138 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1139 | { |
| 1140 | unsigned long r; |
| 1141 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1142 | if (dss_get_dsi_clk_source() == OMAP_DSS_CLK_SRC_FCK) { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1143 | /* DSI FCLK source is DSS_CLK_FCK */ |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1144 | r = dss_clk_get_rate(DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1145 | } else { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1146 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1147 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | return r; |
| 1151 | } |
| 1152 | |
| 1153 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) |
| 1154 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1155 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1156 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1157 | unsigned long dsi_fclk; |
| 1158 | unsigned lp_clk_div; |
| 1159 | unsigned long lp_clk; |
| 1160 | |
Tomi Valkeinen | c6940a3 | 2011-02-22 13:36:10 +0200 | [diff] [blame] | 1161 | lp_clk_div = dssdev->clocks.dsi.lp_clk_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1162 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1163 | if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1164 | return -EINVAL; |
| 1165 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1166 | dsi_fclk = dsi_fclk_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1167 | |
| 1168 | lp_clk = dsi_fclk / 2 / lp_clk_div; |
| 1169 | |
| 1170 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1171 | dsi->current_cinfo.lp_clk = lp_clk; |
| 1172 | dsi->current_cinfo.lp_clk_div = lp_clk_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1173 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1174 | /* LP_CLK_DIVISOR */ |
| 1175 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1176 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1177 | /* LP_RX_SYNCHRO_ENABLE */ |
| 1178 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1179 | |
| 1180 | return 0; |
| 1181 | } |
| 1182 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1183 | static void dsi_enable_scp_clk(struct platform_device *dsidev) |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1184 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1185 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1186 | |
| 1187 | if (dsi->scp_clk_refcount++ == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1188 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1189 | } |
| 1190 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1191 | static void dsi_disable_scp_clk(struct platform_device *dsidev) |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1192 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1193 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1194 | |
| 1195 | WARN_ON(dsi->scp_clk_refcount == 0); |
| 1196 | if (--dsi->scp_clk_refcount == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1197 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1198 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1199 | |
| 1200 | enum dsi_pll_power_state { |
| 1201 | DSI_PLL_POWER_OFF = 0x0, |
| 1202 | DSI_PLL_POWER_ON_HSCLK = 0x1, |
| 1203 | DSI_PLL_POWER_ON_ALL = 0x2, |
| 1204 | DSI_PLL_POWER_ON_DIV = 0x3, |
| 1205 | }; |
| 1206 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1207 | static int dsi_pll_power(struct platform_device *dsidev, |
| 1208 | enum dsi_pll_power_state state) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1209 | { |
| 1210 | int t = 0; |
| 1211 | |
Tomi Valkeinen | c94dfe0 | 2011-04-15 10:42:59 +0300 | [diff] [blame] | 1212 | /* DSI-PLL power command 0x3 is not working */ |
| 1213 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && |
| 1214 | state == DSI_PLL_POWER_ON_DIV) |
| 1215 | state = DSI_PLL_POWER_ON_ALL; |
| 1216 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1217 | /* PLL_PWR_CMD */ |
| 1218 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1219 | |
| 1220 | /* PLL_PWR_STATUS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1221 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1222 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1223 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
| 1224 | state); |
| 1225 | return -ENODEV; |
| 1226 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1227 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1228 | } |
| 1229 | |
| 1230 | return 0; |
| 1231 | } |
| 1232 | |
| 1233 | /* calculate clock rates using dividers in cinfo */ |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1234 | static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, |
| 1235 | struct dsi_clock_info *cinfo) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1236 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1237 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 1238 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1239 | |
| 1240 | if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1241 | return -EINVAL; |
| 1242 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1243 | if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1244 | return -EINVAL; |
| 1245 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1246 | if (cinfo->regm_dispc > dsi->regm_dispc_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1247 | return -EINVAL; |
| 1248 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1249 | if (cinfo->regm_dsi > dsi->regm_dsi_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1250 | return -EINVAL; |
| 1251 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1252 | if (cinfo->use_sys_clk) { |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1253 | cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1254 | /* XXX it is unclear if highfreq should be used |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1255 | * with DSS_SYS_CLK source also */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1256 | cinfo->highfreq = 0; |
| 1257 | } else { |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1258 | cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1259 | |
| 1260 | if (cinfo->clkin < 32000000) |
| 1261 | cinfo->highfreq = 0; |
| 1262 | else |
| 1263 | cinfo->highfreq = 1; |
| 1264 | } |
| 1265 | |
| 1266 | cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); |
| 1267 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1268 | if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1269 | return -EINVAL; |
| 1270 | |
| 1271 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; |
| 1272 | |
| 1273 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) |
| 1274 | return -EINVAL; |
| 1275 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1276 | if (cinfo->regm_dispc > 0) |
| 1277 | cinfo->dsi_pll_hsdiv_dispc_clk = |
| 1278 | cinfo->clkin4ddr / cinfo->regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1279 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1280 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1281 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1282 | if (cinfo->regm_dsi > 0) |
| 1283 | cinfo->dsi_pll_hsdiv_dsi_clk = |
| 1284 | cinfo->clkin4ddr / cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1285 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1286 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1287 | |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1291 | int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, |
| 1292 | unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1293 | struct dispc_clock_info *dispc_cinfo) |
| 1294 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1295 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1296 | struct dsi_clock_info cur, best; |
| 1297 | struct dispc_clock_info best_dispc; |
| 1298 | int min_fck_per_pck; |
| 1299 | int match = 0; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1300 | unsigned long dss_sys_clk, max_dss_fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1301 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1302 | dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1303 | |
Taneja, Archit | 31ef823 | 2011-03-14 23:28:22 -0500 | [diff] [blame] | 1304 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 1305 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1306 | if (req_pck == dsi->cache_req_pck && |
| 1307 | dsi->cache_cinfo.clkin == dss_sys_clk) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1308 | DSSDBG("DSI clock info found from cache\n"); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1309 | *dsi_cinfo = dsi->cache_cinfo; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1310 | dispc_find_clk_divs(is_tft, req_pck, |
| 1311 | dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1312 | return 0; |
| 1313 | } |
| 1314 | |
| 1315 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 1316 | |
| 1317 | if (min_fck_per_pck && |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 1318 | req_pck * min_fck_per_pck > max_dss_fck) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1319 | DSSERR("Requested pixel clock not possible with the current " |
| 1320 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 1321 | "the constraint off.\n"); |
| 1322 | min_fck_per_pck = 0; |
| 1323 | } |
| 1324 | |
| 1325 | DSSDBG("dsi_pll_calc\n"); |
| 1326 | |
| 1327 | retry: |
| 1328 | memset(&best, 0, sizeof(best)); |
| 1329 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 1330 | |
| 1331 | memset(&cur, 0, sizeof(cur)); |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1332 | cur.clkin = dss_sys_clk; |
| 1333 | cur.use_sys_clk = 1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1334 | cur.highfreq = 0; |
| 1335 | |
| 1336 | /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ |
| 1337 | /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ |
| 1338 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1339 | for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1340 | if (cur.highfreq == 0) |
| 1341 | cur.fint = cur.clkin / cur.regn; |
| 1342 | else |
| 1343 | cur.fint = cur.clkin / (2 * cur.regn); |
| 1344 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1345 | if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1346 | continue; |
| 1347 | |
| 1348 | /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1349 | for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1350 | unsigned long a, b; |
| 1351 | |
| 1352 | a = 2 * cur.regm * (cur.clkin/1000); |
| 1353 | b = cur.regn * (cur.highfreq + 1); |
| 1354 | cur.clkin4ddr = a / b * 1000; |
| 1355 | |
| 1356 | if (cur.clkin4ddr > 1800 * 1000 * 1000) |
| 1357 | break; |
| 1358 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1359 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
| 1360 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1361 | for (cur.regm_dispc = 1; cur.regm_dispc < |
| 1362 | dsi->regm_dispc_max; ++cur.regm_dispc) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1363 | struct dispc_clock_info cur_dispc; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1364 | cur.dsi_pll_hsdiv_dispc_clk = |
| 1365 | cur.clkin4ddr / cur.regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1366 | |
| 1367 | /* this will narrow down the search a bit, |
| 1368 | * but still give pixclocks below what was |
| 1369 | * requested */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1370 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1371 | break; |
| 1372 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1373 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1374 | continue; |
| 1375 | |
| 1376 | if (min_fck_per_pck && |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1377 | cur.dsi_pll_hsdiv_dispc_clk < |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1378 | req_pck * min_fck_per_pck) |
| 1379 | continue; |
| 1380 | |
| 1381 | match = 1; |
| 1382 | |
| 1383 | dispc_find_clk_divs(is_tft, req_pck, |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1384 | cur.dsi_pll_hsdiv_dispc_clk, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1385 | &cur_dispc); |
| 1386 | |
| 1387 | if (abs(cur_dispc.pck - req_pck) < |
| 1388 | abs(best_dispc.pck - req_pck)) { |
| 1389 | best = cur; |
| 1390 | best_dispc = cur_dispc; |
| 1391 | |
| 1392 | if (cur_dispc.pck == req_pck) |
| 1393 | goto found; |
| 1394 | } |
| 1395 | } |
| 1396 | } |
| 1397 | } |
| 1398 | found: |
| 1399 | if (!match) { |
| 1400 | if (min_fck_per_pck) { |
| 1401 | DSSERR("Could not find suitable clock settings.\n" |
| 1402 | "Turning FCK/PCK constraint off and" |
| 1403 | "trying again.\n"); |
| 1404 | min_fck_per_pck = 0; |
| 1405 | goto retry; |
| 1406 | } |
| 1407 | |
| 1408 | DSSERR("Could not find suitable clock settings.\n"); |
| 1409 | |
| 1410 | return -EINVAL; |
| 1411 | } |
| 1412 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1413 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
| 1414 | best.regm_dsi = 0; |
| 1415 | best.dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1416 | |
| 1417 | if (dsi_cinfo) |
| 1418 | *dsi_cinfo = best; |
| 1419 | if (dispc_cinfo) |
| 1420 | *dispc_cinfo = best_dispc; |
| 1421 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1422 | dsi->cache_req_pck = req_pck; |
| 1423 | dsi->cache_clk_freq = 0; |
| 1424 | dsi->cache_cinfo = best; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1425 | |
| 1426 | return 0; |
| 1427 | } |
| 1428 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1429 | int dsi_pll_set_clock_div(struct platform_device *dsidev, |
| 1430 | struct dsi_clock_info *cinfo) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1431 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1432 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1433 | int r = 0; |
| 1434 | u32 l; |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1435 | int f = 0; |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1436 | u8 regn_start, regn_end, regm_start, regm_end; |
| 1437 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1438 | |
| 1439 | DSSDBGF(); |
| 1440 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1441 | dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk; |
| 1442 | dsi->current_cinfo.highfreq = cinfo->highfreq; |
Tomi Valkeinen | b276509 | 2011-04-07 15:28:47 +0300 | [diff] [blame] | 1443 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1444 | dsi->current_cinfo.fint = cinfo->fint; |
| 1445 | dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; |
| 1446 | dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1447 | cinfo->dsi_pll_hsdiv_dispc_clk; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1448 | dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk = |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1449 | cinfo->dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1450 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1451 | dsi->current_cinfo.regn = cinfo->regn; |
| 1452 | dsi->current_cinfo.regm = cinfo->regm; |
| 1453 | dsi->current_cinfo.regm_dispc = cinfo->regm_dispc; |
| 1454 | dsi->current_cinfo.regm_dsi = cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1455 | |
| 1456 | DSSDBG("DSI Fint %ld\n", cinfo->fint); |
| 1457 | |
| 1458 | DSSDBG("clkin (%s) rate %ld, highfreq %d\n", |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1459 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1460 | cinfo->clkin, |
| 1461 | cinfo->highfreq); |
| 1462 | |
| 1463 | /* DSIPHY == CLKIN4DDR */ |
| 1464 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", |
| 1465 | cinfo->regm, |
| 1466 | cinfo->regn, |
| 1467 | cinfo->clkin, |
| 1468 | cinfo->highfreq + 1, |
| 1469 | cinfo->clkin4ddr); |
| 1470 | |
| 1471 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", |
| 1472 | cinfo->clkin4ddr / 1000 / 1000 / 2); |
| 1473 | |
| 1474 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); |
| 1475 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1476 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1477 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 1478 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1479 | cinfo->dsi_pll_hsdiv_dispc_clk); |
| 1480 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1481 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 1482 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1483 | cinfo->dsi_pll_hsdiv_dsi_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1484 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1485 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
| 1486 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); |
| 1487 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, |
| 1488 | ®m_dispc_end); |
| 1489 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, |
| 1490 | ®m_dsi_end); |
| 1491 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1492 | /* DSI_PLL_AUTOMODE = manual */ |
| 1493 | REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1494 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1495 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1496 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1497 | /* DSI_PLL_REGN */ |
| 1498 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); |
| 1499 | /* DSI_PLL_REGM */ |
| 1500 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); |
| 1501 | /* DSI_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1502 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1503 | regm_dispc_start, regm_dispc_end); |
| 1504 | /* DSIPROTO_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1505 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1506 | regm_dsi_start, regm_dsi_end); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1507 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1508 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1509 | BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1510 | |
| 1511 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { |
| 1512 | f = cinfo->fint < 1000000 ? 0x3 : |
| 1513 | cinfo->fint < 1250000 ? 0x4 : |
| 1514 | cinfo->fint < 1500000 ? 0x5 : |
| 1515 | cinfo->fint < 1750000 ? 0x6 : |
| 1516 | 0x7; |
| 1517 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1518 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1519 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1520 | |
| 1521 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) |
| 1522 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1523 | l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1524 | 11, 11); /* DSI_PLL_CLKSEL */ |
| 1525 | l = FLD_MOD(l, cinfo->highfreq, |
| 1526 | 12, 12); /* DSI_PLL_HIGHFREQ */ |
| 1527 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1528 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ |
| 1529 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1530 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1531 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1532 | REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1533 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1534 | if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1535 | DSSERR("dsi pll go bit not going down.\n"); |
| 1536 | r = -EIO; |
| 1537 | goto err; |
| 1538 | } |
| 1539 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1540 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1541 | DSSERR("cannot lock PLL\n"); |
| 1542 | r = -EIO; |
| 1543 | goto err; |
| 1544 | } |
| 1545 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1546 | dsi->pll_locked = 1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1547 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1548 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1549 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
| 1550 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ |
| 1551 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ |
| 1552 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ |
| 1553 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ |
| 1554 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ |
| 1555 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1556 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ |
| 1557 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ |
| 1558 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ |
| 1559 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ |
| 1560 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ |
| 1561 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ |
| 1562 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1563 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1564 | |
| 1565 | DSSDBG("PLL config done\n"); |
| 1566 | err: |
| 1567 | return r; |
| 1568 | } |
| 1569 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1570 | int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, |
| 1571 | bool enable_hsdiv) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1572 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1573 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1574 | int r = 0; |
| 1575 | enum dsi_pll_power_state pwstate; |
| 1576 | |
| 1577 | DSSDBG("PLL init\n"); |
| 1578 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1579 | if (dsi->vdds_dsi_reg == NULL) { |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1580 | struct regulator *vdds_dsi; |
| 1581 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1582 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1583 | |
| 1584 | if (IS_ERR(vdds_dsi)) { |
| 1585 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 1586 | return PTR_ERR(vdds_dsi); |
| 1587 | } |
| 1588 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1589 | dsi->vdds_dsi_reg = vdds_dsi; |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1590 | } |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1591 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1592 | enable_clocks(1); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1593 | dsi_enable_pll_clock(dsidev, 1); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1594 | /* |
| 1595 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. |
| 1596 | */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1597 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1598 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1599 | if (!dsi->vdds_dsi_enabled) { |
| 1600 | r = regulator_enable(dsi->vdds_dsi_reg); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1601 | if (r) |
| 1602 | goto err0; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1603 | dsi->vdds_dsi_enabled = true; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1604 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1605 | |
| 1606 | /* XXX PLL does not come out of reset without this... */ |
| 1607 | dispc_pck_free_enable(1); |
| 1608 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1609 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1610 | DSSERR("PLL not coming out of reset.\n"); |
| 1611 | r = -ENODEV; |
Ville Syrjälä | 481dfa0 | 2010-04-22 22:50:04 +0200 | [diff] [blame] | 1612 | dispc_pck_free_enable(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1613 | goto err1; |
| 1614 | } |
| 1615 | |
| 1616 | /* XXX ... but if left on, we get problems when planes do not |
| 1617 | * fill the whole display. No idea about this */ |
| 1618 | dispc_pck_free_enable(0); |
| 1619 | |
| 1620 | if (enable_hsclk && enable_hsdiv) |
| 1621 | pwstate = DSI_PLL_POWER_ON_ALL; |
| 1622 | else if (enable_hsclk) |
| 1623 | pwstate = DSI_PLL_POWER_ON_HSCLK; |
| 1624 | else if (enable_hsdiv) |
| 1625 | pwstate = DSI_PLL_POWER_ON_DIV; |
| 1626 | else |
| 1627 | pwstate = DSI_PLL_POWER_OFF; |
| 1628 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1629 | r = dsi_pll_power(dsidev, pwstate); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1630 | |
| 1631 | if (r) |
| 1632 | goto err1; |
| 1633 | |
| 1634 | DSSDBG("PLL init done\n"); |
| 1635 | |
| 1636 | return 0; |
| 1637 | err1: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1638 | if (dsi->vdds_dsi_enabled) { |
| 1639 | regulator_disable(dsi->vdds_dsi_reg); |
| 1640 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1641 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1642 | err0: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1643 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1644 | enable_clocks(0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1645 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1646 | return r; |
| 1647 | } |
| 1648 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1649 | void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1650 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1651 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1652 | |
| 1653 | dsi->pll_locked = 0; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1654 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1655 | if (disconnect_lanes) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1656 | WARN_ON(!dsi->vdds_dsi_enabled); |
| 1657 | regulator_disable(dsi->vdds_dsi_reg); |
| 1658 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1659 | } |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1660 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1661 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1662 | enable_clocks(0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1663 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1664 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1665 | DSSDBG("PLL uninit done\n"); |
| 1666 | } |
| 1667 | |
| 1668 | void dsi_dump_clocks(struct seq_file *s) |
| 1669 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1670 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1671 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1672 | struct dsi_clock_info *cinfo = &dsi->current_cinfo; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1673 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1674 | |
| 1675 | dispc_clk_src = dss_get_dispc_clk_source(); |
| 1676 | dsi_clk_src = dss_get_dsi_clk_source(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1677 | |
| 1678 | enable_clocks(1); |
| 1679 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1680 | seq_printf(s, "- DSI PLL -\n"); |
| 1681 | |
| 1682 | seq_printf(s, "dsi pll source = %s\n", |
Tomi Valkeinen | a9a6500 | 2011-04-04 10:02:53 +0300 | [diff] [blame] | 1683 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1684 | |
| 1685 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); |
| 1686 | |
| 1687 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", |
| 1688 | cinfo->clkin4ddr, cinfo->regm); |
| 1689 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1690 | seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1691 | dss_get_generic_clk_source_name(dispc_clk_src), |
| 1692 | dss_feat_get_clk_source_name(dispc_clk_src), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1693 | cinfo->dsi_pll_hsdiv_dispc_clk, |
| 1694 | cinfo->regm_dispc, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1695 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1696 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1697 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1698 | seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1699 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1700 | dss_feat_get_clk_source_name(dsi_clk_src), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1701 | cinfo->dsi_pll_hsdiv_dsi_clk, |
| 1702 | cinfo->regm_dsi, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1703 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1704 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1705 | |
| 1706 | seq_printf(s, "- DSI -\n"); |
| 1707 | |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1708 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
| 1709 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1710 | dss_feat_get_clk_source_name(dsi_clk_src)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1711 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1712 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1713 | |
| 1714 | seq_printf(s, "DDR_CLK\t\t%lu\n", |
| 1715 | cinfo->clkin4ddr / 4); |
| 1716 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1717 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1718 | |
| 1719 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); |
| 1720 | |
| 1721 | seq_printf(s, "VP_CLK\t\t%lu\n" |
| 1722 | "VP_PCLK\t\t%lu\n", |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1723 | dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), |
| 1724 | dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1725 | |
| 1726 | enable_clocks(0); |
| 1727 | } |
| 1728 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1729 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 1730 | void dsi_dump_irqs(struct seq_file *s) |
| 1731 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1732 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
| 1733 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1734 | unsigned long flags; |
| 1735 | struct dsi_irq_stats stats; |
| 1736 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1737 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1738 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1739 | stats = dsi->irq_stats; |
| 1740 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); |
| 1741 | dsi->irq_stats.last_reset = jiffies; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1742 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1743 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1744 | |
| 1745 | seq_printf(s, "period %u ms\n", |
| 1746 | jiffies_to_msecs(jiffies - stats.last_reset)); |
| 1747 | |
| 1748 | seq_printf(s, "irqs %d\n", stats.irq_count); |
| 1749 | #define PIS(x) \ |
| 1750 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); |
| 1751 | |
| 1752 | seq_printf(s, "-- DSI interrupts --\n"); |
| 1753 | PIS(VC0); |
| 1754 | PIS(VC1); |
| 1755 | PIS(VC2); |
| 1756 | PIS(VC3); |
| 1757 | PIS(WAKEUP); |
| 1758 | PIS(RESYNC); |
| 1759 | PIS(PLL_LOCK); |
| 1760 | PIS(PLL_UNLOCK); |
| 1761 | PIS(PLL_RECALL); |
| 1762 | PIS(COMPLEXIO_ERR); |
| 1763 | PIS(HS_TX_TIMEOUT); |
| 1764 | PIS(LP_RX_TIMEOUT); |
| 1765 | PIS(TE_TRIGGER); |
| 1766 | PIS(ACK_TRIGGER); |
| 1767 | PIS(SYNC_LOST); |
| 1768 | PIS(LDO_POWER_GOOD); |
| 1769 | PIS(TA_TIMEOUT); |
| 1770 | #undef PIS |
| 1771 | |
| 1772 | #define PIS(x) \ |
| 1773 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ |
| 1774 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1775 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1776 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1777 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); |
| 1778 | |
| 1779 | seq_printf(s, "-- VC interrupts --\n"); |
| 1780 | PIS(CS); |
| 1781 | PIS(ECC_CORR); |
| 1782 | PIS(PACKET_SENT); |
| 1783 | PIS(FIFO_TX_OVF); |
| 1784 | PIS(FIFO_RX_OVF); |
| 1785 | PIS(BTA); |
| 1786 | PIS(ECC_NO_CORR); |
| 1787 | PIS(FIFO_TX_UDF); |
| 1788 | PIS(PP_BUSY_CHANGE); |
| 1789 | #undef PIS |
| 1790 | |
| 1791 | #define PIS(x) \ |
| 1792 | seq_printf(s, "%-20s %10d\n", #x, \ |
| 1793 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); |
| 1794 | |
| 1795 | seq_printf(s, "-- CIO interrupts --\n"); |
| 1796 | PIS(ERRSYNCESC1); |
| 1797 | PIS(ERRSYNCESC2); |
| 1798 | PIS(ERRSYNCESC3); |
| 1799 | PIS(ERRESC1); |
| 1800 | PIS(ERRESC2); |
| 1801 | PIS(ERRESC3); |
| 1802 | PIS(ERRCONTROL1); |
| 1803 | PIS(ERRCONTROL2); |
| 1804 | PIS(ERRCONTROL3); |
| 1805 | PIS(STATEULPS1); |
| 1806 | PIS(STATEULPS2); |
| 1807 | PIS(STATEULPS3); |
| 1808 | PIS(ERRCONTENTIONLP0_1); |
| 1809 | PIS(ERRCONTENTIONLP1_1); |
| 1810 | PIS(ERRCONTENTIONLP0_2); |
| 1811 | PIS(ERRCONTENTIONLP1_2); |
| 1812 | PIS(ERRCONTENTIONLP0_3); |
| 1813 | PIS(ERRCONTENTIONLP1_3); |
| 1814 | PIS(ULPSACTIVENOT_ALL0); |
| 1815 | PIS(ULPSACTIVENOT_ALL1); |
| 1816 | #undef PIS |
| 1817 | } |
| 1818 | #endif |
| 1819 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1820 | void dsi_dump_regs(struct seq_file *s) |
| 1821 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1822 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
| 1823 | |
| 1824 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1825 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1826 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1827 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1828 | |
| 1829 | DUMPREG(DSI_REVISION); |
| 1830 | DUMPREG(DSI_SYSCONFIG); |
| 1831 | DUMPREG(DSI_SYSSTATUS); |
| 1832 | DUMPREG(DSI_IRQSTATUS); |
| 1833 | DUMPREG(DSI_IRQENABLE); |
| 1834 | DUMPREG(DSI_CTRL); |
| 1835 | DUMPREG(DSI_COMPLEXIO_CFG1); |
| 1836 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); |
| 1837 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); |
| 1838 | DUMPREG(DSI_CLK_CTRL); |
| 1839 | DUMPREG(DSI_TIMING1); |
| 1840 | DUMPREG(DSI_TIMING2); |
| 1841 | DUMPREG(DSI_VM_TIMING1); |
| 1842 | DUMPREG(DSI_VM_TIMING2); |
| 1843 | DUMPREG(DSI_VM_TIMING3); |
| 1844 | DUMPREG(DSI_CLK_TIMING); |
| 1845 | DUMPREG(DSI_TX_FIFO_VC_SIZE); |
| 1846 | DUMPREG(DSI_RX_FIFO_VC_SIZE); |
| 1847 | DUMPREG(DSI_COMPLEXIO_CFG2); |
| 1848 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); |
| 1849 | DUMPREG(DSI_VM_TIMING4); |
| 1850 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); |
| 1851 | DUMPREG(DSI_VM_TIMING5); |
| 1852 | DUMPREG(DSI_VM_TIMING6); |
| 1853 | DUMPREG(DSI_VM_TIMING7); |
| 1854 | DUMPREG(DSI_STOPCLK_TIMING); |
| 1855 | |
| 1856 | DUMPREG(DSI_VC_CTRL(0)); |
| 1857 | DUMPREG(DSI_VC_TE(0)); |
| 1858 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); |
| 1859 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); |
| 1860 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); |
| 1861 | DUMPREG(DSI_VC_IRQSTATUS(0)); |
| 1862 | DUMPREG(DSI_VC_IRQENABLE(0)); |
| 1863 | |
| 1864 | DUMPREG(DSI_VC_CTRL(1)); |
| 1865 | DUMPREG(DSI_VC_TE(1)); |
| 1866 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); |
| 1867 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); |
| 1868 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); |
| 1869 | DUMPREG(DSI_VC_IRQSTATUS(1)); |
| 1870 | DUMPREG(DSI_VC_IRQENABLE(1)); |
| 1871 | |
| 1872 | DUMPREG(DSI_VC_CTRL(2)); |
| 1873 | DUMPREG(DSI_VC_TE(2)); |
| 1874 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); |
| 1875 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); |
| 1876 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); |
| 1877 | DUMPREG(DSI_VC_IRQSTATUS(2)); |
| 1878 | DUMPREG(DSI_VC_IRQENABLE(2)); |
| 1879 | |
| 1880 | DUMPREG(DSI_VC_CTRL(3)); |
| 1881 | DUMPREG(DSI_VC_TE(3)); |
| 1882 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); |
| 1883 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); |
| 1884 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); |
| 1885 | DUMPREG(DSI_VC_IRQSTATUS(3)); |
| 1886 | DUMPREG(DSI_VC_IRQENABLE(3)); |
| 1887 | |
| 1888 | DUMPREG(DSI_DSIPHY_CFG0); |
| 1889 | DUMPREG(DSI_DSIPHY_CFG1); |
| 1890 | DUMPREG(DSI_DSIPHY_CFG2); |
| 1891 | DUMPREG(DSI_DSIPHY_CFG5); |
| 1892 | |
| 1893 | DUMPREG(DSI_PLL_CONTROL); |
| 1894 | DUMPREG(DSI_PLL_STATUS); |
| 1895 | DUMPREG(DSI_PLL_GO); |
| 1896 | DUMPREG(DSI_PLL_CONFIGURATION1); |
| 1897 | DUMPREG(DSI_PLL_CONFIGURATION2); |
| 1898 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1899 | dsi_disable_scp_clk(dsidev); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 1900 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1901 | #undef DUMPREG |
| 1902 | } |
| 1903 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1904 | enum dsi_cio_power_state { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1905 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
| 1906 | DSI_COMPLEXIO_POWER_ON = 0x1, |
| 1907 | DSI_COMPLEXIO_POWER_ULPS = 0x2, |
| 1908 | }; |
| 1909 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1910 | static int dsi_cio_power(struct platform_device *dsidev, |
| 1911 | enum dsi_cio_power_state state) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1912 | { |
| 1913 | int t = 0; |
| 1914 | |
| 1915 | /* PWR_CMD */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1916 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1917 | |
| 1918 | /* PWR_STATUS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1919 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), |
| 1920 | 26, 25) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1921 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1922 | DSSERR("failed to set complexio power state to " |
| 1923 | "%d\n", state); |
| 1924 | return -ENODEV; |
| 1925 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1926 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1927 | } |
| 1928 | |
| 1929 | return 0; |
| 1930 | } |
| 1931 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1932 | static void dsi_set_lane_config(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1933 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1934 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1935 | u32 r; |
| 1936 | |
| 1937 | int clk_lane = dssdev->phy.dsi.clk_lane; |
| 1938 | int data1_lane = dssdev->phy.dsi.data1_lane; |
| 1939 | int data2_lane = dssdev->phy.dsi.data2_lane; |
| 1940 | int clk_pol = dssdev->phy.dsi.clk_pol; |
| 1941 | int data1_pol = dssdev->phy.dsi.data1_pol; |
| 1942 | int data2_pol = dssdev->phy.dsi.data2_pol; |
| 1943 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1944 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1945 | r = FLD_MOD(r, clk_lane, 2, 0); |
| 1946 | r = FLD_MOD(r, clk_pol, 3, 3); |
| 1947 | r = FLD_MOD(r, data1_lane, 6, 4); |
| 1948 | r = FLD_MOD(r, data1_pol, 7, 7); |
| 1949 | r = FLD_MOD(r, data2_lane, 10, 8); |
| 1950 | r = FLD_MOD(r, data2_pol, 11, 11); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1951 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1952 | |
| 1953 | /* The configuration of the DSI complex I/O (number of data lanes, |
| 1954 | position, differential order) should not be changed while |
| 1955 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for |
| 1956 | the hardware to take into account a new configuration of the complex |
| 1957 | I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to |
| 1958 | follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, |
| 1959 | then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set |
| 1960 | DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the |
| 1961 | DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the |
| 1962 | DSI complex I/O configuration is unknown. */ |
| 1963 | |
| 1964 | /* |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1965 | REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0); |
| 1966 | REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0); |
| 1967 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); |
| 1968 | REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1969 | */ |
| 1970 | } |
| 1971 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1972 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1973 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1974 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1975 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1976 | /* convert time in ns to ddr ticks, rounding up */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1977 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1978 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
| 1979 | } |
| 1980 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1981 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1982 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 1983 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1984 | |
| 1985 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1986 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
| 1987 | } |
| 1988 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1989 | static void dsi_cio_timings(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1990 | { |
| 1991 | u32 r; |
| 1992 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; |
| 1993 | u32 tlpx_half, tclk_trail, tclk_zero; |
| 1994 | u32 tclk_prepare; |
| 1995 | |
| 1996 | /* calculate timings */ |
| 1997 | |
| 1998 | /* 1 * DDR_CLK = 2 * UI */ |
| 1999 | |
| 2000 | /* min 40ns + 4*UI max 85ns + 6*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2001 | ths_prepare = ns2ddr(dsidev, 70) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2002 | |
| 2003 | /* min 145ns + 10*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2004 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2005 | |
| 2006 | /* min max(8*UI, 60ns+4*UI) */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2007 | ths_trail = ns2ddr(dsidev, 60) + 5; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2008 | |
| 2009 | /* min 100ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2010 | ths_exit = ns2ddr(dsidev, 145); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2011 | |
| 2012 | /* tlpx min 50n */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2013 | tlpx_half = ns2ddr(dsidev, 25); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2014 | |
| 2015 | /* min 60ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2016 | tclk_trail = ns2ddr(dsidev, 60) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2017 | |
| 2018 | /* min 38ns, max 95ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2019 | tclk_prepare = ns2ddr(dsidev, 65); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2020 | |
| 2021 | /* min tclk-prepare + tclk-zero = 300ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2022 | tclk_zero = ns2ddr(dsidev, 260); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2023 | |
| 2024 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2025 | ths_prepare, ddr2ns(dsidev, ths_prepare), |
| 2026 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2027 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2028 | ths_trail, ddr2ns(dsidev, ths_trail), |
| 2029 | ths_exit, ddr2ns(dsidev, ths_exit)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2030 | |
| 2031 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " |
| 2032 | "tclk_zero %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2033 | tlpx_half, ddr2ns(dsidev, tlpx_half), |
| 2034 | tclk_trail, ddr2ns(dsidev, tclk_trail), |
| 2035 | tclk_zero, ddr2ns(dsidev, tclk_zero)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2036 | DSSDBG("tclk_prepare %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2037 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2038 | |
| 2039 | /* program timings */ |
| 2040 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2041 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2042 | r = FLD_MOD(r, ths_prepare, 31, 24); |
| 2043 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); |
| 2044 | r = FLD_MOD(r, ths_trail, 15, 8); |
| 2045 | r = FLD_MOD(r, ths_exit, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2046 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2047 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2048 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2049 | r = FLD_MOD(r, tlpx_half, 22, 16); |
| 2050 | r = FLD_MOD(r, tclk_trail, 15, 8); |
| 2051 | r = FLD_MOD(r, tclk_zero, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2052 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2053 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2054 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2055 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2056 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2057 | } |
| 2058 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2059 | static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2060 | enum dsi_lane lanes) |
| 2061 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2062 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2063 | int clk_lane = dssdev->phy.dsi.clk_lane; |
| 2064 | int data1_lane = dssdev->phy.dsi.data1_lane; |
| 2065 | int data2_lane = dssdev->phy.dsi.data2_lane; |
| 2066 | int clk_pol = dssdev->phy.dsi.clk_pol; |
| 2067 | int data1_pol = dssdev->phy.dsi.data1_pol; |
| 2068 | int data2_pol = dssdev->phy.dsi.data2_pol; |
| 2069 | |
| 2070 | u32 l = 0; |
| 2071 | |
| 2072 | if (lanes & DSI_CLK_P) |
| 2073 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1)); |
| 2074 | if (lanes & DSI_CLK_N) |
| 2075 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0)); |
| 2076 | |
| 2077 | if (lanes & DSI_DATA1_P) |
| 2078 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1)); |
| 2079 | if (lanes & DSI_DATA1_N) |
| 2080 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0)); |
| 2081 | |
| 2082 | if (lanes & DSI_DATA2_P) |
| 2083 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1)); |
| 2084 | if (lanes & DSI_DATA2_N) |
| 2085 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0)); |
| 2086 | |
| 2087 | /* |
| 2088 | * Bits in REGLPTXSCPDAT4TO0DXDY: |
| 2089 | * 17: DY0 18: DX0 |
| 2090 | * 19: DY1 20: DX1 |
| 2091 | * 21: DY2 22: DX2 |
| 2092 | */ |
| 2093 | |
| 2094 | /* Set the lane override configuration */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2095 | |
| 2096 | /* REGLPTXSCPDAT4TO0DXDY */ |
| 2097 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, 22, 17); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2098 | |
| 2099 | /* Enable lane override */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2100 | |
| 2101 | /* ENLPTXSCPDAT */ |
| 2102 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2103 | } |
| 2104 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2105 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2106 | { |
| 2107 | /* Disable lane override */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2108 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2109 | /* Reset the lane override configuration */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2110 | /* REGLPTXSCPDAT4TO0DXDY */ |
| 2111 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2112 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2113 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2114 | static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev) |
| 2115 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2116 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2117 | int t; |
| 2118 | int bits[3]; |
| 2119 | bool in_use[3]; |
| 2120 | |
| 2121 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
| 2122 | bits[0] = 28; |
| 2123 | bits[1] = 27; |
| 2124 | bits[2] = 26; |
| 2125 | } else { |
| 2126 | bits[0] = 24; |
| 2127 | bits[1] = 25; |
| 2128 | bits[2] = 26; |
| 2129 | } |
| 2130 | |
| 2131 | in_use[0] = false; |
| 2132 | in_use[1] = false; |
| 2133 | in_use[2] = false; |
| 2134 | |
| 2135 | if (dssdev->phy.dsi.clk_lane != 0) |
| 2136 | in_use[dssdev->phy.dsi.clk_lane - 1] = true; |
| 2137 | if (dssdev->phy.dsi.data1_lane != 0) |
| 2138 | in_use[dssdev->phy.dsi.data1_lane - 1] = true; |
| 2139 | if (dssdev->phy.dsi.data2_lane != 0) |
| 2140 | in_use[dssdev->phy.dsi.data2_lane - 1] = true; |
| 2141 | |
| 2142 | t = 100000; |
| 2143 | while (true) { |
| 2144 | u32 l; |
| 2145 | int i; |
| 2146 | int ok; |
| 2147 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2148 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2149 | |
| 2150 | ok = 0; |
| 2151 | for (i = 0; i < 3; ++i) { |
| 2152 | if (!in_use[i] || (l & (1 << bits[i]))) |
| 2153 | ok++; |
| 2154 | } |
| 2155 | |
| 2156 | if (ok == 3) |
| 2157 | break; |
| 2158 | |
| 2159 | if (--t == 0) { |
| 2160 | for (i = 0; i < 3; ++i) { |
| 2161 | if (!in_use[i] || (l & (1 << bits[i]))) |
| 2162 | continue; |
| 2163 | |
| 2164 | DSSERR("CIO TXCLKESC%d domain not coming " \ |
| 2165 | "out of reset\n", i); |
| 2166 | } |
| 2167 | return -EIO; |
| 2168 | } |
| 2169 | } |
| 2170 | |
| 2171 | return 0; |
| 2172 | } |
| 2173 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2174 | static int dsi_cio_init(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2175 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2176 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2177 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2178 | int r; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2179 | u32 l; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2180 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2181 | DSSDBGF(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2182 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2183 | if (dsi->dsi_mux_pads) |
| 2184 | dsi->dsi_mux_pads(true); |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 2185 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2186 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2187 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2188 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 2189 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 2190 | * I/O. */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2191 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2192 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2193 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2194 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
| 2195 | r = -EIO; |
| 2196 | goto err_scp_clk_dom; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2197 | } |
| 2198 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2199 | dsi_set_lane_config(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2200 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2201 | /* set TX STOP MODE timer to maximum for this operation */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2202 | l = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2203 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
| 2204 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ |
| 2205 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ |
| 2206 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2207 | dsi_write_reg(dsidev, DSI_TIMING1, l); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2208 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2209 | if (dsi->ulps_enabled) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2210 | DSSDBG("manual ulps exit\n"); |
| 2211 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2212 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
| 2213 | * stop state. DSS HW cannot do this via the normal |
| 2214 | * ULPS exit sequence, as after reset the DSS HW thinks |
| 2215 | * that we are not in ULPS mode, and refuses to send the |
| 2216 | * sequence. So we need to send the ULPS exit sequence |
| 2217 | * manually. |
| 2218 | */ |
| 2219 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2220 | dsi_cio_enable_lane_override(dssdev, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2221 | DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P); |
| 2222 | } |
| 2223 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2224 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2225 | if (r) |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2226 | goto err_cio_pwr; |
| 2227 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2228 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2229 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
| 2230 | r = -ENODEV; |
| 2231 | goto err_cio_pwr_dom; |
| 2232 | } |
| 2233 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2234 | dsi_if_enable(dsidev, true); |
| 2235 | dsi_if_enable(dsidev, false); |
| 2236 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2237 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2238 | r = dsi_cio_wait_tx_clk_esc_reset(dssdev); |
| 2239 | if (r) |
| 2240 | goto err_tx_clk_esc_rst; |
| 2241 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2242 | if (dsi->ulps_enabled) { |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2243 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
| 2244 | ktime_t wait = ns_to_ktime(1000 * 1000); |
| 2245 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 2246 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); |
| 2247 | |
| 2248 | /* Disable the override. The lanes should be set to Mark-11 |
| 2249 | * state by the HW */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2250 | dsi_cio_disable_lane_override(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2251 | } |
| 2252 | |
| 2253 | /* FORCE_TX_STOP_MODE_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2254 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2255 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2256 | dsi_cio_timings(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2257 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2258 | dsi->ulps_enabled = false; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2259 | |
| 2260 | DSSDBG("CIO init done\n"); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2261 | |
| 2262 | return 0; |
| 2263 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2264 | err_tx_clk_esc_rst: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2265 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2266 | err_cio_pwr_dom: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2267 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2268 | err_cio_pwr: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2269 | if (dsi->ulps_enabled) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2270 | dsi_cio_disable_lane_override(dsidev); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2271 | err_scp_clk_dom: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2272 | dsi_disable_scp_clk(dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2273 | if (dsi->dsi_mux_pads) |
| 2274 | dsi->dsi_mux_pads(false); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2275 | return r; |
| 2276 | } |
| 2277 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2278 | static void dsi_cio_uninit(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2279 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2280 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2281 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2282 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
| 2283 | dsi_disable_scp_clk(dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2284 | if (dsi->dsi_mux_pads) |
| 2285 | dsi->dsi_mux_pads(false); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2286 | } |
| 2287 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2288 | static int _dsi_wait_reset(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2289 | { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 2290 | int t = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2291 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2292 | while (REG_GET(dsidev, DSI_SYSSTATUS, 0, 0) == 0) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 2293 | if (++t > 5) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2294 | DSSERR("soft reset failed\n"); |
| 2295 | return -ENODEV; |
| 2296 | } |
| 2297 | udelay(1); |
| 2298 | } |
| 2299 | |
| 2300 | return 0; |
| 2301 | } |
| 2302 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2303 | static int _dsi_reset(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2304 | { |
| 2305 | /* Soft reset */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2306 | REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 1, 1, 1); |
| 2307 | return _dsi_wait_reset(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2308 | } |
| 2309 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2310 | static void dsi_config_tx_fifo(struct platform_device *dsidev, |
| 2311 | enum fifo_size size1, enum fifo_size size2, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2312 | enum fifo_size size3, enum fifo_size size4) |
| 2313 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2314 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2315 | u32 r = 0; |
| 2316 | int add = 0; |
| 2317 | int i; |
| 2318 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2319 | dsi->vc[0].fifo_size = size1; |
| 2320 | dsi->vc[1].fifo_size = size2; |
| 2321 | dsi->vc[2].fifo_size = size3; |
| 2322 | dsi->vc[3].fifo_size = size4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2323 | |
| 2324 | for (i = 0; i < 4; i++) { |
| 2325 | u8 v; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2326 | int size = dsi->vc[i].fifo_size; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2327 | |
| 2328 | if (add + size > 4) { |
| 2329 | DSSERR("Illegal FIFO configuration\n"); |
| 2330 | BUG(); |
| 2331 | } |
| 2332 | |
| 2333 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2334 | r |= v << (8 * i); |
| 2335 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2336 | add += size; |
| 2337 | } |
| 2338 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2339 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2340 | } |
| 2341 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2342 | static void dsi_config_rx_fifo(struct platform_device *dsidev, |
| 2343 | enum fifo_size size1, enum fifo_size size2, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2344 | enum fifo_size size3, enum fifo_size size4) |
| 2345 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2346 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2347 | u32 r = 0; |
| 2348 | int add = 0; |
| 2349 | int i; |
| 2350 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2351 | dsi->vc[0].fifo_size = size1; |
| 2352 | dsi->vc[1].fifo_size = size2; |
| 2353 | dsi->vc[2].fifo_size = size3; |
| 2354 | dsi->vc[3].fifo_size = size4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2355 | |
| 2356 | for (i = 0; i < 4; i++) { |
| 2357 | u8 v; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2358 | int size = dsi->vc[i].fifo_size; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2359 | |
| 2360 | if (add + size > 4) { |
| 2361 | DSSERR("Illegal FIFO configuration\n"); |
| 2362 | BUG(); |
| 2363 | } |
| 2364 | |
| 2365 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2366 | r |= v << (8 * i); |
| 2367 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2368 | add += size; |
| 2369 | } |
| 2370 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2371 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2372 | } |
| 2373 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2374 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2375 | { |
| 2376 | u32 r; |
| 2377 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2378 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2379 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2380 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2381 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2382 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2383 | DSSERR("TX_STOP bit not going down\n"); |
| 2384 | return -EIO; |
| 2385 | } |
| 2386 | |
| 2387 | return 0; |
| 2388 | } |
| 2389 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2390 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2391 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2392 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2393 | } |
| 2394 | |
| 2395 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) |
| 2396 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2397 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2398 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2399 | const int channel = dsi->update_channel; |
| 2400 | u8 bit = dsi->te_enabled ? 30 : 31; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2401 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2402 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit) == 0) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2403 | complete((struct completion *)data); |
| 2404 | } |
| 2405 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2406 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2407 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2408 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2409 | int r = 0; |
| 2410 | u8 bit; |
| 2411 | |
| 2412 | DECLARE_COMPLETION_ONSTACK(completion); |
| 2413 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2414 | bit = dsi->te_enabled ? 30 : 31; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2415 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2416 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2417 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2418 | if (r) |
| 2419 | goto err0; |
| 2420 | |
| 2421 | /* Wait for completion only if TE_EN/TE_START is still set */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2422 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2423 | if (wait_for_completion_timeout(&completion, |
| 2424 | msecs_to_jiffies(10)) == 0) { |
| 2425 | DSSERR("Failed to complete previous frame transfer\n"); |
| 2426 | r = -EIO; |
| 2427 | goto err1; |
| 2428 | } |
| 2429 | } |
| 2430 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2431 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2432 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2433 | |
| 2434 | return 0; |
| 2435 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2436 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
| 2437 | &completion, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2438 | err0: |
| 2439 | return r; |
| 2440 | } |
| 2441 | |
| 2442 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) |
| 2443 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2444 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2445 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2446 | const int channel = dsi->update_channel; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2447 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2448 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2449 | complete((struct completion *)data); |
| 2450 | } |
| 2451 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2452 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2453 | { |
| 2454 | int r = 0; |
| 2455 | |
| 2456 | DECLARE_COMPLETION_ONSTACK(completion); |
| 2457 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2458 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2459 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2460 | if (r) |
| 2461 | goto err0; |
| 2462 | |
| 2463 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2464 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2465 | if (wait_for_completion_timeout(&completion, |
| 2466 | msecs_to_jiffies(10)) == 0) { |
| 2467 | DSSERR("Failed to complete previous l4 transfer\n"); |
| 2468 | r = -EIO; |
| 2469 | goto err1; |
| 2470 | } |
| 2471 | } |
| 2472 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2473 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2474 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2475 | |
| 2476 | return 0; |
| 2477 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2478 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2479 | &completion, DSI_VC_IRQ_PACKET_SENT); |
| 2480 | err0: |
| 2481 | return r; |
| 2482 | } |
| 2483 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2484 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2485 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2486 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2487 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2488 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2489 | |
| 2490 | WARN_ON(in_interrupt()); |
| 2491 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2492 | if (!dsi_vc_is_enabled(dsidev, channel)) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2493 | return 0; |
| 2494 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2495 | switch (dsi->vc[channel].mode) { |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2496 | case DSI_VC_MODE_VP: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2497 | return dsi_sync_vc_vp(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2498 | case DSI_VC_MODE_L4: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2499 | return dsi_sync_vc_l4(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2500 | default: |
| 2501 | BUG(); |
| 2502 | } |
| 2503 | } |
| 2504 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2505 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, |
| 2506 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2507 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 2508 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
| 2509 | channel, enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2510 | |
| 2511 | enable = enable ? 1 : 0; |
| 2512 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2513 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2514 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2515 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), |
| 2516 | 0, enable) != enable) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2517 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
| 2518 | return -EIO; |
| 2519 | } |
| 2520 | |
| 2521 | return 0; |
| 2522 | } |
| 2523 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2524 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2525 | { |
| 2526 | u32 r; |
| 2527 | |
| 2528 | DSSDBGF("%d", channel); |
| 2529 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2530 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2531 | |
| 2532 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ |
| 2533 | DSSERR("VC(%d) busy when trying to configure it!\n", |
| 2534 | channel); |
| 2535 | |
| 2536 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 2537 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ |
| 2538 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ |
| 2539 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ |
| 2540 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ |
| 2541 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ |
| 2542 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2543 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
| 2544 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2545 | |
| 2546 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ |
| 2547 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ |
| 2548 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2549 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2550 | } |
| 2551 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2552 | static int dsi_vc_config_l4(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2553 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2554 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2555 | |
| 2556 | if (dsi->vc[channel].mode == DSI_VC_MODE_L4) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2557 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2558 | |
| 2559 | DSSDBGF("%d", channel); |
| 2560 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2561 | dsi_sync_vc(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2562 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2563 | dsi_vc_enable(dsidev, channel, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2564 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2565 | /* VC_BUSY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2566 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2567 | DSSERR("vc(%d) busy when trying to config for L4\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2568 | return -EIO; |
| 2569 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2570 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2571 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2572 | |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2573 | /* DCS_CMD_ENABLE */ |
| 2574 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2575 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 30, 30); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2576 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2577 | dsi_vc_enable(dsidev, channel, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2578 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2579 | dsi->vc[channel].mode = DSI_VC_MODE_L4; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2580 | |
| 2581 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2582 | } |
| 2583 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2584 | static int dsi_vc_config_vp(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2585 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2586 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2587 | |
| 2588 | if (dsi->vc[channel].mode == DSI_VC_MODE_VP) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2589 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2590 | |
| 2591 | DSSDBGF("%d", channel); |
| 2592 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2593 | dsi_sync_vc(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2594 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2595 | dsi_vc_enable(dsidev, channel, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2596 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2597 | /* VC_BUSY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2598 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2599 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2600 | return -EIO; |
| 2601 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2602 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2603 | /* SOURCE, 1 = video port */ |
| 2604 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 1, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2605 | |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2606 | /* DCS_CMD_ENABLE */ |
| 2607 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2608 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 30, 30); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2609 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2610 | dsi_vc_enable(dsidev, channel, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2611 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2612 | dsi->vc[channel].mode = DSI_VC_MODE_VP; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2613 | |
| 2614 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2615 | } |
| 2616 | |
| 2617 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2618 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
| 2619 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2620 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2621 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 2622 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2623 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
| 2624 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2625 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2626 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2627 | dsi_vc_enable(dsidev, channel, 0); |
| 2628 | dsi_if_enable(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2629 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2630 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2631 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2632 | dsi_vc_enable(dsidev, channel, 1); |
| 2633 | dsi_if_enable(dsidev, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2634 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2635 | dsi_force_tx_stop_mode_io(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2636 | } |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2637 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2638 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2639 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2640 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2641 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2642 | u32 val; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2643 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2644 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
| 2645 | (val >> 0) & 0xff, |
| 2646 | (val >> 8) & 0xff, |
| 2647 | (val >> 16) & 0xff, |
| 2648 | (val >> 24) & 0xff); |
| 2649 | } |
| 2650 | } |
| 2651 | |
| 2652 | static void dsi_show_rx_ack_with_err(u16 err) |
| 2653 | { |
| 2654 | DSSERR("\tACK with ERROR (%#x):\n", err); |
| 2655 | if (err & (1 << 0)) |
| 2656 | DSSERR("\t\tSoT Error\n"); |
| 2657 | if (err & (1 << 1)) |
| 2658 | DSSERR("\t\tSoT Sync Error\n"); |
| 2659 | if (err & (1 << 2)) |
| 2660 | DSSERR("\t\tEoT Sync Error\n"); |
| 2661 | if (err & (1 << 3)) |
| 2662 | DSSERR("\t\tEscape Mode Entry Command Error\n"); |
| 2663 | if (err & (1 << 4)) |
| 2664 | DSSERR("\t\tLP Transmit Sync Error\n"); |
| 2665 | if (err & (1 << 5)) |
| 2666 | DSSERR("\t\tHS Receive Timeout Error\n"); |
| 2667 | if (err & (1 << 6)) |
| 2668 | DSSERR("\t\tFalse Control Error\n"); |
| 2669 | if (err & (1 << 7)) |
| 2670 | DSSERR("\t\t(reserved7)\n"); |
| 2671 | if (err & (1 << 8)) |
| 2672 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); |
| 2673 | if (err & (1 << 9)) |
| 2674 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); |
| 2675 | if (err & (1 << 10)) |
| 2676 | DSSERR("\t\tChecksum Error\n"); |
| 2677 | if (err & (1 << 11)) |
| 2678 | DSSERR("\t\tData type not recognized\n"); |
| 2679 | if (err & (1 << 12)) |
| 2680 | DSSERR("\t\tInvalid VC ID\n"); |
| 2681 | if (err & (1 << 13)) |
| 2682 | DSSERR("\t\tInvalid Transmission Length\n"); |
| 2683 | if (err & (1 << 14)) |
| 2684 | DSSERR("\t\t(reserved14)\n"); |
| 2685 | if (err & (1 << 15)) |
| 2686 | DSSERR("\t\tDSI Protocol Violation\n"); |
| 2687 | } |
| 2688 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2689 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, |
| 2690 | int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2691 | { |
| 2692 | /* RX_FIFO_NOT_EMPTY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2693 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2694 | u32 val; |
| 2695 | u8 dt; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2696 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2697 | DSSERR("\trawval %#08x\n", val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2698 | dt = FLD_GET(val, 5, 0); |
| 2699 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 2700 | u16 err = FLD_GET(val, 23, 8); |
| 2701 | dsi_show_rx_ack_with_err(err); |
| 2702 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2703 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2704 | FLD_GET(val, 23, 8)); |
| 2705 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2706 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2707 | FLD_GET(val, 23, 8)); |
| 2708 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2709 | DSSERR("\tDCS long response, len %d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2710 | FLD_GET(val, 23, 8)); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2711 | dsi_vc_flush_long_data(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2712 | } else { |
| 2713 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
| 2714 | } |
| 2715 | } |
| 2716 | return 0; |
| 2717 | } |
| 2718 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2719 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2720 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2721 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2722 | |
| 2723 | if (dsi->debug_write || dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2724 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
| 2725 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2726 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2727 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2728 | /* RX_FIFO_NOT_EMPTY */ |
| 2729 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2730 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2731 | dsi_vc_flush_receive_data(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2732 | } |
| 2733 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2734 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2735 | |
| 2736 | return 0; |
| 2737 | } |
| 2738 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2739 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2740 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2741 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2742 | DECLARE_COMPLETION_ONSTACK(completion); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2743 | int r = 0; |
| 2744 | u32 err; |
| 2745 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2746 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2747 | &completion, DSI_VC_IRQ_BTA); |
| 2748 | if (r) |
| 2749 | goto err0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2750 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2751 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2752 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2753 | if (r) |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2754 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2755 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2756 | r = dsi_vc_send_bta(dsidev, channel); |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2757 | if (r) |
| 2758 | goto err2; |
| 2759 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2760 | if (wait_for_completion_timeout(&completion, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2761 | msecs_to_jiffies(500)) == 0) { |
| 2762 | DSSERR("Failed to receive BTA\n"); |
| 2763 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2764 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2765 | } |
| 2766 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2767 | err = dsi_get_errors(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2768 | if (err) { |
| 2769 | DSSERR("Error while sending BTA: %x\n", err); |
| 2770 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2771 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2772 | } |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2773 | err2: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2774 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2775 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2776 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2777 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2778 | &completion, DSI_VC_IRQ_BTA); |
| 2779 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2780 | return r; |
| 2781 | } |
| 2782 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); |
| 2783 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2784 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, |
| 2785 | int channel, u8 data_type, u16 len, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2786 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2787 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2788 | u32 val; |
| 2789 | u8 data_id; |
| 2790 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2791 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2792 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2793 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2794 | |
| 2795 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | |
| 2796 | FLD_VAL(ecc, 31, 24); |
| 2797 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2798 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2799 | } |
| 2800 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2801 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, |
| 2802 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2803 | { |
| 2804 | u32 val; |
| 2805 | |
| 2806 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; |
| 2807 | |
| 2808 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", |
| 2809 | b1, b2, b3, b4, val); */ |
| 2810 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2811 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2812 | } |
| 2813 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2814 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, |
| 2815 | u8 data_type, u8 *data, u16 len, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2816 | { |
| 2817 | /*u32 val; */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2818 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2819 | int i; |
| 2820 | u8 *p; |
| 2821 | int r = 0; |
| 2822 | u8 b1, b2, b3, b4; |
| 2823 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2824 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2825 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
| 2826 | |
| 2827 | /* len + header */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2828 | if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2829 | DSSERR("unable to send long packet: packet too long.\n"); |
| 2830 | return -EINVAL; |
| 2831 | } |
| 2832 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2833 | dsi_vc_config_l4(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2834 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2835 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2836 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2837 | p = data; |
| 2838 | for (i = 0; i < len >> 2; i++) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2839 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2840 | DSSDBG("\tsending full packet %d\n", i); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2841 | |
| 2842 | b1 = *p++; |
| 2843 | b2 = *p++; |
| 2844 | b3 = *p++; |
| 2845 | b4 = *p++; |
| 2846 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2847 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2848 | } |
| 2849 | |
| 2850 | i = len % 4; |
| 2851 | if (i) { |
| 2852 | b1 = 0; b2 = 0; b3 = 0; |
| 2853 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2854 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2855 | DSSDBG("\tsending remainder bytes %d\n", i); |
| 2856 | |
| 2857 | switch (i) { |
| 2858 | case 3: |
| 2859 | b1 = *p++; |
| 2860 | b2 = *p++; |
| 2861 | b3 = *p++; |
| 2862 | break; |
| 2863 | case 2: |
| 2864 | b1 = *p++; |
| 2865 | b2 = *p++; |
| 2866 | break; |
| 2867 | case 1: |
| 2868 | b1 = *p++; |
| 2869 | break; |
| 2870 | } |
| 2871 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2872 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2873 | } |
| 2874 | |
| 2875 | return r; |
| 2876 | } |
| 2877 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2878 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, |
| 2879 | u8 data_type, u16 data, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2880 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2881 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2882 | u32 r; |
| 2883 | u8 data_id; |
| 2884 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2885 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2886 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2887 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2888 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
| 2889 | channel, |
| 2890 | data_type, data & 0xff, (data >> 8) & 0xff); |
| 2891 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2892 | dsi_vc_config_l4(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2893 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2894 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2895 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
| 2896 | return -EINVAL; |
| 2897 | } |
| 2898 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2899 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2900 | |
| 2901 | r = (data_id << 0) | (data << 8) | (ecc << 24); |
| 2902 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2903 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2904 | |
| 2905 | return 0; |
| 2906 | } |
| 2907 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2908 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2909 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2910 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2911 | u8 nullpkg[] = {0, 0, 0, 0}; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2912 | |
| 2913 | return dsi_vc_send_long(dsidev, channel, DSI_DT_NULL_PACKET, nullpkg, |
| 2914 | 4, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2915 | } |
| 2916 | EXPORT_SYMBOL(dsi_vc_send_null); |
| 2917 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2918 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
| 2919 | u8 *data, int len) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2920 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2921 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2922 | int r; |
| 2923 | |
| 2924 | BUG_ON(len == 0); |
| 2925 | |
| 2926 | if (len == 1) { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2927 | r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_0, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2928 | data[0], 0); |
| 2929 | } else if (len == 2) { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2930 | r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_1, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2931 | data[0] | (data[1] << 8), 0); |
| 2932 | } else { |
| 2933 | /* 0x39 = DCS Long Write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2934 | r = dsi_vc_send_long(dsidev, channel, DSI_DT_DCS_LONG_WRITE, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2935 | data, len, 0); |
| 2936 | } |
| 2937 | |
| 2938 | return r; |
| 2939 | } |
| 2940 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
| 2941 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2942 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
| 2943 | int len) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2944 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2945 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2946 | int r; |
| 2947 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2948 | r = dsi_vc_dcs_write_nosync(dssdev, channel, data, len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2949 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2950 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2951 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2952 | r = dsi_vc_send_bta_sync(dssdev, channel); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2953 | if (r) |
| 2954 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2955 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2956 | /* RX_FIFO_NOT_EMPTY */ |
| 2957 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 2958 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2959 | dsi_vc_flush_receive_data(dsidev, channel); |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 2960 | r = -EIO; |
| 2961 | goto err; |
| 2962 | } |
| 2963 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2964 | return 0; |
| 2965 | err: |
| 2966 | DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n", |
| 2967 | channel, data[0], len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2968 | return r; |
| 2969 | } |
| 2970 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
| 2971 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2972 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd) |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2973 | { |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2974 | return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1); |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2975 | } |
| 2976 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); |
| 2977 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2978 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
| 2979 | u8 param) |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2980 | { |
| 2981 | u8 buf[2]; |
| 2982 | buf[0] = dcs_cmd; |
| 2983 | buf[1] = param; |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2984 | return dsi_vc_dcs_write(dssdev, channel, buf, 2); |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 2985 | } |
| 2986 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); |
| 2987 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2988 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
| 2989 | u8 *buf, int buflen) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2990 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2991 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2992 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2993 | u32 val; |
| 2994 | u8 dt; |
| 2995 | int r; |
| 2996 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 2997 | if (dsi->debug_read) |
Tomi Valkeinen | ff90a34 | 2009-12-03 13:38:04 +0200 | [diff] [blame] | 2998 | DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2999 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3000 | r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_READ, dcs_cmd, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3001 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3002 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3003 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3004 | r = dsi_vc_send_bta_sync(dssdev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3005 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3006 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3007 | |
| 3008 | /* RX_FIFO_NOT_EMPTY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3009 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3010 | DSSERR("RX fifo empty when trying to read.\n"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3011 | r = -EIO; |
| 3012 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3013 | } |
| 3014 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3015 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3016 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3017 | DSSDBG("\theader: %08x\n", val); |
| 3018 | dt = FLD_GET(val, 5, 0); |
| 3019 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { |
| 3020 | u16 err = FLD_GET(val, 23, 8); |
| 3021 | dsi_show_rx_ack_with_err(err); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3022 | r = -EIO; |
| 3023 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3024 | |
| 3025 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { |
| 3026 | u8 data = FLD_GET(val, 15, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3027 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3028 | DSSDBG("\tDCS short response, 1 byte: %02x\n", data); |
| 3029 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3030 | if (buflen < 1) { |
| 3031 | r = -EIO; |
| 3032 | goto err; |
| 3033 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3034 | |
| 3035 | buf[0] = data; |
| 3036 | |
| 3037 | return 1; |
| 3038 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { |
| 3039 | u16 data = FLD_GET(val, 23, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3040 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3041 | DSSDBG("\tDCS short response, 2 byte: %04x\n", data); |
| 3042 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3043 | if (buflen < 2) { |
| 3044 | r = -EIO; |
| 3045 | goto err; |
| 3046 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3047 | |
| 3048 | buf[0] = data & 0xff; |
| 3049 | buf[1] = (data >> 8) & 0xff; |
| 3050 | |
| 3051 | return 2; |
| 3052 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { |
| 3053 | int w; |
| 3054 | int len = FLD_GET(val, 23, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3055 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3056 | DSSDBG("\tDCS long response, len %d\n", len); |
| 3057 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3058 | if (len > buflen) { |
| 3059 | r = -EIO; |
| 3060 | goto err; |
| 3061 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3062 | |
| 3063 | /* two byte checksum ends the packet, not included in len */ |
| 3064 | for (w = 0; w < len + 2;) { |
| 3065 | int b; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3066 | val = dsi_read_reg(dsidev, |
| 3067 | DSI_VC_SHORT_PACKET_HEADER(channel)); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3068 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3069 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
| 3070 | (val >> 0) & 0xff, |
| 3071 | (val >> 8) & 0xff, |
| 3072 | (val >> 16) & 0xff, |
| 3073 | (val >> 24) & 0xff); |
| 3074 | |
| 3075 | for (b = 0; b < 4; ++b) { |
| 3076 | if (w < len) |
| 3077 | buf[w] = (val >> (b * 8)) & 0xff; |
| 3078 | /* we discard the 2 byte checksum */ |
| 3079 | ++w; |
| 3080 | } |
| 3081 | } |
| 3082 | |
| 3083 | return len; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3084 | } else { |
| 3085 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3086 | r = -EIO; |
| 3087 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3088 | } |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3089 | |
| 3090 | BUG(); |
| 3091 | err: |
| 3092 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", |
| 3093 | channel, dcs_cmd); |
| 3094 | return r; |
| 3095 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3096 | } |
| 3097 | EXPORT_SYMBOL(dsi_vc_dcs_read); |
| 3098 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3099 | int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
| 3100 | u8 *data) |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 3101 | { |
| 3102 | int r; |
| 3103 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3104 | r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, data, 1); |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 3105 | |
| 3106 | if (r < 0) |
| 3107 | return r; |
| 3108 | |
| 3109 | if (r != 1) |
| 3110 | return -EIO; |
| 3111 | |
| 3112 | return 0; |
| 3113 | } |
| 3114 | EXPORT_SYMBOL(dsi_vc_dcs_read_1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3115 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3116 | int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
| 3117 | u8 *data1, u8 *data2) |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 3118 | { |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 3119 | u8 buf[2]; |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 3120 | int r; |
| 3121 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3122 | r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, buf, 2); |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 3123 | |
| 3124 | if (r < 0) |
| 3125 | return r; |
| 3126 | |
| 3127 | if (r != 2) |
| 3128 | return -EIO; |
| 3129 | |
Tomi Valkeinen | 0c244f7 | 2010-06-09 15:19:29 +0300 | [diff] [blame] | 3130 | *data1 = buf[0]; |
| 3131 | *data2 = buf[1]; |
| 3132 | |
Tomi Valkeinen | 53055aa | 2010-02-25 11:38:13 +0200 | [diff] [blame] | 3133 | return 0; |
| 3134 | } |
| 3135 | EXPORT_SYMBOL(dsi_vc_dcs_read_2); |
| 3136 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3137 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
| 3138 | u16 len) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3139 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3140 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3141 | |
| 3142 | return dsi_vc_send_short(dsidev, channel, DSI_DT_SET_MAX_RET_PKG_SIZE, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3143 | len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3144 | } |
| 3145 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); |
| 3146 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3147 | static int dsi_enter_ulps(struct platform_device *dsidev) |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3148 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3149 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3150 | DECLARE_COMPLETION_ONSTACK(completion); |
| 3151 | int r; |
| 3152 | |
| 3153 | DSSDBGF(); |
| 3154 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3155 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3156 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3157 | WARN_ON(dsi->ulps_enabled); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3158 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3159 | if (dsi->ulps_enabled) |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3160 | return 0; |
| 3161 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3162 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3163 | DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n"); |
| 3164 | return -EIO; |
| 3165 | } |
| 3166 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3167 | dsi_sync_vc(dsidev, 0); |
| 3168 | dsi_sync_vc(dsidev, 1); |
| 3169 | dsi_sync_vc(dsidev, 2); |
| 3170 | dsi_sync_vc(dsidev, 3); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3171 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3172 | dsi_force_tx_stop_mode_io(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3173 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3174 | dsi_vc_enable(dsidev, 0, false); |
| 3175 | dsi_vc_enable(dsidev, 1, false); |
| 3176 | dsi_vc_enable(dsidev, 2, false); |
| 3177 | dsi_vc_enable(dsidev, 3, false); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3178 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3179 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3180 | DSSERR("HS busy when enabling ULPS\n"); |
| 3181 | return -EIO; |
| 3182 | } |
| 3183 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3184 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3185 | DSSERR("LP busy when enabling ULPS\n"); |
| 3186 | return -EIO; |
| 3187 | } |
| 3188 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3189 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3190 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3191 | if (r) |
| 3192 | return r; |
| 3193 | |
| 3194 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ |
| 3195 | /* LANEx_ULPS_SIG2 */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3196 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2), |
| 3197 | 7, 5); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3198 | |
| 3199 | if (wait_for_completion_timeout(&completion, |
| 3200 | msecs_to_jiffies(1000)) == 0) { |
| 3201 | DSSERR("ULPS enable timeout\n"); |
| 3202 | r = -EIO; |
| 3203 | goto err; |
| 3204 | } |
| 3205 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3206 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3207 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3208 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3209 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3210 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3211 | dsi_if_enable(dsidev, false); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3212 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3213 | dsi->ulps_enabled = true; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3214 | |
| 3215 | return 0; |
| 3216 | |
| 3217 | err: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3218 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3219 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3220 | return r; |
| 3221 | } |
| 3222 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3223 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, |
| 3224 | unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3225 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3226 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3227 | unsigned long total_ticks; |
| 3228 | u32 r; |
| 3229 | |
| 3230 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3231 | |
| 3232 | /* ticks in DSI_FCK */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3233 | fck = dsi_fclk_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3234 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3235 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3236 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3237 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
| 3238 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3239 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3240 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3241 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3242 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3243 | |
| 3244 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3245 | total_ticks, |
| 3246 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3247 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3248 | } |
| 3249 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3250 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, |
| 3251 | bool x8, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3252 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3253 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3254 | unsigned long total_ticks; |
| 3255 | u32 r; |
| 3256 | |
| 3257 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3258 | |
| 3259 | /* ticks in DSI_FCK */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3260 | fck = dsi_fclk_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3261 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3262 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3263 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3264 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
| 3265 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3266 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3267 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3268 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3269 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
| 3270 | |
| 3271 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3272 | total_ticks, |
| 3273 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", |
| 3274 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3275 | } |
| 3276 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3277 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, |
| 3278 | unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3279 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3280 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3281 | unsigned long total_ticks; |
| 3282 | u32 r; |
| 3283 | |
| 3284 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3285 | |
| 3286 | /* ticks in DSI_FCK */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3287 | fck = dsi_fclk_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3288 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3289 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3290 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3291 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
| 3292 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3293 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3294 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3295 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3296 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3297 | |
| 3298 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", |
| 3299 | total_ticks, |
| 3300 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3301 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3302 | } |
| 3303 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3304 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, |
| 3305 | unsigned ticks, bool x4, bool x16) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3306 | { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3307 | unsigned long fck; |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3308 | unsigned long total_ticks; |
| 3309 | u32 r; |
| 3310 | |
| 3311 | BUG_ON(ticks > 0x1fff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3312 | |
| 3313 | /* ticks in TxByteClkHS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3314 | fck = dsi_get_txbyteclkhs(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3315 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3316 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3317 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3318 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
| 3319 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3320 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3321 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3322 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3323 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3324 | |
| 3325 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3326 | total_ticks, |
| 3327 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3328 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3329 | } |
| 3330 | static int dsi_proto_config(struct omap_dss_device *dssdev) |
| 3331 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3332 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3333 | u32 r; |
| 3334 | int buswidth = 0; |
| 3335 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3336 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3337 | DSI_FIFO_SIZE_32, |
| 3338 | DSI_FIFO_SIZE_32, |
| 3339 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3340 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3341 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3342 | DSI_FIFO_SIZE_32, |
| 3343 | DSI_FIFO_SIZE_32, |
| 3344 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3345 | |
| 3346 | /* XXX what values for the timeouts? */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3347 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); |
| 3348 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); |
| 3349 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); |
| 3350 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3351 | |
| 3352 | switch (dssdev->ctrl.pixel_size) { |
| 3353 | case 16: |
| 3354 | buswidth = 0; |
| 3355 | break; |
| 3356 | case 18: |
| 3357 | buswidth = 1; |
| 3358 | break; |
| 3359 | case 24: |
| 3360 | buswidth = 2; |
| 3361 | break; |
| 3362 | default: |
| 3363 | BUG(); |
| 3364 | } |
| 3365 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3366 | r = dsi_read_reg(dsidev, DSI_CTRL); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3367 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
| 3368 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ |
| 3369 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ |
| 3370 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ |
| 3371 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ |
| 3372 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ |
| 3373 | r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ |
| 3374 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
| 3375 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 3376 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
| 3377 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ |
| 3378 | /* DCS_CMD_CODE, 1=start, 0=continue */ |
| 3379 | r = FLD_MOD(r, 0, 25, 25); |
| 3380 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3381 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3382 | dsi_write_reg(dsidev, DSI_CTRL, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3383 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3384 | dsi_vc_initial_config(dsidev, 0); |
| 3385 | dsi_vc_initial_config(dsidev, 1); |
| 3386 | dsi_vc_initial_config(dsidev, 2); |
| 3387 | dsi_vc_initial_config(dsidev, 3); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3388 | |
| 3389 | return 0; |
| 3390 | } |
| 3391 | |
| 3392 | static void dsi_proto_timings(struct omap_dss_device *dssdev) |
| 3393 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3394 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3395 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
| 3396 | unsigned tclk_pre, tclk_post; |
| 3397 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; |
| 3398 | unsigned ths_trail, ths_exit; |
| 3399 | unsigned ddr_clk_pre, ddr_clk_post; |
| 3400 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; |
| 3401 | unsigned ths_eot; |
| 3402 | u32 r; |
| 3403 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3404 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3405 | ths_prepare = FLD_GET(r, 31, 24); |
| 3406 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); |
| 3407 | ths_zero = ths_prepare_ths_zero - ths_prepare; |
| 3408 | ths_trail = FLD_GET(r, 15, 8); |
| 3409 | ths_exit = FLD_GET(r, 7, 0); |
| 3410 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3411 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3412 | tlpx = FLD_GET(r, 22, 16) * 2; |
| 3413 | tclk_trail = FLD_GET(r, 15, 8); |
| 3414 | tclk_zero = FLD_GET(r, 7, 0); |
| 3415 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3416 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3417 | tclk_prepare = FLD_GET(r, 7, 0); |
| 3418 | |
| 3419 | /* min 8*UI */ |
| 3420 | tclk_pre = 20; |
| 3421 | /* min 60ns + 52*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3422 | tclk_post = ns2ddr(dsidev, 60) + 26; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3423 | |
| 3424 | /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */ |
| 3425 | if (dssdev->phy.dsi.data1_lane != 0 && |
| 3426 | dssdev->phy.dsi.data2_lane != 0) |
| 3427 | ths_eot = 2; |
| 3428 | else |
| 3429 | ths_eot = 4; |
| 3430 | |
| 3431 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, |
| 3432 | 4); |
| 3433 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; |
| 3434 | |
| 3435 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); |
| 3436 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); |
| 3437 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3438 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3439 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
| 3440 | r = FLD_MOD(r, ddr_clk_post, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3441 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3442 | |
| 3443 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", |
| 3444 | ddr_clk_pre, |
| 3445 | ddr_clk_post); |
| 3446 | |
| 3447 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + |
| 3448 | DIV_ROUND_UP(ths_prepare, 4) + |
| 3449 | DIV_ROUND_UP(ths_zero + 3, 4); |
| 3450 | |
| 3451 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; |
| 3452 | |
| 3453 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | |
| 3454 | FLD_VAL(exit_hs_mode_lat, 15, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3455 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3456 | |
| 3457 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", |
| 3458 | enter_hs_mode_lat, exit_hs_mode_lat); |
| 3459 | } |
| 3460 | |
| 3461 | |
| 3462 | #define DSI_DECL_VARS \ |
| 3463 | int __dsi_cb = 0; u32 __dsi_cv = 0; |
| 3464 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3465 | #define DSI_FLUSH(dsidev, ch) \ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3466 | if (__dsi_cb > 0) { \ |
| 3467 | /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3468 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3469 | __dsi_cb = __dsi_cv = 0; \ |
| 3470 | } |
| 3471 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3472 | #define DSI_PUSH(dsidev, ch, data) \ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3473 | do { \ |
| 3474 | __dsi_cv |= (data) << (__dsi_cb * 8); \ |
| 3475 | /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \ |
| 3476 | if (++__dsi_cb > 3) \ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3477 | DSI_FLUSH(dsidev, ch); \ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3478 | } while (0) |
| 3479 | |
| 3480 | static int dsi_update_screen_l4(struct omap_dss_device *dssdev, |
| 3481 | int x, int y, int w, int h) |
| 3482 | { |
| 3483 | /* Note: supports only 24bit colors in 32bit container */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3484 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3485 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3486 | int first = 1; |
| 3487 | int fifo_stalls = 0; |
| 3488 | int max_dsi_packet_size; |
| 3489 | int max_data_per_packet; |
| 3490 | int max_pixels_per_packet; |
| 3491 | int pixels_left; |
| 3492 | int bytespp = dssdev->ctrl.pixel_size / 8; |
| 3493 | int scr_width; |
| 3494 | u32 __iomem *data; |
| 3495 | int start_offset; |
| 3496 | int horiz_inc; |
| 3497 | int current_x; |
| 3498 | struct omap_overlay *ovl; |
| 3499 | |
| 3500 | debug_irq = 0; |
| 3501 | |
| 3502 | DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n", |
| 3503 | x, y, w, h); |
| 3504 | |
| 3505 | ovl = dssdev->manager->overlays[0]; |
| 3506 | |
| 3507 | if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U) |
| 3508 | return -EINVAL; |
| 3509 | |
| 3510 | if (dssdev->ctrl.pixel_size != 24) |
| 3511 | return -EINVAL; |
| 3512 | |
| 3513 | scr_width = ovl->info.screen_width; |
| 3514 | data = ovl->info.vaddr; |
| 3515 | |
| 3516 | start_offset = scr_width * y + x; |
| 3517 | horiz_inc = scr_width - w; |
| 3518 | current_x = x; |
| 3519 | |
| 3520 | /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes |
| 3521 | * in fifo */ |
| 3522 | |
| 3523 | /* When using CPU, max long packet size is TX buffer size */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3524 | max_dsi_packet_size = dsi->vc[0].fifo_size * 32 * 4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3525 | |
| 3526 | /* we seem to get better perf if we divide the tx fifo to half, |
| 3527 | and while the other half is being sent, we fill the other half |
| 3528 | max_dsi_packet_size /= 2; */ |
| 3529 | |
| 3530 | max_data_per_packet = max_dsi_packet_size - 4 - 1; |
| 3531 | |
| 3532 | max_pixels_per_packet = max_data_per_packet / bytespp; |
| 3533 | |
| 3534 | DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet); |
| 3535 | |
| 3536 | pixels_left = w * h; |
| 3537 | |
| 3538 | DSSDBG("total pixels %d\n", pixels_left); |
| 3539 | |
| 3540 | data += start_offset; |
| 3541 | |
| 3542 | while (pixels_left > 0) { |
| 3543 | /* 0x2c = write_memory_start */ |
| 3544 | /* 0x3c = write_memory_continue */ |
| 3545 | u8 dcs_cmd = first ? 0x2c : 0x3c; |
| 3546 | int pixels; |
| 3547 | DSI_DECL_VARS; |
| 3548 | first = 0; |
| 3549 | |
| 3550 | #if 1 |
| 3551 | /* using fifo not empty */ |
| 3552 | /* TX_FIFO_NOT_EMPTY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3553 | while (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(0)), 5, 5)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3554 | fifo_stalls++; |
| 3555 | if (fifo_stalls > 0xfffff) { |
| 3556 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 3557 | pixels_left); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3558 | dsi_if_enable(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3559 | return -EIO; |
| 3560 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 3561 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3562 | } |
| 3563 | #elif 1 |
| 3564 | /* using fifo emptiness */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3565 | while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 < |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3566 | max_dsi_packet_size) { |
| 3567 | fifo_stalls++; |
| 3568 | if (fifo_stalls > 0xfffff) { |
| 3569 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 3570 | pixels_left); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3571 | dsi_if_enable(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3572 | return -EIO; |
| 3573 | } |
| 3574 | } |
| 3575 | #else |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3576 | while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS, |
| 3577 | 7, 0) + 1) * 4 == 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3578 | fifo_stalls++; |
| 3579 | if (fifo_stalls > 0xfffff) { |
| 3580 | DSSERR("fifo stalls overflow, pixels left %d\n", |
| 3581 | pixels_left); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3582 | dsi_if_enable(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3583 | return -EIO; |
| 3584 | } |
| 3585 | } |
| 3586 | #endif |
| 3587 | pixels = min(max_pixels_per_packet, pixels_left); |
| 3588 | |
| 3589 | pixels_left -= pixels; |
| 3590 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3591 | dsi_vc_write_long_header(dsidev, 0, DSI_DT_DCS_LONG_WRITE, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3592 | 1 + pixels * bytespp, 0); |
| 3593 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3594 | DSI_PUSH(dsidev, 0, dcs_cmd); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3595 | |
| 3596 | while (pixels-- > 0) { |
| 3597 | u32 pix = __raw_readl(data++); |
| 3598 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3599 | DSI_PUSH(dsidev, 0, (pix >> 16) & 0xff); |
| 3600 | DSI_PUSH(dsidev, 0, (pix >> 8) & 0xff); |
| 3601 | DSI_PUSH(dsidev, 0, (pix >> 0) & 0xff); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3602 | |
| 3603 | current_x++; |
| 3604 | if (current_x == x+w) { |
| 3605 | current_x = x; |
| 3606 | data += horiz_inc; |
| 3607 | } |
| 3608 | } |
| 3609 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3610 | DSI_FLUSH(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3611 | } |
| 3612 | |
| 3613 | return 0; |
| 3614 | } |
| 3615 | |
| 3616 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, |
| 3617 | u16 x, u16 y, u16 w, u16 h) |
| 3618 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3619 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3620 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3621 | unsigned bytespp; |
| 3622 | unsigned bytespl; |
| 3623 | unsigned bytespf; |
| 3624 | unsigned total_len; |
| 3625 | unsigned packet_payload; |
| 3626 | unsigned packet_len; |
| 3627 | u32 l; |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3628 | int r; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3629 | const unsigned channel = dsi->update_channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3630 | /* line buffer is 1024 x 24bits */ |
| 3631 | /* XXX: for some reason using full buffer size causes considerable TX |
| 3632 | * slowdown with update sizes that fill the whole buffer */ |
| 3633 | const unsigned line_buf_size = 1023 * 3; |
| 3634 | |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 3635 | DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", |
| 3636 | x, y, w, h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3637 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3638 | dsi_vc_config_vp(dsidev, channel); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3639 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3640 | bytespp = dssdev->ctrl.pixel_size / 8; |
| 3641 | bytespl = w * bytespp; |
| 3642 | bytespf = bytespl * h; |
| 3643 | |
| 3644 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is |
| 3645 | * number of lines in a packet. See errata about VP_CLK_RATIO */ |
| 3646 | |
| 3647 | if (bytespf < line_buf_size) |
| 3648 | packet_payload = bytespf; |
| 3649 | else |
| 3650 | packet_payload = (line_buf_size) / bytespl * bytespl; |
| 3651 | |
| 3652 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ |
| 3653 | total_len = (bytespf / packet_payload) * packet_len; |
| 3654 | |
| 3655 | if (bytespf % packet_payload) |
| 3656 | total_len += (bytespf % packet_payload) + 1; |
| 3657 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3658 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3659 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3660 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3661 | dsi_vc_write_long_header(dsidev, channel, DSI_DT_DCS_LONG_WRITE, |
| 3662 | packet_len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3663 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3664 | if (dsi->te_enabled) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3665 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
| 3666 | else |
| 3667 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3668 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3669 | |
| 3670 | /* We put SIDLEMODE to no-idle for the duration of the transfer, |
| 3671 | * because DSS interrupts are not capable of waking up the CPU and the |
| 3672 | * framedone interrupt could be delayed for quite a long time. I think |
| 3673 | * the same goes for any DSS interrupts, but for some reason I have not |
| 3674 | * seen the problem anywhere else than here. |
| 3675 | */ |
| 3676 | dispc_disable_sidle(); |
| 3677 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3678 | dsi_perf_mark_start(dsidev); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3679 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3680 | r = queue_delayed_work(dsi->workqueue, &dsi->framedone_timeout_work, |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3681 | msecs_to_jiffies(250)); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3682 | BUG_ON(r == 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3683 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3684 | dss_start_update(dssdev); |
| 3685 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3686 | if (dsi->te_enabled) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3687 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
| 3688 | * for TE is longer than the timer allows */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3689 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3690 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3691 | dsi_vc_send_bta(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3692 | |
| 3693 | #ifdef DSI_CATCH_MISSING_TE |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3694 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3695 | #endif |
| 3696 | } |
| 3697 | } |
| 3698 | |
| 3699 | #ifdef DSI_CATCH_MISSING_TE |
| 3700 | static void dsi_te_timeout(unsigned long arg) |
| 3701 | { |
| 3702 | DSSERR("TE not received for 250ms!\n"); |
| 3703 | } |
| 3704 | #endif |
| 3705 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3706 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3707 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3708 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 3709 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3710 | /* SIDLEMODE back to smart-idle */ |
| 3711 | dispc_enable_sidle(); |
| 3712 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3713 | if (dsi->te_enabled) { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3714 | /* enable LP_RX_TO again after the TE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3715 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3716 | } |
| 3717 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3718 | dsi->framedone_callback(error, dsi->framedone_data); |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3719 | |
| 3720 | if (!error) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3721 | dsi_perf_show(dsidev, "DISPC"); |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3722 | } |
| 3723 | |
| 3724 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
| 3725 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3726 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
| 3727 | framedone_timeout_work.work); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3728 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
| 3729 | * 250ms which would conflict with this timeout work. What should be |
| 3730 | * done is first cancel the transfer on the HW, and then cancel the |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3731 | * possibly scheduled framedone work. However, cancelling the transfer |
| 3732 | * on the HW is buggy, and would probably require resetting the whole |
| 3733 | * DSI */ |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3734 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3735 | DSSERR("Framedone not received for 250ms!\n"); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3736 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3737 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3738 | } |
| 3739 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3740 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3741 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3742 | struct omap_dss_device *dssdev = (struct omap_dss_device *) data; |
| 3743 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3744 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 3745 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3746 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
| 3747 | * turns itself off. However, DSI still has the pixels in its buffers, |
| 3748 | * and is sending the data. |
| 3749 | */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3750 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3751 | __cancel_delayed_work(&dsi->framedone_timeout_work); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3752 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3753 | dsi_handle_framedone(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3754 | |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 3755 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
| 3756 | dispc_fake_vsync_irq(); |
| 3757 | #endif |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3758 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3759 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3760 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 3761 | u16 *x, u16 *y, u16 *w, u16 *h, |
| 3762 | bool enlarge_update_area) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3763 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3764 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3765 | u16 dw, dh; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3766 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3767 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3768 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3769 | if (*x > dw || *y > dh) |
| 3770 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3771 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3772 | if (*x + *w > dw) |
| 3773 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3774 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3775 | if (*y + *h > dh) |
| 3776 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3777 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3778 | if (*w == 1) |
| 3779 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3780 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3781 | if (*w == 0 || *h == 0) |
| 3782 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3783 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3784 | dsi_perf_mark_setup(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3785 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3786 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
Tomi Valkeinen | 26a8c25 | 2010-06-09 15:31:34 +0300 | [diff] [blame] | 3787 | dss_setup_partial_planes(dssdev, x, y, w, h, |
| 3788 | enlarge_update_area); |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3789 | dispc_set_lcd_size(dssdev->manager->id, *w, *h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3790 | } |
| 3791 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3792 | return 0; |
| 3793 | } |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3794 | EXPORT_SYMBOL(omap_dsi_prepare_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3795 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3796 | int omap_dsi_update(struct omap_dss_device *dssdev, |
| 3797 | int channel, |
| 3798 | u16 x, u16 y, u16 w, u16 h, |
| 3799 | void (*callback)(int, void *), void *data) |
| 3800 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3801 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3802 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3803 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3804 | dsi->update_channel = channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3805 | |
Tomi Valkeinen | a602771 | 2010-05-25 17:01:28 +0300 | [diff] [blame] | 3806 | /* OMAP DSS cannot send updates of odd widths. |
| 3807 | * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON |
| 3808 | * here to make sure we catch erroneous updates. Otherwise we'll only |
| 3809 | * see rather obscure HW error happening, as DSS halts. */ |
| 3810 | BUG_ON(x % 2 == 1); |
| 3811 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3812 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3813 | dsi->framedone_callback = callback; |
| 3814 | dsi->framedone_data = data; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3815 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 3816 | dsi->update_region.x = x; |
| 3817 | dsi->update_region.y = y; |
| 3818 | dsi->update_region.w = w; |
| 3819 | dsi->update_region.h = h; |
| 3820 | dsi->update_region.device = dssdev; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3821 | |
| 3822 | dsi_update_screen_dispc(dssdev, x, y, w, h); |
| 3823 | } else { |
Archit Taneja | e9c31af | 2010-07-14 14:11:50 +0200 | [diff] [blame] | 3824 | int r; |
| 3825 | |
| 3826 | r = dsi_update_screen_l4(dssdev, x, y, w, h); |
| 3827 | if (r) |
| 3828 | return r; |
| 3829 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3830 | dsi_perf_show(dsidev, "L4"); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3831 | callback(0, data); |
| 3832 | } |
| 3833 | |
| 3834 | return 0; |
| 3835 | } |
| 3836 | EXPORT_SYMBOL(omap_dsi_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3837 | |
| 3838 | /* Display funcs */ |
| 3839 | |
| 3840 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) |
| 3841 | { |
| 3842 | int r; |
| 3843 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3844 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3845 | DISPC_IRQ_FRAMEDONE); |
| 3846 | if (r) { |
| 3847 | DSSERR("can't get FRAMEDONE irq\n"); |
| 3848 | return r; |
| 3849 | } |
| 3850 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3851 | dispc_set_lcd_display_type(dssdev->manager->id, |
| 3852 | OMAP_DSS_LCD_DISPLAY_TFT); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3853 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3854 | dispc_set_parallel_interface_mode(dssdev->manager->id, |
| 3855 | OMAP_DSS_PARALLELMODE_DSI); |
| 3856 | dispc_enable_fifohandcheck(dssdev->manager->id, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3857 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3858 | dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3859 | |
| 3860 | { |
| 3861 | struct omap_video_timings timings = { |
| 3862 | .hsw = 1, |
| 3863 | .hfp = 1, |
| 3864 | .hbp = 1, |
| 3865 | .vsw = 1, |
| 3866 | .vfp = 0, |
| 3867 | .vbp = 0, |
| 3868 | }; |
| 3869 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 3870 | dispc_set_lcd_timings(dssdev->manager->id, &timings); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3871 | } |
| 3872 | |
| 3873 | return 0; |
| 3874 | } |
| 3875 | |
| 3876 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) |
| 3877 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3878 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3879 | DISPC_IRQ_FRAMEDONE); |
| 3880 | } |
| 3881 | |
| 3882 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) |
| 3883 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3884 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3885 | struct dsi_clock_info cinfo; |
| 3886 | int r; |
| 3887 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 3888 | /* we always use DSS_CLK_SYSCK as input clock */ |
| 3889 | cinfo.use_sys_clk = true; |
Tomi Valkeinen | c6940a3 | 2011-02-22 13:36:10 +0200 | [diff] [blame] | 3890 | cinfo.regn = dssdev->clocks.dsi.regn; |
| 3891 | cinfo.regm = dssdev->clocks.dsi.regm; |
| 3892 | cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; |
| 3893 | cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 3894 | r = dsi_calc_clock_rates(dssdev, &cinfo); |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 3895 | if (r) { |
| 3896 | DSSERR("Failed to calc dsi clocks\n"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3897 | return r; |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 3898 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3899 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3900 | r = dsi_pll_set_clock_div(dsidev, &cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3901 | if (r) { |
| 3902 | DSSERR("Failed to set dsi clocks\n"); |
| 3903 | return r; |
| 3904 | } |
| 3905 | |
| 3906 | return 0; |
| 3907 | } |
| 3908 | |
| 3909 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) |
| 3910 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3911 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3912 | struct dispc_clock_info dispc_cinfo; |
| 3913 | int r; |
| 3914 | unsigned long long fck; |
| 3915 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3916 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3917 | |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 3918 | dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div; |
| 3919 | dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3920 | |
| 3921 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); |
| 3922 | if (r) { |
| 3923 | DSSERR("Failed to calc dispc clocks\n"); |
| 3924 | return r; |
| 3925 | } |
| 3926 | |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 3927 | r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3928 | if (r) { |
| 3929 | DSSERR("Failed to set dispc clocks\n"); |
| 3930 | return r; |
| 3931 | } |
| 3932 | |
| 3933 | return 0; |
| 3934 | } |
| 3935 | |
| 3936 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) |
| 3937 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3938 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3939 | int r; |
| 3940 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3941 | r = dsi_pll_init(dsidev, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3942 | if (r) |
| 3943 | goto err0; |
| 3944 | |
| 3945 | r = dsi_configure_dsi_clocks(dssdev); |
| 3946 | if (r) |
| 3947 | goto err1; |
| 3948 | |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 3949 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
| 3950 | dss_select_dsi_clk_source(dssdev->clocks.dsi.dsi_fclk_src); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 3951 | dss_select_lcd_clk_source(dssdev->manager->id, |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 3952 | dssdev->clocks.dispc.channel.lcd_clk_src); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3953 | |
| 3954 | DSSDBG("PLL OK\n"); |
| 3955 | |
| 3956 | r = dsi_configure_dispc_clocks(dssdev); |
| 3957 | if (r) |
| 3958 | goto err2; |
| 3959 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 3960 | r = dsi_cio_init(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3961 | if (r) |
| 3962 | goto err2; |
| 3963 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3964 | _dsi_print_reset_status(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3965 | |
| 3966 | dsi_proto_timings(dssdev); |
| 3967 | dsi_set_lp_clk_divisor(dssdev); |
| 3968 | |
| 3969 | if (1) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3970 | _dsi_print_reset_status(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3971 | |
| 3972 | r = dsi_proto_config(dssdev); |
| 3973 | if (r) |
| 3974 | goto err3; |
| 3975 | |
| 3976 | /* enable interface */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3977 | dsi_vc_enable(dsidev, 0, 1); |
| 3978 | dsi_vc_enable(dsidev, 1, 1); |
| 3979 | dsi_vc_enable(dsidev, 2, 1); |
| 3980 | dsi_vc_enable(dsidev, 3, 1); |
| 3981 | dsi_if_enable(dsidev, 1); |
| 3982 | dsi_force_tx_stop_mode_io(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3983 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3984 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3985 | err3: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3986 | dsi_cio_uninit(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3987 | err2: |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 3988 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
| 3989 | dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3990 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3991 | dsi_pll_uninit(dsidev, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3992 | err0: |
| 3993 | return r; |
| 3994 | } |
| 3995 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 3996 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 3997 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3998 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3999 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4000 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4001 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4002 | if (enter_ulps && !dsi->ulps_enabled) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4003 | dsi_enter_ulps(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 4004 | |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 4005 | /* disable interface */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4006 | dsi_if_enable(dsidev, 0); |
| 4007 | dsi_vc_enable(dsidev, 0, 0); |
| 4008 | dsi_vc_enable(dsidev, 1, 0); |
| 4009 | dsi_vc_enable(dsidev, 2, 0); |
| 4010 | dsi_vc_enable(dsidev, 3, 0); |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 4011 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 4012 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
| 4013 | dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4014 | dsi_cio_uninit(dsidev); |
| 4015 | dsi_pll_uninit(dsidev, disconnect_lanes); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4016 | } |
| 4017 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4018 | static int dsi_core_init(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4019 | { |
| 4020 | /* Autoidle */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4021 | REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 1, 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4022 | |
| 4023 | /* ENWAKEUP */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4024 | REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 1, 2, 2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4025 | |
| 4026 | /* SIDLEMODE smart-idle */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4027 | REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 2, 4, 3); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4028 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4029 | _dsi_initialize_irq(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4030 | |
| 4031 | return 0; |
| 4032 | } |
| 4033 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4034 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4035 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4036 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4037 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4038 | int r = 0; |
| 4039 | |
| 4040 | DSSDBG("dsi_display_enable\n"); |
| 4041 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4042 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4043 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4044 | mutex_lock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4045 | |
| 4046 | r = omap_dss_start_device(dssdev); |
| 4047 | if (r) { |
| 4048 | DSSERR("failed to start device\n"); |
| 4049 | goto err0; |
| 4050 | } |
| 4051 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4052 | enable_clocks(1); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4053 | dsi_enable_pll_clock(dsidev, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4054 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4055 | r = _dsi_reset(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4056 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4057 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4058 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4059 | dsi_core_init(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4060 | |
| 4061 | r = dsi_display_init_dispc(dssdev); |
| 4062 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4063 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4064 | |
| 4065 | r = dsi_display_init_dsi(dssdev); |
| 4066 | if (r) |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4067 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4068 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4069 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4070 | |
| 4071 | return 0; |
| 4072 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4073 | err2: |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4074 | dsi_display_uninit_dispc(dssdev); |
| 4075 | err1: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4076 | enable_clocks(0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4077 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4078 | omap_dss_stop_device(dssdev); |
| 4079 | err0: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4080 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4081 | DSSDBG("dsi_display_enable FAILED\n"); |
| 4082 | return r; |
| 4083 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4084 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4085 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 4086 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 4087 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4088 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4089 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4090 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4091 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4092 | DSSDBG("dsi_display_disable\n"); |
| 4093 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4094 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4095 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4096 | mutex_lock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4097 | |
| 4098 | dsi_display_uninit_dispc(dssdev); |
| 4099 | |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 4100 | dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4101 | |
| 4102 | enable_clocks(0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4103 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4104 | |
| 4105 | omap_dss_stop_device(dssdev); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4106 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4107 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4108 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4109 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4110 | |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 4111 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4112 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4113 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4114 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4115 | |
| 4116 | dsi->te_enabled = enable; |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 4117 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4118 | } |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 4119 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4120 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4121 | void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, |
| 4122 | u32 fifo_size, enum omap_burst_size *burst_size, |
| 4123 | u32 *fifo_low, u32 *fifo_high) |
| 4124 | { |
| 4125 | unsigned burst_size_bytes; |
| 4126 | |
| 4127 | *burst_size = OMAP_DSS_BURST_16x32; |
| 4128 | burst_size_bytes = 16 * 32 / 8; |
| 4129 | |
| 4130 | *fifo_high = fifo_size - burst_size_bytes; |
Tomi Valkeinen | 36194b4 | 2010-05-18 13:35:37 +0300 | [diff] [blame] | 4131 | *fifo_low = fifo_size - burst_size_bytes * 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4132 | } |
| 4133 | |
| 4134 | int dsi_init_display(struct omap_dss_device *dssdev) |
| 4135 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4136 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4137 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4138 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4139 | DSSDBG("DSI init\n"); |
| 4140 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4141 | /* XXX these should be figured out dynamically */ |
| 4142 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | |
| 4143 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; |
| 4144 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4145 | if (dsi->vdds_dsi_reg == NULL) { |
Tomi Valkeinen | 5f42f2c | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 4146 | struct regulator *vdds_dsi; |
| 4147 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4148 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
Tomi Valkeinen | 5f42f2c | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 4149 | |
| 4150 | if (IS_ERR(vdds_dsi)) { |
| 4151 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 4152 | return PTR_ERR(vdds_dsi); |
| 4153 | } |
| 4154 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4155 | dsi->vdds_dsi_reg = vdds_dsi; |
Tomi Valkeinen | 5f42f2c | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 4156 | } |
| 4157 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4158 | return 0; |
| 4159 | } |
| 4160 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4161 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
| 4162 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4163 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4164 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4165 | int i; |
| 4166 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4167 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
| 4168 | if (!dsi->vc[i].dssdev) { |
| 4169 | dsi->vc[i].dssdev = dssdev; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4170 | *channel = i; |
| 4171 | return 0; |
| 4172 | } |
| 4173 | } |
| 4174 | |
| 4175 | DSSERR("cannot get VC for display %s", dssdev->name); |
| 4176 | return -ENOSPC; |
| 4177 | } |
| 4178 | EXPORT_SYMBOL(omap_dsi_request_vc); |
| 4179 | |
| 4180 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) |
| 4181 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4182 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4183 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4184 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4185 | if (vc_id < 0 || vc_id > 3) { |
| 4186 | DSSERR("VC ID out of range\n"); |
| 4187 | return -EINVAL; |
| 4188 | } |
| 4189 | |
| 4190 | if (channel < 0 || channel > 3) { |
| 4191 | DSSERR("Virtual Channel out of range\n"); |
| 4192 | return -EINVAL; |
| 4193 | } |
| 4194 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4195 | if (dsi->vc[channel].dssdev != dssdev) { |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4196 | DSSERR("Virtual Channel not allocated to display %s\n", |
| 4197 | dssdev->name); |
| 4198 | return -EINVAL; |
| 4199 | } |
| 4200 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4201 | dsi->vc[channel].vc_id = vc_id; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4202 | |
| 4203 | return 0; |
| 4204 | } |
| 4205 | EXPORT_SYMBOL(omap_dsi_set_vc_id); |
| 4206 | |
| 4207 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) |
| 4208 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4209 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4210 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4211 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4212 | if ((channel >= 0 && channel <= 3) && |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4213 | dsi->vc[channel].dssdev == dssdev) { |
| 4214 | dsi->vc[channel].dssdev = NULL; |
| 4215 | dsi->vc[channel].vc_id = 0; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4216 | } |
| 4217 | } |
| 4218 | EXPORT_SYMBOL(omap_dsi_release_vc); |
| 4219 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4220 | void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4221 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4222 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 4223 | DSSERR("%s (%s) not active\n", |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 4224 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 4225 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4226 | } |
| 4227 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4228 | void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4229 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4230 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 4231 | DSSERR("%s (%s) not active\n", |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 4232 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 4233 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4234 | } |
| 4235 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4236 | static void dsi_calc_clock_param_ranges(struct platform_device *dsidev) |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 4237 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4238 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4239 | |
| 4240 | dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); |
| 4241 | dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); |
| 4242 | dsi->regm_dispc_max = |
| 4243 | dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); |
| 4244 | dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); |
| 4245 | dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); |
| 4246 | dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); |
| 4247 | dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 4248 | } |
| 4249 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4250 | static int dsi_init(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4251 | { |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 4252 | struct omap_display_platform_data *dss_plat_data; |
| 4253 | struct omap_dss_board_info *board_info; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4254 | u32 rev; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4255 | int r, i, dsi_module = dsi_get_dsidev_id(dsidev); |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 4256 | struct resource *dsi_mem; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4257 | struct dsi_data *dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4258 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4259 | dsi = kzalloc(sizeof(*dsi), GFP_KERNEL); |
| 4260 | if (!dsi) { |
| 4261 | r = -ENOMEM; |
| 4262 | goto err0; |
| 4263 | } |
| 4264 | |
| 4265 | dsi->pdev = dsidev; |
| 4266 | dsi_pdev_map[dsi_module] = dsidev; |
| 4267 | dev_set_drvdata(&dsidev->dev, dsi); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4268 | |
| 4269 | dss_plat_data = dsidev->dev.platform_data; |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 4270 | board_info = dss_plat_data->board_data; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4271 | dsi->dsi_mux_pads = board_info->dsi_mux_pads; |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 4272 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4273 | spin_lock_init(&dsi->irq_lock); |
| 4274 | spin_lock_init(&dsi->errors_lock); |
| 4275 | dsi->errors = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4276 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 4277 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4278 | spin_lock_init(&dsi->irq_stats_lock); |
| 4279 | dsi->irq_stats.last_reset = jiffies; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 4280 | #endif |
| 4281 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4282 | mutex_init(&dsi->lock); |
| 4283 | sema_init(&dsi->bus_lock, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4284 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4285 | dsi->workqueue = create_singlethread_workqueue(dev_name(&dsidev->dev)); |
| 4286 | if (dsi->workqueue == NULL) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4287 | r = -ENOMEM; |
| 4288 | goto err1; |
| 4289 | } |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4290 | |
| 4291 | INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work, |
| 4292 | dsi_framedone_timeout_work_callback); |
| 4293 | |
| 4294 | #ifdef DSI_CATCH_MISSING_TE |
| 4295 | init_timer(&dsi->te_timer); |
| 4296 | dsi->te_timer.function = dsi_te_timeout; |
| 4297 | dsi->te_timer.data = 0; |
| 4298 | #endif |
| 4299 | dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0); |
| 4300 | if (!dsi_mem) { |
| 4301 | DSSERR("can't get IORESOURCE_MEM DSI\n"); |
| 4302 | r = -EINVAL; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4303 | goto err2; |
| 4304 | } |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4305 | dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem)); |
| 4306 | if (!dsi->base) { |
| 4307 | DSSERR("can't ioremap DSI\n"); |
| 4308 | r = -ENOMEM; |
| 4309 | goto err2; |
| 4310 | } |
| 4311 | dsi->irq = platform_get_irq(dsi->pdev, 0); |
| 4312 | if (dsi->irq < 0) { |
| 4313 | DSSERR("platform_get_irq failed\n"); |
| 4314 | r = -ENODEV; |
| 4315 | goto err3; |
| 4316 | } |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4317 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4318 | r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED, |
| 4319 | dev_name(&dsidev->dev), dsi->pdev); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4320 | if (r < 0) { |
| 4321 | DSSERR("request_irq failed\n"); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4322 | goto err3; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4323 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4324 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4325 | /* DSI VCs initialization */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4326 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
| 4327 | dsi->vc[i].mode = DSI_VC_MODE_L4; |
| 4328 | dsi->vc[i].dssdev = NULL; |
| 4329 | dsi->vc[i].vc_id = 0; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4330 | } |
| 4331 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4332 | dsi_calc_clock_param_ranges(dsidev); |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 4333 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4334 | enable_clocks(1); |
| 4335 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4336 | rev = dsi_read_reg(dsidev, DSI_REVISION); |
| 4337 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4338 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 4339 | |
| 4340 | enable_clocks(0); |
| 4341 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4342 | return 0; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4343 | err3: |
| 4344 | iounmap(dsi->base); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4345 | err2: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4346 | destroy_workqueue(dsi->workqueue); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4347 | err1: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4348 | kfree(dsi); |
| 4349 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4350 | return r; |
| 4351 | } |
| 4352 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4353 | static void dsi_exit(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4354 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4355 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4356 | |
| 4357 | if (dsi->vdds_dsi_reg != NULL) { |
| 4358 | if (dsi->vdds_dsi_enabled) { |
| 4359 | regulator_disable(dsi->vdds_dsi_reg); |
| 4360 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 88257b2 | 2010-12-20 16:26:22 +0200 | [diff] [blame] | 4361 | } |
| 4362 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4363 | regulator_put(dsi->vdds_dsi_reg); |
| 4364 | dsi->vdds_dsi_reg = NULL; |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4365 | } |
| 4366 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4367 | free_irq(dsi->irq, dsi->pdev); |
| 4368 | iounmap(dsi->base); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4369 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4370 | destroy_workqueue(dsi->workqueue); |
| 4371 | kfree(dsi); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4372 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4373 | DSSDBG("omap_dsi_exit\n"); |
| 4374 | } |
| 4375 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4376 | /* DSI1 HW IP initialisation */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4377 | static int omap_dsi1hw_probe(struct platform_device *dsidev) |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4378 | { |
| 4379 | int r; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4380 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4381 | r = dsi_init(dsidev); |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4382 | if (r) { |
| 4383 | DSSERR("Failed to initialize DSI\n"); |
| 4384 | goto err_dsi; |
| 4385 | } |
| 4386 | err_dsi: |
| 4387 | return r; |
| 4388 | } |
| 4389 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4390 | static int omap_dsi1hw_remove(struct platform_device *dsidev) |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4391 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4392 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4393 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4394 | dsi_exit(dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame^] | 4395 | WARN_ON(dsi->scp_clk_refcount > 0); |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4396 | return 0; |
| 4397 | } |
| 4398 | |
| 4399 | static struct platform_driver omap_dsi1hw_driver = { |
| 4400 | .probe = omap_dsi1hw_probe, |
| 4401 | .remove = omap_dsi1hw_remove, |
| 4402 | .driver = { |
| 4403 | .name = "omapdss_dsi1", |
| 4404 | .owner = THIS_MODULE, |
| 4405 | }, |
| 4406 | }; |
| 4407 | |
| 4408 | int dsi_init_platform_driver(void) |
| 4409 | { |
| 4410 | return platform_driver_register(&omap_dsi1hw_driver); |
| 4411 | } |
| 4412 | |
| 4413 | void dsi_uninit_platform_driver(void) |
| 4414 | { |
| 4415 | return platform_driver_unregister(&omap_dsi1hw_driver); |
| 4416 | } |