blob: 889a9b1337be92c2ee16e245d3ef068ff769e087 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
Tvrtko Ursulin93b81f52015-02-10 17:16:05 +000034#include <uapi/drm/drm_fourcc.h>
Chris Wilsone9b73c62012-12-03 21:03:14 +000035
Keith Packard0839ccb2008-10-30 19:38:48 -070036#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070037#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010038#include <linux/i2c-algo-bit.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020039#include <linux/backlight.h>
Chris Wilson4ff4b442017-06-16 15:05:16 +010040#include <linux/hash.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070041#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020042#include <linux/kref.h>
Tvrtko Ursulinb46a33e2017-11-21 18:18:45 +000043#include <linux/perf_event.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010044#include <linux/pm_qos.h>
Chris Wilsond07f0e52016-10-28 13:58:44 +010045#include <linux/reservation.h>
Chris Wilsone73bdd22016-04-13 17:35:01 +010046#include <linux/shmem_fs.h>
47
48#include <drm/drmP.h>
49#include <drm/intel-gtt.h>
50#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
51#include <drm/drm_gem.h>
Daniel Vetter3b96a0b2016-06-21 10:54:22 +020052#include <drm/drm_auth.h>
Gabriel Krisman Bertazif9a87bd2017-01-09 19:56:49 -020053#include <drm/drm_cache.h>
Chris Wilsone73bdd22016-04-13 17:35:01 +010054
55#include "i915_params.h"
56#include "i915_reg.h"
Chris Wilson40b326e2017-01-05 15:30:22 +000057#include "i915_utils.h"
Chris Wilsone73bdd22016-04-13 17:35:01 +010058
Michal Wajdeczko16586fc2017-05-09 09:20:21 +000059#include "intel_uncore.h"
Chris Wilsone73bdd22016-04-13 17:35:01 +010060#include "intel_bios.h"
Ander Conselvan de Oliveiraac7f11c2016-03-08 17:46:19 +020061#include "intel_dpll_mgr.h"
Arkadiusz Hiler8c4f24f2016-11-25 18:59:33 +010062#include "intel_uc.h"
Chris Wilsone73bdd22016-04-13 17:35:01 +010063#include "intel_lrc.h"
64#include "intel_ringbuffer.h"
Michal Wajdeczko09a28bd2017-12-21 21:57:30 +000065#include "intel_display.h"
Chris Wilsone73bdd22016-04-13 17:35:01 +010066
Chris Wilsond501b1d2016-04-13 17:35:02 +010067#include "i915_gem.h"
Chris Wilson60958682016-12-31 11:20:11 +000068#include "i915_gem_context.h"
Joonas Lahtinenb42fe9c2016-11-11 12:43:54 +020069#include "i915_gem_fence_reg.h"
70#include "i915_gem_object.h"
Chris Wilsone73bdd22016-04-13 17:35:01 +010071#include "i915_gem_gtt.h"
Chris Wilson05235c52016-07-20 09:21:08 +010072#include "i915_gem_request.h"
Chris Wilson73cb9702016-10-28 13:58:46 +010073#include "i915_gem_timeline.h"
Jesse Barnes585fb112008-07-29 11:54:06 -070074
Joonas Lahtinenb42fe9c2016-11-11 12:43:54 +020075#include "i915_vma.h"
76
Zhi Wang0ad35fe2016-06-16 08:07:00 -040077#include "intel_gvt.h"
78
Linus Torvalds1da177e2005-04-16 15:20:36 -070079/* General customization:
80 */
81
Linus Torvalds1da177e2005-04-16 15:20:36 -070082#define DRIVER_NAME "i915"
83#define DRIVER_DESC "Intel Graphics"
Rodrigo Viviee5b5bf2017-12-14 12:10:02 -080084#define DRIVER_DATE "20171214"
85#define DRIVER_TIMESTAMP 1513282202
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
Rob Clarke2c719b2014-12-15 13:56:32 -050087/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
88 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
89 * which may not necessarily be a user visible problem. This will either
90 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
91 * enable distros and users to tailor their preferred amount of i915 abrt
92 * spam.
93 */
94#define I915_STATE_WARN(condition, format...) ({ \
95 int __ret_warn_on = !!(condition); \
Joonas Lahtinen32753cb2015-12-18 14:27:26 +020096 if (unlikely(__ret_warn_on)) \
Michal Wajdeczko4f044a82017-09-19 19:38:44 +000097 if (!WARN(i915_modparams.verbose_state_checks, format)) \
Rob Clarke2c719b2014-12-15 13:56:32 -050098 DRM_ERROR(format); \
Rob Clarke2c719b2014-12-15 13:56:32 -050099 unlikely(__ret_warn_on); \
100})
101
Joonas Lahtinen152b2262015-12-18 14:27:27 +0200102#define I915_STATE_WARN_ON(x) \
103 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
Mika Kuoppalac883ef12014-10-28 17:32:30 +0200104
Imre Deak4fec15d2016-03-16 13:39:08 +0200105bool __i915_inject_load_failure(const char *func, int line);
106#define i915_inject_load_failure() \
107 __i915_inject_load_failure(__func__, __LINE__)
108
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530109typedef struct {
110 uint32_t val;
111} uint_fixed_16_16_t;
112
113#define FP_16_16_MAX ({ \
114 uint_fixed_16_16_t fp; \
115 fp.val = UINT_MAX; \
116 fp; \
117})
118
Kumar, Maheshd555cb52017-05-17 17:28:29 +0530119static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
120{
121 if (val.val == 0)
122 return true;
123 return false;
124}
125
Kumar, Mahesheac2cb82017-07-05 20:01:46 +0530126static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530127{
128 uint_fixed_16_16_t fp;
129
Kumar, Mahesh0b4d7cb2017-08-17 19:15:22 +0530130 WARN_ON(val > U16_MAX);
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530131
132 fp.val = val << 16;
133 return fp;
134}
135
Kumar, Mahesheac2cb82017-07-05 20:01:46 +0530136static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530137{
138 return DIV_ROUND_UP(fp.val, 1 << 16);
139}
140
Kumar, Mahesheac2cb82017-07-05 20:01:46 +0530141static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530142{
143 return fp.val >> 16;
144}
145
Kumar, Mahesheac2cb82017-07-05 20:01:46 +0530146static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530147 uint_fixed_16_16_t min2)
148{
149 uint_fixed_16_16_t min;
150
151 min.val = min(min1.val, min2.val);
152 return min;
153}
154
Kumar, Mahesheac2cb82017-07-05 20:01:46 +0530155static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530156 uint_fixed_16_16_t max2)
157{
158 uint_fixed_16_16_t max;
159
160 max.val = max(max1.val, max2.val);
161 return max;
162}
163
Kumar, Mahesh07ab9762017-07-05 20:01:44 +0530164static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
165{
166 uint_fixed_16_16_t fp;
Kumar, Mahesh0b4d7cb2017-08-17 19:15:22 +0530167 WARN_ON(val > U32_MAX);
168 fp.val = (uint32_t) val;
Kumar, Mahesh07ab9762017-07-05 20:01:44 +0530169 return fp;
170}
171
Kumar, Mahesha9d055d2017-05-17 17:28:21 +0530172static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
173 uint_fixed_16_16_t d)
174{
175 return DIV_ROUND_UP(val.val, d.val);
176}
177
178static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
179 uint_fixed_16_16_t mul)
180{
181 uint64_t intermediate_val;
Kumar, Mahesha9d055d2017-05-17 17:28:21 +0530182
183 intermediate_val = (uint64_t) val * mul.val;
184 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
Kumar, Mahesh0b4d7cb2017-08-17 19:15:22 +0530185 WARN_ON(intermediate_val > U32_MAX);
186 return (uint32_t) intermediate_val;
Kumar, Mahesha9d055d2017-05-17 17:28:21 +0530187}
188
189static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
190 uint_fixed_16_16_t mul)
191{
192 uint64_t intermediate_val;
Kumar, Mahesha9d055d2017-05-17 17:28:21 +0530193
194 intermediate_val = (uint64_t) val.val * mul.val;
195 intermediate_val = intermediate_val >> 16;
Kumar, Mahesh07ab9762017-07-05 20:01:44 +0530196 return clamp_u64_to_fixed16(intermediate_val);
Kumar, Mahesha9d055d2017-05-17 17:28:21 +0530197}
198
Kumar, Mahesheac2cb82017-07-05 20:01:46 +0530199static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530200{
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530201 uint64_t interm_val;
202
203 interm_val = (uint64_t)val << 16;
204 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
Kumar, Mahesh07ab9762017-07-05 20:01:44 +0530205 return clamp_u64_to_fixed16(interm_val);
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530206}
207
Kumar, Mahesha9d055d2017-05-17 17:28:21 +0530208static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
209 uint_fixed_16_16_t d)
210{
211 uint64_t interm_val;
212
213 interm_val = (uint64_t)val << 16;
214 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
Kumar, Mahesh0b4d7cb2017-08-17 19:15:22 +0530215 WARN_ON(interm_val > U32_MAX);
216 return (uint32_t) interm_val;
Kumar, Mahesha9d055d2017-05-17 17:28:21 +0530217}
218
Kumar, Mahesheac2cb82017-07-05 20:01:46 +0530219static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530220 uint_fixed_16_16_t mul)
221{
222 uint64_t intermediate_val;
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530223
224 intermediate_val = (uint64_t) val * mul.val;
Kumar, Mahesh07ab9762017-07-05 20:01:44 +0530225 return clamp_u64_to_fixed16(intermediate_val);
Mahesh Kumarb95320b2016-12-01 21:19:37 +0530226}
227
Kumar, Mahesh6ea593c2017-07-05 20:01:47 +0530228static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
229 uint_fixed_16_16_t add2)
230{
231 uint64_t interm_sum;
232
233 interm_sum = (uint64_t) add1.val + add2.val;
234 return clamp_u64_to_fixed16(interm_sum);
235}
236
237static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
238 uint32_t add2)
239{
240 uint64_t interm_sum;
241 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
242
243 interm_sum = (uint64_t) add1.val + interm_add2.val;
244 return clamp_u64_to_fixed16(interm_sum);
245}
246
Egbert Eich1d843f92013-02-25 12:06:49 -0500247enum hpd_pin {
248 HPD_NONE = 0,
Egbert Eich1d843f92013-02-25 12:06:49 -0500249 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
250 HPD_CRT,
251 HPD_SDVO_B,
252 HPD_SDVO_C,
Imre Deakcc24fcd2015-07-21 15:32:45 -0700253 HPD_PORT_A,
Egbert Eich1d843f92013-02-25 12:06:49 -0500254 HPD_PORT_B,
255 HPD_PORT_C,
256 HPD_PORT_D,
Xiong Zhang26951ca2015-08-17 15:55:50 +0800257 HPD_PORT_E,
Egbert Eich1d843f92013-02-25 12:06:49 -0500258 HPD_NUM_PINS
259};
260
Jani Nikulac91711f2015-05-28 15:43:48 +0300261#define for_each_hpd_pin(__pin) \
262 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
263
Lyude317eaa92017-02-03 21:18:25 -0500264#define HPD_STORM_DEFAULT_THRESHOLD 5
265
Jani Nikula5fcece82015-05-27 15:03:42 +0300266struct i915_hotplug {
267 struct work_struct hotplug_work;
268
269 struct {
270 unsigned long last_jiffies;
271 int count;
272 enum {
273 HPD_ENABLED = 0,
274 HPD_DISABLED = 1,
275 HPD_MARK_DISABLED = 2
276 } state;
277 } stats[HPD_NUM_PINS];
278 u32 event_bits;
279 struct delayed_work reenable_work;
280
281 struct intel_digital_port *irq_port[I915_MAX_PORTS];
282 u32 long_port_mask;
283 u32 short_port_mask;
284 struct work_struct dig_port_work;
285
Lyude19625e82016-06-21 17:03:44 -0400286 struct work_struct poll_init_work;
287 bool poll_enabled;
288
Lyude317eaa92017-02-03 21:18:25 -0500289 unsigned int hpd_storm_threshold;
290
Jani Nikula5fcece82015-05-27 15:03:42 +0300291 /*
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
297 */
298 struct workqueue_struct *dp_wq;
299};
300
Chris Wilson2a2d5482012-12-03 11:49:06 +0000301#define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700307
Daniel Vettere7b903d2013-06-05 13:34:14 +0200308struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100309struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100310struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200311
Chris Wilsona6f766f2015-04-27 13:41:20 +0100312struct drm_i915_file_private {
313 struct drm_i915_private *dev_priv;
314 struct drm_file *file;
315
316 struct {
317 spinlock_t lock;
318 struct list_head request_list;
Chris Wilsond0bc54f2015-05-21 21:01:48 +0100319/* 20ms is a fairly arbitrary limit (greater than the average frame time)
320 * chosen to prevent the CPU getting more than a frame ahead of the GPU
321 * (when using lax throttling for the frontbuffer). We also use it to
322 * offer free GPU waitboosts for severely congested workloads.
323 */
324#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
Chris Wilsona6f766f2015-04-27 13:41:20 +0100325 } mm;
326 struct idr context_idr;
327
Chris Wilson2e1b8732015-04-27 13:41:22 +0100328 struct intel_rps_client {
Chris Wilson7b92c1b2017-06-28 13:35:48 +0100329 atomic_t boosts;
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +0100330 } rps_client;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100331
Chris Wilsonc80ff162016-07-27 09:07:27 +0100332 unsigned int bsd_engine;
Mika Kuoppalab083a082016-11-18 15:10:47 +0200333
334/* Client can have a maximum of 3 contexts banned before
335 * it is denied of creating new contexts. As one context
336 * ban needs 4 consecutive hangs, and more if there is
337 * progress in between, this is a last resort stop gap measure
338 * to limit the badly behaving clients access to gpu.
339 */
340#define I915_MAX_CLIENT_CONTEXT_BANS 3
Chris Wilson77b25a92017-07-21 13:32:30 +0100341 atomic_t context_bans;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100342};
343
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344/* Interface history:
345 *
346 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100347 * 1.2: Add Power Management
348 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100349 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000350 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000351 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
352 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 */
354#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000355#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356#define DRIVER_PATCHLEVEL 0
357
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700358struct opregion_header;
359struct opregion_acpi;
360struct opregion_swsci;
361struct opregion_asle;
362
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100363struct intel_opregion {
Williams, Dan J115719f2015-10-12 21:12:57 +0000364 struct opregion_header *header;
365 struct opregion_acpi *acpi;
366 struct opregion_swsci *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300367 u32 swsci_gbda_sub_functions;
368 u32 swsci_sbcb_sub_functions;
Williams, Dan J115719f2015-10-12 21:12:57 +0000369 struct opregion_asle *asle;
Jani Nikula04ebaad2015-12-15 13:18:00 +0200370 void *rvda;
Jani Nikulaab3595b2017-08-17 14:52:09 +0300371 void *vbt_firmware;
Jani Nikula82730382015-12-14 12:50:52 +0200372 const void *vbt;
Jani Nikulaada8f952015-12-15 13:17:12 +0200373 u32 vbt_size;
Williams, Dan J115719f2015-10-12 21:12:57 +0000374 u32 *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200375 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100376};
Chris Wilson44834a62010-08-19 16:09:23 +0100377#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100378
Chris Wilson6ef3d422010-08-04 20:26:07 +0100379struct intel_overlay;
380struct intel_overlay_error_state;
381
yakui_zhao9b9d1722009-05-31 17:17:17 +0800382struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100383 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800384 u8 dvo_port;
385 u8 slave_addr;
386 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100387 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400388 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800389};
390
Jani Nikula7bd688c2013-11-08 16:48:56 +0200391struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200392struct intel_encoder;
Maarten Lankhorstccf010f2016-11-08 13:55:32 +0100393struct intel_atomic_state;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200394struct intel_crtc_state;
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000395struct intel_initial_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100396struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200397struct intel_limit;
398struct dpll;
Ville Syrjälä49cd97a2017-02-07 20:33:45 +0200399struct intel_cdclk_state;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100400
Jesse Barnese70236a2009-09-21 10:42:27 -0700401struct drm_i915_display_funcs {
Ville Syrjälä49cd97a2017-02-07 20:33:45 +0200402 void (*get_cdclk)(struct drm_i915_private *dev_priv,
403 struct intel_cdclk_state *cdclk_state);
Ville Syrjäläb0587e42017-01-26 21:52:01 +0200404 void (*set_cdclk)(struct drm_i915_private *dev_priv,
405 const struct intel_cdclk_state *cdclk_state);
Ville Syrjäläbdaf8432017-11-17 21:19:11 +0200406 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
407 enum i9xx_plane_id i9xx_plane);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +0100408 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
Matt Ropered4a6a72016-02-23 17:20:13 -0800409 int (*compute_intermediate_wm)(struct drm_device *dev,
410 struct intel_crtc *intel_crtc,
411 struct intel_crtc_state *newstate);
Maarten Lankhorstccf010f2016-11-08 13:55:32 +0100412 void (*initial_watermarks)(struct intel_atomic_state *state,
413 struct intel_crtc_state *cstate);
414 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
415 struct intel_crtc_state *cstate);
416 void (*optimize_watermarks)(struct intel_atomic_state *state,
417 struct intel_crtc_state *cstate);
Matt Roper98d39492016-05-12 07:06:03 -0700418 int (*compute_global_watermarks)(struct drm_atomic_state *state);
Ville Syrjälä432081b2016-10-31 22:37:03 +0200419 void (*update_wm)(struct intel_crtc *crtc);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +0200420 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100421 /* Returns the active state of the crtc, and if the crtc is active,
422 * fills out the pipe-config with the hw state. */
423 bool (*get_pipe_config)(struct intel_crtc *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200424 struct intel_crtc_state *);
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000425 void (*get_initial_plane_config)(struct intel_crtc *,
426 struct intel_initial_plane_config *);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +0200427 int (*crtc_compute_clock)(struct intel_crtc *crtc,
428 struct intel_crtc_state *crtc_state);
Maarten Lankhorst4a806552016-08-09 17:04:01 +0200429 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
430 struct drm_atomic_state *old_state);
431 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
432 struct drm_atomic_state *old_state);
Maarten Lankhorstb44d5c02017-09-04 12:48:33 +0200433 void (*update_crtcs)(struct drm_atomic_state *state);
Ville Syrjälä8ec47de2017-10-30 20:46:53 +0200434 void (*audio_codec_enable)(struct intel_encoder *encoder,
435 const struct intel_crtc_state *crtc_state,
436 const struct drm_connector_state *conn_state);
437 void (*audio_codec_disable)(struct intel_encoder *encoder,
438 const struct intel_crtc_state *old_crtc_state,
439 const struct drm_connector_state *old_conn_state);
Ander Conselvan de Oliveiradc4a1092017-03-02 14:58:54 +0200440 void (*fdi_link_train)(struct intel_crtc *crtc,
441 const struct intel_crtc_state *crtc_state);
Ville Syrjälä46f16e62016-10-31 22:37:22 +0200442 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +0100443 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
Jesse Barnese70236a2009-09-21 10:42:27 -0700444 /* clock updates for mode set */
445 /* cursor updates */
446 /* render clock increase/decrease */
447 /* display clock increase/decrease */
448 /* pll clock increase/decrease */
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +0000449
Maarten Lankhorstb95c5322016-03-30 17:16:34 +0200450 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
451 void (*load_luts)(struct drm_crtc_state *crtc_state);
Jesse Barnese70236a2009-09-21 10:42:27 -0700452};
453
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200454#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
455#define CSR_VERSION_MAJOR(version) ((version) >> 16)
456#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
457
Daniel Vettereb805622015-05-04 14:58:44 +0200458struct intel_csr {
Daniel Vetter8144ac52015-10-28 23:59:04 +0200459 struct work_struct work;
Daniel Vettereb805622015-05-04 14:58:44 +0200460 const char *fw_path;
Animesh Mannaa7f749f2015-08-03 21:55:32 +0530461 uint32_t *dmc_payload;
Daniel Vettereb805622015-05-04 14:58:44 +0200462 uint32_t dmc_fw_size;
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200463 uint32_t version;
Daniel Vettereb805622015-05-04 14:58:44 +0200464 uint32_t mmio_count;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200465 i915_reg_t mmioaddr[8];
Daniel Vettereb805622015-05-04 14:58:44 +0200466 uint32_t mmiodata[8];
Patrik Jakobsson832dba82016-02-18 17:21:11 +0200467 uint32_t dc_state;
Imre Deaka37baf32016-02-29 22:49:03 +0200468 uint32_t allowed_dc_mask;
Daniel Vettereb805622015-05-04 14:58:44 +0200469};
470
Joonas Lahtinen604db652016-10-05 13:50:16 +0300471#define DEV_INFO_FOR_EACH_FLAG(func) \
472 func(is_mobile); \
Ander Conselvan de Oliveira3e4274f2016-11-10 17:23:09 +0200473 func(is_lp); \
Jani Nikulac007fb42016-10-31 12:18:28 +0200474 func(is_alpha_support); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300475 /* Keep has_* in alphabetical order */ \
Joonas Lahtinendfc51482016-11-03 10:39:46 +0200476 func(has_64bit_reloc); \
Michel Thierry9e1d0e62016-12-05 17:57:03 -0800477 func(has_aliasing_ppgtt); \
Joonas Lahtinen604db652016-10-05 13:50:16 +0300478 func(has_csr); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300479 func(has_ddi); \
Joonas Lahtinen604db652016-10-05 13:50:16 +0300480 func(has_dp_mst); \
Michel Thierry142bc7d2017-06-20 10:57:46 +0100481 func(has_reset_engine); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300482 func(has_fbc); \
483 func(has_fpga_dbg); \
Michel Thierry9e1d0e62016-12-05 17:57:03 -0800484 func(has_full_ppgtt); \
485 func(has_full_48bit_ppgtt); \
Joonas Lahtinen604db652016-10-05 13:50:16 +0300486 func(has_gmch_display); \
487 func(has_guc); \
Michal Wajdeczkof8a58d62017-05-26 11:13:25 +0000488 func(has_guc_ct); \
Joonas Lahtinen604db652016-10-05 13:50:16 +0300489 func(has_hotplug); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300490 func(has_l3_dpf); \
Joonas Lahtinen604db652016-10-05 13:50:16 +0300491 func(has_llc); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300492 func(has_logical_ring_contexts); \
Chris Wilsone7af3112017-10-03 21:34:48 +0100493 func(has_logical_ring_preemption); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300494 func(has_overlay); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300495 func(has_pooled_eu); \
496 func(has_psr); \
497 func(has_rc6); \
498 func(has_rc6p); \
499 func(has_resource_streamer); \
500 func(has_runtime_pm); \
Joonas Lahtinen604db652016-10-05 13:50:16 +0300501 func(has_snoop); \
Chris Wilsonf4ce7662017-03-25 11:32:43 +0000502 func(unfenced_needs_alignment); \
Joonas Lahtinen566c56a2016-10-05 13:50:17 +0300503 func(cursor_needs_physical); \
504 func(hws_needs_physical); \
505 func(overlay_needs_physical); \
Mahesh Kumare57f1c022017-08-17 19:15:27 +0530506 func(supports_tv); \
507 func(has_ipc);
Daniel Vetterc96ea642012-08-08 22:01:51 +0200508
Imre Deak915490d2016-08-31 19:13:01 +0300509struct sseu_dev_info {
Imre Deakf08a0c92016-08-31 19:13:04 +0300510 u8 slice_mask;
Imre Deak57ec1712016-08-31 19:13:05 +0300511 u8 subslice_mask;
Imre Deak915490d2016-08-31 19:13:01 +0300512 u8 eu_total;
513 u8 eu_per_subslice;
Imre Deak43b67992016-08-31 19:13:02 +0300514 u8 min_eu_in_pool;
515 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
516 u8 subslice_7eu[3];
517 u8 has_slice_pg:1;
518 u8 has_subslice_pg:1;
519 u8 has_eu_pg:1;
Imre Deak915490d2016-08-31 19:13:01 +0300520};
521
Imre Deak57ec1712016-08-31 19:13:05 +0300522static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
523{
524 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
525}
526
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200527/* Keep in gen based order, and chronological order within a gen */
528enum intel_platform {
529 INTEL_PLATFORM_UNINITIALIZED = 0,
530 INTEL_I830,
531 INTEL_I845G,
532 INTEL_I85X,
533 INTEL_I865G,
534 INTEL_I915G,
535 INTEL_I915GM,
536 INTEL_I945G,
537 INTEL_I945GM,
538 INTEL_G33,
539 INTEL_PINEVIEW,
Jani Nikulac0f86832016-12-07 12:13:04 +0200540 INTEL_I965G,
541 INTEL_I965GM,
Jani Nikulaf69c11a2016-11-30 17:43:05 +0200542 INTEL_G45,
543 INTEL_GM45,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200544 INTEL_IRONLAKE,
545 INTEL_SANDYBRIDGE,
546 INTEL_IVYBRIDGE,
547 INTEL_VALLEYVIEW,
548 INTEL_HASWELL,
549 INTEL_BROADWELL,
550 INTEL_CHERRYVIEW,
551 INTEL_SKYLAKE,
552 INTEL_BROXTON,
553 INTEL_KABYLAKE,
554 INTEL_GEMINILAKE,
Rodrigo Vivi71851fa2017-06-08 08:49:58 -0700555 INTEL_COFFEELAKE,
Rodrigo Vivi413f3c12017-06-06 13:30:30 -0700556 INTEL_CANNONLAKE,
Jani Nikula91600952017-02-28 13:11:43 +0200557 INTEL_MAX_PLATFORMS
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200558};
559
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500560struct intel_device_info {
Chris Wilson87f1f462014-08-09 19:18:42 +0100561 u16 device_id;
Tvrtko Ursulin4d34b112017-09-20 10:27:00 +0100562 u16 gen_mask;
563
564 u8 gen;
565 u8 gt; /* GT number, 0 if undefined */
566 u8 num_rings;
567 u8 ring_mask; /* Rings supported by the HW */
568
569 enum intel_platform platform;
Tvrtko Ursulinae7617f2017-09-27 17:41:38 +0100570 u32 platform_mask;
Tvrtko Ursulin4d34b112017-09-20 10:27:00 +0100571
572 u32 display_mmio_offset;
573
Tvrtko Ursulinac208a82016-05-10 10:57:07 +0100574 u8 num_pipes;
Damien Lespiaud615a162014-03-03 17:31:48 +0000575 u8 num_sprites[I915_MAX_PIPES];
Nabendu Maiti1c74eea2016-11-29 11:23:14 +0530576 u8 num_scalers[I915_MAX_PIPES];
Tvrtko Ursulin4d34b112017-09-20 10:27:00 +0100577
Matthew Auld2a9654b2017-10-06 23:18:16 +0100578 unsigned int page_sizes; /* page sizes supported by the HW */
579
Joonas Lahtinen604db652016-10-05 13:50:16 +0300580#define DEFINE_FLAG(name) u8 name:1
581 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
582#undef DEFINE_FLAG
Deepak M6f3fff62016-09-15 15:01:10 +0530583 u16 ddb_size; /* in blocks */
Tvrtko Ursulin4d34b112017-09-20 10:27:00 +0100584
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200585 /* Register offsets for the various display pipes and transcoders */
586 int pipe_offsets[I915_MAX_TRANSCODERS];
587 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200588 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300589 int cursor_offsets[I915_MAX_PIPES];
Jeff McGee38732182015-02-13 10:27:54 -0600590
591 /* Slice/subslice/EU info */
Imre Deak43b67992016-08-31 19:13:02 +0300592 struct sseu_dev_info sseu;
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000593
Lionel Landwerlinf577a032017-11-13 23:34:53 +0000594 u32 cs_timestamp_frequency_khz;
Lionel Landwerlindab91782017-11-10 19:08:44 +0000595
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000596 struct color_luts {
597 u16 degamma_lut_size;
598 u16 gamma_lut_size;
599 } color;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500600};
601
Chris Wilson2bd160a2016-08-15 10:48:45 +0100602struct intel_display_error_state;
603
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000604struct i915_gpu_state {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100605 struct kref ref;
606 struct timeval time;
Chris Wilsonde867c22016-10-25 13:16:02 +0100607 struct timeval boottime;
608 struct timeval uptime;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100609
Chris Wilson9f267eb2016-10-12 10:05:19 +0100610 struct drm_i915_private *i915;
611
Chris Wilson2bd160a2016-08-15 10:48:45 +0100612 char error_msg[128];
613 bool simulated;
Chris Wilsonf73b5672017-03-02 15:03:56 +0000614 bool awake;
Chris Wilsone5aac872017-03-02 15:15:44 +0000615 bool wakelock;
616 bool suspended;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100617 int iommu;
618 u32 reset_count;
619 u32 suspend_count;
620 struct intel_device_info device_info;
Chris Wilson642c8a72017-02-06 21:36:07 +0000621 struct i915_params params;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100622
Michal Wajdeczko7d41ef32017-10-26 17:36:55 +0000623 struct i915_error_uc {
624 struct intel_uc_fw guc_fw;
625 struct intel_uc_fw huc_fw;
Michal Wajdeczko0397ac12017-10-26 17:36:56 +0000626 struct drm_i915_error_object *guc_log;
Michal Wajdeczko7d41ef32017-10-26 17:36:55 +0000627 } uc;
628
Chris Wilson2bd160a2016-08-15 10:48:45 +0100629 /* Generic register state */
630 u32 eir;
631 u32 pgtbl_er;
632 u32 ier;
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000633 u32 gtier[4], ngtier;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100634 u32 ccid;
635 u32 derrmr;
636 u32 forcewake;
637 u32 error; /* gen6+ */
638 u32 err_int; /* gen7 */
639 u32 fault_data0; /* gen8, gen9 */
640 u32 fault_data1; /* gen8, gen9 */
641 u32 done_reg;
642 u32 gac_eco;
643 u32 gam_ecochk;
644 u32 gab_ctl;
645 u32 gfx_mode;
Ben Widawskyd6369512016-09-20 16:54:32 +0300646
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000647 u32 nfence;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100648 u64 fence[I915_MAX_NUM_FENCES];
649 struct intel_overlay_error_state *overlay;
650 struct intel_display_error_state *display;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100651
652 struct drm_i915_error_engine {
653 int engine_id;
654 /* Software tracked state */
Chris Wilson398c8a32017-12-19 13:14:19 +0000655 bool idle;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100656 bool waiting;
657 int num_waiters;
Mika Kuoppala3fe3b032016-11-18 15:09:04 +0200658 unsigned long hangcheck_timestamp;
659 bool hangcheck_stalled;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100660 enum intel_engine_hangcheck_action hangcheck_action;
661 struct i915_address_space *vm;
662 int num_requests;
Michel Thierry702c8f82017-06-20 10:57:48 +0100663 u32 reset_count;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100664
Chris Wilsoncdb324b2016-10-04 21:11:30 +0100665 /* position of active request inside the ring */
666 u32 rq_head, rq_post, rq_tail;
667
Chris Wilson2bd160a2016-08-15 10:48:45 +0100668 /* our own tracking of ring head and tail */
669 u32 cpu_ring_head;
670 u32 cpu_ring_tail;
671
672 u32 last_seqno;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100673
674 /* Register state */
675 u32 start;
676 u32 tail;
677 u32 head;
678 u32 ctl;
Chris Wilson21a2c582016-08-15 10:49:11 +0100679 u32 mode;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100680 u32 hws;
681 u32 ipeir;
682 u32 ipehr;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100683 u32 bbstate;
684 u32 instpm;
685 u32 instps;
686 u32 seqno;
687 u64 bbaddr;
688 u64 acthd;
689 u32 fault_reg;
690 u64 faddr;
691 u32 rc_psmi; /* sleep state */
692 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
Ben Widawskyd6369512016-09-20 16:54:32 +0300693 struct intel_instdone instdone;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100694
Chris Wilson4fa60532017-01-29 09:24:33 +0000695 struct drm_i915_error_context {
696 char comm[TASK_COMM_LEN];
697 pid_t pid;
698 u32 handle;
699 u32 hw_id;
Chris Wilson1f181222017-10-03 21:34:50 +0100700 int priority;
Chris Wilson4fa60532017-01-29 09:24:33 +0000701 int ban_score;
702 int active;
703 int guilty;
704 } context;
705
Chris Wilson2bd160a2016-08-15 10:48:45 +0100706 struct drm_i915_error_object {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100707 u64 gtt_offset;
Chris Wilson03382df2016-08-15 10:49:09 +0100708 u64 gtt_size;
Chris Wilson0a970152016-10-12 10:05:22 +0100709 int page_count;
710 int unused;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100711 u32 *pages[0];
712 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
713
Chris Wilsonb0fd47a2017-04-15 10:39:02 +0100714 struct drm_i915_error_object **user_bo;
715 long user_bo_count;
716
Chris Wilson2bd160a2016-08-15 10:48:45 +0100717 struct drm_i915_error_object *wa_ctx;
Chris Wilson4e90a6e22017-11-26 22:09:01 +0000718 struct drm_i915_error_object *default_state;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100719
720 struct drm_i915_error_request {
721 long jiffies;
Chris Wilsonc84455b2016-08-15 10:49:08 +0100722 pid_t pid;
Chris Wilson35ca0392016-10-13 11:18:14 +0100723 u32 context;
Chris Wilson1f181222017-10-03 21:34:50 +0100724 int priority;
Mika Kuoppala84102172016-11-16 17:20:32 +0200725 int ban_score;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100726 u32 seqno;
727 u32 head;
728 u32 tail;
Mika Kuoppala76e70082017-09-22 15:43:07 +0300729 } *requests, execlist[EXECLIST_MAX_PORTS];
730 unsigned int num_ports;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100731
732 struct drm_i915_error_waiter {
733 char comm[TASK_COMM_LEN];
734 pid_t pid;
735 u32 seqno;
736 } *waiters;
737
738 struct {
739 u32 gfx_mode;
740 union {
741 u64 pdp[4];
742 u32 pp_dir_base;
743 };
744 } vm_info;
Chris Wilson2bd160a2016-08-15 10:48:45 +0100745 } engine[I915_NUM_ENGINES];
746
747 struct drm_i915_error_buffer {
748 u32 size;
749 u32 name;
750 u32 rseqno[I915_NUM_ENGINES], wseqno;
751 u64 gtt_offset;
752 u32 read_domains;
753 u32 write_domain;
754 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
755 u32 tiling:2;
756 u32 dirty:1;
757 u32 purgeable:1;
758 u32 userptr:1;
759 s32 engine:4;
760 u32 cache_level:3;
761 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
762 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
763 struct i915_address_space *active_vm[I915_NUM_ENGINES];
764};
765
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800766enum i915_cache_level {
767 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100768 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
769 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
770 caches, eg sampler/render caches, and the
771 large Last-Level-Cache. LLC is coherent with
772 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100773 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800774};
775
Chris Wilson85fd4f52016-12-05 14:29:36 +0000776#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
777
Paulo Zanonia4001f12015-02-13 17:23:44 -0200778enum fb_op_origin {
779 ORIGIN_GTT,
780 ORIGIN_CPU,
781 ORIGIN_CS,
782 ORIGIN_FLIP,
Paulo Zanoni74b4ea12015-07-14 16:29:14 -0300783 ORIGIN_DIRTYFB,
Paulo Zanonia4001f12015-02-13 17:23:44 -0200784};
785
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200786struct intel_fbc {
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300787 /* This is always the inner lock when overlapping with struct_mutex and
788 * it's the outer lock when overlapping with stolen_lock. */
789 struct mutex lock;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700790 unsigned threshold;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200791 unsigned int possible_framebuffer_bits;
792 unsigned int busy_bits;
Paulo Zanoni010cf732016-01-19 11:35:48 -0200793 unsigned int visible_pipes_mask;
Paulo Zanonie35fef22015-02-09 14:46:29 -0200794 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700795
Ben Widawskyc4213882014-06-19 12:06:10 -0700796 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700797 struct drm_mm_node *compressed_llb;
798
Rodrigo Vivida46f932014-08-01 02:04:45 -0700799 bool false_color;
800
Paulo Zanonid029bca2015-10-15 10:44:46 -0300801 bool enabled;
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300802 bool active;
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300803
Paulo Zanoni61a585d2016-09-13 10:38:57 -0300804 bool underrun_detected;
805 struct work_struct underrun_work;
806
Paulo Zanoni525a4f92017-07-14 16:38:22 -0300807 /*
808 * Due to the atomic rules we can't access some structures without the
809 * appropriate locking, so we cache information here in order to avoid
810 * these problems.
811 */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200812 struct intel_fbc_state_cache {
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000813 struct i915_vma *vma;
814
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200815 struct {
816 unsigned int mode_flags;
817 uint32_t hsw_bdw_pixel_rate;
818 } crtc;
819
820 struct {
821 unsigned int rotation;
822 int src_w;
823 int src_h;
824 bool visible;
Juha-Pekka Heikkilabf0a5d42017-10-17 23:08:07 +0300825 /*
826 * Display surface base address adjustement for
827 * pageflips. Note that on gen4+ this only adjusts up
828 * to a tile, offsets within a tile are handled in
829 * the hw itself (with the TILEOFF register).
830 */
831 int adjusted_x;
832 int adjusted_y;
Juha-Pekka Heikkila31d1d3c2017-10-17 23:08:11 +0300833
834 int y;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200835 } plane;
836
837 struct {
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200838 const struct drm_format_info *format;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200839 unsigned int stride;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200840 } fb;
841 } state_cache;
842
Paulo Zanoni525a4f92017-07-14 16:38:22 -0300843 /*
844 * This structure contains everything that's relevant to program the
845 * hardware registers. When we want to figure out if we need to disable
846 * and re-enable FBC for a new configuration we just check if there's
847 * something different in the struct. The genx_fbc_activate functions
848 * are supposed to read from it in order to program the registers.
849 */
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200850 struct intel_fbc_reg_params {
Chris Wilsonbe1e3412017-01-16 15:21:27 +0000851 struct i915_vma *vma;
852
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200853 struct {
854 enum pipe pipe;
Ville Syrjäläed150302017-11-17 21:19:10 +0200855 enum i9xx_plane_id i9xx_plane;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200856 unsigned int fence_y_offset;
857 } crtc;
858
859 struct {
Ville Syrjälä801c8fe2016-11-18 21:53:04 +0200860 const struct drm_format_info *format;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200861 unsigned int stride;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200862 } fb;
863
864 int cfb_size;
Praveen Paneri5654a162017-08-11 00:00:33 +0530865 unsigned int gen9_wa_cfb_stride;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200866 } params;
867
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700868 struct intel_fbc_work {
Paulo Zanoni128d7352015-10-26 16:27:49 -0200869 bool scheduled;
Paulo Zanonica18d512016-01-21 18:03:05 -0200870 u32 scheduled_vblank;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200871 struct work_struct work;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200872 } work;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700873
Paulo Zanonibf6189c2015-10-27 14:50:03 -0200874 const char *no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800875};
876
Chris Wilsonfe88d122016-12-31 11:20:12 +0000877/*
Vandana Kannan96178ee2015-01-10 02:25:56 +0530878 * HIGH_RR is the highest eDP panel refresh rate read from EDID
879 * LOW_RR is the lowest eDP panel refresh rate found from EDID
880 * parsing for same resolution.
881 */
882enum drrs_refresh_rate_type {
883 DRRS_HIGH_RR,
884 DRRS_LOW_RR,
885 DRRS_MAX_RR, /* RR count */
886};
887
888enum drrs_support_type {
889 DRRS_NOT_SUPPORTED = 0,
890 STATIC_DRRS_SUPPORT = 1,
891 SEAMLESS_DRRS_SUPPORT = 2
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530892};
893
Daniel Vetter2807cf62014-07-11 10:30:11 -0700894struct intel_dp;
Vandana Kannan96178ee2015-01-10 02:25:56 +0530895struct i915_drrs {
896 struct mutex mutex;
897 struct delayed_work work;
898 struct intel_dp *dp;
899 unsigned busy_frontbuffer_bits;
900 enum drrs_refresh_rate_type refresh_rate_type;
901 enum drrs_support_type type;
902};
903
Rodrigo Vivia031d702013-10-03 16:15:06 -0300904struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -0700905 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300906 bool sink_support;
907 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -0700908 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -0700909 bool active;
910 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -0700911 unsigned busy_frontbuffer_bits;
Sonika Jindal474d1ec2015-04-02 11:02:44 +0530912 bool psr2_support;
913 bool aux_frame_sync;
Rodrigo Vivi60e5ffe2016-02-01 12:02:07 -0800914 bool link_standby;
Nagaraju, Vathsala97da2ef2017-01-02 17:00:55 +0530915 bool y_cord_support;
916 bool colorimetry_support;
Nagaraju, Vathsala340c93c2017-01-02 17:00:58 +0530917 bool alpm;
Rodrigo Vivi424644c2017-09-07 16:00:32 -0700918
Rodrigo Vivid0d5e0d2017-09-07 16:00:41 -0700919 void (*enable_source)(struct intel_dp *,
920 const struct intel_crtc_state *);
Rodrigo Vivi424644c2017-09-07 16:00:32 -0700921 void (*disable_source)(struct intel_dp *,
922 const struct intel_crtc_state *);
Rodrigo Vivi49ad3162017-09-07 16:00:40 -0700923 void (*enable_sink)(struct intel_dp *);
Rodrigo Vivie3702ac2017-09-07 16:00:34 -0700924 void (*activate)(struct intel_dp *);
Rodrigo Vivi2a5db872017-09-07 16:00:39 -0700925 void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300926};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700927
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800928enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300929 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800930 PCH_IBX, /* Ibexpeak PCH */
Ville Syrjälä243dec52017-06-20 16:03:08 +0300931 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
932 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530933 PCH_SPT, /* Sunrisepoint PCH */
Rodrigo Vivi23247d72017-07-31 11:52:20 -0700934 PCH_KBP, /* Kaby Lake PCH */
935 PCH_CNP, /* Cannon Lake PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700936 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800937};
938
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200939enum intel_sbi_destination {
940 SBI_ICLK,
941 SBI_MPHY,
942};
943
Keith Packard435793d2011-07-12 14:56:22 -0700944#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100945#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +0000946#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Daniel Vetter656bfa32014-11-20 09:26:30 +0100947#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Manasi Navarec99a2592017-06-30 09:33:48 -0700948#define QUIRK_INCREASE_T12_DELAY (1<<6)
Jesse Barnesb690e962010-07-19 13:53:12 -0700949
Dave Airlie8be48d92010-03-30 05:34:14 +0000950struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100951struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000952
Daniel Vetterc2b91522012-02-14 22:37:19 +0100953struct intel_gmbus {
954 struct i2c_adapter adapter;
Ville Syrjälä3e4d44e2016-03-07 17:56:59 +0200955#define GMBUS_FORCE_BIT_RETRY (1U << 31)
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000956 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100957 u32 reg0;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200958 i915_reg_t gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100959 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100960 struct drm_i915_private *dev_priv;
961};
962
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100963struct i915_suspend_saved_registers {
Keith Packarde948e992008-05-07 12:27:53 +1000964 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000965 u32 saveFBC_CONTROL;
Keith Packard1f84e552008-02-16 19:19:29 -0800966 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800967 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000968 u32 saveSWF0[16];
969 u32 saveSWF1[16];
Ville Syrjälä85fa7922015-09-18 20:03:43 +0300970 u32 saveSWF3[3];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200971 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400972 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -0800973 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100974};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100975
Imre Deakddeea5b2014-05-05 15:19:56 +0300976struct vlv_s0ix_state {
977 /* GAM */
978 u32 wr_watermark;
979 u32 gfx_prio_ctrl;
980 u32 arb_mode;
981 u32 gfx_pend_tlb0;
982 u32 gfx_pend_tlb1;
983 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
984 u32 media_max_req_count;
985 u32 gfx_max_req_count;
986 u32 render_hwsp;
987 u32 ecochk;
988 u32 bsd_hwsp;
989 u32 blt_hwsp;
990 u32 tlb_rd_addr;
991
992 /* MBC */
993 u32 g3dctl;
994 u32 gsckgctl;
995 u32 mbctl;
996
997 /* GCP */
998 u32 ucgctl1;
999 u32 ucgctl3;
1000 u32 rcgctl1;
1001 u32 rcgctl2;
1002 u32 rstctl;
1003 u32 misccpctl;
1004
1005 /* GPM */
1006 u32 gfxpause;
1007 u32 rpdeuhwtc;
1008 u32 rpdeuc;
1009 u32 ecobus;
1010 u32 pwrdwnupctl;
1011 u32 rp_down_timeout;
1012 u32 rp_deucsw;
1013 u32 rcubmabdtmr;
1014 u32 rcedata;
1015 u32 spare2gh;
1016
1017 /* Display 1 CZ domain */
1018 u32 gt_imr;
1019 u32 gt_ier;
1020 u32 pm_imr;
1021 u32 pm_ier;
1022 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1023
1024 /* GT SA CZ domain */
1025 u32 tilectl;
1026 u32 gt_fifoctl;
1027 u32 gtlc_wake_ctrl;
1028 u32 gtlc_survive;
1029 u32 pmwgicz;
1030
1031 /* Display 2 CZ domain */
1032 u32 gu_ctl0;
1033 u32 gu_ctl1;
Jesse Barnes9c252102015-04-01 14:22:57 -07001034 u32 pcbr;
Imre Deakddeea5b2014-05-05 15:19:56 +03001035 u32 clock_gate_dis2;
1036};
1037
Chris Wilsonbf225f22014-07-10 20:31:18 +01001038struct intel_rps_ei {
Mika Kuoppala679cb6c2017-03-15 17:43:03 +02001039 ktime_t ktime;
Chris Wilsonbf225f22014-07-10 20:31:18 +01001040 u32 render_c0;
1041 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -04001042};
1043
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001044struct intel_rps {
Imre Deakd4d70aa2014-11-19 15:30:04 +02001045 /*
1046 * work, interrupts_enabled and pm_iir are protected by
1047 * dev_priv->irq_lock
1048 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001049 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001050 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001051 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001052
Dave Gordonb20e3cf2016-09-12 21:19:35 +01001053 /* PM interrupt bits that should never be masked */
Sagar Arun Kamble5dd04552017-03-11 08:07:00 +05301054 u32 pm_intrmsk_mbz;
Sagar Arun Kamble1800ad22016-05-31 13:58:27 +05301055
Ben Widawskyb39fb292014-03-19 18:31:11 -07001056 /* Frequencies are stored in potentially platform dependent multiples.
1057 * In other words, *_freq needs to be multiplied by X to be interesting.
1058 * Soft limits are those which are used for the dynamic reclocking done
1059 * by the driver (raise frequencies under heavy loads, and lower for
1060 * lighter loads). Hard limits are those imposed by the hardware.
1061 *
1062 * A distinction is made for overclocking, which is never enabled by
1063 * default, and is considered to be above the hard limit if it's
1064 * possible at all.
1065 */
1066 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1067 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1068 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1069 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1070 u8 min_freq; /* AKA RPn. Minimum frequency */
Chris Wilson29ecd78d2016-07-13 09:10:35 +01001071 u8 boost_freq; /* Frequency to request when wait boosting */
Chris Wilsonaed242f2015-03-18 09:48:21 +00001072 u8 idle_freq; /* Frequency to request when we are idle */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001073 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1074 u8 rp1_freq; /* "less than" RP0 power/freqency */
1075 u8 rp0_freq; /* Non-overclocked max frequency. */
Ville Syrjäläc30fec62016-03-04 21:43:02 +02001076 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001077
Chris Wilson8fb55192015-04-07 16:20:28 +01001078 u8 up_threshold; /* Current %busy required to uplock */
1079 u8 down_threshold; /* Current %busy required to downclock */
1080
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001081 int last_adj;
1082 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1083
Chris Wilsonc0951f02013-10-10 21:58:50 +01001084 bool enabled;
Chris Wilson7b92c1b2017-06-28 13:35:48 +01001085 atomic_t num_waiters;
1086 atomic_t boosts;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001087
Chris Wilsonbf225f22014-07-10 20:31:18 +01001088 /* manual wa residency calculations */
Chris Wilsone0e8c7c2017-03-09 21:12:30 +00001089 struct intel_rps_ei ei;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001090};
1091
Sagar Arun Kamble37d933f2017-10-10 22:30:10 +01001092struct intel_rc6 {
1093 bool enabled;
1094};
1095
1096struct intel_llc_pstate {
1097 bool enabled;
1098};
1099
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001100struct intel_gen6_power_mgmt {
1101 struct intel_rps rps;
Sagar Arun Kamble37d933f2017-10-10 22:30:10 +01001102 struct intel_rc6 rc6;
1103 struct intel_llc_pstate llc_pstate;
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001104};
1105
Daniel Vetter1a240d42012-11-29 22:18:51 +01001106/* defined intel_pm.c */
1107extern spinlock_t mchdev_lock;
1108
Daniel Vetterc85aa882012-11-02 19:55:03 +01001109struct intel_ilk_power_mgmt {
1110 u8 cur_delay;
1111 u8 min_delay;
1112 u8 max_delay;
1113 u8 fmax;
1114 u8 fstart;
1115
1116 u64 last_count1;
1117 unsigned long last_time1;
1118 unsigned long chipset_power;
1119 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001120 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001121 unsigned long gfx_power;
1122 u8 corr;
1123
1124 int c_m;
1125 int r_t;
1126};
1127
Imre Deakc6cb5822014-03-04 19:22:55 +02001128struct drm_i915_private;
1129struct i915_power_well;
1130
1131struct i915_power_well_ops {
1132 /*
1133 * Synchronize the well's hw state to match the current sw state, for
1134 * example enable/disable it based on the current refcount. Called
1135 * during driver init and resume time, possibly after first calling
1136 * the enable/disable handlers.
1137 */
1138 void (*sync_hw)(struct drm_i915_private *dev_priv,
1139 struct i915_power_well *power_well);
1140 /*
1141 * Enable the well and resources that depend on it (for example
1142 * interrupts located on the well). Called after the 0->1 refcount
1143 * transition.
1144 */
1145 void (*enable)(struct drm_i915_private *dev_priv,
1146 struct i915_power_well *power_well);
1147 /*
1148 * Disable the well and resources that depend on it. Called after
1149 * the 1->0 refcount transition.
1150 */
1151 void (*disable)(struct drm_i915_private *dev_priv,
1152 struct i915_power_well *power_well);
1153 /* Returns the hw enabled state. */
1154 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1155 struct i915_power_well *power_well);
1156};
1157
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001158/* Power well structure for haswell */
1159struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001160 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001161 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001162 /* power well enable/disable usage count */
1163 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001164 /* cached hw enabled state */
1165 bool hw_enabled;
Ander Conselvan de Oliveirad8fc70b2017-02-09 11:31:21 +02001166 u64 domains;
Ander Conselvan de Oliveira01c3faa2016-10-06 19:22:14 +03001167 /* unique identifier for this power well */
Imre Deak438b8dc2017-07-11 23:42:30 +03001168 enum i915_power_well_id id;
Ander Conselvan de Oliveira362624c2016-10-06 19:22:15 +03001169 /*
1170 * Arbitraty data associated with this power well. Platform and power
1171 * well specific.
1172 */
Imre Deakb5565a22017-07-06 17:40:29 +03001173 union {
1174 struct {
1175 enum dpio_phy phy;
1176 } bxt;
Imre Deak001bd2c2017-07-12 18:54:13 +03001177 struct {
1178 /* Mask of pipes whose IRQ logic is backed by the pw */
1179 u8 irq_pipe_mask;
1180 /* The pw is backing the VGA functionality */
1181 bool has_vga:1;
Imre Deakb2891eb2017-07-11 23:42:35 +03001182 bool has_fuses:1;
Imre Deak001bd2c2017-07-12 18:54:13 +03001183 } hsw;
Imre Deakb5565a22017-07-06 17:40:29 +03001184 };
Imre Deakc6cb5822014-03-04 19:22:55 +02001185 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001186};
1187
Imre Deak83c00f52013-10-25 17:36:47 +03001188struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001189 /*
1190 * Power wells needed for initialization at driver init and suspend
1191 * time are on. They are kept on until after the first modeset.
1192 */
1193 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001194 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001195 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001196
Imre Deak83c00f52013-10-25 17:36:47 +03001197 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001198 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001199 struct i915_power_well *power_wells;
Imre Deak83c00f52013-10-25 17:36:47 +03001200};
1201
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001202#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001203struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001204 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001205 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001206 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001207};
1208
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001209struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001210 /** Memory allocator for GTT stolen memory */
1211 struct drm_mm stolen;
Paulo Zanoni92e97d22015-07-02 19:25:09 -03001212 /** Protects the usage of the GTT stolen memory allocator. This is
1213 * always the inner lock when overlapping with struct_mutex. */
1214 struct mutex stolen_lock;
1215
Chris Wilsonf2123812017-10-16 12:40:37 +01001216 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
1217 spinlock_t obj_lock;
1218
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001219 /** List of all objects in gtt_space. Used to restore gtt
1220 * mappings on resume */
1221 struct list_head bound_list;
1222 /**
1223 * List of objects which are not bound to the GTT (thus
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01001224 * are idle and not used by the GPU). These objects may or may
1225 * not actually have any pages attached.
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001226 */
1227 struct list_head unbound_list;
1228
Chris Wilson275f0392016-10-24 13:42:14 +01001229 /** List of all objects in gtt_space, currently mmaped by userspace.
1230 * All objects within this list must also be on bound_list.
1231 */
1232 struct list_head userfault_list;
1233
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01001234 /**
1235 * List of objects which are pending destruction.
1236 */
1237 struct llist_head free_list;
1238 struct work_struct free_work;
Chris Wilson87701b42017-10-13 21:26:20 +01001239 spinlock_t free_lock;
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01001240
Chris Wilson66df1012017-08-22 18:38:28 +01001241 /**
1242 * Small stash of WC pages
1243 */
1244 struct pagevec wc_stash;
1245
Matthew Auld465c4032017-10-06 23:18:14 +01001246 /**
1247 * tmpfs instance used for shmem backed objects
1248 */
1249 struct vfsmount *gemfs;
1250
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001251 /** PPGTT used for aliasing the PPGTT with the GTT */
1252 struct i915_hw_ppgtt *aliasing_ppgtt;
1253
Chris Wilson2cfcd322014-05-20 08:28:43 +01001254 struct notifier_block oom_notifier;
Chris Wilsone87666b2016-04-04 14:46:43 +01001255 struct notifier_block vmap_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001256 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001257
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001258 /** LRU list of objects with fence regs on them. */
1259 struct list_head fence_list;
1260
Chris Wilson8a2421b2017-06-16 15:05:22 +01001261 /**
1262 * Workqueue to fault in userptr pages, flushed by the execbuf
1263 * when required but otherwise left to userspace to try again
1264 * on EAGAIN.
1265 */
1266 struct workqueue_struct *userptr_wq;
1267
Chris Wilson94312822017-05-03 10:39:18 +01001268 u64 unordered_timeline;
1269
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001270 /* the indicator for dispatch video commands on two BSD rings */
Joonas Lahtinen6f633402016-09-01 14:58:21 +03001271 atomic_t bsd_engine_dispatch_index;
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001272
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001273 /** Bit 6 swizzling required for X tiling */
1274 uint32_t bit_6_swizzle_x;
1275 /** Bit 6 swizzling required for Y tiling */
1276 uint32_t bit_6_swizzle_y;
1277
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001278 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001279 spinlock_t object_stat_lock;
Chris Wilson3ef7f222016-10-18 13:02:48 +01001280 u64 object_memory;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001281 u32 object_count;
1282};
1283
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001284struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001285 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001286 unsigned bytes;
1287 unsigned size;
1288 int err;
1289 u8 *buf;
1290 loff_t start;
1291 loff_t pos;
1292};
1293
Chris Wilsonee42c002017-12-11 19:41:34 +00001294#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
1295
Chris Wilsonb52992c2016-10-28 13:58:24 +01001296#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1297#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1298
Mika Kuoppala3fe3b032016-11-18 15:09:04 +02001299#define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1300#define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1301
Daniel Vetter99584db2012-11-14 17:14:04 +01001302struct i915_gpu_error {
1303 /* For hangcheck timer */
1304#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1305#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001306
Chris Wilson737b1502015-01-26 18:03:03 +02001307 struct delayed_work hangcheck_work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001308
1309 /* For reset and error_state handling. */
1310 spinlock_t lock;
1311 /* Protected by the above dev->gpu_error.lock. */
Chris Wilson5a4c6f12017-02-14 16:46:11 +00001312 struct i915_gpu_state *first_error;
Chris Wilson094f9a52013-09-25 17:34:55 +01001313
Daniel Vetter9db529a2017-08-08 10:08:28 +02001314 atomic_t pending_fb_pin;
1315
Chris Wilson094f9a52013-09-25 17:34:55 +01001316 unsigned long missed_irq_rings;
1317
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001318 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001319 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001320 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001321 * This is a counter which gets incremented when reset is triggered,
Chris Wilson8af29b02016-09-09 14:11:47 +01001322 *
Michel Thierry56306c62017-04-18 13:23:16 -07001323 * Before the reset commences, the I915_RESET_BACKOFF bit is set
Chris Wilson8af29b02016-09-09 14:11:47 +01001324 * meaning that any waiters holding onto the struct_mutex should
1325 * relinquish the lock immediately in order for the reset to start.
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001326 *
1327 * If reset is not completed succesfully, the I915_WEDGE bit is
1328 * set meaning that hardware is terminally sour and there is no
1329 * recovery. All waiters on the reset_queue will be woken when
1330 * that happens.
1331 *
1332 * This counter is used by the wait_seqno code to notice that reset
1333 * event happened and it needs to restart the entire ioctl (since most
1334 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001335 *
1336 * This is important for lock-free wait paths, where no contended lock
1337 * naturally enforces the correct ordering between the bail-out of the
1338 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001339 */
Chris Wilson8af29b02016-09-09 14:11:47 +01001340 unsigned long reset_count;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001341
Chris Wilson8c185ec2017-03-16 17:13:02 +00001342 /**
1343 * flags: Control various stages of the GPU reset
1344 *
1345 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1346 * other users acquiring the struct_mutex. To do this we set the
1347 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1348 * and then check for that bit before acquiring the struct_mutex (in
1349 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1350 * secondary role in preventing two concurrent global reset attempts.
1351 *
1352 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1353 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1354 * but it may be held by some long running waiter (that we cannot
1355 * interrupt without causing trouble). Once we are ready to do the GPU
1356 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1357 * they already hold the struct_mutex and want to participate they can
1358 * inspect the bit and do the reset directly, otherwise the worker
1359 * waits for the struct_mutex.
1360 *
Michel Thierry142bc7d2017-06-20 10:57:46 +01001361 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1362 * acquire the struct_mutex to reset an engine, we need an explicit
1363 * flag to prevent two concurrent reset attempts in the same engine.
1364 * As the number of engines continues to grow, allocate the flags from
1365 * the most significant bits.
1366 *
Chris Wilson8c185ec2017-03-16 17:13:02 +00001367 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1368 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1369 * i915_gem_request_alloc(), this bit is checked and the sequence
1370 * aborted (with -EIO reported to userspace) if set.
1371 */
Chris Wilson8af29b02016-09-09 14:11:47 +01001372 unsigned long flags;
Chris Wilson8c185ec2017-03-16 17:13:02 +00001373#define I915_RESET_BACKOFF 0
1374#define I915_RESET_HANDOFF 1
Daniel Vetter9db529a2017-08-08 10:08:28 +02001375#define I915_RESET_MODESET 2
Chris Wilson8af29b02016-09-09 14:11:47 +01001376#define I915_WEDGED (BITS_PER_LONG - 1)
Michel Thierry142bc7d2017-06-20 10:57:46 +01001377#define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001378
Michel Thierry702c8f82017-06-20 10:57:48 +01001379 /** Number of times an engine has been reset */
1380 u32 reset_engine_count[I915_NUM_ENGINES];
1381
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001382 /**
Chris Wilson1f15b762016-07-01 17:23:14 +01001383 * Waitqueue to signal when a hang is detected. Used to for waiters
1384 * to release the struct_mutex for the reset to procede.
1385 */
1386 wait_queue_head_t wait_queue;
1387
1388 /**
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001389 * Waitqueue to signal when the reset has completed. Used by clients
1390 * that wait for dev_priv->mm.wedged to settle.
1391 */
1392 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001393
Chris Wilson094f9a52013-09-25 17:34:55 +01001394 /* For missed irq/seqno simulation. */
Chris Wilson688e6c72016-07-01 17:23:15 +01001395 unsigned long test_irq_rings;
Daniel Vetter99584db2012-11-14 17:14:04 +01001396};
1397
Zhang Ruib8efb172013-02-05 15:41:53 +08001398enum modeset_restore {
1399 MODESET_ON_LID_OPEN,
1400 MODESET_DONE,
1401 MODESET_SUSPENDED,
1402};
1403
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001404#define DP_AUX_A 0x40
1405#define DP_AUX_B 0x10
1406#define DP_AUX_C 0x20
1407#define DP_AUX_D 0x30
1408
Xiong Zhang11c1b652015-08-17 16:04:04 +08001409#define DDC_PIN_B 0x05
1410#define DDC_PIN_C 0x04
1411#define DDC_PIN_D 0x06
1412
Paulo Zanoni6acab152013-09-12 17:06:24 -03001413struct ddi_vbt_port_info {
Ville Syrjäläd6038612017-10-30 16:57:02 +02001414 int max_tmds_clock;
1415
Damien Lespiauce4dd492014-08-01 11:07:54 +01001416 /*
1417 * This is an index in the HDMI/DVI DDI buffer translation table.
1418 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1419 * populate this field.
1420 */
1421#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001422 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001423
1424 uint8_t supports_dvi:1;
1425 uint8_t supports_hdmi:1;
1426 uint8_t supports_dp:1;
Imre Deaka98d9c12016-12-21 12:17:24 +02001427 uint8_t supports_edp:1;
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001428
1429 uint8_t alternate_aux_channel;
Xiong Zhang11c1b652015-08-17 16:04:04 +08001430 uint8_t alternate_ddc_pin;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001431
1432 uint8_t dp_boost_level;
1433 uint8_t hdmi_boost_level;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001434};
1435
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001436enum psr_lines_to_wait {
1437 PSR_0_LINES_TO_WAIT = 0,
1438 PSR_1_LINE_TO_WAIT,
1439 PSR_4_LINES_TO_WAIT,
1440 PSR_8_LINES_TO_WAIT
Pradeep Bhat83a72802014-03-28 10:14:57 +05301441};
1442
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001443struct intel_vbt_data {
1444 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1445 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1446
1447 /* Feature bits */
1448 unsigned int int_tv_support:1;
1449 unsigned int lvds_dither:1;
1450 unsigned int lvds_vbt:1;
1451 unsigned int int_crt_support:1;
1452 unsigned int lvds_use_ssc:1;
1453 unsigned int display_clock_mode:1;
1454 unsigned int fdi_rx_polarity_inverted:1;
Ville Syrjälä3e845c72016-04-08 16:28:12 +03001455 unsigned int panel_type:4;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001456 int lvds_ssc_freq;
1457 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1458
Pradeep Bhat83a72802014-03-28 10:14:57 +05301459 enum drrs_support_type drrs_type;
1460
Jani Nikula6aa23e62016-03-24 17:50:20 +02001461 struct {
1462 int rate;
1463 int lanes;
1464 int preemphasis;
1465 int vswing;
Jani Nikula06411f02016-03-24 17:50:21 +02001466 bool low_vswing;
Jani Nikula6aa23e62016-03-24 17:50:20 +02001467 bool initialized;
1468 bool support;
1469 int bpp;
1470 struct edp_power_seq pps;
1471 } edp;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001472
Jani Nikulaf00076d2013-12-14 20:38:29 -02001473 struct {
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001474 bool full_link;
1475 bool require_aux_wakeup;
1476 int idle_frames;
1477 enum psr_lines_to_wait lines_to_wait;
1478 int tp1_wakeup_time;
1479 int tp2_tp3_wakeup_time;
1480 } psr;
1481
1482 struct {
Jani Nikulaf00076d2013-12-14 20:38:29 -02001483 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001484 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001485 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001486 u8 min_brightness; /* min_brightness/255 of max */
Vidya Srinivasadd03372016-12-08 11:26:18 +02001487 u8 controller; /* brightness controller number */
Deepak M9a41e172016-04-26 16:14:24 +03001488 enum intel_backlight_type type;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001489 } backlight;
1490
Shobhit Kumard17c5442013-08-27 15:12:25 +03001491 /* MIPI DSI */
1492 struct {
1493 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301494 struct mipi_config *config;
1495 struct mipi_pps_data *pps;
Madhav Chauhan46e58322017-10-13 18:14:59 +05301496 u16 bl_ports;
1497 u16 cabc_ports;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301498 u8 seq_version;
1499 u32 size;
1500 u8 *data;
Jani Nikula8d3ed2f2015-12-21 15:10:57 +02001501 const u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001502 } dsi;
1503
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001504 int crt_ddc_pin;
1505
1506 int child_dev_num;
Jani Nikulacc998582017-08-24 21:54:03 +03001507 struct child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001508
1509 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Jani Nikula9d6c8752016-03-24 17:50:22 +02001510 struct sdvo_device_mapping sdvo_mappings[2];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001511};
1512
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001513enum intel_ddb_partitioning {
1514 INTEL_DDB_PART_1_2,
1515 INTEL_DDB_PART_5_6, /* IVB+ */
1516};
1517
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001518struct intel_wm_level {
1519 bool enable;
1520 uint32_t pri_val;
1521 uint32_t spr_val;
1522 uint32_t cur_val;
1523 uint32_t fbc_val;
1524};
1525
Imre Deak820c1982013-12-17 14:46:36 +02001526struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001527 uint32_t wm_pipe[3];
1528 uint32_t wm_lp[3];
1529 uint32_t wm_lp_spr[3];
1530 uint32_t wm_linetime[3];
1531 bool enable_fbc_wm;
1532 enum intel_ddb_partitioning partitioning;
1533};
1534
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001535struct g4x_pipe_wm {
Ville Syrjälä1b313892016-11-28 19:37:08 +02001536 uint16_t plane[I915_MAX_PLANES];
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001537 uint16_t fbc;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001538};
1539
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001540struct g4x_sr_wm {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001541 uint16_t plane;
Ville Syrjälä1b313892016-11-28 19:37:08 +02001542 uint16_t cursor;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001543 uint16_t fbc;
Ville Syrjälä1b313892016-11-28 19:37:08 +02001544};
1545
1546struct vlv_wm_ddl_values {
1547 uint8_t plane[I915_MAX_PLANES];
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001548};
1549
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001550struct vlv_wm_values {
Ville Syrjälä114d7dc2017-04-21 21:14:21 +03001551 struct g4x_pipe_wm pipe[3];
1552 struct g4x_sr_wm sr;
Ville Syrjälä1b313892016-11-28 19:37:08 +02001553 struct vlv_wm_ddl_values ddl[3];
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03001554 uint8_t level;
1555 bool cxsr;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001556};
1557
Ville Syrjälä04548cb2017-04-21 21:14:29 +03001558struct g4x_wm_values {
1559 struct g4x_pipe_wm pipe[2];
1560 struct g4x_sr_wm sr;
1561 struct g4x_sr_wm hpll;
1562 bool cxsr;
1563 bool hpll_en;
1564 bool fbc_en;
1565};
1566
Damien Lespiauc1939242014-11-04 17:06:41 +00001567struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001568 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001569};
1570
1571static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1572{
Damien Lespiau16160e32014-11-04 17:06:53 +00001573 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001574}
1575
Damien Lespiau08db6652014-11-04 17:06:52 +00001576static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1577 const struct skl_ddb_entry *e2)
1578{
1579 if (e1->start == e2->start && e1->end == e2->end)
1580 return true;
1581
1582 return false;
1583}
1584
Damien Lespiauc1939242014-11-04 17:06:41 +00001585struct skl_ddb_allocation {
Chandra Konduru2cd601c2015-04-27 15:47:37 -07001586 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
Matt Roper4969d332015-09-24 15:53:10 -07001587 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001588};
1589
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001590struct skl_wm_values {
Matt Roper2b4b9f32016-05-12 07:06:07 -07001591 unsigned dirty_pipes;
Damien Lespiauc1939242014-11-04 17:06:41 +00001592 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001593};
1594
1595struct skl_wm_level {
Lyudea62163e2016-10-04 14:28:20 -04001596 bool plane_en;
1597 uint16_t plane_res_b;
1598 uint8_t plane_res_l;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001599};
1600
Kumar, Mahesh7e452fd2017-08-17 19:15:23 +05301601/* Stores plane specific WM parameters */
1602struct skl_wm_params {
1603 bool x_tiled, y_tiled;
1604 bool rc_surface;
1605 uint32_t width;
1606 uint8_t cpp;
1607 uint32_t plane_pixel_rate;
1608 uint32_t y_min_scanlines;
1609 uint32_t plane_bytes_per_line;
1610 uint_fixed_16_16_t plane_blocks_per_line;
1611 uint_fixed_16_16_t y_tile_minimum;
1612 uint32_t linetime_us;
1613};
1614
Paulo Zanonic67a4702013-08-19 13:18:09 -03001615/*
Paulo Zanoni765dab672014-03-07 20:08:18 -03001616 * This struct helps tracking the state needed for runtime PM, which puts the
1617 * device in PCI D3 state. Notice that when this happens, nothing on the
1618 * graphics device works, even register access, so we don't get interrupts nor
1619 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001620 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001621 * Every piece of our code that needs to actually touch the hardware needs to
1622 * either call intel_runtime_pm_get or call intel_display_power_get with the
1623 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001624 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001625 * Our driver uses the autosuspend delay feature, which means we'll only really
1626 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001627 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab672014-03-07 20:08:18 -03001628 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001629 *
1630 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1631 * goes back to false exactly before we reenable the IRQs. We use this variable
1632 * to check if someone is trying to enable/disable IRQs while they're supposed
1633 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001634 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001635 *
Paulo Zanoni765dab672014-03-07 20:08:18 -03001636 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001637 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001638struct i915_runtime_pm {
Imre Deak1f814da2015-12-16 02:52:19 +02001639 atomic_t wakeref_count;
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001640 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001641 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001642};
1643
Daniel Vetter926321d2013-10-16 13:30:34 +02001644enum intel_pipe_crc_source {
1645 INTEL_PIPE_CRC_SOURCE_NONE,
1646 INTEL_PIPE_CRC_SOURCE_PLANE1,
1647 INTEL_PIPE_CRC_SOURCE_PLANE2,
1648 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001649 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001650 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1651 INTEL_PIPE_CRC_SOURCE_TV,
1652 INTEL_PIPE_CRC_SOURCE_DP_B,
1653 INTEL_PIPE_CRC_SOURCE_DP_C,
1654 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001655 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001656 INTEL_PIPE_CRC_SOURCE_MAX,
1657};
1658
Shuang He8bf1e9f2013-10-15 18:55:27 +01001659struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001660 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001661 uint32_t crc[5];
1662};
1663
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001664#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001665struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001666 spinlock_t lock;
1667 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001668 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001669 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001670 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001671 wait_queue_head_t wq;
Tomeu Vizoso8c6b7092017-01-10 14:43:04 +01001672 int skipped;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001673};
1674
Daniel Vetterf99d7062014-06-19 16:01:59 +02001675struct i915_frontbuffer_tracking {
Chris Wilsonb5add952016-08-04 16:32:36 +01001676 spinlock_t lock;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001677
1678 /*
1679 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1680 * scheduled flips.
1681 */
1682 unsigned busy_bits;
1683 unsigned flip_bits;
1684};
1685
Mika Kuoppala72253422014-10-07 17:21:26 +03001686struct i915_wa_reg {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001687 i915_reg_t addr;
Mika Kuoppala72253422014-10-07 17:21:26 +03001688 u32 value;
1689 /* bitmask representing WA bits */
1690 u32 mask;
1691};
1692
Oscar Mateod6242ae2017-10-17 13:27:51 -07001693#define I915_MAX_WA_REGS 16
Mika Kuoppala72253422014-10-07 17:21:26 +03001694
1695struct i915_workarounds {
1696 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1697 u32 count;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001698 u32 hw_whitelist_count[I915_NUM_ENGINES];
Mika Kuoppala72253422014-10-07 17:21:26 +03001699};
1700
Yu Zhangcf9d2892015-02-10 19:05:47 +08001701struct i915_virtual_gpu {
1702 bool active;
Tina Zhang8a4ab662017-08-14 15:20:46 +08001703 u32 caps;
Yu Zhangcf9d2892015-02-10 19:05:47 +08001704};
1705
Matt Roperaa363132015-09-24 15:53:18 -07001706/* used in computing the new watermarks state */
1707struct intel_wm_config {
1708 unsigned int num_pipes_active;
1709 bool sprites_enabled;
1710 bool sprites_scaled;
1711};
1712
Robert Braggd7965152016-11-07 19:49:52 +00001713struct i915_oa_format {
1714 u32 format;
1715 int size;
1716};
1717
Robert Bragg8a3003d2016-11-07 19:49:51 +00001718struct i915_oa_reg {
1719 i915_reg_t addr;
1720 u32 value;
1721};
1722
Lionel Landwerlin701f8232017-08-03 17:58:08 +01001723struct i915_oa_config {
1724 char uuid[UUID_STRING_LEN + 1];
1725 int id;
1726
1727 const struct i915_oa_reg *mux_regs;
1728 u32 mux_regs_len;
1729 const struct i915_oa_reg *b_counter_regs;
1730 u32 b_counter_regs_len;
1731 const struct i915_oa_reg *flex_regs;
1732 u32 flex_regs_len;
1733
1734 struct attribute_group sysfs_metric;
1735 struct attribute *attrs[2];
1736 struct device_attribute sysfs_metric_id;
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001737
1738 atomic_t ref_count;
Lionel Landwerlin701f8232017-08-03 17:58:08 +01001739};
1740
Robert Braggeec688e2016-11-07 19:49:47 +00001741struct i915_perf_stream;
1742
Robert Bragg16d98b32016-12-07 21:40:33 +00001743/**
1744 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1745 */
Robert Braggeec688e2016-11-07 19:49:47 +00001746struct i915_perf_stream_ops {
Robert Bragg16d98b32016-12-07 21:40:33 +00001747 /**
1748 * @enable: Enables the collection of HW samples, either in response to
1749 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1750 * without `I915_PERF_FLAG_DISABLED`.
Robert Braggeec688e2016-11-07 19:49:47 +00001751 */
1752 void (*enable)(struct i915_perf_stream *stream);
1753
Robert Bragg16d98b32016-12-07 21:40:33 +00001754 /**
1755 * @disable: Disables the collection of HW samples, either in response
1756 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1757 * the stream.
Robert Braggeec688e2016-11-07 19:49:47 +00001758 */
1759 void (*disable)(struct i915_perf_stream *stream);
1760
Robert Bragg16d98b32016-12-07 21:40:33 +00001761 /**
1762 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
Robert Braggeec688e2016-11-07 19:49:47 +00001763 * once there is something ready to read() for the stream
1764 */
1765 void (*poll_wait)(struct i915_perf_stream *stream,
1766 struct file *file,
1767 poll_table *wait);
1768
Robert Bragg16d98b32016-12-07 21:40:33 +00001769 /**
1770 * @wait_unlocked: For handling a blocking read, wait until there is
1771 * something to ready to read() for the stream. E.g. wait on the same
Robert Braggd7965152016-11-07 19:49:52 +00001772 * wait queue that would be passed to poll_wait().
Robert Braggeec688e2016-11-07 19:49:47 +00001773 */
1774 int (*wait_unlocked)(struct i915_perf_stream *stream);
1775
Robert Bragg16d98b32016-12-07 21:40:33 +00001776 /**
1777 * @read: Copy buffered metrics as records to userspace
1778 * **buf**: the userspace, destination buffer
1779 * **count**: the number of bytes to copy, requested by userspace
1780 * **offset**: zero at the start of the read, updated as the read
1781 * proceeds, it represents how many bytes have been copied so far and
1782 * the buffer offset for copying the next record.
Robert Braggeec688e2016-11-07 19:49:47 +00001783 *
Robert Bragg16d98b32016-12-07 21:40:33 +00001784 * Copy as many buffered i915 perf samples and records for this stream
1785 * to userspace as will fit in the given buffer.
Robert Braggeec688e2016-11-07 19:49:47 +00001786 *
Robert Bragg16d98b32016-12-07 21:40:33 +00001787 * Only write complete records; returning -%ENOSPC if there isn't room
1788 * for a complete record.
Robert Braggeec688e2016-11-07 19:49:47 +00001789 *
Robert Bragg16d98b32016-12-07 21:40:33 +00001790 * Return any error condition that results in a short read such as
1791 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1792 * returning to userspace.
Robert Braggeec688e2016-11-07 19:49:47 +00001793 */
1794 int (*read)(struct i915_perf_stream *stream,
1795 char __user *buf,
1796 size_t count,
1797 size_t *offset);
1798
Robert Bragg16d98b32016-12-07 21:40:33 +00001799 /**
1800 * @destroy: Cleanup any stream specific resources.
Robert Braggeec688e2016-11-07 19:49:47 +00001801 *
1802 * The stream will always be disabled before this is called.
1803 */
1804 void (*destroy)(struct i915_perf_stream *stream);
1805};
1806
Robert Bragg16d98b32016-12-07 21:40:33 +00001807/**
1808 * struct i915_perf_stream - state for a single open stream FD
1809 */
Robert Braggeec688e2016-11-07 19:49:47 +00001810struct i915_perf_stream {
Robert Bragg16d98b32016-12-07 21:40:33 +00001811 /**
1812 * @dev_priv: i915 drm device
1813 */
Robert Braggeec688e2016-11-07 19:49:47 +00001814 struct drm_i915_private *dev_priv;
1815
Robert Bragg16d98b32016-12-07 21:40:33 +00001816 /**
1817 * @link: Links the stream into ``&drm_i915_private->streams``
1818 */
Robert Braggeec688e2016-11-07 19:49:47 +00001819 struct list_head link;
1820
Robert Bragg16d98b32016-12-07 21:40:33 +00001821 /**
1822 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1823 * properties given when opening a stream, representing the contents
1824 * of a single sample as read() by userspace.
1825 */
Robert Braggeec688e2016-11-07 19:49:47 +00001826 u32 sample_flags;
Robert Bragg16d98b32016-12-07 21:40:33 +00001827
1828 /**
1829 * @sample_size: Considering the configured contents of a sample
1830 * combined with the required header size, this is the total size
1831 * of a single sample record.
1832 */
Robert Braggd7965152016-11-07 19:49:52 +00001833 int sample_size;
Robert Braggeec688e2016-11-07 19:49:47 +00001834
Robert Bragg16d98b32016-12-07 21:40:33 +00001835 /**
1836 * @ctx: %NULL if measuring system-wide across all contexts or a
1837 * specific context that is being monitored.
1838 */
Robert Braggeec688e2016-11-07 19:49:47 +00001839 struct i915_gem_context *ctx;
Robert Bragg16d98b32016-12-07 21:40:33 +00001840
1841 /**
1842 * @enabled: Whether the stream is currently enabled, considering
1843 * whether the stream was opened in a disabled state and based
1844 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1845 */
Robert Braggeec688e2016-11-07 19:49:47 +00001846 bool enabled;
1847
Robert Bragg16d98b32016-12-07 21:40:33 +00001848 /**
1849 * @ops: The callbacks providing the implementation of this specific
1850 * type of configured stream.
1851 */
Robert Braggd7965152016-11-07 19:49:52 +00001852 const struct i915_perf_stream_ops *ops;
Lionel Landwerlin701f8232017-08-03 17:58:08 +01001853
1854 /**
1855 * @oa_config: The OA configuration used by the stream.
1856 */
1857 struct i915_oa_config *oa_config;
Robert Braggd7965152016-11-07 19:49:52 +00001858};
1859
Robert Bragg16d98b32016-12-07 21:40:33 +00001860/**
1861 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1862 */
Robert Braggd7965152016-11-07 19:49:52 +00001863struct i915_oa_ops {
Robert Bragg16d98b32016-12-07 21:40:33 +00001864 /**
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01001865 * @is_valid_b_counter_reg: Validates register's address for
1866 * programming boolean counters for a particular platform.
1867 */
1868 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1869 u32 addr);
1870
1871 /**
1872 * @is_valid_mux_reg: Validates register's address for programming mux
1873 * for a particular platform.
1874 */
1875 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1876
1877 /**
1878 * @is_valid_flex_reg: Validates register's address for programming
1879 * flex EU filtering for a particular platform.
1880 */
1881 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1882
1883 /**
Robert Bragg16d98b32016-12-07 21:40:33 +00001884 * @init_oa_buffer: Resets the head and tail pointers of the
1885 * circular buffer for periodic OA reports.
1886 *
1887 * Called when first opening a stream for OA metrics, but also may be
1888 * called in response to an OA buffer overflow or other error
1889 * condition.
1890 *
1891 * Note it may be necessary to clear the full OA buffer here as part of
1892 * maintaining the invariable that new reports must be written to
1893 * zeroed memory for us to be able to reliable detect if an expected
1894 * report has not yet landed in memory. (At least on Haswell the OA
1895 * buffer tail pointer is not synchronized with reports being visible
1896 * to the CPU)
1897 */
Robert Braggd7965152016-11-07 19:49:52 +00001898 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
Robert Bragg16d98b32016-12-07 21:40:33 +00001899
1900 /**
Robert Bragg19f81df2017-06-13 12:23:03 +01001901 * @enable_metric_set: Selects and applies any MUX configuration to set
1902 * up the Boolean and Custom (B/C) counters that are part of the
1903 * counter reports being sampled. May apply system constraints such as
Robert Bragg16d98b32016-12-07 21:40:33 +00001904 * disabling EU clock gating as required.
1905 */
Lionel Landwerlin701f8232017-08-03 17:58:08 +01001906 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1907 const struct i915_oa_config *oa_config);
Robert Bragg16d98b32016-12-07 21:40:33 +00001908
1909 /**
1910 * @disable_metric_set: Remove system constraints associated with using
1911 * the OA unit.
1912 */
Robert Braggd7965152016-11-07 19:49:52 +00001913 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
Robert Bragg16d98b32016-12-07 21:40:33 +00001914
1915 /**
1916 * @oa_enable: Enable periodic sampling
1917 */
Robert Braggd7965152016-11-07 19:49:52 +00001918 void (*oa_enable)(struct drm_i915_private *dev_priv);
Robert Bragg16d98b32016-12-07 21:40:33 +00001919
1920 /**
1921 * @oa_disable: Disable periodic sampling
1922 */
Robert Braggd7965152016-11-07 19:49:52 +00001923 void (*oa_disable)(struct drm_i915_private *dev_priv);
Robert Bragg16d98b32016-12-07 21:40:33 +00001924
1925 /**
1926 * @read: Copy data from the circular OA buffer into a given userspace
1927 * buffer.
1928 */
Robert Braggd7965152016-11-07 19:49:52 +00001929 int (*read)(struct i915_perf_stream *stream,
1930 char __user *buf,
1931 size_t count,
1932 size_t *offset);
Robert Bragg16d98b32016-12-07 21:40:33 +00001933
1934 /**
Robert Bragg19f81df2017-06-13 12:23:03 +01001935 * @oa_hw_tail_read: read the OA tail pointer register
Robert Bragg16d98b32016-12-07 21:40:33 +00001936 *
Robert Bragg19f81df2017-06-13 12:23:03 +01001937 * In particular this enables us to share all the fiddly code for
1938 * handling the OA unit tail pointer race that affects multiple
1939 * generations.
Robert Bragg16d98b32016-12-07 21:40:33 +00001940 */
Robert Bragg19f81df2017-06-13 12:23:03 +01001941 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
Robert Braggeec688e2016-11-07 19:49:47 +00001942};
1943
Ville Syrjälä49cd97a2017-02-07 20:33:45 +02001944struct intel_cdclk_state {
1945 unsigned int cdclk, vco, ref;
Ville Syrjälä64600bd2017-10-24 12:52:08 +03001946 u8 voltage_level;
Ville Syrjälä49cd97a2017-02-07 20:33:45 +02001947};
1948
Jani Nikula77fec552014-03-31 14:27:22 +03001949struct drm_i915_private {
Chris Wilson8f460e22016-06-24 14:00:18 +01001950 struct drm_device drm;
1951
Chris Wilsonefab6d82015-04-07 16:20:57 +01001952 struct kmem_cache *objects;
Chris Wilsone20d2ab2015-04-07 16:20:58 +01001953 struct kmem_cache *vmas;
Chris Wilsond1b48c12017-08-16 09:52:08 +01001954 struct kmem_cache *luts;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001955 struct kmem_cache *requests;
Chris Wilson52e54202016-11-14 20:41:02 +00001956 struct kmem_cache *dependencies;
Chris Wilsonc5cf9a92017-05-17 13:10:04 +01001957 struct kmem_cache *priorities;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001958
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001959 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001960
Matthew Auld77894222017-12-11 15:18:18 +00001961 /**
1962 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1963 * end of stolen which we can optionally use to create GEM objects
Matthew Auldb1ace602017-12-11 15:18:21 +00001964 * backed by stolen memory. Note that stolen_usable_size tells us
Matthew Auld77894222017-12-11 15:18:18 +00001965 * exactly how much of this we are actually allowed to use, given that
1966 * some portion of it is in fact reserved for use by hardware functions.
1967 */
1968 struct resource dsm;
Matthew Auld17a05342017-12-11 15:18:19 +00001969 /**
1970 * Reseved portion of Data Stolen Memory
1971 */
1972 struct resource dsm_reserved;
Matthew Auld77894222017-12-11 15:18:18 +00001973
Matthew Auldb1ace602017-12-11 15:18:21 +00001974 /*
1975 * Stolen memory is segmented in hardware with different portions
1976 * offlimits to certain functions.
1977 *
1978 * The drm_mm is initialised to the total accessible range, as found
1979 * from the PCI config. On Broadwell+, this is further restricted to
1980 * avoid the first page! The upper end of stolen memory is reserved for
1981 * hardware functions and similarly removed from the accessible range.
1982 */
Matthew Auldb7128ef2017-12-11 15:18:22 +00001983 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
Matthew Auldb1ace602017-12-11 15:18:21 +00001984
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001985 void __iomem *regs;
1986
Chris Wilson907b28c2013-07-19 20:36:52 +01001987 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001988
Yu Zhangcf9d2892015-02-10 19:05:47 +08001989 struct i915_virtual_gpu vgpu;
1990
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +08001991 struct intel_gvt *gvt;
Zhi Wang0ad35fe2016-06-16 08:07:00 -04001992
Anusha Srivatsabd1328582017-01-18 08:05:53 -08001993 struct intel_huc huc;
Alex Dai33a732f2015-08-12 15:43:36 +01001994 struct intel_guc guc;
1995
Daniel Vettereb805622015-05-04 14:58:44 +02001996 struct intel_csr csr;
1997
Jani Nikula5ea6e5e2015-04-01 10:55:04 +03001998 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
Daniel Vetter28c70f12012-12-01 13:53:45 +01001999
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002000 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2001 * controller on different i2c buses. */
2002 struct mutex gmbus_mutex;
2003
2004 /**
2005 * Base address of the gmbus and gpio block.
2006 */
2007 uint32_t gpio_mmio_base;
2008
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05302009 /* MMIO base address for MIPI regs */
2010 uint32_t mipi_mmio_base;
2011
Ville Syrjälä443a3892015-11-11 20:34:15 +02002012 uint32_t psr_mmio_base;
2013
Imre Deak44cb7342016-08-10 14:07:29 +03002014 uint32_t pps_mmio_base;
2015
Daniel Vetter28c70f12012-12-01 13:53:45 +01002016 wait_queue_head_t gmbus_wait_queue;
2017
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002018 struct pci_dev *bridge_dev;
Akash Goel3b3f1652016-10-13 22:44:48 +05302019 struct intel_engine_cs *engine[I915_NUM_ENGINES];
Chris Wilsone7af3112017-10-03 21:34:48 +01002020 /* Context used internally to idle the GPU and setup initial state */
2021 struct i915_gem_context *kernel_context;
2022 /* Context only to be used for injecting preemption commands */
2023 struct i915_gem_context *preempt_context;
Tvrtko Ursulinb46a33e2017-11-21 18:18:45 +00002024 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
2025 [MAX_ENGINE_INSTANCE + 1];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002026
Daniel Vetterba8286f2014-09-11 07:43:25 +02002027 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002028 struct resource mch_res;
2029
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002030 /* protects the irq masks */
2031 spinlock_t irq_lock;
2032
Imre Deakf8b79e52014-03-04 19:23:07 +02002033 bool display_irqs_enabled;
2034
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01002035 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2036 struct pm_qos_request pm_qos;
2037
Ville Syrjäläa5805162015-05-26 20:42:30 +03002038 /* Sideband mailbox protection */
2039 struct mutex sb_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002040
2041 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07002042 union {
2043 u32 irq_mask;
2044 u32 de_irq_mask[I915_MAX_PIPES];
2045 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002046 u32 gt_irq_mask;
Akash Goelf4e9af42016-10-12 21:54:30 +05302047 u32 pm_imr;
2048 u32 pm_ier;
Deepak Sa6706b42014-03-15 20:23:22 +05302049 u32 pm_rps_events;
Sagar Arun Kamble26705e22016-10-12 21:54:31 +05302050 u32 pm_guc_events;
Imre Deak91d181d2014-02-10 18:42:49 +02002051 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002052
Jani Nikula5fcece82015-05-27 15:03:42 +03002053 struct i915_hotplug hotplug;
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02002054 struct intel_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05302055 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002056 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03002057 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002058
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002059 bool preserve_bios_swizzle;
2060
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002061 /* overlay */
2062 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002063
Jani Nikula58c68772013-11-08 16:48:54 +02002064 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02002065 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03002066
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002067 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002068 bool no_aux_handshake;
2069
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002070 /* protects panel power sequencer state */
2071 struct mutex pps_mutex;
2072
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002073 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002074 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2075
2076 unsigned int fsb_freq, mem_freq, is_ddr3;
Ville Syrjäläb2045352016-05-13 23:41:27 +03002077 unsigned int skl_preferred_vco_freq;
Ville Syrjälä49cd97a2017-02-07 20:33:45 +02002078 unsigned int max_cdclk_freq;
Ville Syrjälä8d965612016-11-14 18:35:10 +02002079
Mika Kaholaadafdc62015-08-18 14:36:59 +03002080 unsigned int max_dotclk_freq;
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +02002081 unsigned int rawclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03002082 unsigned int hpll_freq;
Chris Wilson58ecd9d2017-11-05 13:49:05 +00002083 unsigned int fdi_pll_freq;
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03002084 unsigned int czclk_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002085
Ville Syrjälä63911d72016-05-13 23:41:32 +03002086 struct {
Ville Syrjäläbb0f4aa2017-01-20 20:21:59 +02002087 /*
2088 * The current logical cdclk state.
2089 * See intel_atomic_state.cdclk.logical
2090 *
2091 * For reading holding any crtc lock is sufficient,
2092 * for writing must hold all of them.
2093 */
2094 struct intel_cdclk_state logical;
2095 /*
2096 * The current actual cdclk state.
2097 * See intel_atomic_state.cdclk.actual
2098 */
2099 struct intel_cdclk_state actual;
2100 /* The current hardware cdclk state */
Ville Syrjälä49cd97a2017-02-07 20:33:45 +02002101 struct intel_cdclk_state hw;
2102 } cdclk;
Ville Syrjälä63911d72016-05-13 23:41:32 +03002103
Daniel Vetter645416f2013-09-02 16:22:25 +02002104 /**
2105 * wq - Driver workqueue for GEM.
2106 *
2107 * NOTE: Work items scheduled here are not allowed to grab any modeset
2108 * locks, for otherwise the flushing done in the pageflip code will
2109 * result in deadlocks.
2110 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002111 struct workqueue_struct *wq;
2112
2113 /* Display functions */
2114 struct drm_i915_display_funcs display;
2115
2116 /* PCH chipset type */
2117 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002118 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002119
2120 unsigned long quirks;
2121
Zhang Ruib8efb172013-02-05 15:41:53 +08002122 enum modeset_restore modeset_restore;
2123 struct mutex modeset_restore_lock;
Maarten Lankhorste2c8b872016-02-16 10:06:14 +01002124 struct drm_atomic_state *modeset_restore_state;
Maarten Lankhorst73974892016-08-05 23:28:27 +03002125 struct drm_modeset_acquire_ctx reset_ctx;
Eric Anholt673a3942008-07-30 12:06:12 -07002126
Ben Widawskya7bbbd62013-07-16 16:50:07 -07002127 struct list_head vm_list; /* Global list of all address spaces */
Joonas Lahtinen62106b42016-03-18 10:42:57 +02002128 struct i915_ggtt ggtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08002129
Daniel Vetter4b5aed62012-11-14 17:14:03 +01002130 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01002131 DECLARE_HASHTABLE(mm_structs, 7);
2132 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02002133
Zhi Wang43958902017-09-14 20:39:40 +08002134 struct intel_ppat ppat;
2135
Daniel Vetter87813422012-05-02 11:49:32 +02002136 /* Kernel Modesetting */
2137
Ville Syrjäläe2af48c2016-10-31 22:37:05 +02002138 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2139 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002140
Daniel Vetterc4597872013-10-21 21:04:07 +02002141#ifdef CONFIG_DEBUG_FS
2142 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2143#endif
2144
Maarten Lankhorst565602d2015-12-10 12:33:57 +01002145 /* dpll and cdclk state is protected by connection_mutex */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02002146 int num_shared_dpll;
2147 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Ander Conselvan de Oliveiraf9476a62016-03-08 17:46:22 +02002148 const struct intel_dpll_mgr *dpll_mgr;
Maarten Lankhorst565602d2015-12-10 12:33:57 +01002149
Maarten Lankhorstfbf6d872016-03-23 14:51:12 +01002150 /*
2151 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2152 * Must be global rather than per dpll, because on some platforms
2153 * plls share registers.
2154 */
2155 struct mutex dpll_lock;
2156
Maarten Lankhorst565602d2015-12-10 12:33:57 +01002157 unsigned int active_crtcs;
Ville Syrjäläd305e062017-08-30 21:57:03 +03002158 /* minimum acceptable cdclk for each pipe */
2159 int min_cdclk[I915_MAX_PIPES];
Ville Syrjälä53e9bf52017-10-24 12:52:14 +03002160 /* minimum acceptable voltage level for each pipe */
2161 u8 min_voltage_level[I915_MAX_PIPES];
Maarten Lankhorst565602d2015-12-10 12:33:57 +01002162
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002163 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002164
Mika Kuoppala72253422014-10-07 17:21:26 +03002165 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01002166
Daniel Vetterf99d7062014-06-19 16:01:59 +02002167 struct i915_frontbuffer_tracking fb_tracking;
2168
Chris Wilsoneb955ee2017-01-23 21:29:39 +00002169 struct intel_atomic_helper {
2170 struct llist_head free_list;
2171 struct work_struct free_work;
2172 } atomic_helper;
2173
Jesse Barnes652c3932009-08-17 13:31:43 -07002174 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08002175
Zhenyu Wangc48044112009-12-17 14:48:43 +08002176 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08002177
Daniel Vettera4da4fa2012-11-02 19:55:07 +01002178 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02002179
Ben Widawsky59124502013-07-04 11:02:05 -07002180 /* Cannot be determined by PCIID. You must always read a register. */
Mika Kuoppala3accaf72016-04-13 17:26:43 +03002181 u32 edram_cap;
Ben Widawsky59124502013-07-04 11:02:05 -07002182
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01002183 /*
2184 * Protects RPS/RC6 register access and PCU communication.
2185 * Must be taken after struct_mutex if nested. Note that
2186 * this lock may be held for long periods of time when
2187 * talking to hw - so only take it when talking to hw!
2188 */
2189 struct mutex pcu_lock;
2190
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002191 /* gen6+ GT PM state */
2192 struct intel_gen6_power_mgmt gt_pm;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02002193
Daniel Vetter20e4d402012-08-08 23:35:39 +02002194 /* ilk-only ips/rps state. Everything in here is protected by the global
2195 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01002196 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08002197
Imre Deak83c00f52013-10-25 17:36:47 +03002198 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08002199
Rodrigo Vivia031d702013-10-03 16:15:06 -03002200 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03002201
Daniel Vetter99584db2012-11-14 17:14:04 +01002202 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01002203
Jesse Barnesc9cddff2013-05-08 10:45:13 -07002204 struct drm_i915_gem_object *vlv_pctx;
2205
Dave Airlie8be48d92010-03-30 05:34:14 +00002206 /* list of fbdev register on this device */
2207 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01002208 struct work_struct fbdev_suspend_work;
Chris Wilsone953fd72011-02-21 22:23:52 +00002209
2210 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01002211 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07002212
Imre Deak58fddc22015-01-08 17:54:14 +02002213 /* hda/i915 audio component */
David Henningsson51e1d832015-08-19 10:48:56 +02002214 struct i915_audio_component *audio_component;
Imre Deak58fddc22015-01-08 17:54:14 +02002215 bool audio_component_registered;
Libin Yang4a21ef72015-09-02 14:11:39 +08002216 /**
2217 * av_mutex - mutex for audio/video sync
2218 *
2219 */
2220 struct mutex av_mutex;
Imre Deak58fddc22015-01-08 17:54:14 +02002221
Chris Wilson829a0af2017-06-20 12:05:45 +01002222 struct {
2223 struct list_head list;
Chris Wilson5f09a9c2017-06-20 12:05:46 +01002224 struct llist_head free_list;
2225 struct work_struct free_work;
Chris Wilson829a0af2017-06-20 12:05:45 +01002226
2227 /* The hw wants to have a stable context identifier for the
2228 * lifetime of the context (for OA, PASID, faults, etc).
2229 * This is limited in execlists to 21 bits.
2230 */
2231 struct ida hw_ida;
2232#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2233 } contexts;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002234
Damien Lespiau3e683202012-12-11 18:48:29 +00002235 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02002236
Ville Syrjäläc2317752016-03-15 16:39:56 +02002237 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
Ville Syrjälä70722462015-04-10 18:21:28 +03002238 u32 chv_phy_control;
Ville Syrjäläc2317752016-03-15 16:39:56 +02002239 /*
2240 * Shadows for CHV DPLL_MD regs to keep the state
2241 * checker somewhat working in the presence hardware
2242 * crappiness (can't read out DPLL_MD for pipes B & C).
2243 */
2244 u32 chv_dpll_md[I915_MAX_PIPES];
Imre Deakadc7f042016-04-04 17:27:10 +03002245 u32 bxt_phy_grc;
Ville Syrjälä70722462015-04-10 18:21:28 +03002246
Daniel Vetter842f1c82014-03-10 10:01:44 +01002247 u32 suspend_count;
Imre Deakbc872292015-11-18 17:32:30 +02002248 bool suspended_to_idle;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01002249 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03002250 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01002251
Lyude656d1b82016-08-17 15:55:54 -04002252 enum {
Paulo Zanoni16dcdc42016-09-22 18:00:27 -03002253 I915_SAGV_UNKNOWN = 0,
2254 I915_SAGV_DISABLED,
2255 I915_SAGV_ENABLED,
2256 I915_SAGV_NOT_CONTROLLED
2257 } sagv_status;
Lyude656d1b82016-08-17 15:55:54 -04002258
Ville Syrjälä53615a52013-08-01 16:18:50 +03002259 struct {
2260 /*
2261 * Raw watermark latency values:
2262 * in 0.1us units for WM0,
2263 * in 0.5us units for WM1+.
2264 */
2265 /* primary */
2266 uint16_t pri_latency[5];
2267 /* sprite */
2268 uint16_t spr_latency[5];
2269 /* cursor */
2270 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00002271 /*
2272 * Raw watermark memory latency values
2273 * for SKL for all 8 levels
2274 * in 1us units.
2275 */
2276 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03002277
2278 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002279 union {
2280 struct ilk_wm_values hw;
2281 struct skl_wm_values skl_hw;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02002282 struct vlv_wm_values vlv;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03002283 struct g4x_wm_values g4x;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00002284 };
Ville Syrjälä58590c12015-09-08 21:05:12 +03002285
2286 uint8_t max_level;
Matt Ropered4a6a72016-02-23 17:20:13 -08002287
2288 /*
2289 * Should be held around atomic WM register writing; also
2290 * protects * intel_crtc->wm.active and
2291 * cstate->wm.need_postvbl_update.
2292 */
2293 struct mutex wm_mutex;
Matt Roper279e99d2016-05-12 07:06:02 -07002294
2295 /*
2296 * Set during HW readout of watermarks/DDB. Some platforms
2297 * need to know when we're still using BIOS-provided values
2298 * (which we don't fully trust).
2299 */
2300 bool distrust_bios_wm;
Ville Syrjälä53615a52013-08-01 16:18:50 +03002301 } wm;
2302
Sagar Arun Kamblead1443f2017-10-10 22:30:04 +01002303 struct i915_runtime_pm runtime_pm;
Paulo Zanoni8a187452013-12-06 20:32:13 -02002304
Robert Braggeec688e2016-11-07 19:49:47 +00002305 struct {
2306 bool initialized;
Robert Braggd7965152016-11-07 19:49:52 +00002307
Robert Bragg442b8c02016-11-07 19:49:53 +00002308 struct kobject *metrics_kobj;
Robert Braggccdf6342016-11-07 19:49:54 +00002309 struct ctl_table_header *sysctl_header;
Robert Bragg442b8c02016-11-07 19:49:53 +00002310
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01002311 /*
2312 * Lock associated with adding/modifying/removing OA configs
2313 * in dev_priv->perf.metrics_idr.
2314 */
2315 struct mutex metrics_lock;
2316
2317 /*
2318 * List of dynamic configurations, you need to hold
2319 * dev_priv->perf.metrics_lock to access it.
2320 */
2321 struct idr metrics_idr;
2322
2323 /*
2324 * Lock associated with anything below within this structure
2325 * except exclusive_stream.
2326 */
Robert Braggeec688e2016-11-07 19:49:47 +00002327 struct mutex lock;
2328 struct list_head streams;
Robert Bragg8a3003d2016-11-07 19:49:51 +00002329
2330 struct {
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01002331 /*
2332 * The stream currently using the OA unit. If accessed
2333 * outside a syscall associated to its file
2334 * descriptor, you need to hold
2335 * dev_priv->drm.struct_mutex.
2336 */
Robert Braggd7965152016-11-07 19:49:52 +00002337 struct i915_perf_stream *exclusive_stream;
2338
2339 u32 specific_ctx_id;
Robert Braggd7965152016-11-07 19:49:52 +00002340
2341 struct hrtimer poll_check_timer;
2342 wait_queue_head_t poll_wq;
2343 bool pollin;
2344
Robert Bragg712122e2017-05-11 16:43:31 +01002345 /**
2346 * For rate limiting any notifications of spurious
2347 * invalid OA reports
2348 */
2349 struct ratelimit_state spurious_report_rs;
2350
Robert Braggd7965152016-11-07 19:49:52 +00002351 bool periodic;
2352 int period_exponent;
Robert Braggd7965152016-11-07 19:49:52 +00002353
Lionel Landwerlin701f8232017-08-03 17:58:08 +01002354 struct i915_oa_config test_config;
Robert Braggd7965152016-11-07 19:49:52 +00002355
2356 struct {
2357 struct i915_vma *vma;
2358 u8 *vaddr;
Robert Bragg19f81df2017-06-13 12:23:03 +01002359 u32 last_ctx_id;
Robert Braggd7965152016-11-07 19:49:52 +00002360 int format;
2361 int format_size;
Robert Braggf2790202017-05-11 16:43:26 +01002362
2363 /**
Robert Bragg0dd860c2017-05-11 16:43:28 +01002364 * Locks reads and writes to all head/tail state
2365 *
2366 * Consider: the head and tail pointer state
2367 * needs to be read consistently from a hrtimer
2368 * callback (atomic context) and read() fop
2369 * (user context) with tail pointer updates
2370 * happening in atomic context and head updates
2371 * in user context and the (unlikely)
2372 * possibility of read() errors needing to
2373 * reset all head/tail state.
2374 *
2375 * Note: Contention or performance aren't
2376 * currently a significant concern here
2377 * considering the relatively low frequency of
2378 * hrtimer callbacks (5ms period) and that
2379 * reads typically only happen in response to a
2380 * hrtimer event and likely complete before the
2381 * next callback.
2382 *
2383 * Note: This lock is not held *while* reading
2384 * and copying data to userspace so the value
2385 * of head observed in htrimer callbacks won't
2386 * represent any partial consumption of data.
2387 */
2388 spinlock_t ptr_lock;
2389
2390 /**
2391 * One 'aging' tail pointer and one 'aged'
2392 * tail pointer ready to used for reading.
2393 *
2394 * Initial values of 0xffffffff are invalid
2395 * and imply that an update is required
2396 * (and should be ignored by an attempted
2397 * read)
2398 */
2399 struct {
2400 u32 offset;
2401 } tails[2];
2402
2403 /**
2404 * Index for the aged tail ready to read()
2405 * data up to.
2406 */
2407 unsigned int aged_tail_idx;
2408
2409 /**
2410 * A monotonic timestamp for when the current
2411 * aging tail pointer was read; used to
2412 * determine when it is old enough to trust.
2413 */
2414 u64 aging_timestamp;
2415
2416 /**
Robert Braggf2790202017-05-11 16:43:26 +01002417 * Although we can always read back the head
2418 * pointer register, we prefer to avoid
2419 * trusting the HW state, just to avoid any
2420 * risk that some hardware condition could
2421 * somehow bump the head pointer unpredictably
2422 * and cause us to forward the wrong OA buffer
2423 * data to userspace.
2424 */
2425 u32 head;
Robert Braggd7965152016-11-07 19:49:52 +00002426 } oa_buffer;
2427
2428 u32 gen7_latched_oastatus1;
Robert Bragg19f81df2017-06-13 12:23:03 +01002429 u32 ctx_oactxctrl_offset;
2430 u32 ctx_flexeu0_offset;
2431
2432 /**
2433 * The RPT_ID/reason field for Gen8+ includes a bit
2434 * to determine if the CTX ID in the report is valid
2435 * but the specific bit differs between Gen 8 and 9
2436 */
2437 u32 gen8_valid_ctx_bit;
Robert Braggd7965152016-11-07 19:49:52 +00002438
2439 struct i915_oa_ops ops;
2440 const struct i915_oa_format *oa_formats;
Robert Bragg8a3003d2016-11-07 19:49:51 +00002441 } oa;
Robert Braggeec688e2016-11-07 19:49:47 +00002442 } perf;
2443
Oscar Mateoa83014d2014-07-24 17:04:21 +01002444 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2445 struct {
Chris Wilson821ed7d2016-09-09 14:11:53 +01002446 void (*resume)(struct drm_i915_private *);
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00002447 void (*cleanup_engine)(struct intel_engine_cs *engine);
Chris Wilson67d97da2016-07-04 08:08:31 +01002448
Chris Wilson73cb9702016-10-28 13:58:46 +01002449 struct list_head timelines;
2450 struct i915_gem_timeline global_timeline;
Chris Wilson28176ef2016-10-28 13:58:56 +01002451 u32 active_requests;
Chris Wilson73cb9702016-10-28 13:58:46 +01002452
Chris Wilson67d97da2016-07-04 08:08:31 +01002453 /**
2454 * Is the GPU currently considered idle, or busy executing
2455 * userspace requests? Whilst idle, we allow runtime power
2456 * management to power down the hardware and display clocks.
2457 * In order to reduce the effect on performance, there
2458 * is a slight delay before we do so.
2459 */
Chris Wilson67d97da2016-07-04 08:08:31 +01002460 bool awake;
2461
2462 /**
2463 * We leave the user IRQ off as much as possible,
2464 * but this means that requests will finish and never
2465 * be retired once the system goes idle. Set a timer to
2466 * fire periodically while the ring is running. When it
2467 * fires, go retire requests.
2468 */
2469 struct delayed_work retire_work;
2470
2471 /**
2472 * When we detect an idle GPU, we want to turn on
2473 * powersaving features. So once we see that there
2474 * are no more requests outstanding and no more
2475 * arrive within a small period of time, we fire
2476 * off the idle_work.
2477 */
2478 struct delayed_work idle_work;
Chris Wilsonde867c22016-10-25 13:16:02 +01002479
2480 ktime_t last_init_time;
Oscar Mateoa83014d2014-07-24 17:04:21 +01002481 } gt;
2482
Ville Syrjälä3be60de2015-09-08 18:05:45 +03002483 /* perform PHY state sanity checks? */
2484 bool chv_phy_assert[2];
2485
Mahesh Kumara3a89862016-12-01 21:19:34 +05302486 bool ipc_enabled;
2487
Pandiyan, Dhinakaranf9318942016-09-21 13:02:48 -07002488 /* Used to save the pipe-to-encoder mapping for audio */
2489 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
Takashi Iwai0bdf5a02015-11-30 18:19:39 +01002490
Jerome Anandeef57322017-01-25 04:27:49 +05302491 /* necessary resource sharing with HDMI LPE audio driver. */
2492 struct {
2493 struct platform_device *platdev;
2494 int irq;
2495 } lpe_audio;
2496
Tvrtko Ursulinb46a33e2017-11-21 18:18:45 +00002497 struct i915_pmu pmu;
2498
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02002499 /*
2500 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2501 * will be rejected. Instead look for a better place.
2502 */
Jani Nikula77fec552014-03-31 14:27:22 +03002503};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504
Chris Wilson2c1792a2013-08-01 18:39:55 +01002505static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2506{
Chris Wilson091387c2016-06-24 14:00:21 +01002507 return container_of(dev, struct drm_i915_private, drm);
Chris Wilson2c1792a2013-08-01 18:39:55 +01002508}
2509
David Weinehallc49d13e2016-08-22 13:32:42 +03002510static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
Imre Deak888d0d42015-01-08 17:54:13 +02002511{
David Weinehallc49d13e2016-08-22 13:32:42 +03002512 return to_i915(dev_get_drvdata(kdev));
Imre Deak888d0d42015-01-08 17:54:13 +02002513}
2514
Alex Dai33a732f2015-08-12 15:43:36 +01002515static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2516{
2517 return container_of(guc, struct drm_i915_private, guc);
2518}
2519
Arkadiusz Hiler50beba52017-03-14 15:28:06 +01002520static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2521{
2522 return container_of(huc, struct drm_i915_private, huc);
2523}
2524
Dave Gordonb4ac5af2016-03-24 11:20:38 +00002525/* Simple iterator over all initialised engines */
Akash Goel3b3f1652016-10-13 22:44:48 +05302526#define for_each_engine(engine__, dev_priv__, id__) \
2527 for ((id__) = 0; \
2528 (id__) < I915_NUM_ENGINES; \
2529 (id__)++) \
2530 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
Dave Gordonc3232b12016-03-23 18:19:53 +00002531
2532/* Iterator over subset of engines selected by mask */
Chris Wilsonbafb0fc2016-08-27 08:54:01 +01002533#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2534 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
Akash Goel3b3f1652016-10-13 22:44:48 +05302535 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02002536
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08002537enum hdmi_force_audio {
2538 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2539 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2540 HDMI_AUDIO_AUTO, /* trust EDID */
2541 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2542};
2543
Daniel Vetter190d6cd2013-07-04 13:06:28 +02002544#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00002545
Daniel Vettera071fa02014-06-18 23:28:09 +02002546/*
2547 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302548 * considered to be the frontbuffer for the given plane interface-wise. This
Daniel Vettera071fa02014-06-18 23:28:09 +02002549 * doesn't mean that the hw necessarily already scans it out, but that any
2550 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2551 *
2552 * We have one bit per pipe and per scanout plane type.
2553 */
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302554#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2555#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
Daniel Vettera071fa02014-06-18 23:28:09 +02002556#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2557 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2558#define INTEL_FRONTBUFFER_CURSOR(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302559 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2560#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2561 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettera071fa02014-06-18 23:28:09 +02002562#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302563 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02002564#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302565 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02002566
Dave Gordon85d12252016-05-20 11:54:06 +01002567/*
2568 * Optimised SGL iterator for GEM objects
2569 */
2570static __always_inline struct sgt_iter {
2571 struct scatterlist *sgp;
2572 union {
2573 unsigned long pfn;
2574 dma_addr_t dma;
2575 };
2576 unsigned int curr;
2577 unsigned int max;
2578} __sgt_iter(struct scatterlist *sgl, bool dma) {
2579 struct sgt_iter s = { .sgp = sgl };
2580
2581 if (s.sgp) {
2582 s.max = s.curr = s.sgp->offset;
2583 s.max += s.sgp->length;
2584 if (dma)
2585 s.dma = sg_dma_address(s.sgp);
2586 else
2587 s.pfn = page_to_pfn(sg_page(s.sgp));
2588 }
2589
2590 return s;
2591}
2592
Chris Wilson96d77632016-10-28 13:58:33 +01002593static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2594{
2595 ++sg;
2596 if (unlikely(sg_is_chain(sg)))
2597 sg = sg_chain_ptr(sg);
2598 return sg;
2599}
2600
Dave Gordon85d12252016-05-20 11:54:06 +01002601/**
Dave Gordon63d15322016-05-20 11:54:07 +01002602 * __sg_next - return the next scatterlist entry in a list
2603 * @sg: The current sg entry
2604 *
2605 * Description:
2606 * If the entry is the last, return NULL; otherwise, step to the next
2607 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2608 * otherwise just return the pointer to the current element.
2609 **/
2610static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2611{
2612#ifdef CONFIG_DEBUG_SG
2613 BUG_ON(sg->sg_magic != SG_MAGIC);
2614#endif
Chris Wilson96d77632016-10-28 13:58:33 +01002615 return sg_is_last(sg) ? NULL : ____sg_next(sg);
Dave Gordon63d15322016-05-20 11:54:07 +01002616}
2617
2618/**
Dave Gordon85d12252016-05-20 11:54:06 +01002619 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2620 * @__dmap: DMA address (output)
2621 * @__iter: 'struct sgt_iter' (iterator state, internal)
2622 * @__sgt: sg_table to iterate over (input)
2623 */
2624#define for_each_sgt_dma(__dmap, __iter, __sgt) \
2625 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2626 ((__dmap) = (__iter).dma + (__iter).curr); \
Chris Wilsone60b36f2017-09-13 11:57:54 +01002627 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2628 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
Dave Gordon85d12252016-05-20 11:54:06 +01002629
2630/**
2631 * for_each_sgt_page - iterate over the pages of the given sg_table
2632 * @__pp: page pointer (output)
2633 * @__iter: 'struct sgt_iter' (iterator state, internal)
2634 * @__sgt: sg_table to iterate over (input)
2635 */
2636#define for_each_sgt_page(__pp, __iter, __sgt) \
2637 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2638 ((__pp) = (__iter).pfn == 0 ? NULL : \
2639 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
Chris Wilsone60b36f2017-09-13 11:57:54 +01002640 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2641 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
Daniel Vettera071fa02014-06-18 23:28:09 +02002642
Matthew Aulda5c081662017-10-06 23:18:18 +01002643static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2644{
2645 unsigned int page_sizes;
2646
2647 page_sizes = 0;
2648 while (sg) {
2649 GEM_BUG_ON(sg->offset);
2650 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2651 page_sizes |= sg->length;
2652 sg = __sg_next(sg);
2653 }
2654
2655 return page_sizes;
2656}
2657
Tvrtko Ursulin56024522017-08-03 10:14:17 +01002658static inline unsigned int i915_sg_segment_size(void)
2659{
2660 unsigned int size = swiotlb_max_segment();
2661
2662 if (size == 0)
2663 return SCATTERLIST_MAX_SEGMENT;
2664
2665 size = rounddown(size, PAGE_SIZE);
2666 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2667 if (size < PAGE_SIZE)
2668 size = PAGE_SIZE;
2669
2670 return size;
2671}
2672
Tvrtko Ursulin5ca43ef2016-11-16 08:55:45 +00002673static inline const struct intel_device_info *
2674intel_info(const struct drm_i915_private *dev_priv)
2675{
2676 return &dev_priv->info;
2677}
2678
2679#define INTEL_INFO(dev_priv) intel_info((dev_priv))
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002680
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +01002681#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002682#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
Zou Nan haicae58522010-11-09 17:17:32 +08002683
Jani Nikulae87a0052015-10-20 15:22:02 +03002684#define REVID_FOREVER 0xff
Tvrtko Ursulin4805fe82016-11-04 14:42:46 +00002685#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
Tvrtko Ursulinac657f62016-05-10 10:57:08 +01002686
2687#define GEN_FOREVER (0)
Joonas Lahtinenfe52e592017-09-13 14:52:54 +03002688
2689#define INTEL_GEN_MASK(s, e) ( \
2690 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2691 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2692 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2693 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2694)
2695
Tvrtko Ursulinac657f62016-05-10 10:57:08 +01002696/*
2697 * Returns true if Gen is in inclusive range [Start, End].
2698 *
2699 * Use GEN_FOREVER for unbound start and or end.
2700 */
Joonas Lahtinenfe52e592017-09-13 14:52:54 +03002701#define IS_GEN(dev_priv, s, e) \
2702 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
Tvrtko Ursulinac657f62016-05-10 10:57:08 +01002703
Jani Nikulae87a0052015-10-20 15:22:02 +03002704/*
2705 * Return true if revision is in range [since,until] inclusive.
2706 *
2707 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2708 */
2709#define IS_REVID(p, since, until) \
2710 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2711
Tvrtko Ursulinae7617f2017-09-27 17:41:38 +01002712#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
Tvrtko Ursulin5a127a82017-09-20 10:26:59 +01002713
2714#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2715#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2716#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2717#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2718#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2719#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2720#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2721#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2722#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2723#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2724#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2725#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
Jani Nikulaf69c11a2016-11-30 17:43:05 +02002726#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002727#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2728#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
Tvrtko Ursulin5a127a82017-09-20 10:26:59 +01002729#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2730#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002731#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
Tvrtko Ursulin5a127a82017-09-20 10:26:59 +01002732#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002733#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2734 (dev_priv)->info.gt == 1)
Tvrtko Ursulin5a127a82017-09-20 10:26:59 +01002735#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2736#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2737#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2738#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2739#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2740#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2741#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2742#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2743#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2744#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
Ville Syrjälä646d5772016-10-31 22:37:14 +02002745#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002746#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2747 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2748#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2749 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2750 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2751 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
Ville Syrjäläebb72aa2015-06-03 15:45:12 +03002752/* ULX machines are also considered ULT. */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002753#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2754 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2755#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002756 (dev_priv)->info.gt == 3)
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002757#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2758 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2759#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002760 (dev_priv)->info.gt == 3)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002761/* ULX machines are also considered ULT. */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002762#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2763 INTEL_DEVID(dev_priv) == 0x0A1E)
2764#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2765 INTEL_DEVID(dev_priv) == 0x1913 || \
2766 INTEL_DEVID(dev_priv) == 0x1916 || \
2767 INTEL_DEVID(dev_priv) == 0x1921 || \
2768 INTEL_DEVID(dev_priv) == 0x1926)
2769#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2770 INTEL_DEVID(dev_priv) == 0x1915 || \
2771 INTEL_DEVID(dev_priv) == 0x191E)
2772#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2773 INTEL_DEVID(dev_priv) == 0x5913 || \
2774 INTEL_DEVID(dev_priv) == 0x5916 || \
2775 INTEL_DEVID(dev_priv) == 0x5921 || \
2776 INTEL_DEVID(dev_priv) == 0x5926)
2777#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2778 INTEL_DEVID(dev_priv) == 0x5915 || \
2779 INTEL_DEVID(dev_priv) == 0x591E)
Robert Bragg19f81df2017-06-13 12:23:03 +01002780#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002781 (dev_priv)->info.gt == 2)
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002782#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002783 (dev_priv)->info.gt == 3)
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002784#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002785 (dev_priv)->info.gt == 4)
Lionel Landwerlin38915892017-06-13 12:23:07 +01002786#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002787 (dev_priv)->info.gt == 2)
Lionel Landwerlin38915892017-06-13 12:23:07 +01002788#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
Lionel Landwerlin18b53812017-08-30 17:12:07 +01002789 (dev_priv)->info.gt == 3)
Rodrigo Vivida411a42017-06-09 15:02:50 -07002790#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2791 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
Lionel Landwerlin22ea4f32017-09-18 12:21:24 +01002792#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2793 (dev_priv)->info.gt == 2)
Lionel Landwerlin4407eaa2017-11-10 19:08:40 +00002794#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2795 (dev_priv)->info.gt == 3)
Sagar Arun Kamble7a58bad2015-09-12 10:17:50 +05302796
Jani Nikulac007fb42016-10-31 12:18:28 +02002797#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
Zou Nan haicae58522010-11-09 17:17:32 +08002798
Jani Nikulaef712bb2015-10-20 15:22:00 +03002799#define SKL_REVID_A0 0x0
2800#define SKL_REVID_B0 0x1
2801#define SKL_REVID_C0 0x2
2802#define SKL_REVID_D0 0x3
2803#define SKL_REVID_E0 0x4
2804#define SKL_REVID_F0 0x5
Mika Kuoppala4ba9c1f2016-07-20 14:26:12 +03002805#define SKL_REVID_G0 0x6
2806#define SKL_REVID_H0 0x7
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002807
Jani Nikulae87a0052015-10-20 15:22:02 +03002808#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2809
Jani Nikulaef712bb2015-10-20 15:22:00 +03002810#define BXT_REVID_A0 0x0
Jani Nikulafffda3f2015-10-20 15:22:01 +03002811#define BXT_REVID_A1 0x1
Jani Nikulaef712bb2015-10-20 15:22:00 +03002812#define BXT_REVID_B0 0x3
Ander Conselvan de Oliveiraa3f79ca2016-11-24 15:23:27 +02002813#define BXT_REVID_B_LAST 0x8
Jani Nikulaef712bb2015-10-20 15:22:00 +03002814#define BXT_REVID_C0 0x9
Nick Hoath6c74c872015-03-20 09:03:52 +00002815
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +01002816#define IS_BXT_REVID(dev_priv, since, until) \
2817 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
Jani Nikulae87a0052015-10-20 15:22:02 +03002818
Mika Kuoppalac033a372016-06-07 17:18:55 +03002819#define KBL_REVID_A0 0x0
2820#define KBL_REVID_B0 0x1
Mika Kuoppalafe905812016-06-07 17:19:03 +03002821#define KBL_REVID_C0 0x2
2822#define KBL_REVID_D0 0x3
2823#define KBL_REVID_E0 0x4
Mika Kuoppalac033a372016-06-07 17:18:55 +03002824
Tvrtko Ursulin08537232016-10-13 11:03:02 +01002825#define IS_KBL_REVID(dev_priv, since, until) \
2826 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
Mika Kuoppalac033a372016-06-07 17:18:55 +03002827
Ander Conselvan de Oliveiraf4f4b592017-02-22 08:34:29 +02002828#define GLK_REVID_A0 0x0
2829#define GLK_REVID_A1 0x1
2830
2831#define IS_GLK_REVID(dev_priv, since, until) \
2832 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2833
Paulo Zanoni3c2e0fd2017-06-06 13:30:34 -07002834#define CNL_REVID_A0 0x0
2835#define CNL_REVID_B0 0x1
Rodrigo Vivie4ffc832017-08-22 16:58:28 -07002836#define CNL_REVID_C0 0x2
Paulo Zanoni3c2e0fd2017-06-06 13:30:34 -07002837
2838#define IS_CNL_REVID(p, since, until) \
2839 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2840
Jesse Barnes85436692011-04-06 12:11:14 -07002841/*
2842 * The genX designation typically refers to the render engine, so render
2843 * capability related checks should use IS_GEN, while display and other checks
2844 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2845 * chips, etc.).
2846 */
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01002847#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2848#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2849#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2850#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2851#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2852#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2853#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2854#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
Rodrigo Vivi413f3c12017-06-06 13:30:30 -07002855#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
Zou Nan haicae58522010-11-09 17:17:32 +08002856
Rodrigo Vivi8727dc02016-12-18 13:36:26 -08002857#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
Rodrigo Vivib976dc52017-01-23 10:32:37 -08002858#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2859#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
Ander Conselvan de Oliveira3e4274f2016-11-10 17:23:09 +02002860
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01002861#define ENGINE_MASK(id) BIT(id)
2862#define RENDER_RING ENGINE_MASK(RCS)
2863#define BSD_RING ENGINE_MASK(VCS)
2864#define BLT_RING ENGINE_MASK(BCS)
2865#define VEBOX_RING ENGINE_MASK(VECS)
2866#define BSD2_RING ENGINE_MASK(VCS2)
2867#define ALL_ENGINES (~0)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02002868
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01002869#define HAS_ENGINE(dev_priv, id) \
Tvrtko Ursulin0031fb92016-11-04 14:42:44 +00002870 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
Tvrtko Ursulina19d6ff2016-06-23 14:52:41 +01002871
2872#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2873#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2874#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2875#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2876
Chris Wilson93c6e962017-11-20 20:55:04 +00002877#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2878
Tvrtko Ursulin0031fb92016-11-04 14:42:44 +00002879#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2880#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2881#define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
Tvrtko Ursulin86527442016-10-13 11:03:00 +01002882#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2883 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
Zou Nan haicae58522010-11-09 17:17:32 +08002884
Tvrtko Ursulin0031fb92016-11-04 14:42:44 +00002885#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002886
Tvrtko Ursulin0031fb92016-11-04 14:42:44 +00002887#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2888 ((dev_priv)->info.has_logical_ring_contexts)
Michał Winiarskia4598d12017-10-25 22:00:18 +02002889#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2890 ((dev_priv)->info.has_logical_ring_preemption)
Chris Wilsonfb5c5512017-11-20 20:55:00 +00002891
2892#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2893
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00002894#define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2895#define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2896#define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
Matthew Aulda5c081662017-10-06 23:18:18 +01002897#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2898 GEM_BUG_ON((sizes) == 0); \
2899 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2900})
Tvrtko Ursulin0031fb92016-11-04 14:42:44 +00002901
2902#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2903#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2904 ((dev_priv)->info.overlay_needs_physical)
Zou Nan haicae58522010-11-09 17:17:32 +08002905
Daniel Vetterb45305f2012-12-17 16:21:27 +01002906/* Early gen2 have a totally busted CS tlb and require pinned batches. */
Jani Nikula2a307c22016-11-30 17:43:04 +02002907#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
Mika Kuoppala06e668a2015-12-16 19:18:37 +02002908
2909/* WaRsDisableCoarsePowerGating:skl,bxt */
Tvrtko Ursulin61251512016-06-21 15:07:14 +01002910#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
Jani Nikulaf2254d22017-02-15 17:21:39 +02002911 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
Mika Kuoppala185c66e2016-04-05 15:56:16 +03002912
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002913/*
2914 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2915 * even when in MSI mode. This results in spurious interrupt warnings if the
2916 * legacy irq no. is shared with another device. The kernel then disables that
2917 * interrupt source and so prevents the other device from working properly.
Ville Syrjälä309bd8e2017-08-18 21:37:05 +03002918 *
2919 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
2920 * interrupts.
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002921 */
Ville Syrjälä309bd8e2017-08-18 21:37:05 +03002922#define HAS_AUX_IRQ(dev_priv) true
2923#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002924
Zou Nan haicae58522010-11-09 17:17:32 +08002925/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2926 * rows, which changed the alignment requirements and fence programming.
2927 */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002928#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2929 !(IS_I915G(dev_priv) || \
2930 IS_I915GM(dev_priv)))
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00002931#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2932#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002933
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00002934#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00002935#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
Ville Syrjälä024faac2017-03-27 21:55:42 +03002936#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
Zou Nan haicae58522010-11-09 17:17:32 +08002937
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01002938#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002939
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00002940#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
Jani Nikula0c9b3712015-05-18 17:10:01 +03002941
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00002942#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2943#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2944#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
Chris Wilsonfb6db0f2017-12-01 11:30:30 +00002945
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00002946#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2947#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
Chris Wilsonfb6db0f2017-12-01 11:30:30 +00002948#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002949
Tvrtko Ursulin56b857a2016-11-07 09:29:20 +00002950#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
Daniel Vettereb805622015-05-04 14:58:44 +02002951
Tvrtko Ursulin6772ffe2016-10-13 11:02:55 +01002952#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
Joonas Lahtinendfc51482016-11-03 10:39:46 +02002953#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2954
Mahesh Kumare57f1c022017-08-17 19:15:27 +05302955#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2956
Dave Gordon1a3d1892016-05-13 15:36:30 +01002957/*
2958 * For now, anything with a GuC requires uCode loading, and then supports
2959 * command submission once loaded. But these are logically independent
2960 * properties, so we have separate macros to test them.
2961 */
Tvrtko Ursulin4805fe82016-11-04 14:42:46 +00002962#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
Michal Wajdeczkof8a58d62017-05-26 11:13:25 +00002963#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
Tvrtko Ursulin4805fe82016-11-04 14:42:46 +00002964#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2965#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
Michal Wajdeczko2fe2d4e2017-12-06 13:53:10 +00002966
2967/* For now, anything with a GuC has also HuC */
2968#define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
Anusha Srivatsabd1328582017-01-18 08:05:53 -08002969#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
Alex Dai33a732f2015-08-12 15:43:36 +01002970
Michal Wajdeczko93ffbe82017-12-06 13:53:12 +00002971/* Having a GuC is not the same as using a GuC */
Michal Wajdeczko121981f2017-12-06 13:53:15 +00002972#define USES_GUC(dev_priv) intel_uc_is_using_guc()
2973#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2974#define USES_HUC(dev_priv) intel_uc_is_using_huc()
Michal Wajdeczko93ffbe82017-12-06 13:53:12 +00002975
Tvrtko Ursulin4805fe82016-11-04 14:42:46 +00002976#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
Abdiel Janulguea9ed33c2015-07-01 10:12:23 +03002977
Tvrtko Ursulin4805fe82016-11-04 14:42:46 +00002978#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
arun.siluvery@linux.intel.com33e141e2016-06-03 06:34:33 +01002979
Ville Syrjäläc5e855d2017-06-21 20:49:44 +03002980#define INTEL_PCH_DEVICE_ID_MASK 0xff80
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002981#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2982#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2983#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2984#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2985#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Ville Syrjäläc5e855d2017-06-21 20:49:44 +03002986#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2987#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302988#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2989#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Ville Syrjäläc5e855d2017-06-21 20:49:44 +03002990#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
Rodrigo Vivi7b22b8c2017-06-02 13:06:39 -07002991#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
Dhinakaran Pandiyanec7e0bb2017-06-02 13:06:40 -07002992#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
Robert Beckett30c964a2015-08-28 13:10:22 +01002993#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
Jesse Barnes1844a662016-03-16 13:31:30 -07002994#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
Gerd Hoffmann39bfcd522015-11-26 12:03:51 +01002995#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002996
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01002997#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
Rodrigo Vivi7b22b8c2017-06-02 13:06:39 -07002998#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
Dhinakaran Pandiyanec7e0bb2017-06-02 13:06:40 -07002999#define HAS_PCH_CNP_LP(dev_priv) \
3000 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01003001#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3002#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3003#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
Tvrtko Ursulin4f8036a2016-10-13 11:02:52 +01003004#define HAS_PCH_LPT_LP(dev_priv) \
Ville Syrjäläc5e855d2017-06-21 20:49:44 +03003005 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3006 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
Tvrtko Ursulin4f8036a2016-10-13 11:02:52 +01003007#define HAS_PCH_LPT_H(dev_priv) \
Ville Syrjäläc5e855d2017-06-21 20:49:44 +03003008 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3009 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
Tvrtko Ursulin6e266952016-10-13 11:02:53 +01003010#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3011#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3012#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3013#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08003014
Tvrtko Ursulin49cff962016-10-13 11:02:54 +01003015#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
Sonika Jindal5fafe292014-07-21 15:23:38 +05303016
Rodrigo Viviff159472017-06-09 15:26:14 -07003017#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
Shashank Sharma6389dd82016-10-14 19:56:50 +05303018
Ben Widawsky040d2ba2013-09-19 11:01:40 -07003019/* DPF == dynamic parity feature */
Tvrtko Ursulin3c9192b2016-10-13 11:03:05 +01003020#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +01003021#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3022 2 : HAS_L3_DPF(dev_priv))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07003023
Ben Widawskyc8735b02012-09-07 19:43:39 -07003024#define GT_FREQUENCY_MULTIPLIER 50
Akash Goelde43ae92015-03-06 11:07:14 +05303025#define GEN9_FREQ_SCALER 3
Ben Widawskyc8735b02012-09-07 19:43:39 -07003026
Chris Wilson05394f32010-11-08 19:18:58 +00003027#include "i915_trace.h"
3028
Chris Wilson80debff2017-05-25 13:16:12 +01003029static inline bool intel_vtd_active(void)
Chris Wilson48f112f2016-06-24 14:07:14 +01003030{
3031#ifdef CONFIG_INTEL_IOMMU
Chris Wilson80debff2017-05-25 13:16:12 +01003032 if (intel_iommu_gfx_mapped)
Chris Wilson48f112f2016-06-24 14:07:14 +01003033 return true;
3034#endif
3035 return false;
3036}
3037
Chris Wilson80debff2017-05-25 13:16:12 +01003038static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
3039{
3040 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
3041}
3042
Jon Bloomfield0ef34ad2017-05-24 08:54:11 -07003043static inline bool
3044intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
3045{
Chris Wilson80debff2017-05-25 13:16:12 +01003046 return IS_BROXTON(dev_priv) && intel_vtd_active();
Jon Bloomfield0ef34ad2017-05-24 08:54:11 -07003047}
3048
Chris Wilsonc0336662016-05-06 15:40:21 +01003049int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
David Weinehall351c3b52016-08-22 13:32:41 +03003050 int enable_ppgtt);
Chris Wilson0e4ca102016-04-29 13:18:22 +01003051
Chris Wilson0673ad42016-06-24 14:00:22 +01003052/* i915_drv.c */
Imre Deakd15d7532016-03-18 10:46:10 +02003053void __printf(3, 4)
3054__i915_printk(struct drm_i915_private *dev_priv, const char *level,
3055 const char *fmt, ...);
3056
3057#define i915_report_error(dev_priv, fmt, ...) \
3058 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3059
Ben Widawskyc43b5632012-04-16 14:07:40 -07003060#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11003061extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
3062 unsigned long arg);
Jani Nikula55edf412016-11-01 17:40:44 +02003063#else
3064#define i915_compat_ioctl NULL
Ben Widawskyc43b5632012-04-16 14:07:40 -07003065#endif
Jani Nikulaefab0692016-09-15 16:28:54 +03003066extern const struct dev_pm_ops i915_pm_ops;
3067
3068extern int i915_driver_load(struct pci_dev *pdev,
3069 const struct pci_device_id *ent);
3070extern void i915_driver_unload(struct drm_device *dev);
Chris Wilsondc979972016-05-10 14:10:04 +01003071extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3072extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
Chris Wilson535275d2017-07-21 13:32:37 +01003073
3074#define I915_RESET_QUIET BIT(0)
3075extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
3076extern int i915_reset_engine(struct intel_engine_cs *engine,
3077 unsigned int flags);
3078
Michel Thierry142bc7d2017-06-20 10:57:46 +01003079extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
Michel Thierrycb20a3c2017-10-30 11:56:14 -07003080extern int intel_reset_guc(struct drm_i915_private *dev_priv);
Michel Thierry6acbea82017-10-31 15:53:09 -07003081extern int intel_guc_reset_engine(struct intel_guc *guc,
3082 struct intel_engine_cs *engine);
Tomas Elffc0768c2016-03-21 16:26:59 +00003083extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
Mika Kuoppala3ac168a2016-11-01 18:43:03 +02003084extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
Jesse Barnes7648fa92010-05-20 14:28:11 -07003085extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3086extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3087extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3088extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03003089int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Jesse Barnes7648fa92010-05-20 14:28:11 -07003090
Joonas Lahtinen63ffbcd2017-04-28 10:53:36 +03003091int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
Chris Wilsonbb8f0f52017-01-24 11:01:34 +00003092int intel_engines_init(struct drm_i915_private *dev_priv);
3093
Jani Nikula77913b32015-06-18 13:06:16 +03003094/* intel_hotplug.c */
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003095void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3096 u32 pin_mask, u32 long_mask);
Jani Nikula77913b32015-06-18 13:06:16 +03003097void intel_hpd_init(struct drm_i915_private *dev_priv);
3098void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3099void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
Rodrigo Vivi256cfdd2017-08-11 11:26:49 -07003100enum port intel_hpd_pin_to_port(enum hpd_pin pin);
Rodrigo Vivif761bef22017-08-11 11:26:50 -07003101enum hpd_pin intel_hpd_pin(enum port port);
Lyudeb236d7c82016-06-21 17:03:43 -04003102bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3103void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
Jani Nikula77913b32015-06-18 13:06:16 +03003104
Linus Torvalds1da177e2005-04-16 15:20:36 -07003105/* i915_irq.c */
Chris Wilson26a02b82016-07-01 17:23:13 +01003106static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3107{
3108 unsigned long delay;
3109
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00003110 if (unlikely(!i915_modparams.enable_hangcheck))
Chris Wilson26a02b82016-07-01 17:23:13 +01003111 return;
3112
3113 /* Don't continually defer the hangcheck so that it is always run at
3114 * least once after work has been scheduled on any ring. Otherwise,
3115 * we will ignore a hung ring if a second ring is kept busy.
3116 */
3117
3118 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3119 queue_delayed_work(system_long_wq,
3120 &dev_priv->gpu_error.hangcheck_work, delay);
3121}
3122
Mika Kuoppala58174462014-02-25 17:11:26 +02003123__printf(3, 4)
Chris Wilsonc0336662016-05-06 15:40:21 +01003124void i915_handle_error(struct drm_i915_private *dev_priv,
3125 u32 engine_mask,
Mika Kuoppala58174462014-02-25 17:11:26 +02003126 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003127
Daniel Vetterb9632912014-09-30 10:56:44 +02003128extern void intel_irq_init(struct drm_i915_private *dev_priv);
Joonas Lahtinencefcff82017-04-28 10:58:39 +03003129extern void intel_irq_fini(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02003130int intel_irq_install(struct drm_i915_private *dev_priv);
3131void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01003132
Zhi Wang0ad35fe2016-06-16 08:07:00 -04003133static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3134{
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +08003135 return dev_priv->gvt;
Zhi Wang0ad35fe2016-06-16 08:07:00 -04003136}
3137
Chris Wilsonc0336662016-05-06 15:40:21 +01003138static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
Yu Zhangcf9d2892015-02-10 19:05:47 +08003139{
Chris Wilsonc0336662016-05-06 15:40:21 +01003140 return dev_priv->vgpu.active;
Yu Zhangcf9d2892015-02-10 19:05:47 +08003141}
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003142
Ville Syrjälä6b12ca52017-09-14 18:17:31 +03003143u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
3144 enum pipe pipe);
Keith Packard7c463582008-11-04 02:03:27 -08003145void
Jani Nikula50227e12014-03-31 14:27:21 +03003146i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02003147 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08003148
3149void
Jani Nikula50227e12014-03-31 14:27:21 +03003150i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02003151 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08003152
Imre Deakf8b79e52014-03-04 19:23:07 +02003153void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3154void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Egbert Eich0706f172015-09-23 16:15:27 +02003155void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3156 uint32_t mask,
3157 uint32_t bits);
Ville Syrjäläfbdedaea2015-11-23 18:06:16 +02003158void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3159 uint32_t interrupt_mask,
3160 uint32_t enabled_irq_mask);
3161static inline void
3162ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3163{
3164 ilk_update_display_irq(dev_priv, bits, bits);
3165}
3166static inline void
3167ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3168{
3169 ilk_update_display_irq(dev_priv, bits, 0);
3170}
Ville Syrjälä013d3752015-11-23 18:06:17 +02003171void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3172 enum pipe pipe,
3173 uint32_t interrupt_mask,
3174 uint32_t enabled_irq_mask);
3175static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3176 enum pipe pipe, uint32_t bits)
3177{
3178 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3179}
3180static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3181 enum pipe pipe, uint32_t bits)
3182{
3183 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3184}
Daniel Vetter47339cd2014-09-30 10:56:46 +02003185void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3186 uint32_t interrupt_mask,
3187 uint32_t enabled_irq_mask);
Ville Syrjälä14443262015-11-23 18:06:15 +02003188static inline void
3189ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3190{
3191 ibx_display_interrupt_update(dev_priv, bits, bits);
3192}
3193static inline void
3194ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3195{
3196 ibx_display_interrupt_update(dev_priv, bits, 0);
3197}
3198
Eric Anholt673a3942008-07-30 12:06:12 -07003199/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07003200int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3201 struct drm_file *file_priv);
3202int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3203 struct drm_file *file_priv);
3204int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3205 struct drm_file *file_priv);
3206int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3207 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08003208int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3209 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07003210int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3211 struct drm_file *file_priv);
3212int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3213 struct drm_file *file_priv);
3214int i915_gem_execbuffer(struct drm_device *dev, void *data,
3215 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003216int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3217 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07003218int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3219 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07003220int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3221 struct drm_file *file);
3222int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3223 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003224int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3225 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01003226int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3227 struct drm_file *file_priv);
Chris Wilson111dbca2017-01-10 12:10:44 +00003228int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3229 struct drm_file *file_priv);
3230int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3231 struct drm_file *file_priv);
Chris Wilson8a2421b2017-06-16 15:05:22 +01003232int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3233void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01003234int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3235 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07003236int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3237 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07003238int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3239 struct drm_file *file_priv);
Chris Wilson24145512017-01-24 11:01:35 +00003240void i915_gem_sanitize(struct drm_i915_private *i915);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +00003241int i915_gem_load_init(struct drm_i915_private *dev_priv);
3242void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
Imre Deak40ae4e12016-03-16 14:54:03 +02003243void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
Chris Wilson6a800ea2016-09-21 14:51:07 +01003244int i915_gem_freeze(struct drm_i915_private *dev_priv);
Chris Wilson461fb992016-05-14 07:26:33 +01003245int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3246
Tvrtko Ursulin187685c2016-12-01 14:16:36 +00003247void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
Chris Wilson42dcedd2012-11-15 11:32:30 +00003248void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01003249void i915_gem_object_init(struct drm_i915_gem_object *obj,
3250 const struct drm_i915_gem_object_ops *ops);
Tvrtko Ursulin12d79d72016-12-01 14:16:37 +00003251struct drm_i915_gem_object *
3252i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3253struct drm_i915_gem_object *
3254i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3255 const void *data, size_t size);
Chris Wilsonb1f788c2016-08-04 07:52:45 +01003256void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003257void i915_gem_free_object(struct drm_gem_object *obj);
Chris Wilson42dcedd2012-11-15 11:32:30 +00003258
Chris Wilsonbdeb9782016-12-23 14:57:56 +00003259static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3260{
3261 /* A single pass should suffice to release all the freed objects (along
3262 * most call paths) , but be a little more paranoid in that freeing
3263 * the objects does take a little amount of time, during which the rcu
3264 * callbacks could have added new objects into the freed list, and
3265 * armed the work again.
3266 */
3267 do {
3268 rcu_barrier();
3269 } while (flush_work(&i915->mm.free_work));
3270}
3271
Chris Wilson3b19f162017-07-18 14:41:24 +01003272static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
3273{
3274 /*
3275 * Similar to objects above (see i915_gem_drain_freed-objects), in
3276 * general we have workers that are armed by RCU and then rearm
3277 * themselves in their callbacks. To be paranoid, we need to
3278 * drain the workqueue a second time after waiting for the RCU
3279 * grace period so that we catch work queued via RCU from the first
3280 * pass. As neither drain_workqueue() nor flush_workqueue() report
3281 * a result, we make an assumption that we only don't require more
3282 * than 2 passes to catch all recursive RCU delayed work.
3283 *
3284 */
3285 int pass = 2;
3286 do {
3287 rcu_barrier();
3288 drain_workqueue(i915->wq);
3289 } while (--pass);
3290}
3291
Chris Wilson058d88c2016-08-15 10:49:06 +01003292struct i915_vma * __must_check
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003293i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3294 const struct i915_ggtt_view *view,
Chris Wilson91b2db62016-08-04 16:32:23 +01003295 u64 size,
Chris Wilson2ffffd02016-08-04 16:32:22 +01003296 u64 alignment,
3297 u64 flags);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003298
Chris Wilsonaa653a62016-08-04 07:52:27 +01003299int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
Chris Wilson05394f32010-11-08 19:18:58 +00003300void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01003301
Chris Wilson7c108fd2016-10-24 13:42:18 +01003302void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3303
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003304static inline int __sg_page_count(const struct scatterlist *sg)
Chris Wilson9da3da62012-06-01 15:20:22 +01003305{
Chris Wilsonee286372015-04-07 16:20:25 +01003306 return sg->length >> PAGE_SHIFT;
Chris Wilson9da3da62012-06-01 15:20:22 +01003307}
Chris Wilsonee286372015-04-07 16:20:25 +01003308
Chris Wilson96d77632016-10-28 13:58:33 +01003309struct scatterlist *
3310i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3311 unsigned int n, unsigned int *offset);
3312
Dave Gordon033908a2015-12-10 18:51:23 +00003313struct page *
Chris Wilson96d77632016-10-28 13:58:33 +01003314i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3315 unsigned int n);
Dave Gordon033908a2015-12-10 18:51:23 +00003316
Chris Wilson96d77632016-10-28 13:58:33 +01003317struct page *
3318i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3319 unsigned int n);
Chris Wilson341be1c2016-06-10 14:23:00 +05303320
Chris Wilson96d77632016-10-28 13:58:33 +01003321dma_addr_t
3322i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3323 unsigned long n);
Chris Wilsonee286372015-04-07 16:20:25 +01003324
Chris Wilson03ac84f2016-10-28 13:58:36 +01003325void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
Matthew Aulda5c081662017-10-06 23:18:18 +01003326 struct sg_table *pages,
Matthew Auld84e89782017-10-09 12:00:24 +01003327 unsigned int sg_page_sizes);
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003328int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3329
3330static inline int __must_check
3331i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
Chris Wilsona5570172012-09-04 21:02:54 +01003332{
Chris Wilson1233e2d2016-10-28 13:58:37 +01003333 might_lock(&obj->mm.lock);
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003334
Chris Wilson1233e2d2016-10-28 13:58:37 +01003335 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003336 return 0;
3337
3338 return __i915_gem_object_get_pages(obj);
3339}
3340
Chris Wilsonf1fa4f42017-10-13 21:26:13 +01003341static inline bool
3342i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
3343{
3344 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
3345}
3346
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003347static inline void
3348__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3349{
Chris Wilsonf1fa4f42017-10-13 21:26:13 +01003350 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003351
Chris Wilson1233e2d2016-10-28 13:58:37 +01003352 atomic_inc(&obj->mm.pages_pin_count);
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003353}
3354
3355static inline bool
3356i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3357{
Chris Wilson1233e2d2016-10-28 13:58:37 +01003358 return atomic_read(&obj->mm.pages_pin_count);
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003359}
3360
3361static inline void
3362__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3363{
Chris Wilsonf1fa4f42017-10-13 21:26:13 +01003364 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003365 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003366
Chris Wilson1233e2d2016-10-28 13:58:37 +01003367 atomic_dec(&obj->mm.pages_pin_count);
Chris Wilsona5570172012-09-04 21:02:54 +01003368}
Chris Wilson0a798eb2016-04-08 12:11:11 +01003369
Chris Wilson1233e2d2016-10-28 13:58:37 +01003370static inline void
3371i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
Chris Wilsona5570172012-09-04 21:02:54 +01003372{
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003373 __i915_gem_object_unpin_pages(obj);
Chris Wilsona5570172012-09-04 21:02:54 +01003374}
3375
Chris Wilson548625e2016-11-01 12:11:34 +00003376enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3377 I915_MM_NORMAL = 0,
3378 I915_MM_SHRINKER
3379};
3380
3381void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3382 enum i915_mm_subclass subclass);
Chris Wilson03ac84f2016-10-28 13:58:36 +01003383void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
Chris Wilsona4f5ea62016-10-28 13:58:35 +01003384
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003385enum i915_map_type {
3386 I915_MAP_WB = 0,
3387 I915_MAP_WC,
Chris Wilsona575c672017-08-28 11:46:31 +01003388#define I915_MAP_OVERRIDE BIT(31)
3389 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3390 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003391};
3392
Chris Wilson0a798eb2016-04-08 12:11:11 +01003393/**
3394 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
Chris Wilsona73c7a42016-12-31 11:20:10 +00003395 * @obj: the object to map into kernel address space
3396 * @type: the type of mapping, used to select pgprot_t
Chris Wilson0a798eb2016-04-08 12:11:11 +01003397 *
3398 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3399 * pages and then returns a contiguous mapping of the backing storage into
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003400 * the kernel address space. Based on the @type of mapping, the PTE will be
3401 * set to either WriteBack or WriteCombine (via pgprot_t).
Chris Wilson0a798eb2016-04-08 12:11:11 +01003402 *
Chris Wilson1233e2d2016-10-28 13:58:37 +01003403 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3404 * mapping is no longer required.
Chris Wilson0a798eb2016-04-08 12:11:11 +01003405 *
Dave Gordon83052162016-04-12 14:46:16 +01003406 * Returns the pointer through which to access the mapped object, or an
3407 * ERR_PTR() on error.
Chris Wilson0a798eb2016-04-08 12:11:11 +01003408 */
Chris Wilsond31d7cb2016-08-12 12:39:58 +01003409void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3410 enum i915_map_type type);
Chris Wilson0a798eb2016-04-08 12:11:11 +01003411
3412/**
3413 * i915_gem_object_unpin_map - releases an earlier mapping
Chris Wilsona73c7a42016-12-31 11:20:10 +00003414 * @obj: the object to unmap
Chris Wilson0a798eb2016-04-08 12:11:11 +01003415 *
3416 * After pinning the object and mapping its pages, once you are finished
3417 * with your access, call i915_gem_object_unpin_map() to release the pin
3418 * upon the mapping. Once the pin count reaches zero, that mapping may be
3419 * removed.
Chris Wilson0a798eb2016-04-08 12:11:11 +01003420 */
3421static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3422{
Chris Wilson0a798eb2016-04-08 12:11:11 +01003423 i915_gem_object_unpin_pages(obj);
3424}
3425
Chris Wilson43394c72016-08-18 17:16:47 +01003426int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3427 unsigned int *needs_clflush);
3428int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3429 unsigned int *needs_clflush);
Chris Wilson7f5f95d2017-03-10 00:09:42 +00003430#define CLFLUSH_BEFORE BIT(0)
3431#define CLFLUSH_AFTER BIT(1)
3432#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
Chris Wilson43394c72016-08-18 17:16:47 +01003433
3434static inline void
3435i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3436{
3437 i915_gem_object_unpin_pages(obj);
3438}
3439
Chris Wilson54cf91d2010-11-25 18:00:26 +00003440int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawskye2d05a82013-09-24 09:57:58 -07003441void i915_vma_move_to_active(struct i915_vma *vma,
Chris Wilson5cf3d282016-08-04 07:52:43 +01003442 struct drm_i915_gem_request *req,
3443 unsigned int flags);
Dave Airlieff72145b2011-02-07 12:16:14 +10003444int i915_gem_dumb_create(struct drm_file *file_priv,
3445 struct drm_device *dev,
3446 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10003447int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3448 uint32_t handle, uint64_t *offset);
Chris Wilson4cc69072016-08-25 19:05:19 +01003449int i915_gem_mmap_gtt_version(void);
Dave Gordon85d12252016-05-20 11:54:06 +01003450
3451void i915_gem_track_fb(struct drm_i915_gem_object *old,
3452 struct drm_i915_gem_object *new,
3453 unsigned frontbuffer_bits);
3454
Chris Wilson73cb9702016-10-28 13:58:46 +01003455int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003456
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02003457struct drm_i915_gem_request *
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00003458i915_gem_find_active_request(struct intel_engine_cs *engine);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02003459
Chris Wilson67d97da2016-07-04 08:08:31 +01003460void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
Sourab Gupta84c33a62014-06-02 16:47:17 +05303461
Chris Wilson8c185ec2017-03-16 17:13:02 +00003462static inline bool i915_reset_backoff(struct i915_gpu_error *error)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003463{
Chris Wilson8c185ec2017-03-16 17:13:02 +00003464 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3465}
3466
3467static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3468{
3469 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003470}
3471
3472static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3473{
Chris Wilson8af29b02016-09-09 14:11:47 +01003474 return unlikely(test_bit(I915_WEDGED, &error->flags));
3475}
3476
Chris Wilson8c185ec2017-03-16 17:13:02 +00003477static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
Chris Wilson8af29b02016-09-09 14:11:47 +01003478{
Chris Wilson8c185ec2017-03-16 17:13:02 +00003479 return i915_reset_backoff(error) | i915_terminally_wedged(error);
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02003480}
3481
3482static inline u32 i915_reset_count(struct i915_gpu_error *error)
3483{
Chris Wilson8af29b02016-09-09 14:11:47 +01003484 return READ_ONCE(error->reset_count);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003485}
Chris Wilsona71d8d92012-02-15 11:25:36 +00003486
Michel Thierry702c8f82017-06-20 10:57:48 +01003487static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3488 struct intel_engine_cs *engine)
3489{
3490 return READ_ONCE(error->reset_engine_count[engine->id]);
3491}
3492
Michel Thierrya1ef70e2017-06-20 10:57:47 +01003493struct drm_i915_gem_request *
3494i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
Chris Wilson0e178ae2017-01-17 17:59:06 +02003495int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
Chris Wilsond8027092017-02-08 14:30:32 +00003496void i915_gem_reset(struct drm_i915_private *dev_priv);
Michel Thierrya1ef70e2017-06-20 10:57:47 +01003497void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
Chris Wilsonb1ed35d2017-01-04 14:51:10 +00003498void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
Chris Wilson821ed7d2016-09-09 14:11:53 +01003499void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
Chris Wilson2e8f9d32017-03-16 17:13:04 +00003500bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
Michel Thierrya1ef70e2017-06-20 10:57:47 +01003501void i915_gem_reset_engine(struct intel_engine_cs *engine,
3502 struct drm_i915_gem_request *request);
Chris Wilson57822dc2017-02-22 11:40:48 +00003503
Chris Wilson24145512017-01-24 11:01:35 +00003504void i915_gem_init_mmio(struct drm_i915_private *i915);
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00003505int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3506int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
Tvrtko Ursulinc6be6072016-11-16 08:55:31 +00003507void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
Tvrtko Ursulincb15d9f2016-12-01 14:16:39 +00003508void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
Chris Wilson496b5752017-02-13 17:15:58 +00003509int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3510 unsigned int flags);
Tvrtko Ursulinbf9e8422016-12-01 14:16:38 +00003511int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3512void i915_gem_resume(struct drm_i915_private *dev_priv);
Dave Jiang11bac802017-02-24 14:56:41 -08003513int i915_gem_fault(struct vm_fault *vmf);
Chris Wilsone95433c2016-10-28 13:58:27 +01003514int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3515 unsigned int flags,
3516 long timeout,
3517 struct intel_rps_client *rps);
Chris Wilson6b5e90f2016-11-14 20:41:05 +00003518int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3519 unsigned int flags,
3520 int priority);
3521#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3522
Chris Wilson2e2f3512015-04-27 13:41:14 +01003523int __must_check
Chris Wilsone22d8e32017-04-12 12:01:11 +01003524i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3525int __must_check
3526i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
Chris Wilson20217462010-11-23 15:26:33 +00003527int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02003528i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
Chris Wilson058d88c2016-08-15 10:49:06 +01003529struct i915_vma * __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003530i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3531 u32 alignment,
Tvrtko Ursuline6617332015-03-23 11:10:33 +00003532 const struct i915_ggtt_view *view);
Chris Wilson058d88c2016-08-15 10:49:06 +01003533void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
Chris Wilson00731152014-05-21 12:42:56 +01003534int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01003535 int align);
Chris Wilson829a0af2017-06-20 12:05:45 +01003536int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00003537void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003538
Chris Wilsone4ffd172011-04-04 09:44:39 +01003539int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3540 enum i915_cache_level cache_level);
3541
Daniel Vetter1286ff72012-05-10 15:25:09 +02003542struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3543 struct dma_buf *dma_buf);
3544
3545struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3546 struct drm_gem_object *gem_obj, int flags);
3547
Daniel Vetter841cd772014-08-06 15:04:48 +02003548static inline struct i915_hw_ppgtt *
3549i915_vm_to_ppgtt(struct i915_address_space *vm)
3550{
Daniel Vetter841cd772014-08-06 15:04:48 +02003551 return container_of(vm, struct i915_hw_ppgtt, base);
3552}
3553
Joonas Lahtinenb42fe9c2016-11-11 12:43:54 +02003554/* i915_gem_fence_reg.c */
Changbin Du969b0952017-09-04 16:01:01 +08003555struct drm_i915_fence_reg *
3556i915_reserve_fence(struct drm_i915_private *dev_priv);
3557void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
Daniel Vetter41a36b72015-07-24 13:55:11 +02003558
Chris Wilsonb1ed35d2017-01-04 14:51:10 +00003559void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
Tvrtko Ursulin4362f4f2016-11-16 08:55:33 +00003560void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
Daniel Vetter41a36b72015-07-24 13:55:11 +02003561
Tvrtko Ursulin4362f4f2016-11-16 08:55:33 +00003562void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
Chris Wilson03ac84f2016-10-28 13:58:36 +01003563void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3564 struct sg_table *pages);
3565void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3566 struct sg_table *pages);
Daniel Vetter7f96eca2015-07-24 17:40:14 +02003567
Chris Wilsonca585b52016-05-24 14:53:36 +01003568static inline struct i915_gem_context *
Chris Wilson1acfc102017-06-20 12:05:47 +01003569__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3570{
3571 return idr_find(&file_priv->context_idr, id);
3572}
3573
3574static inline struct i915_gem_context *
Chris Wilsonca585b52016-05-24 14:53:36 +01003575i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3576{
3577 struct i915_gem_context *ctx;
3578
Chris Wilson1acfc102017-06-20 12:05:47 +01003579 rcu_read_lock();
3580 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3581 if (ctx && !kref_get_unless_zero(&ctx->ref))
3582 ctx = NULL;
3583 rcu_read_unlock();
Chris Wilsonca585b52016-05-24 14:53:36 +01003584
3585 return ctx;
3586}
3587
Chris Wilson80b204b2016-10-28 13:58:58 +01003588static inline struct intel_timeline *
3589i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3590 struct intel_engine_cs *engine)
3591{
3592 struct i915_address_space *vm;
3593
3594 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3595 return &vm->timeline.engine[engine->id];
3596}
3597
Robert Braggeec688e2016-11-07 19:49:47 +00003598int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3599 struct drm_file *file);
Lionel Landwerlinf89823c2017-08-03 18:05:50 +01003600int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3601 struct drm_file *file);
3602int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3603 struct drm_file *file);
Robert Bragg19f81df2017-06-13 12:23:03 +01003604void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3605 struct i915_gem_context *ctx,
3606 uint32_t *reg_state);
Robert Braggeec688e2016-11-07 19:49:47 +00003607
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003608/* i915_gem_evict.c */
Chris Wilsone522ac22016-08-04 16:32:18 +01003609int __must_check i915_gem_evict_something(struct i915_address_space *vm,
Chris Wilson2ffffd02016-08-04 16:32:22 +01003610 u64 min_size, u64 alignment,
Chris Wilson42d6ab42012-07-26 11:49:32 +01003611 unsigned cache_level,
Chris Wilson2ffffd02016-08-04 16:32:22 +01003612 u64 start, u64 end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003613 unsigned flags);
Chris Wilson625d9882017-01-11 11:23:11 +00003614int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3615 struct drm_mm_node *node,
3616 unsigned int flags);
Chris Wilson2889caa2017-06-16 15:05:19 +01003617int i915_gem_evict_vm(struct i915_address_space *vm);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003618
Chris Wilson71253972017-12-06 12:49:14 +00003619void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3620
Ben Widawsky0260c422014-03-22 22:47:21 -07003621/* belongs in i915_gem_gtt.h */
Chris Wilsonc0336662016-05-06 15:40:21 +01003622static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
Eric Anholt673a3942008-07-30 12:06:12 -07003623{
Chris Wilson600f4362016-08-18 17:16:40 +01003624 wmb();
Chris Wilsonc0336662016-05-06 15:40:21 +01003625 if (INTEL_GEN(dev_priv) < 6)
Eric Anholt673a3942008-07-30 12:06:12 -07003626 intel_gtt_chipset_flush();
3627}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08003628
Chris Wilson9797fbf2012-04-24 15:47:39 +01003629/* i915_gem_stolen.c */
Paulo Zanonid713fd42015-07-02 19:25:07 -03003630int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3631 struct drm_mm_node *node, u64 size,
3632 unsigned alignment);
Paulo Zanonia9da5122015-09-14 15:19:57 -03003633int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3634 struct drm_mm_node *node, u64 size,
3635 unsigned alignment, u64 start,
3636 u64 end);
Paulo Zanonid713fd42015-07-02 19:25:07 -03003637void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3638 struct drm_mm_node *node);
Tvrtko Ursulin7ace3d32016-11-16 08:55:35 +00003639int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003640void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00003641struct drm_i915_gem_object *
Matthew Auldb7128ef2017-12-11 15:18:22 +00003642i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3643 resource_size_t size);
Chris Wilson866d12b2013-02-19 13:31:37 -08003644struct drm_i915_gem_object *
Tvrtko Ursulin187685c2016-12-01 14:16:36 +00003645i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
Matthew Auldb7128ef2017-12-11 15:18:22 +00003646 resource_size_t stolen_offset,
3647 resource_size_t gtt_offset,
3648 resource_size_t size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003649
Chris Wilson920cf412016-10-28 13:58:30 +01003650/* i915_gem_internal.c */
3651struct drm_i915_gem_object *
3652i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
Chris Wilsonfcd46e52017-01-12 13:04:31 +00003653 phys_addr_t size);
Chris Wilson920cf412016-10-28 13:58:30 +01003654
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003655/* i915_gem_shrinker.c */
Chris Wilson56fa4bf2017-11-23 11:53:38 +00003656unsigned long i915_gem_shrink(struct drm_i915_private *i915,
Chris Wilson14387542015-10-01 12:18:25 +01003657 unsigned long target,
Chris Wilson912d5722017-09-06 16:19:30 -07003658 unsigned long *nr_scanned,
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003659 unsigned flags);
3660#define I915_SHRINK_PURGEABLE 0x1
3661#define I915_SHRINK_UNBOUND 0x2
3662#define I915_SHRINK_BOUND 0x4
Chris Wilson5763ff02015-10-01 12:18:29 +01003663#define I915_SHRINK_ACTIVE 0x8
Chris Wilsoneae2c432016-04-08 12:11:12 +01003664#define I915_SHRINK_VMAPS 0x10
Chris Wilson56fa4bf2017-11-23 11:53:38 +00003665unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3666void i915_gem_shrinker_register(struct drm_i915_private *i915);
3667void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003668
3669
Eric Anholt673a3942008-07-30 12:06:12 -07003670/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01003671static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00003672{
Chris Wilson091387c2016-06-24 14:00:21 +01003673 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
Chris Wilsone9b73c62012-12-03 21:03:14 +00003674
3675 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
Chris Wilson3e510a82016-08-05 10:14:23 +01003676 i915_gem_object_is_tiled(obj);
Chris Wilsone9b73c62012-12-03 21:03:14 +00003677}
3678
Chris Wilson91d4e0aa2017-01-09 16:16:13 +00003679u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3680 unsigned int tiling, unsigned int stride);
3681u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3682 unsigned int tiling, unsigned int stride);
3683
Ben Gamari20172632009-02-17 20:08:50 -05003684/* i915_debugfs.c */
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003685#ifdef CONFIG_DEBUG_FS
Chris Wilson1dac8912016-06-24 14:00:17 +01003686int i915_debugfs_register(struct drm_i915_private *dev_priv);
Jani Nikula249e87d2015-04-10 16:59:32 +03003687int i915_debugfs_connector_add(struct drm_connector *connector);
David Weinehall36cdd012016-08-22 13:59:31 +03003688void intel_display_crc_init(struct drm_i915_private *dev_priv);
Damien Lespiau07144422013-10-15 18:55:40 +01003689#else
Chris Wilson8d35acb2016-07-12 12:55:29 +01003690static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
Daniel Vetter101057f2015-07-13 09:23:19 +02003691static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3692{ return 0; }
Maarten Lankhorstce5e2ac2016-08-25 11:07:01 +02003693static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
Damien Lespiau07144422013-10-15 18:55:40 +01003694#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03003695
3696/* i915_gpu_error.c */
Chris Wilson98a2f412016-10-12 10:05:18 +01003697#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3698
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003699__printf(2, 3)
3700void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03003701int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
Chris Wilson5a4c6f12017-02-14 16:46:11 +00003702 const struct i915_gpu_state *gpu);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003703int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003704 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003705 size_t count, loff_t pos);
3706static inline void i915_error_state_buf_release(
3707 struct drm_i915_error_state_buf *eb)
3708{
3709 kfree(eb->buf);
3710}
Chris Wilson5a4c6f12017-02-14 16:46:11 +00003711
3712struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
Chris Wilsonc0336662016-05-06 15:40:21 +01003713void i915_capture_error_state(struct drm_i915_private *dev_priv,
3714 u32 engine_mask,
Mika Kuoppala58174462014-02-25 17:11:26 +02003715 const char *error_msg);
Chris Wilson5a4c6f12017-02-14 16:46:11 +00003716
3717static inline struct i915_gpu_state *
3718i915_gpu_state_get(struct i915_gpu_state *gpu)
3719{
3720 kref_get(&gpu->ref);
3721 return gpu;
3722}
3723
3724void __i915_gpu_state_free(struct kref *kref);
3725static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3726{
3727 if (gpu)
3728 kref_put(&gpu->ref, __i915_gpu_state_free);
3729}
3730
3731struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3732void i915_reset_error_state(struct drm_i915_private *i915);
Mika Kuoppala84734a02013-07-12 16:50:57 +03003733
Chris Wilson98a2f412016-10-12 10:05:18 +01003734#else
3735
3736static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3737 u32 engine_mask,
3738 const char *error_msg)
3739{
3740}
3741
Chris Wilson5a4c6f12017-02-14 16:46:11 +00003742static inline struct i915_gpu_state *
3743i915_first_error_state(struct drm_i915_private *i915)
3744{
3745 return NULL;
3746}
3747
3748static inline void i915_reset_error_state(struct drm_i915_private *i915)
Chris Wilson98a2f412016-10-12 10:05:18 +01003749{
3750}
3751
3752#endif
3753
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003754const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05003755
Brad Volkin351e3db2014-02-18 10:15:46 -08003756/* i915_cmd_parser.c */
Chris Wilson1ca37122016-05-04 14:25:36 +01003757int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
Chris Wilson7756e452016-08-18 17:17:10 +01003758void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
Chris Wilson33a051a2016-07-27 09:07:26 +01003759void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
Chris Wilson33a051a2016-07-27 09:07:26 +01003760int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3761 struct drm_i915_gem_object *batch_obj,
3762 struct drm_i915_gem_object *shadow_batch_obj,
3763 u32 batch_start_offset,
3764 u32 batch_len,
3765 bool is_master);
Brad Volkin351e3db2014-02-18 10:15:46 -08003766
Robert Braggeec688e2016-11-07 19:49:47 +00003767/* i915_perf.c */
3768extern void i915_perf_init(struct drm_i915_private *dev_priv);
3769extern void i915_perf_fini(struct drm_i915_private *dev_priv);
Robert Bragg442b8c02016-11-07 19:49:53 +00003770extern void i915_perf_register(struct drm_i915_private *dev_priv);
3771extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
Robert Braggeec688e2016-11-07 19:49:47 +00003772
Jesse Barnes317c35d2008-08-25 15:11:06 -07003773/* i915_suspend.c */
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +00003774extern int i915_save_state(struct drm_i915_private *dev_priv);
3775extern int i915_restore_state(struct drm_i915_private *dev_priv);
Jesse Barnes317c35d2008-08-25 15:11:06 -07003776
Ben Widawsky0136db52012-04-10 21:17:01 -07003777/* i915_sysfs.c */
David Weinehall694c2822016-08-22 13:32:43 +03003778void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3779void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
Ben Widawsky0136db52012-04-10 21:17:01 -07003780
Jerome Anandeef57322017-01-25 04:27:49 +05303781/* intel_lpe_audio.c */
3782int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3783void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3784void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
Jerome Anand46d196e2017-01-25 04:27:50 +05303785void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
Ville Syrjälä20be5512017-04-27 19:02:26 +03003786 enum pipe pipe, enum port port,
3787 const void *eld, int ls_clock, bool dp_output);
Jerome Anandeef57322017-01-25 04:27:49 +05303788
Chris Wilsonf899fc62010-07-20 15:44:45 -07003789/* intel_i2c.c */
Tvrtko Ursulin40196442016-12-01 14:16:42 +00003790extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3791extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
Jani Nikula88ac7932015-03-27 00:20:22 +02003792extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3793 unsigned int pin);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003794
Jani Nikula0184df42015-03-27 00:20:20 +02003795extern struct i2c_adapter *
3796intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
Chris Wilsone957d772010-09-24 12:52:03 +01003797extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3798extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003799static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01003800{
3801 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3802}
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +00003803extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
Chris Wilsonf899fc62010-07-20 15:44:45 -07003804
Jani Nikula8b8e1a82015-12-14 12:50:49 +02003805/* intel_bios.c */
Jani Nikula66578852017-03-10 15:27:57 +02003806void intel_bios_init(struct drm_i915_private *dev_priv);
Jani Nikulaf0067a32015-12-15 13:16:15 +02003807bool intel_bios_is_valid_vbt(const void *buf, size_t size);
Jani Nikula3bdd14d2016-03-16 12:43:29 +02003808bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
Jani Nikula5a69d132016-03-16 12:43:30 +02003809bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
Ville Syrjälä22f350422016-06-03 12:17:43 +03003810bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
Jani Nikula951d9ef2016-03-16 12:43:31 +02003811bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
Ville Syrjäläd6199252016-05-04 14:45:22 +03003812bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
Jani Nikula7137aec2016-03-16 12:43:32 +02003813bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
Shubhangi Shrivastavad252bf62016-03-31 16:11:47 +05303814bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3815 enum port port);
Shashank Sharma6389dd82016-10-14 19:56:50 +05303816bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3817 enum port port);
3818
Jani Nikula8b8e1a82015-12-14 12:50:49 +02003819
Chris Wilson3b617962010-08-24 09:02:58 +01003820/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01003821#ifdef CONFIG_ACPI
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003822extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
Chris Wilson03d92e42016-05-23 15:08:10 +01003823extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3824extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003825extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003826extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3827 bool enable);
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003828extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003829 pci_power_t state);
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003830extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
Len Brown65e082c2008-10-24 17:18:10 -04003831#else
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003832static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
Randy Dunlapbdaa2df2016-06-27 14:53:19 +03003833static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3834static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003835static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3836{
3837}
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003838static inline int
3839intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3840{
3841 return 0;
3842}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003843static inline int
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003844intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003845{
3846 return 0;
3847}
Chris Wilson6f9f4b72016-05-23 15:08:09 +01003848static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
Ville Syrjäläa0562812016-04-11 10:23:51 +03003849{
3850 return -ENODEV;
3851}
Len Brown65e082c2008-10-24 17:18:10 -04003852#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01003853
Jesse Barnes723bfd72010-10-07 16:01:13 -07003854/* intel_acpi.c */
3855#ifdef CONFIG_ACPI
3856extern void intel_register_dsm_handler(void);
3857extern void intel_unregister_dsm_handler(void);
3858#else
3859static inline void intel_register_dsm_handler(void) { return; }
3860static inline void intel_unregister_dsm_handler(void) { return; }
3861#endif /* CONFIG_ACPI */
3862
Chris Wilson94b4f3b2016-07-05 10:40:20 +01003863/* intel_device_info.c */
3864static inline struct intel_device_info *
3865mkwrite_device_info(struct drm_i915_private *dev_priv)
3866{
3867 return (struct intel_device_info *)&dev_priv->info;
3868}
3869
Jani Nikula2e0d26f2016-12-01 14:49:55 +02003870const char *intel_platform_name(enum intel_platform platform);
Chris Wilson94b4f3b2016-07-05 10:40:20 +01003871void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
Michal Wajdeczkoeb10ed92017-12-19 11:43:45 +00003872void intel_device_info_dump(const struct intel_device_info *info,
3873 struct drm_printer *p);
Michal Wajdeczkoa8c9b842017-12-19 11:43:44 +00003874void intel_device_info_dump_flags(const struct intel_device_info *info,
3875 struct drm_printer *p);
Chris Wilson94b4f3b2016-07-05 10:40:20 +01003876
Jesse Barnes79e53942008-11-07 14:24:08 -08003877/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02003878extern void intel_modeset_init_hw(struct drm_device *dev);
Ville Syrjäläb079bd172016-10-25 18:58:02 +03003879extern int intel_modeset_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003880extern void intel_modeset_cleanup(struct drm_device *dev);
Chris Wilson1ebaa0b2016-06-24 14:00:15 +01003881extern int intel_connector_register(struct drm_connector *);
Chris Wilsonc191eca2016-06-17 11:40:33 +01003882extern void intel_connector_unregister(struct drm_connector *);
Tvrtko Ursulin6315b5d2016-11-16 12:32:42 +00003883extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3884 bool state);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +02003885extern void intel_display_resume(struct drm_device *dev);
Tvrtko Ursulin29b74b72016-11-16 08:55:39 +00003886extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3887extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01003888extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
Ander Conselvan de Oliveirac39055b2016-11-23 16:21:44 +02003889extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
Chris Wilson9fcee2f2017-01-26 10:19:19 +00003890extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
Ville Syrjälä11a85d62016-11-28 19:37:12 +02003891extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
Imre Deak5209b1f2014-07-01 12:36:17 +03003892 bool enable);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08003893
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07003894int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3895 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07003896
Chris Wilson6ef3d422010-08-04 20:26:07 +01003897/* overlay */
Chris Wilsonc0336662016-05-06 15:40:21 +01003898extern struct intel_overlay_error_state *
3899intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003900extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3901 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003902
Chris Wilsonc0336662016-05-06 15:40:21 +01003903extern struct intel_display_error_state *
3904intel_display_capture_error_state(struct drm_i915_private *dev_priv);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003905extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003906 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01003907
Tom O'Rourke151a49d2014-11-13 18:50:10 -08003908int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3909int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Imre Deaka0b8a1f2016-12-05 18:27:37 +02003910int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3911 u32 reply_mask, u32 reply, int timeout_base_ms);
Jani Nikula59de0812013-05-22 15:36:16 +03003912
3913/* intel_sideband.c */
Deepak S707b6e32015-01-16 20:42:17 +05303914u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
Chris Wilson9fcee2f2017-01-26 10:19:19 +00003915int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
Jani Nikula64936252013-05-22 15:36:20 +03003916u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Deepak Mdfb19ed2016-02-04 18:55:15 +02003917u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3918void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003919u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3920void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3921u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3922void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08003923u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3924void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003925u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3926void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003927u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3928 enum intel_sbi_destination destination);
3929void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3930 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05303931u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3932void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003933
Ander Conselvan de Oliveirab7fa22d2016-04-27 15:44:17 +03003934/* intel_dpio_phy.c */
Ander Conselvan de Oliveira0a116ce2016-12-02 10:23:51 +02003935void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
Ander Conselvan de Oliveiraed378922016-10-19 10:59:00 +03003936 enum dpio_phy *phy, enum dpio_channel *ch);
Ander Conselvan de Oliveirab6e08202016-10-06 19:22:19 +03003937void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3938 enum port port, u32 margin, u32 scale,
3939 u32 enable, u32 deemphasis);
Ander Conselvan de Oliveira47a6bc62016-10-06 19:22:17 +03003940void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3941void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3942bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3943 enum dpio_phy phy);
3944bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3945 enum dpio_phy phy);
Ville Syrjälä5161d052017-10-27 16:43:48 +03003946uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
Ander Conselvan de Oliveira47a6bc62016-10-06 19:22:17 +03003947void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3948 uint8_t lane_lat_optim_mask);
3949uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3950
Ander Conselvan de Oliveirab7fa22d2016-04-27 15:44:17 +03003951void chv_set_phy_signal_level(struct intel_encoder *encoder,
3952 u32 deemph_reg_value, u32 margin_reg_value,
3953 bool uniq_trans_scale);
Ander Conselvan de Oliveira844b2f92016-04-27 15:44:18 +03003954void chv_data_lane_soft_reset(struct intel_encoder *encoder,
Ville Syrjälä2e1029c2017-10-31 22:51:18 +02003955 const struct intel_crtc_state *crtc_state,
Ander Conselvan de Oliveira844b2f92016-04-27 15:44:18 +03003956 bool reset);
Ville Syrjälä2e1029c2017-10-31 22:51:18 +02003957void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3958 const struct intel_crtc_state *crtc_state);
3959void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3960 const struct intel_crtc_state *crtc_state);
Ander Conselvan de Oliveirae7d2a7172016-04-27 15:44:20 +03003961void chv_phy_release_cl2_override(struct intel_encoder *encoder);
Ville Syrjälä2e1029c2017-10-31 22:51:18 +02003962void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3963 const struct intel_crtc_state *old_crtc_state);
Ander Conselvan de Oliveirab7fa22d2016-04-27 15:44:17 +03003964
Ander Conselvan de Oliveira53d98722016-04-27 15:44:22 +03003965void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3966 u32 demph_reg_value, u32 preemph_reg_value,
3967 u32 uniqtranscale_reg_value, u32 tx3_demph);
Ville Syrjälä2e1029c2017-10-31 22:51:18 +02003968void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3969 const struct intel_crtc_state *crtc_state);
3970void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3971 const struct intel_crtc_state *crtc_state);
3972void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3973 const struct intel_crtc_state *old_crtc_state);
Ander Conselvan de Oliveira53d98722016-04-27 15:44:22 +03003974
Ville Syrjälä616bc822015-01-23 21:04:25 +02003975int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3976int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
Tvrtko Ursulin36cc8b92017-11-21 18:18:51 +00003977u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
Mika Kuoppalac5a0ad12017-03-15 17:43:00 +02003978 const i915_reg_t reg);
Deepak Sc8d9a592013-11-23 14:55:42 +05303979
Tvrtko Ursulinc84b2702017-11-21 18:18:44 +00003980u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3981
Tvrtko Ursulin36cc8b92017-11-21 18:18:51 +00003982static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3983 const i915_reg_t reg)
3984{
3985 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3986}
3987
Ben Widawsky0b274482013-10-04 21:22:51 -07003988#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3989#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00003990
Ben Widawsky0b274482013-10-04 21:22:51 -07003991#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3992#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3993#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3994#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003995
Ben Widawsky0b274482013-10-04 21:22:51 -07003996#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3997#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3998#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3999#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00004000
Chris Wilson698b3132014-03-21 13:16:43 +00004001/* Be very careful with read/write 64-bit values. On 32-bit machines, they
4002 * will be implemented using 2 32-bit writes in an arbitrary order with
4003 * an arbitrary delay between them. This can cause the hardware to
4004 * act upon the intermediate value, possibly leading to corruption and
Chris Wilsonb18c1bb2016-09-06 15:45:38 +01004005 * machine death. For this reason we do not support I915_WRITE64, or
4006 * dev_priv->uncore.funcs.mmio_writeq.
4007 *
4008 * When reading a 64-bit value as two 32-bit values, the delay may cause
4009 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
4010 * occasionally a 64-bit register does not actualy support a full readq
4011 * and must be read using two 32-bit reads.
4012 *
4013 * You have been warned.
Chris Wilson698b3132014-03-21 13:16:43 +00004014 */
Ben Widawsky0b274482013-10-04 21:22:51 -07004015#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08004016
Chris Wilson50877442014-03-21 12:41:53 +00004017#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
Chris Wilsonacd29f72015-09-08 14:17:13 +01004018 u32 upper, lower, old_upper, loop = 0; \
4019 upper = I915_READ(upper_reg); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01004020 do { \
Chris Wilsonacd29f72015-09-08 14:17:13 +01004021 old_upper = upper; \
Chris Wilsonee0a2272015-07-15 09:50:42 +01004022 lower = I915_READ(lower_reg); \
Chris Wilsonacd29f72015-09-08 14:17:13 +01004023 upper = I915_READ(upper_reg); \
4024 } while (upper != old_upper && loop++ < 2); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01004025 (u64)upper << 32 | lower; })
Chris Wilson50877442014-03-21 12:41:53 +00004026
Zou Nan haicae58522010-11-09 17:17:32 +08004027#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
4028#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
4029
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03004030#define __raw_read(x, s) \
Chris Wilson6e3955a2017-03-23 10:19:43 +00004031static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004032 i915_reg_t reg) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03004033{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004034 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03004035}
4036
4037#define __raw_write(x, s) \
Chris Wilson6e3955a2017-03-23 10:19:43 +00004038static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004039 i915_reg_t reg, uint##x##_t val) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03004040{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004041 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03004042}
4043__raw_read(8, b)
4044__raw_read(16, w)
4045__raw_read(32, l)
4046__raw_read(64, q)
4047
4048__raw_write(8, b)
4049__raw_write(16, w)
4050__raw_write(32, l)
4051__raw_write(64, q)
4052
4053#undef __raw_read
4054#undef __raw_write
4055
Chris Wilsona6111f72015-04-07 16:21:02 +01004056/* These are untraced mmio-accessors that are only valid to be used inside
Arkadiusz Hileraafee2e2016-10-25 14:48:02 +02004057 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
Chris Wilsona6111f72015-04-07 16:21:02 +01004058 * controlled.
Arkadiusz Hileraafee2e2016-10-25 14:48:02 +02004059 *
Chris Wilsona6111f72015-04-07 16:21:02 +01004060 * Think twice, and think again, before using these.
Arkadiusz Hileraafee2e2016-10-25 14:48:02 +02004061 *
4062 * As an example, these accessors can possibly be used between:
4063 *
4064 * spin_lock_irq(&dev_priv->uncore.lock);
4065 * intel_uncore_forcewake_get__locked();
4066 *
4067 * and
4068 *
4069 * intel_uncore_forcewake_put__locked();
4070 * spin_unlock_irq(&dev_priv->uncore.lock);
4071 *
4072 *
4073 * Note: some registers may not need forcewake held, so
4074 * intel_uncore_forcewake_{get,put} can be omitted, see
4075 * intel_uncore_forcewake_for_reg().
4076 *
4077 * Certain architectures will die if the same cacheline is concurrently accessed
4078 * by different clients (e.g. on Ivybridge). Access to registers should
4079 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4080 * a more localised lock guarding all access to that bank of registers.
Chris Wilsona6111f72015-04-07 16:21:02 +01004081 */
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03004082#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4083#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
Chris Wilson76f84212016-06-30 15:33:45 +01004084#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
Chris Wilsona6111f72015-04-07 16:21:02 +01004085#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4086
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02004087/* "Broadcast RGB" property */
4088#define INTEL_BROADCAST_RGB_AUTO 0
4089#define INTEL_BROADCAST_RGB_FULL 1
4090#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08004091
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +01004092static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02004093{
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +01004094 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02004095 return VLV_VGACNTRL;
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +01004096 else if (INTEL_GEN(dev_priv) >= 5)
Sonika Jindal92e23b92014-07-21 15:23:40 +05304097 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02004098 else
4099 return VGACNTRL;
4100}
4101
Imre Deakdf977292013-05-21 20:03:17 +03004102static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
4103{
4104 unsigned long j = msecs_to_jiffies(m);
4105
4106 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4107}
4108
Daniel Vetter7bd0e222014-12-04 11:12:54 +01004109static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4110{
Chris Wilsonb8050142017-08-11 11:57:31 +01004111 /* nsecs_to_jiffies64() does not guard against overflow */
4112 if (NSEC_PER_SEC % HZ &&
4113 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
4114 return MAX_JIFFY_OFFSET;
4115
Daniel Vetter7bd0e222014-12-04 11:12:54 +01004116 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4117}
4118
Imre Deakdf977292013-05-21 20:03:17 +03004119static inline unsigned long
4120timespec_to_jiffies_timeout(const struct timespec *value)
4121{
4122 unsigned long j = timespec_to_jiffies(value);
4123
4124 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4125}
4126
Paulo Zanonidce56b32013-12-19 14:29:40 -02004127/*
4128 * If you need to wait X milliseconds between events A and B, but event B
4129 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4130 * when event A happened, then just before event B you call this function and
4131 * pass the timestamp as the first argument, and X as the second argument.
4132 */
4133static inline void
4134wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4135{
Imre Deakec5e0cf2014-01-29 13:25:40 +02004136 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02004137
4138 /*
4139 * Don't re-read the value of "jiffies" every time since it may change
4140 * behind our back and break the math.
4141 */
4142 tmp_jiffies = jiffies;
4143 target_jiffies = timestamp_jiffies +
4144 msecs_to_jiffies_timeout(to_wait_ms);
4145
4146 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02004147 remaining_jiffies = target_jiffies - tmp_jiffies;
4148 while (remaining_jiffies)
4149 remaining_jiffies =
4150 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02004151 }
4152}
Chris Wilson221fe792016-09-09 14:11:51 +01004153
4154static inline bool
Chris Wilson754c9fd2017-02-23 07:44:14 +00004155__i915_request_irq_complete(const struct drm_i915_gem_request *req)
Chris Wilson688e6c72016-07-01 17:23:15 +01004156{
Chris Wilsonf69a02c2016-07-01 17:23:16 +01004157 struct intel_engine_cs *engine = req->engine;
Chris Wilson754c9fd2017-02-23 07:44:14 +00004158 u32 seqno;
Chris Wilsonf69a02c2016-07-01 17:23:16 +01004159
Chris Wilson309663a2017-02-23 07:44:07 +00004160 /* Note that the engine may have wrapped around the seqno, and
4161 * so our request->global_seqno will be ahead of the hardware,
4162 * even though it completed the request before wrapping. We catch
4163 * this by kicking all the waiters before resetting the seqno
4164 * in hardware, and also signal the fence.
4165 */
4166 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4167 return true;
4168
Chris Wilson754c9fd2017-02-23 07:44:14 +00004169 /* The request was dequeued before we were awoken. We check after
4170 * inspecting the hw to confirm that this was the same request
4171 * that generated the HWS update. The memory barriers within
4172 * the request execution are sufficient to ensure that a check
4173 * after reading the value from hw matches this request.
4174 */
4175 seqno = i915_gem_request_global_seqno(req);
4176 if (!seqno)
4177 return false;
4178
Chris Wilson7ec2c732016-07-01 17:23:22 +01004179 /* Before we do the heavier coherent read of the seqno,
4180 * check the value (hopefully) in the CPU cacheline.
4181 */
Chris Wilson754c9fd2017-02-23 07:44:14 +00004182 if (__i915_gem_request_completed(req, seqno))
Chris Wilson7ec2c732016-07-01 17:23:22 +01004183 return true;
4184
Chris Wilson688e6c72016-07-01 17:23:15 +01004185 /* Ensure our read of the seqno is coherent so that we
4186 * do not "miss an interrupt" (i.e. if this is the last
4187 * request and the seqno write from the GPU is not visible
4188 * by the time the interrupt fires, we will see that the
4189 * request is incomplete and go back to sleep awaiting
4190 * another interrupt that will never come.)
4191 *
4192 * Strictly, we only need to do this once after an interrupt,
4193 * but it is easier and safer to do it every time the waiter
4194 * is woken.
4195 */
Chris Wilson3d5564e2016-07-01 17:23:23 +01004196 if (engine->irq_seqno_barrier &&
Chris Wilson538b2572017-01-24 15:18:05 +00004197 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
Chris Wilson56299fb2017-02-27 20:58:48 +00004198 struct intel_breadcrumbs *b = &engine->breadcrumbs;
Chris Wilson99fe4a52016-07-06 12:39:01 +01004199
Chris Wilson3d5564e2016-07-01 17:23:23 +01004200 /* The ordering of irq_posted versus applying the barrier
4201 * is crucial. The clearing of the current irq_posted must
4202 * be visible before we perform the barrier operation,
4203 * such that if a subsequent interrupt arrives, irq_posted
4204 * is reasserted and our task rewoken (which causes us to
4205 * do another __i915_request_irq_complete() immediately
4206 * and reapply the barrier). Conversely, if the clear
4207 * occurs after the barrier, then an interrupt that arrived
4208 * whilst we waited on the barrier would not trigger a
4209 * barrier on the next pass, and the read may not see the
4210 * seqno update.
4211 */
Chris Wilsonf69a02c2016-07-01 17:23:16 +01004212 engine->irq_seqno_barrier(engine);
Chris Wilson99fe4a52016-07-06 12:39:01 +01004213
4214 /* If we consume the irq, but we are no longer the bottom-half,
4215 * the real bottom-half may not have serialised their own
4216 * seqno check with the irq-barrier (i.e. may have inspected
4217 * the seqno before we believe it coherent since they see
4218 * irq_posted == false but we are still running).
4219 */
Tvrtko Ursulin2c33b542017-03-06 15:03:19 +00004220 spin_lock_irq(&b->irq_lock);
Chris Wilson61d3dc72017-03-03 19:08:24 +00004221 if (b->irq_wait && b->irq_wait->tsk != current)
Chris Wilson99fe4a52016-07-06 12:39:01 +01004222 /* Note that if the bottom-half is changed as we
4223 * are sending the wake-up, the new bottom-half will
4224 * be woken by whomever made the change. We only have
4225 * to worry about when we steal the irq-posted for
4226 * ourself.
4227 */
Chris Wilson61d3dc72017-03-03 19:08:24 +00004228 wake_up_process(b->irq_wait->tsk);
Tvrtko Ursulin2c33b542017-03-06 15:03:19 +00004229 spin_unlock_irq(&b->irq_lock);
Chris Wilson99fe4a52016-07-06 12:39:01 +01004230
Chris Wilson754c9fd2017-02-23 07:44:14 +00004231 if (__i915_gem_request_completed(req, seqno))
Chris Wilson7ec2c732016-07-01 17:23:22 +01004232 return true;
4233 }
Chris Wilson688e6c72016-07-01 17:23:15 +01004234
Chris Wilson688e6c72016-07-01 17:23:15 +01004235 return false;
4236}
4237
Chris Wilson0b1de5d2016-08-12 12:39:59 +01004238void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4239bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4240
Chris Wilsonc4d3ae62017-01-06 15:20:09 +00004241/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4242 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4243 * perform the operation. To check beforehand, pass in the parameters to
4244 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4245 * you only need to pass in the minor offsets, page-aligned pointers are
4246 * always valid.
4247 *
4248 * For just checking for SSE4.1, in the foreknowledge that the future use
4249 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4250 */
4251#define i915_can_memcpy_from_wc(dst, src, len) \
4252 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4253
4254#define i915_has_memcpy_from_wc() \
4255 i915_memcpy_from_wc(NULL, NULL, 0)
4256
Chris Wilsonc58305a2016-08-19 16:54:28 +01004257/* i915_mm.c */
4258int remap_io_mapping(struct vm_area_struct *vma,
4259 unsigned long addr, unsigned long pfn, unsigned long size,
4260 struct io_mapping *iomap);
4261
Chris Wilson767a9832017-09-13 09:56:05 +01004262static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
4263{
4264 if (INTEL_GEN(i915) >= 10)
4265 return CNL_HWS_CSB_WRITE_INDEX;
4266 else
4267 return I915_HWS_CSB_WRITE_INDEX;
4268}
4269
Linus Torvalds1da177e2005-04-16 15:20:36 -07004270#endif