Blame - arch/powerpc/include/asm/cputable.h - kernel/msm

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Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	1	#ifndef __ASM_POWERPC_CPUTABLE_H
				2	#define __ASM_POWERPC_CPUTABLE_H
				3
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	4	#define PPC_FEATURE_32 0x80000000
				5	#define PPC_FEATURE_64 0x40000000
				6	#define PPC_FEATURE_601_INSTR 0x20000000
				7	#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
				8	#define PPC_FEATURE_HAS_FPU 0x08000000
				9	#define PPC_FEATURE_HAS_MMU 0x04000000
				10	#define PPC_FEATURE_HAS_4xxMAC 0x02000000
				11	#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
				12	#define PPC_FEATURE_HAS_SPE 0x00800000
				13	#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
				14	#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras	9859901	2005-10-22 16:51:34 +1000	[diff] [blame]	15	#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerras	a7ddc5e	2005-11-10 14:29:18 +1100	[diff] [blame]	16	#define PPC_FEATURE_POWER4 0x00080000
				17	#define PPC_FEATURE_POWER5 0x00040000
				18	#define PPC_FEATURE_POWER5_PLUS 0x00020000
				19	#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	20	#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidt	aa5cb02	2006-03-01 15:07:07 +1100	[diff] [blame]	21	#define PPC_FEATURE_SMT 0x00004000
				22	#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	23	#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johansson	b3ebd1d	2006-09-06 14:35:57 -0500	[diff] [blame]	24	#define PPC_FEATURE_PA6T 0x00000800
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	25	#define PPC_FEATURE_HAS_DFP 0x00000400
				26	#define PPC_FEATURE_POWER6_EXT 0x00000200
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	27	#define PPC_FEATURE_ARCH_2_06 0x00000100
Michael Neuling	b962ce9	2008-06-25 14:07:18 +1000	[diff] [blame]	28	#define PPC_FEATURE_HAS_VSX 0x00000080
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	29
Nathan Lynch	0f47331	2008-07-10 01:06:57 +1000	[diff] [blame]	30	#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
				31	0x00000040
				32
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	33	#define PPC_FEATURE_TRUE_LE 0x00000002
				34	#define PPC_FEATURE_PPC_LE 0x00000001
				35
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	36	#ifdef __KERNEL__
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	37
				38	#include <asm/asm-compat.h>
Michael Ellerman	c5157e5	2008-06-24 11:32:39 +1000	[diff] [blame]	39	#include <asm/feature-fixups.h>
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	40
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	41	#ifndef __ASSEMBLY__
				42
				43	/* This structure can grow, it's real size is used by head.S code
				44	* via the mkdefs mechanism.
				45	*/
				46	struct cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	47
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	48	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	49	typedef void (*cpu_restore_t)(void);
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	50
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	51	enum powerpc_oprofile_type {
Andy Whitcroft	7a45fb1	2006-01-13 12:35:49 +0000	[diff] [blame]	52	PPC_OPROFILE_INVALID = 0,
				53	PPC_OPROFILE_RS64 = 1,
				54	PPC_OPROFILE_POWER4 = 2,
				55	PPC_OPROFILE_G4 = 3,
Andy Fleming	39aef68	2008-02-04 18:27:55 -0600	[diff] [blame]	56	PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson	18f2190	2006-11-20 18:45:16 +0100	[diff] [blame]	57	PPC_OPROFILE_CELL = 5,
Olof Johansson	25fc530	2007-04-18 16:38:21 +1000	[diff] [blame]	58	PPC_OPROFILE_PA6T = 6,
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	59	};
				60
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	61	enum powerpc_pmc_type {
				62	PPC_PMC_DEFAULT = 0,
				63	PPC_PMC_IBM = 1,
				64	PPC_PMC_PA6T = 2,
Benjamin Herrenschmidt	b950bdd	2008-08-18 14:23:51 +1000	[diff] [blame]	65	PPC_PMC_G4 = 3,
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	66	};
				67
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	68	struct pt_regs;
				69
				70	extern int machine_check_generic(struct pt_regs *regs);
				71	extern int machine_check_4xx(struct pt_regs *regs);
				72	extern int machine_check_440A(struct pt_regs *regs);
				73	extern int machine_check_e500(struct pt_regs *regs);
				74	extern int machine_check_e200(struct pt_regs *regs);
				75
Paul Mackerras	87a72f9	2007-10-04 14:18:01 +1000	[diff] [blame]	76	/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	77	struct cpu_spec {
				78	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
				79	unsigned int pvr_mask;
				80	unsigned int pvr_value;
				81
				82	char *cpu_name;
				83	unsigned long cpu_features; /* Kernel features */
				84	unsigned int cpu_user_features; /* Userland features */
				85
				86	/* cache line sizes */
				87	unsigned int icache_bsize;
				88	unsigned int dcache_bsize;
				89
				90	/* number of performance monitor counters */
				91	unsigned int num_pmcs;
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	92	enum powerpc_pmc_type pmc_type;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	93
				94	/* this is called to initialize various CPU bits like L1 cache,
				95	* BHT, SPD, etc... from head.S before branching to identify_machine
				96	*/
				97	cpu_setup_t cpu_setup;
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	98	/* Used to restore cpu setup on secondary processors and at resume */
				99	cpu_restore_t cpu_restore;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	100
				101	/* Used by oprofile userspace to select the right counters */
				102	char *oprofile_cpu_type;
				103
				104	/* Processor specific oprofile operations */
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	105	enum powerpc_oprofile_type oprofile_type;
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	106
Michael Neuling	e78dbc8	2006-06-08 14:42:34 +1000	[diff] [blame]	107	/* Bit locations inside the mmcra change */
				108	unsigned long oprofile_mmcra_sihv;
				109	unsigned long oprofile_mmcra_sipr;
				110
				111	/* Bits to clear during an oprofile exception */
				112	unsigned long oprofile_mmcra_clear;
				113
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	114	/* Name of processor class, for the ELF AT_PLATFORM entry */
				115	char *platform;
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	116
				117	/* Processor specific machine check handling. Return negative
				118	* if the error is fatal, 1 if it was fully recovered and 0 to
				119	* pass up (not CPU originated) */
				120	int (machine_check)(struct pt_regs regs);
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	121	};
				122
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	123	extern struct cpu_spec *cur_cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	124
Benjamin Herrenschmidt	42c4aaa	2006-10-24 16:42:40 +1000	[diff] [blame]	125	extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
				126
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	127	extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	128	extern void do_feature_fixups(unsigned long value, void *fixup_start,
				129	void *fixup_end);
Paul Mackerras	9b6b563	2005-10-06 12:06:20 +1000	[diff] [blame]	130
Nathan Lynch	9115d13	2008-07-16 09:58:51 +1000	[diff] [blame]	131	extern const char *powerpc_base_platform;
				132
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	133	#endif /* __ASSEMBLY__ */
				134
				135	/* CPU kernel features */
				136
				137	/* Retain the 32b definitions all use bottom half of word */
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	138	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	139	#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
				140	#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
				141	#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
				142	#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
				143	#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
				144	#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
Kumar Gala	aba11fc	2008-06-19 09:40:31 -0500	[diff] [blame]	145	#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	146	#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
				147	#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
				148	#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
				149	#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
				150	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
				151	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
				152	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
				153	#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
				154	#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
				155	#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
				156	#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
				157	#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman	3d15910	2006-03-21 20:45:58 +1100	[diff] [blame]	158	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	159	#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
				160	#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	161	#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	162	#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	163	#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	164	#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	165	#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
Benjamin Herrenschmidt	8309ce7	2008-12-12 17:33:25 +1100	[diff] [blame^]	166	#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	167
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	168	/*
				169	* Add the 64-bit processor unique features in the top half of the word;
				170	* on 32-bit, make the names available but defined to be 0.
				171	*/
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	172	#ifdef __powerpc64__
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	173	#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	174	#else
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	175	#define LONG_ASM_CONST(x) 0
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	176	#endif
				177
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	178	#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
				179	#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
				180	#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	181	#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
				182	#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
				183	#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
				184	#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	185	#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
				186	#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
				187	#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
				188	#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt	859deea	2006-10-20 14:37:05 +1000	[diff] [blame]	189	#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	190	#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
Anton Blanchard	4c198557	2006-12-08 17:46:58 +1100	[diff] [blame]	191	#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
Paul Mackerras	1189be6	2007-10-11 20:37:10 +1000	[diff] [blame]	192	#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
Olof Johansson	f66bce5	2007-10-16 00:58:59 +1000	[diff] [blame]	193	#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
Michael Neuling	b962ce9	2008-06-25 14:07:18 +1000	[diff] [blame]	194	#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
Dave Kleikamp	3790704	2008-07-08 00:28:53 +1000	[diff] [blame]	195	#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
Mark Nelson	2a92943	2008-08-22 14:36:19 +1000	[diff] [blame]	196	#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
Mark Nelson	4ec577a	2008-10-27 00:43:02 +0000	[diff] [blame]	197	#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	198
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	199	#ifndef __ASSEMBLY__
				200
Stephen Rothwell	0470466	2006-11-30 11:46:22 +1100	[diff] [blame]	201	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB \| \
				202	CPU_FTR_TLBIEL \| CPU_FTR_NOEXECUTE \| \
				203	CPU_FTR_NODSISRALIGN \| CPU_FTR_16M_PAGE)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	204
				205	/* We only set the altivec features if the kernel was compiled with altivec
				206	* support
				207	*/
				208	#ifdef CONFIG_ALTIVEC
				209	#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
				210	#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
				211	#else
				212	#define CPU_FTR_ALTIVEC_COMP 0
				213	#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
				214	#endif
				215
Michael Neuling	b962ce9	2008-06-25 14:07:18 +1000	[diff] [blame]	216	/* We only set the VSX features if the kernel was compiled with VSX
				217	* support
				218	*/
				219	#ifdef CONFIG_VSX
				220	#define CPU_FTR_VSX_COMP CPU_FTR_VSX
				221	#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
				222	#else
				223	#define CPU_FTR_VSX_COMP 0
				224	#define PPC_FEATURE_HAS_VSX_COMP 0
				225	#endif
				226
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	227	/* We only set the spe features if the kernel was compiled with spe
				228	* support
				229	*/
				230	#ifdef CONFIG_SPE
				231	#define CPU_FTR_SPE_COMP CPU_FTR_SPE
				232	#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
				233	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
				234	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
				235	#else
				236	#define CPU_FTR_SPE_COMP 0
				237	#define PPC_FEATURE_HAS_SPE_COMP 0
				238	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
				239	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
				240	#endif
				241
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	242	/* We need to mark all pages as being coherent if we're SMP or we have a
				243	* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
				244	* require it for PCI "streaming/prefetch" to work properly.
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	245	*/
Kumar Gala	1775dbb	2006-02-22 09:46:02 -0600	[diff] [blame]	246	#if defined(CONFIG_SMP) \|\| defined(CONFIG_MPC10X_BRIDGE) \
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	247	\|\| defined(CONFIG_PPC_83xx) \|\| defined(CONFIG_8260)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	248	#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
				249	#else
				250	#define CPU_FTR_COMMON 0
				251	#endif
				252
				253	/* The powersave features NAP & DOZE seems to confuse BDI when
				254	debugging. So if a BDI is used, disable theses
				255	*/
				256	#ifndef CONFIG_BDI_SWITCH
				257	#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
				258	#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
				259	#else
				260	#define CPU_FTR_MAYBE_CAN_DOZE 0
				261	#define CPU_FTR_MAYBE_CAN_NAP 0
				262	#endif
				263
				264	#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
				265	!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
				266	!defined(CONFIG_BOOKE))
				267
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	268	#define CPU_FTRS_PPC601 (CPU_FTR_COMMON \| CPU_FTR_601 \| CPU_FTR_HPTE_TABLE \| \
				269	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_UNIFIED_ID_CACHE)
				270	#define CPU_FTRS_603 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	271	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	272	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	273	#define CPU_FTRS_604 (CPU_FTR_COMMON \| \
Kumar Gala	aba11fc	2008-06-19 09:40:31 -0500	[diff] [blame]	274	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	275	#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	276	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	277	CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	278	#define CPU_FTRS_740 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	279	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	280	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
				281	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	282	#define CPU_FTRS_750 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	283	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	284	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
				285	CPU_FTR_PPC_LE)
Josh Boyer	b6f41cc	2007-07-03 02:06:53 +1000	[diff] [blame]	286	#define CPU_FTRS_750CL (CPU_FTRS_750 \| CPU_FTR_HAS_HIGH_BATS)
				287	#define CPU_FTRS_750FX1 (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_NO_DPM)
				288	#define CPU_FTRS_750FX2 (CPU_FTRS_750 \| CPU_FTR_NO_DPM)
				289	#define CPU_FTRS_750FX (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX \| \
				290	CPU_FTR_HAS_HIGH_BATS)
				291	#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	292	#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	293	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				294	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	295	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	296	#define CPU_FTRS_7400 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	297	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				298	CPU_FTR_TAU \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	299	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	300	#define CPU_FTRS_7450_20 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	301	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				302	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	303	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	304	#define CPU_FTRS_7450_21 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	305	CPU_FTR_USE_TB \| \
				306	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				307	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				308	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	309	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	310	#define CPU_FTRS_7450_23 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	311	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	312	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				313	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	314	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	315	#define CPU_FTRS_7455_1 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	316	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	317	CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_L3CR \| \
				318	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| CPU_FTR_HAS_HIGH_BATS \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	319	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	320	#define CPU_FTRS_7455_20 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	321	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	322	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				323	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				324	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	325	CPU_FTR_NEED_COHERENT \| CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	326	#define CPU_FTRS_7455 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	327	CPU_FTR_USE_TB \| \
				328	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				329	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				330	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	331	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	332	#define CPU_FTRS_7447_10 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	333	CPU_FTR_USE_TB \| \
				334	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				335	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				336	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	337	CPU_FTR_NEED_COHERENT \| CPU_FTR_NO_BTIC \| CPU_FTR_PPC_LE \| \
				338	CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	339	#define CPU_FTRS_7447 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	340	CPU_FTR_USE_TB \| \
				341	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				342	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				343	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	344	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	345	#define CPU_FTRS_7447A (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	346	CPU_FTR_USE_TB \| \
				347	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				348	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				349	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	350	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	351	#define CPU_FTRS_7448 (CPU_FTR_COMMON \| \
James.Yang	3d37254	2007-05-02 16:34:43 -0500	[diff] [blame]	352	CPU_FTR_USE_TB \| \
				353	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				354	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				355	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	356	CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	357	#define CPU_FTRS_82XX (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	358	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB)
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	359	#define CPU_FTRS_G2_LE (CPU_FTR_COMMON \| CPU_FTR_MAYBE_CAN_DOZE \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	360	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	361	#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	362	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS \| \
				363	CPU_FTR_COMMON)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	364	#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE \| \
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	365	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS \| \
				366	CPU_FTR_COMMON \| CPU_FTR_FPU_UNAVAILABLE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	367	#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	368	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	369	#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
Benjamin Herrenschmidt	8309ce7	2008-12-12 17:33:25 +1100	[diff] [blame^]	370	#define CPU_FTRS_40X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
				371	#define CPU_FTRS_44X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	372	#define CPU_FTRS_E200 (CPU_FTR_USE_TB \| CPU_FTR_SPE_COMP \| \
				373	CPU_FTR_NODSISRALIGN \| CPU_FTR_COHERENT_ICACHE \| \
Benjamin Herrenschmidt	8309ce7	2008-12-12 17:33:25 +1100	[diff] [blame^]	374	CPU_FTR_UNIFIED_ID_CACHE \| CPU_FTR_NOEXECUTE)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	375	#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	8309ce7	2008-12-12 17:33:25 +1100	[diff] [blame^]	376	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_NODSISRALIGN \| \
				377	CPU_FTR_NOEXECUTE)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	378	#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
				379	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_BIG_PHYS \| \
Benjamin Herrenschmidt	8309ce7	2008-12-12 17:33:25 +1100	[diff] [blame^]	380	CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	381	#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Kumar Gala	aba11fc	2008-06-19 09:40:31 -0500	[diff] [blame]	382	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_BIG_PHYS \| CPU_FTR_NODSISRALIGN \| \
Benjamin Herrenschmidt	8309ce7	2008-12-12 17:33:25 +1100	[diff] [blame^]	383	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE)
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	384	#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON \| CPU_FTR_NODSISRALIGN)
Michael Ellerman	0b8e2e1	2006-11-23 00:46:46 +0100	[diff] [blame]	385
				386	/* 64-bit CPUs */
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	387	#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	388	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \| CPU_FTR_PPC_LE)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	389	#define CPU_FTRS_RS64 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	390	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \| \
				391	CPU_FTR_MMCRA \| CPU_FTR_CTRL)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	392	#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	393	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Mark Nelson	2a92943	2008-08-22 14:36:19 +1000	[diff] [blame]	394	CPU_FTR_MMCRA \| CPU_FTR_CP_USE_DCBTZ)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	395	#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	396	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Mark Nelson	2a92943	2008-08-22 14:36:19 +1000	[diff] [blame]	397	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA \| \
				398	CPU_FTR_CP_USE_DCBTZ)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	399	#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	400	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	401	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				402	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
Michael Neuling	e78dbc8	2006-06-08 14:42:34 +1000	[diff] [blame]	403	CPU_FTR_PURR)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	404	#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	405	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	406	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				407	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
Anton Blanchard	4c198557	2006-12-08 17:46:58 +1100	[diff] [blame]	408	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Mark Nelson	4ec577a	2008-10-27 00:43:02 +0000	[diff] [blame]	409	CPU_FTR_DSCR \| CPU_FTR_UNALIGNED_LD_STD)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	410	#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	411	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
				412	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				413	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
				414	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Dave Kleikamp	3790704	2008-07-08 00:28:53 +1000	[diff] [blame]	415	CPU_FTR_DSCR \| CPU_FTR_SAO)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	416	#define CPU_FTRS_CELL (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	417	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	418	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Mark Nelson	2a92943	2008-08-22 14:36:19 +1000	[diff] [blame]	419	CPU_FTR_PAUSE_ZERO \| CPU_FTR_CI_LARGE_PAGE \| \
Mark Nelson	4ec577a	2008-10-27 00:43:02 +0000	[diff] [blame]	420	CPU_FTR_CELL_TB_BUG \| CPU_FTR_CP_USE_DCBTZ \| \
				421	CPU_FTR_UNALIGNED_LD_STD)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	422	#define CPU_FTRS_PA6T (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Olof Johansson	b3ebd1d	2006-09-06 14:35:57 -0500	[diff] [blame]	423	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| \
				424	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CI_LARGE_PAGE \| \
Olof Johansson	f66bce5	2007-10-16 00:58:59 +1000	[diff] [blame]	425	CPU_FTR_PURR \| CPU_FTR_REAL_LE \| CPU_FTR_NO_SLBIE_B)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	426	#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	427	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	428
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	429	#ifdef __powerpc64__
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	430	#define CPU_FTRS_POSSIBLE \
				431	(CPU_FTRS_POWER3 \| CPU_FTRS_RS64 \| CPU_FTRS_POWER4 \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	432	CPU_FTRS_PPC970 \| CPU_FTRS_POWER5 \| CPU_FTRS_POWER6 \| \
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	433	CPU_FTRS_POWER7 \| CPU_FTRS_CELL \| CPU_FTRS_PA6T \| \
Michael Neuling	b962ce9	2008-06-25 14:07:18 +1000	[diff] [blame]	434	CPU_FTR_1T_SEGMENT \| CPU_FTR_VSX)
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	435	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	436	enum {
				437	CPU_FTRS_POSSIBLE =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	438	#if CLASSIC_PPC
				439	CPU_FTRS_PPC601 \| CPU_FTRS_603 \| CPU_FTRS_604 \| CPU_FTRS_740_NOTAU \|
				440	CPU_FTRS_740 \| CPU_FTRS_750 \| CPU_FTRS_750FX1 \|
				441	CPU_FTRS_750FX2 \| CPU_FTRS_750FX \| CPU_FTRS_750GX \|
				442	CPU_FTRS_7400_NOTAU \| CPU_FTRS_7400 \| CPU_FTRS_7450_20 \|
				443	CPU_FTRS_7450_21 \| CPU_FTRS_7450_23 \| CPU_FTRS_7455_1 \|
				444	CPU_FTRS_7455_20 \| CPU_FTRS_7455 \| CPU_FTRS_7447_10 \|
				445	CPU_FTRS_7447 \| CPU_FTRS_7447A \| CPU_FTRS_82XX \|
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	446	CPU_FTRS_G2_LE \| CPU_FTRS_E300 \| CPU_FTRS_E300C2 \|
				447	CPU_FTRS_CLASSIC32 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	448	#else
				449	CPU_FTRS_GENERIC_32 \|
				450	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	451	#ifdef CONFIG_8xx
				452	CPU_FTRS_8XX \|
				453	#endif
				454	#ifdef CONFIG_40x
				455	CPU_FTRS_40X \|
				456	#endif
				457	#ifdef CONFIG_44x
				458	CPU_FTRS_44X \|
				459	#endif
				460	#ifdef CONFIG_E200
				461	CPU_FTRS_E200 \|
				462	#endif
				463	#ifdef CONFIG_E500
Kumar Gala	3dfa877	2008-06-16 09:41:32 -0500	[diff] [blame]	464	CPU_FTRS_E500 \| CPU_FTRS_E500_2 \| CPU_FTRS_E500MC \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	465	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	466	0,
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	467	};
				468	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	469
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	470	#ifdef __powerpc64__
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	471	#define CPU_FTRS_ALWAYS \
				472	(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	473	CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	474	CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	475	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	476	enum {
				477	CPU_FTRS_ALWAYS =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	478	#if CLASSIC_PPC
				479	CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
				480	CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
				481	CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
				482	CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
				483	CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
				484	CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
				485	CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	486	CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
				487	CPU_FTRS_CLASSIC32 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	488	#else
				489	CPU_FTRS_GENERIC_32 &
				490	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	491	#ifdef CONFIG_8xx
				492	CPU_FTRS_8XX &
				493	#endif
				494	#ifdef CONFIG_40x
				495	CPU_FTRS_40X &
				496	#endif
				497	#ifdef CONFIG_44x
				498	CPU_FTRS_44X &
				499	#endif
				500	#ifdef CONFIG_E200
				501	CPU_FTRS_E200 &
				502	#endif
				503	#ifdef CONFIG_E500
Kumar Gala	3dfa877	2008-06-16 09:41:32 -0500	[diff] [blame]	504	CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	505	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	506	CPU_FTRS_POSSIBLE,
				507	};
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	508	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	509
				510	static inline int cpu_has_feature(unsigned long feature)
				511	{
				512	return (CPU_FTRS_ALWAYS & feature) \|\|
				513	(CPU_FTRS_POSSIBLE
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	514	& cur_cpu_spec->cpu_features
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	515	& feature);
				516	}
				517
				518	#endif /* !__ASSEMBLY__ */
				519
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	520	#endif /* __KERNEL__ */
				521	#endif /* __ASM_POWERPC_CPUTABLE_H */