Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 17 | #include <cstdarg> |
Nicolas Geoffray | f3e2cc4 | 2014-02-18 18:37:26 +0000 | [diff] [blame] | 18 | #include <inttypes.h> |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 19 | #include <string> |
Nicolas Geoffray | f3e2cc4 | 2014-02-18 18:37:26 +0000 | [diff] [blame] | 20 | |
Elliott Hughes | 8366ca0 | 2014-11-17 12:02:05 -0800 | [diff] [blame^] | 21 | #include "arch/instruction_set_features.h" |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 22 | #include "backend_x86.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 23 | #include "codegen_x86.h" |
| 24 | #include "dex/compiler_internals.h" |
| 25 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 26 | #include "dex/reg_storage_eq.h" |
Ian Rogers | 7e70b00 | 2014-10-08 11:47:24 -0700 | [diff] [blame] | 27 | #include "mirror/array-inl.h" |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 28 | #include "mirror/art_method.h" |
Mark Mendell | e19c91f | 2014-02-25 08:19:08 -0800 | [diff] [blame] | 29 | #include "mirror/string.h" |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 30 | #include "oat.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 31 | #include "x86_lir.h" |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 32 | #include "utils/dwarf_cfi.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 33 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 34 | namespace art { |
| 35 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 36 | static constexpr RegStorage core_regs_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 37 | rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, |
| 38 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 39 | static constexpr RegStorage core_regs_arr_64[] = { |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 40 | rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 41 | rs_r8, rs_r9, rs_r10, rs_r11, rs_r12, rs_r13, rs_r14, rs_r15 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 42 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 43 | static constexpr RegStorage core_regs_arr_64q[] = { |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 44 | rs_r0q, rs_r1q, rs_r2q, rs_r3q, rs_rX86_SP_64, rs_r5q, rs_r6q, rs_r7q, |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 45 | rs_r8q, rs_r9q, rs_r10q, rs_r11q, rs_r12q, rs_r13q, rs_r14q, rs_r15q |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 46 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 47 | static constexpr RegStorage sp_regs_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 48 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
| 49 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 50 | static constexpr RegStorage sp_regs_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 51 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 52 | rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 53 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 54 | static constexpr RegStorage dp_regs_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 55 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
| 56 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 57 | static constexpr RegStorage dp_regs_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 58 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 59 | rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 60 | }; |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 61 | static constexpr RegStorage xp_regs_arr_32[] = { |
| 62 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
| 63 | }; |
| 64 | static constexpr RegStorage xp_regs_arr_64[] = { |
| 65 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
| 66 | rs_xr8, rs_xr9, rs_xr10, rs_xr11, rs_xr12, rs_xr13, rs_xr14, rs_xr15 |
| 67 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 68 | static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}; |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 69 | static constexpr RegStorage reserved_regs_arr_64[] = {rs_rX86_SP_32}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 70 | static constexpr RegStorage reserved_regs_arr_64q[] = {rs_rX86_SP_64}; |
| 71 | static constexpr RegStorage core_temps_arr_32[] = {rs_rAX, rs_rCX, rs_rDX, rs_rBX}; |
| 72 | static constexpr RegStorage core_temps_arr_64[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 73 | rs_rAX, rs_rCX, rs_rDX, rs_rSI, rs_rDI, |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 74 | rs_r8, rs_r9, rs_r10, rs_r11 |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 75 | }; |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 76 | |
| 77 | // How to add register to be available for promotion: |
| 78 | // 1) Remove register from array defining temp |
| 79 | // 2) Update ClobberCallerSave |
| 80 | // 3) Update JNI compiler ABI: |
| 81 | // 3.1) add reg in JniCallingConvention method |
| 82 | // 3.2) update CoreSpillMask/FpSpillMask |
| 83 | // 4) Update entrypoints |
| 84 | // 4.1) Update constants in asm_support_x86_64.h for new frame size |
| 85 | // 4.2) Remove entry in SmashCallerSaves |
| 86 | // 4.3) Update jni_entrypoints to spill/unspill new callee save reg |
| 87 | // 4.4) Update quick_entrypoints to spill/unspill new callee save reg |
| 88 | // 5) Update runtime ABI |
| 89 | // 5.1) Update quick_method_frame_info with new required spills |
| 90 | // 5.2) Update QuickArgumentVisitor with new offsets to gprs and xmms |
| 91 | // Note that you cannot use register corresponding to incoming args |
| 92 | // according to ABI and QCG needs one additional XMM temp for |
| 93 | // bulk copy in preparation to call. |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 94 | static constexpr RegStorage core_temps_arr_64q[] = { |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 95 | rs_r0q, rs_r1q, rs_r2q, rs_r6q, rs_r7q, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 96 | rs_r8q, rs_r9q, rs_r10q, rs_r11q |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 97 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 98 | static constexpr RegStorage sp_temps_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 99 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
| 100 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 101 | static constexpr RegStorage sp_temps_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 102 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 103 | rs_fr8, rs_fr9, rs_fr10, rs_fr11 |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 104 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 105 | static constexpr RegStorage dp_temps_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 106 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
| 107 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 108 | static constexpr RegStorage dp_temps_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 109 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 110 | rs_dr8, rs_dr9, rs_dr10, rs_dr11 |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 111 | }; |
| 112 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 113 | static constexpr RegStorage xp_temps_arr_32[] = { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 114 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
| 115 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 116 | static constexpr RegStorage xp_temps_arr_64[] = { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 117 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 118 | rs_xr8, rs_xr9, rs_xr10, rs_xr11 |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 119 | }; |
| 120 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 121 | static constexpr ArrayRef<const RegStorage> empty_pool; |
| 122 | static constexpr ArrayRef<const RegStorage> core_regs_32(core_regs_arr_32); |
| 123 | static constexpr ArrayRef<const RegStorage> core_regs_64(core_regs_arr_64); |
| 124 | static constexpr ArrayRef<const RegStorage> core_regs_64q(core_regs_arr_64q); |
| 125 | static constexpr ArrayRef<const RegStorage> sp_regs_32(sp_regs_arr_32); |
| 126 | static constexpr ArrayRef<const RegStorage> sp_regs_64(sp_regs_arr_64); |
| 127 | static constexpr ArrayRef<const RegStorage> dp_regs_32(dp_regs_arr_32); |
| 128 | static constexpr ArrayRef<const RegStorage> dp_regs_64(dp_regs_arr_64); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 129 | static constexpr ArrayRef<const RegStorage> xp_regs_32(xp_regs_arr_32); |
| 130 | static constexpr ArrayRef<const RegStorage> xp_regs_64(xp_regs_arr_64); |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 131 | static constexpr ArrayRef<const RegStorage> reserved_regs_32(reserved_regs_arr_32); |
| 132 | static constexpr ArrayRef<const RegStorage> reserved_regs_64(reserved_regs_arr_64); |
| 133 | static constexpr ArrayRef<const RegStorage> reserved_regs_64q(reserved_regs_arr_64q); |
| 134 | static constexpr ArrayRef<const RegStorage> core_temps_32(core_temps_arr_32); |
| 135 | static constexpr ArrayRef<const RegStorage> core_temps_64(core_temps_arr_64); |
| 136 | static constexpr ArrayRef<const RegStorage> core_temps_64q(core_temps_arr_64q); |
| 137 | static constexpr ArrayRef<const RegStorage> sp_temps_32(sp_temps_arr_32); |
| 138 | static constexpr ArrayRef<const RegStorage> sp_temps_64(sp_temps_arr_64); |
| 139 | static constexpr ArrayRef<const RegStorage> dp_temps_32(dp_temps_arr_32); |
| 140 | static constexpr ArrayRef<const RegStorage> dp_temps_64(dp_temps_arr_64); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 141 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 142 | static constexpr ArrayRef<const RegStorage> xp_temps_32(xp_temps_arr_32); |
| 143 | static constexpr ArrayRef<const RegStorage> xp_temps_64(xp_temps_arr_64); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 144 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 145 | RegLocation X86Mir2Lir::LocCReturn() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 146 | return x86_loc_c_return; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 147 | } |
| 148 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 149 | RegLocation X86Mir2Lir::LocCReturnRef() { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 150 | return cu_->target64 ? x86_64_loc_c_return_ref : x86_loc_c_return_ref; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 153 | RegLocation X86Mir2Lir::LocCReturnWide() { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 154 | return cu_->target64 ? x86_64_loc_c_return_wide : x86_loc_c_return_wide; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 155 | } |
| 156 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 157 | RegLocation X86Mir2Lir::LocCReturnFloat() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 158 | return x86_loc_c_return_float; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 159 | } |
| 160 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 161 | RegLocation X86Mir2Lir::LocCReturnDouble() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 162 | return x86_loc_c_return_double; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 163 | } |
| 164 | |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 165 | // 32-bit reg storage locations for 32-bit targets. |
| 166 | static const RegStorage RegStorage32FromSpecialTargetRegister_Target32[] { |
| 167 | RegStorage::InvalidReg(), // kSelf - Thread pointer. |
| 168 | RegStorage::InvalidReg(), // kSuspend - Used to reduce suspend checks for some targets. |
| 169 | RegStorage::InvalidReg(), // kLr - no register as the return address is pushed on entry. |
| 170 | RegStorage::InvalidReg(), // kPc - not exposed on X86 see kX86StartOfMethod. |
| 171 | rs_rX86_SP_32, // kSp |
| 172 | rs_rAX, // kArg0 |
| 173 | rs_rCX, // kArg1 |
| 174 | rs_rDX, // kArg2 |
| 175 | rs_rBX, // kArg3 |
| 176 | RegStorage::InvalidReg(), // kArg4 |
| 177 | RegStorage::InvalidReg(), // kArg5 |
| 178 | RegStorage::InvalidReg(), // kArg6 |
| 179 | RegStorage::InvalidReg(), // kArg7 |
| 180 | rs_rAX, // kFArg0 |
| 181 | rs_rCX, // kFArg1 |
| 182 | rs_rDX, // kFArg2 |
| 183 | rs_rBX, // kFArg3 |
| 184 | RegStorage::InvalidReg(), // kFArg4 |
| 185 | RegStorage::InvalidReg(), // kFArg5 |
| 186 | RegStorage::InvalidReg(), // kFArg6 |
| 187 | RegStorage::InvalidReg(), // kFArg7 |
| 188 | RegStorage::InvalidReg(), // kFArg8 |
| 189 | RegStorage::InvalidReg(), // kFArg9 |
| 190 | RegStorage::InvalidReg(), // kFArg10 |
| 191 | RegStorage::InvalidReg(), // kFArg11 |
| 192 | RegStorage::InvalidReg(), // kFArg12 |
| 193 | RegStorage::InvalidReg(), // kFArg13 |
| 194 | RegStorage::InvalidReg(), // kFArg14 |
| 195 | RegStorage::InvalidReg(), // kFArg15 |
| 196 | rs_rAX, // kRet0 |
| 197 | rs_rDX, // kRet1 |
| 198 | rs_rAX, // kInvokeTgt |
| 199 | rs_rAX, // kHiddenArg - used to hold the method index before copying to fr0. |
| 200 | rs_fr0, // kHiddenFpArg |
| 201 | rs_rCX, // kCount |
| 202 | }; |
| 203 | |
| 204 | // 32-bit reg storage locations for 64-bit targets. |
| 205 | static const RegStorage RegStorage32FromSpecialTargetRegister_Target64[] { |
| 206 | RegStorage::InvalidReg(), // kSelf - Thread pointer. |
| 207 | RegStorage::InvalidReg(), // kSuspend - Used to reduce suspend checks for some targets. |
| 208 | RegStorage::InvalidReg(), // kLr - no register as the return address is pushed on entry. |
| 209 | RegStorage::InvalidReg(), // kPc - TODO: RIP based addressing. |
| 210 | rs_rX86_SP_32, // kSp |
| 211 | rs_rDI, // kArg0 |
| 212 | rs_rSI, // kArg1 |
| 213 | rs_rDX, // kArg2 |
| 214 | rs_rCX, // kArg3 |
| 215 | rs_r8, // kArg4 |
| 216 | rs_r9, // kArg5 |
| 217 | RegStorage::InvalidReg(), // kArg6 |
| 218 | RegStorage::InvalidReg(), // kArg7 |
| 219 | rs_fr0, // kFArg0 |
| 220 | rs_fr1, // kFArg1 |
| 221 | rs_fr2, // kFArg2 |
| 222 | rs_fr3, // kFArg3 |
| 223 | rs_fr4, // kFArg4 |
| 224 | rs_fr5, // kFArg5 |
| 225 | rs_fr6, // kFArg6 |
| 226 | rs_fr7, // kFArg7 |
| 227 | RegStorage::InvalidReg(), // kFArg8 |
| 228 | RegStorage::InvalidReg(), // kFArg9 |
| 229 | RegStorage::InvalidReg(), // kFArg10 |
| 230 | RegStorage::InvalidReg(), // kFArg11 |
| 231 | RegStorage::InvalidReg(), // kFArg12 |
| 232 | RegStorage::InvalidReg(), // kFArg13 |
| 233 | RegStorage::InvalidReg(), // kFArg14 |
| 234 | RegStorage::InvalidReg(), // kFArg15 |
| 235 | rs_rAX, // kRet0 |
| 236 | rs_rDX, // kRet1 |
| 237 | rs_rAX, // kInvokeTgt |
| 238 | rs_rAX, // kHiddenArg |
| 239 | RegStorage::InvalidReg(), // kHiddenFpArg |
| 240 | rs_rCX, // kCount |
| 241 | }; |
| 242 | static_assert(arraysize(RegStorage32FromSpecialTargetRegister_Target32) == |
| 243 | arraysize(RegStorage32FromSpecialTargetRegister_Target64), |
| 244 | "Mismatch in RegStorage array sizes"); |
| 245 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 246 | // Return a target-dependent special register for 32-bit. |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 247 | RegStorage X86Mir2Lir::TargetReg32(SpecialTargetRegister reg) const { |
| 248 | DCHECK_EQ(RegStorage32FromSpecialTargetRegister_Target32[kCount], rs_rCX); |
| 249 | DCHECK_EQ(RegStorage32FromSpecialTargetRegister_Target64[kCount], rs_rCX); |
| 250 | DCHECK_LT(reg, arraysize(RegStorage32FromSpecialTargetRegister_Target32)); |
| 251 | return cu_->target64 ? RegStorage32FromSpecialTargetRegister_Target64[reg] |
| 252 | : RegStorage32FromSpecialTargetRegister_Target32[reg]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 253 | } |
| 254 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 255 | RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 256 | UNUSED(reg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 257 | LOG(FATAL) << "Do not use this function!!!"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 258 | UNREACHABLE(); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 259 | } |
| 260 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 261 | /* |
| 262 | * Decode the register id. |
| 263 | */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 264 | ResourceMask X86Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { |
| 265 | /* Double registers in x86 are just a single FP register. This is always just a single bit. */ |
| 266 | return ResourceMask::Bit( |
| 267 | /* FP register starts at bit position 16 */ |
| 268 | ((reg.IsFloat() || reg.StorageSize() > 8) ? kX86FPReg0 : 0) + reg.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 269 | } |
| 270 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 271 | ResourceMask X86Mir2Lir::GetPCUseDefEncoding() const { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 272 | return kEncodeNone; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 273 | } |
| 274 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 275 | void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 276 | ResourceMask* use_mask, ResourceMask* def_mask) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 277 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 278 | DCHECK(!lir->flags.use_def_invalid); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 279 | |
| 280 | // X86-specific resource map setup here. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 281 | if (flags & REG_USE_SP) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 282 | use_mask->SetBit(kX86RegSP); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | if (flags & REG_DEF_SP) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 286 | def_mask->SetBit(kX86RegSP); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | if (flags & REG_DEFA) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 290 | SetupRegMask(def_mask, rs_rAX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | if (flags & REG_DEFD) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 294 | SetupRegMask(def_mask, rs_rDX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 295 | } |
| 296 | if (flags & REG_USEA) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 297 | SetupRegMask(use_mask, rs_rAX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | if (flags & REG_USEC) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 301 | SetupRegMask(use_mask, rs_rCX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | if (flags & REG_USED) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 305 | SetupRegMask(use_mask, rs_rDX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 306 | } |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 307 | |
| 308 | if (flags & REG_USEB) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 309 | SetupRegMask(use_mask, rs_rBX.GetReg()); |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 310 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 311 | |
| 312 | // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. |
| 313 | if (lir->opcode == kX86RepneScasw) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 314 | SetupRegMask(use_mask, rs_rAX.GetReg()); |
| 315 | SetupRegMask(use_mask, rs_rCX.GetReg()); |
| 316 | SetupRegMask(use_mask, rs_rDI.GetReg()); |
| 317 | SetupRegMask(def_mask, rs_rDI.GetReg()); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 318 | } |
Serguei Katkov | e90501d | 2014-03-12 15:56:54 +0700 | [diff] [blame] | 319 | |
| 320 | if (flags & USE_FP_STACK) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 321 | use_mask->SetBit(kX86FPStack); |
| 322 | def_mask->SetBit(kX86FPStack); |
Serguei Katkov | e90501d | 2014-03-12 15:56:54 +0700 | [diff] [blame] | 323 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | /* For dumping instructions */ |
| 327 | static const char* x86RegName[] = { |
| 328 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", |
| 329 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
| 330 | }; |
| 331 | |
| 332 | static const char* x86CondName[] = { |
| 333 | "O", |
| 334 | "NO", |
| 335 | "B/NAE/C", |
| 336 | "NB/AE/NC", |
| 337 | "Z/EQ", |
| 338 | "NZ/NE", |
| 339 | "BE/NA", |
| 340 | "NBE/A", |
| 341 | "S", |
| 342 | "NS", |
| 343 | "P/PE", |
| 344 | "NP/PO", |
| 345 | "L/NGE", |
| 346 | "NL/GE", |
| 347 | "LE/NG", |
| 348 | "NLE/G" |
| 349 | }; |
| 350 | |
| 351 | /* |
| 352 | * Interpret a format string and build a string no longer than size |
| 353 | * See format key in Assemble.cc. |
| 354 | */ |
| 355 | std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { |
| 356 | std::string buf; |
| 357 | size_t i = 0; |
| 358 | size_t fmt_len = strlen(fmt); |
| 359 | while (i < fmt_len) { |
| 360 | if (fmt[i] != '!') { |
| 361 | buf += fmt[i]; |
| 362 | i++; |
| 363 | } else { |
| 364 | i++; |
| 365 | DCHECK_LT(i, fmt_len); |
| 366 | char operand_number_ch = fmt[i]; |
| 367 | i++; |
| 368 | if (operand_number_ch == '!') { |
| 369 | buf += "!"; |
| 370 | } else { |
| 371 | int operand_number = operand_number_ch - '0'; |
| 372 | DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. |
| 373 | DCHECK_LT(i, fmt_len); |
| 374 | int operand = lir->operands[operand_number]; |
| 375 | switch (fmt[i]) { |
| 376 | case 'c': |
| 377 | DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); |
| 378 | buf += x86CondName[operand]; |
| 379 | break; |
| 380 | case 'd': |
| 381 | buf += StringPrintf("%d", operand); |
| 382 | break; |
Yixin Shou | 5192cbb | 2014-07-01 13:48:17 -0400 | [diff] [blame] | 383 | case 'q': { |
| 384 | int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 | |
| 385 | static_cast<uint32_t>(lir->operands[operand_number+1])); |
| 386 | buf +=StringPrintf("%" PRId64, value); |
Haitao Feng | e70f179 | 2014-08-09 08:31:02 +0800 | [diff] [blame] | 387 | break; |
Yixin Shou | 5192cbb | 2014-07-01 13:48:17 -0400 | [diff] [blame] | 388 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 389 | case 'p': { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 390 | EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 391 | buf += StringPrintf("0x%08x", tab_rec->offset); |
| 392 | break; |
| 393 | } |
| 394 | case 'r': |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 395 | if (RegStorage::IsFloat(operand)) { |
| 396 | int fp_reg = RegStorage::RegNum(operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 397 | buf += StringPrintf("xmm%d", fp_reg); |
| 398 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 399 | int reg_num = RegStorage::RegNum(operand); |
| 400 | DCHECK_LT(static_cast<size_t>(reg_num), sizeof(x86RegName)); |
| 401 | buf += x86RegName[reg_num]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 402 | } |
| 403 | break; |
| 404 | case 't': |
Ian Rogers | 107c31e | 2014-01-23 20:55:29 -0800 | [diff] [blame] | 405 | buf += StringPrintf("0x%08" PRIxPTR " (L%p)", |
| 406 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, |
| 407 | lir->target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 408 | break; |
| 409 | default: |
| 410 | buf += StringPrintf("DecodeError '%c'", fmt[i]); |
| 411 | break; |
| 412 | } |
| 413 | i++; |
| 414 | } |
| 415 | } |
| 416 | } |
| 417 | return buf; |
| 418 | } |
| 419 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 420 | void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 421 | char buf[256]; |
| 422 | buf[0] = 0; |
| 423 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 424 | if (mask.Equals(kEncodeAll)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 425 | strcpy(buf, "all"); |
| 426 | } else { |
| 427 | char num[8]; |
| 428 | int i; |
| 429 | |
| 430 | for (i = 0; i < kX86RegEnd; i++) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 431 | if (mask.HasBit(i)) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 432 | snprintf(num, arraysize(num), "%d ", i); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 433 | strcat(buf, num); |
| 434 | } |
| 435 | } |
| 436 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 437 | if (mask.HasBit(ResourceMask::kCCode)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 438 | strcat(buf, "cc "); |
| 439 | } |
| 440 | /* Memory bits */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 441 | if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 442 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 443 | DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), |
| 444 | (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 445 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 446 | if (mask.HasBit(ResourceMask::kLiteral)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 447 | strcat(buf, "lit "); |
| 448 | } |
| 449 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 450 | if (mask.HasBit(ResourceMask::kHeapRef)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 451 | strcat(buf, "heap "); |
| 452 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 453 | if (mask.HasBit(ResourceMask::kMustNotAlias)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 454 | strcat(buf, "noalias "); |
| 455 | } |
| 456 | } |
| 457 | if (buf[0]) { |
| 458 | LOG(INFO) << prefix << ": " << buf; |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | void X86Mir2Lir::AdjustSpillMask() { |
| 463 | // Adjustment for LR spilling, x86 has no LR so nothing to do here |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 464 | core_spill_mask_ |= (1 << rs_rRET.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 465 | num_core_spills_++; |
| 466 | } |
| 467 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 468 | RegStorage X86Mir2Lir::AllocateByteRegister() { |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 469 | RegStorage reg = AllocTypedTemp(false, kCoreReg); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 470 | if (!cu_->target64) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 471 | DCHECK_LT(reg.GetRegNum(), rs_rX86_SP_32.GetRegNum()); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 472 | } |
| 473 | return reg; |
| 474 | } |
| 475 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 476 | RegStorage X86Mir2Lir::Get128BitRegister(RegStorage reg) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 477 | return GetRegInfo(reg)->Master()->GetReg(); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 478 | } |
| 479 | |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 480 | bool X86Mir2Lir::IsByteRegister(RegStorage reg) const { |
| 481 | return cu_->target64 || reg.GetRegNum() < rs_rX86_SP_32.GetRegNum(); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 482 | } |
| 483 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 484 | /* Clobber all regs that might be used by an external C call */ |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 485 | void X86Mir2Lir::ClobberCallerSave() { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 486 | if (cu_->target64) { |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 487 | Clobber(rs_rAX); |
| 488 | Clobber(rs_rCX); |
| 489 | Clobber(rs_rDX); |
| 490 | Clobber(rs_rSI); |
| 491 | Clobber(rs_rDI); |
| 492 | |
Chao-ying Fu | 35ec2b5 | 2014-06-16 16:40:31 -0700 | [diff] [blame] | 493 | Clobber(rs_r8); |
| 494 | Clobber(rs_r9); |
| 495 | Clobber(rs_r10); |
| 496 | Clobber(rs_r11); |
| 497 | |
| 498 | Clobber(rs_fr8); |
| 499 | Clobber(rs_fr9); |
| 500 | Clobber(rs_fr10); |
| 501 | Clobber(rs_fr11); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 502 | } else { |
| 503 | Clobber(rs_rAX); |
| 504 | Clobber(rs_rCX); |
| 505 | Clobber(rs_rDX); |
| 506 | Clobber(rs_rBX); |
Chao-ying Fu | 35ec2b5 | 2014-06-16 16:40:31 -0700 | [diff] [blame] | 507 | } |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 508 | |
| 509 | Clobber(rs_fr0); |
| 510 | Clobber(rs_fr1); |
| 511 | Clobber(rs_fr2); |
| 512 | Clobber(rs_fr3); |
| 513 | Clobber(rs_fr4); |
| 514 | Clobber(rs_fr5); |
| 515 | Clobber(rs_fr6); |
| 516 | Clobber(rs_fr7); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 517 | } |
| 518 | |
| 519 | RegLocation X86Mir2Lir::GetReturnWideAlt() { |
| 520 | RegLocation res = LocCReturnWide(); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 521 | DCHECK_EQ(res.reg.GetLowReg(), rs_rAX.GetReg()); |
| 522 | DCHECK_EQ(res.reg.GetHighReg(), rs_rDX.GetReg()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 523 | Clobber(rs_rAX); |
| 524 | Clobber(rs_rDX); |
| 525 | MarkInUse(rs_rAX); |
| 526 | MarkInUse(rs_rDX); |
| 527 | MarkWide(res.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 528 | return res; |
| 529 | } |
| 530 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 531 | RegLocation X86Mir2Lir::GetReturnAlt() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 532 | RegLocation res = LocCReturn(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 533 | res.reg.SetReg(rs_rDX.GetReg()); |
| 534 | Clobber(rs_rDX); |
| 535 | MarkInUse(rs_rDX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 536 | return res; |
| 537 | } |
| 538 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 539 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 540 | void X86Mir2Lir::LockCallTemps() { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 541 | LockTemp(TargetReg32(kArg0)); |
| 542 | LockTemp(TargetReg32(kArg1)); |
| 543 | LockTemp(TargetReg32(kArg2)); |
| 544 | LockTemp(TargetReg32(kArg3)); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 545 | if (cu_->target64) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 546 | LockTemp(TargetReg32(kArg4)); |
| 547 | LockTemp(TargetReg32(kArg5)); |
| 548 | LockTemp(TargetReg32(kFArg0)); |
| 549 | LockTemp(TargetReg32(kFArg1)); |
| 550 | LockTemp(TargetReg32(kFArg2)); |
| 551 | LockTemp(TargetReg32(kFArg3)); |
| 552 | LockTemp(TargetReg32(kFArg4)); |
| 553 | LockTemp(TargetReg32(kFArg5)); |
| 554 | LockTemp(TargetReg32(kFArg6)); |
| 555 | LockTemp(TargetReg32(kFArg7)); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 556 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 557 | } |
| 558 | |
| 559 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 560 | void X86Mir2Lir::FreeCallTemps() { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 561 | FreeTemp(TargetReg32(kArg0)); |
| 562 | FreeTemp(TargetReg32(kArg1)); |
| 563 | FreeTemp(TargetReg32(kArg2)); |
| 564 | FreeTemp(TargetReg32(kArg3)); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 565 | if (cu_->target64) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 566 | FreeTemp(TargetReg32(kArg4)); |
| 567 | FreeTemp(TargetReg32(kArg5)); |
| 568 | FreeTemp(TargetReg32(kFArg0)); |
| 569 | FreeTemp(TargetReg32(kFArg1)); |
| 570 | FreeTemp(TargetReg32(kFArg2)); |
| 571 | FreeTemp(TargetReg32(kFArg3)); |
| 572 | FreeTemp(TargetReg32(kFArg4)); |
| 573 | FreeTemp(TargetReg32(kFArg5)); |
| 574 | FreeTemp(TargetReg32(kFArg6)); |
| 575 | FreeTemp(TargetReg32(kFArg7)); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 576 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 577 | } |
| 578 | |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 579 | bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { |
| 580 | switch (opcode) { |
| 581 | case kX86LockCmpxchgMR: |
| 582 | case kX86LockCmpxchgAR: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 583 | case kX86LockCmpxchg64M: |
| 584 | case kX86LockCmpxchg64A: |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 585 | case kX86XchgMR: |
| 586 | case kX86Mfence: |
| 587 | // Atomic memory instructions provide full barrier. |
| 588 | return true; |
| 589 | default: |
| 590 | break; |
| 591 | } |
| 592 | |
| 593 | // Conservative if cannot prove it provides full barrier. |
| 594 | return false; |
| 595 | } |
| 596 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 597 | bool X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { |
Elliott Hughes | 8366ca0 | 2014-11-17 12:02:05 -0800 | [diff] [blame^] | 598 | if (!cu_->GetInstructionSetFeatures()->IsSmp()) { |
| 599 | return false; |
| 600 | } |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 601 | // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. |
| 602 | LIR* mem_barrier = last_lir_insn_; |
| 603 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 604 | bool ret = false; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 605 | /* |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 606 | * According to the JSR-133 Cookbook, for x86 only StoreLoad/AnyAny barriers need memory fence. |
| 607 | * All other barriers (LoadAny, AnyStore, StoreStore) are nops due to the x86 memory model. |
| 608 | * For those cases, all we need to ensure is that there is a scheduling barrier in place. |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 609 | */ |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 610 | if (barrier_kind == kAnyAny) { |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 611 | // If no LIR exists already that can be used a barrier, then generate an mfence. |
| 612 | if (mem_barrier == nullptr) { |
| 613 | mem_barrier = NewLIR0(kX86Mfence); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 614 | ret = true; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 615 | } |
| 616 | |
| 617 | // If last instruction does not provide full barrier, then insert an mfence. |
| 618 | if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { |
| 619 | mem_barrier = NewLIR0(kX86Mfence); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 620 | ret = true; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 621 | } |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 622 | } else if (barrier_kind == kNTStoreStore) { |
| 623 | mem_barrier = NewLIR0(kX86Sfence); |
| 624 | ret = true; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | // Now ensure that a scheduling barrier is in place. |
| 628 | if (mem_barrier == nullptr) { |
| 629 | GenBarrier(); |
| 630 | } else { |
| 631 | // Mark as a scheduling barrier. |
| 632 | DCHECK(!mem_barrier->flags.use_def_invalid); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 633 | mem_barrier->u.m.def_mask = &kEncodeAll; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 634 | } |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 635 | return ret; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 636 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 637 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 638 | void X86Mir2Lir::CompilerInitializeRegAlloc() { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 639 | if (cu_->target64) { |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 640 | reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs_64, core_regs_64q, sp_regs_64, |
| 641 | dp_regs_64, reserved_regs_64, reserved_regs_64q, |
| 642 | core_temps_64, core_temps_64q, |
| 643 | sp_temps_64, dp_temps_64)); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 644 | } else { |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 645 | reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, sp_regs_32, |
| 646 | dp_regs_32, reserved_regs_32, empty_pool, |
| 647 | core_temps_32, empty_pool, |
| 648 | sp_temps_32, dp_temps_32)); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 649 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 650 | |
| 651 | // Target-specific adjustments. |
| 652 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 653 | // Add in XMM registers. |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 654 | const ArrayRef<const RegStorage> *xp_regs = cu_->target64 ? &xp_regs_64 : &xp_regs_32; |
| 655 | for (RegStorage reg : *xp_regs) { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 656 | RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 657 | reginfo_map_[reg.GetReg()] = info; |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 658 | } |
| 659 | const ArrayRef<const RegStorage> *xp_temps = cu_->target64 ? &xp_temps_64 : &xp_temps_32; |
| 660 | for (RegStorage reg : *xp_temps) { |
| 661 | RegisterInfo* xp_reg_info = GetRegInfo(reg); |
| 662 | xp_reg_info->SetIsTemp(true); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 663 | } |
| 664 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 665 | // Alias single precision xmm to double xmms. |
| 666 | // TODO: as needed, add larger vector sizes - alias all to the largest. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 667 | for (RegisterInfo* info : reg_pool_->sp_regs_) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 668 | int sp_reg_num = info->GetReg().GetRegNum(); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 669 | RegStorage xp_reg = RegStorage::Solo128(sp_reg_num); |
| 670 | RegisterInfo* xp_reg_info = GetRegInfo(xp_reg); |
| 671 | // 128-bit xmm vector register's master storage should refer to itself. |
| 672 | DCHECK_EQ(xp_reg_info, xp_reg_info->Master()); |
| 673 | |
| 674 | // Redirect 32-bit vector's master storage to 128-bit vector. |
| 675 | info->SetMaster(xp_reg_info); |
| 676 | |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 677 | RegStorage dp_reg = RegStorage::FloatSolo64(sp_reg_num); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 678 | RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 679 | // Redirect 64-bit vector's master storage to 128-bit vector. |
| 680 | dp_reg_info->SetMaster(xp_reg_info); |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 681 | // Singles should show a single 32-bit mask bit, at first referring to the low half. |
| 682 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 683 | } |
| 684 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 685 | if (cu_->target64) { |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 686 | // Alias 32bit W registers to corresponding 64bit X registers. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 687 | for (RegisterInfo* info : reg_pool_->core_regs_) { |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 688 | int x_reg_num = info->GetReg().GetRegNum(); |
| 689 | RegStorage x_reg = RegStorage::Solo64(x_reg_num); |
| 690 | RegisterInfo* x_reg_info = GetRegInfo(x_reg); |
| 691 | // 64bit X register's master storage should refer to itself. |
| 692 | DCHECK_EQ(x_reg_info, x_reg_info->Master()); |
| 693 | // Redirect 32bit W master storage to 64bit X. |
| 694 | info->SetMaster(x_reg_info); |
| 695 | // 32bit W should show a single 32-bit mask bit, at first referring to the low half. |
| 696 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 697 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 698 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 699 | |
| 700 | // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. |
| 701 | // TODO: adjust for x86/hard float calling convention. |
| 702 | reg_pool_->next_core_reg_ = 2; |
| 703 | reg_pool_->next_sp_reg_ = 2; |
| 704 | reg_pool_->next_dp_reg_ = 1; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 705 | } |
| 706 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 707 | int X86Mir2Lir::VectorRegisterSize() { |
| 708 | return 128; |
| 709 | } |
| 710 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 711 | int X86Mir2Lir::NumReservableVectorRegisters(bool long_or_fp) { |
| 712 | int num_vector_temps = cu_->target64 ? xp_temps_64.size() : xp_temps_32.size(); |
| 713 | |
| 714 | // Leave a few temps for use by backend as scratch. |
| 715 | return long_or_fp ? num_vector_temps - 2 : num_vector_temps - 1; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 716 | } |
| 717 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 718 | void X86Mir2Lir::SpillCoreRegs() { |
| 719 | if (num_core_spills_ == 0) { |
| 720 | return; |
| 721 | } |
| 722 | // Spill mask not including fake return address register |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 723 | uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 724 | int offset = |
| 725 | frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 726 | OpSize size = cu_->target64 ? k64 : k32; |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 727 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 728 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 729 | if (mask & 0x1) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 730 | StoreBaseDisp(rs_rSP, offset, |
| 731 | cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg), |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 732 | size, kNotVolatile); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 733 | offset += GetInstructionSetPointerSize(cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 734 | } |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | void X86Mir2Lir::UnSpillCoreRegs() { |
| 739 | if (num_core_spills_ == 0) { |
| 740 | return; |
| 741 | } |
| 742 | // Spill mask not including fake return address register |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 743 | uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 744 | int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 745 | OpSize size = cu_->target64 ? k64 : k32; |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 746 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 747 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 748 | if (mask & 0x1) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 749 | LoadBaseDisp(rs_rSP, offset, cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg), |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 750 | size, kNotVolatile); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 751 | offset += GetInstructionSetPointerSize(cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 752 | } |
| 753 | } |
| 754 | } |
| 755 | |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 756 | void X86Mir2Lir::SpillFPRegs() { |
| 757 | if (num_fp_spills_ == 0) { |
| 758 | return; |
| 759 | } |
| 760 | uint32_t mask = fp_spill_mask_; |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 761 | int offset = frame_size_ - |
| 762 | (GetInstructionSetPointerSize(cu_->instruction_set) * (num_fp_spills_ + num_core_spills_)); |
| 763 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 764 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 765 | if (mask & 0x1) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 766 | StoreBaseDisp(rs_rSP, offset, RegStorage::FloatSolo64(reg), k64, kNotVolatile); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 767 | offset += sizeof(double); |
| 768 | } |
| 769 | } |
| 770 | } |
| 771 | void X86Mir2Lir::UnSpillFPRegs() { |
| 772 | if (num_fp_spills_ == 0) { |
| 773 | return; |
| 774 | } |
| 775 | uint32_t mask = fp_spill_mask_; |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 776 | int offset = frame_size_ - |
| 777 | (GetInstructionSetPointerSize(cu_->instruction_set) * (num_fp_spills_ + num_core_spills_)); |
| 778 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 779 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 780 | if (mask & 0x1) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 781 | LoadBaseDisp(rs_rSP, offset, RegStorage::FloatSolo64(reg), |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 782 | k64, kNotVolatile); |
| 783 | offset += sizeof(double); |
| 784 | } |
| 785 | } |
| 786 | } |
| 787 | |
| 788 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 789 | bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 790 | return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); |
| 791 | } |
| 792 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 793 | RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 794 | // X86_64 can handle any size. |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 795 | if (cu_->target64) { |
Chao-ying Fu | 06839f8 | 2014-08-14 15:59:17 -0700 | [diff] [blame] | 796 | return RegClassBySize(size); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 797 | } |
| 798 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 799 | if (UNLIKELY(is_volatile)) { |
| 800 | // On x86, atomic 64-bit load/store requires an fp register. |
| 801 | // Smaller aligned load/store is atomic for both core and fp registers. |
| 802 | if (size == k64 || size == kDouble) { |
| 803 | return kFPReg; |
| 804 | } |
| 805 | } |
| 806 | return RegClassBySize(size); |
| 807 | } |
| 808 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 809 | X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 810 | : Mir2Lir(cu, mir_graph, arena), |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 811 | base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false), |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 812 | method_address_insns_(arena->Adapter()), |
| 813 | class_type_address_insns_(arena->Adapter()), |
| 814 | call_method_insns_(arena->Adapter()), |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 815 | stack_decrement_(nullptr), stack_increment_(nullptr), |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 816 | const_vectors_(nullptr) { |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 817 | method_address_insns_.reserve(100); |
| 818 | class_type_address_insns_.reserve(100); |
| 819 | call_method_insns_.reserve(100); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 820 | store_method_addr_used_ = false; |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 821 | for (int i = 0; i < kX86Last; i++) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 822 | DCHECK_EQ(X86Mir2Lir::EncodingMap[i].opcode, i) |
| 823 | << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name |
| 824 | << " is wrong: expecting " << i << ", seeing " |
| 825 | << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 826 | } |
| 827 | } |
| 828 | |
| 829 | Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 830 | ArenaAllocator* const arena) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 831 | return new X86Mir2Lir(cu, mir_graph, arena); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 832 | } |
| 833 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 834 | // Not used in x86(-64) |
| 835 | RegStorage X86Mir2Lir::LoadHelper(QuickEntrypointEnum trampoline) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 836 | UNUSED(trampoline); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 837 | LOG(FATAL) << "Unexpected use of LoadHelper in x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 838 | UNREACHABLE(); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 839 | } |
| 840 | |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 841 | LIR* X86Mir2Lir::CheckSuspendUsingLoad() { |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 842 | // First load the pointer in fs:[suspend-trigger] into eax |
| 843 | // Then use a test instruction to indirect via that address. |
Dave Allison | dfd3b47 | 2014-07-16 16:04:32 -0700 | [diff] [blame] | 844 | if (cu_->target64) { |
| 845 | NewLIR2(kX86Mov64RT, rs_rAX.GetReg(), |
| 846 | Thread::ThreadSuspendTriggerOffset<8>().Int32Value()); |
| 847 | } else { |
| 848 | NewLIR2(kX86Mov32RT, rs_rAX.GetReg(), |
| 849 | Thread::ThreadSuspendTriggerOffset<4>().Int32Value()); |
| 850 | } |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 851 | return NewLIR3(kX86Test32RM, rs_rAX.GetReg(), rs_rAX.GetReg(), 0); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 852 | } |
| 853 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 854 | uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 855 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 856 | return X86Mir2Lir::EncodingMap[opcode].flags; |
| 857 | } |
| 858 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 859 | const char* X86Mir2Lir::GetTargetInstName(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 860 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 861 | return X86Mir2Lir::EncodingMap[opcode].name; |
| 862 | } |
| 863 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 864 | const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 865 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 866 | return X86Mir2Lir::EncodingMap[opcode].fmt; |
| 867 | } |
| 868 | |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 869 | void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { |
| 870 | // Can we do this directly to memory? |
| 871 | rl_dest = UpdateLocWide(rl_dest); |
| 872 | if ((rl_dest.location == kLocDalvikFrame) || |
| 873 | (rl_dest.location == kLocCompilerTemp)) { |
| 874 | int32_t val_lo = Low32Bits(value); |
| 875 | int32_t val_hi = High32Bits(value); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 876 | int r_base = rs_rX86_SP_32.GetReg(); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 877 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 878 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 879 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 880 | LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 881 | AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, |
| 882 | false /* is_load */, true /* is64bit */); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 883 | store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 884 | AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, |
| 885 | false /* is_load */, true /* is64bit */); |
| 886 | return; |
| 887 | } |
| 888 | |
| 889 | // Just use the standard code to do the generation. |
| 890 | Mir2Lir::GenConstWide(rl_dest, value); |
| 891 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 892 | |
| 893 | // TODO: Merge with existing RegLocation dumper in vreg_analysis.cc |
| 894 | void X86Mir2Lir::DumpRegLocation(RegLocation loc) { |
| 895 | LOG(INFO) << "location: " << loc.location << ',' |
| 896 | << (loc.wide ? " w" : " ") |
| 897 | << (loc.defined ? " D" : " ") |
| 898 | << (loc.is_const ? " c" : " ") |
| 899 | << (loc.fp ? " F" : " ") |
| 900 | << (loc.core ? " C" : " ") |
| 901 | << (loc.ref ? " r" : " ") |
| 902 | << (loc.high_word ? " h" : " ") |
| 903 | << (loc.home ? " H" : " ") |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 904 | << ", low: " << static_cast<int>(loc.reg.GetLowReg()) |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 905 | << ", high: " << static_cast<int>(loc.reg.GetHighReg()) |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 906 | << ", s_reg: " << loc.s_reg_low |
| 907 | << ", orig: " << loc.orig_sreg; |
| 908 | } |
| 909 | |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 910 | void X86Mir2Lir::Materialize() { |
| 911 | // A good place to put the analysis before starting. |
| 912 | AnalyzeMIR(); |
| 913 | |
| 914 | // Now continue with regular code generation. |
| 915 | Mir2Lir::Materialize(); |
| 916 | } |
| 917 | |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 918 | void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 919 | SpecialTargetRegister symbolic_reg) { |
| 920 | /* |
| 921 | * For x86, just generate a 32 bit move immediate instruction, that will be filled |
| 922 | * in at 'link time'. For now, put a unique value based on target to ensure that |
| 923 | * code deduplication works. |
| 924 | */ |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 925 | int target_method_idx = target_method.dex_method_index; |
| 926 | const DexFile* target_dex_file = target_method.dex_file; |
| 927 | const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); |
| 928 | uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 929 | |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 930 | // Generate the move instruction with the unique pointer and save index, dex_file, and type. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 931 | LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, |
| 932 | TargetReg(symbolic_reg, kNotWide).GetReg(), |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 933 | static_cast<int>(target_method_id_ptr), target_method_idx, |
| 934 | WrapPointer(const_cast<DexFile*>(target_dex_file)), type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 935 | AppendLIR(move); |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 936 | method_address_insns_.push_back(move); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 937 | } |
| 938 | |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 939 | void X86Mir2Lir::LoadClassType(const DexFile& dex_file, uint32_t type_idx, |
| 940 | SpecialTargetRegister symbolic_reg) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 941 | /* |
| 942 | * For x86, just generate a 32 bit move immediate instruction, that will be filled |
| 943 | * in at 'link time'. For now, put a unique value based on target to ensure that |
| 944 | * code deduplication works. |
| 945 | */ |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 946 | const DexFile::TypeId& id = dex_file.GetTypeId(type_idx); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 947 | uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); |
| 948 | |
| 949 | // Generate the move instruction with the unique pointer and save index and type. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 950 | LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, |
| 951 | TargetReg(symbolic_reg, kNotWide).GetReg(), |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 952 | static_cast<int>(ptr), type_idx, |
| 953 | WrapPointer(const_cast<DexFile*>(&dex_file))); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 954 | AppendLIR(move); |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 955 | class_type_address_insns_.push_back(move); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 956 | } |
| 957 | |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 958 | LIR* X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 959 | /* |
| 960 | * For x86, just generate a 32 bit call relative instruction, that will be filled |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 961 | * in at 'link time'. |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 962 | */ |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 963 | int target_method_idx = target_method.dex_method_index; |
| 964 | const DexFile* target_dex_file = target_method.dex_file; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 965 | |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 966 | // Generate the call instruction with the unique pointer and save index, dex_file, and type. |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 967 | // NOTE: Method deduplication takes linker patches into account, so we can just pass 0 |
| 968 | // as a placeholder for the offset. |
| 969 | LIR* call = RawLIR(current_dalvik_offset_, kX86CallI, 0, |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 970 | target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 971 | AppendLIR(call); |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 972 | call_method_insns_.push_back(call); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 973 | return call; |
| 974 | } |
| 975 | |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 976 | static LIR* GenInvokeNoInlineCall(Mir2Lir* mir_to_lir, InvokeType type) { |
| 977 | QuickEntrypointEnum trampoline; |
| 978 | switch (type) { |
| 979 | case kInterface: |
| 980 | trampoline = kQuickInvokeInterfaceTrampolineWithAccessCheck; |
| 981 | break; |
| 982 | case kDirect: |
| 983 | trampoline = kQuickInvokeDirectTrampolineWithAccessCheck; |
| 984 | break; |
| 985 | case kStatic: |
| 986 | trampoline = kQuickInvokeStaticTrampolineWithAccessCheck; |
| 987 | break; |
| 988 | case kSuper: |
| 989 | trampoline = kQuickInvokeSuperTrampolineWithAccessCheck; |
| 990 | break; |
| 991 | case kVirtual: |
| 992 | trampoline = kQuickInvokeVirtualTrampolineWithAccessCheck; |
| 993 | break; |
| 994 | default: |
| 995 | LOG(FATAL) << "Unexpected invoke type"; |
| 996 | trampoline = kQuickInvokeInterfaceTrampolineWithAccessCheck; |
| 997 | } |
| 998 | return mir_to_lir->InvokeTrampoline(kOpBlx, RegStorage::InvalidReg(), trampoline); |
| 999 | } |
| 1000 | |
| 1001 | LIR* X86Mir2Lir::GenCallInsn(const MirMethodLoweringInfo& method_info) { |
| 1002 | LIR* call_insn; |
| 1003 | if (method_info.FastPath()) { |
| 1004 | if (method_info.DirectCode() == static_cast<uintptr_t>(-1)) { |
| 1005 | // We can have the linker fixup a call relative. |
| 1006 | call_insn = CallWithLinkerFixup(method_info.GetTargetMethod(), method_info.GetSharpType()); |
| 1007 | } else { |
| 1008 | call_insn = OpMem(kOpBlx, TargetReg(kArg0, kRef), |
Mathieu Chartier | 2d72101 | 2014-11-10 11:08:06 -0800 | [diff] [blame] | 1009 | mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( |
| 1010 | cu_->target64 ? 8 : 4).Int32Value()); |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 1011 | } |
| 1012 | } else { |
| 1013 | call_insn = GenInvokeNoInlineCall(this, method_info.GetSharpType()); |
| 1014 | } |
| 1015 | return call_insn; |
| 1016 | } |
| 1017 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1018 | void X86Mir2Lir::InstallLiteralPools() { |
| 1019 | // These are handled differently for x86. |
| 1020 | DCHECK(code_literal_list_ == nullptr); |
| 1021 | DCHECK(method_literal_list_ == nullptr); |
| 1022 | DCHECK(class_literal_list_ == nullptr); |
| 1023 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1024 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1025 | if (const_vectors_ != nullptr) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1026 | // Vector literals must be 16-byte aligned. The header that is placed |
| 1027 | // in the code section causes misalignment so we take it into account. |
| 1028 | // Otherwise, we are sure that for x86 method is aligned to 16. |
| 1029 | DCHECK_EQ(GetInstructionSetAlignment(cu_->instruction_set), 16u); |
| 1030 | uint32_t bytes_to_fill = (0x10 - ((code_buffer_.size() + sizeof(OatQuickMethodHeader)) & 0xF)) & 0xF; |
| 1031 | while (bytes_to_fill > 0) { |
| 1032 | code_buffer_.push_back(0); |
| 1033 | bytes_to_fill--; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1034 | } |
| 1035 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1036 | for (LIR *p = const_vectors_; p != nullptr; p = p->next) { |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1037 | PushWord(&code_buffer_, p->operands[0]); |
| 1038 | PushWord(&code_buffer_, p->operands[1]); |
| 1039 | PushWord(&code_buffer_, p->operands[2]); |
| 1040 | PushWord(&code_buffer_, p->operands[3]); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1041 | } |
| 1042 | } |
| 1043 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1044 | // Handle the fixups for methods. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 1045 | for (LIR* p : method_address_insns_) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1046 | DCHECK_EQ(p->opcode, kX86Mov32RI); |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1047 | uint32_t target_method_idx = p->operands[2]; |
| 1048 | const DexFile* target_dex_file = |
| 1049 | reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1050 | |
| 1051 | // The offset to patch is the last 4 bytes of the instruction. |
| 1052 | int patch_offset = p->offset + p->flags.size - 4; |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 1053 | patches_.push_back(LinkerPatch::MethodPatch(patch_offset, |
| 1054 | target_dex_file, target_method_idx)); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1055 | } |
| 1056 | |
| 1057 | // Handle the fixups for class types. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 1058 | for (LIR* p : class_type_address_insns_) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1059 | DCHECK_EQ(p->opcode, kX86Mov32RI); |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 1060 | |
| 1061 | const DexFile* class_dex_file = |
| 1062 | reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 1063 | uint32_t target_type_idx = p->operands[2]; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1064 | |
| 1065 | // The offset to patch is the last 4 bytes of the instruction. |
| 1066 | int patch_offset = p->offset + p->flags.size - 4; |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 1067 | patches_.push_back(LinkerPatch::TypePatch(patch_offset, |
| 1068 | class_dex_file, target_type_idx)); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1069 | } |
| 1070 | |
| 1071 | // And now the PC-relative calls to methods. |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 1072 | patches_.reserve(call_method_insns_.size()); |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 1073 | for (LIR* p : call_method_insns_) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1074 | DCHECK_EQ(p->opcode, kX86CallI); |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1075 | uint32_t target_method_idx = p->operands[1]; |
| 1076 | const DexFile* target_dex_file = |
| 1077 | reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1078 | |
| 1079 | // The offset to patch is the last 4 bytes of the instruction. |
| 1080 | int patch_offset = p->offset + p->flags.size - 4; |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 1081 | patches_.push_back(LinkerPatch::RelativeCodePatch(patch_offset, |
| 1082 | target_dex_file, target_method_idx)); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1083 | } |
| 1084 | |
| 1085 | // And do the normal processing. |
| 1086 | Mir2Lir::InstallLiteralPools(); |
| 1087 | } |
| 1088 | |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1089 | bool X86Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) { |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1090 | RegLocation rl_src = info->args[0]; |
| 1091 | RegLocation rl_srcPos = info->args[1]; |
| 1092 | RegLocation rl_dst = info->args[2]; |
| 1093 | RegLocation rl_dstPos = info->args[3]; |
| 1094 | RegLocation rl_length = info->args[4]; |
| 1095 | if (rl_srcPos.is_const && (mir_graph_->ConstantValue(rl_srcPos) < 0)) { |
| 1096 | return false; |
| 1097 | } |
| 1098 | if (rl_dstPos.is_const && (mir_graph_->ConstantValue(rl_dstPos) < 0)) { |
| 1099 | return false; |
| 1100 | } |
| 1101 | ClobberCallerSave(); |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1102 | LockCallTemps(); // Using fixed registers. |
| 1103 | RegStorage tmp_reg = cu_->target64 ? rs_r11 : rs_rBX; |
| 1104 | LoadValueDirectFixed(rl_src, rs_rAX); |
| 1105 | LoadValueDirectFixed(rl_dst, rs_rCX); |
| 1106 | LIR* src_dst_same = OpCmpBranch(kCondEq, rs_rAX, rs_rCX, nullptr); |
| 1107 | LIR* src_null_branch = OpCmpImmBranch(kCondEq, rs_rAX, 0, nullptr); |
| 1108 | LIR* dst_null_branch = OpCmpImmBranch(kCondEq, rs_rCX, 0, nullptr); |
| 1109 | LoadValueDirectFixed(rl_length, rs_rDX); |
| 1110 | // If the length of the copy is > 128 characters (256 bytes) or negative then go slow path. |
| 1111 | LIR* len_too_big = OpCmpImmBranch(kCondHi, rs_rDX, 128, nullptr); |
| 1112 | LoadValueDirectFixed(rl_src, rs_rAX); |
| 1113 | LoadWordDisp(rs_rAX, mirror::Array::LengthOffset().Int32Value(), rs_rAX); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1114 | LIR* src_bad_len = nullptr; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1115 | LIR* src_bad_off = nullptr; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1116 | LIR* srcPos_negative = nullptr; |
| 1117 | if (!rl_srcPos.is_const) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1118 | LoadValueDirectFixed(rl_srcPos, tmp_reg); |
| 1119 | srcPos_negative = OpCmpImmBranch(kCondLt, tmp_reg, 0, nullptr); |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1120 | // src_pos < src_len |
| 1121 | src_bad_off = OpCmpBranch(kCondLt, rs_rAX, tmp_reg, nullptr); |
| 1122 | // src_len - src_pos < copy_len |
| 1123 | OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); |
| 1124 | src_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1125 | } else { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1126 | int32_t pos_val = mir_graph_->ConstantValue(rl_srcPos.orig_sreg); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1127 | if (pos_val == 0) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1128 | src_bad_len = OpCmpBranch(kCondLt, rs_rAX, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1129 | } else { |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1130 | // src_pos < src_len |
| 1131 | src_bad_off = OpCmpImmBranch(kCondLt, rs_rAX, pos_val, nullptr); |
| 1132 | // src_len - src_pos < copy_len |
| 1133 | OpRegRegImm(kOpSub, tmp_reg, rs_rAX, pos_val); |
| 1134 | src_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1135 | } |
| 1136 | } |
| 1137 | LIR* dstPos_negative = nullptr; |
| 1138 | LIR* dst_bad_len = nullptr; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1139 | LIR* dst_bad_off = nullptr; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1140 | LoadValueDirectFixed(rl_dst, rs_rAX); |
| 1141 | LoadWordDisp(rs_rAX, mirror::Array::LengthOffset().Int32Value(), rs_rAX); |
| 1142 | if (!rl_dstPos.is_const) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1143 | LoadValueDirectFixed(rl_dstPos, tmp_reg); |
| 1144 | dstPos_negative = OpCmpImmBranch(kCondLt, tmp_reg, 0, nullptr); |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1145 | // dst_pos < dst_len |
| 1146 | dst_bad_off = OpCmpBranch(kCondLt, rs_rAX, tmp_reg, nullptr); |
| 1147 | // dst_len - dst_pos < copy_len |
| 1148 | OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); |
| 1149 | dst_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1150 | } else { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1151 | int32_t pos_val = mir_graph_->ConstantValue(rl_dstPos.orig_sreg); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1152 | if (pos_val == 0) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1153 | dst_bad_len = OpCmpBranch(kCondLt, rs_rAX, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1154 | } else { |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1155 | // dst_pos < dst_len |
| 1156 | dst_bad_off = OpCmpImmBranch(kCondLt, rs_rAX, pos_val, nullptr); |
| 1157 | // dst_len - dst_pos < copy_len |
| 1158 | OpRegRegImm(kOpSub, tmp_reg, rs_rAX, pos_val); |
| 1159 | dst_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1160 | } |
| 1161 | } |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1162 | // Everything is checked now. |
| 1163 | LoadValueDirectFixed(rl_src, rs_rAX); |
| 1164 | LoadValueDirectFixed(rl_dst, tmp_reg); |
| 1165 | LoadValueDirectFixed(rl_srcPos, rs_rCX); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1166 | NewLIR5(kX86Lea32RA, rs_rAX.GetReg(), rs_rAX.GetReg(), |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1167 | rs_rCX.GetReg(), 1, mirror::Array::DataOffset(2).Int32Value()); |
| 1168 | // RAX now holds the address of the first src element to be copied. |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1169 | |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1170 | LoadValueDirectFixed(rl_dstPos, rs_rCX); |
| 1171 | NewLIR5(kX86Lea32RA, tmp_reg.GetReg(), tmp_reg.GetReg(), |
| 1172 | rs_rCX.GetReg(), 1, mirror::Array::DataOffset(2).Int32Value() ); |
| 1173 | // RBX now holds the address of the first dst element to be copied. |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1174 | |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1175 | // Check if the number of elements to be copied is odd or even. If odd |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1176 | // then copy the first element (so that the remaining number of elements |
| 1177 | // is even). |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1178 | LoadValueDirectFixed(rl_length, rs_rCX); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1179 | OpRegImm(kOpAnd, rs_rCX, 1); |
| 1180 | LIR* jmp_to_begin_loop = OpCmpImmBranch(kCondEq, rs_rCX, 0, nullptr); |
| 1181 | OpRegImm(kOpSub, rs_rDX, 1); |
| 1182 | LoadBaseIndexedDisp(rs_rAX, rs_rDX, 1, 0, rs_rCX, kSignedHalf); |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1183 | StoreBaseIndexedDisp(tmp_reg, rs_rDX, 1, 0, rs_rCX, kSignedHalf); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1184 | |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1185 | // Since the remaining number of elements is even, we will copy by |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1186 | // two elements at a time. |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1187 | LIR* beginLoop = NewLIR0(kPseudoTargetLabel); |
| 1188 | LIR* jmp_to_ret = OpCmpImmBranch(kCondEq, rs_rDX, 0, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1189 | OpRegImm(kOpSub, rs_rDX, 2); |
| 1190 | LoadBaseIndexedDisp(rs_rAX, rs_rDX, 1, 0, rs_rCX, kSingle); |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1191 | StoreBaseIndexedDisp(tmp_reg, rs_rDX, 1, 0, rs_rCX, kSingle); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1192 | OpUnconditionalBranch(beginLoop); |
| 1193 | LIR *check_failed = NewLIR0(kPseudoTargetLabel); |
| 1194 | LIR* launchpad_branch = OpUnconditionalBranch(nullptr); |
| 1195 | LIR *return_point = NewLIR0(kPseudoTargetLabel); |
| 1196 | jmp_to_ret->target = return_point; |
| 1197 | jmp_to_begin_loop->target = beginLoop; |
| 1198 | src_dst_same->target = check_failed; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1199 | len_too_big->target = check_failed; |
| 1200 | src_null_branch->target = check_failed; |
| 1201 | if (srcPos_negative != nullptr) |
| 1202 | srcPos_negative ->target = check_failed; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1203 | if (src_bad_off != nullptr) |
| 1204 | src_bad_off->target = check_failed; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1205 | if (src_bad_len != nullptr) |
| 1206 | src_bad_len->target = check_failed; |
| 1207 | dst_null_branch->target = check_failed; |
| 1208 | if (dstPos_negative != nullptr) |
| 1209 | dstPos_negative->target = check_failed; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame] | 1210 | if (dst_bad_off != nullptr) |
| 1211 | dst_bad_off->target = check_failed; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1212 | if (dst_bad_len != nullptr) |
| 1213 | dst_bad_len->target = check_failed; |
| 1214 | AddIntrinsicSlowPath(info, launchpad_branch, return_point); |
Serguei Katkov | 9863daf | 2014-09-04 15:21:32 +0700 | [diff] [blame] | 1215 | ClobberCallerSave(); // We must clobber everything because slow path will return here |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1216 | return true; |
| 1217 | } |
| 1218 | |
| 1219 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1220 | /* |
| 1221 | * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, |
| 1222 | * otherwise bails to standard library code. |
| 1223 | */ |
| 1224 | bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1225 | RegLocation rl_obj = info->args[0]; |
| 1226 | RegLocation rl_char = info->args[1]; |
buzbee | a44d4f5 | 2014-03-05 11:26:39 -0800 | [diff] [blame] | 1227 | RegLocation rl_start; // Note: only present in III flavor or IndexOf. |
nikolay serdjuk | 8bd698f | 2014-08-01 09:24:06 +0700 | [diff] [blame] | 1228 | // RBX is promotable in 64-bit mode. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1229 | RegStorage rs_tmp = cu_->target64 ? rs_r11 : rs_rBX; |
| 1230 | int start_value = -1; |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1231 | |
| 1232 | uint32_t char_value = |
| 1233 | rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; |
| 1234 | |
| 1235 | if (char_value > 0xFFFF) { |
| 1236 | // We have to punt to the real String.indexOf. |
| 1237 | return false; |
| 1238 | } |
| 1239 | |
| 1240 | // Okay, we are commited to inlining this. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1241 | // EAX: 16 bit character being searched. |
| 1242 | // ECX: count: number of words to be searched. |
| 1243 | // EDI: String being searched. |
| 1244 | // EDX: temporary during execution. |
| 1245 | // EBX or R11: temporary during execution (depending on mode). |
| 1246 | // REP SCASW: search instruction. |
| 1247 | |
nikolay serdjuk | 8bd698f | 2014-08-01 09:24:06 +0700 | [diff] [blame] | 1248 | FlushAllRegs(); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1249 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1250 | RegLocation rl_return = GetReturn(kCoreReg); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1251 | RegLocation rl_dest = InlineTarget(info); |
| 1252 | |
| 1253 | // Is the string non-NULL? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1254 | LoadValueDirectFixed(rl_obj, rs_rDX); |
| 1255 | GenNullCheck(rs_rDX, info->opt_flags); |
Vladimir Marko | 3bc8615 | 2014-03-13 14:11:28 +0000 | [diff] [blame] | 1256 | info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1257 | |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1258 | LIR *slowpath_branch = nullptr, *length_compare = nullptr; |
| 1259 | |
| 1260 | // We need the value in EAX. |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1261 | if (rl_char.is_const) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1262 | LoadConstantNoClobber(rs_rAX, char_value); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1263 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1264 | // Does the character fit in 16 bits? Compare it at runtime. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1265 | LoadValueDirectFixed(rl_char, rs_rAX); |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 1266 | slowpath_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1267 | } |
| 1268 | |
| 1269 | // From here down, we know that we are looking for a char that fits in 16 bits. |
Mark Mendell | e19c91f | 2014-02-25 08:19:08 -0800 | [diff] [blame] | 1270 | // Location of reference to data array within the String object. |
| 1271 | int value_offset = mirror::String::ValueOffset().Int32Value(); |
| 1272 | // Location of count within the String object. |
| 1273 | int count_offset = mirror::String::CountOffset().Int32Value(); |
| 1274 | // Starting offset within data array. |
| 1275 | int offset_offset = mirror::String::OffsetOffset().Int32Value(); |
| 1276 | // Start of char data with array_. |
| 1277 | int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1278 | |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1279 | // Compute the number of words to search in to rCX. |
| 1280 | Load32Disp(rs_rDX, count_offset, rs_rCX); |
| 1281 | |
Dave Allison | dfd3b47 | 2014-07-16 16:04:32 -0700 | [diff] [blame] | 1282 | // Possible signal here due to null pointer dereference. |
| 1283 | // Note that the signal handler will expect the top word of |
| 1284 | // the stack to be the ArtMethod*. If the PUSH edi instruction |
| 1285 | // below is ahead of the load above then this will not be true |
| 1286 | // and the signal handler will not work. |
| 1287 | MarkPossibleNullPointerException(0); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1288 | |
Dave Allison | dfd3b47 | 2014-07-16 16:04:32 -0700 | [diff] [blame] | 1289 | if (!cu_->target64) { |
nikolay serdjuk | 8bd698f | 2014-08-01 09:24:06 +0700 | [diff] [blame] | 1290 | // EDI is promotable in 32-bit mode. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1291 | NewLIR1(kX86Push32R, rs_rDI.GetReg()); |
| 1292 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1293 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1294 | if (zero_based) { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1295 | // Start index is not present. |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1296 | // We have to handle an empty string. Use special instruction JECXZ. |
| 1297 | length_compare = NewLIR0(kX86Jecxz8); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1298 | |
| 1299 | // Copy the number of words to search in a temporary register. |
| 1300 | // We will use the register at the end to calculate result. |
| 1301 | OpRegReg(kOpMov, rs_tmp, rs_rCX); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1302 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1303 | // Start index is present. |
buzbee | a44d4f5 | 2014-03-05 11:26:39 -0800 | [diff] [blame] | 1304 | rl_start = info->args[2]; |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1305 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1306 | // We have to offset by the start index. |
| 1307 | if (rl_start.is_const) { |
| 1308 | start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); |
| 1309 | start_value = std::max(start_value, 0); |
| 1310 | |
| 1311 | // Is the start > count? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1312 | length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1313 | OpRegImm(kOpMov, rs_rDI, start_value); |
| 1314 | |
| 1315 | // Copy the number of words to search in a temporary register. |
| 1316 | // We will use the register at the end to calculate result. |
| 1317 | OpRegReg(kOpMov, rs_tmp, rs_rCX); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1318 | |
| 1319 | if (start_value != 0) { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1320 | // Decrease the number of words to search by the start index. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1321 | OpRegImm(kOpSub, rs_rCX, start_value); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1322 | } |
| 1323 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1324 | // Handle "start index < 0" case. |
| 1325 | if (!cu_->target64 && rl_start.location != kLocPhysReg) { |
Alexei Zavjalov | a1758d8 | 2014-04-17 01:55:43 +0700 | [diff] [blame] | 1326 | // Load the start index from stack, remembering that we pushed EDI. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1327 | int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); |
Vladimir Marko | 74de63b | 2014-08-19 15:00:34 +0100 | [diff] [blame] | 1328 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1329 | Load32Disp(rs_rX86_SP_32, displacement, rs_rDI); |
Vladimir Marko | 74de63b | 2014-08-19 15:00:34 +0100 | [diff] [blame] | 1330 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1331 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1332 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - 1; |
| 1333 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1334 | } else { |
| 1335 | LoadValueDirectFixed(rl_start, rs_rDI); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1336 | } |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1337 | OpRegReg(kOpXor, rs_tmp, rs_tmp); |
| 1338 | OpRegReg(kOpCmp, rs_rDI, rs_tmp); |
| 1339 | OpCondRegReg(kOpCmov, kCondLt, rs_rDI, rs_tmp); |
| 1340 | |
| 1341 | // The length of the string should be greater than the start index. |
| 1342 | length_compare = OpCmpBranch(kCondLe, rs_rCX, rs_rDI, nullptr); |
| 1343 | |
| 1344 | // Copy the number of words to search in a temporary register. |
| 1345 | // We will use the register at the end to calculate result. |
| 1346 | OpRegReg(kOpMov, rs_tmp, rs_rCX); |
| 1347 | |
| 1348 | // Decrease the number of words to search by the start index. |
| 1349 | OpRegReg(kOpSub, rs_rCX, rs_rDI); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1350 | } |
| 1351 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1352 | |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1353 | // Load the address of the string into EDI. |
| 1354 | // In case of start index we have to add the address to existing value in EDI. |
Mark Mendell | e19c91f | 2014-02-25 08:19:08 -0800 | [diff] [blame] | 1355 | // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1356 | if (zero_based || (!zero_based && rl_start.is_const && start_value == 0)) { |
| 1357 | Load32Disp(rs_rDX, offset_offset, rs_rDI); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1358 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1359 | OpRegMem(kOpAdd, rs_rDI, rs_rDX, offset_offset); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1360 | } |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1361 | OpRegImm(kOpLsl, rs_rDI, 1); |
| 1362 | OpRegMem(kOpAdd, rs_rDI, rs_rDX, value_offset); |
| 1363 | OpRegImm(kOpAdd, rs_rDI, data_offset); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1364 | |
| 1365 | // EDI now contains the start of the string to be searched. |
| 1366 | // We are all prepared to do the search for the character. |
| 1367 | NewLIR0(kX86RepneScasw); |
| 1368 | |
| 1369 | // Did we find a match? |
| 1370 | LIR* failed_branch = OpCondBranch(kCondNe, nullptr); |
| 1371 | |
| 1372 | // yes, we matched. Compute the index of the result. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1373 | OpRegReg(kOpSub, rs_tmp, rs_rCX); |
| 1374 | NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rs_tmp.GetReg(), -1); |
| 1375 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1376 | LIR *all_done = NewLIR1(kX86Jmp8, 0); |
| 1377 | |
| 1378 | // Failed to match; return -1. |
| 1379 | LIR *not_found = NewLIR0(kPseudoTargetLabel); |
| 1380 | length_compare->target = not_found; |
| 1381 | failed_branch->target = not_found; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1382 | LoadConstantNoClobber(rl_return.reg, -1); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1383 | |
| 1384 | // And join up at the end. |
| 1385 | all_done->target = NewLIR0(kPseudoTargetLabel); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1386 | |
| 1387 | if (!cu_->target64) |
| 1388 | NewLIR1(kX86Pop32R, rs_rDI.GetReg()); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1389 | |
| 1390 | // Out of line code returns here. |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 1391 | if (slowpath_branch != nullptr) { |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1392 | LIR *return_point = NewLIR0(kPseudoTargetLabel); |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 1393 | AddIntrinsicSlowPath(info, slowpath_branch, return_point); |
Serguei Katkov | 9863daf | 2014-09-04 15:21:32 +0700 | [diff] [blame] | 1394 | ClobberCallerSave(); // We must clobber everything because slow path will return here |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1395 | } |
| 1396 | |
| 1397 | StoreValue(rl_dest, rl_return); |
| 1398 | return true; |
| 1399 | } |
| 1400 | |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1401 | static bool ARTRegIDToDWARFRegID(bool is_x86_64, int art_reg_id, int* dwarf_reg_id) { |
| 1402 | if (is_x86_64) { |
| 1403 | switch (art_reg_id) { |
Andreas Gampe | bda2722 | 2014-07-30 23:21:36 -0700 | [diff] [blame] | 1404 | case 3 : *dwarf_reg_id = 3; return true; // %rbx |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1405 | // This is the only discrepancy between ART & DWARF register numbering. |
Andreas Gampe | bda2722 | 2014-07-30 23:21:36 -0700 | [diff] [blame] | 1406 | case 5 : *dwarf_reg_id = 6; return true; // %rbp |
| 1407 | case 12: *dwarf_reg_id = 12; return true; // %r12 |
| 1408 | case 13: *dwarf_reg_id = 13; return true; // %r13 |
| 1409 | case 14: *dwarf_reg_id = 14; return true; // %r14 |
| 1410 | case 15: *dwarf_reg_id = 15; return true; // %r15 |
| 1411 | default: return false; // Should not get here |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1412 | } |
| 1413 | } else { |
| 1414 | switch (art_reg_id) { |
Andreas Gampe | bda2722 | 2014-07-30 23:21:36 -0700 | [diff] [blame] | 1415 | case 5: *dwarf_reg_id = 5; return true; // %ebp |
| 1416 | case 6: *dwarf_reg_id = 6; return true; // %esi |
| 1417 | case 7: *dwarf_reg_id = 7; return true; // %edi |
| 1418 | default: return false; // Should not get here |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1419 | } |
| 1420 | } |
| 1421 | } |
| 1422 | |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1423 | std::vector<uint8_t>* X86Mir2Lir::ReturnFrameDescriptionEntry() { |
| 1424 | std::vector<uint8_t>* cfi_info = new std::vector<uint8_t>; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1425 | |
| 1426 | // Generate the FDE for the method. |
| 1427 | DCHECK_NE(data_offset_, 0U); |
| 1428 | |
Yevgeny Rouban | e3ea838 | 2014-08-08 16:29:38 +0700 | [diff] [blame] | 1429 | WriteFDEHeader(cfi_info, cu_->target64); |
| 1430 | WriteFDEAddressRange(cfi_info, data_offset_, cu_->target64); |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1431 | |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1432 | // The instructions in the FDE. |
| 1433 | if (stack_decrement_ != nullptr) { |
| 1434 | // Advance LOC to just past the stack decrement. |
| 1435 | uint32_t pc = NEXT_LIR(stack_decrement_)->offset; |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1436 | DW_CFA_advance_loc(cfi_info, pc); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1437 | |
| 1438 | // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1439 | DW_CFA_def_cfa_offset(cfi_info, frame_size_); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1440 | |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1441 | // Handle register spills |
| 1442 | const uint32_t kSpillInstLen = (cu_->target64) ? 5 : 4; |
| 1443 | const int kDataAlignmentFactor = (cu_->target64) ? -8 : -4; |
| 1444 | uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); |
| 1445 | int offset = -(GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); |
| 1446 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 1447 | if (mask & 0x1) { |
| 1448 | pc += kSpillInstLen; |
| 1449 | |
| 1450 | // Advance LOC to pass this instruction |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1451 | DW_CFA_advance_loc(cfi_info, kSpillInstLen); |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1452 | |
| 1453 | int dwarf_reg_id; |
| 1454 | if (ARTRegIDToDWARFRegID(cu_->target64, reg, &dwarf_reg_id)) { |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1455 | // DW_CFA_offset_extended_sf reg offset |
| 1456 | DW_CFA_offset_extended_sf(cfi_info, dwarf_reg_id, offset / kDataAlignmentFactor); |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1457 | } |
| 1458 | |
| 1459 | offset += GetInstructionSetPointerSize(cu_->instruction_set); |
| 1460 | } |
| 1461 | } |
| 1462 | |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1463 | // We continue with that stack until the epilogue. |
| 1464 | if (stack_increment_ != nullptr) { |
| 1465 | uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1466 | DW_CFA_advance_loc(cfi_info, new_pc - pc); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1467 | |
| 1468 | // We probably have code snippets after the epilogue, so save the |
| 1469 | // current state: DW_CFA_remember_state. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1470 | DW_CFA_remember_state(cfi_info); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1471 | |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1472 | // We have now popped the stack: DW_CFA_def_cfa_offset 4/8. |
| 1473 | // There is only the return PC on the stack now. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1474 | DW_CFA_def_cfa_offset(cfi_info, GetInstructionSetPointerSize(cu_->instruction_set)); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1475 | |
| 1476 | // Everything after that is the same as before the epilogue. |
| 1477 | // Stack bump was followed by RET instruction. |
| 1478 | LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); |
| 1479 | if (post_ret_insn != nullptr) { |
| 1480 | pc = new_pc; |
| 1481 | new_pc = post_ret_insn->offset; |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1482 | DW_CFA_advance_loc(cfi_info, new_pc - pc); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1483 | // Restore the state: DW_CFA_restore_state. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1484 | DW_CFA_restore_state(cfi_info); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1485 | } |
| 1486 | } |
| 1487 | } |
| 1488 | |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1489 | PadCFI(cfi_info); |
Yevgeny Rouban | e3ea838 | 2014-08-08 16:29:38 +0700 | [diff] [blame] | 1490 | WriteCFILength(cfi_info, cu_->target64); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1491 | |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1492 | return cfi_info; |
| 1493 | } |
| 1494 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1495 | void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { |
| 1496 | switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1497 | case kMirOpReserveVectorRegisters: |
| 1498 | ReserveVectorRegisters(mir); |
| 1499 | break; |
| 1500 | case kMirOpReturnVectorRegisters: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1501 | ReturnVectorRegisters(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1502 | break; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1503 | case kMirOpConstVector: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1504 | GenConst128(mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1505 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1506 | case kMirOpMoveVector: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1507 | GenMoveVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1508 | break; |
| 1509 | case kMirOpPackedMultiply: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1510 | GenMultiplyVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1511 | break; |
| 1512 | case kMirOpPackedAddition: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1513 | GenAddVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1514 | break; |
| 1515 | case kMirOpPackedSubtract: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1516 | GenSubtractVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1517 | break; |
| 1518 | case kMirOpPackedShiftLeft: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1519 | GenShiftLeftVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1520 | break; |
| 1521 | case kMirOpPackedSignedShiftRight: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1522 | GenSignedShiftRightVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1523 | break; |
| 1524 | case kMirOpPackedUnsignedShiftRight: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1525 | GenUnsignedShiftRightVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1526 | break; |
| 1527 | case kMirOpPackedAnd: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1528 | GenAndVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1529 | break; |
| 1530 | case kMirOpPackedOr: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1531 | GenOrVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1532 | break; |
| 1533 | case kMirOpPackedXor: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1534 | GenXorVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1535 | break; |
| 1536 | case kMirOpPackedAddReduce: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1537 | GenAddReduceVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1538 | break; |
| 1539 | case kMirOpPackedReduce: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1540 | GenReduceVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1541 | break; |
| 1542 | case kMirOpPackedSet: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1543 | GenSetVector(mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1544 | break; |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 1545 | case kMirOpMemBarrier: |
| 1546 | GenMemBarrier(static_cast<MemBarrierKind>(mir->dalvikInsn.vA)); |
| 1547 | break; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1548 | case kMirOpPackedArrayGet: |
| 1549 | GenPackedArrayGet(bb, mir); |
| 1550 | break; |
| 1551 | case kMirOpPackedArrayPut: |
| 1552 | GenPackedArrayPut(bb, mir); |
| 1553 | break; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1554 | default: |
| 1555 | break; |
| 1556 | } |
| 1557 | } |
| 1558 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1559 | void X86Mir2Lir::ReserveVectorRegisters(MIR* mir) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1560 | for (uint32_t i = mir->dalvikInsn.vA; i <= mir->dalvikInsn.vB; i++) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1561 | RegStorage xp_reg = RegStorage::Solo128(i); |
| 1562 | RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); |
| 1563 | Clobber(xp_reg); |
| 1564 | |
| 1565 | for (RegisterInfo *info = xp_reg_info->GetAliasChain(); |
| 1566 | info != nullptr; |
| 1567 | info = info->GetAliasChain()) { |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 1568 | ArenaVector<RegisterInfo*>* regs = |
| 1569 | info->GetReg().IsSingle() ? ®_pool_->sp_regs_ : ®_pool_->dp_regs_; |
| 1570 | auto it = std::find(regs->begin(), regs->end(), info); |
| 1571 | DCHECK(it != regs->end()); |
| 1572 | regs->erase(it); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1573 | } |
| 1574 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1575 | } |
| 1576 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1577 | void X86Mir2Lir::ReturnVectorRegisters(MIR* mir) { |
| 1578 | for (uint32_t i = mir->dalvikInsn.vA; i <= mir->dalvikInsn.vB; i++) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1579 | RegStorage xp_reg = RegStorage::Solo128(i); |
| 1580 | RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); |
| 1581 | |
| 1582 | for (RegisterInfo *info = xp_reg_info->GetAliasChain(); |
| 1583 | info != nullptr; |
| 1584 | info = info->GetAliasChain()) { |
| 1585 | if (info->GetReg().IsSingle()) { |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 1586 | reg_pool_->sp_regs_.push_back(info); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1587 | } else { |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 1588 | reg_pool_->dp_regs_.push_back(info); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1589 | } |
| 1590 | } |
| 1591 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1592 | } |
| 1593 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1594 | void X86Mir2Lir::GenConst128(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1595 | RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1596 | Clobber(rs_dest); |
| 1597 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1598 | uint32_t *args = mir->dalvikInsn.arg; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1599 | int reg = rs_dest.GetReg(); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1600 | // Check for all 0 case. |
| 1601 | if (args[0] == 0 && args[1] == 0 && args[2] == 0 && args[3] == 0) { |
| 1602 | NewLIR2(kX86XorpsRR, reg, reg); |
| 1603 | return; |
| 1604 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1605 | |
| 1606 | // Append the mov const vector to reg opcode. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1607 | AppendOpcodeWithConst(kX86MovdqaRM, reg, mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1608 | } |
| 1609 | |
| 1610 | void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1611 | // The literal pool needs position independent logic. |
| 1612 | store_method_addr_used_ = true; |
| 1613 | |
| 1614 | // To deal with correct memory ordering, reverse order of constants. |
| 1615 | int32_t constants[4]; |
| 1616 | constants[3] = mir->dalvikInsn.arg[0]; |
| 1617 | constants[2] = mir->dalvikInsn.arg[1]; |
| 1618 | constants[1] = mir->dalvikInsn.arg[2]; |
| 1619 | constants[0] = mir->dalvikInsn.arg[3]; |
| 1620 | |
| 1621 | // Search if there is already a constant in pool with this value. |
| 1622 | LIR *data_target = ScanVectorLiteral(constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1623 | if (data_target == nullptr) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1624 | data_target = AddVectorLiteral(constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1625 | } |
| 1626 | |
| 1627 | // Address the start of the method. |
| 1628 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 1629 | if (rl_method.wide) { |
| 1630 | rl_method = LoadValueWide(rl_method, kCoreReg); |
| 1631 | } else { |
| 1632 | rl_method = LoadValue(rl_method, kCoreReg); |
| 1633 | } |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1634 | |
| 1635 | // Load the proper value from the literal area. |
| 1636 | // We don't know the proper offset for the value, so pick one that will force |
| 1637 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 1638 | // value. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1639 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1640 | LIR *load = NewLIR3(opcode, reg, rl_method.reg.GetReg(), 256 /* bogus */); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1641 | load->flags.fixup = kFixupLoad; |
| 1642 | load->target = data_target; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1643 | } |
| 1644 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1645 | void X86Mir2Lir::GenMoveVector(MIR* mir) { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1646 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1647 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1648 | RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1649 | Clobber(rs_dest); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1650 | RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1651 | NewLIR2(kX86MovdqaRR, rs_dest.GetReg(), rs_src.GetReg()); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1652 | } |
| 1653 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1654 | void X86Mir2Lir::GenMultiplyVectorSignedByte(RegStorage rs_dest_src1, RegStorage rs_src2) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1655 | /* |
| 1656 | * Emulate the behavior of a kSignedByte by separating out the 16 values in the two XMM |
| 1657 | * and multiplying 8 at a time before recombining back into one XMM register. |
| 1658 | * |
| 1659 | * let xmm1, xmm2 be real srcs (keep low bits of 16bit lanes) |
| 1660 | * xmm3 is tmp (operate on high bits of 16bit lanes) |
| 1661 | * |
| 1662 | * xmm3 = xmm1 |
| 1663 | * xmm1 = xmm1 .* xmm2 |
| 1664 | * xmm1 = xmm1 & 0x00ff00ff00ff00ff00ff00ff00ff00ff // xmm1 now has low bits |
| 1665 | * xmm3 = xmm3 .>> 8 |
| 1666 | * xmm2 = xmm2 & 0xff00ff00ff00ff00ff00ff00ff00ff00 |
| 1667 | * xmm2 = xmm2 .* xmm3 // xmm2 now has high bits |
| 1668 | * xmm1 = xmm1 | xmm2 // combine results |
| 1669 | */ |
| 1670 | |
| 1671 | // Copy xmm1. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1672 | RegStorage rs_src1_high_tmp = Get128BitRegister(AllocTempDouble()); |
| 1673 | RegStorage rs_dest_high_tmp = Get128BitRegister(AllocTempDouble()); |
| 1674 | NewLIR2(kX86MovdqaRR, rs_src1_high_tmp.GetReg(), rs_src2.GetReg()); |
| 1675 | NewLIR2(kX86MovdqaRR, rs_dest_high_tmp.GetReg(), rs_dest_src1.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1676 | |
| 1677 | // Multiply low bits. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1678 | // x7 *= x3 |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1679 | NewLIR2(kX86PmullwRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1680 | |
| 1681 | // xmm1 now has low bits. |
| 1682 | AndMaskVectorRegister(rs_dest_src1, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF); |
| 1683 | |
| 1684 | // Prepare high bits for multiplication. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1685 | NewLIR2(kX86PsrlwRI, rs_src1_high_tmp.GetReg(), 0x8); |
| 1686 | AndMaskVectorRegister(rs_dest_high_tmp, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1687 | |
| 1688 | // Multiply high bits and xmm2 now has high bits. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1689 | NewLIR2(kX86PmullwRR, rs_src1_high_tmp.GetReg(), rs_dest_high_tmp.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1690 | |
| 1691 | // Combine back into dest XMM register. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1692 | NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src1_high_tmp.GetReg()); |
| 1693 | } |
| 1694 | |
| 1695 | void X86Mir2Lir::GenMultiplyVectorLong(RegStorage rs_dest_src1, RegStorage rs_src2) { |
| 1696 | /* |
| 1697 | * We need to emulate the packed long multiply. |
| 1698 | * For kMirOpPackedMultiply xmm1, xmm0: |
| 1699 | * - xmm1 is src/dest |
| 1700 | * - xmm0 is src |
| 1701 | * - Get xmm2 and xmm3 as temp |
| 1702 | * - Idea is to multiply the lower 32 of each operand with the higher 32 of the other. |
| 1703 | * - Then add the two results. |
| 1704 | * - Move it to the upper 32 of the destination |
| 1705 | * - Then multiply the lower 32-bits of the operands and add the result to the destination. |
| 1706 | * |
| 1707 | * (op dest src ) |
| 1708 | * movdqa %xmm2, %xmm1 |
| 1709 | * movdqa %xmm3, %xmm0 |
| 1710 | * psrlq %xmm3, $0x20 |
| 1711 | * pmuludq %xmm3, %xmm2 |
| 1712 | * psrlq %xmm1, $0x20 |
| 1713 | * pmuludq %xmm1, %xmm0 |
| 1714 | * paddq %xmm1, %xmm3 |
| 1715 | * psllq %xmm1, $0x20 |
| 1716 | * pmuludq %xmm2, %xmm0 |
| 1717 | * paddq %xmm1, %xmm2 |
| 1718 | * |
| 1719 | * When both the operands are the same, then we need to calculate the lower-32 * higher-32 |
| 1720 | * calculation only once. Thus we don't need the xmm3 temp above. That sequence becomes: |
| 1721 | * |
| 1722 | * (op dest src ) |
| 1723 | * movdqa %xmm2, %xmm1 |
| 1724 | * psrlq %xmm1, $0x20 |
| 1725 | * pmuludq %xmm1, %xmm0 |
| 1726 | * paddq %xmm1, %xmm1 |
| 1727 | * psllq %xmm1, $0x20 |
| 1728 | * pmuludq %xmm2, %xmm0 |
| 1729 | * paddq %xmm1, %xmm2 |
| 1730 | * |
| 1731 | */ |
| 1732 | |
| 1733 | bool both_operands_same = (rs_dest_src1.GetReg() == rs_src2.GetReg()); |
| 1734 | |
| 1735 | RegStorage rs_tmp_vector_1; |
| 1736 | RegStorage rs_tmp_vector_2; |
| 1737 | rs_tmp_vector_1 = Get128BitRegister(AllocTempDouble()); |
| 1738 | NewLIR2(kX86MovdqaRR, rs_tmp_vector_1.GetReg(), rs_dest_src1.GetReg()); |
| 1739 | |
| 1740 | if (both_operands_same == false) { |
| 1741 | rs_tmp_vector_2 = Get128BitRegister(AllocTempDouble()); |
| 1742 | NewLIR2(kX86MovdqaRR, rs_tmp_vector_2.GetReg(), rs_src2.GetReg()); |
| 1743 | NewLIR2(kX86PsrlqRI, rs_tmp_vector_2.GetReg(), 0x20); |
| 1744 | NewLIR2(kX86PmuludqRR, rs_tmp_vector_2.GetReg(), rs_tmp_vector_1.GetReg()); |
| 1745 | } |
| 1746 | |
| 1747 | NewLIR2(kX86PsrlqRI, rs_dest_src1.GetReg(), 0x20); |
| 1748 | NewLIR2(kX86PmuludqRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1749 | |
| 1750 | if (both_operands_same == false) { |
| 1751 | NewLIR2(kX86PaddqRR, rs_dest_src1.GetReg(), rs_tmp_vector_2.GetReg()); |
| 1752 | } else { |
| 1753 | NewLIR2(kX86PaddqRR, rs_dest_src1.GetReg(), rs_dest_src1.GetReg()); |
| 1754 | } |
| 1755 | |
| 1756 | NewLIR2(kX86PsllqRI, rs_dest_src1.GetReg(), 0x20); |
| 1757 | NewLIR2(kX86PmuludqRR, rs_tmp_vector_1.GetReg(), rs_src2.GetReg()); |
| 1758 | NewLIR2(kX86PaddqRR, rs_dest_src1.GetReg(), rs_tmp_vector_1.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1759 | } |
| 1760 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1761 | void X86Mir2Lir::GenMultiplyVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1762 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1763 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1764 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1765 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1766 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1767 | int opcode = 0; |
| 1768 | switch (opsize) { |
| 1769 | case k32: |
| 1770 | opcode = kX86PmulldRR; |
| 1771 | break; |
| 1772 | case kSignedHalf: |
| 1773 | opcode = kX86PmullwRR; |
| 1774 | break; |
| 1775 | case kSingle: |
| 1776 | opcode = kX86MulpsRR; |
| 1777 | break; |
| 1778 | case kDouble: |
| 1779 | opcode = kX86MulpdRR; |
| 1780 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1781 | case kSignedByte: |
| 1782 | // HW doesn't support 16x16 byte multiplication so emulate it. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1783 | GenMultiplyVectorSignedByte(rs_dest_src1, rs_src2); |
| 1784 | return; |
| 1785 | case k64: |
| 1786 | GenMultiplyVectorLong(rs_dest_src1, rs_src2); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1787 | return; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1788 | default: |
| 1789 | LOG(FATAL) << "Unsupported vector multiply " << opsize; |
| 1790 | break; |
| 1791 | } |
| 1792 | NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1793 | } |
| 1794 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1795 | void X86Mir2Lir::GenAddVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1796 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1797 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1798 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1799 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1800 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1801 | int opcode = 0; |
| 1802 | switch (opsize) { |
| 1803 | case k32: |
| 1804 | opcode = kX86PadddRR; |
| 1805 | break; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1806 | case k64: |
| 1807 | opcode = kX86PaddqRR; |
| 1808 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1809 | case kSignedHalf: |
| 1810 | case kUnsignedHalf: |
| 1811 | opcode = kX86PaddwRR; |
| 1812 | break; |
| 1813 | case kUnsignedByte: |
| 1814 | case kSignedByte: |
| 1815 | opcode = kX86PaddbRR; |
| 1816 | break; |
| 1817 | case kSingle: |
| 1818 | opcode = kX86AddpsRR; |
| 1819 | break; |
| 1820 | case kDouble: |
| 1821 | opcode = kX86AddpdRR; |
| 1822 | break; |
| 1823 | default: |
| 1824 | LOG(FATAL) << "Unsupported vector addition " << opsize; |
| 1825 | break; |
| 1826 | } |
| 1827 | NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1828 | } |
| 1829 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1830 | void X86Mir2Lir::GenSubtractVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1831 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1832 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1833 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1834 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1835 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1836 | int opcode = 0; |
| 1837 | switch (opsize) { |
| 1838 | case k32: |
| 1839 | opcode = kX86PsubdRR; |
| 1840 | break; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1841 | case k64: |
| 1842 | opcode = kX86PsubqRR; |
| 1843 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1844 | case kSignedHalf: |
| 1845 | case kUnsignedHalf: |
| 1846 | opcode = kX86PsubwRR; |
| 1847 | break; |
| 1848 | case kUnsignedByte: |
| 1849 | case kSignedByte: |
| 1850 | opcode = kX86PsubbRR; |
| 1851 | break; |
| 1852 | case kSingle: |
| 1853 | opcode = kX86SubpsRR; |
| 1854 | break; |
| 1855 | case kDouble: |
| 1856 | opcode = kX86SubpdRR; |
| 1857 | break; |
| 1858 | default: |
| 1859 | LOG(FATAL) << "Unsupported vector subtraction " << opsize; |
| 1860 | break; |
| 1861 | } |
| 1862 | NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1863 | } |
| 1864 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1865 | void X86Mir2Lir::GenShiftByteVector(MIR* mir) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1866 | // Destination does not need clobbered because it has already been as part |
| 1867 | // of the general packed shift handler (caller of this method). |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1868 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1869 | |
| 1870 | int opcode = 0; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1871 | switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { |
| 1872 | case kMirOpPackedShiftLeft: |
| 1873 | opcode = kX86PsllwRI; |
| 1874 | break; |
| 1875 | case kMirOpPackedSignedShiftRight: |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1876 | case kMirOpPackedUnsignedShiftRight: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1877 | // TODO Add support for emulated byte shifts. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1878 | default: |
| 1879 | LOG(FATAL) << "Unsupported shift operation on byte vector " << opcode; |
| 1880 | break; |
| 1881 | } |
| 1882 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1883 | // Clear xmm register and return if shift more than byte length. |
| 1884 | int imm = mir->dalvikInsn.vB; |
| 1885 | if (imm >= 8) { |
| 1886 | NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_dest_src1.GetReg()); |
| 1887 | return; |
| 1888 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1889 | |
| 1890 | // Shift lower values. |
| 1891 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 1892 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1893 | /* |
| 1894 | * The above shift will shift the whole word, but that means |
| 1895 | * both the bytes will shift as well. To emulate a byte level |
| 1896 | * shift, we can just throw away the lower (8 - N) bits of the |
| 1897 | * upper byte, and we are done. |
| 1898 | */ |
| 1899 | uint8_t byte_mask = 0xFF << imm; |
| 1900 | uint32_t int_mask = byte_mask; |
| 1901 | int_mask = int_mask << 8 | byte_mask; |
| 1902 | int_mask = int_mask << 8 | byte_mask; |
| 1903 | int_mask = int_mask << 8 | byte_mask; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1904 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1905 | // And the destination with the mask |
| 1906 | AndMaskVectorRegister(rs_dest_src1, int_mask, int_mask, int_mask, int_mask); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1907 | } |
| 1908 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1909 | void X86Mir2Lir::GenShiftLeftVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1910 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1911 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1912 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1913 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1914 | int imm = mir->dalvikInsn.vB; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1915 | int opcode = 0; |
| 1916 | switch (opsize) { |
| 1917 | case k32: |
| 1918 | opcode = kX86PslldRI; |
| 1919 | break; |
| 1920 | case k64: |
| 1921 | opcode = kX86PsllqRI; |
| 1922 | break; |
| 1923 | case kSignedHalf: |
| 1924 | case kUnsignedHalf: |
| 1925 | opcode = kX86PsllwRI; |
| 1926 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1927 | case kSignedByte: |
| 1928 | case kUnsignedByte: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1929 | GenShiftByteVector(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1930 | return; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1931 | default: |
| 1932 | LOG(FATAL) << "Unsupported vector shift left " << opsize; |
| 1933 | break; |
| 1934 | } |
| 1935 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 1936 | } |
| 1937 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1938 | void X86Mir2Lir::GenSignedShiftRightVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1939 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1940 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1941 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1942 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1943 | int imm = mir->dalvikInsn.vB; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1944 | int opcode = 0; |
| 1945 | switch (opsize) { |
| 1946 | case k32: |
| 1947 | opcode = kX86PsradRI; |
| 1948 | break; |
| 1949 | case kSignedHalf: |
| 1950 | case kUnsignedHalf: |
| 1951 | opcode = kX86PsrawRI; |
| 1952 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1953 | case kSignedByte: |
| 1954 | case kUnsignedByte: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1955 | GenShiftByteVector(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1956 | return; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1957 | case k64: |
| 1958 | // TODO Implement emulated shift algorithm. |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1959 | default: |
| 1960 | LOG(FATAL) << "Unsupported vector signed shift right " << opsize; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1961 | UNREACHABLE(); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1962 | } |
| 1963 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 1964 | } |
| 1965 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1966 | void X86Mir2Lir::GenUnsignedShiftRightVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1967 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1968 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1969 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1970 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1971 | int imm = mir->dalvikInsn.vB; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1972 | int opcode = 0; |
| 1973 | switch (opsize) { |
| 1974 | case k32: |
| 1975 | opcode = kX86PsrldRI; |
| 1976 | break; |
| 1977 | case k64: |
| 1978 | opcode = kX86PsrlqRI; |
| 1979 | break; |
| 1980 | case kSignedHalf: |
| 1981 | case kUnsignedHalf: |
| 1982 | opcode = kX86PsrlwRI; |
| 1983 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1984 | case kSignedByte: |
| 1985 | case kUnsignedByte: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1986 | GenShiftByteVector(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1987 | return; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1988 | default: |
| 1989 | LOG(FATAL) << "Unsupported vector unsigned shift right " << opsize; |
| 1990 | break; |
| 1991 | } |
| 1992 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 1993 | } |
| 1994 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1995 | void X86Mir2Lir::GenAndVector(MIR* mir) { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1996 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1997 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1998 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1999 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2000 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2001 | NewLIR2(kX86PandRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 2002 | } |
| 2003 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2004 | void X86Mir2Lir::GenOrVector(MIR* mir) { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2005 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2006 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 2007 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2008 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2009 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2010 | NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 2011 | } |
| 2012 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2013 | void X86Mir2Lir::GenXorVector(MIR* mir) { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2014 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2015 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 2016 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2017 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2018 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2019 | NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 2020 | } |
| 2021 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2022 | void X86Mir2Lir::AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4) { |
| 2023 | MaskVectorRegister(kX86PandRM, rs_src1, m1, m2, m3, m4); |
| 2024 | } |
| 2025 | |
| 2026 | void X86Mir2Lir::MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m0, uint32_t m1, uint32_t m2, uint32_t m3) { |
| 2027 | // Create temporary MIR as container for 128-bit binary mask. |
| 2028 | MIR const_mir; |
| 2029 | MIR* const_mirp = &const_mir; |
| 2030 | const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector); |
| 2031 | const_mirp->dalvikInsn.arg[0] = m0; |
| 2032 | const_mirp->dalvikInsn.arg[1] = m1; |
| 2033 | const_mirp->dalvikInsn.arg[2] = m2; |
| 2034 | const_mirp->dalvikInsn.arg[3] = m3; |
| 2035 | |
| 2036 | // Mask vector with const from literal pool. |
| 2037 | AppendOpcodeWithConst(opcode, rs_src1.GetReg(), const_mirp); |
| 2038 | } |
| 2039 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2040 | void X86Mir2Lir::GenAddReduceVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2041 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2042 | RegStorage vector_src = RegStorage::Solo128(mir->dalvikInsn.vB); |
| 2043 | bool is_wide = opsize == k64 || opsize == kDouble; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2044 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2045 | // Get the location of the virtual register. Since this bytecode is overloaded |
| 2046 | // for different types (and sizes), we need different logic for each path. |
| 2047 | // The design of bytecode uses same VR for source and destination. |
| 2048 | RegLocation rl_src, rl_dest, rl_result; |
| 2049 | if (is_wide) { |
| 2050 | rl_src = mir_graph_->GetSrcWide(mir, 0); |
| 2051 | rl_dest = mir_graph_->GetDestWide(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2052 | } else { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2053 | rl_src = mir_graph_->GetSrc(mir, 0); |
| 2054 | rl_dest = mir_graph_->GetDest(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2055 | } |
| 2056 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2057 | // We need a temp for byte and short values |
| 2058 | RegStorage temp; |
| 2059 | |
| 2060 | // There is a different path depending on type and size. |
| 2061 | if (opsize == kSingle) { |
| 2062 | // Handle float case. |
| 2063 | // TODO Add support for fast math (not value safe) and do horizontal add in that case. |
| 2064 | |
| 2065 | rl_src = LoadValue(rl_src, kFPReg); |
| 2066 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
| 2067 | |
| 2068 | // Since we are doing an add-reduce, we move the reg holding the VR |
| 2069 | // into the result so we include it in result. |
| 2070 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 2071 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2072 | |
| 2073 | // Since FP must keep order of operation for value safety, we shift to low |
| 2074 | // 32-bits and add to result. |
| 2075 | for (int i = 0; i < 3; i++) { |
| 2076 | NewLIR3(kX86ShufpsRRI, vector_src.GetReg(), vector_src.GetReg(), 0x39); |
| 2077 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2078 | } |
| 2079 | |
| 2080 | StoreValue(rl_dest, rl_result); |
| 2081 | } else if (opsize == kDouble) { |
| 2082 | // Handle double case. |
| 2083 | rl_src = LoadValueWide(rl_src, kFPReg); |
| 2084 | rl_result = EvalLocWide(rl_dest, kFPReg, true); |
| 2085 | LOG(FATAL) << "Unsupported vector add reduce for double."; |
| 2086 | } else if (opsize == k64) { |
| 2087 | /* |
| 2088 | * Handle long case: |
| 2089 | * 1) Reduce the vector register to lower half (with addition). |
| 2090 | * 1-1) Get an xmm temp and fill it with vector register. |
| 2091 | * 1-2) Shift the xmm temp by 8-bytes. |
| 2092 | * 1-3) Add the xmm temp to vector register that is being reduced. |
| 2093 | * 2) Allocate temp GP / GP pair. |
| 2094 | * 2-1) In 64-bit case, use movq to move result to a 64-bit GP. |
| 2095 | * 2-2) In 32-bit case, use movd twice to move to 32-bit GP pair. |
| 2096 | * 3) Finish the add reduction by doing what add-long/2addr does, |
| 2097 | * but instead of having a VR as one of the sources, we have our temp GP. |
| 2098 | */ |
| 2099 | RegStorage rs_tmp_vector = Get128BitRegister(AllocTempDouble()); |
| 2100 | NewLIR2(kX86MovdqaRR, rs_tmp_vector.GetReg(), vector_src.GetReg()); |
| 2101 | NewLIR2(kX86PsrldqRI, rs_tmp_vector.GetReg(), 8); |
| 2102 | NewLIR2(kX86PaddqRR, vector_src.GetReg(), rs_tmp_vector.GetReg()); |
| 2103 | FreeTemp(rs_tmp_vector); |
| 2104 | |
| 2105 | // We would like to be able to reuse the add-long implementation, so set up a fake |
| 2106 | // register location to pass it. |
| 2107 | RegLocation temp_loc = mir_graph_->GetBadLoc(); |
| 2108 | temp_loc.core = 1; |
| 2109 | temp_loc.wide = 1; |
| 2110 | temp_loc.location = kLocPhysReg; |
| 2111 | temp_loc.reg = AllocTempWide(); |
| 2112 | |
| 2113 | if (cu_->target64) { |
| 2114 | DCHECK(!temp_loc.reg.IsPair()); |
| 2115 | NewLIR2(kX86MovqrxRR, temp_loc.reg.GetReg(), vector_src.GetReg()); |
| 2116 | } else { |
| 2117 | NewLIR2(kX86MovdrxRR, temp_loc.reg.GetLowReg(), vector_src.GetReg()); |
| 2118 | NewLIR2(kX86PsrlqRI, vector_src.GetReg(), 0x20); |
| 2119 | NewLIR2(kX86MovdrxRR, temp_loc.reg.GetHighReg(), vector_src.GetReg()); |
| 2120 | } |
| 2121 | |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2122 | GenArithOpLong(Instruction::ADD_LONG_2ADDR, rl_dest, temp_loc, temp_loc, mir->optimization_flags); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2123 | } else if (opsize == kSignedByte || opsize == kUnsignedByte) { |
| 2124 | RegStorage rs_tmp = Get128BitRegister(AllocTempDouble()); |
| 2125 | NewLIR2(kX86PxorRR, rs_tmp.GetReg(), rs_tmp.GetReg()); |
| 2126 | NewLIR2(kX86PsadbwRR, vector_src.GetReg(), rs_tmp.GetReg()); |
| 2127 | NewLIR3(kX86PshufdRRI, rs_tmp.GetReg(), vector_src.GetReg(), 0x4e); |
| 2128 | NewLIR2(kX86PaddbRR, vector_src.GetReg(), rs_tmp.GetReg()); |
| 2129 | // Move to a GPR |
| 2130 | temp = AllocTemp(); |
| 2131 | NewLIR2(kX86MovdrxRR, temp.GetReg(), vector_src.GetReg()); |
| 2132 | } else { |
| 2133 | // Handle and the int and short cases together |
| 2134 | |
| 2135 | // Initialize as if we were handling int case. Below we update |
| 2136 | // the opcode if handling byte or short. |
| 2137 | int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8; |
| 2138 | int vec_unit_size; |
| 2139 | int horizontal_add_opcode; |
| 2140 | int extract_opcode; |
| 2141 | |
| 2142 | if (opsize == kSignedHalf || opsize == kUnsignedHalf) { |
| 2143 | extract_opcode = kX86PextrwRRI; |
| 2144 | horizontal_add_opcode = kX86PhaddwRR; |
| 2145 | vec_unit_size = 2; |
| 2146 | } else if (opsize == k32) { |
| 2147 | vec_unit_size = 4; |
| 2148 | horizontal_add_opcode = kX86PhadddRR; |
| 2149 | extract_opcode = kX86PextrdRRI; |
| 2150 | } else { |
| 2151 | LOG(FATAL) << "Unsupported vector add reduce " << opsize; |
| 2152 | return; |
| 2153 | } |
| 2154 | |
| 2155 | int elems = vec_bytes / vec_unit_size; |
| 2156 | |
| 2157 | while (elems > 1) { |
| 2158 | NewLIR2(horizontal_add_opcode, vector_src.GetReg(), vector_src.GetReg()); |
| 2159 | elems >>= 1; |
| 2160 | } |
| 2161 | |
| 2162 | // Handle this as arithmetic unary case. |
| 2163 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 2164 | |
| 2165 | // Extract to a GP register because this is integral typed. |
| 2166 | temp = AllocTemp(); |
| 2167 | NewLIR3(extract_opcode, temp.GetReg(), vector_src.GetReg(), 0); |
| 2168 | } |
| 2169 | |
| 2170 | if (opsize != k64 && opsize != kSingle && opsize != kDouble) { |
| 2171 | // The logic below looks very similar to the handling of ADD_INT_2ADDR |
| 2172 | // except the rhs is not a VR but a physical register allocated above. |
| 2173 | // No load of source VR is done because it assumes that rl_result will |
| 2174 | // share physical register / memory location. |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2175 | rl_result = UpdateLocTyped(rl_dest); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2176 | if (rl_result.location == kLocPhysReg) { |
| 2177 | // Ensure res is in a core reg. |
| 2178 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 2179 | OpRegReg(kOpAdd, rl_result.reg, temp); |
| 2180 | StoreFinalValue(rl_dest, rl_result); |
| 2181 | } else { |
| 2182 | // Do the addition directly to memory. |
| 2183 | OpMemReg(kOpAdd, rl_result, temp.GetReg()); |
| 2184 | } |
| 2185 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2186 | } |
| 2187 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2188 | void X86Mir2Lir::GenReduceVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2189 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 2190 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2191 | RegStorage vector_src = RegStorage::Solo128(mir->dalvikInsn.vB); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2192 | RegLocation rl_result; |
| 2193 | bool is_wide = false; |
| 2194 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2195 | // There is a different path depending on type and size. |
| 2196 | if (opsize == kSingle) { |
| 2197 | // Handle float case. |
| 2198 | // TODO Add support for fast math (not value safe) and do horizontal add in that case. |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2199 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2200 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
| 2201 | NewLIR2(kX86PxorRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
| 2202 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2203 | |
| 2204 | // Since FP must keep order of operation for value safety, we shift to low |
| 2205 | // 32-bits and add to result. |
| 2206 | for (int i = 0; i < 3; i++) { |
| 2207 | NewLIR3(kX86ShufpsRRI, vector_src.GetReg(), vector_src.GetReg(), 0x39); |
| 2208 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2209 | } |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2210 | |
| 2211 | StoreValue(rl_dest, rl_result); |
| 2212 | } else if (opsize == kDouble) { |
| 2213 | // TODO Handle double case. |
| 2214 | LOG(FATAL) << "Unsupported add reduce for double."; |
| 2215 | } else if (opsize == k64) { |
| 2216 | /* |
| 2217 | * Handle long case: |
| 2218 | * 1) Reduce the vector register to lower half (with addition). |
| 2219 | * 1-1) Get an xmm temp and fill it with vector register. |
| 2220 | * 1-2) Shift the xmm temp by 8-bytes. |
| 2221 | * 1-3) Add the xmm temp to vector register that is being reduced. |
| 2222 | * 2) Evaluate destination to a GP / GP pair. |
| 2223 | * 2-1) In 64-bit case, use movq to move result to a 64-bit GP. |
| 2224 | * 2-2) In 32-bit case, use movd twice to move to 32-bit GP pair. |
| 2225 | * 3) Store the result to the final destination. |
| 2226 | */ |
Udayan Banerji | 53cec00 | 2014-09-26 10:41:47 -0700 | [diff] [blame] | 2227 | NewLIR2(kX86PsrldqRI, vector_src.GetReg(), 8); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2228 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2229 | if (cu_->target64) { |
| 2230 | DCHECK(!rl_result.reg.IsPair()); |
| 2231 | NewLIR2(kX86MovqrxRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2232 | } else { |
| 2233 | NewLIR2(kX86MovdrxRR, rl_result.reg.GetLowReg(), vector_src.GetReg()); |
| 2234 | NewLIR2(kX86PsrlqRI, vector_src.GetReg(), 0x20); |
| 2235 | NewLIR2(kX86MovdrxRR, rl_result.reg.GetHighReg(), vector_src.GetReg()); |
| 2236 | } |
| 2237 | |
| 2238 | StoreValueWide(rl_dest, rl_result); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2239 | } else { |
Udayan Banerji | 53cec00 | 2014-09-26 10:41:47 -0700 | [diff] [blame] | 2240 | int extract_index = mir->dalvikInsn.arg[0]; |
| 2241 | int extr_opcode = 0; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2242 | rl_result = UpdateLocTyped(rl_dest); |
Udayan Banerji | 53cec00 | 2014-09-26 10:41:47 -0700 | [diff] [blame] | 2243 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2244 | // Handle the rest of integral types now. |
| 2245 | switch (opsize) { |
| 2246 | case k32: |
Udayan Banerji | 53cec00 | 2014-09-26 10:41:47 -0700 | [diff] [blame] | 2247 | extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrdRRI : kX86PextrdMRI; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2248 | break; |
| 2249 | case kSignedHalf: |
| 2250 | case kUnsignedHalf: |
Udayan Banerji | 53cec00 | 2014-09-26 10:41:47 -0700 | [diff] [blame] | 2251 | extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrwRRI : kX86PextrwMRI; |
| 2252 | break; |
| 2253 | case kSignedByte: |
| 2254 | extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrbRRI : kX86PextrbMRI; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2255 | break; |
| 2256 | default: |
| 2257 | LOG(FATAL) << "Unsupported vector reduce " << opsize; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2258 | UNREACHABLE(); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2259 | } |
| 2260 | |
| 2261 | if (rl_result.location == kLocPhysReg) { |
| 2262 | NewLIR3(extr_opcode, rl_result.reg.GetReg(), vector_src.GetReg(), extract_index); |
Udayan Banerji | 53cec00 | 2014-09-26 10:41:47 -0700 | [diff] [blame] | 2263 | StoreFinalValue(rl_dest, rl_result); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2264 | } else { |
| 2265 | int displacement = SRegOffset(rl_result.s_reg_low); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2266 | LIR *l = NewLIR3(extr_opcode, rs_rX86_SP_32.GetReg(), displacement, vector_src.GetReg()); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2267 | AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */); |
| 2268 | AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */); |
| 2269 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2270 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2271 | } |
| 2272 | |
Mark Mendell | 0a1174e | 2014-09-11 14:51:02 -0400 | [diff] [blame] | 2273 | void X86Mir2Lir::LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, |
| 2274 | OpSize opsize, int op_mov) { |
| 2275 | if (!cu_->target64 && opsize == k64) { |
| 2276 | // Logic assumes that longs are loaded in GP register pairs. |
| 2277 | NewLIR2(kX86MovdxrRR, rs_dest.GetReg(), rs_src.GetLowReg()); |
| 2278 | RegStorage r_tmp = AllocTempDouble(); |
| 2279 | NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), rs_src.GetHighReg()); |
| 2280 | NewLIR2(kX86PunpckldqRR, rs_dest.GetReg(), r_tmp.GetReg()); |
| 2281 | FreeTemp(r_tmp); |
| 2282 | } else { |
| 2283 | NewLIR2(op_mov, rs_dest.GetReg(), rs_src.GetReg()); |
| 2284 | } |
| 2285 | } |
| 2286 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2287 | void X86Mir2Lir::GenSetVector(MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2288 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 2289 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 2290 | RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2291 | Clobber(rs_dest); |
| 2292 | int op_shuffle = 0, op_shuffle_high = 0, op_mov = kX86MovdxrRR; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2293 | RegisterClass reg_type = kCoreReg; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2294 | bool is_wide = false; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2295 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2296 | switch (opsize) { |
| 2297 | case k32: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2298 | op_shuffle = kX86PshufdRRI; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2299 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2300 | case kSingle: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2301 | op_shuffle = kX86PshufdRRI; |
| 2302 | op_mov = kX86MovdqaRR; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2303 | reg_type = kFPReg; |
| 2304 | break; |
| 2305 | case k64: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2306 | op_shuffle = kX86PunpcklqdqRR; |
Udayan Banerji | 53cec00 | 2014-09-26 10:41:47 -0700 | [diff] [blame] | 2307 | op_mov = kX86MovqxrRR; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2308 | is_wide = true; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2309 | break; |
| 2310 | case kSignedByte: |
| 2311 | case kUnsignedByte: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2312 | // We will have the source loaded up in a |
| 2313 | // double-word before we use this shuffle |
| 2314 | op_shuffle = kX86PshufdRRI; |
| 2315 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2316 | case kSignedHalf: |
| 2317 | case kUnsignedHalf: |
| 2318 | // Handles low quadword. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2319 | op_shuffle = kX86PshuflwRRI; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2320 | // Handles upper quadword. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2321 | op_shuffle_high = kX86PshufdRRI; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2322 | break; |
| 2323 | default: |
| 2324 | LOG(FATAL) << "Unsupported vector set " << opsize; |
| 2325 | break; |
| 2326 | } |
| 2327 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2328 | // Load the value from the VR into a physical register. |
| 2329 | RegLocation rl_src; |
| 2330 | if (!is_wide) { |
| 2331 | rl_src = mir_graph_->GetSrc(mir, 0); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2332 | rl_src = LoadValue(rl_src, reg_type); |
| 2333 | } else { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2334 | rl_src = mir_graph_->GetSrcWide(mir, 0); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2335 | rl_src = LoadValueWide(rl_src, reg_type); |
| 2336 | } |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2337 | RegStorage reg_to_shuffle = rl_src.reg; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2338 | |
| 2339 | // Load the value into the XMM register. |
Mark Mendell | 0a1174e | 2014-09-11 14:51:02 -0400 | [diff] [blame] | 2340 | LoadVectorRegister(rs_dest, reg_to_shuffle, opsize, op_mov); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2341 | |
| 2342 | if (opsize == kSignedByte || opsize == kUnsignedByte) { |
| 2343 | // In the byte case, first duplicate it to be a word |
| 2344 | // Then duplicate it to be a double-word |
| 2345 | NewLIR2(kX86PunpcklbwRR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 2346 | NewLIR2(kX86PunpcklwdRR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 2347 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2348 | |
| 2349 | // Now shuffle the value across the destination. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2350 | if (op_shuffle == kX86PunpcklqdqRR) { |
| 2351 | NewLIR2(op_shuffle, rs_dest.GetReg(), rs_dest.GetReg()); |
| 2352 | } else { |
| 2353 | NewLIR3(op_shuffle, rs_dest.GetReg(), rs_dest.GetReg(), 0); |
| 2354 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2355 | |
| 2356 | // And then repeat as needed. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2357 | if (op_shuffle_high != 0) { |
| 2358 | NewLIR3(op_shuffle_high, rs_dest.GetReg(), rs_dest.GetReg(), 0); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2359 | } |
| 2360 | } |
| 2361 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2362 | void X86Mir2Lir::GenPackedArrayGet(BasicBlock* bb, MIR* mir) { |
| 2363 | UNUSED(bb, mir); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2364 | UNIMPLEMENTED(FATAL) << "Extended opcode kMirOpPackedArrayGet not supported."; |
| 2365 | } |
| 2366 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2367 | void X86Mir2Lir::GenPackedArrayPut(BasicBlock* bb, MIR* mir) { |
| 2368 | UNUSED(bb, mir); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2369 | UNIMPLEMENTED(FATAL) << "Extended opcode kMirOpPackedArrayPut not supported."; |
| 2370 | } |
| 2371 | |
| 2372 | LIR* X86Mir2Lir::ScanVectorLiteral(int32_t* constants) { |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2373 | for (LIR *p = const_vectors_; p != nullptr; p = p->next) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2374 | if (constants[0] == p->operands[0] && constants[1] == p->operands[1] && |
| 2375 | constants[2] == p->operands[2] && constants[3] == p->operands[3]) { |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2376 | return p; |
| 2377 | } |
| 2378 | } |
| 2379 | return nullptr; |
| 2380 | } |
| 2381 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2382 | LIR* X86Mir2Lir::AddVectorLiteral(int32_t* constants) { |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2383 | LIR* new_value = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocData)); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2384 | new_value->operands[0] = constants[0]; |
| 2385 | new_value->operands[1] = constants[1]; |
| 2386 | new_value->operands[2] = constants[2]; |
| 2387 | new_value->operands[3] = constants[3]; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2388 | new_value->next = const_vectors_; |
| 2389 | if (const_vectors_ == nullptr) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2390 | estimated_native_code_size_ += 12; // Maximum needed to align to 16 byte boundary. |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2391 | } |
| 2392 | estimated_native_code_size_ += 16; // Space for one vector. |
| 2393 | const_vectors_ = new_value; |
| 2394 | return new_value; |
| 2395 | } |
| 2396 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2397 | // ------------ ABI support: mapping of args to physical registers ------------- |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2398 | RegStorage X86Mir2Lir::InToRegStorageX86_64Mapper::GetNextReg(bool is_double_or_float, bool is_wide, |
| 2399 | bool is_ref) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2400 | const SpecialTargetRegister coreArgMappingToPhysicalReg[] = {kArg1, kArg2, kArg3, kArg4, kArg5}; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2401 | const int coreArgMappingToPhysicalRegSize = sizeof(coreArgMappingToPhysicalReg) / |
| 2402 | sizeof(SpecialTargetRegister); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2403 | const SpecialTargetRegister fpArgMappingToPhysicalReg[] = {kFArg0, kFArg1, kFArg2, kFArg3, |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2404 | kFArg4, kFArg5, kFArg6, kFArg7}; |
| 2405 | const int fpArgMappingToPhysicalRegSize = sizeof(fpArgMappingToPhysicalReg) / |
| 2406 | sizeof(SpecialTargetRegister); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2407 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2408 | if (is_double_or_float) { |
| 2409 | if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2410 | return ml_->TargetReg(fpArgMappingToPhysicalReg[cur_fp_reg_++], is_wide ? kWide : kNotWide); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2411 | } |
| 2412 | } else { |
| 2413 | if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2414 | return ml_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++], |
| 2415 | is_ref ? kRef : (is_wide ? kWide : kNotWide)); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2416 | } |
| 2417 | } |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2418 | return RegStorage::InvalidReg(); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2419 | } |
| 2420 | |
| 2421 | RegStorage X86Mir2Lir::InToRegStorageMapping::Get(int in_position) { |
| 2422 | DCHECK(IsInitialized()); |
| 2423 | auto res = mapping_.find(in_position); |
| 2424 | return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); |
| 2425 | } |
| 2426 | |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2427 | void X86Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, |
| 2428 | InToRegStorageMapper* mapper) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2429 | DCHECK(mapper != nullptr); |
| 2430 | max_mapped_in_ = -1; |
| 2431 | is_there_stack_mapped_ = false; |
| 2432 | for (int in_position = 0; in_position < count; in_position++) { |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 2433 | RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, |
| 2434 | arg_locs[in_position].wide, arg_locs[in_position].ref); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2435 | if (reg.Valid()) { |
| 2436 | mapping_[in_position] = reg; |
| 2437 | max_mapped_in_ = std::max(max_mapped_in_, in_position); |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 2438 | if (arg_locs[in_position].wide) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2439 | // We covered 2 args, so skip the next one |
| 2440 | in_position++; |
| 2441 | } |
| 2442 | } else { |
| 2443 | is_there_stack_mapped_ = true; |
| 2444 | } |
| 2445 | } |
| 2446 | initialized_ = true; |
| 2447 | } |
| 2448 | |
| 2449 | RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2450 | if (!cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2451 | return GetCoreArgMappingToPhysicalReg(arg_num); |
| 2452 | } |
| 2453 | |
| 2454 | if (!in_to_reg_storage_mapping_.IsInitialized()) { |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2455 | int start_vreg = cu_->mir_graph->GetFirstInVR(); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2456 | RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; |
| 2457 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2458 | InToRegStorageX86_64Mapper mapper(this); |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2459 | in_to_reg_storage_mapping_.Initialize(arg_locs, mir_graph_->GetNumOfInVRs(), &mapper); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2460 | } |
| 2461 | return in_to_reg_storage_mapping_.Get(arg_num); |
| 2462 | } |
| 2463 | |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2464 | RegStorage X86Mir2Lir::GetCoreArgMappingToPhysicalReg(int core_arg_num) const { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2465 | // For the 32-bit internal ABI, the first 3 arguments are passed in registers. |
| 2466 | // Not used for 64-bit, TODO: Move X86_32 to the same framework |
| 2467 | switch (core_arg_num) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2468 | case 0: return TargetReg32(kArg1); |
| 2469 | case 1: return TargetReg32(kArg2); |
| 2470 | case 2: return TargetReg32(kArg3); |
| 2471 | default: return RegStorage::InvalidReg(); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2472 | } |
| 2473 | } |
| 2474 | |
| 2475 | // ---------End of ABI support: mapping of args to physical registers ------------- |
| 2476 | |
| 2477 | /* |
| 2478 | * If there are any ins passed in registers that have not been promoted |
| 2479 | * to a callee-save register, flush them to the frame. Perform initial |
| 2480 | * assignment of promoted arguments. |
| 2481 | * |
| 2482 | * ArgLocs is an array of location records describing the incoming arguments |
| 2483 | * with one location record per word of argument. |
| 2484 | */ |
| 2485 | void X86Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2486 | if (!cu_->target64) return Mir2Lir::FlushIns(ArgLocs, rl_method); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2487 | /* |
| 2488 | * Dummy up a RegLocation for the incoming Method* |
| 2489 | * It will attempt to keep kArg0 live (or copy it to home location |
| 2490 | * if promoted). |
| 2491 | */ |
| 2492 | |
| 2493 | RegLocation rl_src = rl_method; |
| 2494 | rl_src.location = kLocPhysReg; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2495 | rl_src.reg = TargetReg(kArg0, kRef); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2496 | rl_src.home = false; |
| 2497 | MarkLive(rl_src); |
| 2498 | StoreValue(rl_method, rl_src); |
| 2499 | // If Method* has been promoted, explicitly flush |
| 2500 | if (rl_method.location == kLocPhysReg) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2501 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
| 2502 | StoreRefDisp(rs_rSP, 0, As32BitReg(TargetReg(kArg0, kRef)), kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2503 | } |
| 2504 | |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2505 | if (mir_graph_->GetNumOfInVRs() == 0) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2506 | return; |
| 2507 | } |
| 2508 | |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2509 | int start_vreg = cu_->mir_graph->GetFirstInVR(); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2510 | /* |
| 2511 | * Copy incoming arguments to their proper home locations. |
| 2512 | * NOTE: an older version of dx had an issue in which |
| 2513 | * it would reuse static method argument registers. |
| 2514 | * This could result in the same Dalvik virtual register |
| 2515 | * being promoted to both core and fp regs. To account for this, |
| 2516 | * we only copy to the corresponding promoted physical register |
| 2517 | * if it matches the type of the SSA name for the incoming |
| 2518 | * argument. It is also possible that long and double arguments |
| 2519 | * end up half-promoted. In those cases, we must flush the promoted |
| 2520 | * half to memory as well. |
| 2521 | */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2522 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2523 | for (uint32_t i = 0; i < mir_graph_->GetNumOfInVRs(); i++) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2524 | // get reg corresponding to input |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2525 | RegStorage reg = GetArgMappingToPhysicalReg(i); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2526 | |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2527 | RegLocation* t_loc = &ArgLocs[i]; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2528 | if (reg.Valid()) { |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2529 | // If arriving in register. |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2530 | |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2531 | // We have already updated the arg location with promoted info |
| 2532 | // so we can be based on it. |
| 2533 | if (t_loc->location == kLocPhysReg) { |
| 2534 | // Just copy it. |
| 2535 | OpRegCopy(t_loc->reg, reg); |
| 2536 | } else { |
| 2537 | // Needs flush. |
| 2538 | if (t_loc->ref) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2539 | StoreRefDisp(rs_rX86_SP_64, SRegOffset(start_vreg + i), reg, kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2540 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2541 | StoreBaseDisp(rs_rX86_SP_64, SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2542 | kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2543 | } |
| 2544 | } |
| 2545 | } else { |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2546 | // If arriving in frame & promoted. |
| 2547 | if (t_loc->location == kLocPhysReg) { |
| 2548 | if (t_loc->ref) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2549 | LoadRefDisp(rs_rX86_SP_64, SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2550 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2551 | LoadBaseDisp(rs_rX86_SP_64, SRegOffset(start_vreg + i), t_loc->reg, |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2552 | t_loc->wide ? k64 : k32, kNotVolatile); |
| 2553 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2554 | } |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2555 | } |
| 2556 | if (t_loc->wide) { |
| 2557 | // Increment i to skip the next one. |
| 2558 | i++; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2559 | } |
| 2560 | } |
| 2561 | } |
| 2562 | |
| 2563 | /* |
| 2564 | * Load up to 5 arguments, the first three of which will be in |
| 2565 | * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, |
| 2566 | * and as part of the load sequence, it must be replaced with |
| 2567 | * the target method pointer. Note, this may also be called |
| 2568 | * for "range" variants if the number of arguments is 5 or fewer. |
| 2569 | */ |
| 2570 | int X86Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, |
| 2571 | int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, |
| 2572 | const MethodReference& target_method, |
| 2573 | uint32_t vtable_idx, uintptr_t direct_code, |
| 2574 | uintptr_t direct_method, InvokeType type, bool skip_this) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2575 | if (!cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2576 | return Mir2Lir::GenDalvikArgsNoRange(info, |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2577 | call_state, pcrLabel, next_call_insn, |
| 2578 | target_method, |
| 2579 | vtable_idx, direct_code, |
| 2580 | direct_method, type, skip_this); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2581 | } |
| 2582 | return GenDalvikArgsRange(info, |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2583 | call_state, pcrLabel, next_call_insn, |
| 2584 | target_method, |
| 2585 | vtable_idx, direct_code, |
| 2586 | direct_method, type, skip_this); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2587 | } |
| 2588 | |
| 2589 | /* |
| 2590 | * May have 0+ arguments (also used for jumbo). Note that |
| 2591 | * source virtual registers may be in physical registers, so may |
| 2592 | * need to be flushed to home location before copying. This |
| 2593 | * applies to arg3 and above (see below). |
| 2594 | * |
| 2595 | * Two general strategies: |
| 2596 | * If < 20 arguments |
| 2597 | * Pass args 3-18 using vldm/vstm block copy |
| 2598 | * Pass arg0, arg1 & arg2 in kArg1-kArg3 |
| 2599 | * If 20+ arguments |
| 2600 | * Pass args arg19+ using memcpy block copy |
| 2601 | * Pass arg0, arg1 & arg2 in kArg1-kArg3 |
| 2602 | * |
| 2603 | */ |
| 2604 | int X86Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, |
| 2605 | LIR** pcrLabel, NextCallInsn next_call_insn, |
| 2606 | const MethodReference& target_method, |
| 2607 | uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, |
| 2608 | InvokeType type, bool skip_this) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2609 | if (!cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2610 | return Mir2Lir::GenDalvikArgsRange(info, call_state, |
| 2611 | pcrLabel, next_call_insn, |
| 2612 | target_method, |
| 2613 | vtable_idx, direct_code, direct_method, |
| 2614 | type, skip_this); |
| 2615 | } |
| 2616 | |
| 2617 | /* If no arguments, just return */ |
| 2618 | if (info->num_arg_words == 0) |
| 2619 | return call_state; |
| 2620 | |
| 2621 | const int start_index = skip_this ? 1 : 0; |
| 2622 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2623 | InToRegStorageX86_64Mapper mapper(this); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2624 | InToRegStorageMapping in_to_reg_storage_mapping; |
| 2625 | in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); |
| 2626 | const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); |
| 2627 | const int size_of_the_last_mapped = last_mapped_in == -1 ? 1 : |
Serguei Katkov | 8e3acdd | 2014-07-15 12:01:00 +0700 | [diff] [blame] | 2628 | info->args[last_mapped_in].wide ? 2 : 1; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2629 | int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + size_of_the_last_mapped); |
| 2630 | |
| 2631 | // Fisrt of all, check whether it make sense to use bulk copying |
| 2632 | // Optimization is aplicable only for range case |
| 2633 | // TODO: make a constant instead of 2 |
| 2634 | if (info->is_range && regs_left_to_pass_via_stack >= 2) { |
| 2635 | // Scan the rest of the args - if in phys_reg flush to memory |
| 2636 | for (int next_arg = last_mapped_in + size_of_the_last_mapped; next_arg < info->num_arg_words;) { |
| 2637 | RegLocation loc = info->args[next_arg]; |
| 2638 | if (loc.wide) { |
| 2639 | loc = UpdateLocWide(loc); |
| 2640 | if (loc.location == kLocPhysReg) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2641 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2642 | StoreBaseDisp(rs_rX86_SP_64, SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2643 | } |
| 2644 | next_arg += 2; |
| 2645 | } else { |
| 2646 | loc = UpdateLoc(loc); |
| 2647 | if (loc.location == kLocPhysReg) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2648 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2649 | StoreBaseDisp(rs_rX86_SP_64, SRegOffset(loc.s_reg_low), loc.reg, k32, kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2650 | } |
| 2651 | next_arg++; |
| 2652 | } |
| 2653 | } |
| 2654 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2655 | // The rest can be copied together |
| 2656 | int start_offset = SRegOffset(info->args[last_mapped_in + size_of_the_last_mapped].s_reg_low); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2657 | int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + size_of_the_last_mapped, |
| 2658 | cu_->instruction_set); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2659 | |
| 2660 | int current_src_offset = start_offset; |
| 2661 | int current_dest_offset = outs_offset; |
| 2662 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2663 | // Only davik regs are accessed in this loop; no next_call_insn() calls. |
| 2664 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2665 | while (regs_left_to_pass_via_stack > 0) { |
| 2666 | // This is based on the knowledge that the stack itself is 16-byte aligned. |
| 2667 | bool src_is_16b_aligned = (current_src_offset & 0xF) == 0; |
| 2668 | bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0; |
| 2669 | size_t bytes_to_move; |
| 2670 | |
| 2671 | /* |
| 2672 | * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a |
| 2673 | * a 128-bit move because we won't get the chance to try to aligned. If there are more than |
| 2674 | * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned. |
| 2675 | * We do this because we could potentially do a smaller move to align. |
| 2676 | */ |
| 2677 | if (regs_left_to_pass_via_stack == 4 || |
| 2678 | (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) { |
| 2679 | // Moving 128-bits via xmm register. |
| 2680 | bytes_to_move = sizeof(uint32_t) * 4; |
| 2681 | |
| 2682 | // Allocate a free xmm temp. Since we are working through the calling sequence, |
| 2683 | // we expect to have an xmm temporary available. AllocTempDouble will abort if |
| 2684 | // there are no free registers. |
| 2685 | RegStorage temp = AllocTempDouble(); |
| 2686 | |
| 2687 | LIR* ld1 = nullptr; |
| 2688 | LIR* ld2 = nullptr; |
| 2689 | LIR* st1 = nullptr; |
| 2690 | LIR* st2 = nullptr; |
| 2691 | |
| 2692 | /* |
| 2693 | * The logic is similar for both loads and stores. If we have 16-byte alignment, |
| 2694 | * do an aligned move. If we have 8-byte alignment, then do the move in two |
| 2695 | * parts. This approach prevents possible cache line splits. Finally, fall back |
| 2696 | * to doing an unaligned move. In most cases we likely won't split the cache |
| 2697 | * line but we cannot prove it and thus take a conservative approach. |
| 2698 | */ |
| 2699 | bool src_is_8b_aligned = (current_src_offset & 0x7) == 0; |
| 2700 | bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0; |
| 2701 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 2702 | ScopedMemRefType mem_ref_type2(this, ResourceMask::kDalvikReg); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2703 | if (src_is_16b_aligned) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2704 | ld1 = OpMovRegMem(temp, rs_rX86_SP_64, current_src_offset, kMovA128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2705 | } else if (src_is_8b_aligned) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2706 | ld1 = OpMovRegMem(temp, rs_rX86_SP_64, current_src_offset, kMovLo128FP); |
| 2707 | ld2 = OpMovRegMem(temp, rs_rX86_SP_64, current_src_offset + (bytes_to_move >> 1), |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2708 | kMovHi128FP); |
| 2709 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2710 | ld1 = OpMovRegMem(temp, rs_rX86_SP_64, current_src_offset, kMovU128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2711 | } |
| 2712 | |
| 2713 | if (dest_is_16b_aligned) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2714 | st1 = OpMovMemReg(rs_rX86_SP_64, current_dest_offset, temp, kMovA128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2715 | } else if (dest_is_8b_aligned) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2716 | st1 = OpMovMemReg(rs_rX86_SP_64, current_dest_offset, temp, kMovLo128FP); |
| 2717 | st2 = OpMovMemReg(rs_rX86_SP_64, current_dest_offset + (bytes_to_move >> 1), |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2718 | temp, kMovHi128FP); |
| 2719 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2720 | st1 = OpMovMemReg(rs_rX86_SP_64, current_dest_offset, temp, kMovU128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2721 | } |
| 2722 | |
| 2723 | // TODO If we could keep track of aliasing information for memory accesses that are wider |
| 2724 | // than 64-bit, we wouldn't need to set up a barrier. |
| 2725 | if (ld1 != nullptr) { |
| 2726 | if (ld2 != nullptr) { |
| 2727 | // For 64-bit load we can actually set up the aliasing information. |
| 2728 | AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); |
| 2729 | AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, true); |
| 2730 | } else { |
| 2731 | // Set barrier for 128-bit load. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2732 | ld1->u.m.def_mask = &kEncodeAll; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2733 | } |
| 2734 | } |
| 2735 | if (st1 != nullptr) { |
| 2736 | if (st2 != nullptr) { |
| 2737 | // For 64-bit store we can actually set up the aliasing information. |
| 2738 | AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); |
| 2739 | AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, true); |
| 2740 | } else { |
| 2741 | // Set barrier for 128-bit store. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2742 | st1->u.m.def_mask = &kEncodeAll; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2743 | } |
| 2744 | } |
| 2745 | |
| 2746 | // Free the temporary used for the data movement. |
| 2747 | FreeTemp(temp); |
| 2748 | } else { |
| 2749 | // Moving 32-bits via general purpose register. |
| 2750 | bytes_to_move = sizeof(uint32_t); |
| 2751 | |
| 2752 | // Instead of allocating a new temp, simply reuse one of the registers being used |
| 2753 | // for argument passing. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2754 | RegStorage temp = TargetReg(kArg3, kNotWide); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2755 | |
| 2756 | // Now load the argument VR and store to the outs. |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2757 | Load32Disp(rs_rX86_SP_64, current_src_offset, temp); |
| 2758 | Store32Disp(rs_rX86_SP_64, current_dest_offset, temp); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2759 | } |
| 2760 | |
| 2761 | current_src_offset += bytes_to_move; |
| 2762 | current_dest_offset += bytes_to_move; |
| 2763 | regs_left_to_pass_via_stack -= (bytes_to_move >> 2); |
| 2764 | } |
| 2765 | DCHECK_EQ(regs_left_to_pass_via_stack, 0); |
| 2766 | } |
| 2767 | |
| 2768 | // Now handle rest not registers if they are |
| 2769 | if (in_to_reg_storage_mapping.IsThereStackMapped()) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2770 | RegStorage regSingle = TargetReg(kArg2, kNotWide); |
| 2771 | RegStorage regWide = TargetReg(kArg3, kWide); |
Chao-ying Fu | b6564c1 | 2014-06-24 13:24:36 -0700 | [diff] [blame] | 2772 | for (int i = start_index; |
| 2773 | i < last_mapped_in + size_of_the_last_mapped + regs_left_to_pass_via_stack; i++) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2774 | RegLocation rl_arg = info->args[i]; |
| 2775 | rl_arg = UpdateRawLoc(rl_arg); |
| 2776 | RegStorage reg = in_to_reg_storage_mapping.Get(i); |
| 2777 | if (!reg.Valid()) { |
| 2778 | int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); |
| 2779 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2780 | { |
| 2781 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 2782 | if (rl_arg.wide) { |
| 2783 | if (rl_arg.location == kLocPhysReg) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2784 | StoreBaseDisp(rs_rX86_SP_64, out_offset, rl_arg.reg, k64, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2785 | } else { |
| 2786 | LoadValueDirectWideFixed(rl_arg, regWide); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2787 | StoreBaseDisp(rs_rX86_SP_64, out_offset, regWide, k64, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2788 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2789 | } else { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2790 | if (rl_arg.location == kLocPhysReg) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2791 | StoreBaseDisp(rs_rX86_SP_64, out_offset, rl_arg.reg, k32, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2792 | } else { |
| 2793 | LoadValueDirectFixed(rl_arg, regSingle); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2794 | StoreBaseDisp(rs_rX86_SP_64, out_offset, regSingle, k32, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2795 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2796 | } |
| 2797 | } |
| 2798 | call_state = next_call_insn(cu_, info, call_state, target_method, |
| 2799 | vtable_idx, direct_code, direct_method, type); |
| 2800 | } |
Chao-ying Fu | b6564c1 | 2014-06-24 13:24:36 -0700 | [diff] [blame] | 2801 | if (rl_arg.wide) { |
| 2802 | i++; |
| 2803 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2804 | } |
| 2805 | } |
| 2806 | |
| 2807 | // Finish with mapped registers |
| 2808 | for (int i = start_index; i <= last_mapped_in; i++) { |
| 2809 | RegLocation rl_arg = info->args[i]; |
| 2810 | rl_arg = UpdateRawLoc(rl_arg); |
| 2811 | RegStorage reg = in_to_reg_storage_mapping.Get(i); |
| 2812 | if (reg.Valid()) { |
| 2813 | if (rl_arg.wide) { |
| 2814 | LoadValueDirectWideFixed(rl_arg, reg); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2815 | } else { |
| 2816 | LoadValueDirectFixed(rl_arg, reg); |
| 2817 | } |
| 2818 | call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, |
| 2819 | direct_code, direct_method, type); |
| 2820 | } |
Chao-ying Fu | b6564c1 | 2014-06-24 13:24:36 -0700 | [diff] [blame] | 2821 | if (rl_arg.wide) { |
| 2822 | i++; |
| 2823 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2824 | } |
| 2825 | |
| 2826 | call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, |
| 2827 | direct_code, direct_method, type); |
| 2828 | if (pcrLabel) { |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 2829 | if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2830 | *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2831 | } else { |
| 2832 | *pcrLabel = nullptr; |
| 2833 | // In lieu of generating a check for kArg1 being null, we need to |
| 2834 | // perform a load when doing implicit checks. |
| 2835 | RegStorage tmp = AllocTemp(); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2836 | Load32Disp(TargetReg(kArg1, kRef), 0, tmp); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2837 | MarkPossibleNullPointerException(info->opt_flags); |
| 2838 | FreeTemp(tmp); |
| 2839 | } |
| 2840 | } |
| 2841 | return call_state; |
| 2842 | } |
| 2843 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 2844 | bool X86Mir2Lir::GenInlinedCharAt(CallInfo* info) { |
| 2845 | // Location of reference to data array |
| 2846 | int value_offset = mirror::String::ValueOffset().Int32Value(); |
| 2847 | // Location of count |
| 2848 | int count_offset = mirror::String::CountOffset().Int32Value(); |
| 2849 | // Starting offset within data array |
| 2850 | int offset_offset = mirror::String::OffsetOffset().Int32Value(); |
| 2851 | // Start of char data with array_ |
| 2852 | int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); |
| 2853 | |
| 2854 | RegLocation rl_obj = info->args[0]; |
| 2855 | RegLocation rl_idx = info->args[1]; |
| 2856 | rl_obj = LoadValue(rl_obj, kRefReg); |
| 2857 | // X86 wants to avoid putting a constant index into a register. |
| 2858 | if (!rl_idx.is_const) { |
| 2859 | rl_idx = LoadValue(rl_idx, kCoreReg); |
| 2860 | } |
| 2861 | RegStorage reg_max; |
| 2862 | GenNullCheck(rl_obj.reg, info->opt_flags); |
| 2863 | bool range_check = (!(info->opt_flags & MIR_IGNORE_RANGE_CHECK)); |
| 2864 | LIR* range_check_branch = nullptr; |
| 2865 | RegStorage reg_off; |
| 2866 | RegStorage reg_ptr; |
| 2867 | if (range_check) { |
| 2868 | // On x86, we can compare to memory directly |
| 2869 | // Set up a launch pad to allow retry in case of bounds violation */ |
| 2870 | if (rl_idx.is_const) { |
| 2871 | LIR* comparison; |
| 2872 | range_check_branch = OpCmpMemImmBranch( |
| 2873 | kCondUlt, RegStorage::InvalidReg(), rl_obj.reg, count_offset, |
| 2874 | mir_graph_->ConstantValue(rl_idx.orig_sreg), nullptr, &comparison); |
| 2875 | MarkPossibleNullPointerExceptionAfter(0, comparison); |
| 2876 | } else { |
| 2877 | OpRegMem(kOpCmp, rl_idx.reg, rl_obj.reg, count_offset); |
| 2878 | MarkPossibleNullPointerException(0); |
| 2879 | range_check_branch = OpCondBranch(kCondUge, nullptr); |
| 2880 | } |
| 2881 | } |
| 2882 | reg_off = AllocTemp(); |
| 2883 | reg_ptr = AllocTempRef(); |
| 2884 | Load32Disp(rl_obj.reg, offset_offset, reg_off); |
| 2885 | LoadRefDisp(rl_obj.reg, value_offset, reg_ptr, kNotVolatile); |
| 2886 | if (rl_idx.is_const) { |
| 2887 | OpRegImm(kOpAdd, reg_off, mir_graph_->ConstantValue(rl_idx.orig_sreg)); |
| 2888 | } else { |
| 2889 | OpRegReg(kOpAdd, reg_off, rl_idx.reg); |
| 2890 | } |
| 2891 | FreeTemp(rl_obj.reg); |
| 2892 | if (rl_idx.location == kLocPhysReg) { |
| 2893 | FreeTemp(rl_idx.reg); |
| 2894 | } |
| 2895 | RegLocation rl_dest = InlineTarget(info); |
| 2896 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 2897 | LoadBaseIndexedDisp(reg_ptr, reg_off, 1, data_offset, rl_result.reg, kUnsignedHalf); |
| 2898 | FreeTemp(reg_off); |
| 2899 | FreeTemp(reg_ptr); |
| 2900 | StoreValue(rl_dest, rl_result); |
| 2901 | if (range_check) { |
| 2902 | DCHECK(range_check_branch != nullptr); |
| 2903 | info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've already null checked. |
| 2904 | AddIntrinsicSlowPath(info, range_check_branch); |
| 2905 | } |
| 2906 | return true; |
| 2907 | } |
| 2908 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2909 | bool X86Mir2Lir::GenInlinedCurrentThread(CallInfo* info) { |
| 2910 | RegLocation rl_dest = InlineTarget(info); |
| 2911 | |
| 2912 | // Early exit if the result is unused. |
| 2913 | if (rl_dest.orig_sreg < 0) { |
| 2914 | return true; |
| 2915 | } |
| 2916 | |
| 2917 | RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); |
| 2918 | |
| 2919 | if (cu_->target64) { |
| 2920 | OpRegThreadMem(kOpMov, rl_result.reg, Thread::PeerOffset<8>()); |
| 2921 | } else { |
| 2922 | OpRegThreadMem(kOpMov, rl_result.reg, Thread::PeerOffset<4>()); |
| 2923 | } |
| 2924 | |
| 2925 | StoreValue(rl_dest, rl_result); |
| 2926 | return true; |
| 2927 | } |
| 2928 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 2929 | /** |
| 2930 | * Lock temp registers for explicit usage. Registers will be freed in destructor. |
| 2931 | */ |
| 2932 | X86Mir2Lir::ExplicitTempRegisterLock::ExplicitTempRegisterLock(X86Mir2Lir* mir_to_lir, |
| 2933 | int n_regs, ...) : |
| 2934 | temp_regs_(n_regs), |
| 2935 | mir_to_lir_(mir_to_lir) { |
| 2936 | va_list regs; |
| 2937 | va_start(regs, n_regs); |
| 2938 | for (int i = 0; i < n_regs; i++) { |
| 2939 | RegStorage reg = *(va_arg(regs, RegStorage*)); |
| 2940 | RegisterInfo* info = mir_to_lir_->GetRegInfo(reg); |
| 2941 | |
| 2942 | // Make sure we don't have promoted register here. |
| 2943 | DCHECK(info->IsTemp()); |
| 2944 | |
| 2945 | temp_regs_.push_back(reg); |
| 2946 | mir_to_lir_->FlushReg(reg); |
| 2947 | |
| 2948 | if (reg.IsPair()) { |
| 2949 | RegStorage partner = info->Partner(); |
| 2950 | temp_regs_.push_back(partner); |
| 2951 | mir_to_lir_->FlushReg(partner); |
| 2952 | } |
| 2953 | |
| 2954 | mir_to_lir_->Clobber(reg); |
| 2955 | mir_to_lir_->LockTemp(reg); |
| 2956 | } |
| 2957 | |
| 2958 | va_end(regs); |
| 2959 | } |
| 2960 | |
| 2961 | /* |
| 2962 | * Free all locked registers. |
| 2963 | */ |
| 2964 | X86Mir2Lir::ExplicitTempRegisterLock::~ExplicitTempRegisterLock() { |
| 2965 | // Free all locked temps. |
| 2966 | for (auto it : temp_regs_) { |
| 2967 | mir_to_lir_->FreeTemp(it); |
| 2968 | } |
| 2969 | } |
| 2970 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 2971 | } // namespace art |