Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2020 Collabora Ltd. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors (Collabora): |
| 24 | * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> |
| 25 | */ |
| 26 | |
| 27 | #ifndef __BIFROST_COMPILER_H |
| 28 | #define __BIFROST_COMPILER_H |
| 29 | |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 30 | #include "bifrost.h" |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 31 | #include "compiler/nir/nir.h" |
Alyssa Rosenzweig | 9b8cb9f | 2020-03-09 20:19:29 -0400 | [diff] [blame] | 32 | #include "panfrost/util/pan_ir.h" |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 33 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 34 | /* Bifrost opcodes are tricky -- the same op may exist on both FMA and |
| 35 | * ADD with two completely different opcodes, and opcodes can be varying |
| 36 | * length in some cases. Then we have different opcodes for int vs float |
| 37 | * and then sometimes even for different typesizes. Further, virtually |
| 38 | * every op has a number of flags which depend on the op. In constrast |
| 39 | * to Midgard where you have a strict ALU/LDST/TEX division and within |
| 40 | * ALU you have strict int/float and that's it... here it's a *lot* more |
| 41 | * involved. As such, we use something much higher level for our IR, |
| 42 | * encoding "classes" of operations, letting the opcode details get |
| 43 | * sorted out at emit time. |
| 44 | * |
| 45 | * Please keep this list alphabetized. Please use a dictionary if you |
| 46 | * don't know how to do that. |
| 47 | */ |
| 48 | |
| 49 | enum bi_class { |
| 50 | BI_ADD, |
| 51 | BI_ATEST, |
| 52 | BI_BRANCH, |
| 53 | BI_CMP, |
| 54 | BI_BLEND, |
| 55 | BI_BITWISE, |
Alyssa Rosenzweig | e0a51d5 | 2020-03-22 17:31:23 -0400 | [diff] [blame] | 56 | BI_COMBINE, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 57 | BI_CONVERT, |
| 58 | BI_CSEL, |
| 59 | BI_DISCARD, |
| 60 | BI_FMA, |
Alyssa Rosenzweig | 6b7077e | 2020-03-19 16:58:48 -0400 | [diff] [blame] | 61 | BI_FMOV, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 62 | BI_FREXP, |
Alyssa Rosenzweig | 1a94dae | 2020-05-04 14:00:13 -0400 | [diff] [blame] | 63 | BI_IMATH, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 64 | BI_LOAD, |
Alyssa Rosenzweig | 1ead0d3 | 2020-03-06 09:52:09 -0500 | [diff] [blame] | 65 | BI_LOAD_UNIFORM, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 66 | BI_LOAD_ATTR, |
| 67 | BI_LOAD_VAR, |
| 68 | BI_LOAD_VAR_ADDRESS, |
Boris Brezillon | 8da0a1d | 2020-10-12 15:02:29 +0200 | [diff] [blame] | 69 | BI_LOAD_TILE, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 70 | BI_MINMAX, |
| 71 | BI_MOV, |
Alyssa Rosenzweig | 62c8c34 | 2020-04-14 12:33:08 -0400 | [diff] [blame] | 72 | BI_REDUCE_FMA, |
Alyssa Rosenzweig | ee561f0 | 2020-04-24 19:10:44 -0400 | [diff] [blame] | 73 | BI_SELECT, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 74 | BI_STORE, |
| 75 | BI_STORE_VAR, |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 76 | BI_SPECIAL, /* _FAST on supported GPUs */ |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 77 | BI_TABLE, |
Alyssa Rosenzweig | 6ed1bdf | 2020-10-06 10:31:04 -0400 | [diff] [blame] | 78 | BI_TEXS, |
| 79 | BI_TEXC, |
| 80 | BI_TEXC_DUAL, |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 81 | BI_ROUND, |
Chris Forbes | a0a7087 | 2020-07-26 15:54:14 -0700 | [diff] [blame] | 82 | BI_IMUL, |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 83 | BI_NUM_CLASSES |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 84 | }; |
| 85 | |
Alyssa Rosenzweig | 7ac6212 | 2020-03-02 20:38:26 -0500 | [diff] [blame] | 86 | /* Properties of a class... */ |
| 87 | extern unsigned bi_class_props[BI_NUM_CLASSES]; |
| 88 | |
| 89 | /* abs/neg/outmod valid for a float op */ |
| 90 | #define BI_MODS (1 << 0) |
| 91 | |
Alyssa Rosenzweig | 6627b20 | 2020-05-01 18:13:54 -0400 | [diff] [blame] | 92 | /* Accepts a bi_cond */ |
| 93 | #define BI_CONDITIONAL (1 << 1) |
Alyssa Rosenzweig | 34165c7 | 2020-03-02 20:46:37 -0500 | [diff] [blame] | 94 | |
Alyssa Rosenzweig | d69bf8d | 2020-03-02 20:52:36 -0500 | [diff] [blame] | 95 | /* Accepts a bifrost_roundmode */ |
| 96 | #define BI_ROUNDMODE (1 << 2) |
| 97 | |
Alyssa Rosenzweig | 99f3c1f | 2020-03-02 21:53:13 -0500 | [diff] [blame] | 98 | /* Can be scheduled to FMA */ |
| 99 | #define BI_SCHED_FMA (1 << 3) |
| 100 | |
| 101 | /* Can be scheduled to ADD */ |
| 102 | #define BI_SCHED_ADD (1 << 4) |
| 103 | |
| 104 | /* Most ALU ops can do either, actually */ |
| 105 | #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD) |
| 106 | |
Alyssa Rosenzweig | c70a198 | 2020-03-03 08:16:50 -0500 | [diff] [blame] | 107 | /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be |
| 108 | * nopped out. Used for _FAST operations. */ |
| 109 | #define BI_SCHED_SLOW (1 << 5) |
| 110 | |
Alyssa Rosenzweig | 5896db9 | 2020-03-03 08:35:51 -0500 | [diff] [blame] | 111 | /* Swizzling allowed for the 8/16-bit source */ |
| 112 | #define BI_SWIZZLABLE (1 << 6) |
| 113 | |
Alyssa Rosenzweig | 07228a6 | 2020-03-03 13:55:33 -0500 | [diff] [blame] | 114 | /* For scheduling purposes this is a high latency instruction and must be at |
| 115 | * the end of a clause. Implies ADD */ |
Alyssa Rosenzweig | e323df0 | 2020-03-18 13:42:12 -0400 | [diff] [blame] | 116 | #define BI_SCHED_HI_LATENCY (1 << 7) |
Alyssa Rosenzweig | 07228a6 | 2020-03-03 13:55:33 -0500 | [diff] [blame] | 117 | |
Alyssa Rosenzweig | b2c6cf2 | 2020-04-24 17:20:28 -0400 | [diff] [blame] | 118 | /* Intrinsic is vectorized and acts with `vector_channels` components */ |
Alyssa Rosenzweig | e1d9533 | 2020-03-11 21:41:57 -0400 | [diff] [blame] | 119 | #define BI_VECTOR (1 << 8) |
| 120 | |
Alyssa Rosenzweig | d4fbf75 | 2020-03-18 12:08:28 -0400 | [diff] [blame] | 121 | /* Use a data register for src0/dest respectively, bypassing the usual |
Alyssa Rosenzweig | 3089501 | 2020-10-06 12:14:32 -0400 | [diff] [blame] | 122 | * register accessor. */ |
Alyssa Rosenzweig | d4fbf75 | 2020-03-18 12:08:28 -0400 | [diff] [blame] | 123 | #define BI_DATA_REG_SRC (1 << 9) |
| 124 | #define BI_DATA_REG_DEST (1 << 10) |
| 125 | |
Alyssa Rosenzweig | bd19e76 | 2020-03-30 12:25:20 -0400 | [diff] [blame] | 126 | /* Quirk: cannot encode multiple abs on FMA in fp16 mode */ |
| 127 | #define BI_NO_ABS_ABS_FP16_FMA (1 << 11) |
| 128 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 129 | /* It can't get any worse than csel4... can it? */ |
| 130 | #define BIR_SRC_COUNT 4 |
| 131 | |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 132 | /* BI_LD_VARY */ |
| 133 | struct bi_load_vary { |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 134 | enum bifrost_interp_mode interp_mode; |
| 135 | bool reuse; |
| 136 | bool flat; |
| 137 | }; |
| 138 | |
Alyssa Rosenzweig | 47451bb | 2020-03-03 13:48:13 -0500 | [diff] [blame] | 139 | /* BI_BRANCH encoding the details of the branch itself as well as a pointer to |
| 140 | * the target. We forward declare bi_block since this is mildly circular (not |
| 141 | * strictly, but this order of the file makes more sense I think) |
| 142 | * |
| 143 | * We define our own enum of conditions since the conditions in the hardware |
| 144 | * packed in crazy ways that would make manipulation unweildly (meaning changes |
Alyssa Rosenzweig | 514da97 | 2020-09-20 15:34:38 -0400 | [diff] [blame] | 145 | * based on slot swapping, etc), so we defer dealing with that until emit time. |
Alyssa Rosenzweig | 47451bb | 2020-03-03 13:48:13 -0500 | [diff] [blame] | 146 | * Likewise, we expose NIR types instead of the crazy branch types, although |
| 147 | * the restrictions do eventually apply of course. */ |
| 148 | |
| 149 | struct bi_block; |
| 150 | |
Alyssa Rosenzweig | 2ff5387 | 2020-08-03 12:48:44 -0400 | [diff] [blame] | 151 | /* Sync with gen-pack.py */ |
Alyssa Rosenzweig | 47451bb | 2020-03-03 13:48:13 -0500 | [diff] [blame] | 152 | enum bi_cond { |
Alyssa Rosenzweig | 2ff5387 | 2020-08-03 12:48:44 -0400 | [diff] [blame] | 153 | BI_COND_ALWAYS = 0, |
Alyssa Rosenzweig | 47451bb | 2020-03-03 13:48:13 -0500 | [diff] [blame] | 154 | BI_COND_LT, |
| 155 | BI_COND_LE, |
| 156 | BI_COND_GE, |
| 157 | BI_COND_GT, |
| 158 | BI_COND_EQ, |
| 159 | BI_COND_NE, |
| 160 | }; |
| 161 | |
Alyssa Rosenzweig | 6f5b788 | 2020-07-31 17:29:50 -0400 | [diff] [blame] | 162 | /* Segments, as synced with ISA. Used as an immediate in LOAD/STORE |
| 163 | * instructions for address calculation, and directly in SEG_ADD/SEG_SUB |
| 164 | * instructions. */ |
| 165 | |
| 166 | enum bi_segment { |
| 167 | /* No segment (use global addressing, offset from GPU VA 0x0) */ |
| 168 | BI_SEGMENT_NONE = 1, |
| 169 | |
| 170 | /* Within workgroup local memory (shared memory). Relative to |
| 171 | * wls_base_pointer in the draw's thread storage descriptor */ |
| 172 | BI_SEGMENT_WLS = 2, |
| 173 | |
| 174 | /* Within one of the bound uniform buffers. Low 32-bits are the index |
| 175 | * within the uniform buffer; high 32-bits are the index of the uniform |
| 176 | * buffer itself. Relative to the uniform_array_pointer indexed within |
| 177 | * the draw's uniform remap table indexed by the high 32-bits. */ |
| 178 | BI_SEGMENT_UBO = 4, |
| 179 | |
| 180 | /* Within thread local storage (for spilling). Relative to |
| 181 | * tls_base_pointer in the draw's thread storage descriptor */ |
| 182 | BI_SEGMENT_TLS = 7 |
| 183 | }; |
| 184 | |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame] | 185 | /* Opcodes within a class */ |
| 186 | enum bi_minmax_op { |
| 187 | BI_MINMAX_MIN, |
| 188 | BI_MINMAX_MAX |
| 189 | }; |
| 190 | |
| 191 | enum bi_bitwise_op { |
| 192 | BI_BITWISE_AND, |
| 193 | BI_BITWISE_OR, |
| 194 | BI_BITWISE_XOR |
| 195 | }; |
| 196 | |
Alyssa Rosenzweig | cf3c356 | 2020-05-04 14:04:35 -0400 | [diff] [blame] | 197 | enum bi_imath_op { |
| 198 | BI_IMATH_ADD, |
| 199 | BI_IMATH_SUB, |
| 200 | }; |
| 201 | |
Chris Forbes | a0a7087 | 2020-07-26 15:54:14 -0700 | [diff] [blame] | 202 | enum bi_imul_op { |
| 203 | BI_IMUL_IMUL, |
| 204 | }; |
| 205 | |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 206 | enum bi_table_op { |
| 207 | /* fp32 log2() with low precision, suitable for GL or half_log2() in |
| 208 | * CL. In the first argument, takes x. Letting u be such that x = |
| 209 | * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns |
| 210 | * log2(u) / (u - 1). */ |
| 211 | |
| 212 | BI_TABLE_LOG2_U_OVER_U_1_LOW, |
| 213 | }; |
| 214 | |
Alyssa Rosenzweig | 62c8c34 | 2020-04-14 12:33:08 -0400 | [diff] [blame] | 215 | enum bi_reduce_op { |
| 216 | /* Takes two fp32 arguments and returns x + frexp(y). Used in |
| 217 | * low-precision log2 argument reduction on newer models. */ |
| 218 | |
| 219 | BI_REDUCE_ADD_FREXPM, |
| 220 | }; |
| 221 | |
Alyssa Rosenzweig | e067fd7 | 2020-04-14 12:37:29 -0400 | [diff] [blame] | 222 | enum bi_frexp_op { |
| 223 | BI_FREXPE_LOG, |
| 224 | }; |
| 225 | |
Alyssa Rosenzweig | b674e39 | 2020-03-09 21:20:03 -0400 | [diff] [blame] | 226 | enum bi_special_op { |
| 227 | BI_SPECIAL_FRCP, |
| 228 | BI_SPECIAL_FRSQ, |
Alyssa Rosenzweig | cc61156 | 2020-04-14 12:22:28 -0400 | [diff] [blame] | 229 | |
| 230 | /* fp32 exp2() with low precision, suitable for half_exp2() in CL or |
| 231 | * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In |
| 232 | * the second, it takes x itself. */ |
| 233 | BI_SPECIAL_EXP2_LOW, |
Chris Forbes | 1882b1e | 2020-07-27 11:51:31 -0700 | [diff] [blame] | 234 | BI_SPECIAL_IABS, |
Alyssa Rosenzweig | b674e39 | 2020-03-09 21:20:03 -0400 | [diff] [blame] | 235 | }; |
| 236 | |
Alyssa Rosenzweig | 9b415bf | 2020-04-28 13:48:37 -0400 | [diff] [blame] | 237 | struct bi_bitwise { |
Alyssa Rosenzweig | d2158a5 | 2020-09-09 17:46:58 -0400 | [diff] [blame] | 238 | bool dest_invert; |
| 239 | bool src1_invert; |
Alyssa Rosenzweig | 9b415bf | 2020-04-28 13:48:37 -0400 | [diff] [blame] | 240 | bool rshift; /* false for lshift */ |
| 241 | }; |
| 242 | |
Alyssa Rosenzweig | fc634dc | 2020-04-30 16:08:01 -0400 | [diff] [blame] | 243 | struct bi_texture { |
| 244 | /* Constant indices. Indirect would need to be in src[..] like normal, |
| 245 | * we can reserve some sentinels there for that for future. */ |
| 246 | unsigned texture_index, sampler_index; |
Alyssa Rosenzweig | 67d8956 | 2020-08-03 12:47:57 -0400 | [diff] [blame] | 247 | |
| 248 | /* Should the LOD be computed based on neighboring pixels? Only valid |
| 249 | * in fragment shaders. */ |
| 250 | bool compute_lod; |
Alyssa Rosenzweig | fc634dc | 2020-04-30 16:08:01 -0400 | [diff] [blame] | 251 | }; |
| 252 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 253 | typedef struct { |
| 254 | struct list_head link; /* Must be first */ |
| 255 | enum bi_class type; |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 256 | |
Alyssa Rosenzweig | fbbe3d4 | 2020-04-27 16:04:05 -0400 | [diff] [blame] | 257 | /* Indices, see pan_ssa_index etc. Note zero is special cased |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 258 | * to "no argument" */ |
| 259 | unsigned dest; |
| 260 | unsigned src[BIR_SRC_COUNT]; |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 261 | |
Alyssa Rosenzweig | b2c6cf2 | 2020-04-24 17:20:28 -0400 | [diff] [blame] | 262 | /* 32-bit word offset for destination, added to the register number in |
| 263 | * RA when lowering combines */ |
| 264 | unsigned dest_offset; |
| 265 | |
Alyssa Rosenzweig | 795646d | 2020-03-09 14:09:04 -0400 | [diff] [blame] | 266 | /* If one of the sources has BIR_INDEX_CONSTANT */ |
Alyssa Rosenzweig | b5bdd89 | 2020-03-03 07:47:29 -0500 | [diff] [blame] | 267 | union { |
| 268 | uint64_t u64; |
| 269 | uint32_t u32; |
| 270 | uint16_t u16[2]; |
| 271 | uint8_t u8[4]; |
| 272 | } constant; |
| 273 | |
Alyssa Rosenzweig | 29acd7b | 2020-03-02 20:40:52 -0500 | [diff] [blame] | 274 | /* Floating-point modifiers, type/class permitting. If not |
| 275 | * allowed for the type/class, these are ignored. */ |
| 276 | enum bifrost_outmod outmod; |
| 277 | bool src_abs[BIR_SRC_COUNT]; |
| 278 | bool src_neg[BIR_SRC_COUNT]; |
Alyssa Rosenzweig | d69bf8d | 2020-03-02 20:52:36 -0500 | [diff] [blame] | 279 | |
| 280 | /* Round mode (requires BI_ROUNDMODE) */ |
| 281 | enum bifrost_roundmode roundmode; |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 282 | |
Alyssa Rosenzweig | c42002d | 2020-03-02 22:03:05 -0500 | [diff] [blame] | 283 | /* Destination type. Usually the type of the instruction |
| 284 | * itself, but if sources and destination have different |
| 285 | * types, the type of the destination wins (so f2i would be |
| 286 | * int). Zero if there is no destination. Bitsize included */ |
| 287 | nir_alu_type dest_type; |
| 288 | |
Alyssa Rosenzweig | 8929fe0 | 2020-03-03 08:37:15 -0500 | [diff] [blame] | 289 | /* Source types if required by the class */ |
| 290 | nir_alu_type src_types[BIR_SRC_COUNT]; |
| 291 | |
Alyssa Rosenzweig | 8dd3a81 | 2020-07-31 18:48:27 -0400 | [diff] [blame] | 292 | /* register_format if applicable */ |
| 293 | nir_alu_type format; |
| 294 | |
Alyssa Rosenzweig | 795646d | 2020-03-09 14:09:04 -0400 | [diff] [blame] | 295 | /* If the source type is 8-bit or 16-bit such that SIMD is possible, |
| 296 | * and the class has BI_SWIZZLABLE, this is a swizzle in the usual |
| 297 | * sense. On non-SIMD instructions, it can be used for component |
| 298 | * selection, so we don't have to special case extraction. */ |
| 299 | uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS]; |
Alyssa Rosenzweig | 5896db9 | 2020-03-03 08:35:51 -0500 | [diff] [blame] | 300 | |
Alyssa Rosenzweig | b2c6cf2 | 2020-04-24 17:20:28 -0400 | [diff] [blame] | 301 | /* For VECTOR ops, how many channels are written? */ |
| 302 | unsigned vector_channels; |
| 303 | |
Alyssa Rosenzweig | 39ec3eb | 2020-10-06 10:42:39 -0400 | [diff] [blame] | 304 | /* For texture ops, the skip bit. Set if helper invocations can skip |
| 305 | * the operation. That is, set if the result of this texture operation |
| 306 | * is never used for cross-lane operation (including texture |
| 307 | * coordinates and derivatives) as determined by data flow analysis |
| 308 | * (like Midgard) */ |
| 309 | bool skip; |
| 310 | |
Alyssa Rosenzweig | 6627b20 | 2020-05-01 18:13:54 -0400 | [diff] [blame] | 311 | /* The comparison op. BI_COND_ALWAYS may not be valid. */ |
| 312 | enum bi_cond cond; |
| 313 | |
Alyssa Rosenzweig | 6f5b788 | 2020-07-31 17:29:50 -0400 | [diff] [blame] | 314 | /* For memory ops, base address */ |
| 315 | enum bi_segment segment; |
| 316 | |
Alyssa Rosenzweig | ab9abc9 | 2020-10-14 18:57:20 -0400 | [diff] [blame] | 317 | /* Can we spill the value written here? Used to prevent |
| 318 | * useless double fills */ |
| 319 | bool no_spill; |
| 320 | |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame] | 321 | /* A class-specific op from which the actual opcode can be derived |
| 322 | * (along with the above information) */ |
| 323 | |
| 324 | union { |
| 325 | enum bi_minmax_op minmax; |
| 326 | enum bi_bitwise_op bitwise; |
Alyssa Rosenzweig | b674e39 | 2020-03-09 21:20:03 -0400 | [diff] [blame] | 327 | enum bi_special_op special; |
Alyssa Rosenzweig | 62c8c34 | 2020-04-14 12:33:08 -0400 | [diff] [blame] | 328 | enum bi_reduce_op reduce; |
Alyssa Rosenzweig | af01378 | 2020-04-14 12:21:25 -0400 | [diff] [blame] | 329 | enum bi_table_op table; |
Alyssa Rosenzweig | e067fd7 | 2020-04-14 12:37:29 -0400 | [diff] [blame] | 330 | enum bi_frexp_op frexp; |
Alyssa Rosenzweig | cf3c356 | 2020-05-04 14:04:35 -0400 | [diff] [blame] | 331 | enum bi_imath_op imath; |
Chris Forbes | a0a7087 | 2020-07-26 15:54:14 -0700 | [diff] [blame] | 332 | enum bi_imul_op imul; |
Alyssa Rosenzweig | 4570c34 | 2020-04-14 16:13:53 -0400 | [diff] [blame] | 333 | |
| 334 | /* For FMA/ADD, should we add a biased exponent? */ |
| 335 | bool mscale; |
Alyssa Rosenzweig | 44ebc27 | 2020-03-03 07:58:05 -0500 | [diff] [blame] | 336 | } op; |
| 337 | |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 338 | /* Union for class-specific information */ |
| 339 | union { |
| 340 | enum bifrost_minmax_mode minmax; |
Alyssa Rosenzweig | 9643b9d | 2020-03-02 21:48:51 -0500 | [diff] [blame] | 341 | struct bi_load_vary load_vary; |
Alyssa Rosenzweig | 6627b20 | 2020-05-01 18:13:54 -0400 | [diff] [blame] | 342 | struct bi_block *branch_target; |
Alyssa Rosenzweig | 92a4f26 | 2020-03-06 09:25:58 -0500 | [diff] [blame] | 343 | |
| 344 | /* For BLEND -- the location 0-7 */ |
| 345 | unsigned blend_location; |
Alyssa Rosenzweig | 9b415bf | 2020-04-28 13:48:37 -0400 | [diff] [blame] | 346 | |
| 347 | struct bi_bitwise bitwise; |
Alyssa Rosenzweig | fc634dc | 2020-04-30 16:08:01 -0400 | [diff] [blame] | 348 | struct bi_texture texture; |
Alyssa Rosenzweig | b93aec6 | 2020-03-02 20:53:47 -0500 | [diff] [blame] | 349 | }; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 350 | } bi_instruction; |
| 351 | |
Alyssa Rosenzweig | 514da97 | 2020-09-20 15:34:38 -0400 | [diff] [blame] | 352 | /* Represents the assignment of slots for a given bi_bundle */ |
Alyssa Rosenzweig | 79f30d8 | 2020-05-05 14:23:41 -0400 | [diff] [blame] | 353 | |
Alyssa Rosenzweig | dd96b45 | 2020-05-05 14:30:06 -0400 | [diff] [blame] | 354 | typedef struct { |
Alyssa Rosenzweig | 514da97 | 2020-09-20 15:34:38 -0400 | [diff] [blame] | 355 | /* Register to assign to each slot */ |
| 356 | unsigned slot[4]; |
Alyssa Rosenzweig | 79f30d8 | 2020-05-05 14:23:41 -0400 | [diff] [blame] | 357 | |
Alyssa Rosenzweig | 514da97 | 2020-09-20 15:34:38 -0400 | [diff] [blame] | 358 | /* Read slots can be disabled */ |
Alyssa Rosenzweig | 79f30d8 | 2020-05-05 14:23:41 -0400 | [diff] [blame] | 359 | bool enabled[2]; |
| 360 | |
Alyssa Rosenzweig | 7a0f3b6 | 2020-09-20 16:24:04 -0400 | [diff] [blame] | 361 | /* Configuration for slots 2/3 */ |
| 362 | struct bifrost_reg_ctrl_23 slot23; |
Alyssa Rosenzweig | 79f30d8 | 2020-05-05 14:23:41 -0400 | [diff] [blame] | 363 | |
Boris Brezillon | f25850b | 2020-10-12 10:57:40 +0200 | [diff] [blame] | 364 | /* Fast-Access-Uniform RAM index */ |
| 365 | uint8_t fau_idx; |
Alyssa Rosenzweig | 79f30d8 | 2020-05-05 14:23:41 -0400 | [diff] [blame] | 366 | |
| 367 | /* Whether writes are actually for the last instruction */ |
| 368 | bool first_instruction; |
Alyssa Rosenzweig | dd96b45 | 2020-05-05 14:30:06 -0400 | [diff] [blame] | 369 | } bi_registers; |
Alyssa Rosenzweig | 79f30d8 | 2020-05-05 14:23:41 -0400 | [diff] [blame] | 370 | |
Alyssa Rosenzweig | 59f8f20 | 2020-05-05 14:17:58 -0400 | [diff] [blame] | 371 | /* A bi_bundle contains two paired instruction pointers. If a slot is unfilled, |
Alyssa Rosenzweig | b042dde | 2020-05-05 14:28:53 -0400 | [diff] [blame] | 372 | * leave it NULL; the emitter will fill in a nop. Instructions reference |
Alyssa Rosenzweig | 514da97 | 2020-09-20 15:34:38 -0400 | [diff] [blame] | 373 | * registers via slots which are assigned per bundle. |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 374 | */ |
| 375 | |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 376 | typedef struct { |
Boris Brezillon | f25850b | 2020-10-12 10:57:40 +0200 | [diff] [blame] | 377 | uint8_t fau_idx; |
Alyssa Rosenzweig | dd96b45 | 2020-05-05 14:30:06 -0400 | [diff] [blame] | 378 | bi_registers regs; |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 379 | bi_instruction *fma; |
| 380 | bi_instruction *add; |
| 381 | } bi_bundle; |
| 382 | |
Alyssa Rosenzweig | 64bedbf | 2020-05-28 13:48:46 -0400 | [diff] [blame] | 383 | struct bi_block; |
| 384 | |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 385 | typedef struct { |
| 386 | struct list_head link; |
| 387 | |
Alyssa Rosenzweig | 64bedbf | 2020-05-28 13:48:46 -0400 | [diff] [blame] | 388 | /* Link back up for branch calculations */ |
| 389 | struct bi_block *block; |
| 390 | |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 391 | /* A clause can have 8 instructions in bundled FMA/ADD sense, so there |
Alyssa Rosenzweig | c3de28b | 2020-05-05 17:29:24 -0400 | [diff] [blame] | 392 | * can be 8 bundles. */ |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 393 | |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 394 | unsigned bundle_count; |
Alyssa Rosenzweig | c3de28b | 2020-05-05 17:29:24 -0400 | [diff] [blame] | 395 | bi_bundle bundles[8]; |
Alyssa Rosenzweig | fba1d12 | 2020-03-03 08:09:18 -0500 | [diff] [blame] | 396 | |
| 397 | /* For scoreboarding -- the clause ID (this is not globally unique!) |
| 398 | * and its dependencies in terms of other clauses, computed during |
| 399 | * scheduling and used when emitting code. Dependencies expressed as a |
| 400 | * bitfield matching the hardware, except shifted by a clause (the |
| 401 | * shift back to the ISA's off-by-one encoding is worked out when |
| 402 | * emitting clauses) */ |
| 403 | unsigned scoreboard_id; |
| 404 | uint8_t dependencies; |
| 405 | |
Alyssa Rosenzweig | a227798 | 2020-10-02 15:13:29 -0400 | [diff] [blame] | 406 | /* See ISA header for description */ |
| 407 | enum bifrost_flow flow_control; |
Alyssa Rosenzweig | 4131bc3 | 2020-10-02 13:46:35 -0400 | [diff] [blame] | 408 | |
| 409 | /* Can we prefetch the next clause? Usually it makes sense, except for |
| 410 | * clauses ending in unconditional branches */ |
| 411 | bool next_clause_prefetch; |
Alyssa Rosenzweig | fba1d12 | 2020-03-03 08:09:18 -0500 | [diff] [blame] | 412 | |
Alyssa Rosenzweig | 42af9f4 | 2020-03-18 12:18:30 -0400 | [diff] [blame] | 413 | /* Assigned data register */ |
Alyssa Rosenzweig | 785344e | 2020-10-02 13:53:03 -0400 | [diff] [blame] | 414 | unsigned staging_register; |
Alyssa Rosenzweig | 42af9f4 | 2020-03-18 12:18:30 -0400 | [diff] [blame] | 415 | |
Alyssa Rosenzweig | fba1d12 | 2020-03-03 08:09:18 -0500 | [diff] [blame] | 416 | /* Corresponds to the usual bit but shifted by a clause */ |
Alyssa Rosenzweig | 785344e | 2020-10-02 13:53:03 -0400 | [diff] [blame] | 417 | bool staging_barrier; |
Alyssa Rosenzweig | d3370bd | 2020-03-03 13:01:41 -0500 | [diff] [blame] | 418 | |
Alyssa Rosenzweig | a658a4f | 2020-05-05 16:15:16 -0400 | [diff] [blame] | 419 | /* Constants read by this clause. ISA limit. Must satisfy: |
| 420 | * |
| 421 | * constant_count + bundle_count <= 13 |
| 422 | * |
| 423 | * Also implicitly constant_count <= bundle_count since a bundle only |
| 424 | * reads a single constant. |
| 425 | */ |
Alyssa Rosenzweig | d3370bd | 2020-03-03 13:01:41 -0500 | [diff] [blame] | 426 | uint64_t constants[8]; |
| 427 | unsigned constant_count; |
Alyssa Rosenzweig | 42af9f4 | 2020-03-18 12:18:30 -0400 | [diff] [blame] | 428 | |
Alyssa Rosenzweig | 627872e | 2020-05-28 12:53:22 -0400 | [diff] [blame] | 429 | /* Branches encode a constant offset relative to the program counter |
| 430 | * with some magic flags. By convention, if there is a branch, its |
| 431 | * constant will be last. Set this flag to indicate this is required. |
| 432 | */ |
| 433 | bool branch_constant; |
| 434 | |
Alyssa Rosenzweig | 42af9f4 | 2020-03-18 12:18:30 -0400 | [diff] [blame] | 435 | /* What type of high latency instruction is here, basically */ |
Alyssa Rosenzweig | 2b9484c2 | 2020-10-02 14:02:25 -0400 | [diff] [blame] | 436 | unsigned message_type; |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 437 | } bi_clause; |
| 438 | |
| 439 | typedef struct bi_block { |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 440 | pan_block base; /* must be first */ |
Alyssa Rosenzweig | a35854c | 2020-03-02 22:00:07 -0500 | [diff] [blame] | 441 | |
| 442 | /* If true, uses clauses; if false, uses instructions */ |
| 443 | bool scheduled; |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 444 | struct list_head clauses; /* list of bi_clause */ |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 445 | } bi_block; |
| 446 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 447 | typedef struct { |
| 448 | nir_shader *nir; |
Alyssa Rosenzweig | 0d29184 | 2020-03-05 10:11:39 -0500 | [diff] [blame] | 449 | gl_shader_stage stage; |
Alyssa Rosenzweig | e7dc2a7 | 2020-03-02 20:06:34 -0500 | [diff] [blame] | 450 | struct list_head blocks; /* list of bi_block */ |
Alyssa Rosenzweig | 218785c | 2020-03-10 16:20:18 -0400 | [diff] [blame] | 451 | struct panfrost_sysvals sysvals; |
Alyssa Rosenzweig | 0b26cb1 | 2020-03-03 14:27:05 -0500 | [diff] [blame] | 452 | uint32_t quirks; |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 453 | |
Boris Brezillon | 111cf7f | 2020-10-12 15:00:02 +0200 | [diff] [blame] | 454 | /* Is internally a blend shader? Depends on stage == FRAGMENT */ |
| 455 | bool is_blend; |
| 456 | |
| 457 | /* Blend constants */ |
| 458 | float blend_constants[4]; |
| 459 | |
Boris Brezillon | 2f3f5da | 2020-10-13 12:26:11 +0200 | [diff] [blame] | 460 | /* Blend return offsets */ |
| 461 | uint32_t blend_ret_offsets[8]; |
| 462 | |
Boris Brezillon | 111cf7f | 2020-10-12 15:00:02 +0200 | [diff] [blame] | 463 | /* Blend tile buffer conversion desc */ |
| 464 | uint64_t blend_desc; |
| 465 | |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 466 | /* During NIR->BIR */ |
Alyssa Rosenzweig | d86659c | 2020-03-06 09:43:43 -0500 | [diff] [blame] | 467 | nir_function_impl *impl; |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 468 | bi_block *current_block; |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 469 | bi_block *after_block; |
Alyssa Rosenzweig | 987aea1 | 2020-03-05 17:03:53 -0500 | [diff] [blame] | 470 | bi_block *break_block; |
| 471 | bi_block *continue_block; |
Alyssa Rosenzweig | dabb6c6 | 2020-03-06 09:26:44 -0500 | [diff] [blame] | 472 | bool emitted_atest; |
Alyssa Rosenzweig | 1a8f1a3 | 2020-04-23 19:26:01 -0400 | [diff] [blame] | 473 | nir_alu_type *blend_types; |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 474 | |
Alyssa Rosenzweig | d86659c | 2020-03-06 09:43:43 -0500 | [diff] [blame] | 475 | /* For creating temporaries */ |
| 476 | unsigned temp_alloc; |
| 477 | |
Alyssa Rosenzweig | 56e1c60 | 2020-03-11 14:54:49 -0400 | [diff] [blame] | 478 | /* Analysis results */ |
| 479 | bool has_liveness; |
| 480 | |
Alyssa Rosenzweig | 83c4562 | 2020-03-05 10:25:19 -0500 | [diff] [blame] | 481 | /* Stats for shader-db */ |
| 482 | unsigned instruction_count; |
Alyssa Rosenzweig | 987aea1 | 2020-03-05 17:03:53 -0500 | [diff] [blame] | 483 | unsigned loop_count; |
Alyssa Rosenzweig | 171bf19 | 2020-10-14 19:14:43 -0400 | [diff] [blame] | 484 | unsigned spills; |
| 485 | unsigned fills; |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 486 | } bi_context; |
| 487 | |
| 488 | static inline bi_instruction * |
| 489 | bi_emit(bi_context *ctx, bi_instruction ins) |
| 490 | { |
| 491 | bi_instruction *u = rzalloc(ctx, bi_instruction); |
| 492 | memcpy(u, &ins, sizeof(ins)); |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 493 | list_addtail(&u->link, &ctx->current_block->base.instructions); |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 494 | return u; |
| 495 | } |
| 496 | |
Alyssa Rosenzweig | 58a51c4 | 2020-03-19 17:21:34 -0400 | [diff] [blame] | 497 | static inline bi_instruction * |
| 498 | bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins) |
| 499 | { |
| 500 | bi_instruction *u = rzalloc(ctx, bi_instruction); |
| 501 | memcpy(u, &ins, sizeof(ins)); |
| 502 | list_addtail(&u->link, &tag->link); |
| 503 | return u; |
| 504 | } |
| 505 | |
Alyssa Rosenzweig | 55dab92 | 2020-03-05 16:44:49 -0500 | [diff] [blame] | 506 | static inline void |
| 507 | bi_remove_instruction(bi_instruction *ins) |
| 508 | { |
| 509 | list_del(&ins->link); |
| 510 | } |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 511 | |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 512 | /* If high bits are set, instead of SSA/registers, we have specials indexed by |
| 513 | * the low bits if necessary. |
| 514 | * |
| 515 | * Fixed register: do not allocate register, do not collect $200. |
| 516 | * Uniform: access a uniform register given by low bits. |
Alyssa Rosenzweig | 11bccb0 | 2020-03-21 18:42:58 -0400 | [diff] [blame] | 517 | * Constant: access the specified constant (specifies a bit offset / shift) |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 518 | * Zero: special cased to avoid wasting a constant |
Alyssa Rosenzweig | cd40e18 | 2020-03-18 09:57:32 -0400 | [diff] [blame] | 519 | * Passthrough: a bifrost_packed_src to passthrough T/T0/T1 |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 520 | */ |
| 521 | |
| 522 | #define BIR_INDEX_REGISTER (1 << 31) |
| 523 | #define BIR_INDEX_UNIFORM (1 << 30) |
| 524 | #define BIR_INDEX_CONSTANT (1 << 29) |
| 525 | #define BIR_INDEX_ZERO (1 << 28) |
Alyssa Rosenzweig | cd40e18 | 2020-03-18 09:57:32 -0400 | [diff] [blame] | 526 | #define BIR_INDEX_PASS (1 << 27) |
Boris Brezillon | 16179c8 | 2020-10-12 11:19:45 +0200 | [diff] [blame] | 527 | #define BIR_INDEX_BLEND (1 << 26) |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 528 | |
| 529 | /* Keep me synced please so we can check src & BIR_SPECIAL */ |
| 530 | |
Boris Brezillon | 16179c8 | 2020-10-12 11:19:45 +0200 | [diff] [blame] | 531 | #define BIR_SPECIAL (BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM | \ |
| 532 | BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | \ |
| 533 | BIR_INDEX_PASS | BIR_INDEX_BLEND) |
Alyssa Rosenzweig | a2c1265 | 2020-03-03 07:45:33 -0500 | [diff] [blame] | 534 | |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 535 | static inline unsigned |
Alyssa Rosenzweig | 0bff6e5 | 2020-03-11 14:51:57 -0400 | [diff] [blame] | 536 | bi_max_temp(bi_context *ctx) |
| 537 | { |
| 538 | unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc); |
Alyssa Rosenzweig | e8139ef | 2020-03-11 20:39:36 -0400 | [diff] [blame] | 539 | return ((alloc + 2 + ctx->temp_alloc) << 1); |
Alyssa Rosenzweig | 0bff6e5 | 2020-03-11 14:51:57 -0400 | [diff] [blame] | 540 | } |
| 541 | |
| 542 | static inline unsigned |
Alyssa Rosenzweig | d86659c | 2020-03-06 09:43:43 -0500 | [diff] [blame] | 543 | bi_make_temp(bi_context *ctx) |
| 544 | { |
| 545 | return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1; |
| 546 | } |
| 547 | |
| 548 | static inline unsigned |
| 549 | bi_make_temp_reg(bi_context *ctx) |
| 550 | { |
Alyssa Rosenzweig | fbbe3d4 | 2020-04-27 16:04:05 -0400 | [diff] [blame] | 551 | return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG; |
Alyssa Rosenzweig | 230be61 | 2020-03-02 20:24:03 -0500 | [diff] [blame] | 552 | } |
| 553 | |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 554 | /* Iterators for Bifrost IR */ |
| 555 | |
| 556 | #define bi_foreach_block(ctx, v) \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 557 | list_for_each_entry(pan_block, v, &ctx->blocks, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 558 | |
| 559 | #define bi_foreach_block_from(ctx, from, v) \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 560 | list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 561 | |
Alyssa Rosenzweig | a427315 | 2020-05-28 15:01:38 -0400 | [diff] [blame] | 562 | #define bi_foreach_block_from_rev(ctx, from, v) \ |
| 563 | list_for_each_entry_from_rev(pan_block, v, from, &ctx->blocks, link) |
| 564 | |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 565 | #define bi_foreach_instr_in_block(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 566 | list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 567 | |
| 568 | #define bi_foreach_instr_in_block_rev(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 569 | list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 570 | |
| 571 | #define bi_foreach_instr_in_block_safe(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 572 | list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 573 | |
| 574 | #define bi_foreach_instr_in_block_safe_rev(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 575 | list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 576 | |
| 577 | #define bi_foreach_instr_in_block_from(block, v, from) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 578 | list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 579 | |
| 580 | #define bi_foreach_instr_in_block_from_rev(block, v, from) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 581 | list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 582 | |
| 583 | #define bi_foreach_clause_in_block(block, v) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 584 | list_for_each_entry(bi_clause, v, &(block)->clauses, link) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 585 | |
Alyssa Rosenzweig | 64c49ab | 2020-05-28 13:49:41 -0400 | [diff] [blame] | 586 | #define bi_foreach_clause_in_block_from(block, v, from) \ |
| 587 | list_for_each_entry_from(bi_clause, v, from, &(block)->clauses, link) |
| 588 | |
| 589 | #define bi_foreach_clause_in_block_from_rev(block, v, from) \ |
| 590 | list_for_each_entry_from_rev(bi_clause, v, from, &(block)->clauses, link) |
| 591 | |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 592 | #define bi_foreach_instr_global(ctx, v) \ |
| 593 | bi_foreach_block(ctx, v_block) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 594 | bi_foreach_instr_in_block((bi_block *) v_block, v) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 595 | |
| 596 | #define bi_foreach_instr_global_safe(ctx, v) \ |
| 597 | bi_foreach_block(ctx, v_block) \ |
Alyssa Rosenzweig | c63105f | 2020-03-11 21:04:26 -0400 | [diff] [blame] | 598 | bi_foreach_instr_in_block_safe((bi_block *) v_block, v) |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 599 | |
| 600 | /* Based on set_foreach, expanded with automatic type casts */ |
| 601 | |
| 602 | #define bi_foreach_predecessor(blk, v) \ |
| 603 | struct set_entry *_entry_##v; \ |
| 604 | bi_block *v; \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 605 | for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \ |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 606 | v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \ |
| 607 | _entry_##v != NULL; \ |
Alyssa Rosenzweig | 9b75f41 | 2020-03-11 14:35:38 -0400 | [diff] [blame] | 608 | _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \ |
Alyssa Rosenzweig | 8ec6718 | 2020-03-03 14:32:28 -0500 | [diff] [blame] | 609 | v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL)) |
| 610 | |
| 611 | #define bi_foreach_src(ins, v) \ |
| 612 | for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v) |
| 613 | |
Alyssa Rosenzweig | 6e0479a | 2020-03-11 14:48:55 -0400 | [diff] [blame] | 614 | static inline bi_instruction * |
| 615 | bi_prev_op(bi_instruction *ins) |
| 616 | { |
| 617 | return list_last_entry(&(ins->link), bi_instruction, link); |
| 618 | } |
| 619 | |
| 620 | static inline bi_instruction * |
| 621 | bi_next_op(bi_instruction *ins) |
| 622 | { |
| 623 | return list_first_entry(&(ins->link), bi_instruction, link); |
| 624 | } |
| 625 | |
Alyssa Rosenzweig | 9269c85 | 2020-03-12 14:16:22 -0400 | [diff] [blame] | 626 | static inline pan_block * |
| 627 | pan_next_block(pan_block *block) |
| 628 | { |
| 629 | return list_first_entry(&(block->link), pan_block, link); |
| 630 | } |
| 631 | |
Alyssa Rosenzweig | 8e52206 | 2020-04-14 18:52:21 -0400 | [diff] [blame] | 632 | /* Special functions */ |
| 633 | |
| 634 | void bi_emit_fexp2(bi_context *ctx, nir_alu_instr *instr); |
Alyssa Rosenzweig | 031ad0e | 2020-04-14 19:50:24 -0400 | [diff] [blame] | 635 | void bi_emit_flog2(bi_context *ctx, nir_alu_instr *instr); |
Alyssa Rosenzweig | 8e52206 | 2020-04-14 18:52:21 -0400 | [diff] [blame] | 636 | |
Alyssa Rosenzweig | 5d16a81 | 2020-03-04 09:19:06 -0500 | [diff] [blame] | 637 | /* BIR manipulation */ |
| 638 | |
| 639 | bool bi_has_outmod(bi_instruction *ins); |
| 640 | bool bi_has_source_mods(bi_instruction *ins); |
| 641 | bool bi_is_src_swizzled(bi_instruction *ins, unsigned s); |
Alyssa Rosenzweig | e94754a | 2020-03-11 14:40:01 -0400 | [diff] [blame] | 642 | bool bi_has_arg(bi_instruction *ins, unsigned arg); |
Alyssa Rosenzweig | e1d9533 | 2020-03-11 21:41:57 -0400 | [diff] [blame] | 643 | uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes); |
Alyssa Rosenzweig | b2c6cf2 | 2020-04-24 17:20:28 -0400 | [diff] [blame] | 644 | unsigned bi_get_component_count(bi_instruction *ins, signed s); |
Alyssa Rosenzweig | e623007 | 2020-03-11 14:46:01 -0400 | [diff] [blame] | 645 | uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node); |
Alyssa Rosenzweig | 11bccb0 | 2020-03-21 18:42:58 -0400 | [diff] [blame] | 646 | uint64_t bi_get_immediate(bi_instruction *ins, unsigned index); |
Alyssa Rosenzweig | 375a7d0 | 2020-03-27 14:40:30 -0400 | [diff] [blame] | 647 | bool bi_writes_component(bi_instruction *ins, unsigned comp); |
Alyssa Rosenzweig | b2c6cf2 | 2020-04-24 17:20:28 -0400 | [diff] [blame] | 648 | unsigned bi_writemask(bi_instruction *ins); |
Alyssa Rosenzweig | 3089501 | 2020-10-06 12:14:32 -0400 | [diff] [blame] | 649 | void bi_rewrite_uses(bi_context *ctx, unsigned old, unsigned oldc, unsigned new, unsigned newc); |
Alyssa Rosenzweig | 5d16a81 | 2020-03-04 09:19:06 -0500 | [diff] [blame] | 650 | |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 651 | /* BIR passes */ |
| 652 | |
Alyssa Rosenzweig | e0a51d5 | 2020-03-22 17:31:23 -0400 | [diff] [blame] | 653 | void bi_lower_combine(bi_context *ctx, bi_block *block); |
Alyssa Rosenzweig | 58f9171 | 2020-03-11 15:10:32 -0400 | [diff] [blame] | 654 | bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block); |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 655 | void bi_schedule(bi_context *ctx); |
Alyssa Rosenzweig | e8139ef | 2020-03-11 20:39:36 -0400 | [diff] [blame] | 656 | void bi_register_allocate(bi_context *ctx); |
Alyssa Rosenzweig | b329f8c | 2020-03-06 19:25:00 -0500 | [diff] [blame] | 657 | |
Alyssa Rosenzweig | 2ff54ca | 2020-10-14 20:38:13 -0400 | [diff] [blame^] | 658 | bi_clause *bi_make_singleton(void *memctx, bi_instruction *ins, |
| 659 | bi_block *block, |
| 660 | unsigned scoreboard_id, |
| 661 | unsigned dependencies, |
| 662 | bool osrb); |
| 663 | |
Alyssa Rosenzweig | 56e1c60 | 2020-03-11 14:54:49 -0400 | [diff] [blame] | 664 | /* Liveness */ |
| 665 | |
| 666 | void bi_compute_liveness(bi_context *ctx); |
| 667 | void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max); |
| 668 | void bi_invalidate_liveness(bi_context *ctx); |
| 669 | bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src); |
| 670 | |
Alyssa Rosenzweig | 2a4e447 | 2020-05-05 17:58:16 -0400 | [diff] [blame] | 671 | /* Layout */ |
| 672 | |
| 673 | bool bi_can_insert_bundle(bi_clause *clause, bool constant); |
Alyssa Rosenzweig | b3ae088 | 2020-05-05 18:20:08 -0400 | [diff] [blame] | 674 | unsigned bi_clause_quadwords(bi_clause *clause); |
Alyssa Rosenzweig | 682b63c | 2020-05-28 13:49:59 -0400 | [diff] [blame] | 675 | signed bi_block_offset(bi_context *ctx, bi_clause *start, bi_block *target); |
Alyssa Rosenzweig | 2a4e447 | 2020-05-05 17:58:16 -0400 | [diff] [blame] | 676 | |
Alyssa Rosenzweig | 9269c85 | 2020-03-12 14:16:22 -0400 | [diff] [blame] | 677 | /* Code emit */ |
| 678 | |
| 679 | void bi_pack(bi_context *ctx, struct util_dynarray *emission); |
| 680 | |
Alyssa Rosenzweig | eceaea4 | 2020-03-02 19:47:11 -0500 | [diff] [blame] | 681 | #endif |