sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 4 | /*--- This file (main/vex_main.c) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2005 OpenWorks LLP. All rights reserved. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 47 | #include "libvex.h" |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 48 | #include "libvex_emwarn.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 49 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 50 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 51 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 52 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 53 | #include "libvex_guest_ppc64.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 54 | |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 55 | #include "main/vex_globals.h" |
| 56 | #include "main/vex_util.h" |
| 57 | #include "host-generic/h_generic_regs.h" |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 58 | #include "ir/iropt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 59 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 60 | #include "host-x86/hdefs.h" |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 61 | #include "host-amd64/hdefs.h" |
cerion | d0eae2d | 2005-12-23 11:43:01 +0000 | [diff] [blame] | 62 | #include "host-ppc/hdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 63 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 64 | #include "guest-generic/bb_to_IR.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 65 | #include "guest-x86/gdefs.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 66 | #include "guest-amd64/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 67 | #include "guest-arm/gdefs.h" |
cerion | d0eae2d | 2005-12-23 11:43:01 +0000 | [diff] [blame] | 68 | #include "guest-ppc/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 69 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 70 | |
| 71 | /* This file contains the top level interface to the library. */ |
| 72 | |
| 73 | /* --------- Initialise the library. --------- */ |
| 74 | |
| 75 | /* Exported to library client. */ |
| 76 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 77 | const HChar* LibVEX_Version ( void ) |
sewardj | 80f5fce | 2004-12-20 04:37:50 +0000 | [diff] [blame] | 78 | { |
| 79 | return |
| 80 | #include "main/vex_svnversion.h" |
| 81 | ; |
| 82 | } |
| 83 | |
| 84 | |
| 85 | /* Exported to library client. */ |
| 86 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 87 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 88 | { |
| 89 | vcon->iropt_verbosity = 0; |
| 90 | vcon->iropt_level = 2; |
| 91 | vcon->iropt_precise_memory_exns = False; |
| 92 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 93 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 94 | vcon->guest_chase_thresh = 10; |
| 95 | } |
| 96 | |
| 97 | |
| 98 | /* Exported to library client. */ |
| 99 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 100 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 101 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 102 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 103 | void (*failure_exit) ( void ), |
| 104 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 105 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 106 | /* debug paranoia level */ |
| 107 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 108 | /* Are we supporting valgrind checking? */ |
| 109 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 110 | /* Control ... */ |
| 111 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 112 | ) |
| 113 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 114 | /* First off, do enough minimal setup so that the following |
| 115 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 116 | vex_failure_exit = failure_exit; |
| 117 | vex_log_bytes = log_bytes; |
| 118 | |
| 119 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 120 | vassert(!vex_initdone); |
| 121 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 122 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 123 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 124 | |
| 125 | vassert(vcon->iropt_verbosity >= 0); |
| 126 | vassert(vcon->iropt_level >= 0); |
| 127 | vassert(vcon->iropt_level <= 2); |
| 128 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 129 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 130 | vassert(vcon->guest_max_insns >= 1); |
| 131 | vassert(vcon->guest_max_insns <= 100); |
| 132 | vassert(vcon->guest_chase_thresh >= 0); |
| 133 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 134 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 135 | /* Check that Vex has been built with sizes of basic types as |
| 136 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 137 | a serious configuration error and should be corrected |
| 138 | immediately. If any of these assertions fail you can fully |
| 139 | expect Vex not to work properly, if at all. */ |
| 140 | |
| 141 | vassert(1 == sizeof(UChar)); |
| 142 | vassert(1 == sizeof(Char)); |
| 143 | vassert(2 == sizeof(UShort)); |
| 144 | vassert(2 == sizeof(Short)); |
| 145 | vassert(4 == sizeof(UInt)); |
| 146 | vassert(4 == sizeof(Int)); |
| 147 | vassert(8 == sizeof(ULong)); |
| 148 | vassert(8 == sizeof(Long)); |
| 149 | vassert(4 == sizeof(Float)); |
| 150 | vassert(8 == sizeof(Double)); |
| 151 | vassert(1 == sizeof(Bool)); |
| 152 | vassert(4 == sizeof(Addr32)); |
| 153 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 154 | vassert(16 == sizeof(U128)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 155 | |
| 156 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 157 | vassert(sizeof(void*) == sizeof(int*)); |
| 158 | vassert(sizeof(void*) == sizeof(HWord)); |
| 159 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 160 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 161 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 162 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 163 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 164 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 165 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 166 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 167 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 168 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | |
| 172 | /* --------- Make a translation. --------- */ |
| 173 | |
| 174 | /* Exported to library client. */ |
| 175 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 176 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 177 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 178 | /* This the bundle of functions we need to do the back-end stuff |
| 179 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 180 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 181 | HReg* available_real_regs; |
| 182 | Int n_available_real_regs; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 183 | Bool (*isMove) ( HInstr*, HReg*, HReg* ); |
| 184 | void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); |
| 185 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
| 186 | HInstr* (*genSpill) ( HReg, Int, Bool ); |
| 187 | HInstr* (*genReload) ( HReg, Int, Bool ); |
| 188 | void (*ppInstr) ( HInstr*, Bool ); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 189 | void (*ppReg) ( HReg ); |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 190 | HInstrArray* (*iselBB) ( IRBB*, VexArchInfo* ); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 191 | Int (*emit) ( UChar*, Int, HInstr*, Bool, void* ); |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 192 | IRExpr* (*specHelper) ( HChar*, IRExpr** ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 193 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 194 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 195 | DisOneInstrFn disInstrFn; |
| 196 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 197 | VexGuestLayout* guest_layout; |
| 198 | Bool host_is_bigendian = False; |
| 199 | IRBB* irbb; |
| 200 | HInstrArray* vcode; |
| 201 | HInstrArray* rcode; |
| 202 | Int i, j, k, out_used, guest_sizeB; |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 203 | Int offB_TISTART, offB_TILEN; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 204 | UChar insn_bytes[32]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 205 | IRType guest_word_type; |
| 206 | IRType host_word_type; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 207 | Bool mode64; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 208 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 209 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 210 | available_real_regs = NULL; |
| 211 | n_available_real_regs = 0; |
| 212 | isMove = NULL; |
| 213 | getRegUsage = NULL; |
| 214 | mapRegs = NULL; |
| 215 | genSpill = NULL; |
| 216 | genReload = NULL; |
| 217 | ppInstr = NULL; |
| 218 | ppReg = NULL; |
| 219 | iselBB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 220 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 221 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 222 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 223 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 224 | guest_word_type = Ity_INVALID; |
| 225 | host_word_type = Ity_INVALID; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 226 | offB_TISTART = 0; |
| 227 | offB_TILEN = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 228 | mode64 = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 229 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 230 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 231 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 232 | vassert(vex_initdone); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 233 | vexSetAllocModeTEMP_and_clear(); |
| 234 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 235 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 236 | /* First off, check that the guest and host insn sets |
| 237 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 238 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 239 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 240 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 241 | case VexArchX86: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 242 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 243 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 244 | &available_real_regs ); |
| 245 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 246 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_X86Instr; |
| 247 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; |
| 248 | genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86; |
| 249 | genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86; |
| 250 | ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 251 | ppReg = (void(*)(HReg)) ppHRegX86; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 252 | iselBB = iselBB_X86; |
sewardj | 0528bb5 | 2005-12-15 15:45:20 +0000 | [diff] [blame] | 253 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 254 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 255 | host_word_type = Ity_I32; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 256 | vassert(vta->archinfo_host.subarch == VexSubArchX86_sse0 |
| 257 | || vta->archinfo_host.subarch == VexSubArchX86_sse1 |
| 258 | || vta->archinfo_host.subarch == VexSubArchX86_sse2); |
| 259 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 260 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 261 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 262 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 263 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 264 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 265 | &available_real_regs ); |
| 266 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 267 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_AMD64Instr; |
| 268 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; |
| 269 | genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_AMD64; |
| 270 | genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_AMD64; |
| 271 | ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 272 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
| 273 | iselBB = iselBB_AMD64; |
sewardj | 0528bb5 | 2005-12-15 15:45:20 +0000 | [diff] [blame] | 274 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 275 | host_is_bigendian = False; |
| 276 | host_word_type = Ity_I64; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 277 | vassert(vta->archinfo_host.subarch == VexSubArch_NONE); |
| 278 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 279 | break; |
| 280 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 281 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 282 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 283 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 284 | &available_real_regs, mode64 ); |
| 285 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 286 | getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr; |
| 287 | mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr; |
| 288 | genSpill = (HInstr*(*)(HReg,Int,Bool)) genSpill_PPC; |
| 289 | genReload = (HInstr*(*)(HReg,Int,Bool)) genReload_PPC; |
| 290 | ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; |
| 291 | ppReg = (void(*)(HReg)) ppHRegPPC; |
| 292 | iselBB = iselBB_PPC; |
| 293 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 294 | host_is_bigendian = True; |
| 295 | host_word_type = Ity_I32; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 296 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC32_I |
| 297 | || vta->archinfo_guest.subarch == VexSubArchPPC32_FI |
| 298 | || vta->archinfo_guest.subarch == VexSubArchPPC32_VFI); |
| 299 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 300 | break; |
| 301 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 302 | case VexArchPPC64: |
| 303 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 304 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 305 | &available_real_regs, mode64 ); |
| 306 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 307 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr; |
| 308 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr; |
| 309 | genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_PPC; |
| 310 | genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_PPC; |
| 311 | ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; |
| 312 | ppReg = (void(*)(HReg)) ppHRegPPC; |
| 313 | iselBB = iselBB_PPC; |
| 314 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 315 | host_is_bigendian = True; |
| 316 | host_word_type = Ity_I64; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 317 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC64_FI |
| 318 | || vta->archinfo_guest.subarch == VexSubArchPPC64_VFI); |
| 319 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 320 | break; |
| 321 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 322 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 323 | vpanic("LibVEX_Translate: unsupported target insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 324 | } |
| 325 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 326 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 327 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 328 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 329 | case VexArchX86: |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 330 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 331 | disInstrFn = disInstr_X86; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 332 | specHelper = guest_x86_spechelper; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 333 | guest_sizeB = sizeof(VexGuestX86State); |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 334 | guest_word_type = Ity_I32; |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 335 | guest_layout = &x86guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 336 | offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); |
| 337 | offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 338 | vassert(vta->archinfo_guest.subarch == VexSubArchX86_sse0 |
| 339 | || vta->archinfo_guest.subarch == VexSubArchX86_sse1 |
| 340 | || vta->archinfo_guest.subarch == VexSubArchX86_sse2); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 341 | vassert(0 == sizeof(VexGuestX86State) % 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 342 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); |
| 343 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); |
| 344 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 345 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 346 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 347 | case VexArchAMD64: |
| 348 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 349 | disInstrFn = disInstr_AMD64; |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 350 | specHelper = guest_amd64_spechelper; |
| 351 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 352 | guest_word_type = Ity_I64; |
| 353 | guest_layout = &amd64guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 354 | offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); |
| 355 | offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 356 | vassert(vta->archinfo_guest.subarch == VexSubArch_NONE); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 357 | vassert(0 == sizeof(VexGuestAMD64State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 358 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 359 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); |
| 360 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 361 | break; |
| 362 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 363 | case VexArchARM: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 364 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 365 | disInstrFn = NULL; /* HACK */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 366 | specHelper = guest_arm_spechelper; |
| 367 | guest_sizeB = sizeof(VexGuestARMState); |
| 368 | guest_word_type = Ity_I32; |
| 369 | guest_layout = &armGuest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 370 | offB_TISTART = 0; /* hack ... arm has bitrot */ |
| 371 | offB_TILEN = 0; /* hack ... arm has bitrot */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 372 | vassert(vta->archinfo_guest.subarch == VexSubArchARM_v4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 373 | break; |
| 374 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 375 | case VexArchPPC32: |
| 376 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 377 | disInstrFn = disInstr_PPC; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 378 | specHelper = guest_ppc32_spechelper; |
| 379 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 380 | guest_word_type = Ity_I32; |
| 381 | guest_layout = &ppc32Guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 382 | offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); |
| 383 | offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 384 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC32_I |
| 385 | || vta->archinfo_guest.subarch == VexSubArchPPC32_FI |
| 386 | || vta->archinfo_guest.subarch == VexSubArchPPC32_VFI); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 387 | vassert(0 == sizeof(VexGuestPPC32State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 388 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 389 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); |
| 390 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 391 | break; |
| 392 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 393 | case VexArchPPC64: |
| 394 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 395 | disInstrFn = disInstr_PPC; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 396 | specHelper = guest_ppc64_spechelper; |
| 397 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 398 | guest_word_type = Ity_I64; |
| 399 | guest_layout = &ppc64Guest_layout; |
| 400 | offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART); |
| 401 | offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 402 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC64_FI |
| 403 | || vta->archinfo_guest.subarch == VexSubArchPPC64_VFI); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 404 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
| 405 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 406 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); |
| 407 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 408 | break; |
| 409 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 410 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 411 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 412 | } |
| 413 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 414 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 415 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 416 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 417 | we are simulating one flavour of an architecture a different |
| 418 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 419 | vassert(vta->archinfo_guest.subarch == vta->archinfo_host.subarch); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 420 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 421 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 422 | vexAllocSanityCheck(); |
| 423 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 424 | if (vex_traceflags & VEX_TRACE_FE) |
| 425 | vex_printf("\n------------------------" |
| 426 | " Front end " |
| 427 | "------------------------\n\n"); |
| 428 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 429 | irbb = bb_to_IR ( vta->guest_extents, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 430 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 431 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 432 | vta->guest_bytes, |
| 433 | vta->guest_bytes_addr, |
| 434 | vta->chase_into_ok, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 435 | host_is_bigendian, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 436 | &vta->archinfo_guest, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 437 | guest_word_type, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 438 | vta->do_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 439 | vta->preamble_function, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 440 | offB_TISTART, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 441 | offB_TILEN ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 442 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 443 | vexAllocSanityCheck(); |
| 444 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 445 | if (irbb == NULL) { |
| 446 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 447 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 448 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 449 | return VexTransAccessFail; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 450 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 451 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 452 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 453 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 454 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 455 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 456 | } |
| 457 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 458 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 459 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 460 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 461 | vex_printf("can't show code due to extents > 1\n"); |
| 462 | } else { |
| 463 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 464 | UChar* p = (UChar*)vta->guest_bytes; |
| 465 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
| 466 | vex_printf(". 0 %llx %u\n.", vta->guest_bytes_addr, guest_bytes_read ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 467 | for (i = 0; i < guest_bytes_read; i++) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 468 | vex_printf(" %02x", (Int)p[i] ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 469 | vex_printf("\n\n"); |
| 470 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | /* Sanity check the initial IR. */ |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 474 | sanityCheckIRBB( irbb, "initial IR", |
| 475 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 476 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 477 | vexAllocSanityCheck(); |
| 478 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 479 | /* Clean it up, hopefully a lot. */ |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 480 | irbb = do_iropt_BB ( irbb, specHelper, preciseMemExnsFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 481 | vta->guest_bytes_addr ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 482 | sanityCheckIRBB( irbb, "after initial iropt", |
| 483 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 484 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 485 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 486 | vex_printf("\n------------------------" |
| 487 | " After pre-instr IR optimisation " |
| 488 | "------------------------\n\n"); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 489 | ppIRBB ( irbb ); |
| 490 | vex_printf("\n"); |
| 491 | } |
| 492 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 493 | vexAllocSanityCheck(); |
| 494 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 495 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 496 | if (vta->instrument1) |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 497 | irbb = vta->instrument1(vta->callback_opaque, |
| 498 | irbb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 499 | vta->guest_extents, |
| 500 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 501 | vexAllocSanityCheck(); |
| 502 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 503 | if (vta->instrument2) |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 504 | irbb = vta->instrument2(vta->callback_opaque, |
| 505 | irbb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 506 | vta->guest_extents, |
| 507 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 508 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 509 | if (vex_traceflags & VEX_TRACE_INST) { |
| 510 | vex_printf("\n------------------------" |
| 511 | " After instrumentation " |
| 512 | "------------------------\n\n"); |
| 513 | ppIRBB ( irbb ); |
| 514 | vex_printf("\n"); |
| 515 | } |
| 516 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 517 | if (vta->instrument1 || vta->instrument2) |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 518 | sanityCheckIRBB( irbb, "after instrumentation", |
| 519 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 520 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 521 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 522 | if (vta->instrument1 || vta->instrument2) { |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 523 | do_deadcode_BB( irbb ); |
| 524 | irbb = cprop_BB( irbb ); |
| 525 | do_deadcode_BB( irbb ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 526 | sanityCheckIRBB( irbb, "after post-instrumentation cleanup", |
| 527 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 528 | } |
| 529 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 530 | vexAllocSanityCheck(); |
| 531 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 532 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 533 | vex_printf("\n------------------------" |
| 534 | " After post-instr IR optimisation " |
| 535 | "------------------------\n\n"); |
| 536 | ppIRBB ( irbb ); |
| 537 | vex_printf("\n"); |
| 538 | } |
| 539 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 540 | /* Turn it into virtual-registerised code. Build trees -- this |
| 541 | also throws away any dead bindings. */ |
| 542 | ado_treebuild_BB( irbb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 543 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 544 | vexAllocSanityCheck(); |
| 545 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 546 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 547 | vex_printf("\n------------------------" |
| 548 | " After tree-building " |
| 549 | "------------------------\n\n"); |
| 550 | ppIRBB ( irbb ); |
| 551 | vex_printf("\n"); |
| 552 | } |
| 553 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 554 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 555 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 556 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 557 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 558 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 559 | vex_printf("\n------------------------" |
| 560 | " Instruction selection " |
| 561 | "------------------------\n"); |
| 562 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 563 | vcode = iselBB ( irbb, &vta->archinfo_host ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 564 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 565 | vexAllocSanityCheck(); |
| 566 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 567 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 568 | vex_printf("\n"); |
| 569 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 570 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 571 | for (i = 0; i < vcode->arr_used; i++) { |
| 572 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 573 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 574 | vex_printf("\n"); |
| 575 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 576 | vex_printf("\n"); |
| 577 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 578 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 579 | /* Register allocate. */ |
| 580 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 581 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 582 | isMove, getRegUsage, mapRegs, |
| 583 | genSpill, genReload, guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 584 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 585 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 586 | vexAllocSanityCheck(); |
| 587 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 588 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 589 | vex_printf("\n------------------------" |
| 590 | " Register-allocated code " |
| 591 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 592 | for (i = 0; i < rcode->arr_used; i++) { |
| 593 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 594 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 595 | vex_printf("\n"); |
| 596 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 597 | vex_printf("\n"); |
| 598 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 599 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 600 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 601 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 602 | /* end HACK */ |
| 603 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 604 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 605 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 606 | vex_printf("\n------------------------" |
| 607 | " Assembly " |
| 608 | "------------------------\n\n"); |
| 609 | } |
| 610 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 611 | out_used = 0; /* tracks along the host_bytes array */ |
| 612 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 613 | if (vex_traceflags & VEX_TRACE_ASM) { |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 614 | ppInstr(rcode->arr[i], mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 615 | vex_printf("\n"); |
| 616 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 617 | j = (*emit)( insn_bytes, 32, rcode->arr[i], mode64, vta->dispatch ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 618 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 619 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 620 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 621 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 622 | else |
| 623 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 624 | vex_printf("\n\n"); |
| 625 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 626 | if (out_used + j > vta->host_bytes_size) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 627 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 628 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 629 | return VexTransOutputFull; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 630 | } |
| 631 | for (k = 0; k < j; k++) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 632 | vta->host_bytes[out_used] = insn_bytes[k]; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 633 | out_used++; |
| 634 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 635 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 636 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 637 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 638 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 639 | vexAllocSanityCheck(); |
| 640 | |
| 641 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 642 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 643 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 644 | return VexTransOK; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 648 | /* --------- Emulation warnings. --------- */ |
| 649 | |
| 650 | HChar* LibVEX_EmWarn_string ( VexEmWarn ew ) |
| 651 | { |
| 652 | switch (ew) { |
| 653 | case EmWarn_NONE: |
| 654 | return "none"; |
| 655 | case EmWarn_X86_x87exns: |
| 656 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 657 | case EmWarn_X86_x87precision: |
| 658 | return "Selection of non-80-bit x87 FP precision"; |
| 659 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 660 | return "Unmasking SSE FP exceptions"; |
| 661 | case EmWarn_X86_fz: |
| 662 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 663 | case EmWarn_X86_daz: |
| 664 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 665 | case EmWarn_X86_acFlag: |
| 666 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame^] | 667 | case EmWarn_PPCexns: |
| 668 | return "Unmasking PPC32/64 FP exceptions"; |
| 669 | case EmWarn_PPC64_redir_overflow: |
| 670 | return "PPC64 function redirection stack overflow"; |
| 671 | case EmWarn_PPC64_redir_underflow: |
| 672 | return "PPC64 function redirection stack underflow"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 673 | default: |
| 674 | vpanic("LibVEX_EmWarn_string: unknown warning"); |
| 675 | } |
| 676 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 677 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 678 | /* --------- Arch/Subarch stuff. --------- */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 679 | |
| 680 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 681 | { |
| 682 | switch (arch) { |
| 683 | case VexArch_INVALID: return "INVALID"; |
| 684 | case VexArchX86: return "X86"; |
| 685 | case VexArchAMD64: return "AMD64"; |
| 686 | case VexArchARM: return "ARM"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 687 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 688 | case VexArchPPC64: return "PPC64"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 689 | default: return "VexArch???"; |
| 690 | } |
| 691 | } |
| 692 | |
| 693 | const HChar* LibVEX_ppVexSubArch ( VexSubArch subarch ) |
| 694 | { |
| 695 | switch (subarch) { |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 696 | case VexSubArch_INVALID: return "INVALID"; |
| 697 | case VexSubArch_NONE: return "NONE"; |
| 698 | case VexSubArchX86_sse0: return "x86-sse0"; |
| 699 | case VexSubArchX86_sse1: return "x86-sse1"; |
| 700 | case VexSubArchX86_sse2: return "x86-sse2"; |
| 701 | case VexSubArchARM_v4: return "arm-v4"; |
sewardj | 059601a | 2005-11-13 00:53:05 +0000 | [diff] [blame] | 702 | case VexSubArchPPC32_I: return "ppc32-int-only"; |
| 703 | case VexSubArchPPC32_FI: return "ppc32-int-and-fp"; |
| 704 | case VexSubArchPPC32_VFI: return "ppc32-int-fp-and-AV"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 705 | case VexSubArchPPC64_FI: return "ppc64-int-and-fp"; |
| 706 | case VexSubArchPPC64_VFI: return "ppc64-int-fp-and-AV"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 707 | default: return "VexSubArch???"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 708 | } |
| 709 | } |
| 710 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 711 | /* Write default settings info *vai. */ |
| 712 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 713 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 714 | vai->subarch = VexSubArch_INVALID; |
| 715 | vai->ppc_cache_line_szB = 0; |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 716 | } |
| 717 | |
| 718 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 719 | /*---------------------------------------------------------------*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 720 | /*--- end main/vex_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 721 | /*---------------------------------------------------------------*/ |