sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 4 | /*--- This file (main/vex_main.c) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2005 OpenWorks LLP. All rights reserved. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 47 | #include "libvex.h" |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 48 | #include "libvex_emwarn.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 49 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 50 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 51 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 52 | #include "libvex_guest_ppc32.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 53 | |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 54 | #include "main/vex_globals.h" |
| 55 | #include "main/vex_util.h" |
| 56 | #include "host-generic/h_generic_regs.h" |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 57 | #include "ir/iropt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 58 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 59 | #include "host-x86/hdefs.h" |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 60 | #include "host-amd64/hdefs.h" |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 61 | #include "host-ppc32/hdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 62 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 63 | #include "guest-generic/bb_to_IR.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 64 | #include "guest-x86/gdefs.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 65 | #include "guest-amd64/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 66 | #include "guest-arm/gdefs.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 67 | #include "guest-ppc32/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 68 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 69 | |
| 70 | /* This file contains the top level interface to the library. */ |
| 71 | |
| 72 | /* --------- Initialise the library. --------- */ |
| 73 | |
| 74 | /* Exported to library client. */ |
| 75 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 76 | const HChar* LibVEX_Version ( void ) |
sewardj | 80f5fce | 2004-12-20 04:37:50 +0000 | [diff] [blame] | 77 | { |
| 78 | return |
| 79 | #include "main/vex_svnversion.h" |
| 80 | ; |
| 81 | } |
| 82 | |
| 83 | |
| 84 | /* Exported to library client. */ |
| 85 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 86 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 87 | { |
| 88 | vcon->iropt_verbosity = 0; |
| 89 | vcon->iropt_level = 2; |
| 90 | vcon->iropt_precise_memory_exns = False; |
| 91 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 92 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 93 | vcon->guest_chase_thresh = 10; |
| 94 | } |
| 95 | |
| 96 | |
| 97 | /* Exported to library client. */ |
| 98 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 99 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 100 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 101 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 102 | void (*failure_exit) ( void ), |
| 103 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 104 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 105 | /* debug paranoia level */ |
| 106 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 107 | /* Are we supporting valgrind checking? */ |
| 108 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 109 | /* Control ... */ |
| 110 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 111 | ) |
| 112 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 113 | /* First off, do enough minimal setup so that the following |
| 114 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 115 | vex_failure_exit = failure_exit; |
| 116 | vex_log_bytes = log_bytes; |
| 117 | |
| 118 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 119 | vassert(!vex_initdone); |
| 120 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 121 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 122 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 123 | |
| 124 | vassert(vcon->iropt_verbosity >= 0); |
| 125 | vassert(vcon->iropt_level >= 0); |
| 126 | vassert(vcon->iropt_level <= 2); |
| 127 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 128 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 129 | vassert(vcon->guest_max_insns >= 1); |
| 130 | vassert(vcon->guest_max_insns <= 100); |
| 131 | vassert(vcon->guest_chase_thresh >= 0); |
| 132 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 133 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 134 | /* Check that Vex has been built with sizes of basic types as |
| 135 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 136 | a serious configuration error and should be corrected |
| 137 | immediately. If any of these assertions fail you can fully |
| 138 | expect Vex not to work properly, if at all. */ |
| 139 | |
| 140 | vassert(1 == sizeof(UChar)); |
| 141 | vassert(1 == sizeof(Char)); |
| 142 | vassert(2 == sizeof(UShort)); |
| 143 | vassert(2 == sizeof(Short)); |
| 144 | vassert(4 == sizeof(UInt)); |
| 145 | vassert(4 == sizeof(Int)); |
| 146 | vassert(8 == sizeof(ULong)); |
| 147 | vassert(8 == sizeof(Long)); |
| 148 | vassert(4 == sizeof(Float)); |
| 149 | vassert(8 == sizeof(Double)); |
| 150 | vassert(1 == sizeof(Bool)); |
| 151 | vassert(4 == sizeof(Addr32)); |
| 152 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 153 | vassert(16 == sizeof(U128)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 154 | |
| 155 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 156 | vassert(sizeof(void*) == sizeof(int*)); |
| 157 | vassert(sizeof(void*) == sizeof(HWord)); |
| 158 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 159 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 160 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 161 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 162 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 163 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 164 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 165 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 166 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 167 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | |
| 171 | /* --------- Make a translation. --------- */ |
| 172 | |
| 173 | /* Exported to library client. */ |
| 174 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 175 | VexTranslateResult LibVEX_Translate ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 176 | /* The instruction sets we are translating from and to. */ |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 177 | VexArch arch_guest, |
| 178 | VexArchInfo* archinfo_guest, |
| 179 | VexArch arch_host, |
| 180 | VexArchInfo* archinfo_host, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 181 | /* IN: the block to translate, and its guest address. */ |
sewardj | f461149 | 2005-10-18 12:01:48 +0000 | [diff] [blame^] | 182 | /* where are the actual bytes in the host's address space? */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 183 | UChar* guest_bytes, |
sewardj | f461149 | 2005-10-18 12:01:48 +0000 | [diff] [blame^] | 184 | /* where do the bytes came from in the guest's aspace? */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 185 | Addr64 guest_bytes_addr, |
sewardj | f461149 | 2005-10-18 12:01:48 +0000 | [diff] [blame^] | 186 | /* what guest entry point address do they correspond to? */ |
| 187 | Addr64 guest_bytes_addr_noredir, |
| 188 | /* Is it OK to chase into this guest address? */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 189 | Bool (*chase_into_ok) ( Addr64 ), |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 190 | /* OUT: which bits of guest code actually got translated */ |
| 191 | VexGuestExtents* guest_extents, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 192 | /* IN: a place to put the resulting code, and its size */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 193 | UChar* host_bytes, |
| 194 | Int host_bytes_size, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 195 | /* OUT: how much of the output area is used. */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 196 | Int* host_bytes_used, |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 197 | /* IN: optionally, two instrumentation functions. */ |
sewardj | 918c8f3 | 2005-03-21 00:54:33 +0000 | [diff] [blame] | 198 | IRBB* (*instrument1) ( IRBB*, VexGuestLayout*, |
sewardj | f461149 | 2005-10-18 12:01:48 +0000 | [diff] [blame^] | 199 | Addr64, VexGuestExtents*, |
sewardj | 918c8f3 | 2005-03-21 00:54:33 +0000 | [diff] [blame] | 200 | IRType gWordTy, IRType hWordTy ), |
| 201 | IRBB* (*instrument2) ( IRBB*, VexGuestLayout*, |
sewardj | f461149 | 2005-10-18 12:01:48 +0000 | [diff] [blame^] | 202 | Addr64, VexGuestExtents*, |
sewardj | 918c8f3 | 2005-03-21 00:54:33 +0000 | [diff] [blame] | 203 | IRType gWordTy, IRType hWordTy ), |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 204 | Bool cleanup_after_instrumentation, |
sewardj | ec3c885 | 2005-07-07 09:56:24 +0000 | [diff] [blame] | 205 | /* IN: should this translation be self-checking? */ |
| 206 | Bool do_self_check, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 207 | /* IN: optionally, an access check function for guest code. */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 208 | Bool (*byte_accessible) ( Addr64 ), |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 209 | /* IN: debug: trace vex activity at various points */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 210 | Int traceflags |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 211 | ) |
| 212 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 213 | /* This the bundle of functions we need to do the back-end stuff |
| 214 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 215 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 216 | HReg* available_real_regs; |
| 217 | Int n_available_real_regs; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 218 | Bool (*isMove) (HInstr*, HReg*, HReg*); |
| 219 | void (*getRegUsage) (HRegUsage*, HInstr*); |
| 220 | void (*mapRegs) (HRegRemap*, HInstr*); |
| 221 | HInstr* (*genSpill) ( HReg, Int ); |
| 222 | HInstr* (*genReload) ( HReg, Int ); |
| 223 | void (*ppInstr) ( HInstr* ); |
| 224 | void (*ppReg) ( HReg ); |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 225 | HInstrArray* (*iselBB) ( IRBB*, VexArchInfo* ); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 226 | Int (*emit) ( UChar*, Int, HInstr* ); |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 227 | IRExpr* (*specHelper) ( HChar*, IRExpr** ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 228 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 229 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 230 | DisOneInstrFn disInstrFn; |
| 231 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 232 | VexGuestLayout* guest_layout; |
| 233 | Bool host_is_bigendian = False; |
| 234 | IRBB* irbb; |
| 235 | HInstrArray* vcode; |
| 236 | HInstrArray* rcode; |
| 237 | Int i, j, k, out_used, guest_sizeB; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 238 | Int offB_TISTART, offB_TILEN; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 239 | UChar insn_bytes[32]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 240 | IRType guest_word_type; |
| 241 | IRType host_word_type; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 242 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 243 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 244 | available_real_regs = NULL; |
| 245 | n_available_real_regs = 0; |
| 246 | isMove = NULL; |
| 247 | getRegUsage = NULL; |
| 248 | mapRegs = NULL; |
| 249 | genSpill = NULL; |
| 250 | genReload = NULL; |
| 251 | ppInstr = NULL; |
| 252 | ppReg = NULL; |
| 253 | iselBB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 254 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 255 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 256 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 257 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 258 | guest_word_type = Ity_INVALID; |
| 259 | host_word_type = Ity_INVALID; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 260 | offB_TISTART = 0; |
| 261 | offB_TILEN = 0; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 262 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 263 | vex_traceflags = traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 264 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 265 | vassert(vex_initdone); |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 266 | vexClearTEMP(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 267 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 268 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 269 | /* First off, check that the guest and host insn sets |
| 270 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 271 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 272 | switch (arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 273 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 274 | case VexArchX86: |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 275 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 276 | &available_real_regs ); |
| 277 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
| 278 | getRegUsage = (void(*)(HRegUsage*,HInstr*)) getRegUsage_X86Instr; |
| 279 | mapRegs = (void(*)(HRegRemap*,HInstr*)) mapRegs_X86Instr; |
| 280 | genSpill = (HInstr*(*)(HReg,Int)) genSpill_X86; |
| 281 | genReload = (HInstr*(*)(HReg,Int)) genReload_X86; |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 282 | ppInstr = (void(*)(HInstr*)) ppX86Instr; |
| 283 | ppReg = (void(*)(HReg)) ppHRegX86; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 284 | iselBB = iselBB_X86; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 285 | emit = (Int(*)(UChar*,Int,HInstr*)) emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 286 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 287 | host_word_type = Ity_I32; |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 288 | vassert(archinfo_host->subarch == VexSubArchX86_sse0 |
| 289 | || archinfo_host->subarch == VexSubArchX86_sse1 |
| 290 | || archinfo_host->subarch == VexSubArchX86_sse2); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 291 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 292 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 293 | case VexArchAMD64: |
| 294 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 295 | &available_real_regs ); |
| 296 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
| 297 | getRegUsage = (void(*)(HRegUsage*,HInstr*)) getRegUsage_AMD64Instr; |
| 298 | mapRegs = (void(*)(HRegRemap*,HInstr*)) mapRegs_AMD64Instr; |
| 299 | genSpill = (HInstr*(*)(HReg,Int)) genSpill_AMD64; |
| 300 | genReload = (HInstr*(*)(HReg,Int)) genReload_AMD64; |
| 301 | ppInstr = (void(*)(HInstr*)) ppAMD64Instr; |
| 302 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
| 303 | iselBB = iselBB_AMD64; |
| 304 | emit = (Int(*)(UChar*,Int,HInstr*)) emit_AMD64Instr; |
| 305 | host_is_bigendian = False; |
| 306 | host_word_type = Ity_I64; |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 307 | vassert(archinfo_host->subarch == VexSubArch_NONE); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 308 | break; |
| 309 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 310 | case VexArchPPC32: |
| 311 | getAllocableRegs_PPC32 ( &n_available_real_regs, |
| 312 | &available_real_regs ); |
| 313 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPC32Instr; |
| 314 | getRegUsage = (void(*)(HRegUsage*,HInstr*)) getRegUsage_PPC32Instr; |
| 315 | mapRegs = (void(*)(HRegRemap*,HInstr*)) mapRegs_PPC32Instr; |
| 316 | genSpill = (HInstr*(*)(HReg,Int)) genSpill_PPC32; |
| 317 | genReload = (HInstr*(*)(HReg,Int)) genReload_PPC32; |
| 318 | ppInstr = (void(*)(HInstr*)) ppPPC32Instr; |
| 319 | ppReg = (void(*)(HReg)) ppHRegPPC32; |
| 320 | iselBB = iselBB_PPC32; |
| 321 | emit = (Int(*)(UChar*,Int,HInstr*)) emit_PPC32Instr; |
| 322 | host_is_bigendian = True; |
| 323 | host_word_type = Ity_I32; |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 324 | vassert(archinfo_guest->subarch == VexSubArchPPC32_noAV |
| 325 | || archinfo_guest->subarch == VexSubArchPPC32_AV); |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 326 | break; |
| 327 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 328 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 329 | vpanic("LibVEX_Translate: unsupported target insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 330 | } |
| 331 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 332 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 333 | switch (arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 334 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 335 | case VexArchX86: |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 336 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 337 | disInstrFn = disInstr_X86; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 338 | specHelper = guest_x86_spechelper; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 339 | guest_sizeB = sizeof(VexGuestX86State); |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 340 | guest_word_type = Ity_I32; |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 341 | guest_layout = &x86guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 342 | offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); |
| 343 | offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 344 | vassert(archinfo_guest->subarch == VexSubArchX86_sse0 |
| 345 | || archinfo_guest->subarch == VexSubArchX86_sse1 |
| 346 | || archinfo_guest->subarch == VexSubArchX86_sse2); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 347 | vassert(0 == sizeof(VexGuestX86State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 348 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART ) == 4); |
| 349 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 350 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 351 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 352 | case VexArchAMD64: |
| 353 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 354 | disInstrFn = disInstr_AMD64; |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 355 | specHelper = guest_amd64_spechelper; |
| 356 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 357 | guest_word_type = Ity_I64; |
| 358 | guest_layout = &amd64guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 359 | offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); |
| 360 | offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 361 | vassert(archinfo_guest->subarch == VexSubArch_NONE); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 362 | vassert(0 == sizeof(VexGuestAMD64State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 363 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); |
| 364 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 365 | break; |
| 366 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 367 | case VexArchARM: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 368 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 369 | disInstrFn = NULL; /* HACK */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 370 | specHelper = guest_arm_spechelper; |
| 371 | guest_sizeB = sizeof(VexGuestARMState); |
| 372 | guest_word_type = Ity_I32; |
| 373 | guest_layout = &armGuest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 374 | offB_TISTART = 0; /* hack ... arm has bitrot */ |
| 375 | offB_TILEN = 0; /* hack ... arm has bitrot */ |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 376 | vassert(archinfo_guest->subarch == VexSubArchARM_v4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 377 | break; |
| 378 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 379 | case VexArchPPC32: |
| 380 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 381 | disInstrFn = disInstr_PPC32; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 382 | specHelper = guest_ppc32_spechelper; |
| 383 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 384 | guest_word_type = Ity_I32; |
| 385 | guest_layout = &ppc32Guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 386 | offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); |
| 387 | offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 388 | vassert(archinfo_guest->subarch == VexSubArchPPC32_noAV |
| 389 | || archinfo_guest->subarch == VexSubArchPPC32_AV); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 390 | vassert(0 == sizeof(VexGuestPPC32State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 391 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); |
| 392 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 393 | break; |
| 394 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 395 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 396 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 397 | } |
| 398 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 399 | /* yet more sanity checks ... */ |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 400 | if (arch_guest == arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 401 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 402 | we are simulating one flavour of an architecture a different |
| 403 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 404 | vassert(archinfo_guest->subarch == archinfo_host->subarch); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 405 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 406 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 407 | if (vex_traceflags & VEX_TRACE_FE) |
| 408 | vex_printf("\n------------------------" |
| 409 | " Front end " |
| 410 | "------------------------\n\n"); |
| 411 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 412 | irbb = bb_to_IR ( guest_extents, |
| 413 | disInstrFn, |
| 414 | guest_bytes, |
| 415 | guest_bytes_addr, |
| 416 | chase_into_ok, |
| 417 | host_is_bigendian, |
| 418 | archinfo_guest, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 419 | guest_word_type, |
sewardj | ec3c885 | 2005-07-07 09:56:24 +0000 | [diff] [blame] | 420 | do_self_check, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 421 | offB_TISTART, |
| 422 | offB_TILEN ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 423 | |
| 424 | if (irbb == NULL) { |
| 425 | /* Access failure. */ |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 426 | vexClearTEMP(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 427 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 428 | return VexTransAccessFail; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 429 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 430 | |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 431 | vassert(guest_extents->n_used >= 1 && guest_extents->n_used <= 3); |
| 432 | vassert(guest_extents->base[0] == guest_bytes_addr); |
| 433 | for (i = 0; i < guest_extents->n_used; i++) { |
| 434 | vassert(guest_extents->len[i] < 10000); /* sanity */ |
| 435 | } |
| 436 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 437 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 438 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 439 | if (guest_extents->n_used > 1) { |
| 440 | vex_printf("can't show code due to extents > 1\n"); |
| 441 | } else { |
| 442 | /* HACK */ |
| 443 | UChar* p = (UChar*)guest_bytes; |
| 444 | UInt guest_bytes_read = (UInt)guest_extents->len[0]; |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 445 | vex_printf(". 0 %llx %u\n.", guest_bytes_addr, guest_bytes_read ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 446 | for (i = 0; i < guest_bytes_read; i++) |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 447 | vex_printf(" %02x", (Int)p[i] ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 448 | vex_printf("\n\n"); |
| 449 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | /* Sanity check the initial IR. */ |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 453 | sanityCheckIRBB( irbb, "initial IR", |
| 454 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 455 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 456 | /* Clean it up, hopefully a lot. */ |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 457 | irbb = do_iropt_BB ( irbb, specHelper, preciseMemExnsFn, |
| 458 | guest_bytes_addr ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 459 | sanityCheckIRBB( irbb, "after initial iropt", |
| 460 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 461 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 462 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 463 | vex_printf("\n------------------------" |
| 464 | " After pre-instr IR optimisation " |
| 465 | "------------------------\n\n"); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 466 | ppIRBB ( irbb ); |
| 467 | vex_printf("\n"); |
| 468 | } |
| 469 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 470 | /* Get the thing instrumented. */ |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 471 | if (instrument1) |
sewardj | 918c8f3 | 2005-03-21 00:54:33 +0000 | [diff] [blame] | 472 | irbb = (*instrument1)(irbb, guest_layout, |
sewardj | f461149 | 2005-10-18 12:01:48 +0000 | [diff] [blame^] | 473 | guest_bytes_addr_noredir, guest_extents, |
| 474 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 475 | if (instrument2) |
sewardj | 918c8f3 | 2005-03-21 00:54:33 +0000 | [diff] [blame] | 476 | irbb = (*instrument2)(irbb, guest_layout, |
sewardj | f461149 | 2005-10-18 12:01:48 +0000 | [diff] [blame^] | 477 | guest_bytes_addr_noredir, guest_extents, |
| 478 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 479 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 480 | if (vex_traceflags & VEX_TRACE_INST) { |
| 481 | vex_printf("\n------------------------" |
| 482 | " After instrumentation " |
| 483 | "------------------------\n\n"); |
| 484 | ppIRBB ( irbb ); |
| 485 | vex_printf("\n"); |
| 486 | } |
| 487 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 488 | if (instrument1 || instrument2) |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 489 | sanityCheckIRBB( irbb, "after instrumentation", |
| 490 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 491 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 492 | /* Do a post-instrumentation cleanup pass. */ |
| 493 | if (cleanup_after_instrumentation) { |
| 494 | do_deadcode_BB( irbb ); |
| 495 | irbb = cprop_BB( irbb ); |
| 496 | do_deadcode_BB( irbb ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 497 | sanityCheckIRBB( irbb, "after post-instrumentation cleanup", |
| 498 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 502 | vex_printf("\n------------------------" |
| 503 | " After post-instr IR optimisation " |
| 504 | "------------------------\n\n"); |
| 505 | ppIRBB ( irbb ); |
| 506 | vex_printf("\n"); |
| 507 | } |
| 508 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 509 | /* Turn it into virtual-registerised code. */ |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 510 | do_deadcode_BB( irbb ); |
| 511 | do_treebuild_BB( irbb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 512 | |
| 513 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 514 | vex_printf("\n------------------------" |
| 515 | " After tree-building " |
| 516 | "------------------------\n\n"); |
| 517 | ppIRBB ( irbb ); |
| 518 | vex_printf("\n"); |
| 519 | } |
| 520 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 521 | /* HACK */ |
cerion | 5456081 | 2005-02-03 13:40:49 +0000 | [diff] [blame] | 522 | if (0) { *host_bytes_used = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 523 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 524 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 525 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 526 | vex_printf("\n------------------------" |
| 527 | " Instruction selection " |
| 528 | "------------------------\n"); |
| 529 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 530 | vcode = iselBB ( irbb, archinfo_host ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 531 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 532 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 533 | vex_printf("\n"); |
| 534 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 535 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 536 | for (i = 0; i < vcode->arr_used; i++) { |
| 537 | vex_printf("%3d ", i); |
| 538 | ppInstr(vcode->arr[i]); |
| 539 | vex_printf("\n"); |
| 540 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 541 | vex_printf("\n"); |
| 542 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 543 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 544 | /* Register allocate. */ |
| 545 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 546 | n_available_real_regs, |
| 547 | isMove, getRegUsage, mapRegs, |
| 548 | genSpill, genReload, guest_sizeB, |
| 549 | ppInstr, ppReg ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 550 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 551 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 552 | vex_printf("\n------------------------" |
| 553 | " Register-allocated code " |
| 554 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 555 | for (i = 0; i < rcode->arr_used; i++) { |
| 556 | vex_printf("%3d ", i); |
| 557 | ppInstr(rcode->arr[i]); |
| 558 | vex_printf("\n"); |
| 559 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 560 | vex_printf("\n"); |
| 561 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 562 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 563 | /* HACK */ |
| 564 | if (0) { *host_bytes_used = 0; return VexTransOK; } |
| 565 | /* end HACK */ |
| 566 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 567 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 568 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 569 | vex_printf("\n------------------------" |
| 570 | " Assembly " |
| 571 | "------------------------\n\n"); |
| 572 | } |
| 573 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 574 | out_used = 0; /* tracks along the host_bytes array */ |
| 575 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 576 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 577 | ppInstr(rcode->arr[i]); |
| 578 | vex_printf("\n"); |
| 579 | } |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 580 | j = (*emit)( insn_bytes, 32, rcode->arr[i] ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 581 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 582 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 583 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 584 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 585 | else |
| 586 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 587 | vex_printf("\n\n"); |
| 588 | } |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 589 | if (out_used + j > host_bytes_size) { |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 590 | vexClearTEMP(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 591 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 592 | return VexTransOutputFull; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 593 | } |
| 594 | for (k = 0; k < j; k++) { |
| 595 | host_bytes[out_used] = insn_bytes[k]; |
| 596 | out_used++; |
| 597 | } |
| 598 | vassert(out_used <= host_bytes_size); |
| 599 | } |
| 600 | *host_bytes_used = out_used; |
| 601 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 602 | vexClearTEMP(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 603 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 604 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 605 | return VexTransOK; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 609 | /* --------- Emulation warnings. --------- */ |
| 610 | |
| 611 | HChar* LibVEX_EmWarn_string ( VexEmWarn ew ) |
| 612 | { |
| 613 | switch (ew) { |
| 614 | case EmWarn_NONE: |
| 615 | return "none"; |
| 616 | case EmWarn_X86_x87exns: |
| 617 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 618 | case EmWarn_X86_x87precision: |
| 619 | return "Selection of non-80-bit x87 FP precision"; |
| 620 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 621 | return "Unmasking SSE FP exceptions"; |
| 622 | case EmWarn_X86_fz: |
| 623 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 624 | case EmWarn_X86_daz: |
| 625 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 626 | case EmWarn_X86_acFlag: |
| 627 | return "Setting %eflags.ac (setting noted but ignored)"; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 628 | case EmWarn_PPC32exns: |
| 629 | return "Unmasking PPC32 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 630 | default: |
| 631 | vpanic("LibVEX_EmWarn_string: unknown warning"); |
| 632 | } |
| 633 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 634 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 635 | /* --------- Arch/Subarch stuff. --------- */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 636 | |
| 637 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 638 | { |
| 639 | switch (arch) { |
| 640 | case VexArch_INVALID: return "INVALID"; |
| 641 | case VexArchX86: return "X86"; |
| 642 | case VexArchAMD64: return "AMD64"; |
| 643 | case VexArchARM: return "ARM"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 644 | case VexArchPPC32: return "PPC32"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 645 | default: return "VexArch???"; |
| 646 | } |
| 647 | } |
| 648 | |
| 649 | const HChar* LibVEX_ppVexSubArch ( VexSubArch subarch ) |
| 650 | { |
| 651 | switch (subarch) { |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 652 | case VexSubArch_INVALID: return "INVALID"; |
| 653 | case VexSubArch_NONE: return "NONE"; |
| 654 | case VexSubArchX86_sse0: return "x86-sse0"; |
| 655 | case VexSubArchX86_sse1: return "x86-sse1"; |
| 656 | case VexSubArchX86_sse2: return "x86-sse2"; |
| 657 | case VexSubArchARM_v4: return "arm-v4"; |
| 658 | case VexSubArchPPC32_noAV: return "ppc32-noAltivec"; |
| 659 | case VexSubArchPPC32_AV: return "ppc32-Altivec"; |
| 660 | default: return "VexSubArch???"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 661 | } |
| 662 | } |
| 663 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 664 | /* Write default settings info *vai. */ |
| 665 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 666 | { |
| 667 | vai->subarch = VexSubArch_INVALID; |
| 668 | vai->ppc32_cache_line_szB = 0; |
| 669 | } |
| 670 | |
| 671 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 672 | /*---------------------------------------------------------------*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 673 | /*--- end main/vex_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 674 | /*---------------------------------------------------------------*/ |