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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080035
Chia-I Wu3c3edc02014-09-09 10:32:59 +080036/**
37 * Free all resources used by a writer. Note that the initial size is not
38 * reset.
39 */
40static void cmd_writer_reset(struct intel_cmd *cmd,
41 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080042{
Chia-I Wu68f319d2014-09-09 09:43:21 +080043 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080044
Chia-I Wu3c3edc02014-09-09 10:32:59 +080045 if (writer->ptr) {
46 intel_bo_unmap(writer->bo);
47 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080048 }
49
Chia-I Wu3c3edc02014-09-09 10:32:59 +080050 if (writer->bo) {
51 intel_bo_unreference(writer->bo);
52 writer->bo = NULL;
53 }
54
Chia-I Wue24c3292014-08-21 14:05:23 +080055 writer->used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080056}
57
58/**
59 * Discard everything written so far.
60 */
61static void cmd_writer_discard(struct intel_cmd *cmd,
62 enum intel_cmd_writer_type which)
63{
64 struct intel_cmd_writer *writer = &cmd->writers[which];
65
66 intel_bo_truncate_relocs(writer->bo, 0);
67 writer->used = 0;
68}
69
70static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
71 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +080072 XGL_SIZE size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +080073{
74 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
75 [INTEL_CMD_WRITER_BATCH] = "batch",
76 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
77 };
78
Chia-I Wu72292b72014-09-09 10:48:33 +080079 return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true);
Chia-I Wu3c3edc02014-09-09 10:32:59 +080080}
81
82/**
83 * Allocate and map the buffer for writing.
84 */
85static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
86 enum intel_cmd_writer_type which)
87{
88 struct intel_cmd_writer *writer = &cmd->writers[which];
89 struct intel_bo *bo;
90
91 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
92 if (bo) {
93 if (writer->bo)
94 intel_bo_unreference(writer->bo);
95 writer->bo = bo;
96 } else if (writer->bo) {
97 /* reuse the old bo */
98 cmd_writer_discard(cmd, which);
99 } else {
100 return XGL_ERROR_OUT_OF_GPU_MEMORY;
101 }
102
103 writer->used = 0;
104
105 writer->ptr = intel_bo_map(writer->bo, true);
106 if (!writer->ptr)
107 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800108
109 return XGL_SUCCESS;
110}
111
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800112/**
113 * Unmap the buffer for submission.
114 */
115static void cmd_writer_unmap(struct intel_cmd *cmd,
116 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800117{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800118 struct intel_cmd_writer *writer = &cmd->writers[which];
119
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800120 intel_bo_unmap(writer->bo);
121 writer->ptr = NULL;
122}
123
124/**
125 * Grow a mapped writer to at least \p new_size. Failures are handled
126 * silently.
127 */
128void cmd_writer_grow(struct intel_cmd *cmd,
129 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +0800130 XGL_SIZE new_size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800131{
132 struct intel_cmd_writer *writer = &cmd->writers[which];
133 struct intel_bo *new_bo;
134 void *new_ptr;
135
136 if (new_size < writer->size << 1)
137 new_size = writer->size << 1;
138 /* STATE_BASE_ADDRESS requires page-aligned buffers */
Chia-I Wu72292b72014-09-09 10:48:33 +0800139 new_size = u_align(new_size, 4096);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800140
141 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
142 if (!new_bo) {
143 cmd_writer_discard(cmd, which);
144 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
145 return;
146 }
147
148 /* map and copy the data over */
149 new_ptr = intel_bo_map(new_bo, true);
150 if (!new_ptr) {
151 intel_bo_unreference(new_bo);
152 cmd_writer_discard(cmd, which);
153 cmd->result = XGL_ERROR_UNKNOWN;
154 return;
155 }
156
Chia-I Wu72292b72014-09-09 10:48:33 +0800157 memcpy(new_ptr, writer->ptr, writer->used);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800158
159 intel_bo_unmap(writer->bo);
160 intel_bo_unreference(writer->bo);
161
162 writer->size = new_size;
163 writer->bo = new_bo;
164 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800165}
166
167static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800168 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +0800169 XGL_SIZE offset, uint32_t val)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800170{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800171 struct intel_cmd_writer *writer = &cmd->writers[which];
172
Chia-I Wu72292b72014-09-09 10:48:33 +0800173 assert(offset + sizeof(val) <= writer->used);
174 *((uint32_t *) ((char *) writer->ptr + offset)) = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800175}
176
Chia-I Wu730e5362014-08-19 12:15:09 +0800177static void cmd_reset(struct intel_cmd *cmd)
178{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800179 XGL_UINT i;
180
181 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
182 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800183
Chia-I Wu338fe642014-08-28 10:43:04 +0800184 if (cmd->bind.shaderCache.shaderArray)
185 icd_free(cmd->bind.shaderCache.shaderArray);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800186 memset(&cmd->bind, 0, sizeof(cmd->bind));
187
Chia-I Wu343b1372014-08-20 16:39:20 +0800188 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800189 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800190}
191
192static void cmd_destroy(struct intel_obj *obj)
193{
194 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
195
196 intel_cmd_destroy(cmd);
197}
198
199XGL_RESULT intel_cmd_create(struct intel_dev *dev,
200 const XGL_CMD_BUFFER_CREATE_INFO *info,
201 struct intel_cmd **cmd_ret)
202{
Chia-I Wu63883292014-08-25 13:50:26 +0800203 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800204 struct intel_cmd *cmd;
205
Chia-I Wu63883292014-08-25 13:50:26 +0800206 switch (info->queueType) {
207 case XGL_QUEUE_TYPE_GRAPHICS:
208 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
209 break;
210 case XGL_QUEUE_TYPE_COMPUTE:
211 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
212 break;
213 case XGL_QUEUE_TYPE_DMA:
214 pipeline_select = -1;
215 break;
216 default:
217 return XGL_ERROR_INVALID_VALUE;
218 break;
219 }
220
Chia-I Wu730e5362014-08-19 12:15:09 +0800221 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
222 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
223 if (!cmd)
224 return XGL_ERROR_OUT_OF_MEMORY;
225
226 cmd->obj.destroy = cmd_destroy;
227
228 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800229 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800230 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800231
Chia-I Wue0cdd832014-08-25 12:38:56 +0800232 /*
233 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
234 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
235 * and end offsets, for each referenced memories.
236 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800237 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
238 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
239 4096, XGL_SYSTEM_ALLOC_INTERNAL);
240 if (!cmd->relocs) {
241 intel_cmd_destroy(cmd);
242 return XGL_ERROR_OUT_OF_MEMORY;
243 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800244
245 *cmd_ret = cmd;
246
247 return XGL_SUCCESS;
248}
249
250void intel_cmd_destroy(struct intel_cmd *cmd)
251{
252 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800253
254 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800255 intel_base_destroy(&cmd->obj.base);
256}
257
258XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
259{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800260 XGL_RESULT ret;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800261 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800262
263 cmd_reset(cmd);
264
Chia-I Wu24565ee2014-08-21 20:24:31 +0800265 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800266 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800267 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800268 }
269
Chia-I Wu68f319d2014-09-09 09:43:21 +0800270 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Chia-I Wu72292b72014-09-09 10:48:33 +0800271 const XGL_UINT size = cmd->dev->gpu->max_batch_buffer_size / 2;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800272 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800273
274 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
275 divider *= 4;
276
Chia-I Wu68f319d2014-09-09 09:43:21 +0800277 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
278 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider;
Chia-I Wu72292b72014-09-09 10:48:33 +0800279 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800280 }
281
Chia-I Wu68f319d2014-09-09 09:43:21 +0800282 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800283 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800284 if (ret != XGL_SUCCESS) {
285 cmd_reset(cmd);
286 return ret;
287 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800288 }
289
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800290 cmd_batch_begin(cmd);
291
Chia-I Wu24565ee2014-08-21 20:24:31 +0800292 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800293}
294
295XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
296{
297 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800298 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800299
Chia-I Wue24c3292014-08-21 14:05:23 +0800300 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800301
Chia-I Wu343b1372014-08-20 16:39:20 +0800302 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800303 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800304 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800305 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800306 uint64_t presumed_offset;
307 int err;
308
Chia-I Wu72292b72014-09-09 10:48:33 +0800309 err = intel_bo_add_reloc(writer->bo, reloc->offset,
310 reloc->bo, reloc->bo_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800311 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800312 if (err) {
313 cmd->result = XGL_ERROR_UNKNOWN;
314 break;
315 }
316
317 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu72292b72014-09-09 10:48:33 +0800318 cmd_writer_patch(cmd, reloc->which, reloc->offset,
Chia-I Wue24c3292014-08-21 14:05:23 +0800319 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800320 }
321
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800322 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
323 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800324
Chia-I Wu04966702014-08-20 15:05:03 +0800325 if (cmd->result != XGL_SUCCESS)
326 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800327
Chia-I Wu68f319d2014-09-09 09:43:21 +0800328 if (intel_winsys_can_submit_bo(winsys,
329 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800330 return XGL_SUCCESS;
331 else
332 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
333}
334
Chia-I Wu09142132014-08-11 15:42:55 +0800335XGL_RESULT XGLAPI intelCreateCommandBuffer(
336 XGL_DEVICE device,
337 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
338 XGL_CMD_BUFFER* pCmdBuffer)
339{
Chia-I Wu730e5362014-08-19 12:15:09 +0800340 struct intel_dev *dev = intel_dev(device);
341
342 return intel_cmd_create(dev, pCreateInfo,
343 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800344}
345
346XGL_RESULT XGLAPI intelBeginCommandBuffer(
347 XGL_CMD_BUFFER cmdBuffer,
348 XGL_FLAGS flags)
349{
Chia-I Wu730e5362014-08-19 12:15:09 +0800350 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
351
352 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800353}
354
355XGL_RESULT XGLAPI intelEndCommandBuffer(
356 XGL_CMD_BUFFER cmdBuffer)
357{
Chia-I Wu730e5362014-08-19 12:15:09 +0800358 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
359
360 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800361}
362
363XGL_RESULT XGLAPI intelResetCommandBuffer(
364 XGL_CMD_BUFFER cmdBuffer)
365{
Chia-I Wu730e5362014-08-19 12:15:09 +0800366 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
367
368 cmd_reset(cmd);
369
370 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800371}
372
Chia-I Wu09142132014-08-11 15:42:55 +0800373XGL_VOID XGLAPI intelCmdCopyMemory(
374 XGL_CMD_BUFFER cmdBuffer,
375 XGL_GPU_MEMORY srcMem,
376 XGL_GPU_MEMORY destMem,
377 XGL_UINT regionCount,
378 const XGL_MEMORY_COPY* pRegions)
379{
380}
381
382XGL_VOID XGLAPI intelCmdCopyImage(
383 XGL_CMD_BUFFER cmdBuffer,
384 XGL_IMAGE srcImage,
385 XGL_IMAGE destImage,
386 XGL_UINT regionCount,
387 const XGL_IMAGE_COPY* pRegions)
388{
389}
390
391XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
392 XGL_CMD_BUFFER cmdBuffer,
393 XGL_GPU_MEMORY srcMem,
394 XGL_IMAGE destImage,
395 XGL_UINT regionCount,
396 const XGL_MEMORY_IMAGE_COPY* pRegions)
397{
398}
399
400XGL_VOID XGLAPI intelCmdCopyImageToMemory(
401 XGL_CMD_BUFFER cmdBuffer,
402 XGL_IMAGE srcImage,
403 XGL_GPU_MEMORY destMem,
404 XGL_UINT regionCount,
405 const XGL_MEMORY_IMAGE_COPY* pRegions)
406{
407}
408
409XGL_VOID XGLAPI intelCmdCloneImageData(
410 XGL_CMD_BUFFER cmdBuffer,
411 XGL_IMAGE srcImage,
412 XGL_IMAGE_STATE srcImageState,
413 XGL_IMAGE destImage,
414 XGL_IMAGE_STATE destImageState)
415{
416}
417
418XGL_VOID XGLAPI intelCmdUpdateMemory(
419 XGL_CMD_BUFFER cmdBuffer,
420 XGL_GPU_MEMORY destMem,
421 XGL_GPU_SIZE destOffset,
422 XGL_GPU_SIZE dataSize,
423 const XGL_UINT32* pData)
424{
425}
426
427XGL_VOID XGLAPI intelCmdFillMemory(
428 XGL_CMD_BUFFER cmdBuffer,
429 XGL_GPU_MEMORY destMem,
430 XGL_GPU_SIZE destOffset,
431 XGL_GPU_SIZE fillSize,
432 XGL_UINT32 data)
433{
434}
435
436XGL_VOID XGLAPI intelCmdClearColorImage(
437 XGL_CMD_BUFFER cmdBuffer,
438 XGL_IMAGE image,
439 const XGL_FLOAT color[4],
440 XGL_UINT rangeCount,
441 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
442{
443}
444
445XGL_VOID XGLAPI intelCmdClearColorImageRaw(
446 XGL_CMD_BUFFER cmdBuffer,
447 XGL_IMAGE image,
448 const XGL_UINT32 color[4],
449 XGL_UINT rangeCount,
450 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
451{
452}
453
454XGL_VOID XGLAPI intelCmdClearDepthStencil(
455 XGL_CMD_BUFFER cmdBuffer,
456 XGL_IMAGE image,
457 XGL_FLOAT depth,
458 XGL_UINT32 stencil,
459 XGL_UINT rangeCount,
460 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
461{
462}
463
464XGL_VOID XGLAPI intelCmdResolveImage(
465 XGL_CMD_BUFFER cmdBuffer,
466 XGL_IMAGE srcImage,
467 XGL_IMAGE destImage,
468 XGL_UINT rectCount,
469 const XGL_IMAGE_RESOLVE* pRects)
470{
471}
472
Chia-I Wu09142132014-08-11 15:42:55 +0800473XGL_VOID XGLAPI intelCmdMemoryAtomic(
474 XGL_CMD_BUFFER cmdBuffer,
475 XGL_GPU_MEMORY destMem,
476 XGL_GPU_SIZE destOffset,
477 XGL_UINT64 srcData,
478 XGL_ATOMIC_OP atomicOp)
479{
480}
481
Chia-I Wu09142132014-08-11 15:42:55 +0800482XGL_VOID XGLAPI intelCmdInitAtomicCounters(
483 XGL_CMD_BUFFER cmdBuffer,
484 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
485 XGL_UINT startCounter,
486 XGL_UINT counterCount,
487 const XGL_UINT32* pData)
488{
489}
490
491XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
492 XGL_CMD_BUFFER cmdBuffer,
493 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
494 XGL_UINT startCounter,
495 XGL_UINT counterCount,
496 XGL_GPU_MEMORY srcMem,
497 XGL_GPU_SIZE srcOffset)
498{
499}
500
501XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
502 XGL_CMD_BUFFER cmdBuffer,
503 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
504 XGL_UINT startCounter,
505 XGL_UINT counterCount,
506 XGL_GPU_MEMORY destMem,
507 XGL_GPU_SIZE destOffset)
508{
509}
510
511XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
512 XGL_CMD_BUFFER cmdBuffer,
513 const XGL_CHAR* pMarker)
514{
515}
516
517XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
518 XGL_CMD_BUFFER cmdBuffer)
519{
520}