blob: 5443de74057f67a6d524832ef886ab6b483f99fb [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
29#ifndef CMD_H
30#define CMD_H
31
32#include "intel.h"
33#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080034#include "view.h"
35
36struct intel_pipeline;
Chia-I Wuf2b6d722014-09-02 08:52:27 +080037struct intel_pipeline_shader;
Chia-I Wub2755562014-08-20 13:38:52 +080038struct intel_pipeline_delta;
39struct intel_viewport_state;
40struct intel_raster_state;
41struct intel_msaa_state;
42struct intel_blend_state;
43struct intel_ds_state;
44struct intel_dset;
45
Chia-I Wu958d1b72014-08-21 11:28:11 +080046struct intel_cmd_reloc;
47
Chia-I Wu8370b402014-08-29 12:28:37 +080048/*
49 * We know what workarounds are needed for intel_pipeline. These are mostly
50 * for intel_pipeline_delta.
51 */
52enum intel_cmd_wa_flags {
53 /*
54 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
55 *
56 * "Before any depth stall flush (including those produced by
57 * non-pipelined state commands), software needs to first send a
58 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
59 */
60 INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE = 1 << 0,
61
62 /*
63 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
64 *
65 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
66 * field set (DW1 Bit 1), must be issued prior to any change to the
67 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
68 *
69 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
70 *
71 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
72 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
73 * Pixel Scoreboard set is required to be issued."
74 */
75 INTEL_CMD_WA_GEN6_PRE_COMMAND_SCOREBOARD_STALL = 1 << 1,
76
77 /*
78 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
79 *
80 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
81 * stall needs to be sent just prior to any 3DSTATE_VS,
82 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
83 * 3DSTATE_BINDING_TABLE_POINTER_VS, 3DSTATE_SAMPLER_STATE_POINTER_VS
84 * command. Only one PIPE_CONTROL needs to be sent before any
85 * combination of VS associated 3DSTATE."
86 */
87 INTEL_CMD_WA_GEN7_PRE_VS_DEPTH_STALL_WRITE = 1 << 2,
88
89 /*
90 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
91 *
92 * "Due to an HW issue driver needs to send a pipe control with stall
93 * when ever there is state change in depth bias related state"
94 *
95 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
96 *
97 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
98 * in the ring after this instruction
99 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
100 */
101 INTEL_CMD_WA_GEN7_POST_COMMAND_CS_STALL = 1 << 3,
102
103 /*
104 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
105 *
106 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
107 * Enable bit set after all the following states are programmed:
108 *
109 * - 3DSTATE_PS
110 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
111 * - 3DSTATE_CONSTANT_PS
112 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
113 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
114 * - 3DSTATE_CC_STATE_POINTERS
115 * - 3DSTATE_BLEND_STATE_POINTERS
116 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
117 */
118 INTEL_CMD_WA_GEN7_POST_COMMAND_DEPTH_STALL = 1 << 4,
119};
120
Chia-I Wu68f319d2014-09-09 09:43:21 +0800121enum intel_cmd_writer_type {
122 INTEL_CMD_WRITER_BATCH,
123 INTEL_CMD_WRITER_STATE,
124 INTEL_CMD_WRITER_INSTRUCTION,
125
126 INTEL_CMD_WRITER_COUNT,
127};
128
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600129struct intel_cmd_shader {
Chia-I Wuf2b6d722014-09-02 08:52:27 +0800130 const struct intel_pipeline_shader *shader;
Chia-I Wu72292b72014-09-09 10:48:33 +0800131 uint32_t kernel_offset;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600132};
133
Chia-I Wub2755562014-08-20 13:38:52 +0800134/*
135 * States bounded to the command buffer. We want to write states directly to
136 * the command buffer when possible, and reduce this struct.
137 */
138struct intel_cmd_bind {
139 struct {
140 const struct intel_pipeline *graphics;
141 const struct intel_pipeline *compute;
142 const struct intel_pipeline_delta *graphics_delta;
143 const struct intel_pipeline_delta *compute_delta;
144 } pipeline;
145
Courtney Goeltzenleuchterba305812014-08-28 17:27:47 -0600146 /*
147 * Currently active shaders for this command buffer.
148 * Provides data only available after shaders are bound to
149 * a command buffer, such as the kernel position in the kernel BO
150 */
151 struct intel_cmd_shader vs;
152 struct intel_cmd_shader fs;
153 struct intel_cmd_shader gs;
Chia-I Wu95959fb2014-09-02 11:01:03 +0800154 struct intel_cmd_shader tcs;
155 struct intel_cmd_shader tes;
156 struct intel_cmd_shader cs;
Courtney Goeltzenleuchterba305812014-08-28 17:27:47 -0600157
Chia-I Wub2755562014-08-20 13:38:52 +0800158 struct {
Chia-I Wu338fe642014-08-28 10:43:04 +0800159 XGL_UINT count;
160 XGL_UINT used;
161 struct intel_cmd_shader *shaderArray;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600162 } shaderCache;
163
164 struct {
Chia-I Wub2755562014-08-20 13:38:52 +0800165 const struct intel_viewport_state *viewport;
166 const struct intel_raster_state *raster;
167 const struct intel_msaa_state *msaa;
168 const struct intel_blend_state *blend;
169 const struct intel_ds_state *ds;
170 } state;
171
172 struct {
173 const struct intel_dset *graphics;
174 XGL_UINT graphics_offset;
175 const struct intel_dset *compute;
176 XGL_UINT compute_offset;
177 } dset;
178
179 struct {
180 struct intel_mem_view graphics;
181 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +0800182 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +0800183
184 struct {
185 const struct intel_mem *mem;
186 XGL_GPU_SIZE offset;
187 XGL_INDEX_TYPE type;
188 } index;
189
190 struct {
191 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
192 XGL_UINT rt_count;
193
194 const struct intel_ds_view *ds;
195 } att;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800196
Chia-I Wu707a29e2014-08-27 12:51:47 +0800197 XGL_UINT draw_count;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800198 uint32_t wa_flags;
Chia-I Wub2755562014-08-20 13:38:52 +0800199};
Chia-I Wu09142132014-08-11 15:42:55 +0800200
Chia-I Wue24c3292014-08-21 14:05:23 +0800201struct intel_cmd_writer {
Chia-I Wu72292b72014-09-09 10:48:33 +0800202 XGL_SIZE size;
Chia-I Wue24c3292014-08-21 14:05:23 +0800203 struct intel_bo *bo;
Chia-I Wu0f50ba82014-09-09 10:25:46 +0800204 void *ptr;
Chia-I Wue24c3292014-08-21 14:05:23 +0800205
Chia-I Wu72292b72014-09-09 10:48:33 +0800206 XGL_SIZE used;
Chia-I Wue24c3292014-08-21 14:05:23 +0800207};
208
Chia-I Wu730e5362014-08-19 12:15:09 +0800209struct intel_cmd {
210 struct intel_obj obj;
211
212 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800213 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800214 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800215
Chia-I Wu343b1372014-08-20 16:39:20 +0800216 struct intel_cmd_reloc *relocs;
217 XGL_UINT reloc_count;
218
Chia-I Wu730e5362014-08-19 12:15:09 +0800219 XGL_FLAGS flags;
220
Chia-I Wu68f319d2014-09-09 09:43:21 +0800221 struct intel_cmd_writer writers[INTEL_CMD_WRITER_COUNT];
Chia-I Wu730e5362014-08-19 12:15:09 +0800222
Chia-I Wu343b1372014-08-20 16:39:20 +0800223 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800224 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800225
226 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800227};
228
229static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
230{
231 return (struct intel_cmd *) cmd;
232}
233
234static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
235{
236 return (struct intel_cmd *) obj;
237}
238
239XGL_RESULT intel_cmd_create(struct intel_dev *dev,
240 const XGL_CMD_BUFFER_CREATE_INFO *info,
241 struct intel_cmd **cmd_ret);
242void intel_cmd_destroy(struct intel_cmd *cmd);
243
244XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
245XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
246
Chia-I Wue24c3292014-08-21 14:05:23 +0800247static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
248 XGL_GPU_SIZE *used)
249{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800250 const struct intel_cmd_writer *writer =
251 &cmd->writers[INTEL_CMD_WRITER_BATCH];
Chia-I Wue24c3292014-08-21 14:05:23 +0800252
253 if (used)
Chia-I Wu72292b72014-09-09 10:48:33 +0800254 *used = writer->used;
Chia-I Wue24c3292014-08-21 14:05:23 +0800255
256 return writer->bo;
257}
258
Chia-I Wu09142132014-08-11 15:42:55 +0800259XGL_RESULT XGLAPI intelCreateCommandBuffer(
260 XGL_DEVICE device,
261 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
262 XGL_CMD_BUFFER* pCmdBuffer);
263
264XGL_RESULT XGLAPI intelBeginCommandBuffer(
265 XGL_CMD_BUFFER cmdBuffer,
266 XGL_FLAGS flags);
267
268XGL_RESULT XGLAPI intelEndCommandBuffer(
269 XGL_CMD_BUFFER cmdBuffer);
270
271XGL_RESULT XGLAPI intelResetCommandBuffer(
272 XGL_CMD_BUFFER cmdBuffer);
273
274XGL_VOID XGLAPI intelCmdBindPipeline(
275 XGL_CMD_BUFFER cmdBuffer,
276 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
277 XGL_PIPELINE pipeline);
278
279XGL_VOID XGLAPI intelCmdBindPipelineDelta(
280 XGL_CMD_BUFFER cmdBuffer,
281 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
282 XGL_PIPELINE_DELTA delta);
283
284XGL_VOID XGLAPI intelCmdBindStateObject(
285 XGL_CMD_BUFFER cmdBuffer,
286 XGL_STATE_BIND_POINT stateBindPoint,
287 XGL_STATE_OBJECT state);
288
289XGL_VOID XGLAPI intelCmdBindDescriptorSet(
290 XGL_CMD_BUFFER cmdBuffer,
291 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
292 XGL_UINT index,
293 XGL_DESCRIPTOR_SET descriptorSet,
294 XGL_UINT slotOffset);
295
296XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
297 XGL_CMD_BUFFER cmdBuffer,
298 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
299 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
300
301XGL_VOID XGLAPI intelCmdBindIndexData(
302 XGL_CMD_BUFFER cmdBuffer,
303 XGL_GPU_MEMORY mem,
304 XGL_GPU_SIZE offset,
305 XGL_INDEX_TYPE indexType);
306
307XGL_VOID XGLAPI intelCmdBindAttachments(
308 XGL_CMD_BUFFER cmdBuffer,
309 XGL_UINT colorAttachmentCount,
310 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
311 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
312
313XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
314 XGL_CMD_BUFFER cmdBuffer,
315 XGL_UINT transitionCount,
316 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
317
318XGL_VOID XGLAPI intelCmdPrepareImages(
319 XGL_CMD_BUFFER cmdBuffer,
320 XGL_UINT transitionCount,
321 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
322
323XGL_VOID XGLAPI intelCmdDraw(
324 XGL_CMD_BUFFER cmdBuffer,
325 XGL_UINT firstVertex,
326 XGL_UINT vertexCount,
327 XGL_UINT firstInstance,
328 XGL_UINT instanceCount);
329
330XGL_VOID XGLAPI intelCmdDrawIndexed(
331 XGL_CMD_BUFFER cmdBuffer,
332 XGL_UINT firstIndex,
333 XGL_UINT indexCount,
334 XGL_INT vertexOffset,
335 XGL_UINT firstInstance,
336 XGL_UINT instanceCount);
337
338XGL_VOID XGLAPI intelCmdDrawIndirect(
339 XGL_CMD_BUFFER cmdBuffer,
340 XGL_GPU_MEMORY mem,
341 XGL_GPU_SIZE offset,
342 XGL_UINT32 count,
343 XGL_UINT32 stride);
344
345XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
346 XGL_CMD_BUFFER cmdBuffer,
347 XGL_GPU_MEMORY mem,
348 XGL_GPU_SIZE offset,
349 XGL_UINT32 count,
350 XGL_UINT32 stride);
351
352XGL_VOID XGLAPI intelCmdDispatch(
353 XGL_CMD_BUFFER cmdBuffer,
354 XGL_UINT x,
355 XGL_UINT y,
356 XGL_UINT z);
357
358XGL_VOID XGLAPI intelCmdDispatchIndirect(
359 XGL_CMD_BUFFER cmdBuffer,
360 XGL_GPU_MEMORY mem,
361 XGL_GPU_SIZE offset);
362
363XGL_VOID XGLAPI intelCmdCopyMemory(
364 XGL_CMD_BUFFER cmdBuffer,
365 XGL_GPU_MEMORY srcMem,
366 XGL_GPU_MEMORY destMem,
367 XGL_UINT regionCount,
368 const XGL_MEMORY_COPY* pRegions);
369
370XGL_VOID XGLAPI intelCmdCopyImage(
371 XGL_CMD_BUFFER cmdBuffer,
372 XGL_IMAGE srcImage,
373 XGL_IMAGE destImage,
374 XGL_UINT regionCount,
375 const XGL_IMAGE_COPY* pRegions);
376
377XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
378 XGL_CMD_BUFFER cmdBuffer,
379 XGL_GPU_MEMORY srcMem,
380 XGL_IMAGE destImage,
381 XGL_UINT regionCount,
382 const XGL_MEMORY_IMAGE_COPY* pRegions);
383
384XGL_VOID XGLAPI intelCmdCopyImageToMemory(
385 XGL_CMD_BUFFER cmdBuffer,
386 XGL_IMAGE srcImage,
387 XGL_GPU_MEMORY destMem,
388 XGL_UINT regionCount,
389 const XGL_MEMORY_IMAGE_COPY* pRegions);
390
391XGL_VOID XGLAPI intelCmdCloneImageData(
392 XGL_CMD_BUFFER cmdBuffer,
393 XGL_IMAGE srcImage,
394 XGL_IMAGE_STATE srcImageState,
395 XGL_IMAGE destImage,
396 XGL_IMAGE_STATE destImageState);
397
398XGL_VOID XGLAPI intelCmdUpdateMemory(
399 XGL_CMD_BUFFER cmdBuffer,
400 XGL_GPU_MEMORY destMem,
401 XGL_GPU_SIZE destOffset,
402 XGL_GPU_SIZE dataSize,
403 const XGL_UINT32* pData);
404
405XGL_VOID XGLAPI intelCmdFillMemory(
406 XGL_CMD_BUFFER cmdBuffer,
407 XGL_GPU_MEMORY destMem,
408 XGL_GPU_SIZE destOffset,
409 XGL_GPU_SIZE fillSize,
410 XGL_UINT32 data);
411
412XGL_VOID XGLAPI intelCmdClearColorImage(
413 XGL_CMD_BUFFER cmdBuffer,
414 XGL_IMAGE image,
415 const XGL_FLOAT color[4],
416 XGL_UINT rangeCount,
417 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
418
419XGL_VOID XGLAPI intelCmdClearColorImageRaw(
420 XGL_CMD_BUFFER cmdBuffer,
421 XGL_IMAGE image,
422 const XGL_UINT32 color[4],
423 XGL_UINT rangeCount,
424 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
425
426XGL_VOID XGLAPI intelCmdClearDepthStencil(
427 XGL_CMD_BUFFER cmdBuffer,
428 XGL_IMAGE image,
429 XGL_FLOAT depth,
430 XGL_UINT32 stencil,
431 XGL_UINT rangeCount,
432 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
433
434XGL_VOID XGLAPI intelCmdResolveImage(
435 XGL_CMD_BUFFER cmdBuffer,
436 XGL_IMAGE srcImage,
437 XGL_IMAGE destImage,
438 XGL_UINT rectCount,
439 const XGL_IMAGE_RESOLVE* pRects);
440
441XGL_VOID XGLAPI intelCmdSetEvent(
442 XGL_CMD_BUFFER cmdBuffer,
443 XGL_EVENT event);
444
445XGL_VOID XGLAPI intelCmdResetEvent(
446 XGL_CMD_BUFFER cmdBuffer,
447 XGL_EVENT event);
448
449XGL_VOID XGLAPI intelCmdMemoryAtomic(
450 XGL_CMD_BUFFER cmdBuffer,
451 XGL_GPU_MEMORY destMem,
452 XGL_GPU_SIZE destOffset,
453 XGL_UINT64 srcData,
454 XGL_ATOMIC_OP atomicOp);
455
456XGL_VOID XGLAPI intelCmdBeginQuery(
457 XGL_CMD_BUFFER cmdBuffer,
458 XGL_QUERY_POOL queryPool,
459 XGL_UINT slot,
460 XGL_FLAGS flags);
461
462XGL_VOID XGLAPI intelCmdEndQuery(
463 XGL_CMD_BUFFER cmdBuffer,
464 XGL_QUERY_POOL queryPool,
465 XGL_UINT slot);
466
467XGL_VOID XGLAPI intelCmdResetQueryPool(
468 XGL_CMD_BUFFER cmdBuffer,
469 XGL_QUERY_POOL queryPool,
470 XGL_UINT startQuery,
471 XGL_UINT queryCount);
472
473XGL_VOID XGLAPI intelCmdWriteTimestamp(
474 XGL_CMD_BUFFER cmdBuffer,
475 XGL_TIMESTAMP_TYPE timestampType,
476 XGL_GPU_MEMORY destMem,
477 XGL_GPU_SIZE destOffset);
478
479XGL_VOID XGLAPI intelCmdInitAtomicCounters(
480 XGL_CMD_BUFFER cmdBuffer,
481 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
482 XGL_UINT startCounter,
483 XGL_UINT counterCount,
484 const XGL_UINT32* pData);
485
486XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
487 XGL_CMD_BUFFER cmdBuffer,
488 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
489 XGL_UINT startCounter,
490 XGL_UINT counterCount,
491 XGL_GPU_MEMORY srcMem,
492 XGL_GPU_SIZE srcOffset);
493
494XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
495 XGL_CMD_BUFFER cmdBuffer,
496 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
497 XGL_UINT startCounter,
498 XGL_UINT counterCount,
499 XGL_GPU_MEMORY destMem,
500 XGL_GPU_SIZE destOffset);
501
502XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
503 XGL_CMD_BUFFER cmdBuffer,
504 const XGL_CHAR* pMarker);
505
506XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
507 XGL_CMD_BUFFER cmdBuffer);
508
509#endif /* CMD_H */