Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
| 26 | * Courtney Goeltzenleuchter <courtney@lunarg.com> |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 27 | */ |
| 28 | |
| 29 | #ifndef CMD_H |
| 30 | #define CMD_H |
| 31 | |
| 32 | #include "intel.h" |
| 33 | #include "obj.h" |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 34 | #include "view.h" |
| 35 | |
| 36 | struct intel_pipeline; |
Chia-I Wu | f2b6d72 | 2014-09-02 08:52:27 +0800 | [diff] [blame^] | 37 | struct intel_pipeline_shader; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 38 | struct intel_pipeline_delta; |
| 39 | struct intel_viewport_state; |
| 40 | struct intel_raster_state; |
| 41 | struct intel_msaa_state; |
| 42 | struct intel_blend_state; |
| 43 | struct intel_ds_state; |
| 44 | struct intel_dset; |
| 45 | |
Chia-I Wu | 958d1b7 | 2014-08-21 11:28:11 +0800 | [diff] [blame] | 46 | struct intel_cmd_reloc; |
| 47 | |
Chia-I Wu | 8370b40 | 2014-08-29 12:28:37 +0800 | [diff] [blame] | 48 | /* |
| 49 | * We know what workarounds are needed for intel_pipeline. These are mostly |
| 50 | * for intel_pipeline_delta. |
| 51 | */ |
| 52 | enum intel_cmd_wa_flags { |
| 53 | /* |
| 54 | * From the Sandy Bridge PRM, volume 2 part 1, page 60: |
| 55 | * |
| 56 | * "Before any depth stall flush (including those produced by |
| 57 | * non-pipelined state commands), software needs to first send a |
| 58 | * PIPE_CONTROL with no bits set except Post-Sync Operation != 0." |
| 59 | */ |
| 60 | INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE = 1 << 0, |
| 61 | |
| 62 | /* |
| 63 | * From the Sandy Bridge PRM, volume 2 part 1, page 274: |
| 64 | * |
| 65 | * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard |
| 66 | * field set (DW1 Bit 1), must be issued prior to any change to the |
| 67 | * value in this field (Maximum Number of Threads in 3DSTATE_WM)" |
| 68 | * |
| 69 | * From the Ivy Bridge PRM, volume 2 part 1, page 286: |
| 70 | * |
| 71 | * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed |
| 72 | * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at |
| 73 | * Pixel Scoreboard set is required to be issued." |
| 74 | */ |
| 75 | INTEL_CMD_WA_GEN6_PRE_COMMAND_SCOREBOARD_STALL = 1 << 1, |
| 76 | |
| 77 | /* |
| 78 | * From the Ivy Bridge PRM, volume 2 part 1, page 106: |
| 79 | * |
| 80 | * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth |
| 81 | * stall needs to be sent just prior to any 3DSTATE_VS, |
| 82 | * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS, |
| 83 | * 3DSTATE_BINDING_TABLE_POINTER_VS, 3DSTATE_SAMPLER_STATE_POINTER_VS |
| 84 | * command. Only one PIPE_CONTROL needs to be sent before any |
| 85 | * combination of VS associated 3DSTATE." |
| 86 | */ |
| 87 | INTEL_CMD_WA_GEN7_PRE_VS_DEPTH_STALL_WRITE = 1 << 2, |
| 88 | |
| 89 | /* |
| 90 | * From the Ivy Bridge PRM, volume 2 part 1, page 258: |
| 91 | * |
| 92 | * "Due to an HW issue driver needs to send a pipe control with stall |
| 93 | * when ever there is state change in depth bias related state" |
| 94 | * |
| 95 | * From the Ivy Bridge PRM, volume 2 part 1, page 292: |
| 96 | * |
| 97 | * "A PIPE_CONTOL command with the CS Stall bit set must be programmed |
| 98 | * in the ring after this instruction |
| 99 | * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)." |
| 100 | */ |
| 101 | INTEL_CMD_WA_GEN7_POST_COMMAND_CS_STALL = 1 << 3, |
| 102 | |
| 103 | /* |
| 104 | * From the Ivy Bridge PRM, volume 2 part 1, page 276: |
| 105 | * |
| 106 | * "The driver must make sure a PIPE_CONTROL with the Depth Stall |
| 107 | * Enable bit set after all the following states are programmed: |
| 108 | * |
| 109 | * - 3DSTATE_PS |
| 110 | * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC |
| 111 | * - 3DSTATE_CONSTANT_PS |
| 112 | * - 3DSTATE_BINDING_TABLE_POINTERS_PS |
| 113 | * - 3DSTATE_SAMPLER_STATE_POINTERS_PS |
| 114 | * - 3DSTATE_CC_STATE_POINTERS |
| 115 | * - 3DSTATE_BLEND_STATE_POINTERS |
| 116 | * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS" |
| 117 | */ |
| 118 | INTEL_CMD_WA_GEN7_POST_COMMAND_DEPTH_STALL = 1 << 4, |
| 119 | }; |
| 120 | |
Courtney Goeltzenleuchter | d85c1d6 | 2014-08-27 14:04:53 -0600 | [diff] [blame] | 121 | struct intel_cmd_shader { |
Chia-I Wu | f2b6d72 | 2014-09-02 08:52:27 +0800 | [diff] [blame^] | 122 | const struct intel_pipeline_shader *shader; |
Courtney Goeltzenleuchter | d85c1d6 | 2014-08-27 14:04:53 -0600 | [diff] [blame] | 123 | XGL_UINT kernel_pos; |
| 124 | }; |
| 125 | |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 126 | /* |
| 127 | * States bounded to the command buffer. We want to write states directly to |
| 128 | * the command buffer when possible, and reduce this struct. |
| 129 | */ |
| 130 | struct intel_cmd_bind { |
| 131 | struct { |
| 132 | const struct intel_pipeline *graphics; |
| 133 | const struct intel_pipeline *compute; |
| 134 | const struct intel_pipeline_delta *graphics_delta; |
| 135 | const struct intel_pipeline_delta *compute_delta; |
| 136 | } pipeline; |
| 137 | |
Courtney Goeltzenleuchter | ba30581 | 2014-08-28 17:27:47 -0600 | [diff] [blame] | 138 | /* |
| 139 | * Currently active shaders for this command buffer. |
| 140 | * Provides data only available after shaders are bound to |
| 141 | * a command buffer, such as the kernel position in the kernel BO |
| 142 | */ |
| 143 | struct intel_cmd_shader vs; |
| 144 | struct intel_cmd_shader fs; |
| 145 | struct intel_cmd_shader gs; |
| 146 | struct intel_cmd_shader tess_control; |
| 147 | struct intel_cmd_shader tess_eval; |
| 148 | struct intel_cmd_shader compute; |
| 149 | |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 150 | struct { |
Chia-I Wu | 338fe64 | 2014-08-28 10:43:04 +0800 | [diff] [blame] | 151 | XGL_UINT count; |
| 152 | XGL_UINT used; |
| 153 | struct intel_cmd_shader *shaderArray; |
Courtney Goeltzenleuchter | d85c1d6 | 2014-08-27 14:04:53 -0600 | [diff] [blame] | 154 | } shaderCache; |
| 155 | |
| 156 | struct { |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 157 | const struct intel_viewport_state *viewport; |
| 158 | const struct intel_raster_state *raster; |
| 159 | const struct intel_msaa_state *msaa; |
| 160 | const struct intel_blend_state *blend; |
| 161 | const struct intel_ds_state *ds; |
| 162 | } state; |
| 163 | |
| 164 | struct { |
| 165 | const struct intel_dset *graphics; |
| 166 | XGL_UINT graphics_offset; |
| 167 | const struct intel_dset *compute; |
| 168 | XGL_UINT compute_offset; |
| 169 | } dset; |
| 170 | |
| 171 | struct { |
| 172 | struct intel_mem_view graphics; |
| 173 | struct intel_mem_view compute; |
Chia-I Wu | 9f1722c | 2014-08-25 10:17:58 +0800 | [diff] [blame] | 174 | } dyn_view; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 175 | |
| 176 | struct { |
| 177 | const struct intel_mem *mem; |
| 178 | XGL_GPU_SIZE offset; |
| 179 | XGL_INDEX_TYPE type; |
| 180 | } index; |
| 181 | |
| 182 | struct { |
| 183 | const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS]; |
| 184 | XGL_UINT rt_count; |
| 185 | |
| 186 | const struct intel_ds_view *ds; |
| 187 | } att; |
Chia-I Wu | 48c283d | 2014-08-25 23:13:46 +0800 | [diff] [blame] | 188 | |
Chia-I Wu | 707a29e | 2014-08-27 12:51:47 +0800 | [diff] [blame] | 189 | XGL_UINT draw_count; |
Chia-I Wu | 48c283d | 2014-08-25 23:13:46 +0800 | [diff] [blame] | 190 | uint32_t wa_flags; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 191 | }; |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 192 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 193 | struct intel_cmd_writer { |
| 194 | struct intel_bo *bo; |
| 195 | void *ptr_opaque; |
| 196 | |
| 197 | /* in DWords */ |
| 198 | XGL_UINT size; |
| 199 | XGL_UINT used; |
| 200 | }; |
| 201 | |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 202 | struct intel_cmd { |
| 203 | struct intel_obj obj; |
| 204 | |
| 205 | struct intel_dev *dev; |
Chia-I Wu | 0b78444 | 2014-08-25 22:54:16 +0800 | [diff] [blame] | 206 | struct intel_bo *scratch_bo; |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 207 | int pipeline_select; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 208 | |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 209 | struct intel_cmd_reloc *relocs; |
| 210 | XGL_UINT reloc_count; |
| 211 | |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 212 | XGL_FLAGS flags; |
| 213 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 214 | struct intel_cmd_writer batch; |
Chia-I Wu | 24565ee | 2014-08-21 20:24:31 +0800 | [diff] [blame] | 215 | struct intel_cmd_writer state; |
Chia-I Wu | 1cbc005 | 2014-08-25 09:50:12 +0800 | [diff] [blame] | 216 | struct intel_cmd_writer kernel; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 217 | |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 218 | XGL_UINT reloc_used; |
Chia-I Wu | 0496670 | 2014-08-20 15:05:03 +0800 | [diff] [blame] | 219 | XGL_RESULT result; |
Chia-I Wu | b275556 | 2014-08-20 13:38:52 +0800 | [diff] [blame] | 220 | |
| 221 | struct intel_cmd_bind bind; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd) |
| 225 | { |
| 226 | return (struct intel_cmd *) cmd; |
| 227 | } |
| 228 | |
| 229 | static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj) |
| 230 | { |
| 231 | return (struct intel_cmd *) obj; |
| 232 | } |
| 233 | |
| 234 | XGL_RESULT intel_cmd_create(struct intel_dev *dev, |
| 235 | const XGL_CMD_BUFFER_CREATE_INFO *info, |
| 236 | struct intel_cmd **cmd_ret); |
| 237 | void intel_cmd_destroy(struct intel_cmd *cmd); |
| 238 | |
| 239 | XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags); |
| 240 | XGL_RESULT intel_cmd_end(struct intel_cmd *cmd); |
| 241 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 242 | static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd, |
| 243 | XGL_GPU_SIZE *used) |
| 244 | { |
| 245 | const struct intel_cmd_writer *writer = &cmd->batch; |
| 246 | |
| 247 | if (used) |
| 248 | *used = sizeof(uint32_t) * writer->used; |
| 249 | |
| 250 | return writer->bo; |
| 251 | } |
| 252 | |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 253 | XGL_RESULT XGLAPI intelCreateCommandBuffer( |
| 254 | XGL_DEVICE device, |
| 255 | const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo, |
| 256 | XGL_CMD_BUFFER* pCmdBuffer); |
| 257 | |
| 258 | XGL_RESULT XGLAPI intelBeginCommandBuffer( |
| 259 | XGL_CMD_BUFFER cmdBuffer, |
| 260 | XGL_FLAGS flags); |
| 261 | |
| 262 | XGL_RESULT XGLAPI intelEndCommandBuffer( |
| 263 | XGL_CMD_BUFFER cmdBuffer); |
| 264 | |
| 265 | XGL_RESULT XGLAPI intelResetCommandBuffer( |
| 266 | XGL_CMD_BUFFER cmdBuffer); |
| 267 | |
| 268 | XGL_VOID XGLAPI intelCmdBindPipeline( |
| 269 | XGL_CMD_BUFFER cmdBuffer, |
| 270 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 271 | XGL_PIPELINE pipeline); |
| 272 | |
| 273 | XGL_VOID XGLAPI intelCmdBindPipelineDelta( |
| 274 | XGL_CMD_BUFFER cmdBuffer, |
| 275 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 276 | XGL_PIPELINE_DELTA delta); |
| 277 | |
| 278 | XGL_VOID XGLAPI intelCmdBindStateObject( |
| 279 | XGL_CMD_BUFFER cmdBuffer, |
| 280 | XGL_STATE_BIND_POINT stateBindPoint, |
| 281 | XGL_STATE_OBJECT state); |
| 282 | |
| 283 | XGL_VOID XGLAPI intelCmdBindDescriptorSet( |
| 284 | XGL_CMD_BUFFER cmdBuffer, |
| 285 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 286 | XGL_UINT index, |
| 287 | XGL_DESCRIPTOR_SET descriptorSet, |
| 288 | XGL_UINT slotOffset); |
| 289 | |
| 290 | XGL_VOID XGLAPI intelCmdBindDynamicMemoryView( |
| 291 | XGL_CMD_BUFFER cmdBuffer, |
| 292 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 293 | const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView); |
| 294 | |
| 295 | XGL_VOID XGLAPI intelCmdBindIndexData( |
| 296 | XGL_CMD_BUFFER cmdBuffer, |
| 297 | XGL_GPU_MEMORY mem, |
| 298 | XGL_GPU_SIZE offset, |
| 299 | XGL_INDEX_TYPE indexType); |
| 300 | |
| 301 | XGL_VOID XGLAPI intelCmdBindAttachments( |
| 302 | XGL_CMD_BUFFER cmdBuffer, |
| 303 | XGL_UINT colorAttachmentCount, |
| 304 | const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments, |
| 305 | const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment); |
| 306 | |
| 307 | XGL_VOID XGLAPI intelCmdPrepareMemoryRegions( |
| 308 | XGL_CMD_BUFFER cmdBuffer, |
| 309 | XGL_UINT transitionCount, |
| 310 | const XGL_MEMORY_STATE_TRANSITION* pStateTransitions); |
| 311 | |
| 312 | XGL_VOID XGLAPI intelCmdPrepareImages( |
| 313 | XGL_CMD_BUFFER cmdBuffer, |
| 314 | XGL_UINT transitionCount, |
| 315 | const XGL_IMAGE_STATE_TRANSITION* pStateTransitions); |
| 316 | |
| 317 | XGL_VOID XGLAPI intelCmdDraw( |
| 318 | XGL_CMD_BUFFER cmdBuffer, |
| 319 | XGL_UINT firstVertex, |
| 320 | XGL_UINT vertexCount, |
| 321 | XGL_UINT firstInstance, |
| 322 | XGL_UINT instanceCount); |
| 323 | |
| 324 | XGL_VOID XGLAPI intelCmdDrawIndexed( |
| 325 | XGL_CMD_BUFFER cmdBuffer, |
| 326 | XGL_UINT firstIndex, |
| 327 | XGL_UINT indexCount, |
| 328 | XGL_INT vertexOffset, |
| 329 | XGL_UINT firstInstance, |
| 330 | XGL_UINT instanceCount); |
| 331 | |
| 332 | XGL_VOID XGLAPI intelCmdDrawIndirect( |
| 333 | XGL_CMD_BUFFER cmdBuffer, |
| 334 | XGL_GPU_MEMORY mem, |
| 335 | XGL_GPU_SIZE offset, |
| 336 | XGL_UINT32 count, |
| 337 | XGL_UINT32 stride); |
| 338 | |
| 339 | XGL_VOID XGLAPI intelCmdDrawIndexedIndirect( |
| 340 | XGL_CMD_BUFFER cmdBuffer, |
| 341 | XGL_GPU_MEMORY mem, |
| 342 | XGL_GPU_SIZE offset, |
| 343 | XGL_UINT32 count, |
| 344 | XGL_UINT32 stride); |
| 345 | |
| 346 | XGL_VOID XGLAPI intelCmdDispatch( |
| 347 | XGL_CMD_BUFFER cmdBuffer, |
| 348 | XGL_UINT x, |
| 349 | XGL_UINT y, |
| 350 | XGL_UINT z); |
| 351 | |
| 352 | XGL_VOID XGLAPI intelCmdDispatchIndirect( |
| 353 | XGL_CMD_BUFFER cmdBuffer, |
| 354 | XGL_GPU_MEMORY mem, |
| 355 | XGL_GPU_SIZE offset); |
| 356 | |
| 357 | XGL_VOID XGLAPI intelCmdCopyMemory( |
| 358 | XGL_CMD_BUFFER cmdBuffer, |
| 359 | XGL_GPU_MEMORY srcMem, |
| 360 | XGL_GPU_MEMORY destMem, |
| 361 | XGL_UINT regionCount, |
| 362 | const XGL_MEMORY_COPY* pRegions); |
| 363 | |
| 364 | XGL_VOID XGLAPI intelCmdCopyImage( |
| 365 | XGL_CMD_BUFFER cmdBuffer, |
| 366 | XGL_IMAGE srcImage, |
| 367 | XGL_IMAGE destImage, |
| 368 | XGL_UINT regionCount, |
| 369 | const XGL_IMAGE_COPY* pRegions); |
| 370 | |
| 371 | XGL_VOID XGLAPI intelCmdCopyMemoryToImage( |
| 372 | XGL_CMD_BUFFER cmdBuffer, |
| 373 | XGL_GPU_MEMORY srcMem, |
| 374 | XGL_IMAGE destImage, |
| 375 | XGL_UINT regionCount, |
| 376 | const XGL_MEMORY_IMAGE_COPY* pRegions); |
| 377 | |
| 378 | XGL_VOID XGLAPI intelCmdCopyImageToMemory( |
| 379 | XGL_CMD_BUFFER cmdBuffer, |
| 380 | XGL_IMAGE srcImage, |
| 381 | XGL_GPU_MEMORY destMem, |
| 382 | XGL_UINT regionCount, |
| 383 | const XGL_MEMORY_IMAGE_COPY* pRegions); |
| 384 | |
| 385 | XGL_VOID XGLAPI intelCmdCloneImageData( |
| 386 | XGL_CMD_BUFFER cmdBuffer, |
| 387 | XGL_IMAGE srcImage, |
| 388 | XGL_IMAGE_STATE srcImageState, |
| 389 | XGL_IMAGE destImage, |
| 390 | XGL_IMAGE_STATE destImageState); |
| 391 | |
| 392 | XGL_VOID XGLAPI intelCmdUpdateMemory( |
| 393 | XGL_CMD_BUFFER cmdBuffer, |
| 394 | XGL_GPU_MEMORY destMem, |
| 395 | XGL_GPU_SIZE destOffset, |
| 396 | XGL_GPU_SIZE dataSize, |
| 397 | const XGL_UINT32* pData); |
| 398 | |
| 399 | XGL_VOID XGLAPI intelCmdFillMemory( |
| 400 | XGL_CMD_BUFFER cmdBuffer, |
| 401 | XGL_GPU_MEMORY destMem, |
| 402 | XGL_GPU_SIZE destOffset, |
| 403 | XGL_GPU_SIZE fillSize, |
| 404 | XGL_UINT32 data); |
| 405 | |
| 406 | XGL_VOID XGLAPI intelCmdClearColorImage( |
| 407 | XGL_CMD_BUFFER cmdBuffer, |
| 408 | XGL_IMAGE image, |
| 409 | const XGL_FLOAT color[4], |
| 410 | XGL_UINT rangeCount, |
| 411 | const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges); |
| 412 | |
| 413 | XGL_VOID XGLAPI intelCmdClearColorImageRaw( |
| 414 | XGL_CMD_BUFFER cmdBuffer, |
| 415 | XGL_IMAGE image, |
| 416 | const XGL_UINT32 color[4], |
| 417 | XGL_UINT rangeCount, |
| 418 | const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges); |
| 419 | |
| 420 | XGL_VOID XGLAPI intelCmdClearDepthStencil( |
| 421 | XGL_CMD_BUFFER cmdBuffer, |
| 422 | XGL_IMAGE image, |
| 423 | XGL_FLOAT depth, |
| 424 | XGL_UINT32 stencil, |
| 425 | XGL_UINT rangeCount, |
| 426 | const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges); |
| 427 | |
| 428 | XGL_VOID XGLAPI intelCmdResolveImage( |
| 429 | XGL_CMD_BUFFER cmdBuffer, |
| 430 | XGL_IMAGE srcImage, |
| 431 | XGL_IMAGE destImage, |
| 432 | XGL_UINT rectCount, |
| 433 | const XGL_IMAGE_RESOLVE* pRects); |
| 434 | |
| 435 | XGL_VOID XGLAPI intelCmdSetEvent( |
| 436 | XGL_CMD_BUFFER cmdBuffer, |
| 437 | XGL_EVENT event); |
| 438 | |
| 439 | XGL_VOID XGLAPI intelCmdResetEvent( |
| 440 | XGL_CMD_BUFFER cmdBuffer, |
| 441 | XGL_EVENT event); |
| 442 | |
| 443 | XGL_VOID XGLAPI intelCmdMemoryAtomic( |
| 444 | XGL_CMD_BUFFER cmdBuffer, |
| 445 | XGL_GPU_MEMORY destMem, |
| 446 | XGL_GPU_SIZE destOffset, |
| 447 | XGL_UINT64 srcData, |
| 448 | XGL_ATOMIC_OP atomicOp); |
| 449 | |
| 450 | XGL_VOID XGLAPI intelCmdBeginQuery( |
| 451 | XGL_CMD_BUFFER cmdBuffer, |
| 452 | XGL_QUERY_POOL queryPool, |
| 453 | XGL_UINT slot, |
| 454 | XGL_FLAGS flags); |
| 455 | |
| 456 | XGL_VOID XGLAPI intelCmdEndQuery( |
| 457 | XGL_CMD_BUFFER cmdBuffer, |
| 458 | XGL_QUERY_POOL queryPool, |
| 459 | XGL_UINT slot); |
| 460 | |
| 461 | XGL_VOID XGLAPI intelCmdResetQueryPool( |
| 462 | XGL_CMD_BUFFER cmdBuffer, |
| 463 | XGL_QUERY_POOL queryPool, |
| 464 | XGL_UINT startQuery, |
| 465 | XGL_UINT queryCount); |
| 466 | |
| 467 | XGL_VOID XGLAPI intelCmdWriteTimestamp( |
| 468 | XGL_CMD_BUFFER cmdBuffer, |
| 469 | XGL_TIMESTAMP_TYPE timestampType, |
| 470 | XGL_GPU_MEMORY destMem, |
| 471 | XGL_GPU_SIZE destOffset); |
| 472 | |
| 473 | XGL_VOID XGLAPI intelCmdInitAtomicCounters( |
| 474 | XGL_CMD_BUFFER cmdBuffer, |
| 475 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 476 | XGL_UINT startCounter, |
| 477 | XGL_UINT counterCount, |
| 478 | const XGL_UINT32* pData); |
| 479 | |
| 480 | XGL_VOID XGLAPI intelCmdLoadAtomicCounters( |
| 481 | XGL_CMD_BUFFER cmdBuffer, |
| 482 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 483 | XGL_UINT startCounter, |
| 484 | XGL_UINT counterCount, |
| 485 | XGL_GPU_MEMORY srcMem, |
| 486 | XGL_GPU_SIZE srcOffset); |
| 487 | |
| 488 | XGL_VOID XGLAPI intelCmdSaveAtomicCounters( |
| 489 | XGL_CMD_BUFFER cmdBuffer, |
| 490 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 491 | XGL_UINT startCounter, |
| 492 | XGL_UINT counterCount, |
| 493 | XGL_GPU_MEMORY destMem, |
| 494 | XGL_GPU_SIZE destOffset); |
| 495 | |
| 496 | XGL_VOID XGLAPI intelCmdDbgMarkerBegin( |
| 497 | XGL_CMD_BUFFER cmdBuffer, |
| 498 | const XGL_CHAR* pMarker); |
| 499 | |
| 500 | XGL_VOID XGLAPI intelCmdDbgMarkerEnd( |
| 501 | XGL_CMD_BUFFER cmdBuffer); |
| 502 | |
| 503 | #endif /* CMD_H */ |