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gerrit-public.fairphone.software / toolchain / llvm-project / 4891c724aabac8c78d95391db76d04db4ff8d9d5 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: a16ff3f523a5e800bb0abffd3bdf3b48960101a2 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]21#include "llvm/CodeGen/LivePhysRegs.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]22#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]27#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]28#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]29#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]31#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]32#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]33#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]34#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]35#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]36#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]37#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]40#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]61static cl::opt<unsigned>
62PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67static cl::opt<unsigned>
68UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
Marina Yatsina88f0c312016-08-11 07:32:08 +0000[diff] [blame]71 cl::init(128), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]72
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]73enum {
74 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]75 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]79 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]80 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]104};
105
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]106struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]107 uint16_t RegOp;
108 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]109 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]110};
111
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]112// Pin the vtable to this file.
113void X86InstrInfo::anchor() {}
114
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]115X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
Dean Michael Berris52735fc2016-07-14 04:06:33 +0000[diff] [blame]120 X86::CATCHRET,
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]122 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]123
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]124 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
133 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
134 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
136 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
139 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
140 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
142 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
145 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
146 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
148 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16rCL, X86::SHL16mCL, 0 },
232 { X86::SHL16ri, X86::SHL16mi, 0 },
233 { X86::SHL32rCL, X86::SHL32mCL, 0 },
234 { X86::SHL32ri, X86::SHL32mi, 0 },
235 { X86::SHL64rCL, X86::SHL64mCL, 0 },
236 { X86::SHL64ri, X86::SHL64mi, 0 },
237 { X86::SHL8rCL, X86::SHL8mCL, 0 },
238 { X86::SHL8ri, X86::SHL8mi, 0 },
239 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
240 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
241 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
242 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
243 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
244 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
245 { X86::SHR16r1, X86::SHR16m1, 0 },
246 { X86::SHR16rCL, X86::SHR16mCL, 0 },
247 { X86::SHR16ri, X86::SHR16mi, 0 },
248 { X86::SHR32r1, X86::SHR32m1, 0 },
249 { X86::SHR32rCL, X86::SHR32mCL, 0 },
250 { X86::SHR32ri, X86::SHR32mi, 0 },
251 { X86::SHR64r1, X86::SHR64m1, 0 },
252 { X86::SHR64rCL, X86::SHR64mCL, 0 },
253 { X86::SHR64ri, X86::SHR64mi, 0 },
254 { X86::SHR8r1, X86::SHR8m1, 0 },
255 { X86::SHR8rCL, X86::SHR8mCL, 0 },
256 { X86::SHR8ri, X86::SHR8mi, 0 },
257 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
258 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
259 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
260 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
261 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
262 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
263 { X86::SUB16ri, X86::SUB16mi, 0 },
264 { X86::SUB16ri8, X86::SUB16mi8, 0 },
265 { X86::SUB16rr, X86::SUB16mr, 0 },
266 { X86::SUB32ri, X86::SUB32mi, 0 },
267 { X86::SUB32ri8, X86::SUB32mi8, 0 },
268 { X86::SUB32rr, X86::SUB32mr, 0 },
269 { X86::SUB64ri32, X86::SUB64mi32, 0 },
270 { X86::SUB64ri8, X86::SUB64mi8, 0 },
271 { X86::SUB64rr, X86::SUB64mr, 0 },
272 { X86::SUB8ri, X86::SUB8mi, 0 },
273 { X86::SUB8rr, X86::SUB8mr, 0 },
274 { X86::XOR16ri, X86::XOR16mi, 0 },
275 { X86::XOR16ri8, X86::XOR16mi8, 0 },
276 { X86::XOR16rr, X86::XOR16mr, 0 },
277 { X86::XOR32ri, X86::XOR32mi, 0 },
278 { X86::XOR32ri8, X86::XOR32mi8, 0 },
279 { X86::XOR32rr, X86::XOR32mr, 0 },
280 { X86::XOR64ri32, X86::XOR64mi32, 0 },
281 { X86::XOR64ri8, X86::XOR64mi8, 0 },
282 { X86::XOR64rr, X86::XOR64mr, 0 },
283 { X86::XOR8ri, X86::XOR8mi, 0 },
284 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]285 };
286
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]287 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]289 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]290 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]291 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]292 }
293
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]294 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]295 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
296 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
297 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
298 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
299 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]300 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
301 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
302 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
303 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
304 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
305 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
306 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
307 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
308 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
309 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
310 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
311 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
312 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
313 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
314 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]315 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]316 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
317 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
318 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
319 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
320 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
321 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
322 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
323 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
324 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
325 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
326 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
327 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
328 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
329 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
330 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
331 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
332 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
333 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
334 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
336 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
337 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
339 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
340 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
341 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
342 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
343 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]344 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
345 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
346 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
347 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]348 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
349 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]350 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
351 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
352 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]353 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
354 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
355 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
356 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
357 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
358 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
359 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
360 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
361 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
362 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
363 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
364 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
365 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
366 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
367 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
368 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
369 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
370 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]371 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]372 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
373 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
374 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]375 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]378 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]379 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]380 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
382 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
383 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
384 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
386 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
387 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]389 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
390 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]391
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]392 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]393 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]394 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]398 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]399
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]400 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]401 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
403 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
404 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
405 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
406 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]408 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]410 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]411 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]412
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]413 // AVX-512 foldable instructions (256-bit versions)
414 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
415 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
416 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
417 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
418 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
423 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]424
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]425 // AVX-512 foldable instructions (128-bit versions)
426 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
427 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
428 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
429 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
430 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
431 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
432 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
433 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
434 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]435 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]436
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]437 // F16C foldable instructions
438 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
439 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]440 };
441
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]442 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]443 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]445 }
446
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]447 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]448 { X86::BSF16rr, X86::BSF16rm, 0 },
449 { X86::BSF32rr, X86::BSF32rm, 0 },
450 { X86::BSF64rr, X86::BSF64rm, 0 },
451 { X86::BSR16rr, X86::BSR16rm, 0 },
452 { X86::BSR32rr, X86::BSR32rm, 0 },
453 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]454 { X86::CMP16rr, X86::CMP16rm, 0 },
455 { X86::CMP32rr, X86::CMP32rm, 0 },
456 { X86::CMP64rr, X86::CMP64rm, 0 },
457 { X86::CMP8rr, X86::CMP8rm, 0 },
458 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
459 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
460 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
461 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
462 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
463 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
464 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
465 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
466 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
467 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]468 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
469 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
470 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
471 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
472 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
473 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
474 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
475 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]476 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
477 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]478 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
479 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]480 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]481 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]482 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]483 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]484 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]485 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]486 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
487 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
488 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
489 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
490 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
491 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
492 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
493 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]494 { X86::MOV16rr, X86::MOV16rm, 0 },
495 { X86::MOV32rr, X86::MOV32rm, 0 },
496 { X86::MOV64rr, X86::MOV64rm, 0 },
497 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
498 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
499 { X86::MOV8rr, X86::MOV8rm, 0 },
500 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
501 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]502 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
503 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
504 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
505 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]506 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
507 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
508 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
509 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
510 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
511 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
512 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
513 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
514 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
515 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]516 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
517 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
518 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
519 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
520 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]521 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
522 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
523 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]524 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
525 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
526 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
527 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
528 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
529 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
530 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
531 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
532 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
533 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
534 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
535 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
536 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
537 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
538 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
539 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
540 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]541 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
542 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
543 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]544 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]545 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]546 { X86::RCPSSr, X86::RCPSSm, 0 },
547 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]548 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
549 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]550 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]551 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
552 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
553 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]554 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]555 { X86::SQRTSDr, X86::SQRTSDm, 0 },
556 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
557 { X86::SQRTSSr, X86::SQRTSSm, 0 },
558 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
559 { X86::TEST16rr, X86::TEST16rm, 0 },
560 { X86::TEST32rr, X86::TEST32rm, 0 },
561 { X86::TEST64rr, X86::TEST64rm, 0 },
562 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]563 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]564 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
565 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]566
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]567 // MMX version of foldable instructions
568 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
569 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
570 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
571 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
572 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
573 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
574 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
575 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
576 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
577 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
578
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]579 // 3DNow! version of foldable instructions
580 { X86::PF2IDrr, X86::PF2IDrm, 0 },
581 { X86::PF2IWrr, X86::PF2IWrm, 0 },
582 { X86::PFRCPrr, X86::PFRCPrm, 0 },
583 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
584 { X86::PI2FDrr, X86::PI2FDrm, 0 },
585 { X86::PI2FWrr, X86::PI2FWrm, 0 },
586 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
587
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]588 // AVX 128-bit versions of foldable instructions
589 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
590 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]591 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
592 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]593 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
594 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]595 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]596 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
597 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
598 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
600 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
601 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
602 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
603 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
604 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]605 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]606 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]607 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]608 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]609 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]610 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]611 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
612 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]613 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
614 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
615 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
616 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
617 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
618 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
619 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
620 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]621 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
622 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]623 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]624 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]625 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]626 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
627 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
628 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]629 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
630 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
631 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
632 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
633 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]634 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
635 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]636 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
637 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
638 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
639 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
640 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
641 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
642 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
643 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
644 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
645 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
646 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
647 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]648 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
649 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
650 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]651 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]652 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]653 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
654 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]655 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]656 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]657 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]658 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
659 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]660 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]661 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]662
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]663 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]664 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]665 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]666 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]667 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]668 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]669 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]670 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
671 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]672 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
673 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]674 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]675 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]676 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
677 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]678 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]679 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]680 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
681 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]682 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]683 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]684 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
685 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]686 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
687 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
688 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]689 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
690 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]691
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]692 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]693
694 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]699 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
700 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
701 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]702 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
703 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
704 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]705 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
706 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
707 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
708 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
709 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
710 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
711 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
712 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
713 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
714 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
715 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
716 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
717 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
718 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
719 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
720 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
721 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
722 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
723 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
724 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
725 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
726 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]727 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
728 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
729 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]730
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]731 // XOP foldable instructions
732 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
733 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
734 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
735 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
736 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
737 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
738 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
739 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
740 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
741 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
742 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
743 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
744 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
745 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
746 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
747 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
748 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
749 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
750 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
751 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
752 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
753 { X86::VPROTBri, X86::VPROTBmi, 0 },
754 { X86::VPROTBrr, X86::VPROTBmr, 0 },
755 { X86::VPROTDri, X86::VPROTDmi, 0 },
756 { X86::VPROTDrr, X86::VPROTDmr, 0 },
757 { X86::VPROTQri, X86::VPROTQmi, 0 },
758 { X86::VPROTQrr, X86::VPROTQmr, 0 },
759 { X86::VPROTWri, X86::VPROTWmi, 0 },
760 { X86::VPROTWrr, X86::VPROTWmr, 0 },
761 { X86::VPSHABrr, X86::VPSHABmr, 0 },
762 { X86::VPSHADrr, X86::VPSHADmr, 0 },
763 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
764 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
765 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
766 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
767 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
768 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
769
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]770 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]771 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
772 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]773 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
774 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
775 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
776 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
777 { X86::BLCI32rr, X86::BLCI32rm, 0 },
778 { X86::BLCI64rr, X86::BLCI64rm, 0 },
779 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
780 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
781 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
782 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
783 { X86::BLCS32rr, X86::BLCS32rm, 0 },
784 { X86::BLCS64rr, X86::BLCS64rm, 0 },
785 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
786 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]787 { X86::BLSI32rr, X86::BLSI32rm, 0 },
788 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]789 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
790 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]791 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
792 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
793 { X86::BLSR32rr, X86::BLSR32rm, 0 },
794 { X86::BLSR64rr, X86::BLSR64rm, 0 },
795 { X86::BZHI32rr, X86::BZHI32rm, 0 },
796 { X86::BZHI64rr, X86::BZHI64rm, 0 },
797 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
798 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
799 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
800 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
801 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
802 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]803 { X86::RORX32ri, X86::RORX32mi, 0 },
804 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]805 { X86::SARX32rr, X86::SARX32rm, 0 },
806 { X86::SARX64rr, X86::SARX64rm, 0 },
807 { X86::SHRX32rr, X86::SHRX32rm, 0 },
808 { X86::SHRX64rr, X86::SHRX64rm, 0 },
809 { X86::SHLX32rr, X86::SHLX32rm, 0 },
810 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]811 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
812 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]813 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
814 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
815 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]816 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
817 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]818
819 // AVX-512 foldable instructions
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]820 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
821 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
822 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
823 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
824 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
825 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
826 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
827 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
828 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
829 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
830 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
831 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
832 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
833 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
834 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
835 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
837 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]838
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]839 // AVX-512 foldable instructions (256-bit versions)
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]840 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
841 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
842 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
843 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
844 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
845 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
846 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
847 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
848 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
849 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
850 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
851 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
852 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
853 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]854
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]855 // AVX-512 foldable instructions (128-bit versions)
856 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
857 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
858 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
859 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
860 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
861 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
862 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
863 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
864 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
865 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
866 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
867 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]868 // F16C foldable instructions
869 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
870 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]871
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]872 // AES foldable instructions
873 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
874 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]875 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
876 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]877 };
878
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]879 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]880 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]881 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]882 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]883 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]884 }
885
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]886 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]887 { X86::ADC32rr, X86::ADC32rm, 0 },
888 { X86::ADC64rr, X86::ADC64rm, 0 },
889 { X86::ADD16rr, X86::ADD16rm, 0 },
890 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
891 { X86::ADD32rr, X86::ADD32rm, 0 },
892 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
893 { X86::ADD64rr, X86::ADD64rm, 0 },
894 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
895 { X86::ADD8rr, X86::ADD8rm, 0 },
896 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
897 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
898 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]899 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]900 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]901 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]902 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
903 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
904 { X86::AND16rr, X86::AND16rm, 0 },
905 { X86::AND32rr, X86::AND32rm, 0 },
906 { X86::AND64rr, X86::AND64rm, 0 },
907 { X86::AND8rr, X86::AND8rm, 0 },
908 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
909 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
910 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
911 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]912 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
913 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
914 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
915 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]916 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
917 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
918 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
919 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
920 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
921 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
922 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
923 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
924 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
925 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
926 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
927 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
928 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
929 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
930 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
931 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
932 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
933 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
934 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
935 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
936 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
937 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
938 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
939 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
940 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
941 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
942 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
943 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
944 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
945 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
946 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
947 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
948 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
949 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
950 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
951 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
952 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
953 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
954 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
955 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
956 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
957 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
958 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
959 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
960 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
961 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
962 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
963 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
964 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
965 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
966 { X86::CMPSDrr, X86::CMPSDrm, 0 },
967 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]968 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
969 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]970 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
971 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
972 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]973 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]974 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]975 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
976 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
977 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]978 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
979 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
980 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
981 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
982 { X86::IMUL16rr, X86::IMUL16rm, 0 },
983 { X86::IMUL32rr, X86::IMUL32rm, 0 },
984 { X86::IMUL64rr, X86::IMUL64rm, 0 },
985 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
986 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]987 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
988 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
989 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
990 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
991 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
992 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]993 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]994 { X86::MAXCPDrr, X86::MAXCPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]995 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]996 { X86::MAXCPSrr, X86::MAXCPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]997 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]998 { X86::MAXCSDrr, X86::MAXCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]999 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1000 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1001 { X86::MAXCSSrr, X86::MAXCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1002 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1003 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1004 { X86::MINCPDrr, X86::MINCPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1005 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1006 { X86::MINCPSrr, X86::MINCPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::MINSDrr, X86::MINSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1008 { X86::MINCSDrr, X86::MINCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1009 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1010 { X86::MINSSrr, X86::MINSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1011 { X86::MINCSSrr, X86::MINCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1012 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1013 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1014 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1015 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1016 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1017 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1018 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1019 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1020 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1021 { X86::OR16rr, X86::OR16rm, 0 },
1022 { X86::OR32rr, X86::OR32rm, 0 },
1023 { X86::OR64rr, X86::OR64rm, 0 },
1024 { X86::OR8rr, X86::OR8rm, 0 },
1025 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1026 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1027 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1028 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1029 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1030 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1031 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1032 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1033 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1034 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1035 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1036 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1037 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1038 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1039 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1040 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1041 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1042 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1043 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1044 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1045 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1046 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1047 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1048 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1049 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1050 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1051 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1052 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1053 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1054 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1055 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1056 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1057 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1058 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1059 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1060 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1061 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1062 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1063 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1064 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1065 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1066 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1067 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1068 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1069 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1070 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1071 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1072 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1073 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1074 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1075 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1076 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1077 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1078 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1079 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1080 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1081 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1082 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1083 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1084 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1085 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1086 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1087 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1088 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1089 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1090 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1091 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1092 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1093 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1094 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1095 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1096 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1097 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1098 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1099 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1100 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1101 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1102 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1103 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1104 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1105 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1106 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1107 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1108 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1109 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1110 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1111 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1112 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1113 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1114 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1115 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1116 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1117 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1118 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]1119 { X86::ROUNDSDr_Int, X86::ROUNDSDm_Int, 0 },
1120 { X86::ROUNDSSr_Int, X86::ROUNDSSm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1121 { X86::SBB32rr, X86::SBB32rm, 0 },
1122 { X86::SBB64rr, X86::SBB64rm, 0 },
1123 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1124 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1125 { X86::SUB16rr, X86::SUB16rm, 0 },
1126 { X86::SUB32rr, X86::SUB32rm, 0 },
1127 { X86::SUB64rr, X86::SUB64rm, 0 },
1128 { X86::SUB8rr, X86::SUB8rm, 0 },
1129 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1130 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1131 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1132 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1133 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1134 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1135 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1136 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1137 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1138 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1139 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1140 { X86::XOR16rr, X86::XOR16rm, 0 },
1141 { X86::XOR32rr, X86::XOR32rm, 0 },
1142 { X86::XOR64rr, X86::XOR64rm, 0 },
1143 { X86::XOR8rr, X86::XOR8rm, 0 },
1144 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1145 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1146
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1147 // MMX version of foldable instructions
1148 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1149 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1150 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1151 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1152 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1153 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1154 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1155 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1156 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1157 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1158 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1159 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1160 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1161 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1162 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1163 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1164 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1165 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1166 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1167 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1168 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1169 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1170 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1171 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1172 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1173 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1174 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1175 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1176 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1177 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1178 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1179 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1180 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1181 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1182 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1183 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1184 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1185 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1186 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1187 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1188 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1189 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1190 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1191 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1192 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1193 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1194 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1195 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1196 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1197 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1198 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1199 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1200 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1201 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1202 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1203 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1204 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1205 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1206 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1207 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1208 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1209 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1210 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1211 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1212 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1213 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1214 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1215 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1216 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1217 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1218
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1219 // 3DNow! version of foldable instructions
1220 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1221 { X86::PFACCrr, X86::PFACCrm, 0 },
1222 { X86::PFADDrr, X86::PFADDrm, 0 },
1223 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1224 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1225 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1226 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1227 { X86::PFMINrr, X86::PFMINrm, 0 },
1228 { X86::PFMULrr, X86::PFMULrm, 0 },
1229 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1230 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1231 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1232 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1233 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1234 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1235 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1236 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1237
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1238 // AVX 128-bit versions of foldable instructions
1239 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1240 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1241 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1242 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1243 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1244 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1245 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1246 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1247 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1248 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1249 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1250 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1251 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1252 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1253 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1254 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1255 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1256 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1257 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1258 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1259 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1260 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1261 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1262 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1263 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1264 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1265 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1266 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1267 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1268 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1269 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1270 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1271 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1272 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1273 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1274 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1275 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1276 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1277 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1278 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1279 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1280 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1281 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1282 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1283 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1284 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1285 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1286 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1287 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1288 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1289 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1290 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1291 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1292 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1293 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1294 { X86::VMAXCPDrr, X86::VMAXCPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1295 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1296 { X86::VMAXCPSrr, X86::VMAXCPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1297 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1298 { X86::VMAXCSDrr, X86::VMAXCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1299 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1300 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1301 { X86::VMAXCSSrr, X86::VMAXCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1302 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1303 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1304 { X86::VMINCPDrr, X86::VMINCPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1305 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1306 { X86::VMINCPSrr, X86::VMINCPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1307 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1308 { X86::VMINCSDrr, X86::VMINCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1309 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1310 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1311 { X86::VMINCSSrr, X86::VMINCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1312 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1313 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1314 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1315 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1316 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1317 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1318 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1319 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1320 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1321 { X86::VORPDrr, X86::VORPDrm, 0 },
1322 { X86::VORPSrr, X86::VORPSrm, 0 },
1323 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1324 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1325 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1326 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1327 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1328 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1329 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1330 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1331 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1332 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1333 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1334 { X86::VPADDWrr, X86::VPADDWrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1335 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1336 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1337 { X86::VPANDrr, X86::VPANDrm, 0 },
1338 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1339 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1340 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1341 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1342 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1343 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1344 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1345 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1346 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1347 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1348 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1349 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1350 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1351 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1352 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1353 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1354 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1355 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1356 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1357 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1358 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1359 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1360 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1361 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1362 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1363 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1364 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1365 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1366 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1367 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1368 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1369 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1370 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1371 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1372 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1373 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1374 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1375 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1376 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1377 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1378 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1379 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1380 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1381 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1382 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1383 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1384 { X86::VPORrr, X86::VPORrm, 0 },
1385 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1386 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1387 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1388 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1389 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1390 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1391 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1392 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1393 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1394 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1395 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1396 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1397 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1398 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1399 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1400 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1401 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1402 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1403 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1404 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1405 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1406 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1407 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1408 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1409 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1410 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1411 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1412 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1413 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1414 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1415 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1416 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]1417 { X86::VROUNDSDr_Int, X86::VROUNDSDm_Int, 0 },
1418 { X86::VROUNDSSr_Int, X86::VROUNDSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1419 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1420 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1421 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1422 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1423 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1424 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1425 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1426 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1427 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1428 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1429 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1430 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1431 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1432 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1433
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1434 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1435 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1436 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1437 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1438 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1439 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1440 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1441 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1442 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1443 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1444 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1445 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1446 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1447 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1448 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1449 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1450 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1451 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1452 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1453 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1454 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1455 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1456 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1457 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1458 { X86::VMAXCPDYrr, X86::VMAXCPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1459 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1460 { X86::VMAXCPSYrr, X86::VMAXCPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1461 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1462 { X86::VMINCPDYrr, X86::VMINCPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1463 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1464 { X86::VMINCPSYrr, X86::VMINCPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1465 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1466 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1467 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1468 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1469 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1470 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1471 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1472 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1473 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1474 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1475 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1476 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1477 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1478 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1479 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1480 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1481 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1482
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1483 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1484 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1485 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1486 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1487 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1488 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1489 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1490 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1491 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1492 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1493 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1494 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1495 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1496 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1497 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1498 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1499 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1500 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1501 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1502 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1503 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1504 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1505 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1506 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1507 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1508 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1509 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1510 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1511 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1512 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1513 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1514 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1515 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1516 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1517 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1518 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1519 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1520 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1521 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1522 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1523 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1524 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1525 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1526 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1527 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1528 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1529 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1530 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1531 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1532 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1533 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1534 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1535 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1536 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1537 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1538 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1539 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1540 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1541 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1542 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1543 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1544 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1545 { X86::VPORYrr, X86::VPORYrm, 0 },
1546 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1547 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1548 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1549 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1550 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1551 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1552 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1553 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1554 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1555 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1556 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1557 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1558 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1559 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1560 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1561 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1562 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1563 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1564 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1565 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1566 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1567 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1568 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1569 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1570 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1571 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1572 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1573 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1574 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1575 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1576 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1577 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1578 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1579 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1580 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1581 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1582 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1583 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1584 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1585 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1586
1587 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1588 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1589 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1590 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1591 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1592 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Ymr, TB_ALIGN_NONE },
1593 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1594 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1595 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1596 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1597 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1598 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Ymr, TB_ALIGN_NONE },
1599 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1600 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1601 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1602 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1603 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1604 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Ymr, TB_ALIGN_NONE },
1605 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1606 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1607 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1608 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1609 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1610 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Ymr, TB_ALIGN_NONE },
1611 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1612 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1613 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1614 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Ymr, TB_ALIGN_NONE },
1615 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1616 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1617 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1618 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Ymr, TB_ALIGN_NONE },
1619 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Ymr, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1620
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1621 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1622 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1623 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1624 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1625 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1626 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1627 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1628 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1629 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1630 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1631 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1632 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1633 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1634 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1635 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1636 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1637 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1638 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1639 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1640 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1641 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1642 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1643 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1644 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1645 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1646 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1647 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1648 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1649 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1650 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1651 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1652 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1653 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1654 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1655 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1656 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1657 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1658 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1659 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1660 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1661
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1662 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1663 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1664 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1665 { X86::MULX32rr, X86::MULX32rm, 0 },
1666 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1667 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1668 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1669 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1670 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1671
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1672 // ADX foldable instructions
1673 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1674 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1675 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1676 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1677
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1678 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1679 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1680 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1681 { X86::VADDSSZrr, X86::VADDSSZrm, 0 },
1682 { X86::VADDSSZrr_Int, X86::VADDSSZrm_Int, 0 },
1683 { X86::VADDSDZrr, X86::VADDSDZrm, 0 },
1684 { X86::VADDSDZrr_Int, X86::VADDSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1685 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1686 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1687 { X86::VSUBSSZrr, X86::VSUBSSZrm, 0 },
1688 { X86::VSUBSSZrr_Int, X86::VSUBSSZrm_Int, 0 },
1689 { X86::VSUBSDZrr, X86::VSUBSDZrm, 0 },
1690 { X86::VSUBSDZrr_Int, X86::VSUBSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1691 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1692 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1693 { X86::VMULSSZrr, X86::VMULSSZrm, 0 },
1694 { X86::VMULSSZrr_Int, X86::VMULSSZrm_Int, 0 },
1695 { X86::VMULSDZrr, X86::VMULSDZrm, 0 },
1696 { X86::VMULSDZrr_Int, X86::VMULSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1697 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1698 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1699 { X86::VDIVSSZrr, X86::VDIVSSZrm, 0 },
1700 { X86::VDIVSSZrr_Int, X86::VDIVSSZrm_Int, 0 },
1701 { X86::VDIVSDZrr, X86::VDIVSDZrm, 0 },
1702 { X86::VDIVSDZrr_Int, X86::VDIVSDZrm_Int, 0 },
Craig Topper4891c722016-08-27 05:22:08 +0000[diff] [blame^]1703 { X86::VCMPPDZrri, X86::VCMPPDZrmi, 0 },
1704 { X86::VCMPPSZrri, X86::VCMPPSZrmi, 0 },
1705 { X86::VCMPSDZrr, X86::VCMPSDZrm, 0 },
1706 { X86::VCMPSSZrr, X86::VCMPSSZrm, 0 },
Craig Topper8f27f512016-08-26 07:08:00 +0000[diff] [blame]1707 { X86::VCMPSDZrr_Int, X86::VCMPSDZrm_Int, 0 },
1708 { X86::VCMPSSZrr_Int, X86::VCMPSSZrm_Int, 0 },
Craig Topper2c51c742016-08-07 17:14:09 +0000[diff] [blame]1709 { X86::VANDPDZrr, X86::VANDPDZrm, 0 },
1710 { X86::VANDPSZrr, X86::VANDPSZrm, 0 },
1711 { X86::VANDNPDZrr, X86::VANDNPDZrm, 0 },
1712 { X86::VANDNPSZrr, X86::VANDNPSZrm, 0 },
1713 { X86::VORPDZrr, X86::VORPDZrm, 0 },
1714 { X86::VORPSZrr, X86::VORPSZrm, 0 },
1715 { X86::VXORPDZrr, X86::VXORPDZrm, 0 },
1716 { X86::VXORPSZrr, X86::VXORPSZrm, 0 },
1717 { X86::VPANDDZrr, X86::VPANDDZrm, 0 },
1718 { X86::VPANDQZrr, X86::VPANDQZrm, 0 },
1719 { X86::VPANDNDZrr, X86::VPANDNDZrm, 0 },
1720 { X86::VPANDNQZrr, X86::VPANDNQZrm, 0 },
1721 { X86::VPORDZrr, X86::VPORDZrm, 0 },
1722 { X86::VPORQZrr, X86::VPORQZrm, 0 },
1723 { X86::VPXORDZrr, X86::VPXORDZrm, 0 },
1724 { X86::VPXORQZrr, X86::VPXORQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1725 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Craig Topper938e7ab2016-08-07 17:14:05 +0000[diff] [blame]1726 { X86::VMAXCPDZrr, X86::VMAXCPDZrm, 0 },
1727 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1728 { X86::VMAXCPSZrr, X86::VMAXCPSZrm, 0 },
1729 { X86::VMAXSDZrr, X86::VMAXSDZrm, 0 },
1730 { X86::VMAXCSDZrr, X86::VMAXCSDZrm, 0 },
1731 { X86::VMAXSDZrr_Int, X86::VMAXSDZrm_Int, 0 },
1732 { X86::VMAXSSZrr, X86::VMAXSSZrm, 0 },
1733 { X86::VMAXCSSZrr, X86::VMAXCSSZrm, 0 },
1734 { X86::VMAXSSZrr_Int, X86::VMAXSSZrm_Int, 0 },
1735 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1736 { X86::VMINCPDZrr, X86::VMINCPDZrm, 0 },
1737 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1738 { X86::VMINCPSZrr, X86::VMINCPSZrm, 0 },
1739 { X86::VMINSDZrr, X86::VMINSDZrm, 0 },
1740 { X86::VMINCSDZrr, X86::VMINCSDZrm, 0 },
1741 { X86::VMINSDZrr_Int, X86::VMINSDZrm_Int, 0 },
1742 { X86::VMINSSZrr, X86::VMINSSZrm, 0 },
1743 { X86::VMINCSSZrr, X86::VMINCSSZrm, 0 },
1744 { X86::VMINSSZrr_Int, X86::VMINSSZrm_Int, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1745 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1746 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1747 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1748 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1749 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1750 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1751 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1752 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1753 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1754 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1755 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1756 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1757 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1758 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1759 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1760 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1761 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1762 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1763 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1764 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1765 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1766 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1767 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1768 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1769 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1770 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1771 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1772
1773 // AVX-512{F,VL} foldable instructions
1774 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1775 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1776 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1777
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1778 // AVX-512{F,VL} foldable instructions
1779 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1780 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1781 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1782 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
Craig Topper0b907562016-07-22 05:00:39 +0000[diff] [blame]1783 { X86::VANDPDZ128rr, X86::VANDPDZ128rm, 0 },
1784 { X86::VANDPDZ256rr, X86::VANDPDZ256rm, 0 },
1785 { X86::VANDPSZ128rr, X86::VANDPSZ128rm, 0 },
1786 { X86::VANDPSZ256rr, X86::VANDPSZ256rm, 0 },
1787 { X86::VANDNPDZ128rr, X86::VANDNPDZ128rm, 0 },
1788 { X86::VANDNPDZ256rr, X86::VANDNPDZ256rm, 0 },
1789 { X86::VANDNPSZ128rr, X86::VANDNPSZ128rm, 0 },
1790 { X86::VANDNPSZ256rr, X86::VANDNPSZ256rm, 0 },
1791 { X86::VORPDZ128rr, X86::VORPDZ128rm, 0 },
1792 { X86::VORPDZ256rr, X86::VORPDZ256rm, 0 },
1793 { X86::VORPSZ128rr, X86::VORPSZ128rm, 0 },
1794 { X86::VORPSZ256rr, X86::VORPSZ256rm, 0 },
1795 { X86::VPANDDZ128rr, X86::VPANDDZ128rm, 0 },
1796 { X86::VPANDDZ256rr, X86::VPANDDZ256rm, 0 },
1797 { X86::VPANDQZ128rr, X86::VPANDQZ128rm, 0 },
1798 { X86::VPANDQZ256rr, X86::VPANDQZ256rm, 0 },
1799 { X86::VPANDNDZ128rr, X86::VPANDNDZ128rm, 0 },
1800 { X86::VPANDNDZ256rr, X86::VPANDNDZ256rm, 0 },
1801 { X86::VPANDNQZ128rr, X86::VPANDNQZ128rm, 0 },
1802 { X86::VPANDNQZ256rr, X86::VPANDNQZ256rm, 0 },
1803 { X86::VPORDZ128rr, X86::VPORDZ128rm, 0 },
1804 { X86::VPORDZ256rr, X86::VPORDZ256rm, 0 },
1805 { X86::VPORQZ128rr, X86::VPORQZ128rm, 0 },
1806 { X86::VPORQZ256rr, X86::VPORQZ256rm, 0 },
1807 { X86::VPXORDZ128rr, X86::VPXORDZ128rm, 0 },
1808 { X86::VPXORDZ256rr, X86::VPXORDZ256rm, 0 },
1809 { X86::VPXORQZ128rr, X86::VPXORQZ128rm, 0 },
1810 { X86::VPXORQZ256rr, X86::VPXORQZ256rm, 0 },
1811 { X86::VSUBPDZ128rr, X86::VSUBPDZ128rm, 0 },
1812 { X86::VSUBPDZ256rr, X86::VSUBPDZ256rm, 0 },
1813 { X86::VSUBPSZ128rr, X86::VSUBPSZ128rm, 0 },
1814 { X86::VSUBPSZ256rr, X86::VSUBPSZ256rm, 0 },
1815 { X86::VXORPDZ128rr, X86::VXORPDZ128rm, 0 },
1816 { X86::VXORPDZ256rr, X86::VXORPDZ256rm, 0 },
1817 { X86::VXORPSZ128rr, X86::VXORPSZ128rm, 0 },
1818 { X86::VXORPSZ256rr, X86::VXORPSZ256rm, 0 },
Craig Topper938e7ab2016-08-07 17:14:05 +0000[diff] [blame]1819 { X86::VMAXPDZ128rr, X86::VMAXPDZ128rm, 0 },
1820 { X86::VMAXPDZ256rr, X86::VMAXPDZ256rm, 0 },
1821 { X86::VMAXCPDZ128rr, X86::VMAXCPDZ128rm, 0 },
1822 { X86::VMAXCPDZ256rr, X86::VMAXCPDZ256rm, 0 },
1823 { X86::VMAXPSZ128rr, X86::VMAXPSZ128rm, 0 },
1824 { X86::VMAXPSZ256rr, X86::VMAXPSZ256rm, 0 },
1825 { X86::VMAXCPSZ128rr, X86::VMAXCPSZ128rm, 0 },
1826 { X86::VMAXCPSZ256rr, X86::VMAXCPSZ256rm, 0 },
1827 { X86::VMINPDZ128rr, X86::VMINPDZ128rm, 0 },
1828 { X86::VMINPDZ256rr, X86::VMINPDZ256rm, 0 },
1829 { X86::VMINCPDZ128rr, X86::VMINCPDZ128rm, 0 },
1830 { X86::VMINCPDZ256rr, X86::VMINCPDZ256rm, 0 },
1831 { X86::VMINPSZ128rr, X86::VMINPSZ128rm, 0 },
1832 { X86::VMINPSZ256rr, X86::VMINPSZ256rm, 0 },
1833 { X86::VMINCPSZ128rr, X86::VMINCPSZ128rm, 0 },
1834 { X86::VMINCPSZ256rr, X86::VMINCPSZ256rm, 0 },
Craig Topper4891c722016-08-27 05:22:08 +0000[diff] [blame^]1835 { X86::VCMPPDZ128rri, X86::VCMPPDZ128rmi, 0 },
1836 { X86::VCMPPDZ256rri, X86::VCMPPDZ256rmi, 0 },
1837 { X86::VCMPPSZ128rri, X86::VCMPPSZ128rmi, 0 },
1838 { X86::VCMPPSZ256rri, X86::VCMPPSZ256rmi, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1839
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1840 // AES foldable instructions
1841 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1842 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1843 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1844 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1845 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1846 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1847 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1848 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1849
1850 // SHA foldable instructions
1851 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1852 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1853 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1854 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1855 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1856 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1857 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1858 };
1859
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1860 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1861 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1862 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1863 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1864 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1865 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1866
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1867 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1868 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1869 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1870 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1871 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1872 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1873 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Yrm, TB_ALIGN_NONE },
1874 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1875 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1876 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1877 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1878 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1879 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Yrm, TB_ALIGN_NONE },
1880 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1881 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1882 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1883 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1884 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1885 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Yrm, TB_ALIGN_NONE },
1886 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1887 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1888 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1889 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1890 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1891 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Yrm, TB_ALIGN_NONE },
1892 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1893 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1894 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1895 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Yrm, TB_ALIGN_NONE },
1896 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1897 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1898 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1899 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Yrm, TB_ALIGN_NONE },
1900 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1901
1902 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1903 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
1904 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1905 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1906 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1907 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1908 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1909 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1910
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1911 // AVX-512 VPERMI instructions with 3 source operands.
1912 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1913 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1914 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1915 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1916 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1917 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1918 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1919 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1920 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1921 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1922 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1923 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1924 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1925 // AVX-512 arithmetic instructions
1926 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1927 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1928 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1929 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1930 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1931 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1932 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1933 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1934 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1935 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]1936 { X86::VMINCPSZrrkz, X86::VMINCPSZrmkz, 0 },
1937 { X86::VMINCPDZrrkz, X86::VMINCPDZrmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1938 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1939 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]1940 { X86::VMAXCPSZrrkz, X86::VMAXCPSZrmkz, 0 },
1941 { X86::VMAXCPDZrrkz, X86::VMAXCPDZrmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]1942 { X86::VANDPDZrrkz, X86::VANDPDZrmkz, 0 },
1943 { X86::VANDPSZrrkz, X86::VANDPSZrmkz, 0 },
1944 { X86::VANDNPDZrrkz, X86::VANDNPDZrmkz, 0 },
1945 { X86::VANDNPSZrrkz, X86::VANDNPSZrmkz, 0 },
1946 { X86::VORPDZrrkz, X86::VORPDZrmkz, 0 },
1947 { X86::VORPSZrrkz, X86::VORPSZrmkz, 0 },
1948 { X86::VXORPDZrrkz, X86::VXORPDZrmkz, 0 },
1949 { X86::VXORPSZrrkz, X86::VXORPSZrmkz, 0 },
1950 { X86::VPANDDZrrkz, X86::VPANDDZrmkz, 0 },
1951 { X86::VPANDQZrrkz, X86::VPANDQZrmkz, 0 },
1952 { X86::VPANDNDZrrkz, X86::VPANDNDZrmkz, 0 },
1953 { X86::VPANDNQZrrkz, X86::VPANDNQZrmkz, 0 },
1954 { X86::VPORDZrrkz, X86::VPORDZrmkz, 0 },
1955 { X86::VPORQZrrkz, X86::VPORQZrmkz, 0 },
1956 { X86::VPXORDZrrkz, X86::VPXORDZrmkz, 0 },
1957 { X86::VPXORQZrrkz, X86::VPXORQZrmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1958 // AVX-512{F,VL} arithmetic instructions 256-bit
1959 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1960 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1961 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1962 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1963 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1964 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1965 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1966 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1967 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1968 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]1969 { X86::VMINCPSZ256rrkz, X86::VMINCPSZ256rmkz, 0 },
1970 { X86::VMINCPDZ256rrkz, X86::VMINCPDZ256rmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1971 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1972 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]1973 { X86::VMAXCPSZ256rrkz, X86::VMAXCPSZ256rmkz, 0 },
1974 { X86::VMAXCPDZ256rrkz, X86::VMAXCPDZ256rmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]1975 { X86::VANDPDZ256rrkz, X86::VANDPDZ256rmkz, 0 },
1976 { X86::VANDPSZ256rrkz, X86::VANDPSZ256rmkz, 0 },
1977 { X86::VANDNPDZ256rrkz, X86::VANDNPDZ256rmkz, 0 },
1978 { X86::VANDNPSZ256rrkz, X86::VANDNPSZ256rmkz, 0 },
1979 { X86::VORPDZ256rrkz, X86::VORPDZ256rmkz, 0 },
1980 { X86::VORPSZ256rrkz, X86::VORPSZ256rmkz, 0 },
1981 { X86::VXORPDZ256rrkz, X86::VXORPDZ256rmkz, 0 },
1982 { X86::VXORPSZ256rrkz, X86::VXORPSZ256rmkz, 0 },
1983 { X86::VPANDDZ256rrkz, X86::VPANDDZ256rmkz, 0 },
1984 { X86::VPANDQZ256rrkz, X86::VPANDQZ256rmkz, 0 },
1985 { X86::VPANDNDZ256rrkz, X86::VPANDNDZ256rmkz, 0 },
1986 { X86::VPANDNQZ256rrkz, X86::VPANDNQZ256rmkz, 0 },
1987 { X86::VPORDZ256rrkz, X86::VPORDZ256rmkz, 0 },
1988 { X86::VPORQZ256rrkz, X86::VPORQZ256rmkz, 0 },
1989 { X86::VPXORDZ256rrkz, X86::VPXORDZ256rmkz, 0 },
1990 { X86::VPXORQZ256rrkz, X86::VPXORQZ256rmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1991 // AVX-512{F,VL} arithmetic instructions 128-bit
1992 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1993 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1994 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1995 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1996 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1997 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1998 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1999 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
2000 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
2001 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2002 { X86::VMINCPSZ128rrkz, X86::VMINCPSZ128rmkz, 0 },
2003 { X86::VMINCPDZ128rrkz, X86::VMINCPDZ128rmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2004 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2005 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2006 { X86::VMAXCPSZ128rrkz, X86::VMAXCPSZ128rmkz, 0 },
2007 { X86::VMAXCPDZ128rrkz, X86::VMAXCPDZ128rmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2008 { X86::VANDPDZ128rrkz, X86::VANDPDZ128rmkz, 0 },
2009 { X86::VANDPSZ128rrkz, X86::VANDPSZ128rmkz, 0 },
2010 { X86::VANDNPDZ128rrkz, X86::VANDNPDZ128rmkz, 0 },
2011 { X86::VANDNPSZ128rrkz, X86::VANDNPSZ128rmkz, 0 },
2012 { X86::VORPDZ128rrkz, X86::VORPDZ128rmkz, 0 },
2013 { X86::VORPSZ128rrkz, X86::VORPSZ128rmkz, 0 },
2014 { X86::VXORPDZ128rrkz, X86::VXORPDZ128rmkz, 0 },
2015 { X86::VXORPSZ128rrkz, X86::VXORPSZ128rmkz, 0 },
2016 { X86::VPANDDZ128rrkz, X86::VPANDDZ128rmkz, 0 },
2017 { X86::VPANDQZ128rrkz, X86::VPANDQZ128rmkz, 0 },
2018 { X86::VPANDNDZ128rrkz, X86::VPANDNDZ128rmkz, 0 },
2019 { X86::VPANDNQZ128rrkz, X86::VPANDNQZ128rmkz, 0 },
2020 { X86::VPORDZ128rrkz, X86::VPORDZ128rmkz, 0 },
2021 { X86::VPORQZ128rrkz, X86::VPORQZ128rmkz, 0 },
2022 { X86::VPXORDZ128rrkz, X86::VPXORDZ128rmkz, 0 },
2023 { X86::VPXORQZ128rrkz, X86::VPXORQZ128rmkz, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2024 };
2025
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2026 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2027 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2028 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2029 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2030 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2031 }
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]2032 auto I = X86InstrFMA3Info::rm_begin();
2033 auto E = X86InstrFMA3Info::rm_end();
2034 for (; I != E; ++I)
2035 if (!I.getGroup()->isKMasked())
2036 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2037 I.getRegOpcode(), I.getMemOpcode(),
2038 TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2039
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]2040 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2041 // AVX-512 foldable instructions
2042 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
2043 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
2044 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2045 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2046 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2047 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2048 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2049 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2050 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2051 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2052 { X86::VMINCPSZrrk, X86::VMINCPSZrmk, 0 },
2053 { X86::VMINCPDZrrk, X86::VMINCPDZrmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2054 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2055 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2056 { X86::VMAXCPSZrrk, X86::VMAXCPSZrmk, 0 },
2057 { X86::VMAXCPDZrrk, X86::VMAXCPDZrmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2058 { X86::VANDPDZrrk, X86::VANDPDZrmk, 0 },
2059 { X86::VANDPSZrrk, X86::VANDPSZrmk, 0 },
2060 { X86::VANDNPDZrrk, X86::VANDNPDZrmk, 0 },
2061 { X86::VANDNPSZrrk, X86::VANDNPSZrmk, 0 },
2062 { X86::VORPDZrrk, X86::VORPDZrmk, 0 },
2063 { X86::VORPSZrrk, X86::VORPSZrmk, 0 },
2064 { X86::VXORPDZrrk, X86::VXORPDZrmk, 0 },
2065 { X86::VXORPSZrrk, X86::VXORPSZrmk, 0 },
2066 { X86::VPANDDZrrk, X86::VPANDDZrmk, 0 },
2067 { X86::VPANDQZrrk, X86::VPANDQZrmk, 0 },
2068 { X86::VPANDNDZrrk, X86::VPANDNDZrmk, 0 },
2069 { X86::VPANDNQZrrk, X86::VPANDNQZrmk, 0 },
2070 { X86::VPORDZrrk, X86::VPORDZrmk, 0 },
2071 { X86::VPORQZrrk, X86::VPORQZrmk, 0 },
2072 { X86::VPXORDZrrk, X86::VPXORDZrmk, 0 },
2073 { X86::VPXORQZrrk, X86::VPXORQZrmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2074 // AVX-512{F,VL} foldable instructions 256-bit
2075 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2076 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2077 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2078 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2079 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2080 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2081 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2082 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2083 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2084 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2085 { X86::VMINCPSZ256rrk, X86::VMINCPSZ256rmk, 0 },
2086 { X86::VMINCPDZ256rrk, X86::VMINCPDZ256rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2087 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2088 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2089 { X86::VMAXCPSZ256rrk, X86::VMAXCPSZ256rmk, 0 },
2090 { X86::VMAXCPDZ256rrk, X86::VMAXCPDZ256rmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2091 { X86::VANDPDZ256rrk, X86::VANDPDZ256rmk, 0 },
2092 { X86::VANDPSZ256rrk, X86::VANDPSZ256rmk, 0 },
2093 { X86::VANDNPDZ256rrk, X86::VANDNPDZ256rmk, 0 },
2094 { X86::VANDNPSZ256rrk, X86::VANDNPSZ256rmk, 0 },
2095 { X86::VORPDZ256rrk, X86::VORPDZ256rmk, 0 },
2096 { X86::VORPSZ256rrk, X86::VORPSZ256rmk, 0 },
2097 { X86::VXORPDZ256rrk, X86::VXORPDZ256rmk, 0 },
2098 { X86::VXORPSZ256rrk, X86::VXORPSZ256rmk, 0 },
2099 { X86::VPANDDZ256rrk, X86::VPANDDZ256rmk, 0 },
2100 { X86::VPANDQZ256rrk, X86::VPANDQZ256rmk, 0 },
2101 { X86::VPANDNDZ256rrk, X86::VPANDNDZ256rmk, 0 },
2102 { X86::VPANDNQZ256rrk, X86::VPANDNQZ256rmk, 0 },
2103 { X86::VPORDZ256rrk, X86::VPORDZ256rmk, 0 },
2104 { X86::VPORQZ256rrk, X86::VPORQZ256rmk, 0 },
2105 { X86::VPXORDZ256rrk, X86::VPXORDZ256rmk, 0 },
2106 { X86::VPXORQZ256rrk, X86::VPXORQZ256rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2107 // AVX-512{F,VL} foldable instructions 128-bit
2108 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2109 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2110 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2111 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2112 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2113 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2114 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2115 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2116 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2117 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2118 { X86::VMINCPSZ128rrk, X86::VMINCPSZ128rmk, 0 },
2119 { X86::VMINCPDZ128rrk, X86::VMINCPDZ128rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2120 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2121 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2122 { X86::VMAXCPSZ128rrk, X86::VMAXCPSZ128rmk, 0 },
2123 { X86::VMAXCPDZ128rrk, X86::VMAXCPDZ128rmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2124 { X86::VANDPDZ128rrk, X86::VANDPDZ128rmk, 0 },
2125 { X86::VANDPSZ128rrk, X86::VANDPSZ128rmk, 0 },
2126 { X86::VANDNPDZ128rrk, X86::VANDNPDZ128rmk, 0 },
2127 { X86::VANDNPSZ128rrk, X86::VANDNPSZ128rmk, 0 },
2128 { X86::VORPDZ128rrk, X86::VORPDZ128rmk, 0 },
2129 { X86::VORPSZ128rrk, X86::VORPSZ128rmk, 0 },
2130 { X86::VXORPDZ128rrk, X86::VXORPDZ128rmk, 0 },
2131 { X86::VXORPSZ128rrk, X86::VXORPSZ128rmk, 0 },
2132 { X86::VPANDDZ128rrk, X86::VPANDDZ128rmk, 0 },
2133 { X86::VPANDQZ128rrk, X86::VPANDQZ128rmk, 0 },
2134 { X86::VPANDNDZ128rrk, X86::VPANDNDZ128rmk, 0 },
2135 { X86::VPANDNQZ128rrk, X86::VPANDNQZ128rmk, 0 },
2136 { X86::VPORDZ128rrk, X86::VPORDZ128rmk, 0 },
2137 { X86::VPORQZ128rrk, X86::VPORQZ128rmk, 0 },
2138 { X86::VPXORDZ128rrk, X86::VPXORDZ128rmk, 0 },
2139 { X86::VPXORQZ128rrk, X86::VPXORQZ128rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2140 };
2141
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2142 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2143 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2144 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2145 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2146 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2147 }
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]2148 for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I)
2149 if (I.getGroup()->isKMasked())
2150 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2151 I.getRegOpcode(), I.getMemOpcode(),
2152 TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2153}
2154
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2155void
2156X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2157 MemOp2RegOpTableType &M2RTable,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]2158 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
Craig Topper969e56a2016-08-25 04:16:08 +0000[diff] [blame]2159 if ((Flags & TB_NO_FORWARD) == 0) {
2160 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2161 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2162 }
2163 if ((Flags & TB_NO_REVERSE) == 0) {
2164 assert(!M2RTable.count(MemOp) &&
2165 "Duplicated entries in unfolding maps?");
2166 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2167 }
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2168}
2169
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2170bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2171X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2172 unsigned &SrcReg, unsigned &DstReg,
2173 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2174 switch (MI.getOpcode()) {
2175 default: break;
2176 case X86::MOVSX16rr8:
2177 case X86::MOVZX16rr8:
2178 case X86::MOVSX32rr8:
2179 case X86::MOVZX32rr8:
2180 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2181 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2182 // It's not always legal to reference the low 8-bit of the larger
2183 // register in 32-bit mode.
2184 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2185 case X86::MOVSX32rr16:
2186 case X86::MOVZX32rr16:
2187 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2188 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2189 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2190 // Be conservative.
2191 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2192 SrcReg = MI.getOperand(1).getReg();
2193 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2194 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2195 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2196 case X86::MOVSX16rr8:
2197 case X86::MOVZX16rr8:
2198 case X86::MOVSX32rr8:
2199 case X86::MOVZX32rr8:
2200 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2201 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2202 break;
2203 case X86::MOVSX32rr16:
2204 case X86::MOVZX32rr16:
2205 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2206 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2207 break;
2208 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2209 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2210 break;
2211 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2212 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2213 }
2214 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2215 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2216}
2217
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2218int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2219 const MachineFunction *MF = MI.getParent()->getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2220 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2221
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2222 if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2223 MI.getOpcode() == getCallFrameDestroyOpcode()) {
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2224 unsigned StackAlign = TFI->getStackAlignment();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2225 int SPAdj =
2226 (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2227
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2228 SPAdj -= MI.getOperand(1).getImm();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2229
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2230 if (MI.getOpcode() == getCallFrameSetupOpcode())
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2231 return SPAdj;
2232 else
2233 return -SPAdj;
2234 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2235
2236 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2237 // that is bound to the following ADJCALLSTACKUP pseudo.
2238 // Look for the next ADJCALLSTACKUP that follows the call.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2239 if (MI.isCall()) {
2240 const MachineBasicBlock *MBB = MI.getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2241 auto I = ++MachineBasicBlock::const_iterator(MI);
2242 for (auto E = MBB->end(); I != E; ++I) {
2243 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2244 I->isCall())
2245 break;
2246 }
2247
2248 // If we could not find a frame destroy opcode, then it has already
2249 // been simplified, so we don't care.
2250 if (I->getOpcode() != getCallFrameDestroyOpcode())
2251 return 0;
2252
2253 return -(I->getOperand(1).getImm());
2254 }
2255
2256 // Currently handle only PUSHes we can reasonably expect to see
2257 // in call sequences
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2258 switch (MI.getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2259 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2260 return 0;
2261 case X86::PUSH32i8:
2262 case X86::PUSH32r:
2263 case X86::PUSH32rmm:
2264 case X86::PUSH32rmr:
2265 case X86::PUSHi32:
2266 return 4;
David L Kreitzer0fe46322016-05-02 13:45:25 +0000[diff] [blame]2267 case X86::PUSH64i8:
2268 case X86::PUSH64r:
2269 case X86::PUSH64rmm:
2270 case X86::PUSH64rmr:
2271 case X86::PUSH64i32:
2272 return 8;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2273 }
2274}
2275
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2276/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2277/// operand and follow operands form a reference to the stack frame.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2278bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2279 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2280 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2281 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2282 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2283 MI.getOperand(Op + X86::AddrDisp).isImm() &&
2284 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2285 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2286 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2287 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2288 return true;
2289 }
2290 return false;
2291}
2292
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2293static bool isFrameLoadOpcode(int Opcode) {
2294 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2295 default:
2296 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2297 case X86::MOV8rm:
2298 case X86::MOV16rm:
2299 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2300 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2301 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2302 case X86::MOVSSrm:
2303 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2304 case X86::MOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2305 case X86::MOVUPSrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2306 case X86::MOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2307 case X86::MOVUPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2308 case X86::MOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2309 case X86::MOVDQUrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2310 case X86::VMOVSSrm:
2311 case X86::VMOVSDrm:
2312 case X86::VMOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2313 case X86::VMOVUPSrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2314 case X86::VMOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2315 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2316 case X86::VMOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2317 case X86::VMOVDQUrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2318 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2319 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2320 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2321 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2322 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2323 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2324 case X86::MMX_MOVD64rm:
2325 case X86::MMX_MOVQ64rm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2326 case X86::VMOVSSZrm:
2327 case X86::VMOVSDZrm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2328 case X86::VMOVAPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2329 case X86::VMOVAPSZ128rm:
2330 case X86::VMOVAPSZ256rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2331 case X86::VMOVUPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2332 case X86::VMOVUPSZ128rm:
2333 case X86::VMOVUPSZ256rm:
2334 case X86::VMOVAPDZrm:
2335 case X86::VMOVAPDZ128rm:
2336 case X86::VMOVAPDZ256rm:
2337 case X86::VMOVUPDZrm:
2338 case X86::VMOVUPDZ128rm:
2339 case X86::VMOVUPDZ256rm:
2340 case X86::VMOVDQA32Zrm:
2341 case X86::VMOVDQA32Z128rm:
2342 case X86::VMOVDQA32Z256rm:
2343 case X86::VMOVDQU32Zrm:
2344 case X86::VMOVDQU32Z128rm:
2345 case X86::VMOVDQU32Z256rm:
2346 case X86::VMOVDQA64Zrm:
2347 case X86::VMOVDQA64Z128rm:
2348 case X86::VMOVDQA64Z256rm:
2349 case X86::VMOVDQU64Zrm:
2350 case X86::VMOVDQU64Z128rm:
2351 case X86::VMOVDQU64Z256rm:
2352 case X86::VMOVDQU8Zrm:
2353 case X86::VMOVDQU8Z128rm:
2354 case X86::VMOVDQU8Z256rm:
2355 case X86::VMOVDQU16Zrm:
2356 case X86::VMOVDQU16Z128rm:
2357 case X86::VMOVDQU16Z256rm:
2358 case X86::KMOVBkm:
2359 case X86::KMOVWkm:
2360 case X86::KMOVDkm:
2361 case X86::KMOVQkm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2362 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2363 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2364}
2365
2366static bool isFrameStoreOpcode(int Opcode) {
2367 switch (Opcode) {
2368 default: break;
2369 case X86::MOV8mr:
2370 case X86::MOV16mr:
2371 case X86::MOV32mr:
2372 case X86::MOV64mr:
2373 case X86::ST_FpP64m:
2374 case X86::MOVSSmr:
2375 case X86::MOVSDmr:
2376 case X86::MOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2377 case X86::MOVUPSmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2378 case X86::MOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2379 case X86::MOVUPDmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2380 case X86::MOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2381 case X86::MOVDQUmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2382 case X86::VMOVSSmr:
2383 case X86::VMOVSDmr:
2384 case X86::VMOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2385 case X86::VMOVUPSmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2386 case X86::VMOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2387 case X86::VMOVUPDmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2388 case X86::VMOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2389 case X86::VMOVDQUmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2390 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2391 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2392 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2393 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2394 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2395 case X86::VMOVDQAYmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2396 case X86::VMOVSSZmr:
2397 case X86::VMOVSDZmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2398 case X86::VMOVUPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2399 case X86::VMOVUPSZ128mr:
2400 case X86::VMOVUPSZ256mr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2401 case X86::VMOVAPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2402 case X86::VMOVAPSZ128mr:
2403 case X86::VMOVAPSZ256mr:
2404 case X86::VMOVUPDZmr:
2405 case X86::VMOVUPDZ128mr:
2406 case X86::VMOVUPDZ256mr:
2407 case X86::VMOVAPDZmr:
2408 case X86::VMOVAPDZ128mr:
2409 case X86::VMOVAPDZ256mr:
2410 case X86::VMOVDQA32Zmr:
2411 case X86::VMOVDQA32Z128mr:
2412 case X86::VMOVDQA32Z256mr:
2413 case X86::VMOVDQU32Zmr:
2414 case X86::VMOVDQU32Z128mr:
2415 case X86::VMOVDQU32Z256mr:
2416 case X86::VMOVDQA64Zmr:
2417 case X86::VMOVDQA64Z128mr:
2418 case X86::VMOVDQA64Z256mr:
2419 case X86::VMOVDQU64Zmr:
2420 case X86::VMOVDQU64Z128mr:
2421 case X86::VMOVDQU64Z256mr:
2422 case X86::VMOVDQU8Zmr:
2423 case X86::VMOVDQU8Z128mr:
2424 case X86::VMOVDQU8Z256mr:
2425 case X86::VMOVDQU16Zmr:
2426 case X86::VMOVDQU16Z128mr:
2427 case X86::VMOVDQU16Z256mr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2428 case X86::MMX_MOVD64mr:
2429 case X86::MMX_MOVQ64mr:
2430 case X86::MMX_MOVNTQmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2431 case X86::KMOVBmk:
2432 case X86::KMOVWmk:
2433 case X86::KMOVDmk:
2434 case X86::KMOVQmk:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2435 return true;
2436 }
2437 return false;
2438}
2439
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2440unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2441 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2442 if (isFrameLoadOpcode(MI.getOpcode()))
2443 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2444 return MI.getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2445 return 0;
2446}
2447
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2448unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2449 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2450 if (isFrameLoadOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2451 unsigned Reg;
2452 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2453 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2454 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2455 const MachineMemOperand *Dummy;
2456 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2457 }
2458 return 0;
2459}
2460
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2461unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2462 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2463 if (isFrameStoreOpcode(MI.getOpcode()))
2464 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2465 isFrameOperand(MI, 0, FrameIndex))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2466 return MI.getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2467 return 0;
2468}
2469
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2470unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2471 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2472 if (isFrameStoreOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2473 unsigned Reg;
2474 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2475 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2476 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2477 const MachineMemOperand *Dummy;
2478 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2479 }
2480 return 0;
2481}
2482
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2483/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2484static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2485 // Don't waste compile time scanning use-def chains of physregs.
2486 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2487 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2488 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2489 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2490 E = MRI.def_instr_end(); I != E; ++I) {
2491 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2492 if (DefMI->getOpcode() != X86::MOVPC32r)
2493 return false;
2494 assert(!isPICBase && "More than one PIC base?");
2495 isPICBase = true;
2496 }
2497 return isPICBase;
2498}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2499
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2500bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2501 AliasAnalysis *AA) const {
2502 switch (MI.getOpcode()) {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2503 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2504 case X86::MOV8rm:
2505 case X86::MOV16rm:
2506 case X86::MOV32rm:
2507 case X86::MOV64rm:
2508 case X86::LD_Fp64m:
2509 case X86::MOVSSrm:
2510 case X86::MOVSDrm:
2511 case X86::MOVAPSrm:
2512 case X86::MOVUPSrm:
2513 case X86::MOVAPDrm:
2514 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2515 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2516 case X86::VMOVSSrm:
2517 case X86::VMOVSDrm:
2518 case X86::VMOVAPSrm:
2519 case X86::VMOVUPSrm:
2520 case X86::VMOVAPDrm:
2521 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2522 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2523 case X86::VMOVAPSYrm:
2524 case X86::VMOVUPSYrm:
2525 case X86::VMOVAPDYrm:
2526 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2527 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2528 case X86::MMX_MOVD64rm:
2529 case X86::MMX_MOVQ64rm:
2530 case X86::FsVMOVAPSrm:
2531 case X86::FsVMOVAPDrm:
2532 case X86::FsMOVAPSrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2533 case X86::FsMOVAPDrm:
2534 // AVX-512
Craig Toppere4f868e2016-07-29 06:06:04 +0000[diff] [blame]2535 case X86::VMOVSSZrm:
2536 case X86::VMOVSDZrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2537 case X86::VMOVAPDZ128rm:
2538 case X86::VMOVAPDZ256rm:
2539 case X86::VMOVAPDZrm:
2540 case X86::VMOVAPSZ128rm:
2541 case X86::VMOVAPSZ256rm:
2542 case X86::VMOVAPSZrm:
2543 case X86::VMOVDQA32Z128rm:
2544 case X86::VMOVDQA32Z256rm:
2545 case X86::VMOVDQA32Zrm:
2546 case X86::VMOVDQA64Z128rm:
2547 case X86::VMOVDQA64Z256rm:
2548 case X86::VMOVDQA64Zrm:
2549 case X86::VMOVDQU16Z128rm:
2550 case X86::VMOVDQU16Z256rm:
2551 case X86::VMOVDQU16Zrm:
2552 case X86::VMOVDQU32Z128rm:
2553 case X86::VMOVDQU32Z256rm:
2554 case X86::VMOVDQU32Zrm:
2555 case X86::VMOVDQU64Z128rm:
2556 case X86::VMOVDQU64Z256rm:
2557 case X86::VMOVDQU64Zrm:
2558 case X86::VMOVDQU8Z128rm:
2559 case X86::VMOVDQU8Z256rm:
2560 case X86::VMOVDQU8Zrm:
2561 case X86::VMOVUPSZ128rm:
2562 case X86::VMOVUPSZ256rm:
2563 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2564 // Loads from constant pools are trivially rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2565 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2566 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2567 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2568 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2569 MI.isInvariantLoad(AA)) {
2570 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2571 if (BaseReg == 0 || BaseReg == X86::RIP)
2572 return true;
2573 // Allow re-materialization of PIC load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2574 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2575 return false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2576 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2577 const MachineRegisterInfo &MRI = MF.getRegInfo();
2578 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2579 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2580 return false;
2581 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2582
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2583 case X86::LEA32r:
2584 case X86::LEA64r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2585 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2586 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2587 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2588 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2589 // lea fi#, lea GV, etc. are all rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2590 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2591 return true;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2592 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2593 if (BaseReg == 0)
2594 return true;
2595 // Allow re-materialization of lea PICBase + x.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2596 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2597 const MachineRegisterInfo &MRI = MF.getRegInfo();
2598 return regIsPICBase(BaseReg, MRI);
2599 }
2600 return false;
2601 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2602 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2603
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2604 // All other instructions marked M_REMATERIALIZABLE are always trivially
2605 // rematerializable.
2606 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2607}
2608
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2609bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2610 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2611 MachineBasicBlock::iterator E = MBB.end();
2612
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2613 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2614 // safety after visiting 4 instructions in each direction, we will assume
2615 // it's not safe.
2616 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2617 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2618 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2619 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2620 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2621 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2622 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2623 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2624 continue;
2625 if (MO.getReg() == X86::EFLAGS) {
2626 if (MO.isUse())
2627 return false;
2628 SeenDef = true;
2629 }
2630 }
2631
2632 if (SeenDef)
2633 // This instruction defines EFLAGS, no need to look any further.
2634 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2635 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2636 // Skip over DBG_VALUE.
2637 while (Iter != E && Iter->isDebugValue())
2638 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2639 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2640
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2641 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2642 // live in.
2643 if (Iter == E) {
Craig Topperca66fc52015-12-20 18:41:57 +0000[diff] [blame]2644 for (MachineBasicBlock *S : MBB.successors())
2645 if (S->isLiveIn(X86::EFLAGS))
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2646 return false;
2647 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2648 }
2649
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2650 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2651 Iter = I;
2652 for (unsigned i = 0; i < 4; ++i) {
2653 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2654 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2655 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2656 return !MBB.isLiveIn(X86::EFLAGS);
2657
2658 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2659 // Skip over DBG_VALUE.
2660 while (Iter != B && Iter->isDebugValue())
2661 --Iter;
2662
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2663 bool SawKill = false;
2664 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2665 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2666 // A register mask may clobber EFLAGS, but we should still look for a
2667 // live EFLAGS def.
2668 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2669 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2670 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2671 if (MO.isDef()) return MO.isDead();
2672 if (MO.isKill()) SawKill = true;
2673 }
2674 }
2675
2676 if (SawKill)
2677 // This instruction kills EFLAGS and doesn't redefine it, so
2678 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2679 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2680 }
2681
2682 // Conservative answer.
2683 return false;
2684}
2685
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2686void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2687 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2688 unsigned DestReg, unsigned SubIdx,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2689 const MachineInstr &Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2690 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2691 bool ClobbersEFLAGS = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2692 for (const MachineOperand &MO : Orig.operands()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2693 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2694 ClobbersEFLAGS = true;
2695 break;
2696 }
2697 }
2698
2699 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2700 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2701 // effects.
2702 int Value;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2703 switch (Orig.getOpcode()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2704 case X86::MOV32r0: Value = 0; break;
2705 case X86::MOV32r1: Value = 1; break;
2706 case X86::MOV32r_1: Value = -1; break;
2707 default:
2708 llvm_unreachable("Unexpected instruction!");
2709 }
2710
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2711 const DebugLoc &DL = Orig.getDebugLoc();
2712 BuildMI(MBB, I, DL, get(X86::MOV32ri))
2713 .addOperand(Orig.getOperand(0))
2714 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2715 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2716 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2717 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2718 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2719
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]2720 MachineInstr &NewMI = *std::prev(I);
2721 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2722}
2723
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2724/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2725bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2726 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2727 MachineOperand &MO = MI.getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2728 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2729 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2730 return true;
2731 }
2732 }
2733 return false;
2734}
2735
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2736/// Check whether the shift count for a machine operand is non-zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2737inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2738 unsigned ShiftAmtOperandIdx) {
2739 // The shift count is six bits with the REX.W prefix and five bits without.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2740 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2741 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2742 return Imm & ShiftCountMask;
2743}
2744
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2745/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2746/// can be represented by a LEA instruction.
2747inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2748 // Left shift instructions can be transformed into load-effective-address
2749 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2750 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2751 // The SIB.scale field is two bits wide which means that we can encode any
2752 // shift amount less than 4.
2753 return ShAmt < 4 && ShAmt > 0;
2754}
2755
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2756bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2757 unsigned Opc, bool AllowSP, unsigned &NewSrc,
2758 bool &isKill, bool &isUndef,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]2759 MachineOperand &ImplicitOp,
2760 LiveVariables *LV) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2761 MachineFunction &MF = *MI.getParent()->getParent();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2762 const TargetRegisterClass *RC;
2763 if (AllowSP) {
2764 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2765 } else {
2766 RC = Opc != X86::LEA32r ?
2767 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2768 }
2769 unsigned SrcReg = Src.getReg();
2770
2771 // For both LEA64 and LEA32 the register already has essentially the right
2772 // type (32-bit or 64-bit) we may just need to forbid SP.
2773 if (Opc != X86::LEA64_32r) {
2774 NewSrc = SrcReg;
2775 isKill = Src.isKill();
2776 isUndef = Src.isUndef();
2777
2778 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2779 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2780 return false;
2781
2782 return true;
2783 }
2784
2785 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2786 // another we need to add 64-bit registers to the final MI.
2787 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2788 ImplicitOp = Src;
2789 ImplicitOp.setImplicit();
2790
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]2791 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
Matthias Braunca8210a2016-07-21 00:33:38 +0000[diff] [blame]2792 isKill = Src.isKill();
2793 isUndef = Src.isUndef();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2794 } else {
2795 // Virtual register of the wrong class, we have to create a temporary 64-bit
2796 // vreg to feed into the LEA.
2797 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]2798 MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
2799 get(TargetOpcode::COPY))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2800 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2801 .addOperand(Src);
2802
2803 // Which is obviously going to be dead after we're done with it.
2804 isKill = true;
2805 isUndef = false;
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]2806
2807 if (LV)
2808 LV->replaceKillInstruction(SrcReg, MI, *Copy);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2809 }
2810
2811 // We've set all the parameters without issue.
2812 return true;
2813}
2814
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2815/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2816/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2817/// truncating back down to a 16-bit subregister.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2818MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2819 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2820 LiveVariables *LV) const {
2821 MachineBasicBlock::iterator MBBI = MI.getIterator();
2822 unsigned Dest = MI.getOperand(0).getReg();
2823 unsigned Src = MI.getOperand(1).getReg();
2824 bool isDead = MI.getOperand(0).isDead();
2825 bool isKill = MI.getOperand(1).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2826
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2827 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2828 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2829 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2830 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2831 Opc = X86::LEA64_32r;
2832 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2833 } else {
2834 Opc = X86::LEA32r;
2835 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2836 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2837
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2838 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2839 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2840 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2841 // movw (%rbp,%rcx,2), %dx
2842 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2843 // But testing has shown this *does* help performance in 64-bit mode (at
2844 // least on modern x86 machines).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2845 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2846 MachineInstr *InsMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2847 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2848 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2849 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2850
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2851 MachineInstrBuilder MIB =
2852 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2853 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2854 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2855 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2856 unsigned ShAmt = MI.getOperand(2).getImm();
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2857 MIB.addReg(0).addImm(1ULL << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2858 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2859 break;
2860 }
2861 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2862 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2863 break;
2864 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2865 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2866 break;
2867 case X86::ADD16ri:
2868 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2869 case X86::ADD16ri_DB:
2870 case X86::ADD16ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2871 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2872 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2873 case X86::ADD16rr:
2874 case X86::ADD16rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2875 unsigned Src2 = MI.getOperand(2).getReg();
2876 bool isKill2 = MI.getOperand(2).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2877 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2878 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2879 if (Src == Src2) {
2880 // ADD16rr %reg1028<kill>, %reg1028
2881 // just a single insert_subreg.
2882 addRegReg(MIB, leaInReg, true, leaInReg, false);
2883 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2884 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2885 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2886 else
2887 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2888 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2889 // well be shifting and then extracting the lower 16-bits.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2890 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2891 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2892 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2893 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2894 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2895 }
2896 if (LV && isKill2 && InsMI2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2897 LV->replaceKillInstruction(Src2, MI, *InsMI2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2898 break;
2899 }
2900 }
2901
2902 MachineInstr *NewMI = MIB;
2903 MachineInstr *ExtMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2904 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2905 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2906 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2907
2908 if (LV) {
2909 // Update live variables
2910 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2911 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2912 if (isKill)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2913 LV->replaceKillInstruction(Src, MI, *InsMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2914 if (isDead)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2915 LV->replaceKillInstruction(Dest, MI, *ExtMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2916 }
2917
2918 return ExtMI;
2919}
2920
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2921/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2922/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2923/// may be able to convert a two-address instruction into a true
2924/// three-address instruction on demand. This allows the X86 target (for
2925/// example) to convert ADD and SHL instructions into LEA instructions if they
2926/// would require register copies due to two-addressness.
2927///
2928/// This method returns a null pointer if the transformation cannot be
2929/// performed, otherwise it returns the new instruction.
2930///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2931MachineInstr *
2932X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2933 MachineInstr &MI, LiveVariables *LV) const {
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2934 // The following opcodes also sets the condition code register(s). Only
2935 // convert them to equivalent lea if the condition code register def's
2936 // are dead!
2937 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2938 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2939
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2940 MachineFunction &MF = *MI.getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2941 // All instructions input are two-addr instructions. Get the known operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2942 const MachineOperand &Dest = MI.getOperand(0);
2943 const MachineOperand &Src = MI.getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2944
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2945 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2946 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2947 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2948 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2949 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2950 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2951
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2952 unsigned MIOpc = MI.getOpcode();
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2953 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2954 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2955 case X86::SHL64ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2956 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2957 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2958 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2959
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2960 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2961 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2962 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2963 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2964 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2965
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2966 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2967 .addOperand(Dest)
2968 .addReg(0)
2969 .addImm(1ULL << ShAmt)
2970 .addOperand(Src)
2971 .addImm(0)
2972 .addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2973 break;
2974 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2975 case X86::SHL32ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2976 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2977 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2978 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2979
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2980 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2981
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2982 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2983 bool isKill, isUndef;
2984 unsigned SrcReg;
2985 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2986 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]2987 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2988 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2989
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2990 MachineInstrBuilder MIB =
2991 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2992 .addOperand(Dest)
2993 .addReg(0)
2994 .addImm(1ULL << ShAmt)
2995 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2996 .addImm(0)
2997 .addReg(0);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2998 if (ImplicitOp.getReg() != 0)
2999 MIB.addOperand(ImplicitOp);
3000 NewMI = MIB;
3001
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3002 break;
3003 }
3004 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3005 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3006 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3007 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3008
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]3009 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3010 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3011 : nullptr;
3012 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3013 .addOperand(Dest)
3014 .addReg(0)
3015 .addImm(1ULL << ShAmt)
3016 .addOperand(Src)
3017 .addImm(0)
3018 .addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3019 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]3020 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3021 case X86::INC64r:
3022 case X86::INC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3023 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3024 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
3025 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3026 bool isKill, isUndef;
3027 unsigned SrcReg;
3028 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3029 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3030 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3031 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]3032
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3033 MachineInstrBuilder MIB =
3034 BuildMI(MF, MI.getDebugLoc(), get(Opc))
3035 .addOperand(Dest)
3036 .addReg(SrcReg,
3037 getKillRegState(isKill) | getUndefRegState(isUndef));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3038 if (ImplicitOp.getReg() != 0)
3039 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3040
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3041 NewMI = addOffset(MIB, 1);
3042 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]3043 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3044 case X86::INC16r:
3045 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3046 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3047 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3048 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3049 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3050 .addOperand(Dest)
3051 .addOperand(Src),
3052 1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3053 break;
3054 case X86::DEC64r:
3055 case X86::DEC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3056 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3057 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
3058 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3059
3060 bool isKill, isUndef;
3061 unsigned SrcReg;
3062 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3063 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3064 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3065 return nullptr;
3066
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3067 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3068 .addOperand(Dest)
3069 .addReg(SrcReg, getUndefRegState(isUndef) |
3070 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3071 if (ImplicitOp.getReg() != 0)
3072 MIB.addOperand(ImplicitOp);
3073
3074 NewMI = addOffset(MIB, -1);
3075
3076 break;
3077 }
3078 case X86::DEC16r:
3079 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3080 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3081 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3082 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3083 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3084 .addOperand(Dest)
3085 .addOperand(Src),
3086 -1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3087 break;
3088 case X86::ADD64rr:
3089 case X86::ADD64rr_DB:
3090 case X86::ADD32rr:
3091 case X86::ADD32rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3092 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3093 unsigned Opc;
3094 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3095 Opc = X86::LEA64r;
3096 else
3097 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3098
3099 bool isKill, isUndef;
3100 unsigned SrcReg;
3101 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3102 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3103 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3104 return nullptr;
3105
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3106 const MachineOperand &Src2 = MI.getOperand(2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3107 bool isKill2, isUndef2;
3108 unsigned SrcReg2;
3109 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3110 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3111 SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3112 return nullptr;
3113
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3114 MachineInstrBuilder MIB =
3115 BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3116 if (ImplicitOp.getReg() != 0)
3117 MIB.addOperand(ImplicitOp);
3118 if (ImplicitOp2.getReg() != 0)
3119 MIB.addOperand(ImplicitOp2);
3120
3121 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3122
3123 // Preserve undefness of the operands.
3124 NewMI->getOperand(1).setIsUndef(isUndef);
3125 NewMI->getOperand(3).setIsUndef(isUndef2);
3126
3127 if (LV && Src2.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3128 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3129 break;
3130 }
3131 case X86::ADD16rr:
3132 case X86::ADD16rr_DB: {
3133 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3134 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3135 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3136 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3137 unsigned Src2 = MI.getOperand(2).getReg();
3138 bool isKill2 = MI.getOperand(2).isKill();
3139 NewMI = addRegReg(
3140 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3141 Src.getReg(), Src.isKill(), Src2, isKill2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3142
3143 // Preserve undefness of the operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3144 bool isUndef = MI.getOperand(1).isUndef();
3145 bool isUndef2 = MI.getOperand(2).isUndef();
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3146 NewMI->getOperand(1).setIsUndef(isUndef);
3147 NewMI->getOperand(3).setIsUndef(isUndef2);
3148
3149 if (LV && isKill2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3150 LV->replaceKillInstruction(Src2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3151 break;
3152 }
3153 case X86::ADD64ri32:
3154 case X86::ADD64ri8:
3155 case X86::ADD64ri32_DB:
3156 case X86::ADD64ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3157 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3158 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3159 .addOperand(Dest)
3160 .addOperand(Src),
3161 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3162 break;
3163 case X86::ADD32ri:
3164 case X86::ADD32ri8:
3165 case X86::ADD32ri_DB:
3166 case X86::ADD32ri8_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3167 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3168 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3169
3170 bool isKill, isUndef;
3171 unsigned SrcReg;
3172 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3173 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3174 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3175 return nullptr;
3176
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3177 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3178 .addOperand(Dest)
3179 .addReg(SrcReg, getUndefRegState(isUndef) |
3180 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3181 if (ImplicitOp.getReg() != 0)
3182 MIB.addOperand(ImplicitOp);
3183
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3184 NewMI = addOffset(MIB, MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3185 break;
3186 }
3187 case X86::ADD16ri:
3188 case X86::ADD16ri8:
3189 case X86::ADD16ri_DB:
3190 case X86::ADD16ri8_DB:
3191 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3192 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3193 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3194 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3195 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3196 .addOperand(Dest)
3197 .addOperand(Src),
3198 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3199 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3200 }
3201
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3202 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]3203
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3204 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3205 if (Src.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3206 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3207 if (Dest.isDead())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3208 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3209 }
3210
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3211 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]3212 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3213}
3214
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3215unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3216 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
3217 const X86InstrFMA3Group &FMA3Group) const {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3218
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3219 unsigned Opc = MI.getOpcode();
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3220
3221 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3222 if (SrcOpIdx1 > SrcOpIdx2)
3223 std::swap(SrcOpIdx1, SrcOpIdx2);
3224
3225 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3226 // analysis. The commute optimization is legal only if all users of FMA*_Int
3227 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3228 // not implemented yet. So, just return 0 in that case.
3229 // When such analysis are available this place will be the right place for
3230 // calling it.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3231 if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3232 return 0;
3233
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3234 unsigned FMAOp1 = 1, FMAOp2 = 2, FMAOp3 = 3;
3235 if (FMA3Group.isKMasked()) {
3236 // The k-mask operand cannot be commuted.
3237 if (SrcOpIdx1 == 2)
3238 return 0;
3239
3240 // For k-zero-masked operations it is Ok to commute the first vector
3241 // operand.
3242 // For regular k-masked operations a conservative choice is done as the
3243 // elements of the first vector operand, for which the corresponding bit
3244 // in the k-mask operand is set to 0, are copied to the result of FMA.
3245 // TODO/FIXME: The commute still may be legal if it is known that the
3246 // k-mask operand is set to either all ones or all zeroes.
3247 // It is also Ok to commute the 1st operand if all users of MI use only
3248 // the elements enabled by the k-mask operand. For example,
3249 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
3250 // : v1[i];
3251 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
3252 // // Ok, to commute v1 in FMADD213PSZrk.
3253 if (FMA3Group.isKMergeMasked() && SrcOpIdx1 == FMAOp1)
3254 return 0;
3255 FMAOp2++;
3256 FMAOp3++;
3257 }
3258
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3259 unsigned Case;
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3260 if (SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp2)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3261 Case = 0;
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3262 else if (SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp3)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3263 Case = 1;
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3264 else if (SrcOpIdx1 == FMAOp2 && SrcOpIdx2 == FMAOp3)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3265 Case = 2;
3266 else
3267 return 0;
3268
3269 // Define the FMA forms mapping array that helps to map input FMA form
3270 // to output FMA form to preserve the operation semantics after
3271 // commuting the operands.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3272 const unsigned Form132Index = 0;
3273 const unsigned Form213Index = 1;
3274 const unsigned Form231Index = 2;
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3275 static const unsigned FormMapping[][3] = {
3276 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3277 // FMA132 A, C, b; ==> FMA231 C, A, b;
3278 // FMA213 B, A, c; ==> FMA213 A, B, c;
3279 // FMA231 C, A, b; ==> FMA132 A, C, b;
3280 { Form231Index, Form213Index, Form132Index },
3281 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3282 // FMA132 A, c, B; ==> FMA132 B, c, A;
3283 // FMA213 B, a, C; ==> FMA231 C, a, B;
3284 // FMA231 C, a, B; ==> FMA213 B, a, C;
3285 { Form132Index, Form231Index, Form213Index },
3286 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3287 // FMA132 a, C, B; ==> FMA213 a, B, C;
3288 // FMA213 b, A, C; ==> FMA132 b, C, A;
3289 // FMA231 c, A, B; ==> FMA231 c, B, A;
3290 { Form213Index, Form132Index, Form231Index }
3291 };
3292
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3293 unsigned FMAForms[3];
3294 if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
3295 FMAForms[0] = FMA3Group.getReg132Opcode();
3296 FMAForms[1] = FMA3Group.getReg213Opcode();
3297 FMAForms[2] = FMA3Group.getReg231Opcode();
3298 } else {
3299 FMAForms[0] = FMA3Group.getMem132Opcode();
3300 FMAForms[1] = FMA3Group.getMem213Opcode();
3301 FMAForms[2] = FMA3Group.getMem231Opcode();
3302 }
3303 unsigned FormIndex;
3304 for (FormIndex = 0; FormIndex < 3; FormIndex++)
3305 if (Opc == FMAForms[FormIndex])
3306 break;
3307
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3308 // Everything is ready, just adjust the FMA opcode and return it.
3309 FormIndex = FormMapping[Case][FormIndex];
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3310 return FMAForms[FormIndex];
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3311}
3312
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3313MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3314 unsigned OpIdx1,
3315 unsigned OpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3316 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3317 if (NewMI)
3318 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3319 return MI;
3320 };
3321
3322 switch (MI.getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3323 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3324 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3325 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3326 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3327 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3328 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3329 unsigned Opc;
3330 unsigned Size;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3331 switch (MI.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3332 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3333 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3334 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3335 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3336 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3337 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3338 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3339 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3340 unsigned Amt = MI.getOperand(3).getImm();
3341 auto &WorkingMI = cloneIfNew(MI);
3342 WorkingMI.setDesc(get(Opc));
3343 WorkingMI.getOperand(3).setImm(Size - Amt);
3344 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3345 OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3346 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3347 case X86::BLENDPDrri:
3348 case X86::BLENDPSrri:
3349 case X86::PBLENDWrri:
3350 case X86::VBLENDPDrri:
3351 case X86::VBLENDPSrri:
3352 case X86::VBLENDPDYrri:
3353 case X86::VBLENDPSYrri:
3354 case X86::VPBLENDDrri:
3355 case X86::VPBLENDWrri:
3356 case X86::VPBLENDDYrri:
3357 case X86::VPBLENDWYrri:{
3358 unsigned Mask;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3359 switch (MI.getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3360 default: llvm_unreachable("Unreachable!");
3361 case X86::BLENDPDrri: Mask = 0x03; break;
3362 case X86::BLENDPSrri: Mask = 0x0F; break;
3363 case X86::PBLENDWrri: Mask = 0xFF; break;
3364 case X86::VBLENDPDrri: Mask = 0x03; break;
3365 case X86::VBLENDPSrri: Mask = 0x0F; break;
3366 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3367 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3368 case X86::VPBLENDDrri: Mask = 0x0F; break;
3369 case X86::VPBLENDWrri: Mask = 0xFF; break;
3370 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3371 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3372 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3373 // Only the least significant bits of Imm are used.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3374 unsigned Imm = MI.getOperand(3).getImm() & Mask;
3375 auto &WorkingMI = cloneIfNew(MI);
3376 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3377 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3378 OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3379 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3380 case X86::PCLMULQDQrr:
3381 case X86::VPCLMULQDQrr:{
3382 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3383 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3384 unsigned Imm = MI.getOperand(3).getImm();
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3385 unsigned Src1Hi = Imm & 0x01;
3386 unsigned Src2Hi = Imm & 0x10;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3387 auto &WorkingMI = cloneIfNew(MI);
3388 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3389 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3390 OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3391 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3392 case X86::CMPPDrri:
3393 case X86::CMPPSrri:
3394 case X86::VCMPPDrri:
3395 case X86::VCMPPSrri:
3396 case X86::VCMPPDYrri:
3397 case X86::VCMPPSYrri: {
3398 // Float comparison can be safely commuted for
3399 // Ordered/Unordered/Equal/NotEqual tests
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3400 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3401 switch (Imm) {
3402 case 0x00: // EQUAL
3403 case 0x03: // UNORDERED
3404 case 0x04: // NOT EQUAL
3405 case 0x07: // ORDERED
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3406 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3407 default:
3408 return nullptr;
3409 }
3410 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3411 case X86::VPCOMBri: case X86::VPCOMUBri:
3412 case X86::VPCOMDri: case X86::VPCOMUDri:
3413 case X86::VPCOMQri: case X86::VPCOMUQri:
3414 case X86::VPCOMWri: case X86::VPCOMUWri: {
3415 // Flip comparison mode immediate (if necessary).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3416 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3417 switch (Imm) {
3418 case 0x00: Imm = 0x02; break; // LT -> GT
3419 case 0x01: Imm = 0x03; break; // LE -> GE
3420 case 0x02: Imm = 0x00; break; // GT -> LT
3421 case 0x03: Imm = 0x01; break; // GE -> LE
3422 case 0x04: // EQ
3423 case 0x05: // NE
3424 case 0x06: // FALSE
3425 case 0x07: // TRUE
3426 default:
3427 break;
3428 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3429 auto &WorkingMI = cloneIfNew(MI);
3430 WorkingMI.getOperand(3).setImm(Imm);
3431 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3432 OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3433 }
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3434 case X86::VPERM2F128rr:
3435 case X86::VPERM2I128rr: {
3436 // Flip permute source immediate.
3437 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3438 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3439 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3440 auto &WorkingMI = cloneIfNew(MI);
3441 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3442 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3443 OpIdx1, OpIdx2);
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3444 }
Simon Pilgrim7d168e12016-08-06 18:40:28 +0000[diff] [blame]3445 case X86::MOVHLPSrr:
3446 case X86::UNPCKHPDrr: {
3447 if (!Subtarget.hasSSE2())
3448 return nullptr;
3449
3450 unsigned Opc = MI.getOpcode();
3451 switch (Opc) {
3452 default: llvm_unreachable("Unreachable!");
3453 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
3454 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
3455 }
3456 auto &WorkingMI = cloneIfNew(MI);
3457 WorkingMI.setDesc(get(Opc));
3458 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3459 OpIdx1, OpIdx2);
3460 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3461 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3462 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3463 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3464 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3465 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3466 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3467 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3468 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3469 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3470 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3471 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3472 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3473 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3474 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3475 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3476 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3477 unsigned Opc;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3478 switch (MI.getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3479 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3480 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3481 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3482 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3483 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3484 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3485 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3486 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3487 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3488 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3489 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3490 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3491 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3492 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3493 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3494 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3495 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3496 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3497 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3498 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3499 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3500 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3501 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3502 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3503 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3504 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3505 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3506 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3507 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3508 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3509 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3510 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3511 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3512 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3513 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3514 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3515 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3516 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3517 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3518 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3519 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3520 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3521 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3522 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3523 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3524 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3525 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3526 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3527 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3528 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3529 auto &WorkingMI = cloneIfNew(MI);
3530 WorkingMI.setDesc(get(Opc));
3531 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3532 OpIdx1, OpIdx2);
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3533 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3534 default:
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3535 const X86InstrFMA3Group *FMA3Group =
3536 X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
3537 if (FMA3Group) {
3538 unsigned Opc =
3539 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3540 if (Opc == 0)
3541 return nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3542 auto &WorkingMI = cloneIfNew(MI);
3543 WorkingMI.setDesc(get(Opc));
3544 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3545 OpIdx1, OpIdx2);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3546 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3547
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3548 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3549 }
3550}
3551
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3552bool X86InstrInfo::findFMA3CommutedOpIndices(
3553 const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
3554 const X86InstrFMA3Group &FMA3Group) const {
3555 unsigned FirstCommutableVecOp = 1;
3556 unsigned LastCommutableVecOp = 3;
3557 unsigned KMaskOp = 0;
3558 if (FMA3Group.isKMasked()) {
3559 // The k-mask operand has index = 2 for masked and zero-masked operations.
3560 KMaskOp = 2;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3561
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3562 // The operand with index = 1 is used as a source for those elements for
3563 // which the corresponding bit in the k-mask is set to 0.
3564 if (FMA3Group.isKMergeMasked())
3565 FirstCommutableVecOp = 3;
3566
3567 LastCommutableVecOp++;
3568 }
3569
3570 if (isMem(MI, LastCommutableVecOp))
3571 LastCommutableVecOp--;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3572
3573 // Only the first RegOpsNum operands are commutable.
3574 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3575 // that the operand is not specified/fixed.
3576 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3577 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
3578 SrcOpIdx1 == KMaskOp))
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3579 return false;
3580 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3581 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
3582 SrcOpIdx2 == KMaskOp))
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3583 return false;
3584
3585 // Look for two different register operands assumed to be commutable
3586 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3587 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3588 SrcOpIdx2 == CommuteAnyOperandIndex) {
3589 unsigned CommutableOpIdx1 = SrcOpIdx1;
3590 unsigned CommutableOpIdx2 = SrcOpIdx2;
3591
3592 // At least one of operands to be commuted is not specified and
3593 // this method is free to choose appropriate commutable operands.
3594 if (SrcOpIdx1 == SrcOpIdx2)
3595 // Both of operands are not fixed. By default set one of commutable
3596 // operands to the last register operand of the instruction.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3597 CommutableOpIdx2 = LastCommutableVecOp;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3598 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3599 // Only one of operands is not fixed.
3600 CommutableOpIdx2 = SrcOpIdx1;
3601
3602 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3603 // operand and assign its index to CommutableOpIdx1.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3604 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3605 for (CommutableOpIdx1 = LastCommutableVecOp;
3606 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
3607 // Just ignore and skip the k-mask operand.
3608 if (CommutableOpIdx1 == KMaskOp)
3609 continue;
3610
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3611 // The commuted operands must have different registers.
3612 // Otherwise, the commute transformation does not change anything and
3613 // is useless then.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3614 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3615 break;
3616 }
3617
3618 // No appropriate commutable operands were found.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3619 if (CommutableOpIdx1 < FirstCommutableVecOp)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3620 return false;
3621
3622 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3623 // to return those values.
3624 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3625 CommutableOpIdx1, CommutableOpIdx2))
3626 return false;
3627 }
3628
3629 // Check if we can adjust the opcode to preserve the semantics when
3630 // commute the register operands.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3631 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3632}
3633
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3634bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3635 unsigned &SrcOpIdx2) const {
Craig Topper8c372a32016-08-13 06:48:44 +0000[diff] [blame]3636 if (!MI.isCommutable())
3637 return false;
3638
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3639 switch (MI.getOpcode()) {
3640 case X86::CMPPDrri:
3641 case X86::CMPPSrri:
3642 case X86::VCMPPDrri:
3643 case X86::VCMPPSrri:
3644 case X86::VCMPPDYrri:
3645 case X86::VCMPPSYrri: {
3646 // Float comparison can be safely commuted for
3647 // Ordered/Unordered/Equal/NotEqual tests
3648 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3649 switch (Imm) {
3650 case 0x00: // EQUAL
3651 case 0x03: // UNORDERED
3652 case 0x04: // NOT EQUAL
3653 case 0x07: // ORDERED
3654 // The indices of the commutable operands are 1 and 2.
3655 // Assign them to the returned operand indices here.
3656 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3657 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3658 return false;
3659 }
3660 default:
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3661 const X86InstrFMA3Group *FMA3Group =
3662 X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
3663 if (FMA3Group)
3664 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3665 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3666 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3667 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3668}
3669
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3670static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3671 switch (BrOpc) {
3672 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3673 case X86::JE_1: return X86::COND_E;
3674 case X86::JNE_1: return X86::COND_NE;
3675 case X86::JL_1: return X86::COND_L;
3676 case X86::JLE_1: return X86::COND_LE;
3677 case X86::JG_1: return X86::COND_G;
3678 case X86::JGE_1: return X86::COND_GE;
3679 case X86::JB_1: return X86::COND_B;
3680 case X86::JBE_1: return X86::COND_BE;
3681 case X86::JA_1: return X86::COND_A;
3682 case X86::JAE_1: return X86::COND_AE;
3683 case X86::JS_1: return X86::COND_S;
3684 case X86::JNS_1: return X86::COND_NS;
3685 case X86::JP_1: return X86::COND_P;
3686 case X86::JNP_1: return X86::COND_NP;
3687 case X86::JO_1: return X86::COND_O;
3688 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3689 }
3690}
3691
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3692/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3693static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3694 switch (Opc) {
3695 default: return X86::COND_INVALID;
3696 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3697 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3698 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3699 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3700 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3701 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3702 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3703 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3704 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3705 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3706 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3707 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3708 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3709 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3710 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3711 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3712 }
3713}
3714
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3715/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3716X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3717 switch (Opc) {
3718 default: return X86::COND_INVALID;
3719 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3720 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3721 return X86::COND_A;
3722 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3723 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3724 return X86::COND_AE;
3725 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3726 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3727 return X86::COND_B;
3728 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3729 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3730 return X86::COND_BE;
3731 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3732 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3733 return X86::COND_E;
3734 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3735 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3736 return X86::COND_G;
3737 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3738 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3739 return X86::COND_GE;
3740 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3741 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3742 return X86::COND_L;
3743 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3744 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3745 return X86::COND_LE;
3746 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3747 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3748 return X86::COND_NE;
3749 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3750 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3751 return X86::COND_NO;
3752 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3753 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3754 return X86::COND_NP;
3755 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3756 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3757 return X86::COND_NS;
3758 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3759 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3760 return X86::COND_O;
3761 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3762 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3763 return X86::COND_P;
3764 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3765 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3766 return X86::COND_S;
3767 }
3768}
3769
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3770unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3771 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3772 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3773 case X86::COND_E: return X86::JE_1;
3774 case X86::COND_NE: return X86::JNE_1;
3775 case X86::COND_L: return X86::JL_1;
3776 case X86::COND_LE: return X86::JLE_1;
3777 case X86::COND_G: return X86::JG_1;
3778 case X86::COND_GE: return X86::JGE_1;
3779 case X86::COND_B: return X86::JB_1;
3780 case X86::COND_BE: return X86::JBE_1;
3781 case X86::COND_A: return X86::JA_1;
3782 case X86::COND_AE: return X86::JAE_1;
3783 case X86::COND_S: return X86::JS_1;
3784 case X86::COND_NS: return X86::JNS_1;
3785 case X86::COND_P: return X86::JP_1;
3786 case X86::COND_NP: return X86::JNP_1;
3787 case X86::COND_O: return X86::JO_1;
3788 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3789 }
3790}
3791
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3792/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3793/// e.g. turning COND_E to COND_NE.
3794X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3795 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3796 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3797 case X86::COND_E: return X86::COND_NE;
3798 case X86::COND_NE: return X86::COND_E;
3799 case X86::COND_L: return X86::COND_GE;
3800 case X86::COND_LE: return X86::COND_G;
3801 case X86::COND_G: return X86::COND_LE;
3802 case X86::COND_GE: return X86::COND_L;
3803 case X86::COND_B: return X86::COND_AE;
3804 case X86::COND_BE: return X86::COND_A;
3805 case X86::COND_A: return X86::COND_BE;
3806 case X86::COND_AE: return X86::COND_B;
3807 case X86::COND_S: return X86::COND_NS;
3808 case X86::COND_NS: return X86::COND_S;
3809 case X86::COND_P: return X86::COND_NP;
3810 case X86::COND_NP: return X86::COND_P;
3811 case X86::COND_O: return X86::COND_NO;
3812 case X86::COND_NO: return X86::COND_O;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3813 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
3814 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3815 }
3816}
3817
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3818/// Assuming the flags are set by MI(a,b), return the condition code if we
3819/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3820static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3821 switch (CC) {
3822 default: return X86::COND_INVALID;
3823 case X86::COND_E: return X86::COND_E;
3824 case X86::COND_NE: return X86::COND_NE;
3825 case X86::COND_L: return X86::COND_G;
3826 case X86::COND_LE: return X86::COND_GE;
3827 case X86::COND_G: return X86::COND_L;
3828 case X86::COND_GE: return X86::COND_LE;
3829 case X86::COND_B: return X86::COND_A;
3830 case X86::COND_BE: return X86::COND_AE;
3831 case X86::COND_A: return X86::COND_B;
3832 case X86::COND_AE: return X86::COND_BE;
3833 }
3834}
3835
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3836/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3837/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3838unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3839 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3840 { X86::SETAr, X86::SETAm },
3841 { X86::SETAEr, X86::SETAEm },
3842 { X86::SETBr, X86::SETBm },
3843 { X86::SETBEr, X86::SETBEm },
3844 { X86::SETEr, X86::SETEm },
3845 { X86::SETGr, X86::SETGm },
3846 { X86::SETGEr, X86::SETGEm },
3847 { X86::SETLr, X86::SETLm },
3848 { X86::SETLEr, X86::SETLEm },
3849 { X86::SETNEr, X86::SETNEm },
3850 { X86::SETNOr, X86::SETNOm },
3851 { X86::SETNPr, X86::SETNPm },
3852 { X86::SETNSr, X86::SETNSm },
3853 { X86::SETOr, X86::SETOm },
3854 { X86::SETPr, X86::SETPm },
3855 { X86::SETSr, X86::SETSm }
3856 };
3857
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3858 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3859 return Opc[CC][HasMemoryOperand ? 1 : 0];
3860}
3861
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3862/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3863/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3864unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3865 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3866 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3867 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3868 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3869 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3870 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3871 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3872 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3873 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3874 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3875 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3876 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3877 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3878 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3879 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3880 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3881 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3882 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3883 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3884 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3885 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3886 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3887 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3888 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3889 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3890 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3891 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3892 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3893 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3894 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3895 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3896 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3897 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3898 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3899 };
3900
3901 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3902 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3903 switch(RegBytes) {
3904 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3905 case 2: return Opc[Idx][0];
3906 case 4: return Opc[Idx][1];
3907 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3908 }
3909}
3910
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3911bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3912 if (!MI.isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3913
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3914 // Conditional branch is a special case.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3915 if (MI.isBranch() && !MI.isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3916 return true;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3917 if (!MI.isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3918 return true;
3919 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3920}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3921
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3922// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3923// not be a fallthrough MBB now due to layout changes). Return nullptr if the
3924// fallthrough MBB cannot be identified.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3925static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3926 MachineBasicBlock *TBB) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3927 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3928 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3929 // and fallthrough MBB. If we find more than one, we cannot identify the
3930 // fallthrough MBB and should return nullptr.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3931 MachineBasicBlock *FallthroughBB = nullptr;
3932 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3933 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3934 continue;
3935 // Return a nullptr if we found more than one fallthrough successor.
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3936 if (FallthroughBB && FallthroughBB != TBB)
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3937 return nullptr;
3938 FallthroughBB = *SI;
3939 }
3940 return FallthroughBB;
3941}
3942
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3943bool X86InstrInfo::AnalyzeBranchImpl(
3944 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3945 SmallVectorImpl<MachineOperand> &Cond,
3946 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3947
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3948 // Start from the bottom of the block and work up, examining the
3949 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3950 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3951 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3952 while (I != MBB.begin()) {
3953 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3954 if (I->isDebugValue())
3955 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3956
3957 // Working from the bottom, when we see a non-terminator instruction, we're
3958 // done.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3959 if (!isUnpredicatedTerminator(*I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3960 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3961
3962 // A terminator that isn't a branch can't easily be handled by this
3963 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3964 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3965 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3966
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3967 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3968 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3969 UnCondBrIter = I;
3970
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3971 if (!AllowModify) {
3972 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3973 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3974 }
3975
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3976 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3977 while (std::next(I) != MBB.end())
3978 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3979
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3980 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3981 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3982
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3983 // Delete the JMP if it's equivalent to a fall-through.
3984 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3985 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3986 I->eraseFromParent();
3987 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3988 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3989 continue;
3990 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3991
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3992 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3993 TBB = I->getOperand(0).getMBB();
3994 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3995 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3996
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3997 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3998 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3999 if (BranchCode == X86::COND_INVALID)
4000 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4001
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4002 // Working from the bottom, handle the first conditional branch.
4003 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4004 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4005 if (AllowModify && UnCondBrIter != MBB.end() &&
4006 MBB.isLayoutSuccessor(TargetBB)) {
4007 // If we can modify the code and it ends in something like:
4008 //
4009 // jCC L1
4010 // jmp L2
4011 // L1:
4012 // ...
4013 // L2:
4014 //
4015 // Then we can change this to:
4016 //
4017 // jnCC L2
4018 // L1:
4019 // ...
4020 // L2:
4021 //
4022 // Which is a bit more efficient.
4023 // We conditionally jump to the fall-through block.
4024 BranchCode = GetOppositeBranchCondition(BranchCode);
4025 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4026 MachineBasicBlock::iterator OldInst = I;
4027
4028 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4029 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4030 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4031 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4032
4033 OldInst->eraseFromParent();
4034 UnCondBrIter->eraseFromParent();
4035
4036 // Restart the analysis.
4037 UnCondBrIter = MBB.end();
4038 I = MBB.end();
4039 continue;
4040 }
4041
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4042 FBB = TBB;
4043 TBB = I->getOperand(0).getMBB();
4044 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4045 CondBranches.push_back(&*I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4046 continue;
4047 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4048
4049 // Handle subsequent conditional branches. Only handle the case where all
4050 // conditional branches branch to the same destination and their condition
4051 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4052 assert(Cond.size() == 1);
4053 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4054
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4055 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4056 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4057 auto NewTBB = I->getOperand(0).getMBB();
4058 if (OldBranchCode == BranchCode && TBB == NewTBB)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4059 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4060
4061 // If they differ, see if they fit one of the known patterns. Theoretically,
4062 // we could handle more patterns here, but we shouldn't expect to see them
4063 // if instruction selection has done a reasonable job.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4064 if (TBB == NewTBB &&
4065 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4066 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4067 BranchCode = X86::COND_NE_OR_P;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4068 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4069 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4070 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4071 return true;
4072
4073 // X86::COND_E_AND_NP usually has two different branch destinations.
4074 //
4075 // JP B1
4076 // JE B2
4077 // JMP B1
4078 // B1:
4079 // B2:
4080 //
4081 // Here this condition branches to B2 only if NP && E. It has another
4082 // equivalent form:
4083 //
4084 // JNE B1
4085 // JNP B2
4086 // JMP B1
4087 // B1:
4088 // B2:
4089 //
4090 // Similarly it branches to B2 only if E && NP. That is why this condition
4091 // is named with COND_E_AND_NP.
4092 BranchCode = X86::COND_E_AND_NP;
4093 } else
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4094 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4095
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4096 // Update the MachineOperand.
4097 Cond[0].setImm(BranchCode);
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4098 CondBranches.push_back(&*I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4099 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4100
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4101 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4102}
4103
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4104bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4105 MachineBasicBlock *&TBB,
4106 MachineBasicBlock *&FBB,
4107 SmallVectorImpl<MachineOperand> &Cond,
4108 bool AllowModify) const {
4109 SmallVector<MachineInstr *, 4> CondBranches;
4110 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4111}
4112
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4113bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4114 MachineBranchPredicate &MBP,
4115 bool AllowModify) const {
4116 using namespace std::placeholders;
4117
4118 SmallVector<MachineOperand, 4> Cond;
4119 SmallVector<MachineInstr *, 4> CondBranches;
4120 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4121 AllowModify))
4122 return true;
4123
4124 if (Cond.size() != 1)
4125 return true;
4126
4127 assert(MBP.TrueDest && "expected!");
4128
4129 if (!MBP.FalseDest)
4130 MBP.FalseDest = MBB.getNextNode();
4131
4132 const TargetRegisterInfo *TRI = &getRegisterInfo();
4133
4134 MachineInstr *ConditionDef = nullptr;
4135 bool SingleUseCondition = true;
4136
4137 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4138 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4139 ConditionDef = &*I;
4140 break;
4141 }
4142
4143 if (I->readsRegister(X86::EFLAGS, TRI))
4144 SingleUseCondition = false;
4145 }
4146
4147 if (!ConditionDef)
4148 return true;
4149
4150 if (SingleUseCondition) {
4151 for (auto *Succ : MBB.successors())
4152 if (Succ->isLiveIn(X86::EFLAGS))
4153 SingleUseCondition = false;
4154 }
4155
4156 MBP.ConditionDef = ConditionDef;
4157 MBP.SingleUseCondition = SingleUseCondition;
4158
4159 // Currently we only recognize the simple pattern:
4160 //
4161 // test %reg, %reg
4162 // je %label
4163 //
4164 const unsigned TestOpcode =
4165 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4166
4167 if (ConditionDef->getOpcode() == TestOpcode &&
4168 ConditionDef->getNumOperands() == 3 &&
4169 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4170 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4171 MBP.LHS = ConditionDef->getOperand(0);
4172 MBP.RHS = MachineOperand::CreateImm(0);
4173 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4174 ? MachineBranchPredicate::PRED_NE
4175 : MachineBranchPredicate::PRED_EQ;
4176 return false;
4177 }
4178
4179 return true;
4180}
4181
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4182unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4183 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4184 unsigned Count = 0;
4185
4186 while (I != MBB.begin()) {
4187 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4188 if (I->isDebugValue())
4189 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4190 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4191 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4192 break;
4193 // Remove the branch.
4194 I->eraseFromParent();
4195 I = MBB.end();
4196 ++Count;
4197 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4198
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4199 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4200}
4201
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4202unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4203 MachineBasicBlock *TBB,
4204 MachineBasicBlock *FBB,
4205 ArrayRef<MachineOperand> Cond,
4206 const DebugLoc &DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4207 // Shouldn't be a fall through.
4208 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4209 assert((Cond.size() == 1 || Cond.size() == 0) &&
4210 "X86 branch conditions have one component!");
4211
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4212 if (Cond.empty()) {
4213 // Unconditional branch?
4214 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4215 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4216 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4217 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4218
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4219 // If FBB is null, it is implied to be a fall-through block.
4220 bool FallThru = FBB == nullptr;
4221
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4222 // Conditional branch.
4223 unsigned Count = 0;
4224 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4225 switch (CC) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4226 case X86::COND_NE_OR_P:
4227 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4228 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4229 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4230 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4231 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4232 break;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4233 case X86::COND_E_AND_NP:
4234 // Use the next block of MBB as FBB if it is null.
4235 if (FBB == nullptr) {
4236 FBB = getFallThroughMBB(&MBB, TBB);
4237 assert(FBB && "MBB cannot be the last block in function when the false "
4238 "body is a fall-through.");
4239 }
4240 // Synthesize COND_E_AND_NP with two branches.
4241 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4242 ++Count;
4243 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4244 ++Count;
4245 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4246 default: {
4247 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4248 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4249 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4250 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4251 }
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4252 if (!FallThru) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4253 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4254 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4255 ++Count;
4256 }
4257 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4258}
4259
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4260bool X86InstrInfo::
4261canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4262 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4263 unsigned TrueReg, unsigned FalseReg,
4264 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4265 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4266 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4267 return false;
4268 if (Cond.size() != 1)
4269 return false;
4270 // We cannot do the composite conditions, at least not in SSA form.
4271 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4272 return false;
4273
4274 // Check register classes.
4275 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4276 const TargetRegisterClass *RC =
4277 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4278 if (!RC)
4279 return false;
4280
4281 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4282 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4283 X86::GR32RegClass.hasSubClassEq(RC) ||
4284 X86::GR64RegClass.hasSubClassEq(RC)) {
4285 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4286 // Bridge. Probably Ivy Bridge as well.
4287 CondCycles = 2;
4288 TrueCycles = 2;
4289 FalseCycles = 2;
4290 return true;
4291 }
4292
4293 // Can't do vectors.
4294 return false;
4295}
4296
4297void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4298 MachineBasicBlock::iterator I,
4299 const DebugLoc &DL, unsigned DstReg,
4300 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4301 unsigned FalseReg) const {
4302 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4303 assert(Cond.size() == 1 && "Invalid Cond array");
4304 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4305 MRI.getRegClass(DstReg)->getSize(),
4306 false /*HasMemoryOperand*/);
4307 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4308}
4309
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4310/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4311static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4312 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4313}
4314
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4315// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4316static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4317 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4318
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4319 // SrcReg(VR128) -> DestReg(GR64)
4320 // SrcReg(VR64) -> DestReg(GR64)
4321 // SrcReg(GR64) -> DestReg(VR128)
4322 // SrcReg(GR64) -> DestReg(VR64)
4323
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4324 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4325 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4326 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4327 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4328 // Copy from a VR128 register to a GR64 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4329 return HasAVX512 ? X86::VMOVPQIto64Zrr :
4330 HasAVX ? X86::VMOVPQIto64rr :
4331 X86::MOVPQIto64rr;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4332 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4333 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4334 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4335 } else if (X86::GR64RegClass.contains(SrcReg)) {
4336 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4337 if (X86::VR128XRegClass.contains(DestReg))
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4338 return HasAVX512 ? X86::VMOV64toPQIZrr :
4339 HasAVX ? X86::VMOV64toPQIrr :
4340 X86::MOV64toPQIrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4341 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4342 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4343 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4344 }
4345
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4346 // SrcReg(FR32) -> DestReg(GR32)
4347 // SrcReg(GR32) -> DestReg(FR32)
4348
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4349 if (X86::GR32RegClass.contains(DestReg) &&
4350 X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4351 // Copy from a FR32 register to a GR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4352 return HasAVX512 ? X86::VMOVSS2DIZrr :
4353 HasAVX ? X86::VMOVSS2DIrr :
4354 X86::MOVSS2DIrr;
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4355
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4356 if (X86::FR32XRegClass.contains(DestReg) &&
4357 X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4358 // Copy from a GR32 register to a FR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4359 return HasAVX512 ? X86::VMOVDI2SSZrr :
4360 HasAVX ? X86::VMOVDI2SSrr :
4361 X86::MOVDI2SSrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4362 return 0;
4363}
4364
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4365static bool MaskRegClassContains(unsigned Reg) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4366 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4367 return X86::VK16RegClass.contains(Reg);
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4368}
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4369
4370static bool GRRegClassContains(unsigned Reg) {
4371 return X86::GR64RegClass.contains(Reg) ||
4372 X86::GR32RegClass.contains(Reg) ||
4373 X86::GR16RegClass.contains(Reg) ||
4374 X86::GR8RegClass.contains(Reg);
4375}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4376static
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4377unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4378 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4379 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4380 return X86::KMOVBrk;
4381 }
4382 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4383 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4384 return X86::KMOVBkr;
4385 }
4386 return 0;
4387}
4388
4389static
4390unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4391 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4392 return X86::KMOVQkk;
4393 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4394 return X86::KMOVDrk;
4395 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4396 return X86::KMOVQrk;
4397 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4398 return X86::KMOVDkr;
4399 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4400 return X86::KMOVQkr;
4401 return 0;
4402}
4403
4404static
4405unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4406 const X86Subtarget &Subtarget)
4407{
4408 if (Subtarget.hasDQI())
4409 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4410 return Opc;
4411 if (Subtarget.hasBWI())
4412 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4413 return Opc;
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4414 if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
4415 if (Subtarget.hasVLX())
4416 return X86::VMOVAPSZ128rr;
4417 DestReg = get512BitSuperRegister(DestReg);
4418 SrcReg = get512BitSuperRegister(SrcReg);
4419 return X86::VMOVAPSZrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4420 }
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4421 if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
4422 if (Subtarget.hasVLX())
4423 return X86::VMOVAPSZ256rr;
4424 DestReg = get512BitSuperRegister(DestReg);
4425 SrcReg = get512BitSuperRegister(SrcReg);
4426 return X86::VMOVAPSZrr;
4427 }
4428 if (X86::VR512RegClass.contains(DestReg, SrcReg))
4429 return X86::VMOVAPSZrr;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4430 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4431 return X86::KMOVWkk;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4432 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4433 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4434 return X86::KMOVWkr;
4435 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4436 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4437 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4438 return X86::KMOVWrk;
4439 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4440 return 0;
4441}
4442
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4443void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4444 MachineBasicBlock::iterator MI,
4445 const DebugLoc &DL, unsigned DestReg,
4446 unsigned SrcReg, bool KillSrc) const {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4447 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4448 bool HasAVX = Subtarget.hasAVX();
4449 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4450 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4451 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4452 Opc = X86::MOV64rr;
4453 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4454 Opc = X86::MOV32rr;
4455 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4456 Opc = X86::MOV16rr;
4457 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4458 // Copying to or from a physical H register on x86-64 requires a NOREX
4459 // move. Otherwise use a normal move.
4460 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4461 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4462 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4463 // Both operands must be encodable without an REX prefix.
4464 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4465 "8-bit H register can not be copied outside GR8_NOREX");
4466 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4467 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4468 }
4469 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4470 Opc = X86::MMX_MOVQ64rr;
4471 else if (HasAVX512)
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4472 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4473 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4474 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4475 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4476 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4477 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4478 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4479
4480 if (Opc) {
4481 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4482 .addReg(SrcReg, getKillRegState(KillSrc));
4483 return;
4484 }
4485
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4486 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4487 bool ToEFLAGS = DestReg == X86::EFLAGS;
4488 int Reg = FromEFLAGS ? DestReg : SrcReg;
4489 bool is32 = X86::GR32RegClass.contains(Reg);
4490 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4491
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4492 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4493 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4494 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4495 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4496 int Pop = is64 ? X86::POP64r : X86::POP32r;
4497 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4498 int AX = is64 ? X86::RAX : X86::EAX;
4499
4500 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4501 assert(Subtarget.is64Bit() &&
4502 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4503 // Moving EFLAGS to / from another register requires a push and a pop.
4504 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemer33467632015-12-27 06:07:26 +0000[diff] [blame]4505 // first frame index. See X86FrameLowering.cpp - usesTheStack.
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4506 if (FromEFLAGS) {
4507 BuildMI(MBB, MI, DL, get(PushF));
4508 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4509 }
4510 if (ToEFLAGS) {
4511 BuildMI(MBB, MI, DL, get(Push))
4512 .addReg(SrcReg, getKillRegState(KillSrc));
4513 BuildMI(MBB, MI, DL, get(PopF));
4514 }
4515 return;
4516 }
4517
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4518 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4519 // inefficient. Instead:
4520 // - Save the overflow flag OF into AL using SETO, and restore it using a
4521 // signed 8-bit addition of AL and INT8_MAX.
4522 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4523 // using LAHF/SAHF.
4524 // - When RAX/EAX is live and isn't the destination register, make sure it
4525 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4526 // the flags.
4527 // This approach is ~2.25x faster than using PUSHF/POPF.
4528 //
4529 // This is still somewhat inefficient because we don't know which flags are
4530 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4531 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4532 //
4533 // PUSHF/POPF is also potentially incorrect because it affects other flags
4534 // such as TF/IF/DF, which LLVM doesn't model.
4535 //
4536 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemerca1c9f02016-01-04 04:49:41 +0000[diff] [blame]4537 // first frame index.
4538 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4539
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4540 const TargetRegisterInfo *TRI = &getRegisterInfo();
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4541 MachineBasicBlock::LivenessQueryResult LQR =
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4542 MBB.computeRegisterLiveness(TRI, AX, MI);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4543 // We do not want to save and restore AX if we do not have to.
4544 // Moreover, if we do so whereas AX is dead, we would need to set
4545 // an undef flag on the use of AX, otherwise the verifier will
4546 // complain that we read an undef value.
4547 // We do not want to change the behavior of the machine verifier
4548 // as this is usually wrong to read an undef value.
4549 if (MachineBasicBlock::LQR_Unknown == LQR) {
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4550 LivePhysRegs LPR(TRI);
Matthias Braund1aabb22016-05-03 00:24:32 +0000[diff] [blame]4551 LPR.addLiveOuts(MBB);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4552 MachineBasicBlock::iterator I = MBB.end();
4553 while (I != MI) {
4554 --I;
4555 LPR.stepBackward(*I);
4556 }
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4557 // AX contains the top most register in the aliasing hierarchy.
4558 // It may not be live, but one of its aliases may be.
4559 for (MCRegAliasIterator AI(AX, TRI, true);
4560 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4561 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4562 : MachineBasicBlock::LQR_Dead;
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4563 }
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4564 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4565 if (!AXDead)
4566 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4567 if (FromEFLAGS) {
4568 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4569 BuildMI(MBB, MI, DL, get(X86::LAHF));
4570 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4571 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4572 if (ToEFLAGS) {
4573 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4574 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4575 .addReg(X86::AL)
4576 .addImm(INT8_MAX);
4577 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4578 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4579 if (!AXDead)
4580 BuildMI(MBB, MI, DL, get(Pop), AX);
4581 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4582 }
4583
4584 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4585 << " to " << RI.getName(DestReg) << '\n');
4586 llvm_unreachable("Cannot emit physreg copy instruction");
4587}
4588
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4589static unsigned getLoadStoreRegOpcode(unsigned Reg,
4590 const TargetRegisterClass *RC,
4591 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4592 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4593 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4594 bool HasAVX = STI.hasAVX();
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4595 bool HasAVX512 = STI.hasAVX512();
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4596 bool HasVLX = STI.hasVLX();
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4597
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4598 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4599 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4600 llvm_unreachable("Unknown spill size");
4601 case 1:
4602 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4603 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4604 // Copying to or from a physical H register on x86-64 requires a NOREX
4605 // move. Otherwise use a normal move.
4606 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4607 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4608 return load ? X86::MOV8rm : X86::MOV8mr;
4609 case 2:
Craig Topperda50eec2016-08-01 04:29:11 +0000[diff] [blame]4610 if (X86::VK16RegClass.hasSubClassEq(RC))
4611 return load ? X86::KMOVWkm : X86::KMOVWmk;
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4612 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4613 return load ? X86::MOV16rm : X86::MOV16mr;
4614 case 4:
4615 if (X86::GR32RegClass.hasSubClassEq(RC))
4616 return load ? X86::MOV32rm : X86::MOV32mr;
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4617 if (X86::FR32XRegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4618 return load ?
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4619 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4620 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4621 if (X86::RFP32RegClass.hasSubClassEq(RC))
4622 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
Craig Topperda50eec2016-08-01 04:29:11 +0000[diff] [blame]4623 if (X86::VK32RegClass.hasSubClassEq(RC))
4624 return load ? X86::KMOVDkm : X86::KMOVDmk;
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4625 llvm_unreachable("Unknown 4-byte regclass");
4626 case 8:
4627 if (X86::GR64RegClass.hasSubClassEq(RC))
4628 return load ? X86::MOV64rm : X86::MOV64mr;
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4629 if (X86::FR64XRegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4630 return load ?
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4631 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4632 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4633 if (X86::VR64RegClass.hasSubClassEq(RC))
4634 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4635 if (X86::RFP64RegClass.hasSubClassEq(RC))
4636 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
Craig Topperda50eec2016-08-01 04:29:11 +0000[diff] [blame]4637 if (X86::VK64RegClass.hasSubClassEq(RC))
4638 return load ? X86::KMOVQkm : X86::KMOVQmk;
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4639 llvm_unreachable("Unknown 8-byte regclass");
4640 case 10:
4641 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4642 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4643 case 16: {
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4644 assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4645 // If stack is realigned we can use aligned stores.
4646 if (isStackAligned)
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4647 return load ?
4648 (HasVLX ? X86::VMOVAPSZ128rm : HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm):
4649 (HasVLX ? X86::VMOVAPSZ128mr : HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4650 else
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4651 return load ?
4652 (HasVLX ? X86::VMOVUPSZ128rm : HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm):
4653 (HasVLX ? X86::VMOVUPSZ128mr : HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4654 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4655 case 32:
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4656 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4657 // If stack is realigned we can use aligned stores.
4658 if (isStackAligned)
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4659 return load ?
4660 (HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm) :
4661 (HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr);
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4662 else
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4663 return load ?
4664 (HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm) :
4665 (HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr);
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4666 case 64:
4667 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
Craig Topper338ec9a2016-07-31 20:19:53 +0000[diff] [blame]4668 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4669 if (isStackAligned)
4670 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4671 else
4672 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4673 }
4674}
4675
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4676bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
Chad Rosierc27a18f2016-03-09 16:00:35 +0000[diff] [blame]4677 int64_t &Offset,
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4678 const TargetRegisterInfo *TRI) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4679 const MCInstrDesc &Desc = MemOp.getDesc();
Craig Topper477649a2016-04-28 05:58:46 +0000[diff] [blame]4680 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4681 if (MemRefBegin < 0)
4682 return false;
4683
4684 MemRefBegin += X86II::getOperandBias(Desc);
4685
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4686 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
Sanjoy Das881de4d2016-02-02 02:32:43 +0000[diff] [blame]4687 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4688 return false;
4689
4690 BaseReg = BaseMO.getReg();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4691 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4692 return false;
4693
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4694 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4695 X86::NoRegister)
4696 return false;
4697
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4698 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4699
4700 // Displacement can be symbolic
4701 if (!DispMO.isImm())
4702 return false;
4703
4704 Offset = DispMO.getImm();
4705
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4706 return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4707 X86::NoRegister;
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4708}
4709
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4710static unsigned getStoreRegOpcode(unsigned SrcReg,
4711 const TargetRegisterClass *RC,
4712 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4713 const X86Subtarget &STI) {
4714 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4715}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4716
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4717
4718static unsigned getLoadRegOpcode(unsigned DestReg,
4719 const TargetRegisterClass *RC,
4720 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4721 const X86Subtarget &STI) {
4722 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4723}
4724
4725void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4726 MachineBasicBlock::iterator MI,
4727 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4728 const TargetRegisterClass *RC,
4729 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4730 const MachineFunction &MF = *MBB.getParent();
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]4731 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4732 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4733 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4734 bool isAligned =
4735 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4736 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4737 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4738 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4739 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4740 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4741}
4742
4743void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4744 bool isKill,
4745 SmallVectorImpl<MachineOperand> &Addr,
4746 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4747 MachineInstr::mmo_iterator MMOBegin,
4748 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4749 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4750 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4751 bool isAligned = MMOBegin != MMOEnd &&
4752 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4753 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4754 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4755 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4756 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4757 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4758 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4759 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4760 NewMIs.push_back(MIB);
4761}
4762
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4763
4764void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4765 MachineBasicBlock::iterator MI,
4766 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4767 const TargetRegisterClass *RC,
4768 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4769 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4770 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4771 bool isAligned =
4772 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4773 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4774 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4775 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4776 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4777}
4778
4779void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4780 SmallVectorImpl<MachineOperand> &Addr,
4781 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4782 MachineInstr::mmo_iterator MMOBegin,
4783 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4784 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4785 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4786 bool isAligned = MMOBegin != MMOEnd &&
4787 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4788 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4789 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4790 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4791 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4792 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4793 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4794 NewMIs.push_back(MIB);
4795}
4796
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4797bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
4798 unsigned &SrcReg2, int &CmpMask,
4799 int &CmpValue) const {
4800 switch (MI.getOpcode()) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4801 default: break;
4802 case X86::CMP64ri32:
4803 case X86::CMP64ri8:
4804 case X86::CMP32ri:
4805 case X86::CMP32ri8:
4806 case X86::CMP16ri:
4807 case X86::CMP16ri8:
4808 case X86::CMP8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4809 SrcReg = MI.getOperand(0).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4810 SrcReg2 = 0;
4811 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4812 CmpValue = MI.getOperand(1).getImm();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4813 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4814 // A SUB can be used to perform comparison.
4815 case X86::SUB64rm:
4816 case X86::SUB32rm:
4817 case X86::SUB16rm:
4818 case X86::SUB8rm:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4819 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4820 SrcReg2 = 0;
4821 CmpMask = ~0;
4822 CmpValue = 0;
4823 return true;
4824 case X86::SUB64rr:
4825 case X86::SUB32rr:
4826 case X86::SUB16rr:
4827 case X86::SUB8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4828 SrcReg = MI.getOperand(1).getReg();
4829 SrcReg2 = MI.getOperand(2).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4830 CmpMask = ~0;
4831 CmpValue = 0;
4832 return true;
4833 case X86::SUB64ri32:
4834 case X86::SUB64ri8:
4835 case X86::SUB32ri:
4836 case X86::SUB32ri8:
4837 case X86::SUB16ri:
4838 case X86::SUB16ri8:
4839 case X86::SUB8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4840 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4841 SrcReg2 = 0;
4842 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4843 CmpValue = MI.getOperand(2).getImm();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4844 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4845 case X86::CMP64rr:
4846 case X86::CMP32rr:
4847 case X86::CMP16rr:
4848 case X86::CMP8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4849 SrcReg = MI.getOperand(0).getReg();
4850 SrcReg2 = MI.getOperand(1).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4851 CmpMask = ~0;
4852 CmpValue = 0;
4853 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4854 case X86::TEST8rr:
4855 case X86::TEST16rr:
4856 case X86::TEST32rr:
4857 case X86::TEST64rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4858 SrcReg = MI.getOperand(0).getReg();
4859 if (MI.getOperand(1).getReg() != SrcReg)
4860 return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4861 // Compare against zero.
4862 SrcReg2 = 0;
4863 CmpMask = ~0;
4864 CmpValue = 0;
4865 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4866 }
4867 return false;
4868}
4869
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4870/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4871/// purpose is to update flags, can be made redundant.
4872/// CMPrr can be made redundant by SUBrr if the operands are the same.
4873/// This function can be extended later on.
4874/// SrcReg, SrcRegs: register operands for FlagI.
4875/// ImmValue: immediate for FlagI if it takes an immediate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4876inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4877 unsigned SrcReg2, int ImmValue,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4878 MachineInstr &OI) {
4879 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
4880 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
4881 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
4882 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
4883 ((OI.getOperand(1).getReg() == SrcReg &&
4884 OI.getOperand(2).getReg() == SrcReg2) ||
4885 (OI.getOperand(1).getReg() == SrcReg2 &&
4886 OI.getOperand(2).getReg() == SrcReg)))
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4887 return true;
4888
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4889 if (((FlagI.getOpcode() == X86::CMP64ri32 &&
4890 OI.getOpcode() == X86::SUB64ri32) ||
4891 (FlagI.getOpcode() == X86::CMP64ri8 &&
4892 OI.getOpcode() == X86::SUB64ri8) ||
4893 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
4894 (FlagI.getOpcode() == X86::CMP32ri8 &&
4895 OI.getOpcode() == X86::SUB32ri8) ||
4896 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
4897 (FlagI.getOpcode() == X86::CMP16ri8 &&
4898 OI.getOpcode() == X86::SUB16ri8) ||
4899 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
4900 OI.getOperand(1).getReg() == SrcReg &&
4901 OI.getOperand(2).getImm() == ImmValue)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4902 return true;
4903 return false;
4904}
4905
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4906/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4907/// to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4908inline static bool isDefConvertible(MachineInstr &MI) {
4909 switch (MI.getOpcode()) {
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4910 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]4911
4912 // The shift instructions only modify ZF if their shift count is non-zero.
4913 // N.B.: The processor truncates the shift count depending on the encoding.
4914 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4915 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4916 return getTruncatedShiftCount(MI, 2) != 0;
4917
4918 // Some left shift instructions can be turned into LEA instructions but only
4919 // if their flags aren't used. Avoid transforming such instructions.
4920 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4921 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4922 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4923 return ShAmt != 0;
4924 }
4925
4926 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4927 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4928 return getTruncatedShiftCount(MI, 3) != 0;
4929
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4930 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4931 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4932 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4933 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4934 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4935 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4936 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4937 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4938 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4939 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4940 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4941 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4942 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4943 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4944 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4945 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4946 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4947 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4948 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4949 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4950 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4951 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4952 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4953 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4954 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4955 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4956 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4957 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4958 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4959 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4960 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4961 case X86::ADC32ri: case X86::ADC32ri8:
4962 case X86::ADC32rr: case X86::ADC64ri32:
4963 case X86::ADC64ri8: case X86::ADC64rr:
4964 case X86::SBB32ri: case X86::SBB32ri8:
4965 case X86::SBB32rr: case X86::SBB64ri32:
4966 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]4967 case X86::ANDN32rr: case X86::ANDN32rm:
4968 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4969 case X86::BEXTR32rr: case X86::BEXTR64rr:
4970 case X86::BEXTR32rm: case X86::BEXTR64rm:
4971 case X86::BLSI32rr: case X86::BLSI32rm:
4972 case X86::BLSI64rr: case X86::BLSI64rm:
4973 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4974 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4975 case X86::BLSR32rr: case X86::BLSR32rm:
4976 case X86::BLSR64rr: case X86::BLSR64rm:
4977 case X86::BZHI32rr: case X86::BZHI32rm:
4978 case X86::BZHI64rr: case X86::BZHI64rm:
4979 case X86::LZCNT16rr: case X86::LZCNT16rm:
4980 case X86::LZCNT32rr: case X86::LZCNT32rm:
4981 case X86::LZCNT64rr: case X86::LZCNT64rm:
4982 case X86::POPCNT16rr:case X86::POPCNT16rm:
4983 case X86::POPCNT32rr:case X86::POPCNT32rm:
4984 case X86::POPCNT64rr:case X86::POPCNT64rm:
4985 case X86::TZCNT16rr: case X86::TZCNT16rm:
4986 case X86::TZCNT32rr: case X86::TZCNT32rm:
4987 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4988 return true;
4989 }
4990}
4991
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4992/// Check whether the use can be converted to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4993static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
4994 switch (MI.getOpcode()) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4995 default: return X86::COND_INVALID;
4996 case X86::LZCNT16rr: case X86::LZCNT16rm:
4997 case X86::LZCNT32rr: case X86::LZCNT32rm:
4998 case X86::LZCNT64rr: case X86::LZCNT64rm:
4999 return X86::COND_B;
5000 case X86::POPCNT16rr:case X86::POPCNT16rm:
5001 case X86::POPCNT32rr:case X86::POPCNT32rm:
5002 case X86::POPCNT64rr:case X86::POPCNT64rm:
5003 return X86::COND_E;
5004 case X86::TZCNT16rr: case X86::TZCNT16rm:
5005 case X86::TZCNT32rr: case X86::TZCNT32rm:
5006 case X86::TZCNT64rr: case X86::TZCNT64rm:
5007 return X86::COND_B;
5008 }
5009}
5010
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5011/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5012/// operates on the same source operands and sets flags in the same way as
5013/// Compare; remove Compare if possible.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5014bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5015 unsigned SrcReg2, int CmpMask,
5016 int CmpValue,
5017 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5018 // Check whether we can replace SUB with CMP.
5019 unsigned NewOpcode = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5020 switch (CmpInstr.getOpcode()) {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5021 default: break;
5022 case X86::SUB64ri32:
5023 case X86::SUB64ri8:
5024 case X86::SUB32ri:
5025 case X86::SUB32ri8:
5026 case X86::SUB16ri:
5027 case X86::SUB16ri8:
5028 case X86::SUB8ri:
5029 case X86::SUB64rm:
5030 case X86::SUB32rm:
5031 case X86::SUB16rm:
5032 case X86::SUB8rm:
5033 case X86::SUB64rr:
5034 case X86::SUB32rr:
5035 case X86::SUB16rr:
5036 case X86::SUB8rr: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5037 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5038 return false;
5039 // There is no use of the destination register, we can replace SUB with CMP.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5040 switch (CmpInstr.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5041 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5042 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5043 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5044 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5045 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5046 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5047 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5048 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5049 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5050 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5051 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5052 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5053 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5054 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5055 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5056 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5057 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5058 CmpInstr.setDesc(get(NewOpcode));
5059 CmpInstr.RemoveOperand(0);
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5060 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5061 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5062 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5063 return false;
5064 }
5065 }
5066
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5067 // Get the unique definition of SrcReg.
5068 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5069 if (!MI) return false;
5070
5071 // CmpInstr is the first instruction of the BB.
5072 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5073
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5074 // If we are comparing against zero, check whether we can use MI to update
5075 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5076 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5077 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5078 return false;
5079
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5080 // If we have a use of the source register between the def and our compare
5081 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5082 // right way.
5083 bool ShouldUpdateCC = false;
5084 X86::CondCode NewCC = X86::COND_INVALID;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5085 if (IsCmpZero && !isDefConvertible(*MI)) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5086 // Scan forward from the use until we hit the use we're looking for or the
5087 // compare instruction.
5088 for (MachineBasicBlock::iterator J = MI;; ++J) {
5089 // Do we have a convertible instruction?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5090 NewCC = isUseDefConvertible(*J);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5091 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5092 J->getOperand(1).getReg() == SrcReg) {
5093 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5094 ShouldUpdateCC = true; // Update CC later on.
5095 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5096 // with the new def.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]5097 Def = J;
5098 MI = &*Def;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5099 break;
5100 }
5101
5102 if (J == I)
5103 return false;
5104 }
5105 }
5106
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5107 // We are searching for an earlier instruction that can make CmpInstr
5108 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5109 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5110 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5111
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5112 // We iterate backward, starting from the instruction before CmpInstr and
5113 // stop when reaching the definition of a source register or done with the BB.
5114 // RI points to the instruction before CmpInstr.
5115 // If the definition is in this basic block, RE points to the definition;
5116 // otherwise, RE is the rend of the basic block.
5117 MachineBasicBlock::reverse_iterator
5118 RI = MachineBasicBlock::reverse_iterator(I),
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5119 RE = CmpInstr.getParent() == MI->getParent()
5120 ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5121 : CmpInstr.getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5122 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5123 for (; RI != RE; ++RI) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5124 MachineInstr &Instr = *RI;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5125 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5126 if (!IsCmpZero &&
5127 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5128 Sub = &Instr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5129 break;
5130 }
5131
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5132 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5133 Instr.readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5134 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5135
5136 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5137 // They are safe to move up, if the definition to EFLAGS is dead and
5138 // earlier instructions do not read or write EFLAGS.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5139 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5140 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5141 Movr0Inst = &Instr;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5142 continue;
5143 }
5144
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5145 // We can't remove CmpInstr.
5146 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5147 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5148 }
5149
5150 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5151 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5152 return false;
5153
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5154 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5155 Sub->getOperand(2).getReg() == SrcReg);
5156
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5157 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5158 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5159 // If we are done with the basic block, we need to check whether EFLAGS is
5160 // live-out.
5161 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5162 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5163 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5164 for (++I; I != E; ++I) {
5165 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5166 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5167 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5168 // We should check the usage if this instruction uses and updates EFLAGS.
5169 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5170 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5171 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5172 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5173 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5174 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5175 continue;
5176
5177 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5178 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5179 bool OpcIsSET = false;
5180 if (IsCmpZero || IsSwapped) {
5181 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5182 if (Instr.isBranch())
5183 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5184 else {
5185 OldCC = getCondFromSETOpc(Instr.getOpcode());
5186 if (OldCC != X86::COND_INVALID)
5187 OpcIsSET = true;
5188 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5189 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5190 }
5191 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5192 }
5193 if (IsCmpZero) {
5194 switch (OldCC) {
5195 default: break;
5196 case X86::COND_A: case X86::COND_AE:
5197 case X86::COND_B: case X86::COND_BE:
5198 case X86::COND_G: case X86::COND_GE:
5199 case X86::COND_L: case X86::COND_LE:
5200 case X86::COND_O: case X86::COND_NO:
5201 // CF and OF are used, we can't perform this optimization.
5202 return false;
5203 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5204
5205 // If we're updating the condition code check if we have to reverse the
5206 // condition.
5207 if (ShouldUpdateCC)
5208 switch (OldCC) {
5209 default:
5210 return false;
5211 case X86::COND_E:
5212 break;
5213 case X86::COND_NE:
5214 NewCC = GetOppositeBranchCondition(NewCC);
5215 break;
5216 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5217 } else if (IsSwapped) {
5218 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5219 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5220 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5221 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5222 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5223 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5224
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5225 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5226 // Synthesize the new opcode.
5227 bool HasMemoryOperand = Instr.hasOneMemOperand();
5228 unsigned NewOpc;
5229 if (Instr.isBranch())
5230 NewOpc = GetCondBranchFromCond(NewCC);
5231 else if(OpcIsSET)
5232 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5233 else {
5234 unsigned DstReg = Instr.getOperand(0).getReg();
5235 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5236 HasMemoryOperand);
5237 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5238
5239 // Push the MachineInstr to OpsToUpdate.
5240 // If it is safe to remove CmpInstr, the condition code of these
5241 // instructions will be modified.
5242 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5243 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5244 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5245 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5246 IsSafe = true;
5247 break;
5248 }
5249 }
5250
5251 // If EFLAGS is not killed nor re-defined, we should check whether it is
5252 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5253 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5254 MachineBasicBlock *MBB = CmpInstr.getParent();
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5255 for (MachineBasicBlock *Successor : MBB->successors())
5256 if (Successor->isLiveIn(X86::EFLAGS))
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5257 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5258 }
5259
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5260 // The instruction to be updated is either Sub or MI.
5261 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5262 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5263 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5264 // Look backwards until we find a def that doesn't use the current EFLAGS.
5265 Def = Sub;
5266 MachineBasicBlock::reverse_iterator
5267 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5268 InsertE = Sub->getParent()->rend();
5269 for (; InsertI != InsertE; ++InsertI) {
5270 MachineInstr *Instr = &*InsertI;
5271 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5272 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5273 Sub->getParent()->remove(Movr0Inst);
5274 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5275 Movr0Inst);
5276 break;
5277 }
5278 }
5279 if (InsertI == InsertE)
5280 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5281 }
5282
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5283 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5284 unsigned i = 0, e = Sub->getNumOperands();
5285 for (; i != e; ++i) {
5286 MachineOperand &MO = Sub->getOperand(i);
5287 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5288 MO.setIsDead(false);
5289 break;
5290 }
5291 }
5292 assert(i != e && "Unable to locate a def EFLAGS operand");
5293
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5294 CmpInstr.eraseFromParent();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5295
5296 // Modify the condition code of instructions in OpsToUpdate.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5297 for (auto &Op : OpsToUpdate)
5298 Op.first->setDesc(get(Op.second));
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5299 return true;
5300}
5301
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5302/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5303/// operand at the use. We fold the load instructions if load defines a virtual
5304/// register, the virtual register is used once in the same BB, and the
5305/// instructions in-between do not load or store, and have no side effects.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5306MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5307 const MachineRegisterInfo *MRI,
5308 unsigned &FoldAsLoadDefReg,
5309 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5310 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5311 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5312 // To be conservative, if there exists another load, clear the load candidate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5313 if (MI.mayLoad()) {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5314 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5315 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5316 }
5317
5318 // Check whether we can move DefMI here.
5319 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5320 assert(DefMI);
5321 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5322 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5323 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5324
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5325 // Collect information about virtual register operands of MI.
5326 unsigned SrcOperandId = 0;
5327 bool FoundSrcOperand = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5328 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5329 MachineOperand &MO = MI.getOperand(i);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5330 if (!MO.isReg())
5331 continue;
5332 unsigned Reg = MO.getReg();
5333 if (Reg != FoldAsLoadDefReg)
5334 continue;
5335 // Do not fold if we have a subreg use or a def or multiple uses.
5336 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5337 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5338
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5339 SrcOperandId = i;
5340 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5341 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5342 if (!FoundSrcOperand)
5343 return nullptr;
5344
5345 // Check whether we can fold the def into SrcOperandId.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5346 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5347 FoldAsLoadDefReg = 0;
5348 return FoldMI;
5349 }
5350
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5351 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5352}
5353
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5354/// Expand a single-def pseudo instruction to a two-addr
5355/// instruction with two undef reads of the register being defined.
5356/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5357/// %xmm4 = V_SET0
5358/// to:
5359/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5360///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5361static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5362 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5363 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5364 unsigned Reg = MIB->getOperand(0).getReg();
5365 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5366
5367 // MachineInstr::addOperand() will insert explicit operands before any
5368 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5369 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5370 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5371 assert(MIB->getOperand(1).getReg() == Reg &&
5372 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5373 return true;
5374}
5375
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5376/// Expand a single-def pseudo instruction to a two-addr
5377/// instruction with two %k0 reads.
5378/// This is used for mapping:
5379/// %k4 = K_SET1
5380/// to:
5381/// %k4 = KXNORrr %k0, %k0
5382static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5383 const MCInstrDesc &Desc, unsigned Reg) {
5384 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5385 MIB->setDesc(Desc);
5386 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5387 return true;
5388}
5389
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5390static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5391 bool MinusOne) {
5392 MachineBasicBlock &MBB = *MIB->getParent();
5393 DebugLoc DL = MIB->getDebugLoc();
5394 unsigned Reg = MIB->getOperand(0).getReg();
5395
5396 // Insert the XOR.
5397 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5398 .addReg(Reg, RegState::Undef)
5399 .addReg(Reg, RegState::Undef);
5400
5401 // Turn the pseudo into an INC or DEC.
5402 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5403 MIB.addReg(Reg);
5404
5405 return true;
5406}
5407
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5408bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5409 MachineBasicBlock &MBB = *MIB->getParent();
5410 DebugLoc DL = MIB->getDebugLoc();
5411 int64_t Imm = MIB->getOperand(1).getImm();
5412 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5413 MachineBasicBlock::iterator I = MIB.getInstr();
5414
5415 int StackAdjustment;
5416
5417 if (Subtarget.is64Bit()) {
5418 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5419 MIB->getOpcode() == X86::MOV32ImmSExti8);
5420
5421 // Can't use push/pop lowering if the function might write to the red zone.
5422 X86MachineFunctionInfo *X86FI =
5423 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5424 if (X86FI->getUsesRedZone()) {
5425 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5426 : X86::MOV64ri));
5427 return true;
5428 }
5429
5430 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5431 // widen the register if necessary.
5432 StackAdjustment = 8;
5433 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5434 MIB->setDesc(get(X86::POP64r));
5435 MIB->getOperand(0)
5436 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5437 } else {
5438 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5439 StackAdjustment = 4;
5440 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5441 MIB->setDesc(get(X86::POP32r));
5442 }
5443
5444 // Build CFI if necessary.
5445 MachineFunction &MF = *MBB.getParent();
5446 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5447 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5448 bool NeedsDwarfCFI =
5449 !IsWin64Prologue &&
5450 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5451 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5452 if (EmitCFI) {
5453 TFL->BuildCFI(MBB, I, DL,
5454 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5455 TFL->BuildCFI(MBB, std::next(I), DL,
5456 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5457 }
5458
5459 return true;
5460}
5461
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5462// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5463// code sequence is needed for other targets.
5464static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5465 const TargetInstrInfo &TII) {
5466 MachineBasicBlock &MBB = *MIB->getParent();
5467 DebugLoc DL = MIB->getDebugLoc();
5468 unsigned Reg = MIB->getOperand(0).getReg();
5469 const GlobalValue *GV =
5470 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5471 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5472 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5473 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5474 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5475
5476 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5477 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5478 .addMemOperand(MMO);
5479 MIB->setDebugLoc(DL);
5480 MIB->setDesc(TII.get(X86::MOV64rm));
5481 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5482}
5483
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5484bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5485 bool HasAVX = Subtarget.hasAVX();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5486 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5487 switch (MI.getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5488 case X86::MOV32r0:
5489 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5490 case X86::MOV32r1:
5491 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5492 case X86::MOV32r_1:
5493 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5494 case X86::MOV32ImmSExti8:
5495 case X86::MOV64ImmSExti8:
5496 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5497 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5498 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5499 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5500 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5501 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5502 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5503 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5504 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5505 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5506 case X86::FsFLD0SS:
5507 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5508 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5509 case X86::AVX_SET0:
5510 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5511 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Craig Toppere5ce84a2016-05-08 21:33:53 +0000[diff] [blame]5512 case X86::AVX512_128_SET0:
5513 return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5514 case X86::AVX512_256_SET0:
5515 return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5516 case X86::AVX512_512_SET0:
5517 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5518 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5519 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5520 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5521 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]5522 case X86::AVX512_512_SETALLONES: {
5523 unsigned Reg = MIB->getOperand(0).getReg();
5524 MIB->setDesc(get(X86::VPTERNLOGDZrri));
5525 // VPTERNLOGD needs 3 register inputs and an immediate.
5526 // 0xff will return 1s for any input.
5527 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5528 .addReg(Reg, RegState::Undef).addImm(0xff);
5529 return true;
5530 }
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5531 case X86::TEST8ri_NOREX:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5532 MI.setDesc(get(X86::TEST8ri));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5533 return true;
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5534 case X86::MOV32ri64:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5535 MI.setDesc(get(X86::MOV32ri));
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5536 return true;
5537
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5538 // KNL does not recognize dependency-breaking idioms for mask registers,
5539 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5540 // Using %k0 as the undef input register is a performance heuristic based
5541 // on the assumption that %k0 is used less frequently than the other mask
5542 // registers, since it is not usable as a write mask.
5543 // FIXME: A more advanced approach would be to choose the best input mask
5544 // register based on context.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5545 case X86::KSET0B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5546 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5547 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5548 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5549 case X86::KSET1B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5550 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5551 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5552 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5553 case TargetOpcode::LOAD_STACK_GUARD:
5554 expandLoadStackGuard(MIB, *this);
5555 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5556 }
5557 return false;
5558}
5559
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5560static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5561 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5562 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5563
5564 if (NumAddrOps < 4) {
5565 // FrameIndex only - add an immediate offset (whether its zero or not).
5566 for (unsigned i = 0; i != NumAddrOps; ++i)
5567 MIB.addOperand(MOs[i]);
5568 addOffset(MIB, PtrOffset);
5569 } else {
5570 // General Memory Addressing - we need to add any offset to an existing
5571 // offset.
5572 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5573 for (unsigned i = 0; i != NumAddrOps; ++i) {
5574 const MachineOperand &MO = MOs[i];
5575 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5576 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5577 } else {
5578 MIB.addOperand(MO);
5579 }
5580 }
5581 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5582}
5583
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5584static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5585 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5586 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5587 MachineInstr &MI,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5588 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5589 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5590 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5591 MachineInstr *NewMI =
5592 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5593 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5594 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5595
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5596 // Loop over the rest of the ri operands, converting them over.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5597 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5598 for (unsigned i = 0; i != NumOps; ++i) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5599 MachineOperand &MO = MI.getOperand(i + 2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5600 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5601 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5602 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5603 MachineOperand &MO = MI.getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5604 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5605 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5606
5607 MachineBasicBlock *MBB = InsertPt->getParent();
5608 MBB->insert(InsertPt, NewMI);
5609
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5610 return MIB;
5611}
5612
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5613static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5614 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5615 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5616 MachineInstr &MI, const TargetInstrInfo &TII,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5617 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5618 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5619 MachineInstr *NewMI =
5620 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5621 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5622
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5623 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5624 MachineOperand &MO = MI.getOperand(i);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5625 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5626 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5627 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5628 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5629 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5630 }
5631 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5632
5633 MachineBasicBlock *MBB = InsertPt->getParent();
5634 MBB->insert(InsertPt, NewMI);
5635
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5636 return MIB;
5637}
5638
5639static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5640 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5641 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5642 MachineInstr &MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5643 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5644 MI.getDebugLoc(), TII.get(Opcode));
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5645 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5646 return MIB.addImm(0);
5647}
5648
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5649MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5650 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5651 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5652 unsigned Size, unsigned Align) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5653 switch (MI.getOpcode()) {
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5654 case X86::INSERTPSrr:
5655 case X86::VINSERTPSrr:
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5656 case X86::VINSERTPSZrr:
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5657 // Attempt to convert the load of inserted vector into a fold load
5658 // of a single float.
5659 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5660 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5661 unsigned ZMask = Imm & 15;
5662 unsigned DstIdx = (Imm >> 4) & 3;
5663 unsigned SrcIdx = (Imm >> 6) & 3;
5664
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5665 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5666 if (Size <= RCSize && 4 <= Align) {
5667 int PtrOffset = SrcIdx * 4;
5668 unsigned NewImm = (DstIdx << 4) | ZMask;
5669 unsigned NewOpCode =
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5670 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5671 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
5672 X86::INSERTPSrm;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5673 MachineInstr *NewMI =
5674 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5675 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5676 return NewMI;
5677 }
5678 }
5679 break;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5680 case X86::MOVHLPSrr:
5681 case X86::VMOVHLPSrr:
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5682 case X86::VMOVHLPSZrr:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5683 // Move the upper 64-bits of the second operand to the lower 64-bits.
5684 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5685 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5686 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5687 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5688 if (Size <= RCSize && 8 <= Align) {
5689 unsigned NewOpCode =
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5690 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5691 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
5692 X86::MOVLPSrm;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5693 MachineInstr *NewMI =
5694 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5695 return NewMI;
5696 }
5697 }
5698 break;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5699 };
5700
5701 return nullptr;
5702}
5703
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5704MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5705 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5706 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5707 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5708 const DenseMap<unsigned,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5709 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5710 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5711 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5712
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5713 // For CPUs that favor the register form of a call or push,
5714 // do not fold loads into calls or pushes, unless optimizing for size
5715 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5716 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5717 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5718 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5719 MI.getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5720 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5721
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5722 unsigned NumOps = MI.getDesc().getNumOperands();
5723 bool isTwoAddr =
5724 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5725
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5726 // FIXME: AsmPrinter doesn't know how to handle
5727 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5728 if (MI.getOpcode() == X86::ADD32ri &&
5729 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5730 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5731
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5732 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5733
5734 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5735 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5736 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5737 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5738
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5739 // Folding a memory location into the two-address part of a two-address
5740 // instruction is different than folding it other places. It requires
5741 // replacing the *two* registers with the memory location.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5742 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5743 MI.getOperand(1).isReg() &&
5744 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5745 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5746 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5747 } else if (OpNum == 0) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5748 if (MI.getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5749 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5750 if (NewMI)
5751 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5752 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5753
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5754 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5755 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5756 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5757 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5758 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5759 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]5760 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5761 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]5762 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5763 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5764
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5765 // If table selected...
5766 if (OpcodeTablePtr) {
5767 // Find the Opcode to fuse
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5768 auto I = OpcodeTablePtr->find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5769 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5770 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5771 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5772 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5773 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5774 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5775 if (Size) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5776 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5777 if (Size < RCSize) {
5778 // Check if it's safe to fold the load. If the size of the object is
5779 // narrower than the load width, then it's not.
5780 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5781 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5782 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5783 // a 32-bit load which is implicitly zero-extended. This likely is
5784 // due to live interval analysis remat'ing a load from stack slot.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5785 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5786 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5787 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5788 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5789 }
5790 }
5791
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5792 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5793 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5794 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5795 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5796
5797 if (NarrowToMOV32rm) {
5798 // If this is the special case where we use a MOV32rm to load a 32-bit
5799 // value and zero-extend the top bits. Change the destination register
5800 // to a 32-bit one.
5801 unsigned DstReg = NewMI->getOperand(0).getReg();
5802 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5803 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5804 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]5805 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5806 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5807 return NewMI;
5808 }
5809 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5810
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5811 // If the instruction and target operand are commutable, commute the
5812 // instruction and try again.
5813 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5814 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5815 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5816 bool HasDef = MI.getDesc().getNumDefs();
5817 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
5818 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5819 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5820 bool Tied1 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5821 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5822 bool Tied2 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5823 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5824
5825 // If either of the commutable operands are tied to the destination
5826 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5827 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5828 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5829 return nullptr;
5830
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5831 MachineInstr *CommutedMI =
5832 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5833 if (!CommutedMI) {
5834 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5835 return nullptr;
5836 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5837 if (CommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5838 // New instruction. We can't fold from this.
5839 CommutedMI->eraseFromParent();
5840 return nullptr;
5841 }
5842
5843 // Attempt to fold with the commuted version of the instruction.
5844 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5845 Size, Align, /*AllowCommute=*/false);
5846 if (NewMI)
5847 return NewMI;
5848
5849 // Folding failed again - undo the commute before returning.
5850 MachineInstr *UncommutedMI =
5851 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5852 if (!UncommutedMI) {
5853 // Unable to commute.
5854 return nullptr;
5855 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5856 if (UncommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5857 // New instruction. It doesn't need to be kept.
5858 UncommutedMI->eraseFromParent();
5859 return nullptr;
5860 }
5861
5862 // Return here to prevent duplicate fuse failure report.
5863 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5864 }
5865 }
5866
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5867 // No fusion
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5868 if (PrintFailedFusing && !MI.isCopy())
5869 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5870 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5871}
5872
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5873/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5874/// the first 32 or 64-bits of the destination register and leave the rest
5875/// unmodified. This can be used to avoid folding loads if the instructions
5876/// only update part of the destination register, and the non-updated part is
5877/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5878/// instructions breaks the partial register dependency and it can improve
5879/// performance. e.g.:
5880///
5881/// movss (%rdi), %xmm0
5882/// cvtss2sd %xmm0, %xmm0
5883///
5884/// Instead of
5885/// cvtss2sd (%rdi), %xmm0
5886///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]5887/// FIXME: This should be turned into a TSFlags.
5888///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5889static bool hasPartialRegUpdate(unsigned Opcode) {
5890 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5891 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5892 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5893 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5894 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5895 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5896 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5897 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5898 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5899 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5900 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5901 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5902 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5903 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5904 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5905 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5906 case X86::Int_CVTSS2SDrm:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5907 case X86::MOVHPDrm:
5908 case X86::MOVHPSrm:
5909 case X86::MOVLPDrm:
5910 case X86::MOVLPSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5911 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5912 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5913 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5914 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5915 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5916 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5917 case X86::ROUNDSDr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]5918 case X86::ROUNDSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5919 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5920 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5921 case X86::ROUNDSSr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]5922 case X86::ROUNDSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5923 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5924 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5925 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5926 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5927 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5928 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5929 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5930 case X86::SQRTSSm_Int:
5931 case X86::SQRTSDr:
5932 case X86::SQRTSDm:
5933 case X86::SQRTSDr_Int:
5934 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5935 return true;
5936 }
5937
5938 return false;
5939}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5940
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5941/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5942/// instructions we would like before a partial register update.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5943unsigned X86InstrInfo::getPartialRegUpdateClearance(
5944 const MachineInstr &MI, unsigned OpNum,
5945 const TargetRegisterInfo *TRI) const {
5946 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5947 return 0;
5948
5949 // If MI is marked as reading Reg, the partial register update is wanted.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5950 const MachineOperand &MO = MI.getOperand(0);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5951 unsigned Reg = MO.getReg();
5952 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5953 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5954 return 0;
5955 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5956 if (MI.readsRegister(Reg, TRI))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5957 return 0;
5958 }
5959
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]5960 // If any instructions in the clearance range are reading Reg, insert a
5961 // dependency breaking instruction, which is inexpensive and is likely to
5962 // be hidden in other instruction's cycles.
5963 return PartialRegUpdateClearance;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5964}
5965
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5966// Return true for any instruction the copies the high bits of the first source
5967// operand into the unused high bits of the destination operand.
5968static bool hasUndefRegUpdate(unsigned Opcode) {
5969 switch (Opcode) {
5970 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5971 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5972 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5973 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5974 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5975 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5976 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5977 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5978 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5979 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5980 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5981 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5982 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5983 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5984 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5985 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5986 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5987 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5988 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5989 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5990 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5991 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5992 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5993 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5994 case X86::VRCPSSr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]5995 case X86::VRCPSSr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5996 case X86::VRCPSSm:
5997 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5998 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5999 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6000 case X86::VROUNDSDr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]6001 case X86::VROUNDSDm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6002 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6003 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6004 case X86::VROUNDSSr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]6005 case X86::VROUNDSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6006 case X86::VRSQRTSSr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]6007 case X86::VRSQRTSSr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6008 case X86::VRSQRTSSm:
6009 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6010 case X86::VSQRTSSr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]6011 case X86::VSQRTSSr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6012 case X86::VSQRTSSm:
6013 case X86::VSQRTSSm_Int:
6014 case X86::VSQRTSDr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]6015 case X86::VSQRTSDr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6016 case X86::VSQRTSDm:
6017 case X86::VSQRTSDm_Int:
Craig Topper19505bc2016-08-06 19:31:50 +0000[diff] [blame]6018 // AVX-512
6019 case X86::VCVTSI2SSZrr:
6020 case X86::VCVTSI2SSZrm:
6021 case X86::Int_VCVTSI2SSZrr:
6022 case X86::Int_VCVTSI2SSZrm:
6023 case X86::VCVTSI2SSZrr_Int:
6024 case X86::VCVTSI2SSZrm_Int:
6025 case X86::VCVTSI642SSZrr:
6026 case X86::VCVTSI642SSZrm:
6027 case X86::Int_VCVTSI2SS64Zrr:
6028 case X86::Int_VCVTSI2SS64Zrm:
6029 case X86::VCVTSI642SSZrr_Int:
6030 case X86::VCVTSI642SSZrm_Int:
6031 case X86::VCVTSI2SDZrr:
6032 case X86::VCVTSI2SDZrm:
6033 case X86::Int_VCVTSI2SDZrr:
6034 case X86::Int_VCVTSI2SDZrm:
6035 case X86::VCVTSI2SDZrr_Int:
6036 case X86::VCVTSI2SDZrm_Int:
6037 case X86::VCVTSI642SDZrr:
6038 case X86::VCVTSI642SDZrm:
6039 case X86::Int_VCVTSI2SD64Zrr:
6040 case X86::Int_VCVTSI2SD64Zrm:
6041 case X86::VCVTSI642SDZrr_Int:
6042 case X86::VCVTSI642SDZrm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6043 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6044 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6045 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6046 case X86::VCVTSS2SDZrm:
Craig Topper9d8676a2016-08-06 19:31:52 +0000[diff] [blame]6047 case X86::VRNDSCALESDr:
6048 case X86::VRNDSCALESDm:
6049 case X86::VRNDSCALESSr:
6050 case X86::VRNDSCALESSm:
6051 case X86::VRCP14SSrr:
6052 case X86::VRCP14SSrm:
6053 case X86::VRSQRT14SSrr:
6054 case X86::VRSQRT14SSrm:
6055 case X86::VSQRTSSZr:
6056 case X86::VSQRTSSZr_Int:
6057 case X86::VSQRTSSZm:
6058 case X86::VSQRTSSZm_Int:
6059 case X86::VSQRTSDZr:
6060 case X86::VSQRTSDZr_Int:
6061 case X86::VSQRTSDZm:
6062 case X86::VSQRTSDZm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6063 return true;
6064 }
6065
6066 return false;
6067}
6068
6069/// Inform the ExeDepsFix pass how many idle instructions we would like before
6070/// certain undef register reads.
6071///
6072/// This catches the VCVTSI2SD family of instructions:
6073///
6074/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6075///
6076/// We should to be careful *not* to catch VXOR idioms which are presumably
6077/// handled specially in the pipeline:
6078///
6079/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6080///
6081/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6082/// high bits that are passed-through are not live.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6083unsigned
6084X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6085 const TargetRegisterInfo *TRI) const {
6086 if (!hasUndefRegUpdate(MI.getOpcode()))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6087 return 0;
6088
6089 // Set the OpNum parameter to the first source operand.
6090 OpNum = 1;
6091
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6092 const MachineOperand &MO = MI.getOperand(OpNum);
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6093 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6094 return UndefRegClearance;
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6095 }
6096 return 0;
6097}
6098
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6099void X86InstrInfo::breakPartialRegDependency(
6100 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6101 unsigned Reg = MI.getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6102 // If MI kills this register, the false dependence is already broken.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6103 if (MI.killsRegister(Reg, TRI))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6104 return;
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6105
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6106 if (X86::VR128RegClass.contains(Reg)) {
6107 // These instructions are all floating point domain, so xorps is the best
6108 // choice.
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6109 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6110 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6111 .addReg(Reg, RegState::Undef)
6112 .addReg(Reg, RegState::Undef);
6113 MI.addRegisterKilled(Reg, TRI, true);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6114 } else if (X86::VR256RegClass.contains(Reg)) {
6115 // Use vxorps to clear the full ymm register.
6116 // It wants to read and write the xmm sub-register.
6117 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6118 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6119 .addReg(XReg, RegState::Undef)
6120 .addReg(XReg, RegState::Undef)
6121 .addReg(Reg, RegState::ImplicitDefine);
6122 MI.addRegisterKilled(Reg, TRI, true);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6123 }
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6124}
6125
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6126MachineInstr *
6127X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6128 ArrayRef<unsigned> Ops,
6129 MachineBasicBlock::iterator InsertPt,
6130 int FrameIndex, LiveIntervals *LIS) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6131 // Check switch flag
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6132 if (NoFusing)
6133 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6134
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6135 // Unless optimizing for size, don't fold to avoid partial
6136 // register update stalls
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6137 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6138 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6139
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]6140 const MachineFrameInfo &MFI = MF.getFrameInfo();
6141 unsigned Size = MFI.getObjectSize(FrameIndex);
6142 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]6143 // If the function stack isn't realigned we don't want to fold instructions
6144 // that need increased alignment.
6145 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6146 Alignment =
6147 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6148 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6149 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6150 unsigned RCSize = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6151 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6152 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6153 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]6154 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6155 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6156 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6157 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6158 // Check if it's safe to fold the load. If the size of the object is
6159 // narrower than the load width, then it's not.
6160 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6161 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6162 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6163 MI.setDesc(get(NewOpc));
6164 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6165 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6166 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6167
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]6168 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6169 MachineOperand::CreateFI(FrameIndex), InsertPt,
6170 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6171}
6172
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6173/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6174/// because the latter uses contents that wouldn't be defined in the folded
6175/// version. For instance, this transformation isn't legal:
6176/// movss (%rdi), %xmm0
6177/// addps %xmm0, %xmm0
6178/// ->
6179/// addps (%rdi), %xmm0
6180///
6181/// But this one is:
6182/// movss (%rdi), %xmm0
6183/// addss %xmm0, %xmm0
6184/// ->
6185/// addss (%rdi), %xmm0
6186///
6187static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6188 const MachineInstr &UserMI,
6189 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6190 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6191 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6192 unsigned RegSize =
6193 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6194
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6195 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
6196 RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6197 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6198 // destination register is wider than 32 bits (4 bytes), and its user
6199 // instruction isn't scalar (SS).
6200 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6201 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
Craig Topper8f27f512016-08-26 07:08:00 +0000[diff] [blame]6202 case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6203 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
Simon Pilgrime14653e2016-08-24 18:40:53 +0000[diff] [blame]6204 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
6205 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6206 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6207 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]6208 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
6209 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
6210 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
6211 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
6212 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
6213 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6214 return false;
6215 default:
6216 return true;
6217 }
6218 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6219
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6220 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
6221 RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6222 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6223 // destination register is wider than 64 bits (8 bytes), and its user
6224 // instruction isn't scalar (SD).
6225 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6226 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
Craig Topper8f27f512016-08-26 07:08:00 +0000[diff] [blame]6227 case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6228 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
Simon Pilgrime14653e2016-08-24 18:40:53 +0000[diff] [blame]6229 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6230 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6231 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6232 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]6233 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
6234 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
6235 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
6236 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
6237 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
6238 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6239 return false;
6240 default:
6241 return true;
6242 }
6243 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6244
6245 return false;
6246}
6247
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6248MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6249 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6250 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6251 LiveIntervals *LIS) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6252 // If loading from a FrameIndex, fold directly from the FrameIndex.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6253 unsigned NumOps = LoadMI.getDesc().getNumOperands();
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6254 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6255 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6256 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6257 return nullptr;
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6258 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6259 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6260
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6261 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6262 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6263
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6264 // Avoid partial register update stalls unless optimizing for size.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6265 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6266 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6267
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6268 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6269 unsigned Alignment = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6270 if (LoadMI.hasOneMemOperand())
6271 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6272 else
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6273 switch (LoadMI.getOpcode()) {
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6274 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6275 case X86::AVX512_512_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6276 Alignment = 64;
6277 break;
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6278 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6279 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6280 case X86::AVX512_256_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6281 Alignment = 32;
6282 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6283 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6284 case X86::V_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6285 case X86::AVX512_128_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6286 Alignment = 16;
6287 break;
6288 case X86::FsFLD0SD:
6289 Alignment = 8;
6290 break;
6291 case X86::FsFLD0SS:
6292 Alignment = 4;
6293 break;
6294 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6295 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6296 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6297 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6298 unsigned NewOpc = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6299 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6300 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6301 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6302 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6303 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6304 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6305 }
6306 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6307 MI.setDesc(get(NewOpc));
6308 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6309 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6310 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6311
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6312 // Make sure the subregisters match.
6313 // Otherwise we risk changing the size of the load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6314 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6315 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6316
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6317 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6318 switch (LoadMI.getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6319 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6320 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6321 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6322 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6323 case X86::AVX512_128_SET0:
6324 case X86::AVX512_256_SET0:
6325 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6326 case X86::AVX512_512_SETALLONES:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6327 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6328 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6329 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6330 // Create a constant-pool entry and operands to load from it.
6331
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6332 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6333 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6334 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6335 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6336
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6337 // x86-32 PIC requires a PIC base register for constant pools.
6338 unsigned PICBase = 0;
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]6339 if (MF.getTarget().isPositionIndependent()) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6340 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6341 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6342 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6343 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6344 // This doesn't work for several reasons.
6345 // 1. GlobalBaseReg may have been spilled.
6346 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6347 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6348 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6349
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6350 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6351 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6352 Type *Ty;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6353 unsigned Opc = LoadMI.getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6354 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6355 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6356 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6357 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6358 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6359 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6360 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6361 Opc == X86::AVX512_256_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6362 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6363 else
6364 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6365
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6366 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6367 Opc == X86::AVX512_512_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6368 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6369 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6370 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6371
6372 // Create operands to load from the constant pool entry.
6373 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6374 MOs.push_back(MachineOperand::CreateImm(1));
6375 MOs.push_back(MachineOperand::CreateReg(0, false));
6376 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6377 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6378 break;
6379 }
6380 default: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6381 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6382 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6383
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6384 // Folding a normal load. Just copy the load's address operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6385 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6386 LoadMI.operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6387 break;
6388 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6389 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6390 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6391 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6392}
6393
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6394bool X86InstrInfo::unfoldMemoryOperand(
6395 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6396 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6397 auto I = MemOp2RegOpTable.find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6398 if (I == MemOp2RegOpTable.end())
6399 return false;
6400 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6401 unsigned Index = I->second.second & TB_INDEX_MASK;
6402 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6403 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6404 if (UnfoldLoad && !FoldedLoad)
6405 return false;
6406 UnfoldLoad &= FoldedLoad;
6407 if (UnfoldStore && !FoldedStore)
6408 return false;
6409 UnfoldStore &= FoldedStore;
6410
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6411 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6412 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6413 // TODO: Check if 32-byte or greater accesses are slow too?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6414 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6415 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6416 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6417 // conservatively assume the address is unaligned. That's bad for
6418 // performance.
6419 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6420 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6421 SmallVector<MachineOperand,2> BeforeOps;
6422 SmallVector<MachineOperand,2> AfterOps;
6423 SmallVector<MachineOperand,4> ImpOps;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6424 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6425 MachineOperand &Op = MI.getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6426 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6427 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6428 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6429 ImpOps.push_back(Op);
6430 else if (i < Index)
6431 BeforeOps.push_back(Op);
6432 else if (i > Index)
6433 AfterOps.push_back(Op);
6434 }
6435
6436 // Emit the load instruction.
6437 if (UnfoldLoad) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6438 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6439 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6440 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6441 if (UnfoldStore) {
6442 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6443 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6444 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6445 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6446 MO.setIsKill(false);
6447 }
6448 }
6449 }
6450
6451 // Emit the data processing instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6452 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6453 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6454
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6455 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6456 MIB.addReg(Reg, RegState::Define);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6457 for (MachineOperand &BeforeOp : BeforeOps)
6458 MIB.addOperand(BeforeOp);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6459 if (FoldedLoad)
6460 MIB.addReg(Reg);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6461 for (MachineOperand &AfterOp : AfterOps)
6462 MIB.addOperand(AfterOp);
6463 for (MachineOperand &ImpOp : ImpOps) {
6464 MIB.addReg(ImpOp.getReg(),
6465 getDefRegState(ImpOp.isDef()) |
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6466 RegState::Implicit |
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6467 getKillRegState(ImpOp.isKill()) |
6468 getDeadRegState(ImpOp.isDead()) |
6469 getUndefRegState(ImpOp.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6470 }
6471 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6472 switch (DataMI->getOpcode()) {
6473 default: break;
6474 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6475 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6476 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6477 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6478 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6479 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6480 case X86::CMP8ri: {
6481 MachineOperand &MO0 = DataMI->getOperand(0);
6482 MachineOperand &MO1 = DataMI->getOperand(1);
6483 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6484 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6485 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6486 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6487 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6488 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6489 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6490 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6491 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6492 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6493 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6494 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6495 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6496 MO1.ChangeToRegister(MO0.getReg(), false);
6497 }
6498 }
6499 }
6500 NewMIs.push_back(DataMI);
6501
6502 // Emit the store instruction.
6503 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6504 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6505 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6506 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6507 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6508 }
6509
6510 return true;
6511}
6512
6513bool
6514X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6515 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6516 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6517 return false;
6518
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6519 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6520 if (I == MemOp2RegOpTable.end())
6521 return false;
6522 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6523 unsigned Index = I->second.second & TB_INDEX_MASK;
6524 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6525 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6526 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6527 MachineFunction &MF = DAG.getMachineFunction();
6528 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6529 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6530 std::vector<SDValue> AddrOps;
6531 std::vector<SDValue> BeforeOps;
6532 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6533 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6534 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6535 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6536 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6537 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6538 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6539 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6540 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6541 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6542 AfterOps.push_back(Op);
6543 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6544 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6545 AddrOps.push_back(Chain);
6546
6547 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6548 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6549 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6550 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6551 std::pair<MachineInstr::mmo_iterator,
6552 MachineInstr::mmo_iterator> MMOs =
6553 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6554 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6555 if (!(*MMOs.first) &&
6556 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6557 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6558 // Do not introduce a slow unaligned load.
6559 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6560 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6561 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6562 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6563 bool isAligned = (*MMOs.first) &&
6564 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6565 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6566 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6567 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6568
6569 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6570 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6571 }
6572
6573 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6574 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6575 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6576 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6577 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6578 VTs.push_back(*DstRC->vt_begin());
6579 }
6580 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6581 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6582 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6583 VTs.push_back(VT);
6584 }
6585 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6586 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6587 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6588 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6589 NewNodes.push_back(NewNode);
6590
6591 // Emit the store instruction.
6592 if (FoldedStore) {
6593 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6594 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6595 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6596 std::pair<MachineInstr::mmo_iterator,
6597 MachineInstr::mmo_iterator> MMOs =
6598 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6599 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6600 if (!(*MMOs.first) &&
6601 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6602 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6603 // Do not introduce a slow unaligned store.
6604 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6605 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6606 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6607 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6608 bool isAligned = (*MMOs.first) &&
6609 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6610 SDNode *Store =
6611 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6612 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6613 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6614
6615 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6616 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6617 }
6618
6619 return true;
6620}
6621
6622unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6623 bool UnfoldLoad, bool UnfoldStore,
6624 unsigned *LoadRegIndex) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6625 auto I = MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6626 if (I == MemOp2RegOpTable.end())
6627 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6628 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6629 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6630 if (UnfoldLoad && !FoldedLoad)
6631 return 0;
6632 if (UnfoldStore && !FoldedStore)
6633 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6634 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6635 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6636 return I->second.first;
6637}
6638
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6639bool
6640X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6641 int64_t &Offset1, int64_t &Offset2) const {
6642 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6643 return false;
6644 unsigned Opc1 = Load1->getMachineOpcode();
6645 unsigned Opc2 = Load2->getMachineOpcode();
6646 switch (Opc1) {
6647 default: return false;
6648 case X86::MOV8rm:
6649 case X86::MOV16rm:
6650 case X86::MOV32rm:
6651 case X86::MOV64rm:
6652 case X86::LD_Fp32m:
6653 case X86::LD_Fp64m:
6654 case X86::LD_Fp80m:
6655 case X86::MOVSSrm:
6656 case X86::MOVSDrm:
6657 case X86::MMX_MOVD64rm:
6658 case X86::MMX_MOVQ64rm:
6659 case X86::FsMOVAPSrm:
6660 case X86::FsMOVAPDrm:
6661 case X86::MOVAPSrm:
6662 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6663 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6664 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6665 case X86::MOVDQArm:
6666 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6667 // AVX load instructions
6668 case X86::VMOVSSrm:
6669 case X86::VMOVSDrm:
6670 case X86::FsVMOVAPSrm:
6671 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6672 case X86::VMOVAPSrm:
6673 case X86::VMOVUPSrm:
6674 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6675 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6676 case X86::VMOVDQArm:
6677 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6678 case X86::VMOVAPSYrm:
6679 case X86::VMOVUPSYrm:
6680 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6681 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6682 case X86::VMOVDQAYrm:
6683 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6684 // AVX512 load instructions
6685 case X86::VMOVSSZrm:
6686 case X86::VMOVSDZrm:
6687 case X86::VMOVAPSZ128rm:
6688 case X86::VMOVUPSZ128rm:
6689 case X86::VMOVAPDZ128rm:
6690 case X86::VMOVUPDZ128rm:
6691 case X86::VMOVDQU8Z128rm:
6692 case X86::VMOVDQU16Z128rm:
6693 case X86::VMOVDQA32Z128rm:
6694 case X86::VMOVDQU32Z128rm:
6695 case X86::VMOVDQA64Z128rm:
6696 case X86::VMOVDQU64Z128rm:
6697 case X86::VMOVAPSZ256rm:
6698 case X86::VMOVUPSZ256rm:
6699 case X86::VMOVAPDZ256rm:
6700 case X86::VMOVUPDZ256rm:
6701 case X86::VMOVDQU8Z256rm:
6702 case X86::VMOVDQU16Z256rm:
6703 case X86::VMOVDQA32Z256rm:
6704 case X86::VMOVDQU32Z256rm:
6705 case X86::VMOVDQA64Z256rm:
6706 case X86::VMOVDQU64Z256rm:
6707 case X86::VMOVAPSZrm:
6708 case X86::VMOVUPSZrm:
6709 case X86::VMOVAPDZrm:
6710 case X86::VMOVUPDZrm:
6711 case X86::VMOVDQU8Zrm:
6712 case X86::VMOVDQU16Zrm:
6713 case X86::VMOVDQA32Zrm:
6714 case X86::VMOVDQU32Zrm:
6715 case X86::VMOVDQA64Zrm:
6716 case X86::VMOVDQU64Zrm:
6717 case X86::KMOVBkm:
6718 case X86::KMOVWkm:
6719 case X86::KMOVDkm:
6720 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6721 break;
6722 }
6723 switch (Opc2) {
6724 default: return false;
6725 case X86::MOV8rm:
6726 case X86::MOV16rm:
6727 case X86::MOV32rm:
6728 case X86::MOV64rm:
6729 case X86::LD_Fp32m:
6730 case X86::LD_Fp64m:
6731 case X86::LD_Fp80m:
6732 case X86::MOVSSrm:
6733 case X86::MOVSDrm:
6734 case X86::MMX_MOVD64rm:
6735 case X86::MMX_MOVQ64rm:
6736 case X86::FsMOVAPSrm:
6737 case X86::FsMOVAPDrm:
6738 case X86::MOVAPSrm:
6739 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6740 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6741 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6742 case X86::MOVDQArm:
6743 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6744 // AVX load instructions
6745 case X86::VMOVSSrm:
6746 case X86::VMOVSDrm:
6747 case X86::FsVMOVAPSrm:
6748 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6749 case X86::VMOVAPSrm:
6750 case X86::VMOVUPSrm:
6751 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6752 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6753 case X86::VMOVDQArm:
6754 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6755 case X86::VMOVAPSYrm:
6756 case X86::VMOVUPSYrm:
6757 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6758 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6759 case X86::VMOVDQAYrm:
6760 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6761 // AVX512 load instructions
6762 case X86::VMOVSSZrm:
6763 case X86::VMOVSDZrm:
6764 case X86::VMOVAPSZ128rm:
6765 case X86::VMOVUPSZ128rm:
6766 case X86::VMOVAPDZ128rm:
6767 case X86::VMOVUPDZ128rm:
6768 case X86::VMOVDQU8Z128rm:
6769 case X86::VMOVDQU16Z128rm:
6770 case X86::VMOVDQA32Z128rm:
6771 case X86::VMOVDQU32Z128rm:
6772 case X86::VMOVDQA64Z128rm:
6773 case X86::VMOVDQU64Z128rm:
6774 case X86::VMOVAPSZ256rm:
6775 case X86::VMOVUPSZ256rm:
6776 case X86::VMOVAPDZ256rm:
6777 case X86::VMOVUPDZ256rm:
6778 case X86::VMOVDQU8Z256rm:
6779 case X86::VMOVDQU16Z256rm:
6780 case X86::VMOVDQA32Z256rm:
6781 case X86::VMOVDQU32Z256rm:
6782 case X86::VMOVDQA64Z256rm:
6783 case X86::VMOVDQU64Z256rm:
6784 case X86::VMOVAPSZrm:
6785 case X86::VMOVUPSZrm:
6786 case X86::VMOVAPDZrm:
6787 case X86::VMOVUPDZrm:
6788 case X86::VMOVDQU8Zrm:
6789 case X86::VMOVDQU16Zrm:
6790 case X86::VMOVDQA32Zrm:
6791 case X86::VMOVDQU32Zrm:
6792 case X86::VMOVDQA64Zrm:
6793 case X86::VMOVDQU64Zrm:
6794 case X86::KMOVBkm:
6795 case X86::KMOVWkm:
6796 case X86::KMOVDkm:
6797 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6798 break;
6799 }
6800
6801 // Check if chain operands and base addresses match.
6802 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6803 Load1->getOperand(5) != Load2->getOperand(5))
6804 return false;
6805 // Segment operands should match as well.
6806 if (Load1->getOperand(4) != Load2->getOperand(4))
6807 return false;
6808 // Scale should be 1, Index should be Reg0.
6809 if (Load1->getOperand(1) == Load2->getOperand(1) &&
6810 Load1->getOperand(2) == Load2->getOperand(2)) {
6811 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6812 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6813
6814 // Now let's examine the displacements.
6815 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6816 isa<ConstantSDNode>(Load2->getOperand(3))) {
6817 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6818 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6819 return true;
6820 }
6821 }
6822 return false;
6823}
6824
6825bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6826 int64_t Offset1, int64_t Offset2,
6827 unsigned NumLoads) const {
6828 assert(Offset2 > Offset1);
6829 if ((Offset2 - Offset1) / 8 > 64)
6830 return false;
6831
6832 unsigned Opc1 = Load1->getMachineOpcode();
6833 unsigned Opc2 = Load2->getMachineOpcode();
6834 if (Opc1 != Opc2)
6835 return false; // FIXME: overly conservative?
6836
6837 switch (Opc1) {
6838 default: break;
6839 case X86::LD_Fp32m:
6840 case X86::LD_Fp64m:
6841 case X86::LD_Fp80m:
6842 case X86::MMX_MOVD64rm:
6843 case X86::MMX_MOVQ64rm:
6844 return false;
6845 }
6846
6847 EVT VT = Load1->getValueType(0);
6848 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6849 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6850 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6851 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6852 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6853 if (NumLoads >= 3)
6854 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6855 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6856 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6857 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6858 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6859 case MVT::i8:
6860 case MVT::i16:
6861 case MVT::i32:
6862 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]6863 case MVT::f32:
6864 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6865 if (NumLoads)
6866 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6867 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6868 }
6869
6870 return true;
6871}
6872
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6873bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
6874 MachineInstr &Second) const {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6875 // Check if this processor supports macro-fusion. Since this is a minor
6876 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6877 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6878 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6879 return false;
6880
6881 enum {
6882 FuseTest,
6883 FuseCmp,
6884 FuseInc
6885 } FuseKind;
6886
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6887 switch (Second.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6888 default:
6889 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6890 case X86::JE_1:
6891 case X86::JNE_1:
6892 case X86::JL_1:
6893 case X86::JLE_1:
6894 case X86::JG_1:
6895 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6896 FuseKind = FuseInc;
6897 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6898 case X86::JB_1:
6899 case X86::JBE_1:
6900 case X86::JA_1:
6901 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6902 FuseKind = FuseCmp;
6903 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6904 case X86::JS_1:
6905 case X86::JNS_1:
6906 case X86::JP_1:
6907 case X86::JNP_1:
6908 case X86::JO_1:
6909 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6910 FuseKind = FuseTest;
6911 break;
6912 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6913 switch (First.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6914 default:
6915 return false;
6916 case X86::TEST8rr:
6917 case X86::TEST16rr:
6918 case X86::TEST32rr:
6919 case X86::TEST64rr:
6920 case X86::TEST8ri:
6921 case X86::TEST16ri:
6922 case X86::TEST32ri:
6923 case X86::TEST32i32:
6924 case X86::TEST64i32:
6925 case X86::TEST64ri32:
6926 case X86::TEST8rm:
6927 case X86::TEST16rm:
6928 case X86::TEST32rm:
6929 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]6930 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6931 case X86::AND16i16:
6932 case X86::AND16ri:
6933 case X86::AND16ri8:
6934 case X86::AND16rm:
6935 case X86::AND16rr:
6936 case X86::AND32i32:
6937 case X86::AND32ri:
6938 case X86::AND32ri8:
6939 case X86::AND32rm:
6940 case X86::AND32rr:
6941 case X86::AND64i32:
6942 case X86::AND64ri32:
6943 case X86::AND64ri8:
6944 case X86::AND64rm:
6945 case X86::AND64rr:
6946 case X86::AND8i8:
6947 case X86::AND8ri:
6948 case X86::AND8rm:
6949 case X86::AND8rr:
6950 return true;
6951 case X86::CMP16i16:
6952 case X86::CMP16ri:
6953 case X86::CMP16ri8:
6954 case X86::CMP16rm:
6955 case X86::CMP16rr:
6956 case X86::CMP32i32:
6957 case X86::CMP32ri:
6958 case X86::CMP32ri8:
6959 case X86::CMP32rm:
6960 case X86::CMP32rr:
6961 case X86::CMP64i32:
6962 case X86::CMP64ri32:
6963 case X86::CMP64ri8:
6964 case X86::CMP64rm:
6965 case X86::CMP64rr:
6966 case X86::CMP8i8:
6967 case X86::CMP8ri:
6968 case X86::CMP8rm:
6969 case X86::CMP8rr:
6970 case X86::ADD16i16:
6971 case X86::ADD16ri:
6972 case X86::ADD16ri8:
6973 case X86::ADD16ri8_DB:
6974 case X86::ADD16ri_DB:
6975 case X86::ADD16rm:
6976 case X86::ADD16rr:
6977 case X86::ADD16rr_DB:
6978 case X86::ADD32i32:
6979 case X86::ADD32ri:
6980 case X86::ADD32ri8:
6981 case X86::ADD32ri8_DB:
6982 case X86::ADD32ri_DB:
6983 case X86::ADD32rm:
6984 case X86::ADD32rr:
6985 case X86::ADD32rr_DB:
6986 case X86::ADD64i32:
6987 case X86::ADD64ri32:
6988 case X86::ADD64ri32_DB:
6989 case X86::ADD64ri8:
6990 case X86::ADD64ri8_DB:
6991 case X86::ADD64rm:
6992 case X86::ADD64rr:
6993 case X86::ADD64rr_DB:
6994 case X86::ADD8i8:
6995 case X86::ADD8mi:
6996 case X86::ADD8mr:
6997 case X86::ADD8ri:
6998 case X86::ADD8rm:
6999 case X86::ADD8rr:
7000 case X86::SUB16i16:
7001 case X86::SUB16ri:
7002 case X86::SUB16ri8:
7003 case X86::SUB16rm:
7004 case X86::SUB16rr:
7005 case X86::SUB32i32:
7006 case X86::SUB32ri:
7007 case X86::SUB32ri8:
7008 case X86::SUB32rm:
7009 case X86::SUB32rr:
7010 case X86::SUB64i32:
7011 case X86::SUB64ri32:
7012 case X86::SUB64ri8:
7013 case X86::SUB64rm:
7014 case X86::SUB64rr:
7015 case X86::SUB8i8:
7016 case X86::SUB8ri:
7017 case X86::SUB8rm:
7018 case X86::SUB8rr:
7019 return FuseKind == FuseCmp || FuseKind == FuseInc;
7020 case X86::INC16r:
7021 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7022 case X86::INC64r:
7023 case X86::INC8r:
7024 case X86::DEC16r:
7025 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7026 case X86::DEC64r:
7027 case X86::DEC8r:
7028 return FuseKind == FuseInc;
7029 }
7030}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7031
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7032bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]7033ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7034 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]7035 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7036 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7037 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7038}
7039
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7040bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7041isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7042 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7043 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7044 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7045 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7046}
7047
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7048/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7049/// the global base register value. Output instructions required to
7050/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7051///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7052/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7053///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7054unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7055 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7056 "X86-64 PIC uses RIP relative addressing");
7057
7058 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7059 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7060 if (GlobalBaseReg != 0)
7061 return GlobalBaseReg;
7062
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7063 // Create the register. The code to initialize it is inserted
7064 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7065 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]7066 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7067 X86FI->setGlobalBaseReg(GlobalBaseReg);
7068 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7069}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7070
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7071// These are the replaceable SSE instructions. Some of these have Int variants
7072// that we don't include here. We don't want to replace instructions selected
7073// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7074static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]7075 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7076 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
7077 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
7078 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
7079 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
7080 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]7081 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7082 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
7083 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
7084 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
7085 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
7086 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
7087 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
7088 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
7089 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
7090 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7091 // AVX 128-bit support
7092 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
7093 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
7094 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
7095 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
7096 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]7097 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7098 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7099 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
7100 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
7101 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
7102 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
7103 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
7104 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7105 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
7106 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]7107 // AVX 256-bit support
7108 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
7109 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
7110 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
7111 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
7112 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7113 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
7114 // AVX512 support
7115 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
7116 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7117 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7118 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7119};
7120
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7121static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7122 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]7123 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
7124 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
7125 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
7126 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
7127 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
7128 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
7129 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]7130 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
7131 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7132 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7133 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
7134 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
7135 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]7136 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
7137 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7138 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7139 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7140 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7141 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7142 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7143};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7144
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7145static const uint16_t ReplaceableInstrsAVX512[][4] = {
7146 // Two integer columns for 64-bit and 32-bit elements.
Craig Topperc48c0292016-08-01 07:55:33 +0000[diff] [blame]7147 //PackedSingle PackedDouble PackedInt PackedInt
7148 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
7149 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
7150 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
7151 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
7152 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
7153 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
7154 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
7155 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
7156 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
7157 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
7158 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
7159 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
7160 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
7161 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
7162 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7163};
7164
7165static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7166 // Two integer columns for 64-bit and 32-bit elements.
7167 //PackedSingle PackedDouble PackedInt PackedInt
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7168 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7169 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7170 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
7171 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
7172 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
7173 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
7174 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
7175 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
7176 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7177 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7178 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
7179 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
7180 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
7181 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
7182 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
7183 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
7184 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
7185 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
7186 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
7187 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
7188 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
7189 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
7190 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
7191 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7192};
7193
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7194static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7195 // Two integer columns for 64-bit and 32-bit elements.
7196 //PackedSingle PackedDouble
7197 //PackedInt PackedInt
7198 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
7199 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
7200 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7201 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7202 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
7203 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
7204 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7205 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7206 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
7207 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
7208 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
7209 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
7210 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
7211 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
7212 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
7213 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
7214 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
7215 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
7216 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
7217 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
7218 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
7219 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
7220 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
7221 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
7222 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
7223 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
7224 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
7225 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
7226 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
7227 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
7228 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
7229 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
7230 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
7231 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
7232 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7233 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7234 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
7235 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
7236 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7237 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7238 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
7239 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
7240 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
7241 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
7242 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
7243 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
7244 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
7245 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
7246 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
7247 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
7248 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
7249 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
7250 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
7251 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
7252 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
7253 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
7254 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
7255 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
7256 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
7257 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
7258 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
7259 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
7260 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
7261 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
7262 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
7263 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
7264 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
7265 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
7266 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
7267 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
7268 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
7269 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
7270 { X86::VANDPSZrmk, X86::VANDPDZrmk,
7271 X86::VPANDQZrmk, X86::VPANDDZrmk },
7272 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
7273 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
7274 { X86::VANDPSZrrk, X86::VANDPDZrrk,
7275 X86::VPANDQZrrk, X86::VPANDDZrrk },
7276 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
7277 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
7278 { X86::VORPSZrmk, X86::VORPDZrmk,
7279 X86::VPORQZrmk, X86::VPORDZrmk },
7280 { X86::VORPSZrmkz, X86::VORPDZrmkz,
7281 X86::VPORQZrmkz, X86::VPORDZrmkz },
7282 { X86::VORPSZrrk, X86::VORPDZrrk,
7283 X86::VPORQZrrk, X86::VPORDZrrk },
7284 { X86::VORPSZrrkz, X86::VORPDZrrkz,
7285 X86::VPORQZrrkz, X86::VPORDZrrkz },
7286 { X86::VXORPSZrmk, X86::VXORPDZrmk,
7287 X86::VPXORQZrmk, X86::VPXORDZrmk },
7288 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
7289 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
7290 { X86::VXORPSZrrk, X86::VXORPDZrrk,
7291 X86::VPXORQZrrk, X86::VPXORDZrrk },
7292 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
7293 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
7294};
7295
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7296// FIXME: Some shuffle and unpack instructions have equivalents in different
7297// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7298
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7299static const uint16_t *lookup(unsigned opcode, unsigned domain,
7300 ArrayRef<uint16_t[3]> Table) {
7301 for (const uint16_t (&Row)[3] : Table)
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7302 if (Row[domain-1] == opcode)
7303 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7304 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7305}
7306
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7307static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7308 ArrayRef<uint16_t[4]> Table) {
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7309 // If this is the integer domain make sure to check both integer columns.
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7310 for (const uint16_t (&Row)[4] : Table)
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7311 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7312 return Row;
7313 return nullptr;
7314}
7315
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7316std::pair<uint16_t, uint16_t>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7317X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7318 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7319 unsigned opcode = MI.getOpcode();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7320 uint16_t validDomains = 0;
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7321 if (domain) {
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7322 if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7323 validDomains = 0xe;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7324 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7325 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7326 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7327 validDomains = 0xe;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7328 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7329 validDomains = Subtarget.hasDQI() ? 0xe : 0x8;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7330 } else if (const uint16_t *table = lookupAVX512(opcode, domain,
7331 ReplaceableInstrsAVX512DQMasked)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7332 if (domain == 1 || (domain == 3 && table[3] == opcode))
7333 validDomains = Subtarget.hasDQI() ? 0xa : 0x8;
7334 else
7335 validDomains = Subtarget.hasDQI() ? 0xc : 0x8;
7336 }
7337 }
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7338 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7339}
7340
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7341void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7342 assert(Domain>0 && Domain<4 && "Invalid execution domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7343 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7344 assert(dom && "Not an SSE instruction");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7345 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7346 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7347 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7348 "256-bit vector operations only available in AVX2");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7349 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7350 }
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7351 if (!table) { // try the AVX512 table
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7352 assert(Subtarget.hasAVX512() && "Requires AVX-512");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7353 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7354 // Don't change integer Q instructions to D instructions.
Craig Topperc48c0292016-08-01 07:55:33 +0000[diff] [blame]7355 if (table && Domain == 3 && table[3] == MI.getOpcode())
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7356 Domain = 4;
7357 }
7358 if (!table) { // try the AVX512DQ table
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7359 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7360 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7361 // Don't change integer Q instructions to D instructions and
7362 // use D intructions if we started with a PS instruction.
7363 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7364 Domain = 4;
7365 }
7366 if (!table) { // try the AVX512DQMasked table
7367 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7368 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7369 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7370 Domain = 4;
7371 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7372 assert(table && "Cannot change domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7373 MI.setDesc(get(table[Domain - 1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7374}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7375
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7376/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7377void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7378 NopInst.setOpcode(X86::NOOP);
7379}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7380
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7381// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7382// In particular, getJumpInstrTableEntryBound must always return an upper bound
7383// on the encoding lengths of the instructions generated by
7384// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7385void X86InstrInfo::getUnconditionalBranch(
7386 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7387 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]7388 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7389}
7390
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7391// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7392// In particular, getJumpInstrTableEntryBound must always return an upper bound
7393// on the encoding lengths of the instructions generated by
7394// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7395void X86InstrInfo::getTrap(MCInst &MI) const {
7396 MI.setOpcode(X86::TRAP);
7397}
7398
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7399// See getTrap and getUnconditionalBranch for conditions on the value returned
7400// by this function.
7401unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7402 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7403 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7404 return 5;
7405}
7406
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7407bool X86InstrInfo::isHighLatencyDef(int opc) const {
7408 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7409 default: return false;
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7410 case X86::DIVPDrm:
7411 case X86::DIVPDrr:
7412 case X86::DIVPSrm:
7413 case X86::DIVPSrr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7414 case X86::DIVSDrm:
7415 case X86::DIVSDrm_Int:
7416 case X86::DIVSDrr:
7417 case X86::DIVSDrr_Int:
7418 case X86::DIVSSrm:
7419 case X86::DIVSSrm_Int:
7420 case X86::DIVSSrr:
7421 case X86::DIVSSrr_Int:
7422 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7423 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7424 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7425 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7426 case X86::SQRTSDm:
7427 case X86::SQRTSDm_Int:
7428 case X86::SQRTSDr:
7429 case X86::SQRTSDr_Int:
7430 case X86::SQRTSSm:
7431 case X86::SQRTSSm_Int:
7432 case X86::SQRTSSr:
7433 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7434 // AVX instructions with high latency
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7435 case X86::VDIVPDrm:
7436 case X86::VDIVPDrr:
7437 case X86::VDIVPDYrm:
7438 case X86::VDIVPDYrr:
7439 case X86::VDIVPSrm:
7440 case X86::VDIVPSrr:
7441 case X86::VDIVPSYrm:
7442 case X86::VDIVPSYrr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7443 case X86::VDIVSDrm:
7444 case X86::VDIVSDrm_Int:
7445 case X86::VDIVSDrr:
7446 case X86::VDIVSDrr_Int:
7447 case X86::VDIVSSrm:
7448 case X86::VDIVSSrm_Int:
7449 case X86::VDIVSSrr:
7450 case X86::VDIVSSrr_Int:
7451 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7452 case X86::VSQRTPDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7453 case X86::VSQRTPDYm:
7454 case X86::VSQRTPDYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7455 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7456 case X86::VSQRTPSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7457 case X86::VSQRTPSYm:
7458 case X86::VSQRTPSYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7459 case X86::VSQRTSDm:
7460 case X86::VSQRTSDm_Int:
7461 case X86::VSQRTSDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7462 case X86::VSQRTSDr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7463 case X86::VSQRTSSm:
7464 case X86::VSQRTSSm_Int:
7465 case X86::VSQRTSSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7466 case X86::VSQRTSSr_Int:
7467 // AVX512 instructions with high latency
7468 case X86::VDIVPDZ128rm:
7469 case X86::VDIVPDZ128rmb:
7470 case X86::VDIVPDZ128rmbk:
7471 case X86::VDIVPDZ128rmbkz:
7472 case X86::VDIVPDZ128rmk:
7473 case X86::VDIVPDZ128rmkz:
7474 case X86::VDIVPDZ128rr:
7475 case X86::VDIVPDZ128rrk:
7476 case X86::VDIVPDZ128rrkz:
7477 case X86::VDIVPDZ256rm:
7478 case X86::VDIVPDZ256rmb:
7479 case X86::VDIVPDZ256rmbk:
7480 case X86::VDIVPDZ256rmbkz:
7481 case X86::VDIVPDZ256rmk:
7482 case X86::VDIVPDZ256rmkz:
7483 case X86::VDIVPDZ256rr:
7484 case X86::VDIVPDZ256rrk:
7485 case X86::VDIVPDZ256rrkz:
7486 case X86::VDIVPDZrb:
7487 case X86::VDIVPDZrbk:
7488 case X86::VDIVPDZrbkz:
7489 case X86::VDIVPDZrm:
7490 case X86::VDIVPDZrmb:
7491 case X86::VDIVPDZrmbk:
7492 case X86::VDIVPDZrmbkz:
7493 case X86::VDIVPDZrmk:
7494 case X86::VDIVPDZrmkz:
7495 case X86::VDIVPDZrr:
7496 case X86::VDIVPDZrrk:
7497 case X86::VDIVPDZrrkz:
7498 case X86::VDIVPSZ128rm:
7499 case X86::VDIVPSZ128rmb:
7500 case X86::VDIVPSZ128rmbk:
7501 case X86::VDIVPSZ128rmbkz:
7502 case X86::VDIVPSZ128rmk:
7503 case X86::VDIVPSZ128rmkz:
7504 case X86::VDIVPSZ128rr:
7505 case X86::VDIVPSZ128rrk:
7506 case X86::VDIVPSZ128rrkz:
7507 case X86::VDIVPSZ256rm:
7508 case X86::VDIVPSZ256rmb:
7509 case X86::VDIVPSZ256rmbk:
7510 case X86::VDIVPSZ256rmbkz:
7511 case X86::VDIVPSZ256rmk:
7512 case X86::VDIVPSZ256rmkz:
7513 case X86::VDIVPSZ256rr:
7514 case X86::VDIVPSZ256rrk:
7515 case X86::VDIVPSZ256rrkz:
7516 case X86::VDIVPSZrb:
7517 case X86::VDIVPSZrbk:
7518 case X86::VDIVPSZrbkz:
7519 case X86::VDIVPSZrm:
7520 case X86::VDIVPSZrmb:
7521 case X86::VDIVPSZrmbk:
7522 case X86::VDIVPSZrmbkz:
7523 case X86::VDIVPSZrmk:
7524 case X86::VDIVPSZrmkz:
7525 case X86::VDIVPSZrr:
7526 case X86::VDIVPSZrrk:
7527 case X86::VDIVPSZrrkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7528 case X86::VDIVSDZrm:
7529 case X86::VDIVSDZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7530 case X86::VDIVSDZrm_Int:
7531 case X86::VDIVSDZrm_Intk:
7532 case X86::VDIVSDZrm_Intkz:
7533 case X86::VDIVSDZrr_Int:
7534 case X86::VDIVSDZrr_Intk:
7535 case X86::VDIVSDZrr_Intkz:
7536 case X86::VDIVSDZrrb:
7537 case X86::VDIVSDZrrbk:
7538 case X86::VDIVSDZrrbkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7539 case X86::VDIVSSZrm:
7540 case X86::VDIVSSZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7541 case X86::VDIVSSZrm_Int:
7542 case X86::VDIVSSZrm_Intk:
7543 case X86::VDIVSSZrm_Intkz:
7544 case X86::VDIVSSZrr_Int:
7545 case X86::VDIVSSZrr_Intk:
7546 case X86::VDIVSSZrr_Intkz:
7547 case X86::VDIVSSZrrb:
7548 case X86::VDIVSSZrrbk:
7549 case X86::VDIVSSZrrbkz:
7550 case X86::VSQRTPDZ128m:
7551 case X86::VSQRTPDZ128mb:
7552 case X86::VSQRTPDZ128mbk:
7553 case X86::VSQRTPDZ128mbkz:
7554 case X86::VSQRTPDZ128mk:
7555 case X86::VSQRTPDZ128mkz:
7556 case X86::VSQRTPDZ128r:
7557 case X86::VSQRTPDZ128rk:
7558 case X86::VSQRTPDZ128rkz:
7559 case X86::VSQRTPDZ256m:
7560 case X86::VSQRTPDZ256mb:
7561 case X86::VSQRTPDZ256mbk:
7562 case X86::VSQRTPDZ256mbkz:
7563 case X86::VSQRTPDZ256mk:
7564 case X86::VSQRTPDZ256mkz:
7565 case X86::VSQRTPDZ256r:
7566 case X86::VSQRTPDZ256rk:
7567 case X86::VSQRTPDZ256rkz:
7568 case X86::VSQRTPDZm:
7569 case X86::VSQRTPDZmb:
7570 case X86::VSQRTPDZmbk:
7571 case X86::VSQRTPDZmbkz:
7572 case X86::VSQRTPDZmk:
7573 case X86::VSQRTPDZmkz:
7574 case X86::VSQRTPDZr:
7575 case X86::VSQRTPDZrb:
7576 case X86::VSQRTPDZrbk:
7577 case X86::VSQRTPDZrbkz:
7578 case X86::VSQRTPDZrk:
7579 case X86::VSQRTPDZrkz:
7580 case X86::VSQRTPSZ128m:
7581 case X86::VSQRTPSZ128mb:
7582 case X86::VSQRTPSZ128mbk:
7583 case X86::VSQRTPSZ128mbkz:
7584 case X86::VSQRTPSZ128mk:
7585 case X86::VSQRTPSZ128mkz:
7586 case X86::VSQRTPSZ128r:
7587 case X86::VSQRTPSZ128rk:
7588 case X86::VSQRTPSZ128rkz:
7589 case X86::VSQRTPSZ256m:
7590 case X86::VSQRTPSZ256mb:
7591 case X86::VSQRTPSZ256mbk:
7592 case X86::VSQRTPSZ256mbkz:
7593 case X86::VSQRTPSZ256mk:
7594 case X86::VSQRTPSZ256mkz:
7595 case X86::VSQRTPSZ256r:
7596 case X86::VSQRTPSZ256rk:
7597 case X86::VSQRTPSZ256rkz:
7598 case X86::VSQRTPSZm:
7599 case X86::VSQRTPSZmb:
7600 case X86::VSQRTPSZmbk:
7601 case X86::VSQRTPSZmbkz:
7602 case X86::VSQRTPSZmk:
7603 case X86::VSQRTPSZmkz:
7604 case X86::VSQRTPSZr:
7605 case X86::VSQRTPSZrb:
7606 case X86::VSQRTPSZrbk:
7607 case X86::VSQRTPSZrbkz:
7608 case X86::VSQRTPSZrk:
7609 case X86::VSQRTPSZrkz:
7610 case X86::VSQRTSDZm:
7611 case X86::VSQRTSDZm_Int:
7612 case X86::VSQRTSDZm_Intk:
7613 case X86::VSQRTSDZm_Intkz:
7614 case X86::VSQRTSDZr:
7615 case X86::VSQRTSDZr_Int:
7616 case X86::VSQRTSDZr_Intk:
7617 case X86::VSQRTSDZr_Intkz:
7618 case X86::VSQRTSDZrb_Int:
7619 case X86::VSQRTSDZrb_Intk:
7620 case X86::VSQRTSDZrb_Intkz:
7621 case X86::VSQRTSSZm:
7622 case X86::VSQRTSSZm_Int:
7623 case X86::VSQRTSSZm_Intk:
7624 case X86::VSQRTSSZm_Intkz:
7625 case X86::VSQRTSSZr:
7626 case X86::VSQRTSSZr_Int:
7627 case X86::VSQRTSSZr_Intk:
7628 case X86::VSQRTSSZr_Intkz:
7629 case X86::VSQRTSSZrb_Int:
7630 case X86::VSQRTSSZrb_Intk:
7631 case X86::VSQRTSSZrb_Intkz:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7632
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7633 case X86::VGATHERDPDYrm:
7634 case X86::VGATHERDPDZ128rm:
7635 case X86::VGATHERDPDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7636 case X86::VGATHERDPDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7637 case X86::VGATHERDPDrm:
7638 case X86::VGATHERDPSYrm:
7639 case X86::VGATHERDPSZ128rm:
7640 case X86::VGATHERDPSZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7641 case X86::VGATHERDPSZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7642 case X86::VGATHERDPSrm:
7643 case X86::VGATHERPF0DPDm:
7644 case X86::VGATHERPF0DPSm:
7645 case X86::VGATHERPF0QPDm:
7646 case X86::VGATHERPF0QPSm:
7647 case X86::VGATHERPF1DPDm:
7648 case X86::VGATHERPF1DPSm:
7649 case X86::VGATHERPF1QPDm:
7650 case X86::VGATHERPF1QPSm:
7651 case X86::VGATHERQPDYrm:
7652 case X86::VGATHERQPDZ128rm:
7653 case X86::VGATHERQPDZ256rm:
7654 case X86::VGATHERQPDZrm:
7655 case X86::VGATHERQPDrm:
7656 case X86::VGATHERQPSYrm:
7657 case X86::VGATHERQPSZ128rm:
7658 case X86::VGATHERQPSZ256rm:
7659 case X86::VGATHERQPSZrm:
7660 case X86::VGATHERQPSrm:
7661 case X86::VPGATHERDDYrm:
7662 case X86::VPGATHERDDZ128rm:
7663 case X86::VPGATHERDDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7664 case X86::VPGATHERDDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7665 case X86::VPGATHERDDrm:
7666 case X86::VPGATHERDQYrm:
7667 case X86::VPGATHERDQZ128rm:
7668 case X86::VPGATHERDQZ256rm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7669 case X86::VPGATHERDQZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7670 case X86::VPGATHERDQrm:
7671 case X86::VPGATHERQDYrm:
7672 case X86::VPGATHERQDZ128rm:
7673 case X86::VPGATHERQDZ256rm:
7674 case X86::VPGATHERQDZrm:
7675 case X86::VPGATHERQDrm:
7676 case X86::VPGATHERQQYrm:
7677 case X86::VPGATHERQQZ128rm:
7678 case X86::VPGATHERQQZ256rm:
7679 case X86::VPGATHERQQZrm:
7680 case X86::VPGATHERQQrm:
7681 case X86::VSCATTERDPDZ128mr:
7682 case X86::VSCATTERDPDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7683 case X86::VSCATTERDPDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7684 case X86::VSCATTERDPSZ128mr:
7685 case X86::VSCATTERDPSZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7686 case X86::VSCATTERDPSZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7687 case X86::VSCATTERPF0DPDm:
7688 case X86::VSCATTERPF0DPSm:
7689 case X86::VSCATTERPF0QPDm:
7690 case X86::VSCATTERPF0QPSm:
7691 case X86::VSCATTERPF1DPDm:
7692 case X86::VSCATTERPF1DPSm:
7693 case X86::VSCATTERPF1QPDm:
7694 case X86::VSCATTERPF1QPSm:
7695 case X86::VSCATTERQPDZ128mr:
7696 case X86::VSCATTERQPDZ256mr:
7697 case X86::VSCATTERQPDZmr:
7698 case X86::VSCATTERQPSZ128mr:
7699 case X86::VSCATTERQPSZ256mr:
7700 case X86::VSCATTERQPSZmr:
7701 case X86::VPSCATTERDDZ128mr:
7702 case X86::VPSCATTERDDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7703 case X86::VPSCATTERDDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7704 case X86::VPSCATTERDQZ128mr:
7705 case X86::VPSCATTERDQZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7706 case X86::VPSCATTERDQZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7707 case X86::VPSCATTERQDZ128mr:
7708 case X86::VPSCATTERQDZ256mr:
7709 case X86::VPSCATTERQDZmr:
7710 case X86::VPSCATTERQQZ128mr:
7711 case X86::VPSCATTERQQZ256mr:
7712 case X86::VPSCATTERQQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7713 return true;
7714 }
7715}
7716
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7717bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7718 const MachineRegisterInfo *MRI,
7719 const MachineInstr &DefMI,
7720 unsigned DefIdx,
7721 const MachineInstr &UseMI,
7722 unsigned UseIdx) const {
7723 return isHighLatencyDef(DefMI.getOpcode());
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7724}
7725
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7726bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7727 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7728 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7729 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7730
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7731 // Integer binary math/logic instructions have a third source operand:
7732 // the EFLAGS register. That operand must be both defined here and never
7733 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7734 // not change anything because rearranging the operands could affect other
7735 // instructions that depend on the exact status flags (zero, sign, etc.)
7736 // that are set by using these particular operands with this operation.
7737 if (Inst.getNumOperands() == 4) {
7738 assert(Inst.getOperand(3).isReg() &&
7739 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7740 "Unexpected operand in reassociable instruction");
7741 if (!Inst.getOperand(3).isDead())
7742 return false;
7743 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]7744
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7745 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7746}
7747
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7748// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7749// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7750// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7751// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7752bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7753 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7754 case X86::AND8rr:
7755 case X86::AND16rr:
7756 case X86::AND32rr:
7757 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]7758 case X86::OR8rr:
7759 case X86::OR16rr:
7760 case X86::OR32rr:
7761 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]7762 case X86::XOR8rr:
7763 case X86::XOR16rr:
7764 case X86::XOR32rr:
7765 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7766 case X86::IMUL16rr:
7767 case X86::IMUL32rr:
7768 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7769 case X86::PANDrr:
7770 case X86::PORrr:
7771 case X86::PXORrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]7772 case X86::ANDPDrr:
7773 case X86::ANDPSrr:
7774 case X86::ORPDrr:
7775 case X86::ORPSrr:
7776 case X86::XORPDrr:
7777 case X86::XORPSrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]7778 case X86::PADDBrr:
7779 case X86::PADDWrr:
7780 case X86::PADDDrr:
7781 case X86::PADDQrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7782 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7783 case X86::VPANDYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7784 case X86::VPANDDZ128rr:
7785 case X86::VPANDDZ256rr:
7786 case X86::VPANDDZrr:
7787 case X86::VPANDQZ128rr:
7788 case X86::VPANDQZ256rr:
7789 case X86::VPANDQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7790 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7791 case X86::VPORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7792 case X86::VPORDZ128rr:
7793 case X86::VPORDZ256rr:
7794 case X86::VPORDZrr:
7795 case X86::VPORQZ128rr:
7796 case X86::VPORQZ256rr:
7797 case X86::VPORQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7798 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7799 case X86::VPXORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7800 case X86::VPXORDZ128rr:
7801 case X86::VPXORDZ256rr:
7802 case X86::VPXORDZrr:
7803 case X86::VPXORQZ128rr:
7804 case X86::VPXORQZ256rr:
7805 case X86::VPXORQZrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]7806 case X86::VANDPDrr:
7807 case X86::VANDPSrr:
7808 case X86::VANDPDYrr:
7809 case X86::VANDPSYrr:
7810 case X86::VANDPDZ128rr:
7811 case X86::VANDPSZ128rr:
7812 case X86::VANDPDZ256rr:
7813 case X86::VANDPSZ256rr:
7814 case X86::VANDPDZrr:
7815 case X86::VANDPSZrr:
7816 case X86::VORPDrr:
7817 case X86::VORPSrr:
7818 case X86::VORPDYrr:
7819 case X86::VORPSYrr:
7820 case X86::VORPDZ128rr:
7821 case X86::VORPSZ128rr:
7822 case X86::VORPDZ256rr:
7823 case X86::VORPSZ256rr:
7824 case X86::VORPDZrr:
7825 case X86::VORPSZrr:
7826 case X86::VXORPDrr:
7827 case X86::VXORPSrr:
7828 case X86::VXORPDYrr:
7829 case X86::VXORPSYrr:
7830 case X86::VXORPDZ128rr:
7831 case X86::VXORPSZ128rr:
7832 case X86::VXORPDZ256rr:
7833 case X86::VXORPSZ256rr:
7834 case X86::VXORPDZrr:
7835 case X86::VXORPSZrr:
Craig Topper16a07442016-07-18 06:14:59 +0000[diff] [blame]7836 case X86::KADDBrr:
7837 case X86::KADDWrr:
7838 case X86::KADDDrr:
7839 case X86::KADDQrr:
7840 case X86::KANDBrr:
7841 case X86::KANDWrr:
7842 case X86::KANDDrr:
7843 case X86::KANDQrr:
7844 case X86::KORBrr:
7845 case X86::KORWrr:
7846 case X86::KORDrr:
7847 case X86::KORQrr:
7848 case X86::KXORBrr:
7849 case X86::KXORWrr:
7850 case X86::KXORDrr:
7851 case X86::KXORQrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]7852 case X86::VPADDBrr:
7853 case X86::VPADDWrr:
7854 case X86::VPADDDrr:
7855 case X86::VPADDQrr:
7856 case X86::VPADDBYrr:
7857 case X86::VPADDWYrr:
7858 case X86::VPADDDYrr:
7859 case X86::VPADDQYrr:
7860 case X86::VPADDBZ128rr:
7861 case X86::VPADDWZ128rr:
7862 case X86::VPADDDZ128rr:
7863 case X86::VPADDQZ128rr:
7864 case X86::VPADDBZ256rr:
7865 case X86::VPADDWZ256rr:
7866 case X86::VPADDDZ256rr:
7867 case X86::VPADDQZ256rr:
7868 case X86::VPADDBZrr:
7869 case X86::VPADDWZrr:
7870 case X86::VPADDDZrr:
7871 case X86::VPADDQZrr:
Craig Topper463f9492016-07-18 06:14:57 +0000[diff] [blame]7872 case X86::VPMULLWrr:
7873 case X86::VPMULLWYrr:
7874 case X86::VPMULLWZ128rr:
7875 case X86::VPMULLWZ256rr:
7876 case X86::VPMULLWZrr:
7877 case X86::VPMULLDrr:
7878 case X86::VPMULLDYrr:
7879 case X86::VPMULLDZ128rr:
7880 case X86::VPMULLDZ256rr:
7881 case X86::VPMULLDZrr:
7882 case X86::VPMULLQZ128rr:
7883 case X86::VPMULLQZ256rr:
7884 case X86::VPMULLQZrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7885 // Normal min/max instructions are not commutative because of NaN and signed
7886 // zero semantics, but these are. Thus, there's no need to check for global
7887 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7888 case X86::MAXCPDrr:
7889 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7890 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7891 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7892 case X86::MINCPDrr:
7893 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7894 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7895 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7896 case X86::VMAXCPDrr:
7897 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7898 case X86::VMAXCPDYrr:
7899 case X86::VMAXCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7900 case X86::VMAXCPDZ128rr:
7901 case X86::VMAXCPSZ128rr:
7902 case X86::VMAXCPDZ256rr:
7903 case X86::VMAXCPSZ256rr:
7904 case X86::VMAXCPDZrr:
7905 case X86::VMAXCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7906 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7907 case X86::VMAXCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7908 case X86::VMAXCSDZrr:
7909 case X86::VMAXCSSZrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7910 case X86::VMINCPDrr:
7911 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7912 case X86::VMINCPDYrr:
7913 case X86::VMINCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7914 case X86::VMINCPDZ128rr:
7915 case X86::VMINCPSZ128rr:
7916 case X86::VMINCPDZ256rr:
7917 case X86::VMINCPSZ256rr:
7918 case X86::VMINCPDZrr:
7919 case X86::VMINCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7920 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7921 case X86::VMINCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7922 case X86::VMINCSDZrr:
7923 case X86::VMINCSSZrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7924 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7925 case X86::ADDPDrr:
7926 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7927 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7928 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7929 case X86::MULPDrr:
7930 case X86::MULPSrr:
7931 case X86::MULSDrr:
7932 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7933 case X86::VADDPDrr:
7934 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7935 case X86::VADDPDYrr:
7936 case X86::VADDPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7937 case X86::VADDPDZ128rr:
7938 case X86::VADDPSZ128rr:
7939 case X86::VADDPDZ256rr:
7940 case X86::VADDPSZ256rr:
7941 case X86::VADDPDZrr:
7942 case X86::VADDPSZrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7943 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7944 case X86::VADDSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7945 case X86::VADDSDZrr:
7946 case X86::VADDSSZrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7947 case X86::VMULPDrr:
7948 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7949 case X86::VMULPDYrr:
7950 case X86::VMULPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7951 case X86::VMULPDZ128rr:
7952 case X86::VMULPSZ128rr:
7953 case X86::VMULPDZ256rr:
7954 case X86::VMULPSZ256rr:
7955 case X86::VMULPDZrr:
7956 case X86::VMULPSZrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7957 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7958 case X86::VMULSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7959 case X86::VMULSDZrr:
7960 case X86::VMULSSZrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7961 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7962 default:
7963 return false;
7964 }
7965}
7966
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7967/// This is an architecture-specific helper function of reassociateOps.
7968/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7969void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7970 MachineInstr &OldMI2,
7971 MachineInstr &NewMI1,
7972 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7973 // Integer instructions define an implicit EFLAGS source register operand as
7974 // the third source (fourth total) operand.
7975 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7976 return;
7977
7978 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7979 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7980
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7981 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7982 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7983 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7984 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7985
7986 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7987 "Must have dead EFLAGS operand in reassociable instruction");
7988 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7989 "Must have dead EFLAGS operand in reassociable instruction");
7990
7991 (void)OldOp1;
7992 (void)OldOp2;
7993
7994 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7995 "Unexpected operand in reassociable instruction");
7996 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7997 "Unexpected operand in reassociable instruction");
7998
7999 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8000 // of this pass or other passes. The EFLAGS operands must be dead in these new
8001 // instructions because the EFLAGS operands in the original instructions must
8002 // be dead in order for reassociation to occur.
8003 NewOp1.setIsDead();
8004 NewOp2.setIsDead();
8005}
8006
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8007std::pair<unsigned, unsigned>
8008X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8009 return std::make_pair(TF, 0u);
8010}
8011
8012ArrayRef<std::pair<unsigned, const char *>>
8013X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8014 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]8015 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8016 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8017 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8018 {MO_GOT, "x86-got"},
8019 {MO_GOTOFF, "x86-gotoff"},
8020 {MO_GOTPCREL, "x86-gotpcrel"},
8021 {MO_PLT, "x86-plt"},
8022 {MO_TLSGD, "x86-tlsgd"},
8023 {MO_TLSLD, "x86-tlsld"},
8024 {MO_TLSLDM, "x86-tlsldm"},
8025 {MO_GOTTPOFF, "x86-gottpoff"},
8026 {MO_INDNTPOFF, "x86-indntpoff"},
8027 {MO_TPOFF, "x86-tpoff"},
8028 {MO_DTPOFF, "x86-dtpoff"},
8029 {MO_NTPOFF, "x86-ntpoff"},
8030 {MO_GOTNTPOFF, "x86-gotntpoff"},
8031 {MO_DLLIMPORT, "x86-dllimport"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8032 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8033 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8034 {MO_TLVP, "x86-tlvp"},
8035 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8036 {MO_SECREL, "x86-secrel"}};
8037 return makeArrayRef(TargetFlags);
8038}
8039
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8040namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]8041 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8042 /// global base register for x86-32.
8043 struct CGBR : public MachineFunctionPass {
8044 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]8045 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8046
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8047 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8048 const X86TargetMachine *TM =
8049 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8050 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8051
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]8052 // Don't do anything if this is 64-bit as 64-bit PIC
8053 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8054 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]8055 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8056
8057 // Only emit a global base reg in PIC mode.
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]8058 if (!TM->isPositionIndependent())
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8059 return false;
8060
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]8061 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8062 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8063
8064 // If we didn't need a GlobalBaseReg, don't insert code.
8065 if (GlobalBaseReg == 0)
8066 return false;
8067
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8068 // Insert the set of GlobalBaseReg into the first MBB of the function
8069 MachineBasicBlock &FirstMBB = MF.front();
8070 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8071 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8072 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8073 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8074
8075 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8076 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]8077 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8078 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]8079 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]8080
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8081 // Operand of MovePCtoStack is completely ignored by asm printer. It's
8082 // only used in JIT code emission as displacement to pc.
8083 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]8084
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8085 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
8086 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8087 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8088 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
8089 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8090 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8091 X86II::MO_GOT_ABSOLUTE_ADDRESS);
8092 }
8093
8094 return true;
8095 }
8096
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8097 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8098 return "X86 PIC Global Base Reg Initialization";
8099 }
8100
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8101 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8102 AU.setPreservesCFG();
8103 MachineFunctionPass::getAnalysisUsage(AU);
8104 }
8105 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8106}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8107
8108char CGBR::ID = 0;
8109FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]8110llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8111
8112namespace {
8113 struct LDTLSCleanup : public MachineFunctionPass {
8114 static char ID;
8115 LDTLSCleanup() : MachineFunctionPass(ID) {}
8116
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8117 bool runOnMachineFunction(MachineFunction &MF) override {
Andrew Kaylor2bee5ef2016-04-26 21:44:24 +0000[diff] [blame]8118 if (skipFunction(*MF.getFunction()))
8119 return false;
8120
8121 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8122 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8123 // No point folding accesses if there isn't at least two.
8124 return false;
8125 }
8126
8127 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8128 return VisitNode(DT->getRootNode(), 0);
8129 }
8130
8131 // Visit the dominator subtree rooted at Node in pre-order.
8132 // If TLSBaseAddrReg is non-null, then use that to replace any
8133 // TLS_base_addr instructions. Otherwise, create the register
8134 // when the first such instruction is seen, and then use it
8135 // as we encounter more instructions.
8136 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8137 MachineBasicBlock *BB = Node->getBlock();
8138 bool Changed = false;
8139
8140 // Traverse the current block.
8141 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8142 ++I) {
8143 switch (I->getOpcode()) {
8144 case X86::TLS_base_addr32:
8145 case X86::TLS_base_addr64:
8146 if (TLSBaseAddrReg)
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8147 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8148 else
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8149 I = SetRegister(*I, &TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8150 Changed = true;
8151 break;
8152 default:
8153 break;
8154 }
8155 }
8156
8157 // Visit the children of this block in the dominator tree.
8158 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8159 I != E; ++I) {
8160 Changed |= VisitNode(*I, TLSBaseAddrReg);
8161 }
8162
8163 return Changed;
8164 }
8165
8166 // Replace the TLS_base_addr instruction I with a copy from
8167 // TLSBaseAddrReg, returning the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8168 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8169 unsigned TLSBaseAddrReg) {
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8170 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8171 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8172 const bool is64Bit = STI.is64Bit();
8173 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8174
8175 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8176 MachineInstr *Copy =
8177 BuildMI(*I.getParent(), I, I.getDebugLoc(),
8178 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8179 .addReg(TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8180
8181 // Erase the TLS_base_addr instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8182 I.eraseFromParent();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8183
8184 return Copy;
8185 }
8186
8187 // Create a virtal register in *TLSBaseAddrReg, and populate it by
8188 // inserting a copy instruction after I. Returns the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8189 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8190 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8191 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8192 const bool is64Bit = STI.is64Bit();
8193 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8194
8195 // Create a virtual register for the TLS base address.
8196 MachineRegisterInfo &RegInfo = MF->getRegInfo();
8197 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8198 ? &X86::GR64RegClass
8199 : &X86::GR32RegClass);
8200
8201 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8202 MachineInstr *Next = I.getNextNode();
8203 MachineInstr *Copy =
8204 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8205 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8206 .addReg(is64Bit ? X86::RAX : X86::EAX);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8207
8208 return Copy;
8209 }
8210
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8211 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8212 return "Local Dynamic TLS Access Clean-up";
8213 }
8214
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8215 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8216 AU.setPreservesCFG();
8217 AU.addRequired<MachineDominatorTree>();
8218 MachineFunctionPass::getAnalysisUsage(AU);
8219 }
8220 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8221}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8222
8223char LDTLSCleanup::ID = 0;
8224FunctionPass*
8225llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }