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gerrit-public.fairphone.software / toolchain / llvm-project / a3c55f59152cc62397e0420b48734c86162b2f29 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 1672b3855b7981a07b1c154e10a5278e2c556acb [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]21#include "llvm/CodeGen/LivePhysRegs.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]22#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]27#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]28#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]29#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]31#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]32#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]33#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]34#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]35#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]36#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]37#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]40#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]61static cl::opt<unsigned>
62PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67static cl::opt<unsigned>
68UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
71 cl::init(64), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]72
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]73enum {
74 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]75 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]79 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]80 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]104};
105
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]106struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]107 uint16_t RegOp;
108 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]109 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]110};
111
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]112// Pin the vtable to this file.
113void X86InstrInfo::anchor() {}
114
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]115X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
Dean Michael Berris52735fc2016-07-14 04:06:33 +0000[diff] [blame]120 X86::CATCHRET,
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]122 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]123
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]124 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
133 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
134 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
136 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
139 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
140 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
142 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
145 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
146 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
148 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16rCL, X86::SHL16mCL, 0 },
232 { X86::SHL16ri, X86::SHL16mi, 0 },
233 { X86::SHL32rCL, X86::SHL32mCL, 0 },
234 { X86::SHL32ri, X86::SHL32mi, 0 },
235 { X86::SHL64rCL, X86::SHL64mCL, 0 },
236 { X86::SHL64ri, X86::SHL64mi, 0 },
237 { X86::SHL8rCL, X86::SHL8mCL, 0 },
238 { X86::SHL8ri, X86::SHL8mi, 0 },
239 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
240 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
241 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
242 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
243 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
244 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
245 { X86::SHR16r1, X86::SHR16m1, 0 },
246 { X86::SHR16rCL, X86::SHR16mCL, 0 },
247 { X86::SHR16ri, X86::SHR16mi, 0 },
248 { X86::SHR32r1, X86::SHR32m1, 0 },
249 { X86::SHR32rCL, X86::SHR32mCL, 0 },
250 { X86::SHR32ri, X86::SHR32mi, 0 },
251 { X86::SHR64r1, X86::SHR64m1, 0 },
252 { X86::SHR64rCL, X86::SHR64mCL, 0 },
253 { X86::SHR64ri, X86::SHR64mi, 0 },
254 { X86::SHR8r1, X86::SHR8m1, 0 },
255 { X86::SHR8rCL, X86::SHR8mCL, 0 },
256 { X86::SHR8ri, X86::SHR8mi, 0 },
257 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
258 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
259 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
260 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
261 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
262 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
263 { X86::SUB16ri, X86::SUB16mi, 0 },
264 { X86::SUB16ri8, X86::SUB16mi8, 0 },
265 { X86::SUB16rr, X86::SUB16mr, 0 },
266 { X86::SUB32ri, X86::SUB32mi, 0 },
267 { X86::SUB32ri8, X86::SUB32mi8, 0 },
268 { X86::SUB32rr, X86::SUB32mr, 0 },
269 { X86::SUB64ri32, X86::SUB64mi32, 0 },
270 { X86::SUB64ri8, X86::SUB64mi8, 0 },
271 { X86::SUB64rr, X86::SUB64mr, 0 },
272 { X86::SUB8ri, X86::SUB8mi, 0 },
273 { X86::SUB8rr, X86::SUB8mr, 0 },
274 { X86::XOR16ri, X86::XOR16mi, 0 },
275 { X86::XOR16ri8, X86::XOR16mi8, 0 },
276 { X86::XOR16rr, X86::XOR16mr, 0 },
277 { X86::XOR32ri, X86::XOR32mi, 0 },
278 { X86::XOR32ri8, X86::XOR32mi8, 0 },
279 { X86::XOR32rr, X86::XOR32mr, 0 },
280 { X86::XOR64ri32, X86::XOR64mi32, 0 },
281 { X86::XOR64ri8, X86::XOR64mi8, 0 },
282 { X86::XOR64rr, X86::XOR64mr, 0 },
283 { X86::XOR8ri, X86::XOR8mi, 0 },
284 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]285 };
286
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]287 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]289 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]290 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]291 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]292 }
293
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]294 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]295 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
296 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
297 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
298 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
299 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]300 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
301 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
302 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
303 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
304 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
305 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
306 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
307 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
308 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
309 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
310 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
311 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
312 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
313 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
314 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]315 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]316 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
317 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
318 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
319 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
320 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
321 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
322 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
323 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
324 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
325 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
326 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
327 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
328 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
329 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
330 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
331 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
332 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
333 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
334 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
336 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
337 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
339 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
340 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
341 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
342 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
343 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]344 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
345 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
346 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
347 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]348 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
349 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]350 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
351 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
352 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]353 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
354 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
355 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
356 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
357 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
358 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
359 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
360 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
361 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
362 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
363 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
364 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
365 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
366 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
367 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
368 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
369 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
370 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]371 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]372 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
373 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
374 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]375 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]378 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]379 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]380 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
382 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
383 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
384 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
386 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
387 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]389 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
390 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]391
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]392 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]393 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]394 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]398 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]399
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]400 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]401 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
403 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
404 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
405 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
406 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]408 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]410 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]411 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]412
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]413 // AVX-512 foldable instructions (256-bit versions)
414 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
415 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
416 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
417 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
418 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
423 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]424
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]425 // AVX-512 foldable instructions (128-bit versions)
426 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
427 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
428 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
429 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
430 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
431 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
432 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
433 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
434 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]435 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]436
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]437 // F16C foldable instructions
438 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
439 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]440 };
441
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]442 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]443 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]445 }
446
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]447 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]448 { X86::BSF16rr, X86::BSF16rm, 0 },
449 { X86::BSF32rr, X86::BSF32rm, 0 },
450 { X86::BSF64rr, X86::BSF64rm, 0 },
451 { X86::BSR16rr, X86::BSR16rm, 0 },
452 { X86::BSR32rr, X86::BSR32rm, 0 },
453 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]454 { X86::CMP16rr, X86::CMP16rm, 0 },
455 { X86::CMP32rr, X86::CMP32rm, 0 },
456 { X86::CMP64rr, X86::CMP64rm, 0 },
457 { X86::CMP8rr, X86::CMP8rm, 0 },
458 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
459 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
460 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
461 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
462 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
463 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
464 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
465 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
466 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
467 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]468 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
469 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
470 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
471 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
472 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
473 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
474 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
475 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]476 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
477 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]478 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
479 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]480 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]481 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]482 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]483 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]484 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]485 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]486 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
487 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
488 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
489 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
490 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
491 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
492 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
493 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]494 { X86::MOV16rr, X86::MOV16rm, 0 },
495 { X86::MOV32rr, X86::MOV32rm, 0 },
496 { X86::MOV64rr, X86::MOV64rm, 0 },
497 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
498 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
499 { X86::MOV8rr, X86::MOV8rm, 0 },
500 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
501 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]502 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
503 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
504 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
505 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]506 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
507 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
508 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
509 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
510 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
511 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
512 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
513 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
514 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
515 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]516 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
517 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
518 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
519 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
520 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]521 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
522 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
523 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]524 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
525 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
526 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
527 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
528 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
529 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
530 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
531 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
532 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
533 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
534 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
535 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
536 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
537 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
538 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
539 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
540 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]541 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
542 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
543 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]544 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]545 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]546 { X86::RCPSSr, X86::RCPSSm, 0 },
547 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]548 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
549 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]550 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]551 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
552 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
553 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]554 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]555 { X86::SQRTSDr, X86::SQRTSDm, 0 },
556 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
557 { X86::SQRTSSr, X86::SQRTSSm, 0 },
558 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
559 { X86::TEST16rr, X86::TEST16rm, 0 },
560 { X86::TEST32rr, X86::TEST32rm, 0 },
561 { X86::TEST64rr, X86::TEST64rm, 0 },
562 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]563 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]564 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
565 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]566
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]567 // MMX version of foldable instructions
568 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
569 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
570 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
571 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
572 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
573 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
574 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
575 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
576 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
577 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
578
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]579 // 3DNow! version of foldable instructions
580 { X86::PF2IDrr, X86::PF2IDrm, 0 },
581 { X86::PF2IWrr, X86::PF2IWrm, 0 },
582 { X86::PFRCPrr, X86::PFRCPrm, 0 },
583 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
584 { X86::PI2FDrr, X86::PI2FDrm, 0 },
585 { X86::PI2FWrr, X86::PI2FWrm, 0 },
586 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
587
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]588 // AVX 128-bit versions of foldable instructions
589 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
590 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]591 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
592 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]593 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
594 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]595 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]596 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
597 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
598 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
600 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
601 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
602 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
603 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
604 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]605 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]606 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]607 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]608 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]609 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]610 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]611 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
612 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]613 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
614 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
615 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
616 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
617 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
618 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
619 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
620 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]621 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
622 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]623 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]624 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]625 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]626 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
627 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
628 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]629 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
630 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
631 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
632 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
633 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]634 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
635 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]636 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
637 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
638 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
639 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
640 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
641 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
642 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
643 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
644 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
645 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
646 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
647 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]648 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
649 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
650 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]651 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]652 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]653 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
654 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]655 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]656 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]657 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]658 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
659 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]660 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]661 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]662
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]663 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]664 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]665 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]666 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]667 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]668 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]669 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]670 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
671 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]672 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
673 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]674 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]675 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]676 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
677 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]678 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]679 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]680 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
681 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]682 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]683 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]684 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
685 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]686 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
687 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
688 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]689 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
690 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]691
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]692 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]693
694 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]699 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
700 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
701 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]702 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
703 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
704 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]705 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
706 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
707 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
708 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
709 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
710 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
711 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
712 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
713 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
714 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
715 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
716 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
717 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
718 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
719 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
720 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
721 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
722 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
723 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
724 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
725 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
726 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]727 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
728 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
729 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]730
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]731 // XOP foldable instructions
732 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
733 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
734 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
735 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
736 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
737 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
738 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
739 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
740 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
741 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
742 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
743 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
744 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
745 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
746 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
747 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
748 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
749 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
750 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
751 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
752 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
753 { X86::VPROTBri, X86::VPROTBmi, 0 },
754 { X86::VPROTBrr, X86::VPROTBmr, 0 },
755 { X86::VPROTDri, X86::VPROTDmi, 0 },
756 { X86::VPROTDrr, X86::VPROTDmr, 0 },
757 { X86::VPROTQri, X86::VPROTQmi, 0 },
758 { X86::VPROTQrr, X86::VPROTQmr, 0 },
759 { X86::VPROTWri, X86::VPROTWmi, 0 },
760 { X86::VPROTWrr, X86::VPROTWmr, 0 },
761 { X86::VPSHABrr, X86::VPSHABmr, 0 },
762 { X86::VPSHADrr, X86::VPSHADmr, 0 },
763 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
764 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
765 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
766 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
767 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
768 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
769
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]770 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]771 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
772 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]773 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
774 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
775 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
776 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
777 { X86::BLCI32rr, X86::BLCI32rm, 0 },
778 { X86::BLCI64rr, X86::BLCI64rm, 0 },
779 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
780 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
781 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
782 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
783 { X86::BLCS32rr, X86::BLCS32rm, 0 },
784 { X86::BLCS64rr, X86::BLCS64rm, 0 },
785 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
786 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]787 { X86::BLSI32rr, X86::BLSI32rm, 0 },
788 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]789 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
790 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]791 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
792 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
793 { X86::BLSR32rr, X86::BLSR32rm, 0 },
794 { X86::BLSR64rr, X86::BLSR64rm, 0 },
795 { X86::BZHI32rr, X86::BZHI32rm, 0 },
796 { X86::BZHI64rr, X86::BZHI64rm, 0 },
797 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
798 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
799 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
800 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
801 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
802 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]803 { X86::RORX32ri, X86::RORX32mi, 0 },
804 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]805 { X86::SARX32rr, X86::SARX32rm, 0 },
806 { X86::SARX64rr, X86::SARX64rm, 0 },
807 { X86::SHRX32rr, X86::SHRX32rm, 0 },
808 { X86::SHRX64rr, X86::SHRX64rm, 0 },
809 { X86::SHLX32rr, X86::SHLX32rm, 0 },
810 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]811 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
812 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]813 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
814 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
815 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]816 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
817 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]818
819 // AVX-512 foldable instructions
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]820 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
821 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
822 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
823 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
824 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
825 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
826 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
827 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
828 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
829 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
830 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
831 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
832 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
833 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
834 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
835 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
837 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]838
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]839 // AVX-512 foldable instructions (256-bit versions)
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]840 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
841 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
842 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
843 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
844 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
845 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
846 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
847 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
848 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
849 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
850 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
851 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
852 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
853 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]854
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]855 // AVX-512 foldable instructions (128-bit versions)
856 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
857 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
858 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
859 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
860 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
861 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
862 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
863 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
864 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
865 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
866 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
867 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]868 // F16C foldable instructions
869 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
870 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]871
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]872 // AES foldable instructions
873 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
874 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]875 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
876 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]877 };
878
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]879 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]880 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]881 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]882 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]883 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]884 }
885
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]886 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]887 { X86::ADC32rr, X86::ADC32rm, 0 },
888 { X86::ADC64rr, X86::ADC64rm, 0 },
889 { X86::ADD16rr, X86::ADD16rm, 0 },
890 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
891 { X86::ADD32rr, X86::ADD32rm, 0 },
892 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
893 { X86::ADD64rr, X86::ADD64rm, 0 },
894 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
895 { X86::ADD8rr, X86::ADD8rm, 0 },
896 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
897 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
898 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]899 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]900 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]901 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]902 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
903 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
904 { X86::AND16rr, X86::AND16rm, 0 },
905 { X86::AND32rr, X86::AND32rm, 0 },
906 { X86::AND64rr, X86::AND64rm, 0 },
907 { X86::AND8rr, X86::AND8rm, 0 },
908 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
909 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
910 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
911 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]912 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
913 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
914 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
915 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]916 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
917 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
918 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
919 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
920 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
921 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
922 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
923 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
924 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
925 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
926 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
927 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
928 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
929 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
930 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
931 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
932 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
933 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
934 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
935 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
936 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
937 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
938 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
939 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
940 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
941 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
942 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
943 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
944 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
945 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
946 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
947 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
948 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
949 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
950 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
951 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
952 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
953 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
954 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
955 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
956 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
957 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
958 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
959 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
960 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
961 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
962 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
963 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
964 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
965 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
966 { X86::CMPSDrr, X86::CMPSDrm, 0 },
967 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]968 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
969 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]970 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
971 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
972 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]973 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]974 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]975 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
976 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
977 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]978
Sanjay Patel8c13e362015-07-28 00:48:32 +0000[diff] [blame]979 // Do not fold Fs* scalar logical op loads because there are no scalar
980 // load variants for these instructions. When folded, the load is required
981 // to be 128-bits, so the load size would not match.
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]982
983 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
984 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
985 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
986 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
987 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
988 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
989 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
990 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]991 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
992 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
993 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
994 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
995 { X86::IMUL16rr, X86::IMUL16rm, 0 },
996 { X86::IMUL32rr, X86::IMUL32rm, 0 },
997 { X86::IMUL64rr, X86::IMUL64rm, 0 },
998 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
999 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]1000 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
1001 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1002 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1003 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1004 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1005 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1006 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1008 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1009 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1010 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1011 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1012 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1013 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1014 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1015 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1016 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1017 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1018 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1019 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1020 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1021 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1022 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1023 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1024 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1025 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1026 { X86::OR16rr, X86::OR16rm, 0 },
1027 { X86::OR32rr, X86::OR32rm, 0 },
1028 { X86::OR64rr, X86::OR64rm, 0 },
1029 { X86::OR8rr, X86::OR8rm, 0 },
1030 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1031 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1032 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1033 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1034 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1035 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1036 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1037 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1038 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1039 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1040 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1041 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1042 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1043 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1044 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1045 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1046 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1047 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1048 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1049 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1050 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1051 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1052 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1053 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1054 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1055 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1056 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1057 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1058 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1059 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1060 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1061 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1062 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1063 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1064 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1065 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1066 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1067 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1068 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1069 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1070 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1071 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1072 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1073 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1074 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1075 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1076 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1077 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1078 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1079 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1080 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1081 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1082 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1083 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1084 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1085 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1086 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1087 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1088 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1089 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1090 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1091 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1092 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1093 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1094 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1095 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1096 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1097 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1098 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1099 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1100 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1101 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1102 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1103 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1104 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1105 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1106 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1107 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1108 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1109 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1110 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1111 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1112 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1113 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1114 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1115 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1116 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1117 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1118 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1119 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1120 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1121 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1122 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1123 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1124 { X86::SBB32rr, X86::SBB32rm, 0 },
1125 { X86::SBB64rr, X86::SBB64rm, 0 },
1126 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1127 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1128 { X86::SUB16rr, X86::SUB16rm, 0 },
1129 { X86::SUB32rr, X86::SUB32rm, 0 },
1130 { X86::SUB64rr, X86::SUB64rm, 0 },
1131 { X86::SUB8rr, X86::SUB8rm, 0 },
1132 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1133 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1134 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1135 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1136 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1137 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1138 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1139 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1140 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1141 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1142 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1143 { X86::XOR16rr, X86::XOR16rm, 0 },
1144 { X86::XOR32rr, X86::XOR32rm, 0 },
1145 { X86::XOR64rr, X86::XOR64rm, 0 },
1146 { X86::XOR8rr, X86::XOR8rm, 0 },
1147 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1148 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1149
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1150 // MMX version of foldable instructions
1151 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1152 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1153 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1154 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1155 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1156 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1157 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1158 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1159 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1160 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1161 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1162 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1163 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1164 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1165 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1166 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1167 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1168 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1169 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1170 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1171 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1172 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1173 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1174 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1175 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1176 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1177 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1178 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1179 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1180 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1181 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1182 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1183 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1184 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1185 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1186 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1187 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1188 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1189 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1190 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1191 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1192 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1193 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1194 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1195 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1196 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1197 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1198 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1199 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1200 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1201 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1202 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1203 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1204 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1205 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1206 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1207 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1208 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1209 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1210 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1211 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1212 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1213 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1214 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1215 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1216 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1217 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1218 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1219 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1220 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1221
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1222 // 3DNow! version of foldable instructions
1223 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1224 { X86::PFACCrr, X86::PFACCrm, 0 },
1225 { X86::PFADDrr, X86::PFADDrm, 0 },
1226 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1227 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1228 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1229 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1230 { X86::PFMINrr, X86::PFMINrm, 0 },
1231 { X86::PFMULrr, X86::PFMULrm, 0 },
1232 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1233 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1234 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1235 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1236 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1237 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1238 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1239 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1240
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1241 // AVX 128-bit versions of foldable instructions
1242 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1243 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1244 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1245 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1246 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1247 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1248 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1249 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1250 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1251 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1252 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1253 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1254 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1255 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1256 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1257 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1258 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1259 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1260 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1261 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1262 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1263 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1264 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1265 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1266 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1267 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1268 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1269 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1270 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1271 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1272 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1273 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1274 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1275 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1276 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1277 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1278 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1279 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1280 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1281 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1282 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1283 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1284 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1285 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1286 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1287 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1288 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1289 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]1290 // Do not fold VFs* loads because there are no scalar load variants for
1291 // these instructions. When folded, the load is required to be 128-bits, so
1292 // the load size would not match.
1293 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1294 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1295 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1296 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1297 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1298 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1299 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1300 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1301 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1302 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1303 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1304 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1305 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1306 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1307 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1308 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1309 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1310 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1311 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1312 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1313 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1314 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1315 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1316 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1317 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1318 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1319 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1320 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1321 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1322 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1323 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1324 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1325 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1326 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1327 { X86::VORPDrr, X86::VORPDrm, 0 },
1328 { X86::VORPSrr, X86::VORPSrm, 0 },
1329 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1330 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1331 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1332 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1333 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1334 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1335 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1336 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1337 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1338 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1339 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1340 { X86::VPADDWrr, X86::VPADDWrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1341 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1342 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1343 { X86::VPANDrr, X86::VPANDrm, 0 },
1344 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1345 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1346 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1347 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1348 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1349 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1350 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1351 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1352 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1353 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1354 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1355 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1356 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1357 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1358 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1359 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1360 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1361 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1362 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1363 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1364 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1365 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1366 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1367 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1368 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1369 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1370 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1371 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1372 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1373 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1374 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1375 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1376 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1377 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1378 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1379 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1380 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1381 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1382 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1383 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1384 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1385 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1386 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1387 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1388 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1389 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1390 { X86::VPORrr, X86::VPORrm, 0 },
1391 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1392 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1393 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1394 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1395 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1396 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1397 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1398 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1399 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1400 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1401 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1402 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1403 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1404 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1405 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1406 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1407 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1408 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1409 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1410 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1411 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1412 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1413 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1414 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1415 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1416 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1417 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1418 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1419 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1420 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1421 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1422 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1423 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1424 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1425 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1426 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1427 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1428 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1429 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1430 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1431 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1432 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1433 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1434 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1435 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1436 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1437
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1438 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1439 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1440 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1441 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1442 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1443 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1444 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1445 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1446 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1447 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1448 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1449 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1450 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1451 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1452 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1453 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1454 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1455 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1456 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1457 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1458 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1459 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1460 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1461 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1462 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1463 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1464 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1465 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1466 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1467 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1468 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1469 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1470 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1471 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1472 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1473 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1474 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1475 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1476 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1477 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1478 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1479 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1480 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1481 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1482
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1483 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1484 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1485 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1486 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1487 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1488 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1489 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1490 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1491 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1492 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1493 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1494 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1495 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1496 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1497 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1498 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1499 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1500 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1501 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1502 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1503 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1504 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1505 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1506 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1507 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1508 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1509 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1510 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1511 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1512 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1513 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1514 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1515 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1516 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1517 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1518 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1519 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1520 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1521 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1522 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1523 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1524 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1525 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1526 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1527 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1528 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1529 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1530 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1531 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1532 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1533 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1534 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1535 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1536 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1537 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1538 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1539 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1540 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1541 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1542 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1543 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1544 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1545 { X86::VPORYrr, X86::VPORYrm, 0 },
1546 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1547 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1548 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1549 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1550 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1551 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1552 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1553 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1554 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1555 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1556 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1557 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1558 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1559 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1560 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1561 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
Igor Bregere59165c2016-06-20 07:05:43 +0000[diff] [blame]1562 { X86::VPSRAVD_Intrr, X86::VPSRAVD_Intrm, 0 },
1563 { X86::VPSRAVD_IntYrr, X86::VPSRAVD_IntYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1564 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1565 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1566 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1567 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1568 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1569 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1570 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1571 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1572 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1573 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1574 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1575 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1576 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1577 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1578 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1579 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1580 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1581 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1582 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1583 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1584 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1585 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1586 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1587 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1588
1589 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1590 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1591 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1592 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1593 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1594 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1595 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1596 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1597 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1598 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1599 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1600 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1601 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1602 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1603 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1604 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1605 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1606 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1607 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1608 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1609 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1610 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1611 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1612 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1613 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1614 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1615 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1616 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1617 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1618 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1619 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1620 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1621 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1622
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1623 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1624 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1625 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1626 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1627 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1628 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1629 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1630 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1631 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1632 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1633 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1634 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1635 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1636 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1637 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1638 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1639 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1640 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1641 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1642 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1643 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1644 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1645 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1646 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1647 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1648 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1649 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1650 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1651 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1652 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1653 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1654 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1655 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1656 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1657 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1658 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1659 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1660 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1661 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1662 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1663
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1664 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1665 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1666 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1667 { X86::MULX32rr, X86::MULX32rm, 0 },
1668 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1669 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1670 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1671 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1672 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1673
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1674 // ADX foldable instructions
1675 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1676 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1677 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1678 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1679
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1680 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1681 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1682 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]1683 { X86::VADDSSZrr, X86::VADDSSZrm, 0 },
1684 { X86::VADDSSZrr_Int, X86::VADDSSZrm_Int, 0 },
1685 { X86::VADDSDZrr, X86::VADDSDZrm, 0 },
1686 { X86::VADDSDZrr_Int, X86::VADDSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1687 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1688 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]1689 { X86::VSUBSSZrr, X86::VSUBSSZrm, 0 },
1690 { X86::VSUBSSZrr_Int, X86::VSUBSSZrm_Int, 0 },
1691 { X86::VSUBSDZrr, X86::VSUBSDZrm, 0 },
1692 { X86::VSUBSDZrr_Int, X86::VSUBSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1693 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1694 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]1695 { X86::VMULSSZrr, X86::VMULSSZrm, 0 },
1696 { X86::VMULSSZrr_Int, X86::VMULSSZrm_Int, 0 },
1697 { X86::VMULSDZrr, X86::VMULSDZrm, 0 },
1698 { X86::VMULSDZrr_Int, X86::VMULSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1699 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1700 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]1701 { X86::VDIVSSZrr, X86::VDIVSSZrm, 0 },
1702 { X86::VDIVSSZrr_Int, X86::VDIVSSZrm_Int, 0 },
1703 { X86::VDIVSDZrr, X86::VDIVSDZrm, 0 },
1704 { X86::VDIVSDZrr_Int, X86::VDIVSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1705 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1706 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1707 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1708 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1709 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1710 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1711 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1712 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1713 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1714 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1715 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1716 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1717 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1718 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1719 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1720 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1721 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1722 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1723 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1724 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1725 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1726 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1727 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1728 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1729 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1730 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1731 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1732 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1733 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1734 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1735 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1736
1737 // AVX-512{F,VL} foldable instructions
1738 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1739 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1740 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1741
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1742 // AVX-512{F,VL} foldable instructions
1743 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1744 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1745 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1746 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1747
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1748 // AES foldable instructions
1749 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1750 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1751 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1752 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1753 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1754 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1755 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1756 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1757
1758 // SHA foldable instructions
1759 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1760 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1761 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1762 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1763 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1764 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1765 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1766 };
1767
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1768 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1769 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1770 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1771 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1772 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1773 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1774
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1775 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1776 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1777 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1778 { X86::VFMADDSSr231r_Int, X86::VFMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1779 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1780 { X86::VFMADDSDr231r_Int, X86::VFMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1781 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1782 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1783 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1784 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1785 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1786 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1787 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1788 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1789
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1790 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1791 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1792 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1793 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1794 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1795 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1796 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1797 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1798 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1799 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1800 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1801 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1802
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1803 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1804 { X86::VFNMADDSSr231r_Int, X86::VFNMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1805 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1806 { X86::VFNMADDSDr231r_Int, X86::VFNMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1807 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1808 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1809 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1810 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1811 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1812 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1813 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1814 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1815
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1816 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1817 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1818 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1819 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1820 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1821 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1822 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1823 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1824 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1825 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1826 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1827 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1828
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1829 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1830 { X86::VFMSUBSSr231r_Int, X86::VFMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1831 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1832 { X86::VFMSUBSDr231r_Int, X86::VFMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1833 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1834 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1835 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1836 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1837 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1838 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1839 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1840 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1841
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1842 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1843 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1844 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1845 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1846 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1847 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1848 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1849 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1850 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1851 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1852 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1853 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1854
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1855 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1856 { X86::VFNMSUBSSr231r_Int, X86::VFNMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1857 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1858 { X86::VFNMSUBSDr231r_Int, X86::VFNMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1859 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1860 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1861 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1862 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1863 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1864 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1865 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1866 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1867
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1868 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1869 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1870 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1871 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1872 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1873 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1874 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1875 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1876 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1877 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1878 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1879 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1880
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1881 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1882 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1883 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1884 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1885 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1886 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1887 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1888 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1889 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1890 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1891 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1892 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1893
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1894 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1895 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1896 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1897 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1898 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1899 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1900 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1901 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1902 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1903 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1904 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1905 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1906
1907 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1908 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1909 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1910 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1911 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1912 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1913 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1914 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1915 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1916 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1917 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1918 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1919 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1920 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1921 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1922 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1923 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1924 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1925 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1926 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1927 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1928 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1929 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1930 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1931 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1932 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1933 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1934 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1935 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1936 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1937 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1938 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1939 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1940
1941 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1942 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
1943 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1944 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1945 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1946 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1947 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1948 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1949
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1950 // AVX-512 VPERMI instructions with 3 source operands.
1951 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1952 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1953 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1954 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1955 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1956 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1957 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1958 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1959 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1960 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1961 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1962 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1963 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1964 // AVX-512 arithmetic instructions
1965 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1966 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1967 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1968 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1969 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1970 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1971 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1972 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1973 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1974 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1975 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1976 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1977 // AVX-512{F,VL} arithmetic instructions 256-bit
1978 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1979 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1980 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1981 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1982 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1983 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1984 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1985 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1986 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1987 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1988 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1989 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1990 // AVX-512{F,VL} arithmetic instructions 128-bit
1991 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1992 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1993 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1994 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1995 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1996 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1997 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1998 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1999 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
2000 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
2001 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
2002 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2003 };
2004
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2005 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2006 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2007 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2008 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2009 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2010 }
2011
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]2012 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2013 // AVX-512 foldable instructions
2014 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
2015 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
2016 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2017 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2018 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2019 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2020 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2021 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2022 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2023 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
2024 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2025 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
2026 // AVX-512{F,VL} foldable instructions 256-bit
2027 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2028 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2029 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2030 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2031 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2032 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2033 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2034 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2035 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2036 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2037 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2038 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2039 // AVX-512{F,VL} foldable instructions 128-bit
2040 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2041 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2042 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2043 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2044 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2045 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2046 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2047 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2048 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2049 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2050 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2051 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2052 };
2053
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2054 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2055 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2056 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2057 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2058 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2059 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2060}
2061
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2062void
2063X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2064 MemOp2RegOpTableType &M2RTable,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]2065 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2066 if ((Flags & TB_NO_FORWARD) == 0) {
2067 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2068 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2069 }
2070 if ((Flags & TB_NO_REVERSE) == 0) {
2071 assert(!M2RTable.count(MemOp) &&
2072 "Duplicated entries in unfolding maps?");
2073 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2074 }
2075}
2076
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2077bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2078X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2079 unsigned &SrcReg, unsigned &DstReg,
2080 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2081 switch (MI.getOpcode()) {
2082 default: break;
2083 case X86::MOVSX16rr8:
2084 case X86::MOVZX16rr8:
2085 case X86::MOVSX32rr8:
2086 case X86::MOVZX32rr8:
2087 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2088 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2089 // It's not always legal to reference the low 8-bit of the larger
2090 // register in 32-bit mode.
2091 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2092 case X86::MOVSX32rr16:
2093 case X86::MOVZX32rr16:
2094 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2095 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2096 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2097 // Be conservative.
2098 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2099 SrcReg = MI.getOperand(1).getReg();
2100 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2101 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2102 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2103 case X86::MOVSX16rr8:
2104 case X86::MOVZX16rr8:
2105 case X86::MOVSX32rr8:
2106 case X86::MOVZX32rr8:
2107 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2108 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2109 break;
2110 case X86::MOVSX32rr16:
2111 case X86::MOVZX32rr16:
2112 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2113 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2114 break;
2115 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2116 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2117 break;
2118 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2119 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2120 }
2121 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2122 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2123}
2124
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2125int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2126 const MachineFunction *MF = MI.getParent()->getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2127 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2128
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2129 if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2130 MI.getOpcode() == getCallFrameDestroyOpcode()) {
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2131 unsigned StackAlign = TFI->getStackAlignment();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2132 int SPAdj =
2133 (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2134
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2135 SPAdj -= MI.getOperand(1).getImm();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2136
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2137 if (MI.getOpcode() == getCallFrameSetupOpcode())
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2138 return SPAdj;
2139 else
2140 return -SPAdj;
2141 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2142
2143 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2144 // that is bound to the following ADJCALLSTACKUP pseudo.
2145 // Look for the next ADJCALLSTACKUP that follows the call.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2146 if (MI.isCall()) {
2147 const MachineBasicBlock *MBB = MI.getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2148 auto I = ++MachineBasicBlock::const_iterator(MI);
2149 for (auto E = MBB->end(); I != E; ++I) {
2150 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2151 I->isCall())
2152 break;
2153 }
2154
2155 // If we could not find a frame destroy opcode, then it has already
2156 // been simplified, so we don't care.
2157 if (I->getOpcode() != getCallFrameDestroyOpcode())
2158 return 0;
2159
2160 return -(I->getOperand(1).getImm());
2161 }
2162
2163 // Currently handle only PUSHes we can reasonably expect to see
2164 // in call sequences
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2165 switch (MI.getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2166 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2167 return 0;
2168 case X86::PUSH32i8:
2169 case X86::PUSH32r:
2170 case X86::PUSH32rmm:
2171 case X86::PUSH32rmr:
2172 case X86::PUSHi32:
2173 return 4;
David L Kreitzer0fe46322016-05-02 13:45:25 +0000[diff] [blame]2174 case X86::PUSH64i8:
2175 case X86::PUSH64r:
2176 case X86::PUSH64rmm:
2177 case X86::PUSH64rmr:
2178 case X86::PUSH64i32:
2179 return 8;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2180 }
2181}
2182
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2183/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2184/// operand and follow operands form a reference to the stack frame.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2185bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2186 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2187 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2188 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2189 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2190 MI.getOperand(Op + X86::AddrDisp).isImm() &&
2191 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2192 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2193 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2194 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2195 return true;
2196 }
2197 return false;
2198}
2199
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2200static bool isFrameLoadOpcode(int Opcode) {
2201 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2202 default:
2203 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2204 case X86::MOV8rm:
2205 case X86::MOV16rm:
2206 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2207 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2208 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2209 case X86::MOVSSrm:
2210 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2211 case X86::MOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2212 case X86::MOVUPSrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2213 case X86::MOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2214 case X86::MOVUPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2215 case X86::MOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2216 case X86::MOVDQUrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2217 case X86::VMOVSSrm:
2218 case X86::VMOVSDrm:
2219 case X86::VMOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2220 case X86::VMOVUPSrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2221 case X86::VMOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2222 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2223 case X86::VMOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2224 case X86::VMOVDQUrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2225 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2226 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2227 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2228 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2229 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2230 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2231 case X86::MMX_MOVD64rm:
2232 case X86::MMX_MOVQ64rm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2233 case X86::VMOVSSZrm:
2234 case X86::VMOVSDZrm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2235 case X86::VMOVAPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2236 case X86::VMOVAPSZ128rm:
2237 case X86::VMOVAPSZ256rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2238 case X86::VMOVUPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2239 case X86::VMOVUPSZ128rm:
2240 case X86::VMOVUPSZ256rm:
2241 case X86::VMOVAPDZrm:
2242 case X86::VMOVAPDZ128rm:
2243 case X86::VMOVAPDZ256rm:
2244 case X86::VMOVUPDZrm:
2245 case X86::VMOVUPDZ128rm:
2246 case X86::VMOVUPDZ256rm:
2247 case X86::VMOVDQA32Zrm:
2248 case X86::VMOVDQA32Z128rm:
2249 case X86::VMOVDQA32Z256rm:
2250 case X86::VMOVDQU32Zrm:
2251 case X86::VMOVDQU32Z128rm:
2252 case X86::VMOVDQU32Z256rm:
2253 case X86::VMOVDQA64Zrm:
2254 case X86::VMOVDQA64Z128rm:
2255 case X86::VMOVDQA64Z256rm:
2256 case X86::VMOVDQU64Zrm:
2257 case X86::VMOVDQU64Z128rm:
2258 case X86::VMOVDQU64Z256rm:
2259 case X86::VMOVDQU8Zrm:
2260 case X86::VMOVDQU8Z128rm:
2261 case X86::VMOVDQU8Z256rm:
2262 case X86::VMOVDQU16Zrm:
2263 case X86::VMOVDQU16Z128rm:
2264 case X86::VMOVDQU16Z256rm:
2265 case X86::KMOVBkm:
2266 case X86::KMOVWkm:
2267 case X86::KMOVDkm:
2268 case X86::KMOVQkm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2269 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2270 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2271}
2272
2273static bool isFrameStoreOpcode(int Opcode) {
2274 switch (Opcode) {
2275 default: break;
2276 case X86::MOV8mr:
2277 case X86::MOV16mr:
2278 case X86::MOV32mr:
2279 case X86::MOV64mr:
2280 case X86::ST_FpP64m:
2281 case X86::MOVSSmr:
2282 case X86::MOVSDmr:
2283 case X86::MOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2284 case X86::MOVUPSmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2285 case X86::MOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2286 case X86::MOVUPDmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2287 case X86::MOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2288 case X86::MOVDQUmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2289 case X86::VMOVSSmr:
2290 case X86::VMOVSDmr:
2291 case X86::VMOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2292 case X86::VMOVUPSmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2293 case X86::VMOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2294 case X86::VMOVUPDmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2295 case X86::VMOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2296 case X86::VMOVDQUmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2297 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2298 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2299 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2300 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2301 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2302 case X86::VMOVDQAYmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2303 case X86::VMOVSSZmr:
2304 case X86::VMOVSDZmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2305 case X86::VMOVUPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2306 case X86::VMOVUPSZ128mr:
2307 case X86::VMOVUPSZ256mr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2308 case X86::VMOVAPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2309 case X86::VMOVAPSZ128mr:
2310 case X86::VMOVAPSZ256mr:
2311 case X86::VMOVUPDZmr:
2312 case X86::VMOVUPDZ128mr:
2313 case X86::VMOVUPDZ256mr:
2314 case X86::VMOVAPDZmr:
2315 case X86::VMOVAPDZ128mr:
2316 case X86::VMOVAPDZ256mr:
2317 case X86::VMOVDQA32Zmr:
2318 case X86::VMOVDQA32Z128mr:
2319 case X86::VMOVDQA32Z256mr:
2320 case X86::VMOVDQU32Zmr:
2321 case X86::VMOVDQU32Z128mr:
2322 case X86::VMOVDQU32Z256mr:
2323 case X86::VMOVDQA64Zmr:
2324 case X86::VMOVDQA64Z128mr:
2325 case X86::VMOVDQA64Z256mr:
2326 case X86::VMOVDQU64Zmr:
2327 case X86::VMOVDQU64Z128mr:
2328 case X86::VMOVDQU64Z256mr:
2329 case X86::VMOVDQU8Zmr:
2330 case X86::VMOVDQU8Z128mr:
2331 case X86::VMOVDQU8Z256mr:
2332 case X86::VMOVDQU16Zmr:
2333 case X86::VMOVDQU16Z128mr:
2334 case X86::VMOVDQU16Z256mr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2335 case X86::MMX_MOVD64mr:
2336 case X86::MMX_MOVQ64mr:
2337 case X86::MMX_MOVNTQmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2338 case X86::KMOVBmk:
2339 case X86::KMOVWmk:
2340 case X86::KMOVDmk:
2341 case X86::KMOVQmk:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2342 return true;
2343 }
2344 return false;
2345}
2346
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2347unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2348 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2349 if (isFrameLoadOpcode(MI.getOpcode()))
2350 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2351 return MI.getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2352 return 0;
2353}
2354
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2355unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2356 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2357 if (isFrameLoadOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2358 unsigned Reg;
2359 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2360 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2361 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2362 const MachineMemOperand *Dummy;
2363 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2364 }
2365 return 0;
2366}
2367
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2368unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2369 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2370 if (isFrameStoreOpcode(MI.getOpcode()))
2371 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2372 isFrameOperand(MI, 0, FrameIndex))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2373 return MI.getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2374 return 0;
2375}
2376
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2377unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2378 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2379 if (isFrameStoreOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2380 unsigned Reg;
2381 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2382 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2383 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2384 const MachineMemOperand *Dummy;
2385 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2386 }
2387 return 0;
2388}
2389
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2390/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2391static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2392 // Don't waste compile time scanning use-def chains of physregs.
2393 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2394 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2395 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2396 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2397 E = MRI.def_instr_end(); I != E; ++I) {
2398 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2399 if (DefMI->getOpcode() != X86::MOVPC32r)
2400 return false;
2401 assert(!isPICBase && "More than one PIC base?");
2402 isPICBase = true;
2403 }
2404 return isPICBase;
2405}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2406
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2407bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2408 AliasAnalysis *AA) const {
2409 switch (MI.getOpcode()) {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2410 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2411 case X86::MOV8rm:
2412 case X86::MOV16rm:
2413 case X86::MOV32rm:
2414 case X86::MOV64rm:
2415 case X86::LD_Fp64m:
2416 case X86::MOVSSrm:
2417 case X86::MOVSDrm:
2418 case X86::MOVAPSrm:
2419 case X86::MOVUPSrm:
2420 case X86::MOVAPDrm:
2421 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2422 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2423 case X86::VMOVSSrm:
2424 case X86::VMOVSDrm:
2425 case X86::VMOVAPSrm:
2426 case X86::VMOVUPSrm:
2427 case X86::VMOVAPDrm:
2428 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2429 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2430 case X86::VMOVAPSYrm:
2431 case X86::VMOVUPSYrm:
2432 case X86::VMOVAPDYrm:
2433 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2434 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2435 case X86::MMX_MOVD64rm:
2436 case X86::MMX_MOVQ64rm:
2437 case X86::FsVMOVAPSrm:
2438 case X86::FsVMOVAPDrm:
2439 case X86::FsMOVAPSrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2440 case X86::FsMOVAPDrm:
2441 // AVX-512
2442 case X86::VMOVAPDZ128rm:
2443 case X86::VMOVAPDZ256rm:
2444 case X86::VMOVAPDZrm:
2445 case X86::VMOVAPSZ128rm:
2446 case X86::VMOVAPSZ256rm:
2447 case X86::VMOVAPSZrm:
2448 case X86::VMOVDQA32Z128rm:
2449 case X86::VMOVDQA32Z256rm:
2450 case X86::VMOVDQA32Zrm:
2451 case X86::VMOVDQA64Z128rm:
2452 case X86::VMOVDQA64Z256rm:
2453 case X86::VMOVDQA64Zrm:
2454 case X86::VMOVDQU16Z128rm:
2455 case X86::VMOVDQU16Z256rm:
2456 case X86::VMOVDQU16Zrm:
2457 case X86::VMOVDQU32Z128rm:
2458 case X86::VMOVDQU32Z256rm:
2459 case X86::VMOVDQU32Zrm:
2460 case X86::VMOVDQU64Z128rm:
2461 case X86::VMOVDQU64Z256rm:
2462 case X86::VMOVDQU64Zrm:
2463 case X86::VMOVDQU8Z128rm:
2464 case X86::VMOVDQU8Z256rm:
2465 case X86::VMOVDQU8Zrm:
2466 case X86::VMOVUPSZ128rm:
2467 case X86::VMOVUPSZ256rm:
2468 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2469 // Loads from constant pools are trivially rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2470 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2471 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2472 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2473 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2474 MI.isInvariantLoad(AA)) {
2475 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2476 if (BaseReg == 0 || BaseReg == X86::RIP)
2477 return true;
2478 // Allow re-materialization of PIC load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2479 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2480 return false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2481 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2482 const MachineRegisterInfo &MRI = MF.getRegInfo();
2483 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2484 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2485 return false;
2486 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2487
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2488 case X86::LEA32r:
2489 case X86::LEA64r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2490 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2491 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2492 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2493 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2494 // lea fi#, lea GV, etc. are all rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2495 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2496 return true;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2497 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2498 if (BaseReg == 0)
2499 return true;
2500 // Allow re-materialization of lea PICBase + x.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2501 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2502 const MachineRegisterInfo &MRI = MF.getRegInfo();
2503 return regIsPICBase(BaseReg, MRI);
2504 }
2505 return false;
2506 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2507 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2508
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2509 // All other instructions marked M_REMATERIALIZABLE are always trivially
2510 // rematerializable.
2511 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2512}
2513
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2514bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2515 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2516 MachineBasicBlock::iterator E = MBB.end();
2517
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2518 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2519 // safety after visiting 4 instructions in each direction, we will assume
2520 // it's not safe.
2521 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2522 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2523 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2524 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2525 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2526 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2527 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2528 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2529 continue;
2530 if (MO.getReg() == X86::EFLAGS) {
2531 if (MO.isUse())
2532 return false;
2533 SeenDef = true;
2534 }
2535 }
2536
2537 if (SeenDef)
2538 // This instruction defines EFLAGS, no need to look any further.
2539 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2540 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2541 // Skip over DBG_VALUE.
2542 while (Iter != E && Iter->isDebugValue())
2543 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2544 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2545
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2546 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2547 // live in.
2548 if (Iter == E) {
Craig Topperca66fc52015-12-20 18:41:57 +0000[diff] [blame]2549 for (MachineBasicBlock *S : MBB.successors())
2550 if (S->isLiveIn(X86::EFLAGS))
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2551 return false;
2552 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2553 }
2554
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2555 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2556 Iter = I;
2557 for (unsigned i = 0; i < 4; ++i) {
2558 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2559 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2560 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2561 return !MBB.isLiveIn(X86::EFLAGS);
2562
2563 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2564 // Skip over DBG_VALUE.
2565 while (Iter != B && Iter->isDebugValue())
2566 --Iter;
2567
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2568 bool SawKill = false;
2569 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2570 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2571 // A register mask may clobber EFLAGS, but we should still look for a
2572 // live EFLAGS def.
2573 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2574 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2575 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2576 if (MO.isDef()) return MO.isDead();
2577 if (MO.isKill()) SawKill = true;
2578 }
2579 }
2580
2581 if (SawKill)
2582 // This instruction kills EFLAGS and doesn't redefine it, so
2583 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2584 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2585 }
2586
2587 // Conservative answer.
2588 return false;
2589}
2590
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2591void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2592 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2593 unsigned DestReg, unsigned SubIdx,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2594 const MachineInstr &Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2595 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2596 bool ClobbersEFLAGS = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2597 for (const MachineOperand &MO : Orig.operands()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2598 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2599 ClobbersEFLAGS = true;
2600 break;
2601 }
2602 }
2603
2604 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2605 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2606 // effects.
2607 int Value;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2608 switch (Orig.getOpcode()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2609 case X86::MOV32r0: Value = 0; break;
2610 case X86::MOV32r1: Value = 1; break;
2611 case X86::MOV32r_1: Value = -1; break;
2612 default:
2613 llvm_unreachable("Unexpected instruction!");
2614 }
2615
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2616 const DebugLoc &DL = Orig.getDebugLoc();
2617 BuildMI(MBB, I, DL, get(X86::MOV32ri))
2618 .addOperand(Orig.getOperand(0))
2619 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2620 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2621 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2622 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2623 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2624
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]2625 MachineInstr &NewMI = *std::prev(I);
2626 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2627}
2628
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2629/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2630bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2631 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2632 MachineOperand &MO = MI.getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2633 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2634 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2635 return true;
2636 }
2637 }
2638 return false;
2639}
2640
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2641/// Check whether the shift count for a machine operand is non-zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2642inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2643 unsigned ShiftAmtOperandIdx) {
2644 // The shift count is six bits with the REX.W prefix and five bits without.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2645 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2646 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2647 return Imm & ShiftCountMask;
2648}
2649
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2650/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2651/// can be represented by a LEA instruction.
2652inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2653 // Left shift instructions can be transformed into load-effective-address
2654 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2655 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2656 // The SIB.scale field is two bits wide which means that we can encode any
2657 // shift amount less than 4.
2658 return ShAmt < 4 && ShAmt > 0;
2659}
2660
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2661bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2662 unsigned Opc, bool AllowSP, unsigned &NewSrc,
2663 bool &isKill, bool &isUndef,
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2664 MachineOperand &ImplicitOp) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2665 MachineFunction &MF = *MI.getParent()->getParent();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2666 const TargetRegisterClass *RC;
2667 if (AllowSP) {
2668 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2669 } else {
2670 RC = Opc != X86::LEA32r ?
2671 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2672 }
2673 unsigned SrcReg = Src.getReg();
2674
2675 // For both LEA64 and LEA32 the register already has essentially the right
2676 // type (32-bit or 64-bit) we may just need to forbid SP.
2677 if (Opc != X86::LEA64_32r) {
2678 NewSrc = SrcReg;
2679 isKill = Src.isKill();
2680 isUndef = Src.isUndef();
2681
2682 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2683 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2684 return false;
2685
2686 return true;
2687 }
2688
2689 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2690 // another we need to add 64-bit registers to the final MI.
2691 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2692 ImplicitOp = Src;
2693 ImplicitOp.setImplicit();
2694
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]2695 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2696 MachineBasicBlock::LivenessQueryResult LQR =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2697 MI.getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2698
2699 switch (LQR) {
2700 case MachineBasicBlock::LQR_Unknown:
2701 // We can't give sane liveness flags to the instruction, abandon LEA
2702 // formation.
2703 return false;
2704 case MachineBasicBlock::LQR_Live:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2705 isKill = MI.killsRegister(SrcReg);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2706 isUndef = false;
2707 break;
2708 default:
2709 // The physreg itself is dead, so we have to use it as an <undef>.
2710 isKill = false;
2711 isUndef = true;
2712 break;
2713 }
2714 } else {
2715 // Virtual register of the wrong class, we have to create a temporary 64-bit
2716 // vreg to feed into the LEA.
2717 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2718 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2719 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2720 .addOperand(Src);
2721
2722 // Which is obviously going to be dead after we're done with it.
2723 isKill = true;
2724 isUndef = false;
2725 }
2726
2727 // We've set all the parameters without issue.
2728 return true;
2729}
2730
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2731/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2732/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2733/// truncating back down to a 16-bit subregister.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2734MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2735 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2736 LiveVariables *LV) const {
2737 MachineBasicBlock::iterator MBBI = MI.getIterator();
2738 unsigned Dest = MI.getOperand(0).getReg();
2739 unsigned Src = MI.getOperand(1).getReg();
2740 bool isDead = MI.getOperand(0).isDead();
2741 bool isKill = MI.getOperand(1).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2742
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2743 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2744 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2745 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2746 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2747 Opc = X86::LEA64_32r;
2748 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2749 } else {
2750 Opc = X86::LEA32r;
2751 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2752 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2753
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2754 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2755 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2756 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2757 // movw (%rbp,%rcx,2), %dx
2758 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2759 // But testing has shown this *does* help performance in 64-bit mode (at
2760 // least on modern x86 machines).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2761 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2762 MachineInstr *InsMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2763 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2764 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2765 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2766
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2767 MachineInstrBuilder MIB =
2768 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2769 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2770 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2771 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2772 unsigned ShAmt = MI.getOperand(2).getImm();
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2773 MIB.addReg(0).addImm(1ULL << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2774 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2775 break;
2776 }
2777 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2778 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2779 break;
2780 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2781 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2782 break;
2783 case X86::ADD16ri:
2784 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2785 case X86::ADD16ri_DB:
2786 case X86::ADD16ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2787 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2788 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2789 case X86::ADD16rr:
2790 case X86::ADD16rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2791 unsigned Src2 = MI.getOperand(2).getReg();
2792 bool isKill2 = MI.getOperand(2).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2793 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2794 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2795 if (Src == Src2) {
2796 // ADD16rr %reg1028<kill>, %reg1028
2797 // just a single insert_subreg.
2798 addRegReg(MIB, leaInReg, true, leaInReg, false);
2799 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2800 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2801 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2802 else
2803 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2804 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2805 // well be shifting and then extracting the lower 16-bits.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2806 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2807 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2808 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2809 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2810 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2811 }
2812 if (LV && isKill2 && InsMI2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2813 LV->replaceKillInstruction(Src2, MI, *InsMI2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2814 break;
2815 }
2816 }
2817
2818 MachineInstr *NewMI = MIB;
2819 MachineInstr *ExtMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2820 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2821 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2822 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2823
2824 if (LV) {
2825 // Update live variables
2826 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2827 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2828 if (isKill)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2829 LV->replaceKillInstruction(Src, MI, *InsMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2830 if (isDead)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2831 LV->replaceKillInstruction(Dest, MI, *ExtMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2832 }
2833
2834 return ExtMI;
2835}
2836
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2837/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2838/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2839/// may be able to convert a two-address instruction into a true
2840/// three-address instruction on demand. This allows the X86 target (for
2841/// example) to convert ADD and SHL instructions into LEA instructions if they
2842/// would require register copies due to two-addressness.
2843///
2844/// This method returns a null pointer if the transformation cannot be
2845/// performed, otherwise it returns the new instruction.
2846///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2847MachineInstr *
2848X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2849 MachineInstr &MI, LiveVariables *LV) const {
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2850 // The following opcodes also sets the condition code register(s). Only
2851 // convert them to equivalent lea if the condition code register def's
2852 // are dead!
2853 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2854 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2855
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2856 MachineFunction &MF = *MI.getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2857 // All instructions input are two-addr instructions. Get the known operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2858 const MachineOperand &Dest = MI.getOperand(0);
2859 const MachineOperand &Src = MI.getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2860
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2861 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2862 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2863 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2864 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2865 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2866 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2867
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2868 unsigned MIOpc = MI.getOpcode();
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2869 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2870 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2871 case X86::SHL64ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2872 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2873 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2874 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2875
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2876 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2877 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2878 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2879 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2880 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2881
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2882 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2883 .addOperand(Dest)
2884 .addReg(0)
2885 .addImm(1ULL << ShAmt)
2886 .addOperand(Src)
2887 .addImm(0)
2888 .addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2889 break;
2890 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2891 case X86::SHL32ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2892 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2893 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2894 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2895
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2896 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2897
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2898 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2899 bool isKill, isUndef;
2900 unsigned SrcReg;
2901 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2902 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2903 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2904 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2905
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2906 MachineInstrBuilder MIB =
2907 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2908 .addOperand(Dest)
2909 .addReg(0)
2910 .addImm(1ULL << ShAmt)
2911 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2912 .addImm(0)
2913 .addReg(0);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2914 if (ImplicitOp.getReg() != 0)
2915 MIB.addOperand(ImplicitOp);
2916 NewMI = MIB;
2917
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2918 break;
2919 }
2920 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2921 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2922 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2923 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2924
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2925 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2926 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2927 : nullptr;
2928 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2929 .addOperand(Dest)
2930 .addReg(0)
2931 .addImm(1ULL << ShAmt)
2932 .addOperand(Src)
2933 .addImm(0)
2934 .addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2935 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2936 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2937 case X86::INC64r:
2938 case X86::INC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2939 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2940 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2941 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2942 bool isKill, isUndef;
2943 unsigned SrcReg;
2944 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2945 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2946 SrcReg, isKill, isUndef, ImplicitOp))
2947 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2948
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2949 MachineInstrBuilder MIB =
2950 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2951 .addOperand(Dest)
2952 .addReg(SrcReg,
2953 getKillRegState(isKill) | getUndefRegState(isUndef));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2954 if (ImplicitOp.getReg() != 0)
2955 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2956
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2957 NewMI = addOffset(MIB, 1);
2958 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2959 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2960 case X86::INC16r:
2961 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2962 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2963 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2964 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
2965 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2966 .addOperand(Dest)
2967 .addOperand(Src),
2968 1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2969 break;
2970 case X86::DEC64r:
2971 case X86::DEC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2972 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2973 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2974 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2975
2976 bool isKill, isUndef;
2977 unsigned SrcReg;
2978 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2979 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2980 SrcReg, isKill, isUndef, ImplicitOp))
2981 return nullptr;
2982
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2983 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2984 .addOperand(Dest)
2985 .addReg(SrcReg, getUndefRegState(isUndef) |
2986 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2987 if (ImplicitOp.getReg() != 0)
2988 MIB.addOperand(ImplicitOp);
2989
2990 NewMI = addOffset(MIB, -1);
2991
2992 break;
2993 }
2994 case X86::DEC16r:
2995 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2996 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2997 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2998 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
2999 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3000 .addOperand(Dest)
3001 .addOperand(Src),
3002 -1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3003 break;
3004 case X86::ADD64rr:
3005 case X86::ADD64rr_DB:
3006 case X86::ADD32rr:
3007 case X86::ADD32rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3008 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3009 unsigned Opc;
3010 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3011 Opc = X86::LEA64r;
3012 else
3013 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3014
3015 bool isKill, isUndef;
3016 unsigned SrcReg;
3017 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3018 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3019 SrcReg, isKill, isUndef, ImplicitOp))
3020 return nullptr;
3021
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3022 const MachineOperand &Src2 = MI.getOperand(2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3023 bool isKill2, isUndef2;
3024 unsigned SrcReg2;
3025 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3026 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
3027 SrcReg2, isKill2, isUndef2, ImplicitOp2))
3028 return nullptr;
3029
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3030 MachineInstrBuilder MIB =
3031 BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3032 if (ImplicitOp.getReg() != 0)
3033 MIB.addOperand(ImplicitOp);
3034 if (ImplicitOp2.getReg() != 0)
3035 MIB.addOperand(ImplicitOp2);
3036
3037 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3038
3039 // Preserve undefness of the operands.
3040 NewMI->getOperand(1).setIsUndef(isUndef);
3041 NewMI->getOperand(3).setIsUndef(isUndef2);
3042
3043 if (LV && Src2.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3044 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3045 break;
3046 }
3047 case X86::ADD16rr:
3048 case X86::ADD16rr_DB: {
3049 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3050 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3051 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3052 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3053 unsigned Src2 = MI.getOperand(2).getReg();
3054 bool isKill2 = MI.getOperand(2).isKill();
3055 NewMI = addRegReg(
3056 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3057 Src.getReg(), Src.isKill(), Src2, isKill2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3058
3059 // Preserve undefness of the operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3060 bool isUndef = MI.getOperand(1).isUndef();
3061 bool isUndef2 = MI.getOperand(2).isUndef();
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3062 NewMI->getOperand(1).setIsUndef(isUndef);
3063 NewMI->getOperand(3).setIsUndef(isUndef2);
3064
3065 if (LV && isKill2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3066 LV->replaceKillInstruction(Src2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3067 break;
3068 }
3069 case X86::ADD64ri32:
3070 case X86::ADD64ri8:
3071 case X86::ADD64ri32_DB:
3072 case X86::ADD64ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3073 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3074 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3075 .addOperand(Dest)
3076 .addOperand(Src),
3077 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3078 break;
3079 case X86::ADD32ri:
3080 case X86::ADD32ri8:
3081 case X86::ADD32ri_DB:
3082 case X86::ADD32ri8_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3083 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3084 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3085
3086 bool isKill, isUndef;
3087 unsigned SrcReg;
3088 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3089 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3090 SrcReg, isKill, isUndef, ImplicitOp))
3091 return nullptr;
3092
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3093 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3094 .addOperand(Dest)
3095 .addReg(SrcReg, getUndefRegState(isUndef) |
3096 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3097 if (ImplicitOp.getReg() != 0)
3098 MIB.addOperand(ImplicitOp);
3099
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3100 NewMI = addOffset(MIB, MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3101 break;
3102 }
3103 case X86::ADD16ri:
3104 case X86::ADD16ri8:
3105 case X86::ADD16ri_DB:
3106 case X86::ADD16ri8_DB:
3107 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3108 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3109 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3110 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3111 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3112 .addOperand(Dest)
3113 .addOperand(Src),
3114 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3115 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3116 }
3117
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3118 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]3119
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3120 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3121 if (Src.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3122 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3123 if (Dest.isDead())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3124 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3125 }
3126
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3127 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]3128 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3129}
3130
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3131/// Returns true if the given instruction opcode is FMA3.
3132/// Otherwise, returns false.
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3133/// The second parameter is optional and is used as the second return from
3134/// the function. It is set to true if the given instruction has FMA3 opcode
3135/// that is used for lowering of scalar FMA intrinsics, and it is set to false
3136/// otherwise.
3137static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3138 if (IsIntrinsic)
3139 *IsIntrinsic = false;
3140
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3141 switch (Opcode) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3142 case X86::VFMADDSDr132r: case X86::VFMADDSDr132m:
3143 case X86::VFMADDSSr132r: case X86::VFMADDSSr132m:
3144 case X86::VFMSUBSDr132r: case X86::VFMSUBSDr132m:
3145 case X86::VFMSUBSSr132r: case X86::VFMSUBSSr132m:
3146 case X86::VFNMADDSDr132r: case X86::VFNMADDSDr132m:
3147 case X86::VFNMADDSSr132r: case X86::VFNMADDSSr132m:
3148 case X86::VFNMSUBSDr132r: case X86::VFNMSUBSDr132m:
3149 case X86::VFNMSUBSSr132r: case X86::VFNMSUBSSr132m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3150
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3151 case X86::VFMADDSDr213r: case X86::VFMADDSDr213m:
3152 case X86::VFMADDSSr213r: case X86::VFMADDSSr213m:
3153 case X86::VFMSUBSDr213r: case X86::VFMSUBSDr213m:
3154 case X86::VFMSUBSSr213r: case X86::VFMSUBSSr213m:
3155 case X86::VFNMADDSDr213r: case X86::VFNMADDSDr213m:
3156 case X86::VFNMADDSSr213r: case X86::VFNMADDSSr213m:
3157 case X86::VFNMSUBSDr213r: case X86::VFNMSUBSDr213m:
3158 case X86::VFNMSUBSSr213r: case X86::VFNMSUBSSr213m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3159
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3160 case X86::VFMADDSDr231r: case X86::VFMADDSDr231m:
3161 case X86::VFMADDSSr231r: case X86::VFMADDSSr231m:
3162 case X86::VFMSUBSDr231r: case X86::VFMSUBSDr231m:
3163 case X86::VFMSUBSSr231r: case X86::VFMSUBSSr231m:
3164 case X86::VFNMADDSDr231r: case X86::VFNMADDSDr231m:
3165 case X86::VFNMADDSSr231r: case X86::VFNMADDSSr231m:
3166 case X86::VFNMSUBSDr231r: case X86::VFNMSUBSDr231m:
3167 case X86::VFNMSUBSSr231r: case X86::VFNMSUBSSr231m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3168
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3169 case X86::VFMADDSUBPDr132r: case X86::VFMADDSUBPDr132m:
3170 case X86::VFMADDSUBPSr132r: case X86::VFMADDSUBPSr132m:
3171 case X86::VFMSUBADDPDr132r: case X86::VFMSUBADDPDr132m:
3172 case X86::VFMSUBADDPSr132r: case X86::VFMSUBADDPSr132m:
3173 case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY:
3174 case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY:
3175 case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY:
3176 case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3177
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3178 case X86::VFMADDPDr132r: case X86::VFMADDPDr132m:
3179 case X86::VFMADDPSr132r: case X86::VFMADDPSr132m:
3180 case X86::VFMSUBPDr132r: case X86::VFMSUBPDr132m:
3181 case X86::VFMSUBPSr132r: case X86::VFMSUBPSr132m:
3182 case X86::VFNMADDPDr132r: case X86::VFNMADDPDr132m:
3183 case X86::VFNMADDPSr132r: case X86::VFNMADDPSr132m:
3184 case X86::VFNMSUBPDr132r: case X86::VFNMSUBPDr132m:
3185 case X86::VFNMSUBPSr132r: case X86::VFNMSUBPSr132m:
3186 case X86::VFMADDPDr132rY: case X86::VFMADDPDr132mY:
3187 case X86::VFMADDPSr132rY: case X86::VFMADDPSr132mY:
3188 case X86::VFMSUBPDr132rY: case X86::VFMSUBPDr132mY:
3189 case X86::VFMSUBPSr132rY: case X86::VFMSUBPSr132mY:
3190 case X86::VFNMADDPDr132rY: case X86::VFNMADDPDr132mY:
3191 case X86::VFNMADDPSr132rY: case X86::VFNMADDPSr132mY:
3192 case X86::VFNMSUBPDr132rY: case X86::VFNMSUBPDr132mY:
3193 case X86::VFNMSUBPSr132rY: case X86::VFNMSUBPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3194
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3195 case X86::VFMADDSUBPDr213r: case X86::VFMADDSUBPDr213m:
3196 case X86::VFMADDSUBPSr213r: case X86::VFMADDSUBPSr213m:
3197 case X86::VFMSUBADDPDr213r: case X86::VFMSUBADDPDr213m:
3198 case X86::VFMSUBADDPSr213r: case X86::VFMSUBADDPSr213m:
3199 case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY:
3200 case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY:
3201 case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY:
3202 case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3203
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3204 case X86::VFMADDPDr213r: case X86::VFMADDPDr213m:
3205 case X86::VFMADDPSr213r: case X86::VFMADDPSr213m:
3206 case X86::VFMSUBPDr213r: case X86::VFMSUBPDr213m:
3207 case X86::VFMSUBPSr213r: case X86::VFMSUBPSr213m:
3208 case X86::VFNMADDPDr213r: case X86::VFNMADDPDr213m:
3209 case X86::VFNMADDPSr213r: case X86::VFNMADDPSr213m:
3210 case X86::VFNMSUBPDr213r: case X86::VFNMSUBPDr213m:
3211 case X86::VFNMSUBPSr213r: case X86::VFNMSUBPSr213m:
3212 case X86::VFMADDPDr213rY: case X86::VFMADDPDr213mY:
3213 case X86::VFMADDPSr213rY: case X86::VFMADDPSr213mY:
3214 case X86::VFMSUBPDr213rY: case X86::VFMSUBPDr213mY:
3215 case X86::VFMSUBPSr213rY: case X86::VFMSUBPSr213mY:
3216 case X86::VFNMADDPDr213rY: case X86::VFNMADDPDr213mY:
3217 case X86::VFNMADDPSr213rY: case X86::VFNMADDPSr213mY:
3218 case X86::VFNMSUBPDr213rY: case X86::VFNMSUBPDr213mY:
3219 case X86::VFNMSUBPSr213rY: case X86::VFNMSUBPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3220
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3221 case X86::VFMADDSUBPDr231r: case X86::VFMADDSUBPDr231m:
3222 case X86::VFMADDSUBPSr231r: case X86::VFMADDSUBPSr231m:
3223 case X86::VFMSUBADDPDr231r: case X86::VFMSUBADDPDr231m:
3224 case X86::VFMSUBADDPSr231r: case X86::VFMSUBADDPSr231m:
3225 case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY:
3226 case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY:
3227 case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY:
3228 case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3229
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3230 case X86::VFMADDPDr231r: case X86::VFMADDPDr231m:
3231 case X86::VFMADDPSr231r: case X86::VFMADDPSr231m:
3232 case X86::VFMSUBPDr231r: case X86::VFMSUBPDr231m:
3233 case X86::VFMSUBPSr231r: case X86::VFMSUBPSr231m:
3234 case X86::VFNMADDPDr231r: case X86::VFNMADDPDr231m:
3235 case X86::VFNMADDPSr231r: case X86::VFNMADDPSr231m:
3236 case X86::VFNMSUBPDr231r: case X86::VFNMSUBPDr231m:
3237 case X86::VFNMSUBPSr231r: case X86::VFNMSUBPSr231m:
3238 case X86::VFMADDPDr231rY: case X86::VFMADDPDr231mY:
3239 case X86::VFMADDPSr231rY: case X86::VFMADDPSr231mY:
3240 case X86::VFMSUBPDr231rY: case X86::VFMSUBPDr231mY:
3241 case X86::VFMSUBPSr231rY: case X86::VFMSUBPSr231mY:
3242 case X86::VFNMADDPDr231rY: case X86::VFNMADDPDr231mY:
3243 case X86::VFNMADDPSr231rY: case X86::VFNMADDPSr231mY:
3244 case X86::VFNMSUBPDr231rY: case X86::VFNMSUBPDr231mY:
3245 case X86::VFNMSUBPSr231rY: case X86::VFNMSUBPSr231mY:
3246 return true;
3247
3248 case X86::VFMADDSDr132r_Int: case X86::VFMADDSDr132m_Int:
3249 case X86::VFMADDSSr132r_Int: case X86::VFMADDSSr132m_Int:
3250 case X86::VFMSUBSDr132r_Int: case X86::VFMSUBSDr132m_Int:
3251 case X86::VFMSUBSSr132r_Int: case X86::VFMSUBSSr132m_Int:
3252 case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3253 case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3254 case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3255 case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3256
3257 case X86::VFMADDSDr213r_Int: case X86::VFMADDSDr213m_Int:
3258 case X86::VFMADDSSr213r_Int: case X86::VFMADDSSr213m_Int:
3259 case X86::VFMSUBSDr213r_Int: case X86::VFMSUBSDr213m_Int:
3260 case X86::VFMSUBSSr213r_Int: case X86::VFMSUBSSr213m_Int:
3261 case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3262 case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3263 case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3264 case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3265
3266 case X86::VFMADDSDr231r_Int: case X86::VFMADDSDr231m_Int:
3267 case X86::VFMADDSSr231r_Int: case X86::VFMADDSSr231m_Int:
3268 case X86::VFMSUBSDr231r_Int: case X86::VFMSUBSDr231m_Int:
3269 case X86::VFMSUBSSr231r_Int: case X86::VFMSUBSSr231m_Int:
3270 case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3271 case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3272 case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3273 case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3274 if (IsIntrinsic)
3275 *IsIntrinsic = true;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3276 return true;
3277 default:
3278 return false;
3279 }
3280 llvm_unreachable("Opcode not handled by the switch");
3281}
3282
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3283MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3284 unsigned OpIdx1,
3285 unsigned OpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3286 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3287 if (NewMI)
3288 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3289 return MI;
3290 };
3291
3292 switch (MI.getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3293 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3294 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3295 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3296 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3297 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3298 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3299 unsigned Opc;
3300 unsigned Size;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3301 switch (MI.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3302 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3303 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3304 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3305 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3306 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3307 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3308 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3309 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3310 unsigned Amt = MI.getOperand(3).getImm();
3311 auto &WorkingMI = cloneIfNew(MI);
3312 WorkingMI.setDesc(get(Opc));
3313 WorkingMI.getOperand(3).setImm(Size - Amt);
3314 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3315 OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3316 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3317 case X86::BLENDPDrri:
3318 case X86::BLENDPSrri:
3319 case X86::PBLENDWrri:
3320 case X86::VBLENDPDrri:
3321 case X86::VBLENDPSrri:
3322 case X86::VBLENDPDYrri:
3323 case X86::VBLENDPSYrri:
3324 case X86::VPBLENDDrri:
3325 case X86::VPBLENDWrri:
3326 case X86::VPBLENDDYrri:
3327 case X86::VPBLENDWYrri:{
3328 unsigned Mask;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3329 switch (MI.getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3330 default: llvm_unreachable("Unreachable!");
3331 case X86::BLENDPDrri: Mask = 0x03; break;
3332 case X86::BLENDPSrri: Mask = 0x0F; break;
3333 case X86::PBLENDWrri: Mask = 0xFF; break;
3334 case X86::VBLENDPDrri: Mask = 0x03; break;
3335 case X86::VBLENDPSrri: Mask = 0x0F; break;
3336 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3337 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3338 case X86::VPBLENDDrri: Mask = 0x0F; break;
3339 case X86::VPBLENDWrri: Mask = 0xFF; break;
3340 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3341 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3342 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3343 // Only the least significant bits of Imm are used.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3344 unsigned Imm = MI.getOperand(3).getImm() & Mask;
3345 auto &WorkingMI = cloneIfNew(MI);
3346 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3347 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3348 OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3349 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3350 case X86::PCLMULQDQrr:
3351 case X86::VPCLMULQDQrr:{
3352 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3353 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3354 unsigned Imm = MI.getOperand(3).getImm();
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3355 unsigned Src1Hi = Imm & 0x01;
3356 unsigned Src2Hi = Imm & 0x10;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3357 auto &WorkingMI = cloneIfNew(MI);
3358 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3359 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3360 OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3361 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3362 case X86::CMPPDrri:
3363 case X86::CMPPSrri:
3364 case X86::VCMPPDrri:
3365 case X86::VCMPPSrri:
3366 case X86::VCMPPDYrri:
3367 case X86::VCMPPSYrri: {
3368 // Float comparison can be safely commuted for
3369 // Ordered/Unordered/Equal/NotEqual tests
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3370 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3371 switch (Imm) {
3372 case 0x00: // EQUAL
3373 case 0x03: // UNORDERED
3374 case 0x04: // NOT EQUAL
3375 case 0x07: // ORDERED
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3376 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3377 default:
3378 return nullptr;
3379 }
3380 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3381 case X86::VPCOMBri: case X86::VPCOMUBri:
3382 case X86::VPCOMDri: case X86::VPCOMUDri:
3383 case X86::VPCOMQri: case X86::VPCOMUQri:
3384 case X86::VPCOMWri: case X86::VPCOMUWri: {
3385 // Flip comparison mode immediate (if necessary).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3386 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3387 switch (Imm) {
3388 case 0x00: Imm = 0x02; break; // LT -> GT
3389 case 0x01: Imm = 0x03; break; // LE -> GE
3390 case 0x02: Imm = 0x00; break; // GT -> LT
3391 case 0x03: Imm = 0x01; break; // GE -> LE
3392 case 0x04: // EQ
3393 case 0x05: // NE
3394 case 0x06: // FALSE
3395 case 0x07: // TRUE
3396 default:
3397 break;
3398 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3399 auto &WorkingMI = cloneIfNew(MI);
3400 WorkingMI.getOperand(3).setImm(Imm);
3401 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3402 OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3403 }
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3404 case X86::VPERM2F128rr:
3405 case X86::VPERM2I128rr: {
3406 // Flip permute source immediate.
3407 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3408 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3409 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3410 auto &WorkingMI = cloneIfNew(MI);
3411 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3412 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3413 OpIdx1, OpIdx2);
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3414 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3415 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3416 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3417 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3418 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3419 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3420 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3421 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3422 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3423 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3424 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3425 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3426 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3427 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3428 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3429 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3430 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3431 unsigned Opc;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3432 switch (MI.getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3433 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3434 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3435 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3436 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3437 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3438 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3439 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3440 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3441 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3442 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3443 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3444 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3445 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3446 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3447 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3448 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3449 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3450 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3451 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3452 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3453 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3454 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3455 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3456 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3457 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3458 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3459 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3460 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3461 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3462 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3463 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3464 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3465 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3466 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3467 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3468 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3469 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3470 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3471 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3472 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3473 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3474 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3475 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3476 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3477 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3478 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3479 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3480 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3481 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3482 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3483 auto &WorkingMI = cloneIfNew(MI);
3484 WorkingMI.setDesc(get(Opc));
3485 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3486 OpIdx1, OpIdx2);
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3487 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3488 default:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3489 if (isFMA3(MI.getOpcode())) {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3490 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3491 if (Opc == 0)
3492 return nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3493 auto &WorkingMI = cloneIfNew(MI);
3494 WorkingMI.setDesc(get(Opc));
3495 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3496 OpIdx1, OpIdx2);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3497 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3498
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3499 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3500 }
3501}
3502
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3503bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3504 unsigned &SrcOpIdx1,
3505 unsigned &SrcOpIdx2) const {
3506
3507 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3508
3509 // Only the first RegOpsNum operands are commutable.
3510 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3511 // that the operand is not specified/fixed.
3512 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3513 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3514 return false;
3515 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3516 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3517 return false;
3518
3519 // Look for two different register operands assumed to be commutable
3520 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3521 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3522 SrcOpIdx2 == CommuteAnyOperandIndex) {
3523 unsigned CommutableOpIdx1 = SrcOpIdx1;
3524 unsigned CommutableOpIdx2 = SrcOpIdx2;
3525
3526 // At least one of operands to be commuted is not specified and
3527 // this method is free to choose appropriate commutable operands.
3528 if (SrcOpIdx1 == SrcOpIdx2)
3529 // Both of operands are not fixed. By default set one of commutable
3530 // operands to the last register operand of the instruction.
3531 CommutableOpIdx2 = RegOpsNum;
3532 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3533 // Only one of operands is not fixed.
3534 CommutableOpIdx2 = SrcOpIdx1;
3535
3536 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3537 // operand and assign its index to CommutableOpIdx1.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3538 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3539 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3540 // The commuted operands must have different registers.
3541 // Otherwise, the commute transformation does not change anything and
3542 // is useless then.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3543 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3544 break;
3545 }
3546
3547 // No appropriate commutable operands were found.
3548 if (CommutableOpIdx1 == 0)
3549 return false;
3550
3551 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3552 // to return those values.
3553 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3554 CommutableOpIdx1, CommutableOpIdx2))
3555 return false;
3556 }
3557
3558 // Check if we can adjust the opcode to preserve the semantics when
3559 // commute the register operands.
3560 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3561}
3562
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3563unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3564 MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) const {
3565 unsigned Opc = MI.getOpcode();
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3566
3567 // Define the array that holds FMA opcodes in groups
3568 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3569 static const uint16_t RegularOpcodeGroups[][3] = {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3570 { X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
3571 { X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
3572 { X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
3573 { X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
3574 { X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
3575 { X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
3576 { X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
3577 { X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
3578 { X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
3579 { X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
3580 { X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
3581 { X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
3582
3583 { X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
3584 { X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
3585 { X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
3586 { X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
3587 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
3588 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
3589 { X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
3590 { X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
3591 { X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
3592 { X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
3593 { X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
3594 { X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
Vyacheslav Klochkov1ff9cbd2015-11-12 20:11:57 +0000[diff] [blame]3595
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3596 { X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
3597 { X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
3598 { X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
3599 { X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
3600 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3601 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3602 { X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
3603 { X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
3604 { X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
3605 { X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
3606 { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3607 { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3608
3609 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
3610 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
3611 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
3612 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
3613 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3614 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3615 { X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
3616 { X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
3617 { X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
3618 { X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
3619 { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3620 { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3621
3622 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
3623 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
3624 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3625 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3626 { X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
3627 { X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
3628 { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3629 { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3630
3631 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
3632 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
3633 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3634 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3635 { X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
3636 { X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
3637 { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3638 { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3639 };
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3640
3641 // Define the array that holds FMA*_Int opcodes in groups
3642 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3643 static const uint16_t IntrinOpcodeGroups[][3] = {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3644 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
3645 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
3646 { X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
3647 { X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
3648
3649 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
3650 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
3651 { X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
3652 { X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
3653
3654 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3655 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3656 { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3657 { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3658
3659 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3660 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3661 { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3662 { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3663 };
3664
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3665 const unsigned Form132Index = 0;
3666 const unsigned Form213Index = 1;
3667 const unsigned Form231Index = 2;
3668 const unsigned FormsNum = 3;
3669
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3670 bool IsIntrinOpcode;
3671 isFMA3(Opc, &IsIntrinOpcode);
3672
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3673 size_t GroupsNum;
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3674 const uint16_t (*OpcodeGroups)[3];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3675 if (IsIntrinOpcode) {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3676 GroupsNum = array_lengthof(IntrinOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3677 OpcodeGroups = IntrinOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3678 } else {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3679 GroupsNum = array_lengthof(RegularOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3680 OpcodeGroups = RegularOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3681 }
3682
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3683 const uint16_t *FoundOpcodesGroup = nullptr;
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3684 size_t FormIndex;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3685
3686 // Look for the input opcode in the corresponding opcodes table.
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3687 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3688 ++GroupIndex) {
3689 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3690 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3691 FoundOpcodesGroup = OpcodeGroups[GroupIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3692 break;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3693 }
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3694 }
3695 }
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3696
3697 // The input opcode does not match with any of the opcodes from the tables.
3698 // The unsupported FMA opcode must be added to one of the two opcode groups
3699 // defined above.
3700 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3701
3702 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3703 if (SrcOpIdx1 > SrcOpIdx2)
3704 std::swap(SrcOpIdx1, SrcOpIdx2);
3705
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3706 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3707 // analysis. The commute optimization is legal only if all users of FMA*_Int
3708 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3709 // not implemented yet. So, just return 0 in that case.
3710 // When such analysis are available this place will be the right place for
3711 // calling it.
3712 if (IsIntrinOpcode && SrcOpIdx1 == 1)
3713 return 0;
3714
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3715 unsigned Case;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3716 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3717 Case = 0;
3718 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3719 Case = 1;
3720 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3721 Case = 2;
3722 else
3723 return 0;
3724
3725 // Define the FMA forms mapping array that helps to map input FMA form
3726 // to output FMA form to preserve the operation semantics after
3727 // commuting the operands.
3728 static const unsigned FormMapping[][3] = {
3729 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3730 // FMA132 A, C, b; ==> FMA231 C, A, b;
3731 // FMA213 B, A, c; ==> FMA213 A, B, c;
3732 // FMA231 C, A, b; ==> FMA132 A, C, b;
3733 { Form231Index, Form213Index, Form132Index },
3734 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3735 // FMA132 A, c, B; ==> FMA132 B, c, A;
3736 // FMA213 B, a, C; ==> FMA231 C, a, B;
3737 // FMA231 C, a, B; ==> FMA213 B, a, C;
3738 { Form132Index, Form231Index, Form213Index },
3739 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3740 // FMA132 a, C, B; ==> FMA213 a, B, C;
3741 // FMA213 b, A, C; ==> FMA132 b, C, A;
3742 // FMA231 c, A, B; ==> FMA231 c, B, A;
3743 { Form213Index, Form132Index, Form231Index }
3744 };
3745
3746 // Everything is ready, just adjust the FMA opcode and return it.
3747 FormIndex = FormMapping[Case][FormIndex];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3748 return FoundOpcodesGroup[FormIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3749}
3750
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3751bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3752 unsigned &SrcOpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3753 switch (MI.getOpcode()) {
3754 case X86::CMPPDrri:
3755 case X86::CMPPSrri:
3756 case X86::VCMPPDrri:
3757 case X86::VCMPPSrri:
3758 case X86::VCMPPDYrri:
3759 case X86::VCMPPSYrri: {
3760 // Float comparison can be safely commuted for
3761 // Ordered/Unordered/Equal/NotEqual tests
3762 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3763 switch (Imm) {
3764 case 0x00: // EQUAL
3765 case 0x03: // UNORDERED
3766 case 0x04: // NOT EQUAL
3767 case 0x07: // ORDERED
3768 // The indices of the commutable operands are 1 and 2.
3769 // Assign them to the returned operand indices here.
3770 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3771 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3772 return false;
3773 }
3774 default:
3775 if (isFMA3(MI.getOpcode()))
3776 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3777 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3778 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3779 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3780}
3781
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3782static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3783 switch (BrOpc) {
3784 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3785 case X86::JE_1: return X86::COND_E;
3786 case X86::JNE_1: return X86::COND_NE;
3787 case X86::JL_1: return X86::COND_L;
3788 case X86::JLE_1: return X86::COND_LE;
3789 case X86::JG_1: return X86::COND_G;
3790 case X86::JGE_1: return X86::COND_GE;
3791 case X86::JB_1: return X86::COND_B;
3792 case X86::JBE_1: return X86::COND_BE;
3793 case X86::JA_1: return X86::COND_A;
3794 case X86::JAE_1: return X86::COND_AE;
3795 case X86::JS_1: return X86::COND_S;
3796 case X86::JNS_1: return X86::COND_NS;
3797 case X86::JP_1: return X86::COND_P;
3798 case X86::JNP_1: return X86::COND_NP;
3799 case X86::JO_1: return X86::COND_O;
3800 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3801 }
3802}
3803
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3804/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3805static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3806 switch (Opc) {
3807 default: return X86::COND_INVALID;
3808 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3809 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3810 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3811 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3812 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3813 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3814 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3815 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3816 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3817 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3818 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3819 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3820 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3821 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3822 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3823 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3824 }
3825}
3826
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3827/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3828X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3829 switch (Opc) {
3830 default: return X86::COND_INVALID;
3831 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3832 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3833 return X86::COND_A;
3834 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3835 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3836 return X86::COND_AE;
3837 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3838 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3839 return X86::COND_B;
3840 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3841 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3842 return X86::COND_BE;
3843 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3844 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3845 return X86::COND_E;
3846 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3847 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3848 return X86::COND_G;
3849 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3850 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3851 return X86::COND_GE;
3852 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3853 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3854 return X86::COND_L;
3855 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3856 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3857 return X86::COND_LE;
3858 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3859 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3860 return X86::COND_NE;
3861 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3862 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3863 return X86::COND_NO;
3864 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3865 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3866 return X86::COND_NP;
3867 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3868 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3869 return X86::COND_NS;
3870 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3871 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3872 return X86::COND_O;
3873 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3874 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3875 return X86::COND_P;
3876 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3877 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3878 return X86::COND_S;
3879 }
3880}
3881
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3882unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3883 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3884 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3885 case X86::COND_E: return X86::JE_1;
3886 case X86::COND_NE: return X86::JNE_1;
3887 case X86::COND_L: return X86::JL_1;
3888 case X86::COND_LE: return X86::JLE_1;
3889 case X86::COND_G: return X86::JG_1;
3890 case X86::COND_GE: return X86::JGE_1;
3891 case X86::COND_B: return X86::JB_1;
3892 case X86::COND_BE: return X86::JBE_1;
3893 case X86::COND_A: return X86::JA_1;
3894 case X86::COND_AE: return X86::JAE_1;
3895 case X86::COND_S: return X86::JS_1;
3896 case X86::COND_NS: return X86::JNS_1;
3897 case X86::COND_P: return X86::JP_1;
3898 case X86::COND_NP: return X86::JNP_1;
3899 case X86::COND_O: return X86::JO_1;
3900 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3901 }
3902}
3903
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3904/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3905/// e.g. turning COND_E to COND_NE.
3906X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3907 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3908 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3909 case X86::COND_E: return X86::COND_NE;
3910 case X86::COND_NE: return X86::COND_E;
3911 case X86::COND_L: return X86::COND_GE;
3912 case X86::COND_LE: return X86::COND_G;
3913 case X86::COND_G: return X86::COND_LE;
3914 case X86::COND_GE: return X86::COND_L;
3915 case X86::COND_B: return X86::COND_AE;
3916 case X86::COND_BE: return X86::COND_A;
3917 case X86::COND_A: return X86::COND_BE;
3918 case X86::COND_AE: return X86::COND_B;
3919 case X86::COND_S: return X86::COND_NS;
3920 case X86::COND_NS: return X86::COND_S;
3921 case X86::COND_P: return X86::COND_NP;
3922 case X86::COND_NP: return X86::COND_P;
3923 case X86::COND_O: return X86::COND_NO;
3924 case X86::COND_NO: return X86::COND_O;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3925 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
3926 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3927 }
3928}
3929
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3930/// Assuming the flags are set by MI(a,b), return the condition code if we
3931/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3932static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3933 switch (CC) {
3934 default: return X86::COND_INVALID;
3935 case X86::COND_E: return X86::COND_E;
3936 case X86::COND_NE: return X86::COND_NE;
3937 case X86::COND_L: return X86::COND_G;
3938 case X86::COND_LE: return X86::COND_GE;
3939 case X86::COND_G: return X86::COND_L;
3940 case X86::COND_GE: return X86::COND_LE;
3941 case X86::COND_B: return X86::COND_A;
3942 case X86::COND_BE: return X86::COND_AE;
3943 case X86::COND_A: return X86::COND_B;
3944 case X86::COND_AE: return X86::COND_BE;
3945 }
3946}
3947
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3948/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3949/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3950unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3951 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3952 { X86::SETAr, X86::SETAm },
3953 { X86::SETAEr, X86::SETAEm },
3954 { X86::SETBr, X86::SETBm },
3955 { X86::SETBEr, X86::SETBEm },
3956 { X86::SETEr, X86::SETEm },
3957 { X86::SETGr, X86::SETGm },
3958 { X86::SETGEr, X86::SETGEm },
3959 { X86::SETLr, X86::SETLm },
3960 { X86::SETLEr, X86::SETLEm },
3961 { X86::SETNEr, X86::SETNEm },
3962 { X86::SETNOr, X86::SETNOm },
3963 { X86::SETNPr, X86::SETNPm },
3964 { X86::SETNSr, X86::SETNSm },
3965 { X86::SETOr, X86::SETOm },
3966 { X86::SETPr, X86::SETPm },
3967 { X86::SETSr, X86::SETSm }
3968 };
3969
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3970 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3971 return Opc[CC][HasMemoryOperand ? 1 : 0];
3972}
3973
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3974/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3975/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3976unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3977 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3978 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3979 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3980 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3981 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3982 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3983 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3984 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3985 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3986 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3987 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3988 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3989 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3990 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3991 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3992 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3993 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3994 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3995 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3996 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3997 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3998 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3999 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
4000 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
4001 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
4002 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
4003 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
4004 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
4005 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
4006 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
4007 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
4008 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
4009 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
4010 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4011 };
4012
4013 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4014 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4015 switch(RegBytes) {
4016 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4017 case 2: return Opc[Idx][0];
4018 case 4: return Opc[Idx][1];
4019 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4020 }
4021}
4022
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4023bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4024 if (!MI.isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4025
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4026 // Conditional branch is a special case.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4027 if (MI.isBranch() && !MI.isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4028 return true;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4029 if (!MI.isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4030 return true;
4031 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]4032}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4033
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4034// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
4035// not be a fallthrough MBB now due to layout changes). Return nullptr if the
4036// fallthrough MBB cannot be identified.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4037static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
4038 MachineBasicBlock *TBB) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4039 // Look for non-EHPad successors other than TBB. If we find exactly one, it
4040 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
4041 // and fallthrough MBB. If we find more than one, we cannot identify the
4042 // fallthrough MBB and should return nullptr.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4043 MachineBasicBlock *FallthroughBB = nullptr;
4044 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4045 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4046 continue;
4047 // Return a nullptr if we found more than one fallthrough successor.
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4048 if (FallthroughBB && FallthroughBB != TBB)
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4049 return nullptr;
4050 FallthroughBB = *SI;
4051 }
4052 return FallthroughBB;
4053}
4054
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4055bool X86InstrInfo::AnalyzeBranchImpl(
4056 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
4057 SmallVectorImpl<MachineOperand> &Cond,
4058 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
4059
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4060 // Start from the bottom of the block and work up, examining the
4061 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4062 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4063 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4064 while (I != MBB.begin()) {
4065 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4066 if (I->isDebugValue())
4067 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4068
4069 // Working from the bottom, when we see a non-terminator instruction, we're
4070 // done.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4071 if (!isUnpredicatedTerminator(*I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4072 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4073
4074 // A terminator that isn't a branch can't easily be handled by this
4075 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]4076 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4077 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4078
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4079 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4080 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4081 UnCondBrIter = I;
4082
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4083 if (!AllowModify) {
4084 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]4085 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4086 }
4087
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4088 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]4089 while (std::next(I) != MBB.end())
4090 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4091
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4092 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4093 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4094
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4095 // Delete the JMP if it's equivalent to a fall-through.
4096 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4097 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4098 I->eraseFromParent();
4099 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4100 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4101 continue;
4102 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4103
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4104 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4105 TBB = I->getOperand(0).getMBB();
4106 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4107 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4108
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4109 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4110 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4111 if (BranchCode == X86::COND_INVALID)
4112 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4113
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4114 // Working from the bottom, handle the first conditional branch.
4115 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4116 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4117 if (AllowModify && UnCondBrIter != MBB.end() &&
4118 MBB.isLayoutSuccessor(TargetBB)) {
4119 // If we can modify the code and it ends in something like:
4120 //
4121 // jCC L1
4122 // jmp L2
4123 // L1:
4124 // ...
4125 // L2:
4126 //
4127 // Then we can change this to:
4128 //
4129 // jnCC L2
4130 // L1:
4131 // ...
4132 // L2:
4133 //
4134 // Which is a bit more efficient.
4135 // We conditionally jump to the fall-through block.
4136 BranchCode = GetOppositeBranchCondition(BranchCode);
4137 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4138 MachineBasicBlock::iterator OldInst = I;
4139
4140 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4141 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4142 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4143 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4144
4145 OldInst->eraseFromParent();
4146 UnCondBrIter->eraseFromParent();
4147
4148 // Restart the analysis.
4149 UnCondBrIter = MBB.end();
4150 I = MBB.end();
4151 continue;
4152 }
4153
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4154 FBB = TBB;
4155 TBB = I->getOperand(0).getMBB();
4156 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4157 CondBranches.push_back(&*I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4158 continue;
4159 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4160
4161 // Handle subsequent conditional branches. Only handle the case where all
4162 // conditional branches branch to the same destination and their condition
4163 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4164 assert(Cond.size() == 1);
4165 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4166
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4167 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4168 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4169 auto NewTBB = I->getOperand(0).getMBB();
4170 if (OldBranchCode == BranchCode && TBB == NewTBB)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4171 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4172
4173 // If they differ, see if they fit one of the known patterns. Theoretically,
4174 // we could handle more patterns here, but we shouldn't expect to see them
4175 // if instruction selection has done a reasonable job.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4176 if (TBB == NewTBB &&
4177 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4178 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4179 BranchCode = X86::COND_NE_OR_P;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4180 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4181 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4182 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4183 return true;
4184
4185 // X86::COND_E_AND_NP usually has two different branch destinations.
4186 //
4187 // JP B1
4188 // JE B2
4189 // JMP B1
4190 // B1:
4191 // B2:
4192 //
4193 // Here this condition branches to B2 only if NP && E. It has another
4194 // equivalent form:
4195 //
4196 // JNE B1
4197 // JNP B2
4198 // JMP B1
4199 // B1:
4200 // B2:
4201 //
4202 // Similarly it branches to B2 only if E && NP. That is why this condition
4203 // is named with COND_E_AND_NP.
4204 BranchCode = X86::COND_E_AND_NP;
4205 } else
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4206 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4207
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4208 // Update the MachineOperand.
4209 Cond[0].setImm(BranchCode);
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4210 CondBranches.push_back(&*I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4211 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4212
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4213 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4214}
4215
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4216bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4217 MachineBasicBlock *&TBB,
4218 MachineBasicBlock *&FBB,
4219 SmallVectorImpl<MachineOperand> &Cond,
4220 bool AllowModify) const {
4221 SmallVector<MachineInstr *, 4> CondBranches;
4222 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4223}
4224
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4225bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4226 MachineBranchPredicate &MBP,
4227 bool AllowModify) const {
4228 using namespace std::placeholders;
4229
4230 SmallVector<MachineOperand, 4> Cond;
4231 SmallVector<MachineInstr *, 4> CondBranches;
4232 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4233 AllowModify))
4234 return true;
4235
4236 if (Cond.size() != 1)
4237 return true;
4238
4239 assert(MBP.TrueDest && "expected!");
4240
4241 if (!MBP.FalseDest)
4242 MBP.FalseDest = MBB.getNextNode();
4243
4244 const TargetRegisterInfo *TRI = &getRegisterInfo();
4245
4246 MachineInstr *ConditionDef = nullptr;
4247 bool SingleUseCondition = true;
4248
4249 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4250 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4251 ConditionDef = &*I;
4252 break;
4253 }
4254
4255 if (I->readsRegister(X86::EFLAGS, TRI))
4256 SingleUseCondition = false;
4257 }
4258
4259 if (!ConditionDef)
4260 return true;
4261
4262 if (SingleUseCondition) {
4263 for (auto *Succ : MBB.successors())
4264 if (Succ->isLiveIn(X86::EFLAGS))
4265 SingleUseCondition = false;
4266 }
4267
4268 MBP.ConditionDef = ConditionDef;
4269 MBP.SingleUseCondition = SingleUseCondition;
4270
4271 // Currently we only recognize the simple pattern:
4272 //
4273 // test %reg, %reg
4274 // je %label
4275 //
4276 const unsigned TestOpcode =
4277 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4278
4279 if (ConditionDef->getOpcode() == TestOpcode &&
4280 ConditionDef->getNumOperands() == 3 &&
4281 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4282 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4283 MBP.LHS = ConditionDef->getOperand(0);
4284 MBP.RHS = MachineOperand::CreateImm(0);
4285 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4286 ? MachineBranchPredicate::PRED_NE
4287 : MachineBranchPredicate::PRED_EQ;
4288 return false;
4289 }
4290
4291 return true;
4292}
4293
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4294unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4295 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4296 unsigned Count = 0;
4297
4298 while (I != MBB.begin()) {
4299 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4300 if (I->isDebugValue())
4301 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4302 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4303 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4304 break;
4305 // Remove the branch.
4306 I->eraseFromParent();
4307 I = MBB.end();
4308 ++Count;
4309 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4310
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4311 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4312}
4313
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4314unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4315 MachineBasicBlock *TBB,
4316 MachineBasicBlock *FBB,
4317 ArrayRef<MachineOperand> Cond,
4318 const DebugLoc &DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4319 // Shouldn't be a fall through.
4320 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4321 assert((Cond.size() == 1 || Cond.size() == 0) &&
4322 "X86 branch conditions have one component!");
4323
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4324 if (Cond.empty()) {
4325 // Unconditional branch?
4326 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4327 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4328 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4329 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4330
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4331 // If FBB is null, it is implied to be a fall-through block.
4332 bool FallThru = FBB == nullptr;
4333
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4334 // Conditional branch.
4335 unsigned Count = 0;
4336 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4337 switch (CC) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4338 case X86::COND_NE_OR_P:
4339 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4340 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4341 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4342 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4343 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4344 break;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4345 case X86::COND_E_AND_NP:
4346 // Use the next block of MBB as FBB if it is null.
4347 if (FBB == nullptr) {
4348 FBB = getFallThroughMBB(&MBB, TBB);
4349 assert(FBB && "MBB cannot be the last block in function when the false "
4350 "body is a fall-through.");
4351 }
4352 // Synthesize COND_E_AND_NP with two branches.
4353 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4354 ++Count;
4355 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4356 ++Count;
4357 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4358 default: {
4359 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4360 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4361 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4362 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4363 }
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4364 if (!FallThru) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4365 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4366 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4367 ++Count;
4368 }
4369 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4370}
4371
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4372bool X86InstrInfo::
4373canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4374 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4375 unsigned TrueReg, unsigned FalseReg,
4376 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4377 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4378 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4379 return false;
4380 if (Cond.size() != 1)
4381 return false;
4382 // We cannot do the composite conditions, at least not in SSA form.
4383 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4384 return false;
4385
4386 // Check register classes.
4387 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4388 const TargetRegisterClass *RC =
4389 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4390 if (!RC)
4391 return false;
4392
4393 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4394 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4395 X86::GR32RegClass.hasSubClassEq(RC) ||
4396 X86::GR64RegClass.hasSubClassEq(RC)) {
4397 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4398 // Bridge. Probably Ivy Bridge as well.
4399 CondCycles = 2;
4400 TrueCycles = 2;
4401 FalseCycles = 2;
4402 return true;
4403 }
4404
4405 // Can't do vectors.
4406 return false;
4407}
4408
4409void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4410 MachineBasicBlock::iterator I,
4411 const DebugLoc &DL, unsigned DstReg,
4412 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4413 unsigned FalseReg) const {
4414 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4415 assert(Cond.size() == 1 && "Invalid Cond array");
4416 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4417 MRI.getRegClass(DstReg)->getSize(),
4418 false /*HasMemoryOperand*/);
4419 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4420}
4421
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4422/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4423static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4424 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4425}
4426
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4427// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4428static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4429 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4430
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4431 // SrcReg(VR128) -> DestReg(GR64)
4432 // SrcReg(VR64) -> DestReg(GR64)
4433 // SrcReg(GR64) -> DestReg(VR128)
4434 // SrcReg(GR64) -> DestReg(VR64)
4435
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4436 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4437 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4438 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4439 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4440 // Copy from a VR128 register to a GR64 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4441 return HasAVX512 ? X86::VMOVPQIto64Zrr :
4442 HasAVX ? X86::VMOVPQIto64rr :
4443 X86::MOVPQIto64rr;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4444 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4445 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4446 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4447 } else if (X86::GR64RegClass.contains(SrcReg)) {
4448 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4449 if (X86::VR128XRegClass.contains(DestReg))
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4450 return HasAVX512 ? X86::VMOV64toPQIZrr :
4451 HasAVX ? X86::VMOV64toPQIrr :
4452 X86::MOV64toPQIrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4453 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4454 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4455 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4456 }
4457
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4458 // SrcReg(FR32) -> DestReg(GR32)
4459 // SrcReg(GR32) -> DestReg(FR32)
4460
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4461 if (X86::GR32RegClass.contains(DestReg) &&
4462 X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4463 // Copy from a FR32 register to a GR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4464 return HasAVX512 ? X86::VMOVSS2DIZrr :
4465 HasAVX ? X86::VMOVSS2DIrr :
4466 X86::MOVSS2DIrr;
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4467
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4468 if (X86::FR32XRegClass.contains(DestReg) &&
4469 X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4470 // Copy from a GR32 register to a FR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4471 return HasAVX512 ? X86::VMOVDI2SSZrr :
4472 HasAVX ? X86::VMOVDI2SSrr :
4473 X86::MOVDI2SSrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4474 return 0;
4475}
4476
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4477static bool isMaskRegClass(const TargetRegisterClass *RC) {
4478 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4479 return X86::VK16RegClass.hasSubClassEq(RC);
4480}
4481
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4482static bool MaskRegClassContains(unsigned Reg) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4483 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4484 return X86::VK16RegClass.contains(Reg);
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4485}
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4486
4487static bool GRRegClassContains(unsigned Reg) {
4488 return X86::GR64RegClass.contains(Reg) ||
4489 X86::GR32RegClass.contains(Reg) ||
4490 X86::GR16RegClass.contains(Reg) ||
4491 X86::GR8RegClass.contains(Reg);
4492}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4493static
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4494unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4495 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4496 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4497 return X86::KMOVBrk;
4498 }
4499 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4500 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4501 return X86::KMOVBkr;
4502 }
4503 return 0;
4504}
4505
4506static
4507unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4508 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4509 return X86::KMOVQkk;
4510 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4511 return X86::KMOVDrk;
4512 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4513 return X86::KMOVQrk;
4514 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4515 return X86::KMOVDkr;
4516 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4517 return X86::KMOVQkr;
4518 return 0;
4519}
4520
4521static
4522unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4523 const X86Subtarget &Subtarget)
4524{
4525 if (Subtarget.hasDQI())
4526 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4527 return Opc;
4528 if (Subtarget.hasBWI())
4529 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4530 return Opc;
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4531 if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
4532 if (Subtarget.hasVLX())
4533 return X86::VMOVAPSZ128rr;
4534 DestReg = get512BitSuperRegister(DestReg);
4535 SrcReg = get512BitSuperRegister(SrcReg);
4536 return X86::VMOVAPSZrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4537 }
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4538 if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
4539 if (Subtarget.hasVLX())
4540 return X86::VMOVAPSZ256rr;
4541 DestReg = get512BitSuperRegister(DestReg);
4542 SrcReg = get512BitSuperRegister(SrcReg);
4543 return X86::VMOVAPSZrr;
4544 }
4545 if (X86::VR512RegClass.contains(DestReg, SrcReg))
4546 return X86::VMOVAPSZrr;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4547 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4548 return X86::KMOVWkk;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4549 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4550 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4551 return X86::KMOVWkr;
4552 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4553 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4554 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4555 return X86::KMOVWrk;
4556 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4557 return 0;
4558}
4559
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4560void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4561 MachineBasicBlock::iterator MI,
4562 const DebugLoc &DL, unsigned DestReg,
4563 unsigned SrcReg, bool KillSrc) const {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4564 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4565 bool HasAVX = Subtarget.hasAVX();
4566 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4567 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4568 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4569 Opc = X86::MOV64rr;
4570 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4571 Opc = X86::MOV32rr;
4572 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4573 Opc = X86::MOV16rr;
4574 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4575 // Copying to or from a physical H register on x86-64 requires a NOREX
4576 // move. Otherwise use a normal move.
4577 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4578 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4579 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4580 // Both operands must be encodable without an REX prefix.
4581 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4582 "8-bit H register can not be copied outside GR8_NOREX");
4583 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4584 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4585 }
4586 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4587 Opc = X86::MMX_MOVQ64rr;
4588 else if (HasAVX512)
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4589 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4590 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4591 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4592 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4593 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4594 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4595 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4596
4597 if (Opc) {
4598 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4599 .addReg(SrcReg, getKillRegState(KillSrc));
4600 return;
4601 }
4602
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4603 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4604 bool ToEFLAGS = DestReg == X86::EFLAGS;
4605 int Reg = FromEFLAGS ? DestReg : SrcReg;
4606 bool is32 = X86::GR32RegClass.contains(Reg);
4607 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4608
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4609 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4610 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4611 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4612 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4613 int Pop = is64 ? X86::POP64r : X86::POP32r;
4614 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4615 int AX = is64 ? X86::RAX : X86::EAX;
4616
4617 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4618 assert(Subtarget.is64Bit() &&
4619 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4620 // Moving EFLAGS to / from another register requires a push and a pop.
4621 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemer33467632015-12-27 06:07:26 +0000[diff] [blame]4622 // first frame index. See X86FrameLowering.cpp - usesTheStack.
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4623 if (FromEFLAGS) {
4624 BuildMI(MBB, MI, DL, get(PushF));
4625 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4626 }
4627 if (ToEFLAGS) {
4628 BuildMI(MBB, MI, DL, get(Push))
4629 .addReg(SrcReg, getKillRegState(KillSrc));
4630 BuildMI(MBB, MI, DL, get(PopF));
4631 }
4632 return;
4633 }
4634
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4635 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4636 // inefficient. Instead:
4637 // - Save the overflow flag OF into AL using SETO, and restore it using a
4638 // signed 8-bit addition of AL and INT8_MAX.
4639 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4640 // using LAHF/SAHF.
4641 // - When RAX/EAX is live and isn't the destination register, make sure it
4642 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4643 // the flags.
4644 // This approach is ~2.25x faster than using PUSHF/POPF.
4645 //
4646 // This is still somewhat inefficient because we don't know which flags are
4647 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4648 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4649 //
4650 // PUSHF/POPF is also potentially incorrect because it affects other flags
4651 // such as TF/IF/DF, which LLVM doesn't model.
4652 //
4653 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemerca1c9f02016-01-04 04:49:41 +0000[diff] [blame]4654 // first frame index.
4655 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4656
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4657 const TargetRegisterInfo *TRI = &getRegisterInfo();
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4658 MachineBasicBlock::LivenessQueryResult LQR =
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4659 MBB.computeRegisterLiveness(TRI, AX, MI);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4660 // We do not want to save and restore AX if we do not have to.
4661 // Moreover, if we do so whereas AX is dead, we would need to set
4662 // an undef flag on the use of AX, otherwise the verifier will
4663 // complain that we read an undef value.
4664 // We do not want to change the behavior of the machine verifier
4665 // as this is usually wrong to read an undef value.
4666 if (MachineBasicBlock::LQR_Unknown == LQR) {
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4667 LivePhysRegs LPR(TRI);
Matthias Braund1aabb22016-05-03 00:24:32 +0000[diff] [blame]4668 LPR.addLiveOuts(MBB);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4669 MachineBasicBlock::iterator I = MBB.end();
4670 while (I != MI) {
4671 --I;
4672 LPR.stepBackward(*I);
4673 }
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4674 // AX contains the top most register in the aliasing hierarchy.
4675 // It may not be live, but one of its aliases may be.
4676 for (MCRegAliasIterator AI(AX, TRI, true);
4677 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4678 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4679 : MachineBasicBlock::LQR_Dead;
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4680 }
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4681 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4682 if (!AXDead)
4683 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4684 if (FromEFLAGS) {
4685 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4686 BuildMI(MBB, MI, DL, get(X86::LAHF));
4687 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4688 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4689 if (ToEFLAGS) {
4690 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4691 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4692 .addReg(X86::AL)
4693 .addImm(INT8_MAX);
4694 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4695 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4696 if (!AXDead)
4697 BuildMI(MBB, MI, DL, get(Pop), AX);
4698 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4699 }
4700
4701 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4702 << " to " << RI.getName(DestReg) << '\n');
4703 llvm_unreachable("Cannot emit physreg copy instruction");
4704}
4705
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4706static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4707 bool load) {
4708 switch (RC->getSize()) {
4709 default:
4710 llvm_unreachable("Unknown spill size");
4711 case 2:
4712 return load ? X86::KMOVWkm : X86::KMOVWmk;
4713 case 4:
4714 return load ? X86::KMOVDkm : X86::KMOVDmk;
4715 case 8:
4716 return load ? X86::KMOVQkm : X86::KMOVQmk;
4717 }
4718}
4719
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4720static unsigned getLoadStoreRegOpcode(unsigned Reg,
4721 const TargetRegisterClass *RC,
4722 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4723 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4724 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4725 if (STI.hasAVX512()) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4726 if (isMaskRegClass(RC))
4727 return getLoadStoreMaskRegOpcode(RC, load);
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4728 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4729 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4730 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4731 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4732 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4733 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4734 }
4735
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4736 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4737 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4738 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4739 llvm_unreachable("Unknown spill size");
4740 case 1:
4741 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4742 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4743 // Copying to or from a physical H register on x86-64 requires a NOREX
4744 // move. Otherwise use a normal move.
4745 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4746 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4747 return load ? X86::MOV8rm : X86::MOV8mr;
4748 case 2:
4749 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4750 return load ? X86::MOV16rm : X86::MOV16mr;
4751 case 4:
4752 if (X86::GR32RegClass.hasSubClassEq(RC))
4753 return load ? X86::MOV32rm : X86::MOV32mr;
4754 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4755 return load ?
4756 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4757 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4758 if (X86::RFP32RegClass.hasSubClassEq(RC))
4759 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4760 llvm_unreachable("Unknown 4-byte regclass");
4761 case 8:
4762 if (X86::GR64RegClass.hasSubClassEq(RC))
4763 return load ? X86::MOV64rm : X86::MOV64mr;
4764 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4765 return load ?
4766 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4767 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4768 if (X86::VR64RegClass.hasSubClassEq(RC))
4769 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4770 if (X86::RFP64RegClass.hasSubClassEq(RC))
4771 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4772 llvm_unreachable("Unknown 8-byte regclass");
4773 case 10:
4774 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4775 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4776 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4777 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4778 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4779 // If stack is realigned we can use aligned stores.
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4780 if (X86::VR128RegClass.hasSubClassEq(RC)) {
4781 if (isStackAligned)
4782 return load ? (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
4783 : (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4784 else
4785 return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
4786 : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4787 }
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4788 assert(STI.hasVLX() && "Using extended register requires VLX");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4789 if (isStackAligned)
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4790 return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4791 else
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4792 return load ? X86::VMOVUPSZ128rm : X86::VMOVUPSZ128mr;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4793 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4794 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4795 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4796 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4797 // If stack is realigned we can use aligned stores.
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4798 if (X86::VR256RegClass.hasSubClassEq(RC)) {
4799 if (isStackAligned)
4800 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4801 else
4802 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4803 }
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4804 assert(STI.hasVLX() && "Using extended register requires VLX");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4805 if (isStackAligned)
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4806 return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4807 else
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4808 return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4809 case 64:
4810 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4811 assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4812 if (isStackAligned)
4813 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4814 else
4815 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4816 }
4817}
4818
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4819bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
Chad Rosierc27a18f2016-03-09 16:00:35 +0000[diff] [blame]4820 int64_t &Offset,
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4821 const TargetRegisterInfo *TRI) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4822 const MCInstrDesc &Desc = MemOp.getDesc();
Craig Topper477649a2016-04-28 05:58:46 +0000[diff] [blame]4823 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4824 if (MemRefBegin < 0)
4825 return false;
4826
4827 MemRefBegin += X86II::getOperandBias(Desc);
4828
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4829 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
Sanjoy Das881de4d2016-02-02 02:32:43 +0000[diff] [blame]4830 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4831 return false;
4832
4833 BaseReg = BaseMO.getReg();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4834 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4835 return false;
4836
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4837 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4838 X86::NoRegister)
4839 return false;
4840
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4841 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4842
4843 // Displacement can be symbolic
4844 if (!DispMO.isImm())
4845 return false;
4846
4847 Offset = DispMO.getImm();
4848
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4849 return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4850 X86::NoRegister;
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4851}
4852
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4853static unsigned getStoreRegOpcode(unsigned SrcReg,
4854 const TargetRegisterClass *RC,
4855 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4856 const X86Subtarget &STI) {
4857 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4858}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4859
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4860
4861static unsigned getLoadRegOpcode(unsigned DestReg,
4862 const TargetRegisterClass *RC,
4863 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4864 const X86Subtarget &STI) {
4865 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4866}
4867
4868void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4869 MachineBasicBlock::iterator MI,
4870 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4871 const TargetRegisterClass *RC,
4872 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4873 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4874 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4875 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4876 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4877 bool isAligned =
4878 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4879 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4880 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4881 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4882 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4883 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4884}
4885
4886void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4887 bool isKill,
4888 SmallVectorImpl<MachineOperand> &Addr,
4889 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4890 MachineInstr::mmo_iterator MMOBegin,
4891 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4892 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4893 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4894 bool isAligned = MMOBegin != MMOEnd &&
4895 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4896 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4897 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4898 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4899 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4900 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4901 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4902 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4903 NewMIs.push_back(MIB);
4904}
4905
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4906
4907void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4908 MachineBasicBlock::iterator MI,
4909 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4910 const TargetRegisterClass *RC,
4911 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4912 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4913 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4914 bool isAligned =
4915 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4916 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4917 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4918 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4919 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4920}
4921
4922void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4923 SmallVectorImpl<MachineOperand> &Addr,
4924 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4925 MachineInstr::mmo_iterator MMOBegin,
4926 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4927 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4928 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4929 bool isAligned = MMOBegin != MMOEnd &&
4930 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4931 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4932 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4933 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4934 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4935 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4936 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4937 NewMIs.push_back(MIB);
4938}
4939
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4940bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
4941 unsigned &SrcReg2, int &CmpMask,
4942 int &CmpValue) const {
4943 switch (MI.getOpcode()) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4944 default: break;
4945 case X86::CMP64ri32:
4946 case X86::CMP64ri8:
4947 case X86::CMP32ri:
4948 case X86::CMP32ri8:
4949 case X86::CMP16ri:
4950 case X86::CMP16ri8:
4951 case X86::CMP8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4952 SrcReg = MI.getOperand(0).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4953 SrcReg2 = 0;
4954 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4955 CmpValue = MI.getOperand(1).getImm();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4956 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4957 // A SUB can be used to perform comparison.
4958 case X86::SUB64rm:
4959 case X86::SUB32rm:
4960 case X86::SUB16rm:
4961 case X86::SUB8rm:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4962 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4963 SrcReg2 = 0;
4964 CmpMask = ~0;
4965 CmpValue = 0;
4966 return true;
4967 case X86::SUB64rr:
4968 case X86::SUB32rr:
4969 case X86::SUB16rr:
4970 case X86::SUB8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4971 SrcReg = MI.getOperand(1).getReg();
4972 SrcReg2 = MI.getOperand(2).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4973 CmpMask = ~0;
4974 CmpValue = 0;
4975 return true;
4976 case X86::SUB64ri32:
4977 case X86::SUB64ri8:
4978 case X86::SUB32ri:
4979 case X86::SUB32ri8:
4980 case X86::SUB16ri:
4981 case X86::SUB16ri8:
4982 case X86::SUB8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4983 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4984 SrcReg2 = 0;
4985 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4986 CmpValue = MI.getOperand(2).getImm();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4987 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4988 case X86::CMP64rr:
4989 case X86::CMP32rr:
4990 case X86::CMP16rr:
4991 case X86::CMP8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4992 SrcReg = MI.getOperand(0).getReg();
4993 SrcReg2 = MI.getOperand(1).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4994 CmpMask = ~0;
4995 CmpValue = 0;
4996 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4997 case X86::TEST8rr:
4998 case X86::TEST16rr:
4999 case X86::TEST32rr:
5000 case X86::TEST64rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5001 SrcReg = MI.getOperand(0).getReg();
5002 if (MI.getOperand(1).getReg() != SrcReg)
5003 return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5004 // Compare against zero.
5005 SrcReg2 = 0;
5006 CmpMask = ~0;
5007 CmpValue = 0;
5008 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5009 }
5010 return false;
5011}
5012
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5013/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5014/// purpose is to update flags, can be made redundant.
5015/// CMPrr can be made redundant by SUBrr if the operands are the same.
5016/// This function can be extended later on.
5017/// SrcReg, SrcRegs: register operands for FlagI.
5018/// ImmValue: immediate for FlagI if it takes an immediate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5019inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5020 unsigned SrcReg2, int ImmValue,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5021 MachineInstr &OI) {
5022 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
5023 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
5024 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
5025 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
5026 ((OI.getOperand(1).getReg() == SrcReg &&
5027 OI.getOperand(2).getReg() == SrcReg2) ||
5028 (OI.getOperand(1).getReg() == SrcReg2 &&
5029 OI.getOperand(2).getReg() == SrcReg)))
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5030 return true;
5031
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5032 if (((FlagI.getOpcode() == X86::CMP64ri32 &&
5033 OI.getOpcode() == X86::SUB64ri32) ||
5034 (FlagI.getOpcode() == X86::CMP64ri8 &&
5035 OI.getOpcode() == X86::SUB64ri8) ||
5036 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
5037 (FlagI.getOpcode() == X86::CMP32ri8 &&
5038 OI.getOpcode() == X86::SUB32ri8) ||
5039 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
5040 (FlagI.getOpcode() == X86::CMP16ri8 &&
5041 OI.getOpcode() == X86::SUB16ri8) ||
5042 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
5043 OI.getOperand(1).getReg() == SrcReg &&
5044 OI.getOperand(2).getImm() == ImmValue)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5045 return true;
5046 return false;
5047}
5048
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5049/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5050/// to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5051inline static bool isDefConvertible(MachineInstr &MI) {
5052 switch (MI.getOpcode()) {
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5053 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]5054
5055 // The shift instructions only modify ZF if their shift count is non-zero.
5056 // N.B.: The processor truncates the shift count depending on the encoding.
5057 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
5058 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
5059 return getTruncatedShiftCount(MI, 2) != 0;
5060
5061 // Some left shift instructions can be turned into LEA instructions but only
5062 // if their flags aren't used. Avoid transforming such instructions.
5063 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
5064 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
5065 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
5066 return ShAmt != 0;
5067 }
5068
5069 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
5070 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
5071 return getTruncatedShiftCount(MI, 3) != 0;
5072
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5073 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
5074 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
5075 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
5076 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
5077 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5078 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5079 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
5080 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
5081 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
5082 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
5083 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5084 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5085 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
5086 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
5087 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
5088 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
5089 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
5090 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
5091 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
5092 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
5093 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
5094 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
5095 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
5096 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
5097 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
5098 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
5099 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5100 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
5101 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
5102 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
5103 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
5104 case X86::ADC32ri: case X86::ADC32ri8:
5105 case X86::ADC32rr: case X86::ADC64ri32:
5106 case X86::ADC64ri8: case X86::ADC64rr:
5107 case X86::SBB32ri: case X86::SBB32ri8:
5108 case X86::SBB32rr: case X86::SBB64ri32:
5109 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]5110 case X86::ANDN32rr: case X86::ANDN32rm:
5111 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5112 case X86::BEXTR32rr: case X86::BEXTR64rr:
5113 case X86::BEXTR32rm: case X86::BEXTR64rm:
5114 case X86::BLSI32rr: case X86::BLSI32rm:
5115 case X86::BLSI64rr: case X86::BLSI64rm:
5116 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5117 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5118 case X86::BLSR32rr: case X86::BLSR32rm:
5119 case X86::BLSR64rr: case X86::BLSR64rm:
5120 case X86::BZHI32rr: case X86::BZHI32rm:
5121 case X86::BZHI64rr: case X86::BZHI64rm:
5122 case X86::LZCNT16rr: case X86::LZCNT16rm:
5123 case X86::LZCNT32rr: case X86::LZCNT32rm:
5124 case X86::LZCNT64rr: case X86::LZCNT64rm:
5125 case X86::POPCNT16rr:case X86::POPCNT16rm:
5126 case X86::POPCNT32rr:case X86::POPCNT32rm:
5127 case X86::POPCNT64rr:case X86::POPCNT64rm:
5128 case X86::TZCNT16rr: case X86::TZCNT16rm:
5129 case X86::TZCNT32rr: case X86::TZCNT32rm:
5130 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5131 return true;
5132 }
5133}
5134
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5135/// Check whether the use can be converted to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5136static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5137 switch (MI.getOpcode()) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5138 default: return X86::COND_INVALID;
5139 case X86::LZCNT16rr: case X86::LZCNT16rm:
5140 case X86::LZCNT32rr: case X86::LZCNT32rm:
5141 case X86::LZCNT64rr: case X86::LZCNT64rm:
5142 return X86::COND_B;
5143 case X86::POPCNT16rr:case X86::POPCNT16rm:
5144 case X86::POPCNT32rr:case X86::POPCNT32rm:
5145 case X86::POPCNT64rr:case X86::POPCNT64rm:
5146 return X86::COND_E;
5147 case X86::TZCNT16rr: case X86::TZCNT16rm:
5148 case X86::TZCNT32rr: case X86::TZCNT32rm:
5149 case X86::TZCNT64rr: case X86::TZCNT64rm:
5150 return X86::COND_B;
5151 }
5152}
5153
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5154/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5155/// operates on the same source operands and sets flags in the same way as
5156/// Compare; remove Compare if possible.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5157bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5158 unsigned SrcReg2, int CmpMask,
5159 int CmpValue,
5160 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5161 // Check whether we can replace SUB with CMP.
5162 unsigned NewOpcode = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5163 switch (CmpInstr.getOpcode()) {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5164 default: break;
5165 case X86::SUB64ri32:
5166 case X86::SUB64ri8:
5167 case X86::SUB32ri:
5168 case X86::SUB32ri8:
5169 case X86::SUB16ri:
5170 case X86::SUB16ri8:
5171 case X86::SUB8ri:
5172 case X86::SUB64rm:
5173 case X86::SUB32rm:
5174 case X86::SUB16rm:
5175 case X86::SUB8rm:
5176 case X86::SUB64rr:
5177 case X86::SUB32rr:
5178 case X86::SUB16rr:
5179 case X86::SUB8rr: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5180 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5181 return false;
5182 // There is no use of the destination register, we can replace SUB with CMP.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5183 switch (CmpInstr.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5184 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5185 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5186 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5187 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5188 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5189 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5190 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5191 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5192 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5193 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5194 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5195 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5196 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5197 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5198 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5199 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5200 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5201 CmpInstr.setDesc(get(NewOpcode));
5202 CmpInstr.RemoveOperand(0);
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5203 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5204 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5205 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5206 return false;
5207 }
5208 }
5209
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5210 // Get the unique definition of SrcReg.
5211 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5212 if (!MI) return false;
5213
5214 // CmpInstr is the first instruction of the BB.
5215 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5216
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5217 // If we are comparing against zero, check whether we can use MI to update
5218 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5219 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5220 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5221 return false;
5222
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5223 // If we have a use of the source register between the def and our compare
5224 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5225 // right way.
5226 bool ShouldUpdateCC = false;
5227 X86::CondCode NewCC = X86::COND_INVALID;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5228 if (IsCmpZero && !isDefConvertible(*MI)) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5229 // Scan forward from the use until we hit the use we're looking for or the
5230 // compare instruction.
5231 for (MachineBasicBlock::iterator J = MI;; ++J) {
5232 // Do we have a convertible instruction?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5233 NewCC = isUseDefConvertible(*J);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5234 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5235 J->getOperand(1).getReg() == SrcReg) {
5236 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5237 ShouldUpdateCC = true; // Update CC later on.
5238 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5239 // with the new def.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]5240 Def = J;
5241 MI = &*Def;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5242 break;
5243 }
5244
5245 if (J == I)
5246 return false;
5247 }
5248 }
5249
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5250 // We are searching for an earlier instruction that can make CmpInstr
5251 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5252 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5253 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5254
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5255 // We iterate backward, starting from the instruction before CmpInstr and
5256 // stop when reaching the definition of a source register or done with the BB.
5257 // RI points to the instruction before CmpInstr.
5258 // If the definition is in this basic block, RE points to the definition;
5259 // otherwise, RE is the rend of the basic block.
5260 MachineBasicBlock::reverse_iterator
5261 RI = MachineBasicBlock::reverse_iterator(I),
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5262 RE = CmpInstr.getParent() == MI->getParent()
5263 ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5264 : CmpInstr.getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5265 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5266 for (; RI != RE; ++RI) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5267 MachineInstr &Instr = *RI;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5268 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5269 if (!IsCmpZero &&
5270 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5271 Sub = &Instr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5272 break;
5273 }
5274
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5275 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5276 Instr.readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5277 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5278
5279 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5280 // They are safe to move up, if the definition to EFLAGS is dead and
5281 // earlier instructions do not read or write EFLAGS.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5282 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5283 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5284 Movr0Inst = &Instr;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5285 continue;
5286 }
5287
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5288 // We can't remove CmpInstr.
5289 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5290 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5291 }
5292
5293 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5294 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5295 return false;
5296
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5297 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5298 Sub->getOperand(2).getReg() == SrcReg);
5299
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5300 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5301 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5302 // If we are done with the basic block, we need to check whether EFLAGS is
5303 // live-out.
5304 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5305 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5306 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5307 for (++I; I != E; ++I) {
5308 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5309 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5310 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5311 // We should check the usage if this instruction uses and updates EFLAGS.
5312 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5313 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5314 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5315 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5316 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5317 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5318 continue;
5319
5320 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5321 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5322 bool OpcIsSET = false;
5323 if (IsCmpZero || IsSwapped) {
5324 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5325 if (Instr.isBranch())
5326 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5327 else {
5328 OldCC = getCondFromSETOpc(Instr.getOpcode());
5329 if (OldCC != X86::COND_INVALID)
5330 OpcIsSET = true;
5331 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5332 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5333 }
5334 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5335 }
5336 if (IsCmpZero) {
5337 switch (OldCC) {
5338 default: break;
5339 case X86::COND_A: case X86::COND_AE:
5340 case X86::COND_B: case X86::COND_BE:
5341 case X86::COND_G: case X86::COND_GE:
5342 case X86::COND_L: case X86::COND_LE:
5343 case X86::COND_O: case X86::COND_NO:
5344 // CF and OF are used, we can't perform this optimization.
5345 return false;
5346 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5347
5348 // If we're updating the condition code check if we have to reverse the
5349 // condition.
5350 if (ShouldUpdateCC)
5351 switch (OldCC) {
5352 default:
5353 return false;
5354 case X86::COND_E:
5355 break;
5356 case X86::COND_NE:
5357 NewCC = GetOppositeBranchCondition(NewCC);
5358 break;
5359 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5360 } else if (IsSwapped) {
5361 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5362 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5363 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5364 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5365 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5366 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5367
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5368 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5369 // Synthesize the new opcode.
5370 bool HasMemoryOperand = Instr.hasOneMemOperand();
5371 unsigned NewOpc;
5372 if (Instr.isBranch())
5373 NewOpc = GetCondBranchFromCond(NewCC);
5374 else if(OpcIsSET)
5375 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5376 else {
5377 unsigned DstReg = Instr.getOperand(0).getReg();
5378 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5379 HasMemoryOperand);
5380 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5381
5382 // Push the MachineInstr to OpsToUpdate.
5383 // If it is safe to remove CmpInstr, the condition code of these
5384 // instructions will be modified.
5385 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5386 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5387 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5388 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5389 IsSafe = true;
5390 break;
5391 }
5392 }
5393
5394 // If EFLAGS is not killed nor re-defined, we should check whether it is
5395 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5396 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5397 MachineBasicBlock *MBB = CmpInstr.getParent();
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5398 for (MachineBasicBlock *Successor : MBB->successors())
5399 if (Successor->isLiveIn(X86::EFLAGS))
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5400 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5401 }
5402
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5403 // The instruction to be updated is either Sub or MI.
5404 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5405 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5406 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5407 // Look backwards until we find a def that doesn't use the current EFLAGS.
5408 Def = Sub;
5409 MachineBasicBlock::reverse_iterator
5410 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5411 InsertE = Sub->getParent()->rend();
5412 for (; InsertI != InsertE; ++InsertI) {
5413 MachineInstr *Instr = &*InsertI;
5414 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5415 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5416 Sub->getParent()->remove(Movr0Inst);
5417 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5418 Movr0Inst);
5419 break;
5420 }
5421 }
5422 if (InsertI == InsertE)
5423 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5424 }
5425
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5426 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5427 unsigned i = 0, e = Sub->getNumOperands();
5428 for (; i != e; ++i) {
5429 MachineOperand &MO = Sub->getOperand(i);
5430 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5431 MO.setIsDead(false);
5432 break;
5433 }
5434 }
5435 assert(i != e && "Unable to locate a def EFLAGS operand");
5436
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5437 CmpInstr.eraseFromParent();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5438
5439 // Modify the condition code of instructions in OpsToUpdate.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5440 for (auto &Op : OpsToUpdate)
5441 Op.first->setDesc(get(Op.second));
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5442 return true;
5443}
5444
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5445/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5446/// operand at the use. We fold the load instructions if load defines a virtual
5447/// register, the virtual register is used once in the same BB, and the
5448/// instructions in-between do not load or store, and have no side effects.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5449MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5450 const MachineRegisterInfo *MRI,
5451 unsigned &FoldAsLoadDefReg,
5452 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5453 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5454 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5455 // To be conservative, if there exists another load, clear the load candidate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5456 if (MI.mayLoad()) {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5457 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5458 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5459 }
5460
5461 // Check whether we can move DefMI here.
5462 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5463 assert(DefMI);
5464 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5465 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5466 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5467
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5468 // Collect information about virtual register operands of MI.
5469 unsigned SrcOperandId = 0;
5470 bool FoundSrcOperand = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5471 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5472 MachineOperand &MO = MI.getOperand(i);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5473 if (!MO.isReg())
5474 continue;
5475 unsigned Reg = MO.getReg();
5476 if (Reg != FoldAsLoadDefReg)
5477 continue;
5478 // Do not fold if we have a subreg use or a def or multiple uses.
5479 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5480 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5481
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5482 SrcOperandId = i;
5483 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5484 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5485 if (!FoundSrcOperand)
5486 return nullptr;
5487
5488 // Check whether we can fold the def into SrcOperandId.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5489 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5490 FoldAsLoadDefReg = 0;
5491 return FoldMI;
5492 }
5493
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5494 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5495}
5496
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5497/// Expand a single-def pseudo instruction to a two-addr
5498/// instruction with two undef reads of the register being defined.
5499/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5500/// %xmm4 = V_SET0
5501/// to:
5502/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5503///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5504static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5505 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5506 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5507 unsigned Reg = MIB->getOperand(0).getReg();
5508 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5509
5510 // MachineInstr::addOperand() will insert explicit operands before any
5511 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5512 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5513 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5514 assert(MIB->getOperand(1).getReg() == Reg &&
5515 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5516 return true;
5517}
5518
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5519/// Expand a single-def pseudo instruction to a two-addr
5520/// instruction with two %k0 reads.
5521/// This is used for mapping:
5522/// %k4 = K_SET1
5523/// to:
5524/// %k4 = KXNORrr %k0, %k0
5525static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5526 const MCInstrDesc &Desc, unsigned Reg) {
5527 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5528 MIB->setDesc(Desc);
5529 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5530 return true;
5531}
5532
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5533static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5534 bool MinusOne) {
5535 MachineBasicBlock &MBB = *MIB->getParent();
5536 DebugLoc DL = MIB->getDebugLoc();
5537 unsigned Reg = MIB->getOperand(0).getReg();
5538
5539 // Insert the XOR.
5540 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5541 .addReg(Reg, RegState::Undef)
5542 .addReg(Reg, RegState::Undef);
5543
5544 // Turn the pseudo into an INC or DEC.
5545 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5546 MIB.addReg(Reg);
5547
5548 return true;
5549}
5550
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5551bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5552 MachineBasicBlock &MBB = *MIB->getParent();
5553 DebugLoc DL = MIB->getDebugLoc();
5554 int64_t Imm = MIB->getOperand(1).getImm();
5555 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5556 MachineBasicBlock::iterator I = MIB.getInstr();
5557
5558 int StackAdjustment;
5559
5560 if (Subtarget.is64Bit()) {
5561 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5562 MIB->getOpcode() == X86::MOV32ImmSExti8);
5563
5564 // Can't use push/pop lowering if the function might write to the red zone.
5565 X86MachineFunctionInfo *X86FI =
5566 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5567 if (X86FI->getUsesRedZone()) {
5568 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5569 : X86::MOV64ri));
5570 return true;
5571 }
5572
5573 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5574 // widen the register if necessary.
5575 StackAdjustment = 8;
5576 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5577 MIB->setDesc(get(X86::POP64r));
5578 MIB->getOperand(0)
5579 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5580 } else {
5581 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5582 StackAdjustment = 4;
5583 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5584 MIB->setDesc(get(X86::POP32r));
5585 }
5586
5587 // Build CFI if necessary.
5588 MachineFunction &MF = *MBB.getParent();
5589 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5590 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5591 bool NeedsDwarfCFI =
5592 !IsWin64Prologue &&
5593 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5594 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5595 if (EmitCFI) {
5596 TFL->BuildCFI(MBB, I, DL,
5597 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5598 TFL->BuildCFI(MBB, std::next(I), DL,
5599 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5600 }
5601
5602 return true;
5603}
5604
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5605// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5606// code sequence is needed for other targets.
5607static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5608 const TargetInstrInfo &TII) {
5609 MachineBasicBlock &MBB = *MIB->getParent();
5610 DebugLoc DL = MIB->getDebugLoc();
5611 unsigned Reg = MIB->getOperand(0).getReg();
5612 const GlobalValue *GV =
5613 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5614 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5615 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5616 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5617 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5618
5619 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5620 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5621 .addMemOperand(MMO);
5622 MIB->setDebugLoc(DL);
5623 MIB->setDesc(TII.get(X86::MOV64rm));
5624 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5625}
5626
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5627bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5628 bool HasAVX = Subtarget.hasAVX();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5629 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5630 switch (MI.getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5631 case X86::MOV32r0:
5632 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5633 case X86::MOV32r1:
5634 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5635 case X86::MOV32r_1:
5636 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5637 case X86::MOV32ImmSExti8:
5638 case X86::MOV64ImmSExti8:
5639 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5640 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5641 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5642 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5643 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5644 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5645 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5646 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5647 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5648 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5649 case X86::FsFLD0SS:
5650 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5651 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5652 case X86::AVX_SET0:
5653 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5654 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Craig Toppere5ce84a2016-05-08 21:33:53 +0000[diff] [blame]5655 case X86::AVX512_128_SET0:
5656 return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5657 case X86::AVX512_256_SET0:
5658 return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5659 case X86::AVX512_512_SET0:
5660 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5661 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5662 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5663 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5664 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]5665 case X86::AVX512_512_SETALLONES: {
5666 unsigned Reg = MIB->getOperand(0).getReg();
5667 MIB->setDesc(get(X86::VPTERNLOGDZrri));
5668 // VPTERNLOGD needs 3 register inputs and an immediate.
5669 // 0xff will return 1s for any input.
5670 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5671 .addReg(Reg, RegState::Undef).addImm(0xff);
5672 return true;
5673 }
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5674 case X86::TEST8ri_NOREX:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5675 MI.setDesc(get(X86::TEST8ri));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5676 return true;
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5677 case X86::MOV32ri64:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5678 MI.setDesc(get(X86::MOV32ri));
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5679 return true;
5680
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5681 // KNL does not recognize dependency-breaking idioms for mask registers,
5682 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5683 // Using %k0 as the undef input register is a performance heuristic based
5684 // on the assumption that %k0 is used less frequently than the other mask
5685 // registers, since it is not usable as a write mask.
5686 // FIXME: A more advanced approach would be to choose the best input mask
5687 // register based on context.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5688 case X86::KSET0B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5689 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5690 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5691 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5692 case X86::KSET1B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5693 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5694 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5695 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5696 case TargetOpcode::LOAD_STACK_GUARD:
5697 expandLoadStackGuard(MIB, *this);
5698 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5699 }
5700 return false;
5701}
5702
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5703static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5704 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5705 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5706
5707 if (NumAddrOps < 4) {
5708 // FrameIndex only - add an immediate offset (whether its zero or not).
5709 for (unsigned i = 0; i != NumAddrOps; ++i)
5710 MIB.addOperand(MOs[i]);
5711 addOffset(MIB, PtrOffset);
5712 } else {
5713 // General Memory Addressing - we need to add any offset to an existing
5714 // offset.
5715 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5716 for (unsigned i = 0; i != NumAddrOps; ++i) {
5717 const MachineOperand &MO = MOs[i];
5718 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5719 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5720 } else {
5721 MIB.addOperand(MO);
5722 }
5723 }
5724 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5725}
5726
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5727static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5728 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5729 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5730 MachineInstr &MI,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5731 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5732 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5733 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5734 MachineInstr *NewMI =
5735 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5736 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5737 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5738
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5739 // Loop over the rest of the ri operands, converting them over.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5740 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5741 for (unsigned i = 0; i != NumOps; ++i) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5742 MachineOperand &MO = MI.getOperand(i + 2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5743 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5744 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5745 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5746 MachineOperand &MO = MI.getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5747 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5748 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5749
5750 MachineBasicBlock *MBB = InsertPt->getParent();
5751 MBB->insert(InsertPt, NewMI);
5752
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5753 return MIB;
5754}
5755
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5756static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5757 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5758 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5759 MachineInstr &MI, const TargetInstrInfo &TII,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5760 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5761 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5762 MachineInstr *NewMI =
5763 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5764 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5765
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5766 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5767 MachineOperand &MO = MI.getOperand(i);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5768 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5769 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5770 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5771 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5772 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5773 }
5774 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5775
5776 MachineBasicBlock *MBB = InsertPt->getParent();
5777 MBB->insert(InsertPt, NewMI);
5778
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5779 return MIB;
5780}
5781
5782static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5783 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5784 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5785 MachineInstr &MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5786 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5787 MI.getDebugLoc(), TII.get(Opcode));
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5788 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5789 return MIB.addImm(0);
5790}
5791
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5792MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5793 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5794 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5795 unsigned Size, unsigned Align) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5796 switch (MI.getOpcode()) {
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5797 case X86::INSERTPSrr:
5798 case X86::VINSERTPSrr:
5799 // Attempt to convert the load of inserted vector into a fold load
5800 // of a single float.
5801 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5802 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5803 unsigned ZMask = Imm & 15;
5804 unsigned DstIdx = (Imm >> 4) & 3;
5805 unsigned SrcIdx = (Imm >> 6) & 3;
5806
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5807 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5808 if (Size <= RCSize && 4 <= Align) {
5809 int PtrOffset = SrcIdx * 4;
5810 unsigned NewImm = (DstIdx << 4) | ZMask;
5811 unsigned NewOpCode =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5812 (MI.getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5813 : X86::INSERTPSrm);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5814 MachineInstr *NewMI =
5815 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5816 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5817 return NewMI;
5818 }
5819 }
5820 break;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5821 case X86::MOVHLPSrr:
5822 case X86::VMOVHLPSrr:
5823 // Move the upper 64-bits of the second operand to the lower 64-bits.
5824 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5825 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5826 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5827 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5828 if (Size <= RCSize && 8 <= Align) {
5829 unsigned NewOpCode =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5830 (MI.getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5831 : X86::MOVLPSrm);
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5832 MachineInstr *NewMI =
5833 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5834 return NewMI;
5835 }
5836 }
5837 break;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5838 };
5839
5840 return nullptr;
5841}
5842
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5843MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5844 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5845 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5846 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5847 const DenseMap<unsigned,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5848 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5849 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5850 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5851
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5852 // For CPUs that favor the register form of a call or push,
5853 // do not fold loads into calls or pushes, unless optimizing for size
5854 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5855 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5856 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5857 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5858 MI.getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5859 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5860
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5861 unsigned NumOps = MI.getDesc().getNumOperands();
5862 bool isTwoAddr =
5863 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5864
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5865 // FIXME: AsmPrinter doesn't know how to handle
5866 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5867 if (MI.getOpcode() == X86::ADD32ri &&
5868 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5869 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5870
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5871 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5872
5873 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5874 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5875 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5876 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5877
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5878 // Folding a memory location into the two-address part of a two-address
5879 // instruction is different than folding it other places. It requires
5880 // replacing the *two* registers with the memory location.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5881 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5882 MI.getOperand(1).isReg() &&
5883 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5884 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5885 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5886 } else if (OpNum == 0) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5887 if (MI.getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5888 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5889 if (NewMI)
5890 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5891 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5892
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5893 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5894 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5895 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5896 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5897 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5898 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]5899 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5900 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]5901 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5902 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5903
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5904 // If table selected...
5905 if (OpcodeTablePtr) {
5906 // Find the Opcode to fuse
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5907 auto I = OpcodeTablePtr->find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5908 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5909 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5910 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5911 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5912 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5913 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5914 if (Size) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5915 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5916 if (Size < RCSize) {
5917 // Check if it's safe to fold the load. If the size of the object is
5918 // narrower than the load width, then it's not.
5919 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5920 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5921 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5922 // a 32-bit load which is implicitly zero-extended. This likely is
5923 // due to live interval analysis remat'ing a load from stack slot.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5924 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5925 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5926 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5927 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5928 }
5929 }
5930
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5931 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5932 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5933 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5934 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5935
5936 if (NarrowToMOV32rm) {
5937 // If this is the special case where we use a MOV32rm to load a 32-bit
5938 // value and zero-extend the top bits. Change the destination register
5939 // to a 32-bit one.
5940 unsigned DstReg = NewMI->getOperand(0).getReg();
5941 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5942 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5943 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]5944 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5945 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5946 return NewMI;
5947 }
5948 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5949
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5950 // If the instruction and target operand are commutable, commute the
5951 // instruction and try again.
5952 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5953 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5954 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5955 bool HasDef = MI.getDesc().getNumDefs();
5956 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
5957 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5958 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5959 bool Tied1 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5960 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5961 bool Tied2 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5962 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5963
5964 // If either of the commutable operands are tied to the destination
5965 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5966 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5967 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5968 return nullptr;
5969
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5970 MachineInstr *CommutedMI =
5971 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5972 if (!CommutedMI) {
5973 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5974 return nullptr;
5975 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5976 if (CommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5977 // New instruction. We can't fold from this.
5978 CommutedMI->eraseFromParent();
5979 return nullptr;
5980 }
5981
5982 // Attempt to fold with the commuted version of the instruction.
5983 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5984 Size, Align, /*AllowCommute=*/false);
5985 if (NewMI)
5986 return NewMI;
5987
5988 // Folding failed again - undo the commute before returning.
5989 MachineInstr *UncommutedMI =
5990 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5991 if (!UncommutedMI) {
5992 // Unable to commute.
5993 return nullptr;
5994 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5995 if (UncommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5996 // New instruction. It doesn't need to be kept.
5997 UncommutedMI->eraseFromParent();
5998 return nullptr;
5999 }
6000
6001 // Return here to prevent duplicate fuse failure report.
6002 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6003 }
6004 }
6005
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6006 // No fusion
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6007 if (PrintFailedFusing && !MI.isCopy())
6008 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6009 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6010}
6011
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6012/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6013/// the first 32 or 64-bits of the destination register and leave the rest
6014/// unmodified. This can be used to avoid folding loads if the instructions
6015/// only update part of the destination register, and the non-updated part is
6016/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6017/// instructions breaks the partial register dependency and it can improve
6018/// performance. e.g.:
6019///
6020/// movss (%rdi), %xmm0
6021/// cvtss2sd %xmm0, %xmm0
6022///
6023/// Instead of
6024/// cvtss2sd (%rdi), %xmm0
6025///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]6026/// FIXME: This should be turned into a TSFlags.
6027///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6028static bool hasPartialRegUpdate(unsigned Opcode) {
6029 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6030 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6031 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6032 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6033 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6034 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6035 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6036 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6037 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6038 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6039 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6040 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6041 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6042 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6043 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6044 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6045 case X86::Int_CVTSS2SDrm:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]6046 case X86::MOVHPDrm:
6047 case X86::MOVHPSrm:
6048 case X86::MOVLPDrm:
6049 case X86::MOVLPSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6050 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6051 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6052 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6053 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6054 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6055 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6056 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6057 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6058 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6059 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6060 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6061 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6062 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6063 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6064 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6065 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6066 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6067 case X86::SQRTSSm_Int:
6068 case X86::SQRTSDr:
6069 case X86::SQRTSDm:
6070 case X86::SQRTSDr_Int:
6071 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6072 return true;
6073 }
6074
6075 return false;
6076}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6077
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6078/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6079/// instructions we would like before a partial register update.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6080unsigned X86InstrInfo::getPartialRegUpdateClearance(
6081 const MachineInstr &MI, unsigned OpNum,
6082 const TargetRegisterInfo *TRI) const {
6083 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6084 return 0;
6085
6086 // If MI is marked as reading Reg, the partial register update is wanted.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6087 const MachineOperand &MO = MI.getOperand(0);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6088 unsigned Reg = MO.getReg();
6089 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6090 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6091 return 0;
6092 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6093 if (MI.readsRegister(Reg, TRI))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6094 return 0;
6095 }
6096
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6097 // If any instructions in the clearance range are reading Reg, insert a
6098 // dependency breaking instruction, which is inexpensive and is likely to
6099 // be hidden in other instruction's cycles.
6100 return PartialRegUpdateClearance;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6101}
6102
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6103// Return true for any instruction the copies the high bits of the first source
6104// operand into the unused high bits of the destination operand.
6105static bool hasUndefRegUpdate(unsigned Opcode) {
6106 switch (Opcode) {
6107 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6108 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6109 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6110 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6111 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6112 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6113 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6114 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6115 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6116 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6117 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6118 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6119 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6120 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6121 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6122 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6123 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6124 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6125 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6126 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6127 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6128 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6129 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6130 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6131 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6132 case X86::VRCPSSm:
6133 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6134 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6135 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6136 case X86::VROUNDSDr_Int:
6137 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6138 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6139 case X86::VROUNDSSr_Int:
6140 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6141 case X86::VRSQRTSSm:
6142 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6143 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6144 case X86::VSQRTSSm:
6145 case X86::VSQRTSSm_Int:
6146 case X86::VSQRTSDr:
6147 case X86::VSQRTSDm:
6148 case X86::VSQRTSDm_Int:
6149 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6150 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6151 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6152 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6153 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6154 return true;
6155 }
6156
6157 return false;
6158}
6159
6160/// Inform the ExeDepsFix pass how many idle instructions we would like before
6161/// certain undef register reads.
6162///
6163/// This catches the VCVTSI2SD family of instructions:
6164///
6165/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6166///
6167/// We should to be careful *not* to catch VXOR idioms which are presumably
6168/// handled specially in the pipeline:
6169///
6170/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6171///
6172/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6173/// high bits that are passed-through are not live.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6174unsigned
6175X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6176 const TargetRegisterInfo *TRI) const {
6177 if (!hasUndefRegUpdate(MI.getOpcode()))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6178 return 0;
6179
6180 // Set the OpNum parameter to the first source operand.
6181 OpNum = 1;
6182
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6183 const MachineOperand &MO = MI.getOperand(OpNum);
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6184 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6185 return UndefRegClearance;
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6186 }
6187 return 0;
6188}
6189
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6190void X86InstrInfo::breakPartialRegDependency(
6191 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6192 unsigned Reg = MI.getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6193 // If MI kills this register, the false dependence is already broken.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6194 if (MI.killsRegister(Reg, TRI))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6195 return;
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6196
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6197 if (X86::VR128RegClass.contains(Reg)) {
6198 // These instructions are all floating point domain, so xorps is the best
6199 // choice.
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6200 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6201 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6202 .addReg(Reg, RegState::Undef)
6203 .addReg(Reg, RegState::Undef);
6204 MI.addRegisterKilled(Reg, TRI, true);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6205 } else if (X86::VR256RegClass.contains(Reg)) {
6206 // Use vxorps to clear the full ymm register.
6207 // It wants to read and write the xmm sub-register.
6208 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6209 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6210 .addReg(XReg, RegState::Undef)
6211 .addReg(XReg, RegState::Undef)
6212 .addReg(Reg, RegState::ImplicitDefine);
6213 MI.addRegisterKilled(Reg, TRI, true);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6214 }
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6215}
6216
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6217MachineInstr *
6218X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6219 ArrayRef<unsigned> Ops,
6220 MachineBasicBlock::iterator InsertPt,
6221 int FrameIndex, LiveIntervals *LIS) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6222 // Check switch flag
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6223 if (NoFusing)
6224 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6225
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6226 // Unless optimizing for size, don't fold to avoid partial
6227 // register update stalls
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6228 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6229 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6230
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6231 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6232 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6233 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]6234 // If the function stack isn't realigned we don't want to fold instructions
6235 // that need increased alignment.
6236 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6237 Alignment =
6238 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6239 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6240 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6241 unsigned RCSize = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6242 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6243 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6244 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]6245 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6246 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6247 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6248 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6249 // Check if it's safe to fold the load. If the size of the object is
6250 // narrower than the load width, then it's not.
6251 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6252 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6253 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6254 MI.setDesc(get(NewOpc));
6255 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6256 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6257 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6258
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]6259 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6260 MachineOperand::CreateFI(FrameIndex), InsertPt,
6261 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6262}
6263
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6264/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6265/// because the latter uses contents that wouldn't be defined in the folded
6266/// version. For instance, this transformation isn't legal:
6267/// movss (%rdi), %xmm0
6268/// addps %xmm0, %xmm0
6269/// ->
6270/// addps (%rdi), %xmm0
6271///
6272/// But this one is:
6273/// movss (%rdi), %xmm0
6274/// addss %xmm0, %xmm0
6275/// ->
6276/// addss (%rdi), %xmm0
6277///
6278static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6279 const MachineInstr &UserMI,
6280 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6281 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6282 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6283 unsigned RegSize =
6284 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6285
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]6286 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
6287 RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6288 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6289 // destination register is wider than 32 bits (4 bytes), and its user
6290 // instruction isn't scalar (SS).
6291 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]6292 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
6293 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
6294 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6295 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6296 case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6297 case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6298 case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6299 case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6300 case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6301 case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6302 return false;
6303 default:
6304 return true;
6305 }
6306 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6307
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]6308 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
6309 RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6310 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6311 // destination register is wider than 64 bits (8 bytes), and its user
6312 // instruction isn't scalar (SD).
6313 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame^]6314 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6315 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6316 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6317 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6318 case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6319 case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6320 case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6321 case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6322 case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6323 case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6324 return false;
6325 default:
6326 return true;
6327 }
6328 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6329
6330 return false;
6331}
6332
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6333MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6334 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6335 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6336 LiveIntervals *LIS) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6337 // If loading from a FrameIndex, fold directly from the FrameIndex.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6338 unsigned NumOps = LoadMI.getDesc().getNumOperands();
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6339 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6340 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6341 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6342 return nullptr;
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6343 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6344 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6345
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6346 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6347 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6348
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6349 // Avoid partial register update stalls unless optimizing for size.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6350 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6351 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6352
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6353 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6354 unsigned Alignment = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6355 if (LoadMI.hasOneMemOperand())
6356 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6357 else
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6358 switch (LoadMI.getOpcode()) {
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6359 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6360 case X86::AVX512_512_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6361 Alignment = 64;
6362 break;
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6363 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6364 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6365 case X86::AVX512_256_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6366 Alignment = 32;
6367 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6368 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6369 case X86::V_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6370 case X86::AVX512_128_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6371 Alignment = 16;
6372 break;
6373 case X86::FsFLD0SD:
6374 Alignment = 8;
6375 break;
6376 case X86::FsFLD0SS:
6377 Alignment = 4;
6378 break;
6379 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6380 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6381 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6382 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6383 unsigned NewOpc = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6384 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6385 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6386 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6387 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6388 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6389 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6390 }
6391 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6392 MI.setDesc(get(NewOpc));
6393 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6394 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6395 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6396
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6397 // Make sure the subregisters match.
6398 // Otherwise we risk changing the size of the load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6399 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6400 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6401
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6402 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6403 switch (LoadMI.getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6404 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6405 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6406 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6407 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6408 case X86::AVX512_128_SET0:
6409 case X86::AVX512_256_SET0:
6410 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6411 case X86::AVX512_512_SETALLONES:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6412 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6413 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6414 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6415 // Create a constant-pool entry and operands to load from it.
6416
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6417 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6418 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6419 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6420 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6421
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6422 // x86-32 PIC requires a PIC base register for constant pools.
6423 unsigned PICBase = 0;
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]6424 if (MF.getTarget().isPositionIndependent()) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6425 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6426 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6427 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6428 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6429 // This doesn't work for several reasons.
6430 // 1. GlobalBaseReg may have been spilled.
6431 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6432 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6433 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6434
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6435 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6436 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6437 Type *Ty;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6438 unsigned Opc = LoadMI.getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6439 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6440 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6441 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6442 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6443 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6444 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6445 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6446 Opc == X86::AVX512_256_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6447 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6448 else
6449 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6450
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6451 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6452 Opc == X86::AVX512_512_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6453 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6454 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6455 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6456
6457 // Create operands to load from the constant pool entry.
6458 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6459 MOs.push_back(MachineOperand::CreateImm(1));
6460 MOs.push_back(MachineOperand::CreateReg(0, false));
6461 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6462 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6463 break;
6464 }
6465 default: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6466 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6467 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6468
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6469 // Folding a normal load. Just copy the load's address operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6470 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6471 LoadMI.operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6472 break;
6473 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6474 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6475 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6476 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6477}
6478
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6479bool X86InstrInfo::unfoldMemoryOperand(
6480 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6481 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6482 auto I = MemOp2RegOpTable.find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6483 if (I == MemOp2RegOpTable.end())
6484 return false;
6485 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6486 unsigned Index = I->second.second & TB_INDEX_MASK;
6487 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6488 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6489 if (UnfoldLoad && !FoldedLoad)
6490 return false;
6491 UnfoldLoad &= FoldedLoad;
6492 if (UnfoldStore && !FoldedStore)
6493 return false;
6494 UnfoldStore &= FoldedStore;
6495
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6496 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6497 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6498 // TODO: Check if 32-byte or greater accesses are slow too?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6499 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6500 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6501 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6502 // conservatively assume the address is unaligned. That's bad for
6503 // performance.
6504 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6505 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6506 SmallVector<MachineOperand,2> BeforeOps;
6507 SmallVector<MachineOperand,2> AfterOps;
6508 SmallVector<MachineOperand,4> ImpOps;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6509 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6510 MachineOperand &Op = MI.getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6511 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6512 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6513 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6514 ImpOps.push_back(Op);
6515 else if (i < Index)
6516 BeforeOps.push_back(Op);
6517 else if (i > Index)
6518 AfterOps.push_back(Op);
6519 }
6520
6521 // Emit the load instruction.
6522 if (UnfoldLoad) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6523 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6524 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6525 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6526 if (UnfoldStore) {
6527 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6528 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6529 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6530 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6531 MO.setIsKill(false);
6532 }
6533 }
6534 }
6535
6536 // Emit the data processing instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6537 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6538 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6539
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6540 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6541 MIB.addReg(Reg, RegState::Define);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6542 for (MachineOperand &BeforeOp : BeforeOps)
6543 MIB.addOperand(BeforeOp);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6544 if (FoldedLoad)
6545 MIB.addReg(Reg);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6546 for (MachineOperand &AfterOp : AfterOps)
6547 MIB.addOperand(AfterOp);
6548 for (MachineOperand &ImpOp : ImpOps) {
6549 MIB.addReg(ImpOp.getReg(),
6550 getDefRegState(ImpOp.isDef()) |
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6551 RegState::Implicit |
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6552 getKillRegState(ImpOp.isKill()) |
6553 getDeadRegState(ImpOp.isDead()) |
6554 getUndefRegState(ImpOp.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6555 }
6556 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6557 switch (DataMI->getOpcode()) {
6558 default: break;
6559 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6560 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6561 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6562 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6563 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6564 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6565 case X86::CMP8ri: {
6566 MachineOperand &MO0 = DataMI->getOperand(0);
6567 MachineOperand &MO1 = DataMI->getOperand(1);
6568 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6569 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6570 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6571 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6572 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6573 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6574 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6575 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6576 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6577 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6578 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6579 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6580 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6581 MO1.ChangeToRegister(MO0.getReg(), false);
6582 }
6583 }
6584 }
6585 NewMIs.push_back(DataMI);
6586
6587 // Emit the store instruction.
6588 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6589 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6590 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6591 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6592 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6593 }
6594
6595 return true;
6596}
6597
6598bool
6599X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6600 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6601 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6602 return false;
6603
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6604 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6605 if (I == MemOp2RegOpTable.end())
6606 return false;
6607 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6608 unsigned Index = I->second.second & TB_INDEX_MASK;
6609 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6610 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6611 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6612 MachineFunction &MF = DAG.getMachineFunction();
6613 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6614 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6615 std::vector<SDValue> AddrOps;
6616 std::vector<SDValue> BeforeOps;
6617 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6618 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6619 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6620 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6621 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6622 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6623 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6624 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6625 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6626 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6627 AfterOps.push_back(Op);
6628 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6629 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6630 AddrOps.push_back(Chain);
6631
6632 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6633 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6634 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6635 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6636 std::pair<MachineInstr::mmo_iterator,
6637 MachineInstr::mmo_iterator> MMOs =
6638 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6639 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6640 if (!(*MMOs.first) &&
6641 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6642 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6643 // Do not introduce a slow unaligned load.
6644 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6645 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6646 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6647 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6648 bool isAligned = (*MMOs.first) &&
6649 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6650 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6651 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6652 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6653
6654 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6655 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6656 }
6657
6658 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6659 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6660 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6661 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6662 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6663 VTs.push_back(*DstRC->vt_begin());
6664 }
6665 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6666 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6667 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6668 VTs.push_back(VT);
6669 }
6670 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6671 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6672 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6673 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6674 NewNodes.push_back(NewNode);
6675
6676 // Emit the store instruction.
6677 if (FoldedStore) {
6678 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6679 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6680 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6681 std::pair<MachineInstr::mmo_iterator,
6682 MachineInstr::mmo_iterator> MMOs =
6683 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6684 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6685 if (!(*MMOs.first) &&
6686 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6687 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6688 // Do not introduce a slow unaligned store.
6689 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6690 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6691 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6692 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6693 bool isAligned = (*MMOs.first) &&
6694 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6695 SDNode *Store =
6696 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6697 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6698 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6699
6700 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6701 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6702 }
6703
6704 return true;
6705}
6706
6707unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6708 bool UnfoldLoad, bool UnfoldStore,
6709 unsigned *LoadRegIndex) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6710 auto I = MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6711 if (I == MemOp2RegOpTable.end())
6712 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6713 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6714 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6715 if (UnfoldLoad && !FoldedLoad)
6716 return 0;
6717 if (UnfoldStore && !FoldedStore)
6718 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6719 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6720 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6721 return I->second.first;
6722}
6723
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6724bool
6725X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6726 int64_t &Offset1, int64_t &Offset2) const {
6727 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6728 return false;
6729 unsigned Opc1 = Load1->getMachineOpcode();
6730 unsigned Opc2 = Load2->getMachineOpcode();
6731 switch (Opc1) {
6732 default: return false;
6733 case X86::MOV8rm:
6734 case X86::MOV16rm:
6735 case X86::MOV32rm:
6736 case X86::MOV64rm:
6737 case X86::LD_Fp32m:
6738 case X86::LD_Fp64m:
6739 case X86::LD_Fp80m:
6740 case X86::MOVSSrm:
6741 case X86::MOVSDrm:
6742 case X86::MMX_MOVD64rm:
6743 case X86::MMX_MOVQ64rm:
6744 case X86::FsMOVAPSrm:
6745 case X86::FsMOVAPDrm:
6746 case X86::MOVAPSrm:
6747 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6748 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6749 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6750 case X86::MOVDQArm:
6751 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6752 // AVX load instructions
6753 case X86::VMOVSSrm:
6754 case X86::VMOVSDrm:
6755 case X86::FsVMOVAPSrm:
6756 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6757 case X86::VMOVAPSrm:
6758 case X86::VMOVUPSrm:
6759 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6760 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6761 case X86::VMOVDQArm:
6762 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6763 case X86::VMOVAPSYrm:
6764 case X86::VMOVUPSYrm:
6765 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6766 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6767 case X86::VMOVDQAYrm:
6768 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6769 // AVX512 load instructions
6770 case X86::VMOVSSZrm:
6771 case X86::VMOVSDZrm:
6772 case X86::VMOVAPSZ128rm:
6773 case X86::VMOVUPSZ128rm:
6774 case X86::VMOVAPDZ128rm:
6775 case X86::VMOVUPDZ128rm:
6776 case X86::VMOVDQU8Z128rm:
6777 case X86::VMOVDQU16Z128rm:
6778 case X86::VMOVDQA32Z128rm:
6779 case X86::VMOVDQU32Z128rm:
6780 case X86::VMOVDQA64Z128rm:
6781 case X86::VMOVDQU64Z128rm:
6782 case X86::VMOVAPSZ256rm:
6783 case X86::VMOVUPSZ256rm:
6784 case X86::VMOVAPDZ256rm:
6785 case X86::VMOVUPDZ256rm:
6786 case X86::VMOVDQU8Z256rm:
6787 case X86::VMOVDQU16Z256rm:
6788 case X86::VMOVDQA32Z256rm:
6789 case X86::VMOVDQU32Z256rm:
6790 case X86::VMOVDQA64Z256rm:
6791 case X86::VMOVDQU64Z256rm:
6792 case X86::VMOVAPSZrm:
6793 case X86::VMOVUPSZrm:
6794 case X86::VMOVAPDZrm:
6795 case X86::VMOVUPDZrm:
6796 case X86::VMOVDQU8Zrm:
6797 case X86::VMOVDQU16Zrm:
6798 case X86::VMOVDQA32Zrm:
6799 case X86::VMOVDQU32Zrm:
6800 case X86::VMOVDQA64Zrm:
6801 case X86::VMOVDQU64Zrm:
6802 case X86::KMOVBkm:
6803 case X86::KMOVWkm:
6804 case X86::KMOVDkm:
6805 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6806 break;
6807 }
6808 switch (Opc2) {
6809 default: return false;
6810 case X86::MOV8rm:
6811 case X86::MOV16rm:
6812 case X86::MOV32rm:
6813 case X86::MOV64rm:
6814 case X86::LD_Fp32m:
6815 case X86::LD_Fp64m:
6816 case X86::LD_Fp80m:
6817 case X86::MOVSSrm:
6818 case X86::MOVSDrm:
6819 case X86::MMX_MOVD64rm:
6820 case X86::MMX_MOVQ64rm:
6821 case X86::FsMOVAPSrm:
6822 case X86::FsMOVAPDrm:
6823 case X86::MOVAPSrm:
6824 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6825 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6826 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6827 case X86::MOVDQArm:
6828 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6829 // AVX load instructions
6830 case X86::VMOVSSrm:
6831 case X86::VMOVSDrm:
6832 case X86::FsVMOVAPSrm:
6833 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6834 case X86::VMOVAPSrm:
6835 case X86::VMOVUPSrm:
6836 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6837 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6838 case X86::VMOVDQArm:
6839 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6840 case X86::VMOVAPSYrm:
6841 case X86::VMOVUPSYrm:
6842 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6843 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6844 case X86::VMOVDQAYrm:
6845 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6846 // AVX512 load instructions
6847 case X86::VMOVSSZrm:
6848 case X86::VMOVSDZrm:
6849 case X86::VMOVAPSZ128rm:
6850 case X86::VMOVUPSZ128rm:
6851 case X86::VMOVAPDZ128rm:
6852 case X86::VMOVUPDZ128rm:
6853 case X86::VMOVDQU8Z128rm:
6854 case X86::VMOVDQU16Z128rm:
6855 case X86::VMOVDQA32Z128rm:
6856 case X86::VMOVDQU32Z128rm:
6857 case X86::VMOVDQA64Z128rm:
6858 case X86::VMOVDQU64Z128rm:
6859 case X86::VMOVAPSZ256rm:
6860 case X86::VMOVUPSZ256rm:
6861 case X86::VMOVAPDZ256rm:
6862 case X86::VMOVUPDZ256rm:
6863 case X86::VMOVDQU8Z256rm:
6864 case X86::VMOVDQU16Z256rm:
6865 case X86::VMOVDQA32Z256rm:
6866 case X86::VMOVDQU32Z256rm:
6867 case X86::VMOVDQA64Z256rm:
6868 case X86::VMOVDQU64Z256rm:
6869 case X86::VMOVAPSZrm:
6870 case X86::VMOVUPSZrm:
6871 case X86::VMOVAPDZrm:
6872 case X86::VMOVUPDZrm:
6873 case X86::VMOVDQU8Zrm:
6874 case X86::VMOVDQU16Zrm:
6875 case X86::VMOVDQA32Zrm:
6876 case X86::VMOVDQU32Zrm:
6877 case X86::VMOVDQA64Zrm:
6878 case X86::VMOVDQU64Zrm:
6879 case X86::KMOVBkm:
6880 case X86::KMOVWkm:
6881 case X86::KMOVDkm:
6882 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6883 break;
6884 }
6885
6886 // Check if chain operands and base addresses match.
6887 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6888 Load1->getOperand(5) != Load2->getOperand(5))
6889 return false;
6890 // Segment operands should match as well.
6891 if (Load1->getOperand(4) != Load2->getOperand(4))
6892 return false;
6893 // Scale should be 1, Index should be Reg0.
6894 if (Load1->getOperand(1) == Load2->getOperand(1) &&
6895 Load1->getOperand(2) == Load2->getOperand(2)) {
6896 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6897 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6898
6899 // Now let's examine the displacements.
6900 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6901 isa<ConstantSDNode>(Load2->getOperand(3))) {
6902 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6903 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6904 return true;
6905 }
6906 }
6907 return false;
6908}
6909
6910bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6911 int64_t Offset1, int64_t Offset2,
6912 unsigned NumLoads) const {
6913 assert(Offset2 > Offset1);
6914 if ((Offset2 - Offset1) / 8 > 64)
6915 return false;
6916
6917 unsigned Opc1 = Load1->getMachineOpcode();
6918 unsigned Opc2 = Load2->getMachineOpcode();
6919 if (Opc1 != Opc2)
6920 return false; // FIXME: overly conservative?
6921
6922 switch (Opc1) {
6923 default: break;
6924 case X86::LD_Fp32m:
6925 case X86::LD_Fp64m:
6926 case X86::LD_Fp80m:
6927 case X86::MMX_MOVD64rm:
6928 case X86::MMX_MOVQ64rm:
6929 return false;
6930 }
6931
6932 EVT VT = Load1->getValueType(0);
6933 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6934 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6935 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6936 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6937 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6938 if (NumLoads >= 3)
6939 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6940 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6941 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6942 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6943 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6944 case MVT::i8:
6945 case MVT::i16:
6946 case MVT::i32:
6947 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]6948 case MVT::f32:
6949 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6950 if (NumLoads)
6951 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6952 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6953 }
6954
6955 return true;
6956}
6957
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6958bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
6959 MachineInstr &Second) const {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6960 // Check if this processor supports macro-fusion. Since this is a minor
6961 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6962 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6963 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6964 return false;
6965
6966 enum {
6967 FuseTest,
6968 FuseCmp,
6969 FuseInc
6970 } FuseKind;
6971
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6972 switch (Second.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6973 default:
6974 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6975 case X86::JE_1:
6976 case X86::JNE_1:
6977 case X86::JL_1:
6978 case X86::JLE_1:
6979 case X86::JG_1:
6980 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6981 FuseKind = FuseInc;
6982 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6983 case X86::JB_1:
6984 case X86::JBE_1:
6985 case X86::JA_1:
6986 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6987 FuseKind = FuseCmp;
6988 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6989 case X86::JS_1:
6990 case X86::JNS_1:
6991 case X86::JP_1:
6992 case X86::JNP_1:
6993 case X86::JO_1:
6994 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6995 FuseKind = FuseTest;
6996 break;
6997 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6998 switch (First.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6999 default:
7000 return false;
7001 case X86::TEST8rr:
7002 case X86::TEST16rr:
7003 case X86::TEST32rr:
7004 case X86::TEST64rr:
7005 case X86::TEST8ri:
7006 case X86::TEST16ri:
7007 case X86::TEST32ri:
7008 case X86::TEST32i32:
7009 case X86::TEST64i32:
7010 case X86::TEST64ri32:
7011 case X86::TEST8rm:
7012 case X86::TEST16rm:
7013 case X86::TEST32rm:
7014 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]7015 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7016 case X86::AND16i16:
7017 case X86::AND16ri:
7018 case X86::AND16ri8:
7019 case X86::AND16rm:
7020 case X86::AND16rr:
7021 case X86::AND32i32:
7022 case X86::AND32ri:
7023 case X86::AND32ri8:
7024 case X86::AND32rm:
7025 case X86::AND32rr:
7026 case X86::AND64i32:
7027 case X86::AND64ri32:
7028 case X86::AND64ri8:
7029 case X86::AND64rm:
7030 case X86::AND64rr:
7031 case X86::AND8i8:
7032 case X86::AND8ri:
7033 case X86::AND8rm:
7034 case X86::AND8rr:
7035 return true;
7036 case X86::CMP16i16:
7037 case X86::CMP16ri:
7038 case X86::CMP16ri8:
7039 case X86::CMP16rm:
7040 case X86::CMP16rr:
7041 case X86::CMP32i32:
7042 case X86::CMP32ri:
7043 case X86::CMP32ri8:
7044 case X86::CMP32rm:
7045 case X86::CMP32rr:
7046 case X86::CMP64i32:
7047 case X86::CMP64ri32:
7048 case X86::CMP64ri8:
7049 case X86::CMP64rm:
7050 case X86::CMP64rr:
7051 case X86::CMP8i8:
7052 case X86::CMP8ri:
7053 case X86::CMP8rm:
7054 case X86::CMP8rr:
7055 case X86::ADD16i16:
7056 case X86::ADD16ri:
7057 case X86::ADD16ri8:
7058 case X86::ADD16ri8_DB:
7059 case X86::ADD16ri_DB:
7060 case X86::ADD16rm:
7061 case X86::ADD16rr:
7062 case X86::ADD16rr_DB:
7063 case X86::ADD32i32:
7064 case X86::ADD32ri:
7065 case X86::ADD32ri8:
7066 case X86::ADD32ri8_DB:
7067 case X86::ADD32ri_DB:
7068 case X86::ADD32rm:
7069 case X86::ADD32rr:
7070 case X86::ADD32rr_DB:
7071 case X86::ADD64i32:
7072 case X86::ADD64ri32:
7073 case X86::ADD64ri32_DB:
7074 case X86::ADD64ri8:
7075 case X86::ADD64ri8_DB:
7076 case X86::ADD64rm:
7077 case X86::ADD64rr:
7078 case X86::ADD64rr_DB:
7079 case X86::ADD8i8:
7080 case X86::ADD8mi:
7081 case X86::ADD8mr:
7082 case X86::ADD8ri:
7083 case X86::ADD8rm:
7084 case X86::ADD8rr:
7085 case X86::SUB16i16:
7086 case X86::SUB16ri:
7087 case X86::SUB16ri8:
7088 case X86::SUB16rm:
7089 case X86::SUB16rr:
7090 case X86::SUB32i32:
7091 case X86::SUB32ri:
7092 case X86::SUB32ri8:
7093 case X86::SUB32rm:
7094 case X86::SUB32rr:
7095 case X86::SUB64i32:
7096 case X86::SUB64ri32:
7097 case X86::SUB64ri8:
7098 case X86::SUB64rm:
7099 case X86::SUB64rr:
7100 case X86::SUB8i8:
7101 case X86::SUB8ri:
7102 case X86::SUB8rm:
7103 case X86::SUB8rr:
7104 return FuseKind == FuseCmp || FuseKind == FuseInc;
7105 case X86::INC16r:
7106 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7107 case X86::INC64r:
7108 case X86::INC8r:
7109 case X86::DEC16r:
7110 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7111 case X86::DEC64r:
7112 case X86::DEC8r:
7113 return FuseKind == FuseInc;
7114 }
7115}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7116
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7117bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]7118ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7119 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]7120 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7121 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7122 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7123}
7124
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7125bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7126isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7127 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7128 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7129 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7130 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7131}
7132
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7133/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7134/// the global base register value. Output instructions required to
7135/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7136///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7137/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7138///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7139unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7140 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7141 "X86-64 PIC uses RIP relative addressing");
7142
7143 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7144 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7145 if (GlobalBaseReg != 0)
7146 return GlobalBaseReg;
7147
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7148 // Create the register. The code to initialize it is inserted
7149 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7150 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]7151 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7152 X86FI->setGlobalBaseReg(GlobalBaseReg);
7153 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7154}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7155
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7156// These are the replaceable SSE instructions. Some of these have Int variants
7157// that we don't include here. We don't want to replace instructions selected
7158// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7159static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]7160 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7161 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
7162 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
7163 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
7164 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
7165 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]7166 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7167 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
7168 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
7169 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
7170 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
7171 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
7172 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
7173 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
7174 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
7175 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7176 // AVX 128-bit support
7177 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
7178 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
7179 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
7180 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
7181 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]7182 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7183 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7184 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
7185 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
7186 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
7187 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
7188 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
7189 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7190 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
7191 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]7192 // AVX 256-bit support
7193 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
7194 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
7195 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
7196 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
7197 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7198 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
7199};
7200
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7201static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7202 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]7203 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
7204 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
7205 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
7206 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
7207 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
7208 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
7209 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]7210 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
7211 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7212 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7213 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
7214 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
7215 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]7216 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
7217 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7218 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7219 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7220 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7221 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7222 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7223};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7224
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7225// FIXME: Some shuffle and unpack instructions have equivalents in different
7226// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7227
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7228static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7229 for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7230 if (Row[domain-1] == opcode)
7231 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7232 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7233}
7234
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7235static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7236 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7237 if (Row[domain-1] == opcode)
7238 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7239 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7240}
7241
7242std::pair<uint16_t, uint16_t>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7243X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7244 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7245 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7246 uint16_t validDomains = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7247 if (domain && lookup(MI.getOpcode(), domain))
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7248 validDomains = 0xe;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7249 else if (domain && lookupAVX2(MI.getOpcode(), domain))
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7250 validDomains = hasAVX2 ? 0xe : 0x6;
7251 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7252}
7253
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7254void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7255 assert(Domain>0 && Domain<4 && "Invalid execution domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7256 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7257 assert(dom && "Not an SSE instruction");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7258 const uint16_t *table = lookup(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7259 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7260 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7261 "256-bit vector operations only available in AVX2");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7262 table = lookupAVX2(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7263 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7264 assert(table && "Cannot change domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7265 MI.setDesc(get(table[Domain - 1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7266}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7267
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7268/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7269void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7270 NopInst.setOpcode(X86::NOOP);
7271}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7272
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7273// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7274// In particular, getJumpInstrTableEntryBound must always return an upper bound
7275// on the encoding lengths of the instructions generated by
7276// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7277void X86InstrInfo::getUnconditionalBranch(
7278 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7279 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]7280 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7281}
7282
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7283// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7284// In particular, getJumpInstrTableEntryBound must always return an upper bound
7285// on the encoding lengths of the instructions generated by
7286// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7287void X86InstrInfo::getTrap(MCInst &MI) const {
7288 MI.setOpcode(X86::TRAP);
7289}
7290
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7291// See getTrap and getUnconditionalBranch for conditions on the value returned
7292// by this function.
7293unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7294 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7295 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7296 return 5;
7297}
7298
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7299bool X86InstrInfo::isHighLatencyDef(int opc) const {
7300 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7301 default: return false;
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7302 case X86::DIVPDrm:
7303 case X86::DIVPDrr:
7304 case X86::DIVPSrm:
7305 case X86::DIVPSrr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7306 case X86::DIVSDrm:
7307 case X86::DIVSDrm_Int:
7308 case X86::DIVSDrr:
7309 case X86::DIVSDrr_Int:
7310 case X86::DIVSSrm:
7311 case X86::DIVSSrm_Int:
7312 case X86::DIVSSrr:
7313 case X86::DIVSSrr_Int:
7314 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7315 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7316 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7317 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7318 case X86::SQRTSDm:
7319 case X86::SQRTSDm_Int:
7320 case X86::SQRTSDr:
7321 case X86::SQRTSDr_Int:
7322 case X86::SQRTSSm:
7323 case X86::SQRTSSm_Int:
7324 case X86::SQRTSSr:
7325 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7326 // AVX instructions with high latency
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7327 case X86::VDIVPDrm:
7328 case X86::VDIVPDrr:
7329 case X86::VDIVPDYrm:
7330 case X86::VDIVPDYrr:
7331 case X86::VDIVPSrm:
7332 case X86::VDIVPSrr:
7333 case X86::VDIVPSYrm:
7334 case X86::VDIVPSYrr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7335 case X86::VDIVSDrm:
7336 case X86::VDIVSDrm_Int:
7337 case X86::VDIVSDrr:
7338 case X86::VDIVSDrr_Int:
7339 case X86::VDIVSSrm:
7340 case X86::VDIVSSrm_Int:
7341 case X86::VDIVSSrr:
7342 case X86::VDIVSSrr_Int:
7343 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7344 case X86::VSQRTPDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7345 case X86::VSQRTPDYm:
7346 case X86::VSQRTPDYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7347 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7348 case X86::VSQRTPSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7349 case X86::VSQRTPSYm:
7350 case X86::VSQRTPSYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7351 case X86::VSQRTSDm:
7352 case X86::VSQRTSDm_Int:
7353 case X86::VSQRTSDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7354 case X86::VSQRTSDr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7355 case X86::VSQRTSSm:
7356 case X86::VSQRTSSm_Int:
7357 case X86::VSQRTSSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7358 case X86::VSQRTSSr_Int:
7359 // AVX512 instructions with high latency
7360 case X86::VDIVPDZ128rm:
7361 case X86::VDIVPDZ128rmb:
7362 case X86::VDIVPDZ128rmbk:
7363 case X86::VDIVPDZ128rmbkz:
7364 case X86::VDIVPDZ128rmk:
7365 case X86::VDIVPDZ128rmkz:
7366 case X86::VDIVPDZ128rr:
7367 case X86::VDIVPDZ128rrk:
7368 case X86::VDIVPDZ128rrkz:
7369 case X86::VDIVPDZ256rm:
7370 case X86::VDIVPDZ256rmb:
7371 case X86::VDIVPDZ256rmbk:
7372 case X86::VDIVPDZ256rmbkz:
7373 case X86::VDIVPDZ256rmk:
7374 case X86::VDIVPDZ256rmkz:
7375 case X86::VDIVPDZ256rr:
7376 case X86::VDIVPDZ256rrk:
7377 case X86::VDIVPDZ256rrkz:
7378 case X86::VDIVPDZrb:
7379 case X86::VDIVPDZrbk:
7380 case X86::VDIVPDZrbkz:
7381 case X86::VDIVPDZrm:
7382 case X86::VDIVPDZrmb:
7383 case X86::VDIVPDZrmbk:
7384 case X86::VDIVPDZrmbkz:
7385 case X86::VDIVPDZrmk:
7386 case X86::VDIVPDZrmkz:
7387 case X86::VDIVPDZrr:
7388 case X86::VDIVPDZrrk:
7389 case X86::VDIVPDZrrkz:
7390 case X86::VDIVPSZ128rm:
7391 case X86::VDIVPSZ128rmb:
7392 case X86::VDIVPSZ128rmbk:
7393 case X86::VDIVPSZ128rmbkz:
7394 case X86::VDIVPSZ128rmk:
7395 case X86::VDIVPSZ128rmkz:
7396 case X86::VDIVPSZ128rr:
7397 case X86::VDIVPSZ128rrk:
7398 case X86::VDIVPSZ128rrkz:
7399 case X86::VDIVPSZ256rm:
7400 case X86::VDIVPSZ256rmb:
7401 case X86::VDIVPSZ256rmbk:
7402 case X86::VDIVPSZ256rmbkz:
7403 case X86::VDIVPSZ256rmk:
7404 case X86::VDIVPSZ256rmkz:
7405 case X86::VDIVPSZ256rr:
7406 case X86::VDIVPSZ256rrk:
7407 case X86::VDIVPSZ256rrkz:
7408 case X86::VDIVPSZrb:
7409 case X86::VDIVPSZrbk:
7410 case X86::VDIVPSZrbkz:
7411 case X86::VDIVPSZrm:
7412 case X86::VDIVPSZrmb:
7413 case X86::VDIVPSZrmbk:
7414 case X86::VDIVPSZrmbkz:
7415 case X86::VDIVPSZrmk:
7416 case X86::VDIVPSZrmkz:
7417 case X86::VDIVPSZrr:
7418 case X86::VDIVPSZrrk:
7419 case X86::VDIVPSZrrkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7420 case X86::VDIVSDZrm:
7421 case X86::VDIVSDZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7422 case X86::VDIVSDZrm_Int:
7423 case X86::VDIVSDZrm_Intk:
7424 case X86::VDIVSDZrm_Intkz:
7425 case X86::VDIVSDZrr_Int:
7426 case X86::VDIVSDZrr_Intk:
7427 case X86::VDIVSDZrr_Intkz:
7428 case X86::VDIVSDZrrb:
7429 case X86::VDIVSDZrrbk:
7430 case X86::VDIVSDZrrbkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7431 case X86::VDIVSSZrm:
7432 case X86::VDIVSSZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7433 case X86::VDIVSSZrm_Int:
7434 case X86::VDIVSSZrm_Intk:
7435 case X86::VDIVSSZrm_Intkz:
7436 case X86::VDIVSSZrr_Int:
7437 case X86::VDIVSSZrr_Intk:
7438 case X86::VDIVSSZrr_Intkz:
7439 case X86::VDIVSSZrrb:
7440 case X86::VDIVSSZrrbk:
7441 case X86::VDIVSSZrrbkz:
7442 case X86::VSQRTPDZ128m:
7443 case X86::VSQRTPDZ128mb:
7444 case X86::VSQRTPDZ128mbk:
7445 case X86::VSQRTPDZ128mbkz:
7446 case X86::VSQRTPDZ128mk:
7447 case X86::VSQRTPDZ128mkz:
7448 case X86::VSQRTPDZ128r:
7449 case X86::VSQRTPDZ128rk:
7450 case X86::VSQRTPDZ128rkz:
7451 case X86::VSQRTPDZ256m:
7452 case X86::VSQRTPDZ256mb:
7453 case X86::VSQRTPDZ256mbk:
7454 case X86::VSQRTPDZ256mbkz:
7455 case X86::VSQRTPDZ256mk:
7456 case X86::VSQRTPDZ256mkz:
7457 case X86::VSQRTPDZ256r:
7458 case X86::VSQRTPDZ256rk:
7459 case X86::VSQRTPDZ256rkz:
7460 case X86::VSQRTPDZm:
7461 case X86::VSQRTPDZmb:
7462 case X86::VSQRTPDZmbk:
7463 case X86::VSQRTPDZmbkz:
7464 case X86::VSQRTPDZmk:
7465 case X86::VSQRTPDZmkz:
7466 case X86::VSQRTPDZr:
7467 case X86::VSQRTPDZrb:
7468 case X86::VSQRTPDZrbk:
7469 case X86::VSQRTPDZrbkz:
7470 case X86::VSQRTPDZrk:
7471 case X86::VSQRTPDZrkz:
7472 case X86::VSQRTPSZ128m:
7473 case X86::VSQRTPSZ128mb:
7474 case X86::VSQRTPSZ128mbk:
7475 case X86::VSQRTPSZ128mbkz:
7476 case X86::VSQRTPSZ128mk:
7477 case X86::VSQRTPSZ128mkz:
7478 case X86::VSQRTPSZ128r:
7479 case X86::VSQRTPSZ128rk:
7480 case X86::VSQRTPSZ128rkz:
7481 case X86::VSQRTPSZ256m:
7482 case X86::VSQRTPSZ256mb:
7483 case X86::VSQRTPSZ256mbk:
7484 case X86::VSQRTPSZ256mbkz:
7485 case X86::VSQRTPSZ256mk:
7486 case X86::VSQRTPSZ256mkz:
7487 case X86::VSQRTPSZ256r:
7488 case X86::VSQRTPSZ256rk:
7489 case X86::VSQRTPSZ256rkz:
7490 case X86::VSQRTPSZm:
7491 case X86::VSQRTPSZmb:
7492 case X86::VSQRTPSZmbk:
7493 case X86::VSQRTPSZmbkz:
7494 case X86::VSQRTPSZmk:
7495 case X86::VSQRTPSZmkz:
7496 case X86::VSQRTPSZr:
7497 case X86::VSQRTPSZrb:
7498 case X86::VSQRTPSZrbk:
7499 case X86::VSQRTPSZrbkz:
7500 case X86::VSQRTPSZrk:
7501 case X86::VSQRTPSZrkz:
7502 case X86::VSQRTSDZm:
7503 case X86::VSQRTSDZm_Int:
7504 case X86::VSQRTSDZm_Intk:
7505 case X86::VSQRTSDZm_Intkz:
7506 case X86::VSQRTSDZr:
7507 case X86::VSQRTSDZr_Int:
7508 case X86::VSQRTSDZr_Intk:
7509 case X86::VSQRTSDZr_Intkz:
7510 case X86::VSQRTSDZrb_Int:
7511 case X86::VSQRTSDZrb_Intk:
7512 case X86::VSQRTSDZrb_Intkz:
7513 case X86::VSQRTSSZm:
7514 case X86::VSQRTSSZm_Int:
7515 case X86::VSQRTSSZm_Intk:
7516 case X86::VSQRTSSZm_Intkz:
7517 case X86::VSQRTSSZr:
7518 case X86::VSQRTSSZr_Int:
7519 case X86::VSQRTSSZr_Intk:
7520 case X86::VSQRTSSZr_Intkz:
7521 case X86::VSQRTSSZrb_Int:
7522 case X86::VSQRTSSZrb_Intk:
7523 case X86::VSQRTSSZrb_Intkz:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7524
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7525 case X86::VGATHERDPDYrm:
7526 case X86::VGATHERDPDZ128rm:
7527 case X86::VGATHERDPDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7528 case X86::VGATHERDPDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7529 case X86::VGATHERDPDrm:
7530 case X86::VGATHERDPSYrm:
7531 case X86::VGATHERDPSZ128rm:
7532 case X86::VGATHERDPSZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7533 case X86::VGATHERDPSZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7534 case X86::VGATHERDPSrm:
7535 case X86::VGATHERPF0DPDm:
7536 case X86::VGATHERPF0DPSm:
7537 case X86::VGATHERPF0QPDm:
7538 case X86::VGATHERPF0QPSm:
7539 case X86::VGATHERPF1DPDm:
7540 case X86::VGATHERPF1DPSm:
7541 case X86::VGATHERPF1QPDm:
7542 case X86::VGATHERPF1QPSm:
7543 case X86::VGATHERQPDYrm:
7544 case X86::VGATHERQPDZ128rm:
7545 case X86::VGATHERQPDZ256rm:
7546 case X86::VGATHERQPDZrm:
7547 case X86::VGATHERQPDrm:
7548 case X86::VGATHERQPSYrm:
7549 case X86::VGATHERQPSZ128rm:
7550 case X86::VGATHERQPSZ256rm:
7551 case X86::VGATHERQPSZrm:
7552 case X86::VGATHERQPSrm:
7553 case X86::VPGATHERDDYrm:
7554 case X86::VPGATHERDDZ128rm:
7555 case X86::VPGATHERDDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7556 case X86::VPGATHERDDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7557 case X86::VPGATHERDDrm:
7558 case X86::VPGATHERDQYrm:
7559 case X86::VPGATHERDQZ128rm:
7560 case X86::VPGATHERDQZ256rm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7561 case X86::VPGATHERDQZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7562 case X86::VPGATHERDQrm:
7563 case X86::VPGATHERQDYrm:
7564 case X86::VPGATHERQDZ128rm:
7565 case X86::VPGATHERQDZ256rm:
7566 case X86::VPGATHERQDZrm:
7567 case X86::VPGATHERQDrm:
7568 case X86::VPGATHERQQYrm:
7569 case X86::VPGATHERQQZ128rm:
7570 case X86::VPGATHERQQZ256rm:
7571 case X86::VPGATHERQQZrm:
7572 case X86::VPGATHERQQrm:
7573 case X86::VSCATTERDPDZ128mr:
7574 case X86::VSCATTERDPDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7575 case X86::VSCATTERDPDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7576 case X86::VSCATTERDPSZ128mr:
7577 case X86::VSCATTERDPSZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7578 case X86::VSCATTERDPSZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7579 case X86::VSCATTERPF0DPDm:
7580 case X86::VSCATTERPF0DPSm:
7581 case X86::VSCATTERPF0QPDm:
7582 case X86::VSCATTERPF0QPSm:
7583 case X86::VSCATTERPF1DPDm:
7584 case X86::VSCATTERPF1DPSm:
7585 case X86::VSCATTERPF1QPDm:
7586 case X86::VSCATTERPF1QPSm:
7587 case X86::VSCATTERQPDZ128mr:
7588 case X86::VSCATTERQPDZ256mr:
7589 case X86::VSCATTERQPDZmr:
7590 case X86::VSCATTERQPSZ128mr:
7591 case X86::VSCATTERQPSZ256mr:
7592 case X86::VSCATTERQPSZmr:
7593 case X86::VPSCATTERDDZ128mr:
7594 case X86::VPSCATTERDDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7595 case X86::VPSCATTERDDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7596 case X86::VPSCATTERDQZ128mr:
7597 case X86::VPSCATTERDQZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7598 case X86::VPSCATTERDQZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7599 case X86::VPSCATTERQDZ128mr:
7600 case X86::VPSCATTERQDZ256mr:
7601 case X86::VPSCATTERQDZmr:
7602 case X86::VPSCATTERQQZ128mr:
7603 case X86::VPSCATTERQQZ256mr:
7604 case X86::VPSCATTERQQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7605 return true;
7606 }
7607}
7608
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7609bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7610 const MachineRegisterInfo *MRI,
7611 const MachineInstr &DefMI,
7612 unsigned DefIdx,
7613 const MachineInstr &UseMI,
7614 unsigned UseIdx) const {
7615 return isHighLatencyDef(DefMI.getOpcode());
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7616}
7617
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7618bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7619 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7620 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7621 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7622
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7623 // Integer binary math/logic instructions have a third source operand:
7624 // the EFLAGS register. That operand must be both defined here and never
7625 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7626 // not change anything because rearranging the operands could affect other
7627 // instructions that depend on the exact status flags (zero, sign, etc.)
7628 // that are set by using these particular operands with this operation.
7629 if (Inst.getNumOperands() == 4) {
7630 assert(Inst.getOperand(3).isReg() &&
7631 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7632 "Unexpected operand in reassociable instruction");
7633 if (!Inst.getOperand(3).isDead())
7634 return false;
7635 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]7636
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7637 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7638}
7639
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7640// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7641// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7642// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7643// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7644bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7645 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7646 case X86::AND8rr:
7647 case X86::AND16rr:
7648 case X86::AND32rr:
7649 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]7650 case X86::OR8rr:
7651 case X86::OR16rr:
7652 case X86::OR32rr:
7653 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]7654 case X86::XOR8rr:
7655 case X86::XOR16rr:
7656 case X86::XOR32rr:
7657 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7658 case X86::IMUL16rr:
7659 case X86::IMUL32rr:
7660 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7661 case X86::PANDrr:
7662 case X86::PORrr:
7663 case X86::PXORrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]7664 case X86::ANDPDrr:
7665 case X86::ANDPSrr:
7666 case X86::ORPDrr:
7667 case X86::ORPSrr:
7668 case X86::XORPDrr:
7669 case X86::XORPSrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]7670 case X86::PADDBrr:
7671 case X86::PADDWrr:
7672 case X86::PADDDrr:
7673 case X86::PADDQrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7674 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7675 case X86::VPANDYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7676 case X86::VPANDDZ128rr:
7677 case X86::VPANDDZ256rr:
7678 case X86::VPANDDZrr:
7679 case X86::VPANDQZ128rr:
7680 case X86::VPANDQZ256rr:
7681 case X86::VPANDQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7682 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7683 case X86::VPORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7684 case X86::VPORDZ128rr:
7685 case X86::VPORDZ256rr:
7686 case X86::VPORDZrr:
7687 case X86::VPORQZ128rr:
7688 case X86::VPORQZ256rr:
7689 case X86::VPORQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7690 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7691 case X86::VPXORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7692 case X86::VPXORDZ128rr:
7693 case X86::VPXORDZ256rr:
7694 case X86::VPXORDZrr:
7695 case X86::VPXORQZ128rr:
7696 case X86::VPXORQZ256rr:
7697 case X86::VPXORQZrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]7698 case X86::VANDPDrr:
7699 case X86::VANDPSrr:
7700 case X86::VANDPDYrr:
7701 case X86::VANDPSYrr:
7702 case X86::VANDPDZ128rr:
7703 case X86::VANDPSZ128rr:
7704 case X86::VANDPDZ256rr:
7705 case X86::VANDPSZ256rr:
7706 case X86::VANDPDZrr:
7707 case X86::VANDPSZrr:
7708 case X86::VORPDrr:
7709 case X86::VORPSrr:
7710 case X86::VORPDYrr:
7711 case X86::VORPSYrr:
7712 case X86::VORPDZ128rr:
7713 case X86::VORPSZ128rr:
7714 case X86::VORPDZ256rr:
7715 case X86::VORPSZ256rr:
7716 case X86::VORPDZrr:
7717 case X86::VORPSZrr:
7718 case X86::VXORPDrr:
7719 case X86::VXORPSrr:
7720 case X86::VXORPDYrr:
7721 case X86::VXORPSYrr:
7722 case X86::VXORPDZ128rr:
7723 case X86::VXORPSZ128rr:
7724 case X86::VXORPDZ256rr:
7725 case X86::VXORPSZ256rr:
7726 case X86::VXORPDZrr:
7727 case X86::VXORPSZrr:
Craig Topper16a07442016-07-18 06:14:59 +0000[diff] [blame]7728 case X86::KADDBrr:
7729 case X86::KADDWrr:
7730 case X86::KADDDrr:
7731 case X86::KADDQrr:
7732 case X86::KANDBrr:
7733 case X86::KANDWrr:
7734 case X86::KANDDrr:
7735 case X86::KANDQrr:
7736 case X86::KORBrr:
7737 case X86::KORWrr:
7738 case X86::KORDrr:
7739 case X86::KORQrr:
7740 case X86::KXORBrr:
7741 case X86::KXORWrr:
7742 case X86::KXORDrr:
7743 case X86::KXORQrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]7744 case X86::VPADDBrr:
7745 case X86::VPADDWrr:
7746 case X86::VPADDDrr:
7747 case X86::VPADDQrr:
7748 case X86::VPADDBYrr:
7749 case X86::VPADDWYrr:
7750 case X86::VPADDDYrr:
7751 case X86::VPADDQYrr:
7752 case X86::VPADDBZ128rr:
7753 case X86::VPADDWZ128rr:
7754 case X86::VPADDDZ128rr:
7755 case X86::VPADDQZ128rr:
7756 case X86::VPADDBZ256rr:
7757 case X86::VPADDWZ256rr:
7758 case X86::VPADDDZ256rr:
7759 case X86::VPADDQZ256rr:
7760 case X86::VPADDBZrr:
7761 case X86::VPADDWZrr:
7762 case X86::VPADDDZrr:
7763 case X86::VPADDQZrr:
Craig Topper463f9492016-07-18 06:14:57 +0000[diff] [blame]7764 case X86::VPMULLWrr:
7765 case X86::VPMULLWYrr:
7766 case X86::VPMULLWZ128rr:
7767 case X86::VPMULLWZ256rr:
7768 case X86::VPMULLWZrr:
7769 case X86::VPMULLDrr:
7770 case X86::VPMULLDYrr:
7771 case X86::VPMULLDZ128rr:
7772 case X86::VPMULLDZ256rr:
7773 case X86::VPMULLDZrr:
7774 case X86::VPMULLQZ128rr:
7775 case X86::VPMULLQZ256rr:
7776 case X86::VPMULLQZrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7777 // Normal min/max instructions are not commutative because of NaN and signed
7778 // zero semantics, but these are. Thus, there's no need to check for global
7779 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7780 case X86::MAXCPDrr:
7781 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7782 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7783 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7784 case X86::MINCPDrr:
7785 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7786 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7787 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7788 case X86::VMAXCPDrr:
7789 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7790 case X86::VMAXCPDYrr:
7791 case X86::VMAXCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7792 case X86::VMAXCPDZ128rr:
7793 case X86::VMAXCPSZ128rr:
7794 case X86::VMAXCPDZ256rr:
7795 case X86::VMAXCPSZ256rr:
7796 case X86::VMAXCPDZrr:
7797 case X86::VMAXCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7798 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7799 case X86::VMAXCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7800 case X86::VMAXCSDZrr:
7801 case X86::VMAXCSSZrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7802 case X86::VMINCPDrr:
7803 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7804 case X86::VMINCPDYrr:
7805 case X86::VMINCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7806 case X86::VMINCPDZ128rr:
7807 case X86::VMINCPSZ128rr:
7808 case X86::VMINCPDZ256rr:
7809 case X86::VMINCPSZ256rr:
7810 case X86::VMINCPDZrr:
7811 case X86::VMINCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7812 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7813 case X86::VMINCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7814 case X86::VMINCSDZrr:
7815 case X86::VMINCSSZrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7816 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7817 case X86::ADDPDrr:
7818 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7819 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7820 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7821 case X86::MULPDrr:
7822 case X86::MULPSrr:
7823 case X86::MULSDrr:
7824 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7825 case X86::VADDPDrr:
7826 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7827 case X86::VADDPDYrr:
7828 case X86::VADDPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7829 case X86::VADDPDZ128rr:
7830 case X86::VADDPSZ128rr:
7831 case X86::VADDPDZ256rr:
7832 case X86::VADDPSZ256rr:
7833 case X86::VADDPDZrr:
7834 case X86::VADDPSZrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7835 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7836 case X86::VADDSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7837 case X86::VADDSDZrr:
7838 case X86::VADDSSZrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7839 case X86::VMULPDrr:
7840 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7841 case X86::VMULPDYrr:
7842 case X86::VMULPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7843 case X86::VMULPDZ128rr:
7844 case X86::VMULPSZ128rr:
7845 case X86::VMULPDZ256rr:
7846 case X86::VMULPSZ256rr:
7847 case X86::VMULPDZrr:
7848 case X86::VMULPSZrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7849 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7850 case X86::VMULSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7851 case X86::VMULSDZrr:
7852 case X86::VMULSSZrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7853 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7854 default:
7855 return false;
7856 }
7857}
7858
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7859/// This is an architecture-specific helper function of reassociateOps.
7860/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7861void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7862 MachineInstr &OldMI2,
7863 MachineInstr &NewMI1,
7864 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7865 // Integer instructions define an implicit EFLAGS source register operand as
7866 // the third source (fourth total) operand.
7867 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7868 return;
7869
7870 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7871 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7872
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7873 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7874 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7875 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7876 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7877
7878 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7879 "Must have dead EFLAGS operand in reassociable instruction");
7880 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7881 "Must have dead EFLAGS operand in reassociable instruction");
7882
7883 (void)OldOp1;
7884 (void)OldOp2;
7885
7886 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7887 "Unexpected operand in reassociable instruction");
7888 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7889 "Unexpected operand in reassociable instruction");
7890
7891 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7892 // of this pass or other passes. The EFLAGS operands must be dead in these new
7893 // instructions because the EFLAGS operands in the original instructions must
7894 // be dead in order for reassociation to occur.
7895 NewOp1.setIsDead();
7896 NewOp2.setIsDead();
7897}
7898
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7899std::pair<unsigned, unsigned>
7900X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7901 return std::make_pair(TF, 0u);
7902}
7903
7904ArrayRef<std::pair<unsigned, const char *>>
7905X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7906 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]7907 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7908 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7909 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7910 {MO_GOT, "x86-got"},
7911 {MO_GOTOFF, "x86-gotoff"},
7912 {MO_GOTPCREL, "x86-gotpcrel"},
7913 {MO_PLT, "x86-plt"},
7914 {MO_TLSGD, "x86-tlsgd"},
7915 {MO_TLSLD, "x86-tlsld"},
7916 {MO_TLSLDM, "x86-tlsldm"},
7917 {MO_GOTTPOFF, "x86-gottpoff"},
7918 {MO_INDNTPOFF, "x86-indntpoff"},
7919 {MO_TPOFF, "x86-tpoff"},
7920 {MO_DTPOFF, "x86-dtpoff"},
7921 {MO_NTPOFF, "x86-ntpoff"},
7922 {MO_GOTNTPOFF, "x86-gotntpoff"},
7923 {MO_DLLIMPORT, "x86-dllimport"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7924 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7925 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7926 {MO_TLVP, "x86-tlvp"},
7927 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7928 {MO_SECREL, "x86-secrel"}};
7929 return makeArrayRef(TargetFlags);
7930}
7931
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7932namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7933 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7934 /// global base register for x86-32.
7935 struct CGBR : public MachineFunctionPass {
7936 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]7937 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7938
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7939 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7940 const X86TargetMachine *TM =
7941 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7942 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7943
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7944 // Don't do anything if this is 64-bit as 64-bit PIC
7945 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7946 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7947 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7948
7949 // Only emit a global base reg in PIC mode.
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]7950 if (!TM->isPositionIndependent())
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7951 return false;
7952
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7953 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7954 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7955
7956 // If we didn't need a GlobalBaseReg, don't insert code.
7957 if (GlobalBaseReg == 0)
7958 return false;
7959
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7960 // Insert the set of GlobalBaseReg into the first MBB of the function
7961 MachineBasicBlock &FirstMBB = MF.front();
7962 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7963 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7964 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7965 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7966
7967 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7968 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]7969 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7970 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7971 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7972
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7973 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7974 // only used in JIT code emission as displacement to pc.
7975 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7976
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7977 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7978 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7979 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7980 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7981 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7982 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7983 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7984 }
7985
7986 return true;
7987 }
7988
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7989 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7990 return "X86 PIC Global Base Reg Initialization";
7991 }
7992
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7993 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7994 AU.setPreservesCFG();
7995 MachineFunctionPass::getAnalysisUsage(AU);
7996 }
7997 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7998}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7999
8000char CGBR::ID = 0;
8001FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]8002llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8003
8004namespace {
8005 struct LDTLSCleanup : public MachineFunctionPass {
8006 static char ID;
8007 LDTLSCleanup() : MachineFunctionPass(ID) {}
8008
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8009 bool runOnMachineFunction(MachineFunction &MF) override {
Andrew Kaylor2bee5ef2016-04-26 21:44:24 +0000[diff] [blame]8010 if (skipFunction(*MF.getFunction()))
8011 return false;
8012
8013 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8014 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8015 // No point folding accesses if there isn't at least two.
8016 return false;
8017 }
8018
8019 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8020 return VisitNode(DT->getRootNode(), 0);
8021 }
8022
8023 // Visit the dominator subtree rooted at Node in pre-order.
8024 // If TLSBaseAddrReg is non-null, then use that to replace any
8025 // TLS_base_addr instructions. Otherwise, create the register
8026 // when the first such instruction is seen, and then use it
8027 // as we encounter more instructions.
8028 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8029 MachineBasicBlock *BB = Node->getBlock();
8030 bool Changed = false;
8031
8032 // Traverse the current block.
8033 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8034 ++I) {
8035 switch (I->getOpcode()) {
8036 case X86::TLS_base_addr32:
8037 case X86::TLS_base_addr64:
8038 if (TLSBaseAddrReg)
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8039 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8040 else
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8041 I = SetRegister(*I, &TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8042 Changed = true;
8043 break;
8044 default:
8045 break;
8046 }
8047 }
8048
8049 // Visit the children of this block in the dominator tree.
8050 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8051 I != E; ++I) {
8052 Changed |= VisitNode(*I, TLSBaseAddrReg);
8053 }
8054
8055 return Changed;
8056 }
8057
8058 // Replace the TLS_base_addr instruction I with a copy from
8059 // TLSBaseAddrReg, returning the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8060 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8061 unsigned TLSBaseAddrReg) {
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8062 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8063 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8064 const bool is64Bit = STI.is64Bit();
8065 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8066
8067 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8068 MachineInstr *Copy =
8069 BuildMI(*I.getParent(), I, I.getDebugLoc(),
8070 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8071 .addReg(TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8072
8073 // Erase the TLS_base_addr instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8074 I.eraseFromParent();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8075
8076 return Copy;
8077 }
8078
8079 // Create a virtal register in *TLSBaseAddrReg, and populate it by
8080 // inserting a copy instruction after I. Returns the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8081 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8082 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8083 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8084 const bool is64Bit = STI.is64Bit();
8085 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8086
8087 // Create a virtual register for the TLS base address.
8088 MachineRegisterInfo &RegInfo = MF->getRegInfo();
8089 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8090 ? &X86::GR64RegClass
8091 : &X86::GR32RegClass);
8092
8093 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8094 MachineInstr *Next = I.getNextNode();
8095 MachineInstr *Copy =
8096 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8097 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8098 .addReg(is64Bit ? X86::RAX : X86::EAX);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8099
8100 return Copy;
8101 }
8102
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8103 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8104 return "Local Dynamic TLS Access Clean-up";
8105 }
8106
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8107 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8108 AU.setPreservesCFG();
8109 AU.addRequired<MachineDominatorTree>();
8110 MachineFunctionPass::getAnalysisUsage(AU);
8111 }
8112 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8113}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8114
8115char LDTLSCleanup::ID = 0;
8116FunctionPass*
8117llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }