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gerrit-public.fairphone.software / toolchain / llvm-project / ba9b93d7f2badb8b7686f8bf3ca9aa983b016eaf / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 520981892bf65ff2c890a4983636c320c70bdacf [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]21#include "llvm/CodeGen/LivePhysRegs.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]22#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]27#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]28#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]29#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]31#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]32#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]33#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]34#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]35#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]36#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]37#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]40#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]61static cl::opt<unsigned>
62PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67static cl::opt<unsigned>
68UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
71 cl::init(64), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]72
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]73enum {
74 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]75 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]79 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]80 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]104};
105
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]106struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]107 uint16_t RegOp;
108 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]109 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]110};
111
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]112// Pin the vtable to this file.
113void X86InstrInfo::anchor() {}
114
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]115X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
Dean Michael Berris52735fc2016-07-14 04:06:33 +0000[diff] [blame]120 X86::CATCHRET,
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]122 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]123
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]124 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
133 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
134 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
136 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
139 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
140 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
142 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
145 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
146 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
148 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16rCL, X86::SHL16mCL, 0 },
232 { X86::SHL16ri, X86::SHL16mi, 0 },
233 { X86::SHL32rCL, X86::SHL32mCL, 0 },
234 { X86::SHL32ri, X86::SHL32mi, 0 },
235 { X86::SHL64rCL, X86::SHL64mCL, 0 },
236 { X86::SHL64ri, X86::SHL64mi, 0 },
237 { X86::SHL8rCL, X86::SHL8mCL, 0 },
238 { X86::SHL8ri, X86::SHL8mi, 0 },
239 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
240 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
241 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
242 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
243 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
244 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
245 { X86::SHR16r1, X86::SHR16m1, 0 },
246 { X86::SHR16rCL, X86::SHR16mCL, 0 },
247 { X86::SHR16ri, X86::SHR16mi, 0 },
248 { X86::SHR32r1, X86::SHR32m1, 0 },
249 { X86::SHR32rCL, X86::SHR32mCL, 0 },
250 { X86::SHR32ri, X86::SHR32mi, 0 },
251 { X86::SHR64r1, X86::SHR64m1, 0 },
252 { X86::SHR64rCL, X86::SHR64mCL, 0 },
253 { X86::SHR64ri, X86::SHR64mi, 0 },
254 { X86::SHR8r1, X86::SHR8m1, 0 },
255 { X86::SHR8rCL, X86::SHR8mCL, 0 },
256 { X86::SHR8ri, X86::SHR8mi, 0 },
257 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
258 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
259 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
260 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
261 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
262 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
263 { X86::SUB16ri, X86::SUB16mi, 0 },
264 { X86::SUB16ri8, X86::SUB16mi8, 0 },
265 { X86::SUB16rr, X86::SUB16mr, 0 },
266 { X86::SUB32ri, X86::SUB32mi, 0 },
267 { X86::SUB32ri8, X86::SUB32mi8, 0 },
268 { X86::SUB32rr, X86::SUB32mr, 0 },
269 { X86::SUB64ri32, X86::SUB64mi32, 0 },
270 { X86::SUB64ri8, X86::SUB64mi8, 0 },
271 { X86::SUB64rr, X86::SUB64mr, 0 },
272 { X86::SUB8ri, X86::SUB8mi, 0 },
273 { X86::SUB8rr, X86::SUB8mr, 0 },
274 { X86::XOR16ri, X86::XOR16mi, 0 },
275 { X86::XOR16ri8, X86::XOR16mi8, 0 },
276 { X86::XOR16rr, X86::XOR16mr, 0 },
277 { X86::XOR32ri, X86::XOR32mi, 0 },
278 { X86::XOR32ri8, X86::XOR32mi8, 0 },
279 { X86::XOR32rr, X86::XOR32mr, 0 },
280 { X86::XOR64ri32, X86::XOR64mi32, 0 },
281 { X86::XOR64ri8, X86::XOR64mi8, 0 },
282 { X86::XOR64rr, X86::XOR64mr, 0 },
283 { X86::XOR8ri, X86::XOR8mi, 0 },
284 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]285 };
286
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]287 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]289 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]290 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]291 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]292 }
293
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]294 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]295 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
296 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
297 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
298 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
299 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]300 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
301 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
302 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
303 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
304 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
305 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
306 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
307 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
308 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
309 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
310 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
311 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
312 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
313 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
314 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]315 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]316 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
317 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
318 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
319 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
320 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
321 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
322 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
323 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
324 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
325 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
326 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
327 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
328 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
329 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
330 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
331 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
332 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
333 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
334 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
336 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
337 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
339 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
340 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
341 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
342 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
343 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]344 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
345 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
346 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
347 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]348 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
349 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]350 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
351 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
352 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]353 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
354 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
355 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
356 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
357 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
358 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
359 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
360 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
361 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
362 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
363 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
364 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
365 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
366 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
367 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
368 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
369 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
370 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]371 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]372 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
373 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
374 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]375 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]378 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]379 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]380 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
382 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
383 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
384 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
386 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
387 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]389 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
390 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]391
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]392 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]393 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]394 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]398 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]399
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]400 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]401 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
403 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
404 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
405 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
406 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]408 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]410 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]411 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]412
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]413 // AVX-512 foldable instructions (256-bit versions)
414 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
415 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
416 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
417 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
418 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
423 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]424
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]425 // AVX-512 foldable instructions (128-bit versions)
426 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
427 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
428 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
429 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
430 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
431 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
432 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
433 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
434 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]435 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]436
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]437 // F16C foldable instructions
438 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
439 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]440 };
441
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]442 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]443 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]445 }
446
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]447 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]448 { X86::BSF16rr, X86::BSF16rm, 0 },
449 { X86::BSF32rr, X86::BSF32rm, 0 },
450 { X86::BSF64rr, X86::BSF64rm, 0 },
451 { X86::BSR16rr, X86::BSR16rm, 0 },
452 { X86::BSR32rr, X86::BSR32rm, 0 },
453 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]454 { X86::CMP16rr, X86::CMP16rm, 0 },
455 { X86::CMP32rr, X86::CMP32rm, 0 },
456 { X86::CMP64rr, X86::CMP64rm, 0 },
457 { X86::CMP8rr, X86::CMP8rm, 0 },
458 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
459 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
460 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
461 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
462 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
463 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
464 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
465 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
466 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
467 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]468 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
469 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
470 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
471 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
472 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
473 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
474 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
475 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]476 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
477 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]478 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
479 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]480 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]481 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]482 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]483 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]484 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]485 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]486 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
487 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
488 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
489 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
490 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
491 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
492 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
493 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]494 { X86::MOV16rr, X86::MOV16rm, 0 },
495 { X86::MOV32rr, X86::MOV32rm, 0 },
496 { X86::MOV64rr, X86::MOV64rm, 0 },
497 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
498 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
499 { X86::MOV8rr, X86::MOV8rm, 0 },
500 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
501 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]502 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
503 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
504 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
505 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]506 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
507 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
508 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
509 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
510 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
511 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
512 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
513 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
514 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
515 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]516 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
517 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
518 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
519 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
520 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]521 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
522 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
523 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]524 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
525 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
526 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
527 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
528 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
529 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
530 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
531 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
532 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
533 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
534 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
535 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
536 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
537 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
538 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
539 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
540 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]541 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
542 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
543 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]544 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]545 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]546 { X86::RCPSSr, X86::RCPSSm, 0 },
547 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]548 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
549 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]550 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]551 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
552 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
553 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]554 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]555 { X86::SQRTSDr, X86::SQRTSDm, 0 },
556 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
557 { X86::SQRTSSr, X86::SQRTSSm, 0 },
558 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
559 { X86::TEST16rr, X86::TEST16rm, 0 },
560 { X86::TEST32rr, X86::TEST32rm, 0 },
561 { X86::TEST64rr, X86::TEST64rm, 0 },
562 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]563 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]564 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
565 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]566
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]567 // MMX version of foldable instructions
568 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
569 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
570 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
571 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
572 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
573 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
574 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
575 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
576 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
577 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
578
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]579 // 3DNow! version of foldable instructions
580 { X86::PF2IDrr, X86::PF2IDrm, 0 },
581 { X86::PF2IWrr, X86::PF2IWrm, 0 },
582 { X86::PFRCPrr, X86::PFRCPrm, 0 },
583 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
584 { X86::PI2FDrr, X86::PI2FDrm, 0 },
585 { X86::PI2FWrr, X86::PI2FWrm, 0 },
586 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
587
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]588 // AVX 128-bit versions of foldable instructions
589 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
590 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]591 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
592 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]593 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
594 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]595 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]596 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
597 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
598 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
600 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
601 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
602 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
603 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
604 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]605 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]606 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]607 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]608 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]609 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]610 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]611 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
612 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]613 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
614 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
615 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
616 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
617 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
618 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
619 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
620 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]621 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
622 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]623 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]624 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]625 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]626 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
627 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
628 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]629 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
630 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
631 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
632 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
633 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]634 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
635 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]636 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
637 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
638 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
639 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
640 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
641 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
642 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
643 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
644 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
645 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
646 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
647 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]648 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
649 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
650 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]651 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]652 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]653 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
654 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]655 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]656 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]657 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]658 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
659 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]660 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]661 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]662
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]663 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]664 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]665 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]666 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]667 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]668 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]669 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]670 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
671 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]672 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
673 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]674 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]675 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]676 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
677 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]678 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]679 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]680 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
681 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]682 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]683 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]684 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
685 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]686 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
687 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
688 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]689 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
690 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]691
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]692 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]693
694 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]699 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
700 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
701 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]702 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
703 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
704 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]705 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
706 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
707 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
708 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
709 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
710 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
711 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
712 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
713 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
714 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
715 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
716 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
717 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
718 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
719 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
720 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
721 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
722 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
723 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
724 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
725 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
726 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]727 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
728 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
729 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]730
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]731 // XOP foldable instructions
732 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
733 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
734 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
735 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
736 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
737 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
738 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
739 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
740 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
741 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
742 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
743 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
744 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
745 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
746 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
747 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
748 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
749 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
750 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
751 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
752 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
753 { X86::VPROTBri, X86::VPROTBmi, 0 },
754 { X86::VPROTBrr, X86::VPROTBmr, 0 },
755 { X86::VPROTDri, X86::VPROTDmi, 0 },
756 { X86::VPROTDrr, X86::VPROTDmr, 0 },
757 { X86::VPROTQri, X86::VPROTQmi, 0 },
758 { X86::VPROTQrr, X86::VPROTQmr, 0 },
759 { X86::VPROTWri, X86::VPROTWmi, 0 },
760 { X86::VPROTWrr, X86::VPROTWmr, 0 },
761 { X86::VPSHABrr, X86::VPSHABmr, 0 },
762 { X86::VPSHADrr, X86::VPSHADmr, 0 },
763 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
764 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
765 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
766 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
767 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
768 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
769
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]770 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]771 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
772 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]773 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
774 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
775 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
776 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
777 { X86::BLCI32rr, X86::BLCI32rm, 0 },
778 { X86::BLCI64rr, X86::BLCI64rm, 0 },
779 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
780 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
781 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
782 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
783 { X86::BLCS32rr, X86::BLCS32rm, 0 },
784 { X86::BLCS64rr, X86::BLCS64rm, 0 },
785 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
786 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]787 { X86::BLSI32rr, X86::BLSI32rm, 0 },
788 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]789 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
790 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]791 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
792 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
793 { X86::BLSR32rr, X86::BLSR32rm, 0 },
794 { X86::BLSR64rr, X86::BLSR64rm, 0 },
795 { X86::BZHI32rr, X86::BZHI32rm, 0 },
796 { X86::BZHI64rr, X86::BZHI64rm, 0 },
797 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
798 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
799 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
800 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
801 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
802 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]803 { X86::RORX32ri, X86::RORX32mi, 0 },
804 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]805 { X86::SARX32rr, X86::SARX32rm, 0 },
806 { X86::SARX64rr, X86::SARX64rm, 0 },
807 { X86::SHRX32rr, X86::SHRX32rm, 0 },
808 { X86::SHRX64rr, X86::SHRX64rm, 0 },
809 { X86::SHLX32rr, X86::SHLX32rm, 0 },
810 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]811 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
812 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]813 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
814 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
815 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]816 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
817 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]818
819 // AVX-512 foldable instructions
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]820 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
821 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
822 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
823 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
824 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
825 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
826 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
827 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
828 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
829 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
830 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
831 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
832 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
833 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
834 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
835 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
837 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]838
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]839 // AVX-512 foldable instructions (256-bit versions)
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]840 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
841 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
842 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
843 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
844 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
845 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
846 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
847 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
848 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
849 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
850 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
851 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
852 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
853 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]854
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]855 // AVX-512 foldable instructions (128-bit versions)
856 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
857 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
858 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
859 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
860 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
861 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
862 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
863 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
864 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
865 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
866 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
867 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]868 // F16C foldable instructions
869 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
870 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]871
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]872 // AES foldable instructions
873 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
874 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]875 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
876 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]877 };
878
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]879 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]880 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]881 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]882 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]883 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]884 }
885
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]886 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]887 { X86::ADC32rr, X86::ADC32rm, 0 },
888 { X86::ADC64rr, X86::ADC64rm, 0 },
889 { X86::ADD16rr, X86::ADD16rm, 0 },
890 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
891 { X86::ADD32rr, X86::ADD32rm, 0 },
892 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
893 { X86::ADD64rr, X86::ADD64rm, 0 },
894 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
895 { X86::ADD8rr, X86::ADD8rm, 0 },
896 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
897 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
898 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]899 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]900 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]901 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]902 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
903 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
904 { X86::AND16rr, X86::AND16rm, 0 },
905 { X86::AND32rr, X86::AND32rm, 0 },
906 { X86::AND64rr, X86::AND64rm, 0 },
907 { X86::AND8rr, X86::AND8rm, 0 },
908 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
909 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
910 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
911 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]912 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
913 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
914 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
915 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]916 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
917 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
918 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
919 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
920 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
921 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
922 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
923 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
924 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
925 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
926 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
927 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
928 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
929 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
930 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
931 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
932 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
933 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
934 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
935 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
936 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
937 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
938 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
939 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
940 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
941 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
942 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
943 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
944 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
945 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
946 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
947 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
948 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
949 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
950 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
951 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
952 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
953 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
954 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
955 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
956 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
957 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
958 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
959 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
960 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
961 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
962 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
963 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
964 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
965 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
966 { X86::CMPSDrr, X86::CMPSDrm, 0 },
967 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]968 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
969 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]970 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
971 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
972 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]973 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]974 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]975 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
976 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
977 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]978
Sanjay Patel8c13e362015-07-28 00:48:32 +0000[diff] [blame]979 // Do not fold Fs* scalar logical op loads because there are no scalar
980 // load variants for these instructions. When folded, the load is required
981 // to be 128-bits, so the load size would not match.
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]982
983 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
984 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
985 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
986 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
987 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
988 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
989 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
990 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]991 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
992 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
993 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
994 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
995 { X86::IMUL16rr, X86::IMUL16rm, 0 },
996 { X86::IMUL32rr, X86::IMUL32rm, 0 },
997 { X86::IMUL64rr, X86::IMUL64rm, 0 },
998 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
999 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]1000 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
1001 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1002 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1003 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1004 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1005 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1006 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1008 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1009 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1010 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1011 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1012 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1013 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1014 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1015 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1016 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1017 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1018 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1019 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1020 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1021 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1022 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1023 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1024 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1025 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1026 { X86::OR16rr, X86::OR16rm, 0 },
1027 { X86::OR32rr, X86::OR32rm, 0 },
1028 { X86::OR64rr, X86::OR64rm, 0 },
1029 { X86::OR8rr, X86::OR8rm, 0 },
1030 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1031 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1032 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1033 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1034 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1035 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1036 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1037 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1038 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1039 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1040 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1041 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1042 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1043 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1044 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1045 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1046 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1047 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1048 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1049 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1050 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1051 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1052 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1053 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1054 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1055 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1056 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1057 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1058 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1059 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1060 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1061 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1062 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1063 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1064 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1065 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1066 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1067 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1068 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1069 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1070 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1071 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1072 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1073 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1074 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1075 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1076 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1077 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1078 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1079 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1080 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1081 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1082 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1083 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1084 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1085 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1086 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1087 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1088 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1089 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1090 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1091 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1092 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1093 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1094 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1095 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1096 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1097 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1098 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1099 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1100 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1101 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1102 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1103 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1104 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1105 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1106 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1107 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1108 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1109 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1110 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1111 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1112 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1113 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1114 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1115 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1116 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1117 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1118 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1119 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1120 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1121 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1122 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1123 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1124 { X86::SBB32rr, X86::SBB32rm, 0 },
1125 { X86::SBB64rr, X86::SBB64rm, 0 },
1126 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1127 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1128 { X86::SUB16rr, X86::SUB16rm, 0 },
1129 { X86::SUB32rr, X86::SUB32rm, 0 },
1130 { X86::SUB64rr, X86::SUB64rm, 0 },
1131 { X86::SUB8rr, X86::SUB8rm, 0 },
1132 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1133 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1134 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1135 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1136 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1137 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1138 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1139 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1140 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1141 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1142 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1143 { X86::XOR16rr, X86::XOR16rm, 0 },
1144 { X86::XOR32rr, X86::XOR32rm, 0 },
1145 { X86::XOR64rr, X86::XOR64rm, 0 },
1146 { X86::XOR8rr, X86::XOR8rm, 0 },
1147 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1148 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1149
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1150 // MMX version of foldable instructions
1151 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1152 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1153 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1154 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1155 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1156 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1157 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1158 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1159 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1160 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1161 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1162 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1163 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1164 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1165 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1166 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1167 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1168 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1169 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1170 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1171 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1172 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1173 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1174 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1175 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1176 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1177 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1178 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1179 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1180 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1181 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1182 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1183 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1184 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1185 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1186 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1187 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1188 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1189 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1190 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1191 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1192 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1193 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1194 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1195 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1196 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1197 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1198 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1199 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1200 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1201 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1202 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1203 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1204 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1205 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1206 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1207 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1208 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1209 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1210 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1211 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1212 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1213 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1214 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1215 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1216 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1217 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1218 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1219 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1220 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1221
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1222 // 3DNow! version of foldable instructions
1223 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1224 { X86::PFACCrr, X86::PFACCrm, 0 },
1225 { X86::PFADDrr, X86::PFADDrm, 0 },
1226 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1227 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1228 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1229 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1230 { X86::PFMINrr, X86::PFMINrm, 0 },
1231 { X86::PFMULrr, X86::PFMULrm, 0 },
1232 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1233 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1234 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1235 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1236 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1237 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1238 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1239 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1240
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1241 // AVX 128-bit versions of foldable instructions
1242 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1243 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1244 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1245 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1246 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1247 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1248 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1249 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1250 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1251 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1252 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1253 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1254 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1255 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1256 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1257 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1258 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1259 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1260 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1261 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1262 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1263 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1264 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1265 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1266 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1267 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1268 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1269 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1270 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1271 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1272 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1273 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1274 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1275 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1276 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1277 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1278 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1279 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1280 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1281 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1282 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1283 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1284 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1285 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1286 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1287 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1288 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1289 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]1290 // Do not fold VFs* loads because there are no scalar load variants for
1291 // these instructions. When folded, the load is required to be 128-bits, so
1292 // the load size would not match.
1293 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1294 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1295 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1296 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1297 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1298 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1299 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1300 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1301 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1302 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1303 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1304 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1305 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1306 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1307 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1308 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1309 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1310 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1311 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1312 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1313 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1314 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1315 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1316 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1317 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1318 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1319 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1320 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1321 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1322 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1323 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1324 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1325 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1326 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1327 { X86::VORPDrr, X86::VORPDrm, 0 },
1328 { X86::VORPSrr, X86::VORPSrm, 0 },
1329 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1330 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1331 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1332 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1333 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1334 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1335 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1336 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1337 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1338 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1339 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1340 { X86::VPADDWrr, X86::VPADDWrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1341 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1342 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1343 { X86::VPANDrr, X86::VPANDrm, 0 },
1344 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1345 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1346 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1347 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1348 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1349 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1350 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1351 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1352 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1353 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1354 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1355 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1356 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1357 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1358 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1359 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1360 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1361 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1362 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1363 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1364 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1365 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1366 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1367 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1368 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1369 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1370 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1371 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1372 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1373 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1374 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1375 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1376 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1377 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1378 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1379 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1380 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1381 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1382 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1383 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1384 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1385 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1386 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1387 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1388 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1389 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1390 { X86::VPORrr, X86::VPORrm, 0 },
1391 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1392 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1393 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1394 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1395 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1396 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1397 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1398 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1399 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1400 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1401 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1402 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1403 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1404 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1405 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1406 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1407 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1408 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1409 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1410 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1411 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1412 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1413 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1414 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1415 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1416 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1417 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1418 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1419 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1420 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1421 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1422 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1423 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1424 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1425 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1426 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1427 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1428 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1429 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1430 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1431 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1432 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1433 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1434 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1435 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1436 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1437
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1438 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1439 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1440 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1441 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1442 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1443 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1444 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1445 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1446 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1447 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1448 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1449 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1450 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1451 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1452 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1453 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1454 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1455 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1456 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1457 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1458 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1459 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1460 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1461 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1462 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1463 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1464 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1465 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1466 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1467 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1468 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1469 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1470 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1471 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1472 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1473 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1474 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1475 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1476 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1477 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1478 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1479 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1480 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1481 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1482
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1483 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1484 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1485 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1486 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1487 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1488 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1489 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1490 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1491 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1492 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1493 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1494 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1495 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1496 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1497 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1498 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1499 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1500 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1501 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1502 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1503 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1504 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1505 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1506 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1507 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1508 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1509 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1510 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1511 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1512 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1513 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1514 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1515 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1516 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1517 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1518 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1519 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1520 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1521 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1522 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1523 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1524 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1525 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1526 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1527 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1528 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1529 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1530 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1531 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1532 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1533 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1534 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1535 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1536 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1537 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1538 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1539 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1540 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1541 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1542 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1543 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1544 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1545 { X86::VPORYrr, X86::VPORYrm, 0 },
1546 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1547 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1548 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1549 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1550 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1551 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1552 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1553 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1554 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1555 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1556 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1557 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1558 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1559 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1560 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1561 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
Igor Bregere59165c2016-06-20 07:05:43 +0000[diff] [blame]1562 { X86::VPSRAVD_Intrr, X86::VPSRAVD_Intrm, 0 },
1563 { X86::VPSRAVD_IntYrr, X86::VPSRAVD_IntYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1564 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1565 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1566 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1567 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1568 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1569 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1570 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1571 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1572 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1573 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1574 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1575 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1576 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1577 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1578 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1579 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1580 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1581 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1582 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1583 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1584 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1585 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1586 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1587 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1588
1589 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1590 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1591 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1592 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1593 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1594 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1595 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1596 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1597 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1598 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1599 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1600 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1601 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1602 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1603 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1604 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1605 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1606 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1607 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1608 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1609 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1610 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1611 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1612 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1613 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1614 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1615 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1616 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1617 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1618 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1619 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1620 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1621 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1622
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1623 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1624 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1625 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1626 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1627 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1628 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1629 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1630 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1631 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1632 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1633 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1634 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1635 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1636 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1637 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1638 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1639 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1640 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1641 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1642 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1643 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1644 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1645 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1646 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1647 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1648 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1649 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1650 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1651 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1652 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1653 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1654 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1655 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1656 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1657 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1658 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1659 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1660 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1661 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1662 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1663
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1664 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1665 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1666 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1667 { X86::MULX32rr, X86::MULX32rm, 0 },
1668 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1669 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1670 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1671 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1672 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1673
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1674 // ADX foldable instructions
1675 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1676 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1677 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1678 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1679
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1680 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1681 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1682 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1683 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1684 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1685 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1686 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1687 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1688 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1689 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1690 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1691 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1692 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1693 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1694 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1695 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1696 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1697 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1698 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1699 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1700 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1701 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1702 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1703 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1704 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1705 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1706 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1707 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1708 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1709 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1710 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1711 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1712 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1713 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1714 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1715 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1716 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1717 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1718 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1719 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1720
1721 // AVX-512{F,VL} foldable instructions
1722 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1723 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1724 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1725
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1726 // AVX-512{F,VL} foldable instructions
1727 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1728 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1729 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1730 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1731
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1732 // AES foldable instructions
1733 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1734 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1735 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1736 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1737 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1738 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1739 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1740 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1741
1742 // SHA foldable instructions
1743 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1744 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1745 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1746 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1747 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1748 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1749 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1750 };
1751
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1752 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1753 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1754 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1755 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1756 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1757 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1758
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1759 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1760 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1761 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1762 { X86::VFMADDSSr231r_Int, X86::VFMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1763 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1764 { X86::VFMADDSDr231r_Int, X86::VFMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1765 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1766 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1767 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1768 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1769 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1770 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1771 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1772 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1773
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1774 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1775 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1776 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1777 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1778 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1779 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1780 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1781 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1782 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1783 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1784 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1785 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1786
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1787 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1788 { X86::VFNMADDSSr231r_Int, X86::VFNMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1789 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1790 { X86::VFNMADDSDr231r_Int, X86::VFNMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1791 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1792 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1793 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1794 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1795 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1796 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1797 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1798 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1799
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1800 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1801 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1802 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1803 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1804 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1805 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1806 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1807 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1808 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1809 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1810 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1811 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1812
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1813 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1814 { X86::VFMSUBSSr231r_Int, X86::VFMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1815 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1816 { X86::VFMSUBSDr231r_Int, X86::VFMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1817 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1818 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1819 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1820 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1821 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1822 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1823 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1824 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1825
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1826 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1827 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1828 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1829 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1830 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1831 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1832 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1833 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1834 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1835 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1836 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1837 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1838
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1839 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1840 { X86::VFNMSUBSSr231r_Int, X86::VFNMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1841 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1842 { X86::VFNMSUBSDr231r_Int, X86::VFNMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1843 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1844 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1845 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1846 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1847 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1848 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1849 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1850 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1851
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1852 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1853 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1854 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1855 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1856 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1857 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1858 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1859 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1860 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1861 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1862 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1863 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1864
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1865 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1866 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1867 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1868 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1869 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1870 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1871 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1872 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1873 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1874 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1875 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1876 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1877
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1878 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1879 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1880 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1881 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1882 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1883 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1884 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1885 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1886 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1887 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1888 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1889 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1890
1891 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1892 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1893 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1894 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1895 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1896 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1897 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1898 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1899 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1900 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1901 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1902 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1903 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1904 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1905 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1906 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1907 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1908 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1909 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1910 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1911 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1912 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1913 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1914 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1915 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1916 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1917 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1918 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1919 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1920 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1921 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1922 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1923 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1924
1925 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1926 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
1927 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1928 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1929 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1930 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1931 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1932 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1933
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1934 // AVX-512 VPERMI instructions with 3 source operands.
1935 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1936 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1937 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1938 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1939 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1940 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1941 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1942 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1943 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1944 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1945 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1946 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1947 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1948 // AVX-512 arithmetic instructions
1949 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1950 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1951 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1952 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1953 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1954 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1955 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1956 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1957 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1958 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1959 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1960 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1961 // AVX-512{F,VL} arithmetic instructions 256-bit
1962 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1963 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1964 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1965 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1966 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1967 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1968 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1969 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1970 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1971 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1972 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1973 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1974 // AVX-512{F,VL} arithmetic instructions 128-bit
1975 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1976 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1977 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1978 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1979 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1980 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1981 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1982 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1983 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1984 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1985 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1986 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1987 };
1988
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1989 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1990 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1991 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1992 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1993 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1994 }
1995
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1996 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1997 // AVX-512 foldable instructions
1998 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1999 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
2000 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2001 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2002 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2003 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2004 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2005 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2006 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2007 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
2008 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2009 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
2010 // AVX-512{F,VL} foldable instructions 256-bit
2011 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2012 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2013 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2014 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2015 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2016 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2017 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2018 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2019 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2020 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2021 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2022 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2023 // AVX-512{F,VL} foldable instructions 128-bit
2024 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2025 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2026 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2027 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2028 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2029 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2030 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2031 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2032 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2033 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2034 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2035 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2036 };
2037
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2038 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2039 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2040 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2041 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2042 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2043 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2044}
2045
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2046void
2047X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2048 MemOp2RegOpTableType &M2RTable,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]2049 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2050 if ((Flags & TB_NO_FORWARD) == 0) {
2051 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2052 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2053 }
2054 if ((Flags & TB_NO_REVERSE) == 0) {
2055 assert(!M2RTable.count(MemOp) &&
2056 "Duplicated entries in unfolding maps?");
2057 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2058 }
2059}
2060
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2061bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2062X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2063 unsigned &SrcReg, unsigned &DstReg,
2064 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2065 switch (MI.getOpcode()) {
2066 default: break;
2067 case X86::MOVSX16rr8:
2068 case X86::MOVZX16rr8:
2069 case X86::MOVSX32rr8:
2070 case X86::MOVZX32rr8:
2071 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2072 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2073 // It's not always legal to reference the low 8-bit of the larger
2074 // register in 32-bit mode.
2075 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2076 case X86::MOVSX32rr16:
2077 case X86::MOVZX32rr16:
2078 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2079 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2080 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2081 // Be conservative.
2082 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2083 SrcReg = MI.getOperand(1).getReg();
2084 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2085 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2086 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2087 case X86::MOVSX16rr8:
2088 case X86::MOVZX16rr8:
2089 case X86::MOVSX32rr8:
2090 case X86::MOVZX32rr8:
2091 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2092 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2093 break;
2094 case X86::MOVSX32rr16:
2095 case X86::MOVZX32rr16:
2096 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2097 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2098 break;
2099 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2100 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2101 break;
2102 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2103 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2104 }
2105 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2106 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2107}
2108
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2109int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2110 const MachineFunction *MF = MI.getParent()->getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2111 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2112
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2113 if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2114 MI.getOpcode() == getCallFrameDestroyOpcode()) {
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2115 unsigned StackAlign = TFI->getStackAlignment();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2116 int SPAdj =
2117 (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2118
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2119 SPAdj -= MI.getOperand(1).getImm();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2120
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2121 if (MI.getOpcode() == getCallFrameSetupOpcode())
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2122 return SPAdj;
2123 else
2124 return -SPAdj;
2125 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2126
2127 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2128 // that is bound to the following ADJCALLSTACKUP pseudo.
2129 // Look for the next ADJCALLSTACKUP that follows the call.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2130 if (MI.isCall()) {
2131 const MachineBasicBlock *MBB = MI.getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2132 auto I = ++MachineBasicBlock::const_iterator(MI);
2133 for (auto E = MBB->end(); I != E; ++I) {
2134 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2135 I->isCall())
2136 break;
2137 }
2138
2139 // If we could not find a frame destroy opcode, then it has already
2140 // been simplified, so we don't care.
2141 if (I->getOpcode() != getCallFrameDestroyOpcode())
2142 return 0;
2143
2144 return -(I->getOperand(1).getImm());
2145 }
2146
2147 // Currently handle only PUSHes we can reasonably expect to see
2148 // in call sequences
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2149 switch (MI.getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2150 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2151 return 0;
2152 case X86::PUSH32i8:
2153 case X86::PUSH32r:
2154 case X86::PUSH32rmm:
2155 case X86::PUSH32rmr:
2156 case X86::PUSHi32:
2157 return 4;
David L Kreitzer0fe46322016-05-02 13:45:25 +0000[diff] [blame]2158 case X86::PUSH64i8:
2159 case X86::PUSH64r:
2160 case X86::PUSH64rmm:
2161 case X86::PUSH64rmr:
2162 case X86::PUSH64i32:
2163 return 8;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2164 }
2165}
2166
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2167/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2168/// operand and follow operands form a reference to the stack frame.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2169bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2170 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2171 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2172 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2173 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2174 MI.getOperand(Op + X86::AddrDisp).isImm() &&
2175 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2176 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2177 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2178 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2179 return true;
2180 }
2181 return false;
2182}
2183
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2184static bool isFrameLoadOpcode(int Opcode) {
2185 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2186 default:
2187 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2188 case X86::MOV8rm:
2189 case X86::MOV16rm:
2190 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2191 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2192 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2193 case X86::MOVSSrm:
2194 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2195 case X86::MOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2196 case X86::MOVUPSrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2197 case X86::MOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2198 case X86::MOVUPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2199 case X86::MOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2200 case X86::MOVDQUrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2201 case X86::VMOVSSrm:
2202 case X86::VMOVSDrm:
2203 case X86::VMOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2204 case X86::VMOVUPSrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2205 case X86::VMOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2206 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2207 case X86::VMOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2208 case X86::VMOVDQUrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2209 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2210 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2211 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2212 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2213 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2214 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2215 case X86::MMX_MOVD64rm:
2216 case X86::MMX_MOVQ64rm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2217 case X86::VMOVSSZrm:
2218 case X86::VMOVSDZrm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2219 case X86::VMOVAPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2220 case X86::VMOVAPSZ128rm:
2221 case X86::VMOVAPSZ256rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2222 case X86::VMOVUPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2223 case X86::VMOVUPSZ128rm:
2224 case X86::VMOVUPSZ256rm:
2225 case X86::VMOVAPDZrm:
2226 case X86::VMOVAPDZ128rm:
2227 case X86::VMOVAPDZ256rm:
2228 case X86::VMOVUPDZrm:
2229 case X86::VMOVUPDZ128rm:
2230 case X86::VMOVUPDZ256rm:
2231 case X86::VMOVDQA32Zrm:
2232 case X86::VMOVDQA32Z128rm:
2233 case X86::VMOVDQA32Z256rm:
2234 case X86::VMOVDQU32Zrm:
2235 case X86::VMOVDQU32Z128rm:
2236 case X86::VMOVDQU32Z256rm:
2237 case X86::VMOVDQA64Zrm:
2238 case X86::VMOVDQA64Z128rm:
2239 case X86::VMOVDQA64Z256rm:
2240 case X86::VMOVDQU64Zrm:
2241 case X86::VMOVDQU64Z128rm:
2242 case X86::VMOVDQU64Z256rm:
2243 case X86::VMOVDQU8Zrm:
2244 case X86::VMOVDQU8Z128rm:
2245 case X86::VMOVDQU8Z256rm:
2246 case X86::VMOVDQU16Zrm:
2247 case X86::VMOVDQU16Z128rm:
2248 case X86::VMOVDQU16Z256rm:
2249 case X86::KMOVBkm:
2250 case X86::KMOVWkm:
2251 case X86::KMOVDkm:
2252 case X86::KMOVQkm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2253 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2254 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2255}
2256
2257static bool isFrameStoreOpcode(int Opcode) {
2258 switch (Opcode) {
2259 default: break;
2260 case X86::MOV8mr:
2261 case X86::MOV16mr:
2262 case X86::MOV32mr:
2263 case X86::MOV64mr:
2264 case X86::ST_FpP64m:
2265 case X86::MOVSSmr:
2266 case X86::MOVSDmr:
2267 case X86::MOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2268 case X86::MOVUPSmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2269 case X86::MOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2270 case X86::MOVUPDmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2271 case X86::MOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2272 case X86::MOVDQUmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2273 case X86::VMOVSSmr:
2274 case X86::VMOVSDmr:
2275 case X86::VMOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2276 case X86::VMOVUPSmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2277 case X86::VMOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2278 case X86::VMOVUPDmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2279 case X86::VMOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2280 case X86::VMOVDQUmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2281 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2282 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2283 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2284 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2285 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2286 case X86::VMOVDQAYmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2287 case X86::VMOVSSZmr:
2288 case X86::VMOVSDZmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2289 case X86::VMOVUPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2290 case X86::VMOVUPSZ128mr:
2291 case X86::VMOVUPSZ256mr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2292 case X86::VMOVAPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2293 case X86::VMOVAPSZ128mr:
2294 case X86::VMOVAPSZ256mr:
2295 case X86::VMOVUPDZmr:
2296 case X86::VMOVUPDZ128mr:
2297 case X86::VMOVUPDZ256mr:
2298 case X86::VMOVAPDZmr:
2299 case X86::VMOVAPDZ128mr:
2300 case X86::VMOVAPDZ256mr:
2301 case X86::VMOVDQA32Zmr:
2302 case X86::VMOVDQA32Z128mr:
2303 case X86::VMOVDQA32Z256mr:
2304 case X86::VMOVDQU32Zmr:
2305 case X86::VMOVDQU32Z128mr:
2306 case X86::VMOVDQU32Z256mr:
2307 case X86::VMOVDQA64Zmr:
2308 case X86::VMOVDQA64Z128mr:
2309 case X86::VMOVDQA64Z256mr:
2310 case X86::VMOVDQU64Zmr:
2311 case X86::VMOVDQU64Z128mr:
2312 case X86::VMOVDQU64Z256mr:
2313 case X86::VMOVDQU8Zmr:
2314 case X86::VMOVDQU8Z128mr:
2315 case X86::VMOVDQU8Z256mr:
2316 case X86::VMOVDQU16Zmr:
2317 case X86::VMOVDQU16Z128mr:
2318 case X86::VMOVDQU16Z256mr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2319 case X86::MMX_MOVD64mr:
2320 case X86::MMX_MOVQ64mr:
2321 case X86::MMX_MOVNTQmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2322 case X86::KMOVBmk:
2323 case X86::KMOVWmk:
2324 case X86::KMOVDmk:
2325 case X86::KMOVQmk:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2326 return true;
2327 }
2328 return false;
2329}
2330
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2331unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2332 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2333 if (isFrameLoadOpcode(MI.getOpcode()))
2334 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2335 return MI.getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2336 return 0;
2337}
2338
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2339unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2340 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2341 if (isFrameLoadOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2342 unsigned Reg;
2343 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2344 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2345 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2346 const MachineMemOperand *Dummy;
2347 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2348 }
2349 return 0;
2350}
2351
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2352unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2353 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2354 if (isFrameStoreOpcode(MI.getOpcode()))
2355 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2356 isFrameOperand(MI, 0, FrameIndex))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2357 return MI.getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2358 return 0;
2359}
2360
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2361unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2362 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2363 if (isFrameStoreOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2364 unsigned Reg;
2365 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2366 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2367 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2368 const MachineMemOperand *Dummy;
2369 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2370 }
2371 return 0;
2372}
2373
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2374/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2375static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2376 // Don't waste compile time scanning use-def chains of physregs.
2377 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2378 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2379 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2380 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2381 E = MRI.def_instr_end(); I != E; ++I) {
2382 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2383 if (DefMI->getOpcode() != X86::MOVPC32r)
2384 return false;
2385 assert(!isPICBase && "More than one PIC base?");
2386 isPICBase = true;
2387 }
2388 return isPICBase;
2389}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2390
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2391bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2392 AliasAnalysis *AA) const {
2393 switch (MI.getOpcode()) {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2394 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2395 case X86::MOV8rm:
2396 case X86::MOV16rm:
2397 case X86::MOV32rm:
2398 case X86::MOV64rm:
2399 case X86::LD_Fp64m:
2400 case X86::MOVSSrm:
2401 case X86::MOVSDrm:
2402 case X86::MOVAPSrm:
2403 case X86::MOVUPSrm:
2404 case X86::MOVAPDrm:
2405 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2406 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2407 case X86::VMOVSSrm:
2408 case X86::VMOVSDrm:
2409 case X86::VMOVAPSrm:
2410 case X86::VMOVUPSrm:
2411 case X86::VMOVAPDrm:
2412 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2413 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2414 case X86::VMOVAPSYrm:
2415 case X86::VMOVUPSYrm:
2416 case X86::VMOVAPDYrm:
2417 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2418 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2419 case X86::MMX_MOVD64rm:
2420 case X86::MMX_MOVQ64rm:
2421 case X86::FsVMOVAPSrm:
2422 case X86::FsVMOVAPDrm:
2423 case X86::FsMOVAPSrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2424 case X86::FsMOVAPDrm:
2425 // AVX-512
2426 case X86::VMOVAPDZ128rm:
2427 case X86::VMOVAPDZ256rm:
2428 case X86::VMOVAPDZrm:
2429 case X86::VMOVAPSZ128rm:
2430 case X86::VMOVAPSZ256rm:
2431 case X86::VMOVAPSZrm:
2432 case X86::VMOVDQA32Z128rm:
2433 case X86::VMOVDQA32Z256rm:
2434 case X86::VMOVDQA32Zrm:
2435 case X86::VMOVDQA64Z128rm:
2436 case X86::VMOVDQA64Z256rm:
2437 case X86::VMOVDQA64Zrm:
2438 case X86::VMOVDQU16Z128rm:
2439 case X86::VMOVDQU16Z256rm:
2440 case X86::VMOVDQU16Zrm:
2441 case X86::VMOVDQU32Z128rm:
2442 case X86::VMOVDQU32Z256rm:
2443 case X86::VMOVDQU32Zrm:
2444 case X86::VMOVDQU64Z128rm:
2445 case X86::VMOVDQU64Z256rm:
2446 case X86::VMOVDQU64Zrm:
2447 case X86::VMOVDQU8Z128rm:
2448 case X86::VMOVDQU8Z256rm:
2449 case X86::VMOVDQU8Zrm:
2450 case X86::VMOVUPSZ128rm:
2451 case X86::VMOVUPSZ256rm:
2452 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2453 // Loads from constant pools are trivially rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2454 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2455 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2456 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2457 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2458 MI.isInvariantLoad(AA)) {
2459 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2460 if (BaseReg == 0 || BaseReg == X86::RIP)
2461 return true;
2462 // Allow re-materialization of PIC load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2463 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2464 return false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2465 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2466 const MachineRegisterInfo &MRI = MF.getRegInfo();
2467 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2468 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2469 return false;
2470 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2471
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2472 case X86::LEA32r:
2473 case X86::LEA64r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2474 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2475 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2476 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2477 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2478 // lea fi#, lea GV, etc. are all rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2479 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2480 return true;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2481 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2482 if (BaseReg == 0)
2483 return true;
2484 // Allow re-materialization of lea PICBase + x.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2485 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2486 const MachineRegisterInfo &MRI = MF.getRegInfo();
2487 return regIsPICBase(BaseReg, MRI);
2488 }
2489 return false;
2490 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2491 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2492
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2493 // All other instructions marked M_REMATERIALIZABLE are always trivially
2494 // rematerializable.
2495 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2496}
2497
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2498bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2499 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2500 MachineBasicBlock::iterator E = MBB.end();
2501
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2502 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2503 // safety after visiting 4 instructions in each direction, we will assume
2504 // it's not safe.
2505 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2506 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2507 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2508 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2509 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2510 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2511 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2512 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2513 continue;
2514 if (MO.getReg() == X86::EFLAGS) {
2515 if (MO.isUse())
2516 return false;
2517 SeenDef = true;
2518 }
2519 }
2520
2521 if (SeenDef)
2522 // This instruction defines EFLAGS, no need to look any further.
2523 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2524 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2525 // Skip over DBG_VALUE.
2526 while (Iter != E && Iter->isDebugValue())
2527 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2528 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2529
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2530 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2531 // live in.
2532 if (Iter == E) {
Craig Topperca66fc52015-12-20 18:41:57 +0000[diff] [blame]2533 for (MachineBasicBlock *S : MBB.successors())
2534 if (S->isLiveIn(X86::EFLAGS))
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2535 return false;
2536 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2537 }
2538
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2539 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2540 Iter = I;
2541 for (unsigned i = 0; i < 4; ++i) {
2542 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2543 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2544 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2545 return !MBB.isLiveIn(X86::EFLAGS);
2546
2547 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2548 // Skip over DBG_VALUE.
2549 while (Iter != B && Iter->isDebugValue())
2550 --Iter;
2551
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2552 bool SawKill = false;
2553 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2554 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2555 // A register mask may clobber EFLAGS, but we should still look for a
2556 // live EFLAGS def.
2557 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2558 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2559 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2560 if (MO.isDef()) return MO.isDead();
2561 if (MO.isKill()) SawKill = true;
2562 }
2563 }
2564
2565 if (SawKill)
2566 // This instruction kills EFLAGS and doesn't redefine it, so
2567 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2568 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2569 }
2570
2571 // Conservative answer.
2572 return false;
2573}
2574
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2575void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2576 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2577 unsigned DestReg, unsigned SubIdx,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2578 const MachineInstr &Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2579 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2580 bool ClobbersEFLAGS = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2581 for (const MachineOperand &MO : Orig.operands()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2582 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2583 ClobbersEFLAGS = true;
2584 break;
2585 }
2586 }
2587
2588 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2589 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2590 // effects.
2591 int Value;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2592 switch (Orig.getOpcode()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2593 case X86::MOV32r0: Value = 0; break;
2594 case X86::MOV32r1: Value = 1; break;
2595 case X86::MOV32r_1: Value = -1; break;
2596 default:
2597 llvm_unreachable("Unexpected instruction!");
2598 }
2599
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2600 const DebugLoc &DL = Orig.getDebugLoc();
2601 BuildMI(MBB, I, DL, get(X86::MOV32ri))
2602 .addOperand(Orig.getOperand(0))
2603 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2604 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2605 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2606 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2607 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2608
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]2609 MachineInstr &NewMI = *std::prev(I);
2610 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2611}
2612
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2613/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2614bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2615 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2616 MachineOperand &MO = MI.getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2617 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2618 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2619 return true;
2620 }
2621 }
2622 return false;
2623}
2624
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2625/// Check whether the shift count for a machine operand is non-zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2626inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2627 unsigned ShiftAmtOperandIdx) {
2628 // The shift count is six bits with the REX.W prefix and five bits without.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2629 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2630 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2631 return Imm & ShiftCountMask;
2632}
2633
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2634/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2635/// can be represented by a LEA instruction.
2636inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2637 // Left shift instructions can be transformed into load-effective-address
2638 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2639 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2640 // The SIB.scale field is two bits wide which means that we can encode any
2641 // shift amount less than 4.
2642 return ShAmt < 4 && ShAmt > 0;
2643}
2644
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2645bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2646 unsigned Opc, bool AllowSP, unsigned &NewSrc,
2647 bool &isKill, bool &isUndef,
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2648 MachineOperand &ImplicitOp) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2649 MachineFunction &MF = *MI.getParent()->getParent();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2650 const TargetRegisterClass *RC;
2651 if (AllowSP) {
2652 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2653 } else {
2654 RC = Opc != X86::LEA32r ?
2655 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2656 }
2657 unsigned SrcReg = Src.getReg();
2658
2659 // For both LEA64 and LEA32 the register already has essentially the right
2660 // type (32-bit or 64-bit) we may just need to forbid SP.
2661 if (Opc != X86::LEA64_32r) {
2662 NewSrc = SrcReg;
2663 isKill = Src.isKill();
2664 isUndef = Src.isUndef();
2665
2666 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2667 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2668 return false;
2669
2670 return true;
2671 }
2672
2673 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2674 // another we need to add 64-bit registers to the final MI.
2675 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2676 ImplicitOp = Src;
2677 ImplicitOp.setImplicit();
2678
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]2679 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2680 MachineBasicBlock::LivenessQueryResult LQR =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2681 MI.getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2682
2683 switch (LQR) {
2684 case MachineBasicBlock::LQR_Unknown:
2685 // We can't give sane liveness flags to the instruction, abandon LEA
2686 // formation.
2687 return false;
2688 case MachineBasicBlock::LQR_Live:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2689 isKill = MI.killsRegister(SrcReg);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2690 isUndef = false;
2691 break;
2692 default:
2693 // The physreg itself is dead, so we have to use it as an <undef>.
2694 isKill = false;
2695 isUndef = true;
2696 break;
2697 }
2698 } else {
2699 // Virtual register of the wrong class, we have to create a temporary 64-bit
2700 // vreg to feed into the LEA.
2701 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2702 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2703 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2704 .addOperand(Src);
2705
2706 // Which is obviously going to be dead after we're done with it.
2707 isKill = true;
2708 isUndef = false;
2709 }
2710
2711 // We've set all the parameters without issue.
2712 return true;
2713}
2714
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2715/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2716/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2717/// truncating back down to a 16-bit subregister.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2718MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2719 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2720 LiveVariables *LV) const {
2721 MachineBasicBlock::iterator MBBI = MI.getIterator();
2722 unsigned Dest = MI.getOperand(0).getReg();
2723 unsigned Src = MI.getOperand(1).getReg();
2724 bool isDead = MI.getOperand(0).isDead();
2725 bool isKill = MI.getOperand(1).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2726
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2727 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2728 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2729 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2730 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2731 Opc = X86::LEA64_32r;
2732 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2733 } else {
2734 Opc = X86::LEA32r;
2735 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2736 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2737
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2738 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2739 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2740 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2741 // movw (%rbp,%rcx,2), %dx
2742 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2743 // But testing has shown this *does* help performance in 64-bit mode (at
2744 // least on modern x86 machines).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2745 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2746 MachineInstr *InsMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2747 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2748 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2749 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2750
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2751 MachineInstrBuilder MIB =
2752 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2753 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2754 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2755 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2756 unsigned ShAmt = MI.getOperand(2).getImm();
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2757 MIB.addReg(0).addImm(1ULL << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2758 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2759 break;
2760 }
2761 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2762 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2763 break;
2764 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2765 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2766 break;
2767 case X86::ADD16ri:
2768 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2769 case X86::ADD16ri_DB:
2770 case X86::ADD16ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2771 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2772 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2773 case X86::ADD16rr:
2774 case X86::ADD16rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2775 unsigned Src2 = MI.getOperand(2).getReg();
2776 bool isKill2 = MI.getOperand(2).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2777 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2778 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2779 if (Src == Src2) {
2780 // ADD16rr %reg1028<kill>, %reg1028
2781 // just a single insert_subreg.
2782 addRegReg(MIB, leaInReg, true, leaInReg, false);
2783 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2784 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2785 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2786 else
2787 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2788 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2789 // well be shifting and then extracting the lower 16-bits.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2790 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2791 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2792 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2793 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2794 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2795 }
2796 if (LV && isKill2 && InsMI2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2797 LV->replaceKillInstruction(Src2, MI, *InsMI2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2798 break;
2799 }
2800 }
2801
2802 MachineInstr *NewMI = MIB;
2803 MachineInstr *ExtMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2804 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2805 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2806 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2807
2808 if (LV) {
2809 // Update live variables
2810 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2811 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2812 if (isKill)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2813 LV->replaceKillInstruction(Src, MI, *InsMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2814 if (isDead)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2815 LV->replaceKillInstruction(Dest, MI, *ExtMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2816 }
2817
2818 return ExtMI;
2819}
2820
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2821/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2822/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2823/// may be able to convert a two-address instruction into a true
2824/// three-address instruction on demand. This allows the X86 target (for
2825/// example) to convert ADD and SHL instructions into LEA instructions if they
2826/// would require register copies due to two-addressness.
2827///
2828/// This method returns a null pointer if the transformation cannot be
2829/// performed, otherwise it returns the new instruction.
2830///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2831MachineInstr *
2832X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2833 MachineInstr &MI, LiveVariables *LV) const {
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2834 // The following opcodes also sets the condition code register(s). Only
2835 // convert them to equivalent lea if the condition code register def's
2836 // are dead!
2837 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2838 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2839
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2840 MachineFunction &MF = *MI.getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2841 // All instructions input are two-addr instructions. Get the known operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2842 const MachineOperand &Dest = MI.getOperand(0);
2843 const MachineOperand &Src = MI.getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2844
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2845 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2846 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2847 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2848 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2849 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2850 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2851
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2852 unsigned MIOpc = MI.getOpcode();
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2853 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2854 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2855 case X86::SHL64ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2856 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2857 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2858 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2859
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2860 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2861 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2862 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2863 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2864 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2865
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2866 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2867 .addOperand(Dest)
2868 .addReg(0)
2869 .addImm(1ULL << ShAmt)
2870 .addOperand(Src)
2871 .addImm(0)
2872 .addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2873 break;
2874 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2875 case X86::SHL32ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2876 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2877 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2878 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2879
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2880 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2881
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2882 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2883 bool isKill, isUndef;
2884 unsigned SrcReg;
2885 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2886 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2887 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2888 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2889
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2890 MachineInstrBuilder MIB =
2891 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2892 .addOperand(Dest)
2893 .addReg(0)
2894 .addImm(1ULL << ShAmt)
2895 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2896 .addImm(0)
2897 .addReg(0);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2898 if (ImplicitOp.getReg() != 0)
2899 MIB.addOperand(ImplicitOp);
2900 NewMI = MIB;
2901
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2902 break;
2903 }
2904 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2905 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2906 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2907 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2908
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2909 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2910 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2911 : nullptr;
2912 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2913 .addOperand(Dest)
2914 .addReg(0)
2915 .addImm(1ULL << ShAmt)
2916 .addOperand(Src)
2917 .addImm(0)
2918 .addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2919 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2920 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2921 case X86::INC64r:
2922 case X86::INC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2923 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2924 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2925 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2926 bool isKill, isUndef;
2927 unsigned SrcReg;
2928 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2929 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2930 SrcReg, isKill, isUndef, ImplicitOp))
2931 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2932
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2933 MachineInstrBuilder MIB =
2934 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2935 .addOperand(Dest)
2936 .addReg(SrcReg,
2937 getKillRegState(isKill) | getUndefRegState(isUndef));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2938 if (ImplicitOp.getReg() != 0)
2939 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2940
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2941 NewMI = addOffset(MIB, 1);
2942 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2943 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2944 case X86::INC16r:
2945 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2946 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2947 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2948 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
2949 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2950 .addOperand(Dest)
2951 .addOperand(Src),
2952 1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2953 break;
2954 case X86::DEC64r:
2955 case X86::DEC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2956 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2957 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2958 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2959
2960 bool isKill, isUndef;
2961 unsigned SrcReg;
2962 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2963 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2964 SrcReg, isKill, isUndef, ImplicitOp))
2965 return nullptr;
2966
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2967 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2968 .addOperand(Dest)
2969 .addReg(SrcReg, getUndefRegState(isUndef) |
2970 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2971 if (ImplicitOp.getReg() != 0)
2972 MIB.addOperand(ImplicitOp);
2973
2974 NewMI = addOffset(MIB, -1);
2975
2976 break;
2977 }
2978 case X86::DEC16r:
2979 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2980 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2981 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2982 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
2983 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2984 .addOperand(Dest)
2985 .addOperand(Src),
2986 -1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2987 break;
2988 case X86::ADD64rr:
2989 case X86::ADD64rr_DB:
2990 case X86::ADD32rr:
2991 case X86::ADD32rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2992 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2993 unsigned Opc;
2994 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2995 Opc = X86::LEA64r;
2996 else
2997 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2998
2999 bool isKill, isUndef;
3000 unsigned SrcReg;
3001 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3002 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3003 SrcReg, isKill, isUndef, ImplicitOp))
3004 return nullptr;
3005
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3006 const MachineOperand &Src2 = MI.getOperand(2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3007 bool isKill2, isUndef2;
3008 unsigned SrcReg2;
3009 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3010 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
3011 SrcReg2, isKill2, isUndef2, ImplicitOp2))
3012 return nullptr;
3013
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3014 MachineInstrBuilder MIB =
3015 BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3016 if (ImplicitOp.getReg() != 0)
3017 MIB.addOperand(ImplicitOp);
3018 if (ImplicitOp2.getReg() != 0)
3019 MIB.addOperand(ImplicitOp2);
3020
3021 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3022
3023 // Preserve undefness of the operands.
3024 NewMI->getOperand(1).setIsUndef(isUndef);
3025 NewMI->getOperand(3).setIsUndef(isUndef2);
3026
3027 if (LV && Src2.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3028 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3029 break;
3030 }
3031 case X86::ADD16rr:
3032 case X86::ADD16rr_DB: {
3033 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3034 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3035 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3036 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3037 unsigned Src2 = MI.getOperand(2).getReg();
3038 bool isKill2 = MI.getOperand(2).isKill();
3039 NewMI = addRegReg(
3040 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3041 Src.getReg(), Src.isKill(), Src2, isKill2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3042
3043 // Preserve undefness of the operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3044 bool isUndef = MI.getOperand(1).isUndef();
3045 bool isUndef2 = MI.getOperand(2).isUndef();
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3046 NewMI->getOperand(1).setIsUndef(isUndef);
3047 NewMI->getOperand(3).setIsUndef(isUndef2);
3048
3049 if (LV && isKill2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3050 LV->replaceKillInstruction(Src2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3051 break;
3052 }
3053 case X86::ADD64ri32:
3054 case X86::ADD64ri8:
3055 case X86::ADD64ri32_DB:
3056 case X86::ADD64ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3057 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3058 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3059 .addOperand(Dest)
3060 .addOperand(Src),
3061 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3062 break;
3063 case X86::ADD32ri:
3064 case X86::ADD32ri8:
3065 case X86::ADD32ri_DB:
3066 case X86::ADD32ri8_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3067 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3068 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3069
3070 bool isKill, isUndef;
3071 unsigned SrcReg;
3072 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3073 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3074 SrcReg, isKill, isUndef, ImplicitOp))
3075 return nullptr;
3076
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3077 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3078 .addOperand(Dest)
3079 .addReg(SrcReg, getUndefRegState(isUndef) |
3080 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3081 if (ImplicitOp.getReg() != 0)
3082 MIB.addOperand(ImplicitOp);
3083
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3084 NewMI = addOffset(MIB, MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3085 break;
3086 }
3087 case X86::ADD16ri:
3088 case X86::ADD16ri8:
3089 case X86::ADD16ri_DB:
3090 case X86::ADD16ri8_DB:
3091 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3092 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3093 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3094 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3095 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3096 .addOperand(Dest)
3097 .addOperand(Src),
3098 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3099 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3100 }
3101
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3102 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]3103
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3104 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3105 if (Src.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3106 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3107 if (Dest.isDead())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3108 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3109 }
3110
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3111 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]3112 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3113}
3114
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3115/// Returns true if the given instruction opcode is FMA3.
3116/// Otherwise, returns false.
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3117/// The second parameter is optional and is used as the second return from
3118/// the function. It is set to true if the given instruction has FMA3 opcode
3119/// that is used for lowering of scalar FMA intrinsics, and it is set to false
3120/// otherwise.
3121static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3122 if (IsIntrinsic)
3123 *IsIntrinsic = false;
3124
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3125 switch (Opcode) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3126 case X86::VFMADDSDr132r: case X86::VFMADDSDr132m:
3127 case X86::VFMADDSSr132r: case X86::VFMADDSSr132m:
3128 case X86::VFMSUBSDr132r: case X86::VFMSUBSDr132m:
3129 case X86::VFMSUBSSr132r: case X86::VFMSUBSSr132m:
3130 case X86::VFNMADDSDr132r: case X86::VFNMADDSDr132m:
3131 case X86::VFNMADDSSr132r: case X86::VFNMADDSSr132m:
3132 case X86::VFNMSUBSDr132r: case X86::VFNMSUBSDr132m:
3133 case X86::VFNMSUBSSr132r: case X86::VFNMSUBSSr132m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3134
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3135 case X86::VFMADDSDr213r: case X86::VFMADDSDr213m:
3136 case X86::VFMADDSSr213r: case X86::VFMADDSSr213m:
3137 case X86::VFMSUBSDr213r: case X86::VFMSUBSDr213m:
3138 case X86::VFMSUBSSr213r: case X86::VFMSUBSSr213m:
3139 case X86::VFNMADDSDr213r: case X86::VFNMADDSDr213m:
3140 case X86::VFNMADDSSr213r: case X86::VFNMADDSSr213m:
3141 case X86::VFNMSUBSDr213r: case X86::VFNMSUBSDr213m:
3142 case X86::VFNMSUBSSr213r: case X86::VFNMSUBSSr213m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3143
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3144 case X86::VFMADDSDr231r: case X86::VFMADDSDr231m:
3145 case X86::VFMADDSSr231r: case X86::VFMADDSSr231m:
3146 case X86::VFMSUBSDr231r: case X86::VFMSUBSDr231m:
3147 case X86::VFMSUBSSr231r: case X86::VFMSUBSSr231m:
3148 case X86::VFNMADDSDr231r: case X86::VFNMADDSDr231m:
3149 case X86::VFNMADDSSr231r: case X86::VFNMADDSSr231m:
3150 case X86::VFNMSUBSDr231r: case X86::VFNMSUBSDr231m:
3151 case X86::VFNMSUBSSr231r: case X86::VFNMSUBSSr231m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3152
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3153 case X86::VFMADDSUBPDr132r: case X86::VFMADDSUBPDr132m:
3154 case X86::VFMADDSUBPSr132r: case X86::VFMADDSUBPSr132m:
3155 case X86::VFMSUBADDPDr132r: case X86::VFMSUBADDPDr132m:
3156 case X86::VFMSUBADDPSr132r: case X86::VFMSUBADDPSr132m:
3157 case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY:
3158 case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY:
3159 case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY:
3160 case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3161
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3162 case X86::VFMADDPDr132r: case X86::VFMADDPDr132m:
3163 case X86::VFMADDPSr132r: case X86::VFMADDPSr132m:
3164 case X86::VFMSUBPDr132r: case X86::VFMSUBPDr132m:
3165 case X86::VFMSUBPSr132r: case X86::VFMSUBPSr132m:
3166 case X86::VFNMADDPDr132r: case X86::VFNMADDPDr132m:
3167 case X86::VFNMADDPSr132r: case X86::VFNMADDPSr132m:
3168 case X86::VFNMSUBPDr132r: case X86::VFNMSUBPDr132m:
3169 case X86::VFNMSUBPSr132r: case X86::VFNMSUBPSr132m:
3170 case X86::VFMADDPDr132rY: case X86::VFMADDPDr132mY:
3171 case X86::VFMADDPSr132rY: case X86::VFMADDPSr132mY:
3172 case X86::VFMSUBPDr132rY: case X86::VFMSUBPDr132mY:
3173 case X86::VFMSUBPSr132rY: case X86::VFMSUBPSr132mY:
3174 case X86::VFNMADDPDr132rY: case X86::VFNMADDPDr132mY:
3175 case X86::VFNMADDPSr132rY: case X86::VFNMADDPSr132mY:
3176 case X86::VFNMSUBPDr132rY: case X86::VFNMSUBPDr132mY:
3177 case X86::VFNMSUBPSr132rY: case X86::VFNMSUBPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3178
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3179 case X86::VFMADDSUBPDr213r: case X86::VFMADDSUBPDr213m:
3180 case X86::VFMADDSUBPSr213r: case X86::VFMADDSUBPSr213m:
3181 case X86::VFMSUBADDPDr213r: case X86::VFMSUBADDPDr213m:
3182 case X86::VFMSUBADDPSr213r: case X86::VFMSUBADDPSr213m:
3183 case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY:
3184 case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY:
3185 case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY:
3186 case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3187
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3188 case X86::VFMADDPDr213r: case X86::VFMADDPDr213m:
3189 case X86::VFMADDPSr213r: case X86::VFMADDPSr213m:
3190 case X86::VFMSUBPDr213r: case X86::VFMSUBPDr213m:
3191 case X86::VFMSUBPSr213r: case X86::VFMSUBPSr213m:
3192 case X86::VFNMADDPDr213r: case X86::VFNMADDPDr213m:
3193 case X86::VFNMADDPSr213r: case X86::VFNMADDPSr213m:
3194 case X86::VFNMSUBPDr213r: case X86::VFNMSUBPDr213m:
3195 case X86::VFNMSUBPSr213r: case X86::VFNMSUBPSr213m:
3196 case X86::VFMADDPDr213rY: case X86::VFMADDPDr213mY:
3197 case X86::VFMADDPSr213rY: case X86::VFMADDPSr213mY:
3198 case X86::VFMSUBPDr213rY: case X86::VFMSUBPDr213mY:
3199 case X86::VFMSUBPSr213rY: case X86::VFMSUBPSr213mY:
3200 case X86::VFNMADDPDr213rY: case X86::VFNMADDPDr213mY:
3201 case X86::VFNMADDPSr213rY: case X86::VFNMADDPSr213mY:
3202 case X86::VFNMSUBPDr213rY: case X86::VFNMSUBPDr213mY:
3203 case X86::VFNMSUBPSr213rY: case X86::VFNMSUBPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3204
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3205 case X86::VFMADDSUBPDr231r: case X86::VFMADDSUBPDr231m:
3206 case X86::VFMADDSUBPSr231r: case X86::VFMADDSUBPSr231m:
3207 case X86::VFMSUBADDPDr231r: case X86::VFMSUBADDPDr231m:
3208 case X86::VFMSUBADDPSr231r: case X86::VFMSUBADDPSr231m:
3209 case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY:
3210 case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY:
3211 case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY:
3212 case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3213
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3214 case X86::VFMADDPDr231r: case X86::VFMADDPDr231m:
3215 case X86::VFMADDPSr231r: case X86::VFMADDPSr231m:
3216 case X86::VFMSUBPDr231r: case X86::VFMSUBPDr231m:
3217 case X86::VFMSUBPSr231r: case X86::VFMSUBPSr231m:
3218 case X86::VFNMADDPDr231r: case X86::VFNMADDPDr231m:
3219 case X86::VFNMADDPSr231r: case X86::VFNMADDPSr231m:
3220 case X86::VFNMSUBPDr231r: case X86::VFNMSUBPDr231m:
3221 case X86::VFNMSUBPSr231r: case X86::VFNMSUBPSr231m:
3222 case X86::VFMADDPDr231rY: case X86::VFMADDPDr231mY:
3223 case X86::VFMADDPSr231rY: case X86::VFMADDPSr231mY:
3224 case X86::VFMSUBPDr231rY: case X86::VFMSUBPDr231mY:
3225 case X86::VFMSUBPSr231rY: case X86::VFMSUBPSr231mY:
3226 case X86::VFNMADDPDr231rY: case X86::VFNMADDPDr231mY:
3227 case X86::VFNMADDPSr231rY: case X86::VFNMADDPSr231mY:
3228 case X86::VFNMSUBPDr231rY: case X86::VFNMSUBPDr231mY:
3229 case X86::VFNMSUBPSr231rY: case X86::VFNMSUBPSr231mY:
3230 return true;
3231
3232 case X86::VFMADDSDr132r_Int: case X86::VFMADDSDr132m_Int:
3233 case X86::VFMADDSSr132r_Int: case X86::VFMADDSSr132m_Int:
3234 case X86::VFMSUBSDr132r_Int: case X86::VFMSUBSDr132m_Int:
3235 case X86::VFMSUBSSr132r_Int: case X86::VFMSUBSSr132m_Int:
3236 case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3237 case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3238 case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3239 case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3240
3241 case X86::VFMADDSDr213r_Int: case X86::VFMADDSDr213m_Int:
3242 case X86::VFMADDSSr213r_Int: case X86::VFMADDSSr213m_Int:
3243 case X86::VFMSUBSDr213r_Int: case X86::VFMSUBSDr213m_Int:
3244 case X86::VFMSUBSSr213r_Int: case X86::VFMSUBSSr213m_Int:
3245 case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3246 case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3247 case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3248 case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3249
3250 case X86::VFMADDSDr231r_Int: case X86::VFMADDSDr231m_Int:
3251 case X86::VFMADDSSr231r_Int: case X86::VFMADDSSr231m_Int:
3252 case X86::VFMSUBSDr231r_Int: case X86::VFMSUBSDr231m_Int:
3253 case X86::VFMSUBSSr231r_Int: case X86::VFMSUBSSr231m_Int:
3254 case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3255 case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3256 case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3257 case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3258 if (IsIntrinsic)
3259 *IsIntrinsic = true;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3260 return true;
3261 default:
3262 return false;
3263 }
3264 llvm_unreachable("Opcode not handled by the switch");
3265}
3266
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3267MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3268 unsigned OpIdx1,
3269 unsigned OpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3270 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3271 if (NewMI)
3272 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3273 return MI;
3274 };
3275
3276 switch (MI.getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3277 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3278 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3279 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3280 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3281 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3282 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3283 unsigned Opc;
3284 unsigned Size;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3285 switch (MI.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3286 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3287 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3288 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3289 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3290 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3291 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3292 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3293 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3294 unsigned Amt = MI.getOperand(3).getImm();
3295 auto &WorkingMI = cloneIfNew(MI);
3296 WorkingMI.setDesc(get(Opc));
3297 WorkingMI.getOperand(3).setImm(Size - Amt);
3298 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3299 OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3300 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3301 case X86::BLENDPDrri:
3302 case X86::BLENDPSrri:
3303 case X86::PBLENDWrri:
3304 case X86::VBLENDPDrri:
3305 case X86::VBLENDPSrri:
3306 case X86::VBLENDPDYrri:
3307 case X86::VBLENDPSYrri:
3308 case X86::VPBLENDDrri:
3309 case X86::VPBLENDWrri:
3310 case X86::VPBLENDDYrri:
3311 case X86::VPBLENDWYrri:{
3312 unsigned Mask;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3313 switch (MI.getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3314 default: llvm_unreachable("Unreachable!");
3315 case X86::BLENDPDrri: Mask = 0x03; break;
3316 case X86::BLENDPSrri: Mask = 0x0F; break;
3317 case X86::PBLENDWrri: Mask = 0xFF; break;
3318 case X86::VBLENDPDrri: Mask = 0x03; break;
3319 case X86::VBLENDPSrri: Mask = 0x0F; break;
3320 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3321 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3322 case X86::VPBLENDDrri: Mask = 0x0F; break;
3323 case X86::VPBLENDWrri: Mask = 0xFF; break;
3324 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3325 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3326 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3327 // Only the least significant bits of Imm are used.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3328 unsigned Imm = MI.getOperand(3).getImm() & Mask;
3329 auto &WorkingMI = cloneIfNew(MI);
3330 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3331 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3332 OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3333 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3334 case X86::PCLMULQDQrr:
3335 case X86::VPCLMULQDQrr:{
3336 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3337 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3338 unsigned Imm = MI.getOperand(3).getImm();
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3339 unsigned Src1Hi = Imm & 0x01;
3340 unsigned Src2Hi = Imm & 0x10;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3341 auto &WorkingMI = cloneIfNew(MI);
3342 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3343 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3344 OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3345 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3346 case X86::CMPPDrri:
3347 case X86::CMPPSrri:
3348 case X86::VCMPPDrri:
3349 case X86::VCMPPSrri:
3350 case X86::VCMPPDYrri:
3351 case X86::VCMPPSYrri: {
3352 // Float comparison can be safely commuted for
3353 // Ordered/Unordered/Equal/NotEqual tests
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3354 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3355 switch (Imm) {
3356 case 0x00: // EQUAL
3357 case 0x03: // UNORDERED
3358 case 0x04: // NOT EQUAL
3359 case 0x07: // ORDERED
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3360 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3361 default:
3362 return nullptr;
3363 }
3364 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3365 case X86::VPCOMBri: case X86::VPCOMUBri:
3366 case X86::VPCOMDri: case X86::VPCOMUDri:
3367 case X86::VPCOMQri: case X86::VPCOMUQri:
3368 case X86::VPCOMWri: case X86::VPCOMUWri: {
3369 // Flip comparison mode immediate (if necessary).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3370 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3371 switch (Imm) {
3372 case 0x00: Imm = 0x02; break; // LT -> GT
3373 case 0x01: Imm = 0x03; break; // LE -> GE
3374 case 0x02: Imm = 0x00; break; // GT -> LT
3375 case 0x03: Imm = 0x01; break; // GE -> LE
3376 case 0x04: // EQ
3377 case 0x05: // NE
3378 case 0x06: // FALSE
3379 case 0x07: // TRUE
3380 default:
3381 break;
3382 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3383 auto &WorkingMI = cloneIfNew(MI);
3384 WorkingMI.getOperand(3).setImm(Imm);
3385 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3386 OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3387 }
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3388 case X86::VPERM2F128rr:
3389 case X86::VPERM2I128rr: {
3390 // Flip permute source immediate.
3391 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3392 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3393 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3394 auto &WorkingMI = cloneIfNew(MI);
3395 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3396 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3397 OpIdx1, OpIdx2);
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3398 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3399 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3400 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3401 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3402 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3403 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3404 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3405 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3406 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3407 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3408 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3409 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3410 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3411 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3412 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3413 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3414 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3415 unsigned Opc;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3416 switch (MI.getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3417 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3418 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3419 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3420 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3421 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3422 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3423 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3424 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3425 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3426 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3427 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3428 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3429 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3430 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3431 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3432 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3433 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3434 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3435 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3436 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3437 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3438 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3439 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3440 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3441 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3442 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3443 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3444 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3445 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3446 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3447 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3448 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3449 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3450 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3451 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3452 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3453 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3454 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3455 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3456 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3457 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3458 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3459 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3460 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3461 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3462 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3463 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3464 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3465 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3466 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3467 auto &WorkingMI = cloneIfNew(MI);
3468 WorkingMI.setDesc(get(Opc));
3469 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3470 OpIdx1, OpIdx2);
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3471 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3472 default:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3473 if (isFMA3(MI.getOpcode())) {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3474 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3475 if (Opc == 0)
3476 return nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3477 auto &WorkingMI = cloneIfNew(MI);
3478 WorkingMI.setDesc(get(Opc));
3479 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3480 OpIdx1, OpIdx2);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3481 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3482
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3483 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3484 }
3485}
3486
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3487bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3488 unsigned &SrcOpIdx1,
3489 unsigned &SrcOpIdx2) const {
3490
3491 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3492
3493 // Only the first RegOpsNum operands are commutable.
3494 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3495 // that the operand is not specified/fixed.
3496 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3497 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3498 return false;
3499 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3500 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3501 return false;
3502
3503 // Look for two different register operands assumed to be commutable
3504 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3505 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3506 SrcOpIdx2 == CommuteAnyOperandIndex) {
3507 unsigned CommutableOpIdx1 = SrcOpIdx1;
3508 unsigned CommutableOpIdx2 = SrcOpIdx2;
3509
3510 // At least one of operands to be commuted is not specified and
3511 // this method is free to choose appropriate commutable operands.
3512 if (SrcOpIdx1 == SrcOpIdx2)
3513 // Both of operands are not fixed. By default set one of commutable
3514 // operands to the last register operand of the instruction.
3515 CommutableOpIdx2 = RegOpsNum;
3516 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3517 // Only one of operands is not fixed.
3518 CommutableOpIdx2 = SrcOpIdx1;
3519
3520 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3521 // operand and assign its index to CommutableOpIdx1.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3522 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3523 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3524 // The commuted operands must have different registers.
3525 // Otherwise, the commute transformation does not change anything and
3526 // is useless then.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3527 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3528 break;
3529 }
3530
3531 // No appropriate commutable operands were found.
3532 if (CommutableOpIdx1 == 0)
3533 return false;
3534
3535 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3536 // to return those values.
3537 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3538 CommutableOpIdx1, CommutableOpIdx2))
3539 return false;
3540 }
3541
3542 // Check if we can adjust the opcode to preserve the semantics when
3543 // commute the register operands.
3544 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3545}
3546
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3547unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3548 MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) const {
3549 unsigned Opc = MI.getOpcode();
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3550
3551 // Define the array that holds FMA opcodes in groups
3552 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3553 static const uint16_t RegularOpcodeGroups[][3] = {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3554 { X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
3555 { X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
3556 { X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
3557 { X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
3558 { X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
3559 { X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
3560 { X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
3561 { X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
3562 { X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
3563 { X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
3564 { X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
3565 { X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
3566
3567 { X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
3568 { X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
3569 { X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
3570 { X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
3571 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
3572 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
3573 { X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
3574 { X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
3575 { X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
3576 { X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
3577 { X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
3578 { X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
Vyacheslav Klochkov1ff9cbd2015-11-12 20:11:57 +0000[diff] [blame]3579
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3580 { X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
3581 { X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
3582 { X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
3583 { X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
3584 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3585 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3586 { X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
3587 { X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
3588 { X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
3589 { X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
3590 { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3591 { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3592
3593 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
3594 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
3595 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
3596 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
3597 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3598 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3599 { X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
3600 { X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
3601 { X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
3602 { X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
3603 { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3604 { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3605
3606 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
3607 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
3608 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3609 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3610 { X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
3611 { X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
3612 { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3613 { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3614
3615 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
3616 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
3617 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3618 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3619 { X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
3620 { X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
3621 { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3622 { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3623 };
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3624
3625 // Define the array that holds FMA*_Int opcodes in groups
3626 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3627 static const uint16_t IntrinOpcodeGroups[][3] = {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3628 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
3629 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
3630 { X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
3631 { X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
3632
3633 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
3634 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
3635 { X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
3636 { X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
3637
3638 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3639 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3640 { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3641 { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3642
3643 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3644 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3645 { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3646 { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3647 };
3648
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3649 const unsigned Form132Index = 0;
3650 const unsigned Form213Index = 1;
3651 const unsigned Form231Index = 2;
3652 const unsigned FormsNum = 3;
3653
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3654 bool IsIntrinOpcode;
3655 isFMA3(Opc, &IsIntrinOpcode);
3656
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3657 size_t GroupsNum;
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3658 const uint16_t (*OpcodeGroups)[3];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3659 if (IsIntrinOpcode) {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3660 GroupsNum = array_lengthof(IntrinOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3661 OpcodeGroups = IntrinOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3662 } else {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3663 GroupsNum = array_lengthof(RegularOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3664 OpcodeGroups = RegularOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3665 }
3666
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3667 const uint16_t *FoundOpcodesGroup = nullptr;
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3668 size_t FormIndex;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3669
3670 // Look for the input opcode in the corresponding opcodes table.
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3671 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3672 ++GroupIndex) {
3673 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3674 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3675 FoundOpcodesGroup = OpcodeGroups[GroupIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3676 break;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3677 }
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3678 }
3679 }
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3680
3681 // The input opcode does not match with any of the opcodes from the tables.
3682 // The unsupported FMA opcode must be added to one of the two opcode groups
3683 // defined above.
3684 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3685
3686 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3687 if (SrcOpIdx1 > SrcOpIdx2)
3688 std::swap(SrcOpIdx1, SrcOpIdx2);
3689
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3690 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3691 // analysis. The commute optimization is legal only if all users of FMA*_Int
3692 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3693 // not implemented yet. So, just return 0 in that case.
3694 // When such analysis are available this place will be the right place for
3695 // calling it.
3696 if (IsIntrinOpcode && SrcOpIdx1 == 1)
3697 return 0;
3698
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3699 unsigned Case;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3700 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3701 Case = 0;
3702 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3703 Case = 1;
3704 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3705 Case = 2;
3706 else
3707 return 0;
3708
3709 // Define the FMA forms mapping array that helps to map input FMA form
3710 // to output FMA form to preserve the operation semantics after
3711 // commuting the operands.
3712 static const unsigned FormMapping[][3] = {
3713 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3714 // FMA132 A, C, b; ==> FMA231 C, A, b;
3715 // FMA213 B, A, c; ==> FMA213 A, B, c;
3716 // FMA231 C, A, b; ==> FMA132 A, C, b;
3717 { Form231Index, Form213Index, Form132Index },
3718 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3719 // FMA132 A, c, B; ==> FMA132 B, c, A;
3720 // FMA213 B, a, C; ==> FMA231 C, a, B;
3721 // FMA231 C, a, B; ==> FMA213 B, a, C;
3722 { Form132Index, Form231Index, Form213Index },
3723 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3724 // FMA132 a, C, B; ==> FMA213 a, B, C;
3725 // FMA213 b, A, C; ==> FMA132 b, C, A;
3726 // FMA231 c, A, B; ==> FMA231 c, B, A;
3727 { Form213Index, Form132Index, Form231Index }
3728 };
3729
3730 // Everything is ready, just adjust the FMA opcode and return it.
3731 FormIndex = FormMapping[Case][FormIndex];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3732 return FoundOpcodesGroup[FormIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3733}
3734
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3735bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3736 unsigned &SrcOpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3737 switch (MI.getOpcode()) {
3738 case X86::CMPPDrri:
3739 case X86::CMPPSrri:
3740 case X86::VCMPPDrri:
3741 case X86::VCMPPSrri:
3742 case X86::VCMPPDYrri:
3743 case X86::VCMPPSYrri: {
3744 // Float comparison can be safely commuted for
3745 // Ordered/Unordered/Equal/NotEqual tests
3746 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3747 switch (Imm) {
3748 case 0x00: // EQUAL
3749 case 0x03: // UNORDERED
3750 case 0x04: // NOT EQUAL
3751 case 0x07: // ORDERED
3752 // The indices of the commutable operands are 1 and 2.
3753 // Assign them to the returned operand indices here.
3754 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3755 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3756 return false;
3757 }
3758 default:
3759 if (isFMA3(MI.getOpcode()))
3760 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3761 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3762 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3763 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3764}
3765
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3766static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3767 switch (BrOpc) {
3768 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3769 case X86::JE_1: return X86::COND_E;
3770 case X86::JNE_1: return X86::COND_NE;
3771 case X86::JL_1: return X86::COND_L;
3772 case X86::JLE_1: return X86::COND_LE;
3773 case X86::JG_1: return X86::COND_G;
3774 case X86::JGE_1: return X86::COND_GE;
3775 case X86::JB_1: return X86::COND_B;
3776 case X86::JBE_1: return X86::COND_BE;
3777 case X86::JA_1: return X86::COND_A;
3778 case X86::JAE_1: return X86::COND_AE;
3779 case X86::JS_1: return X86::COND_S;
3780 case X86::JNS_1: return X86::COND_NS;
3781 case X86::JP_1: return X86::COND_P;
3782 case X86::JNP_1: return X86::COND_NP;
3783 case X86::JO_1: return X86::COND_O;
3784 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3785 }
3786}
3787
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3788/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3789static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3790 switch (Opc) {
3791 default: return X86::COND_INVALID;
3792 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3793 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3794 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3795 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3796 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3797 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3798 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3799 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3800 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3801 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3802 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3803 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3804 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3805 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3806 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3807 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3808 }
3809}
3810
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3811/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3812X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3813 switch (Opc) {
3814 default: return X86::COND_INVALID;
3815 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3816 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3817 return X86::COND_A;
3818 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3819 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3820 return X86::COND_AE;
3821 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3822 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3823 return X86::COND_B;
3824 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3825 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3826 return X86::COND_BE;
3827 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3828 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3829 return X86::COND_E;
3830 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3831 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3832 return X86::COND_G;
3833 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3834 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3835 return X86::COND_GE;
3836 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3837 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3838 return X86::COND_L;
3839 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3840 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3841 return X86::COND_LE;
3842 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3843 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3844 return X86::COND_NE;
3845 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3846 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3847 return X86::COND_NO;
3848 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3849 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3850 return X86::COND_NP;
3851 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3852 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3853 return X86::COND_NS;
3854 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3855 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3856 return X86::COND_O;
3857 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3858 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3859 return X86::COND_P;
3860 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3861 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3862 return X86::COND_S;
3863 }
3864}
3865
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3866unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3867 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3868 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3869 case X86::COND_E: return X86::JE_1;
3870 case X86::COND_NE: return X86::JNE_1;
3871 case X86::COND_L: return X86::JL_1;
3872 case X86::COND_LE: return X86::JLE_1;
3873 case X86::COND_G: return X86::JG_1;
3874 case X86::COND_GE: return X86::JGE_1;
3875 case X86::COND_B: return X86::JB_1;
3876 case X86::COND_BE: return X86::JBE_1;
3877 case X86::COND_A: return X86::JA_1;
3878 case X86::COND_AE: return X86::JAE_1;
3879 case X86::COND_S: return X86::JS_1;
3880 case X86::COND_NS: return X86::JNS_1;
3881 case X86::COND_P: return X86::JP_1;
3882 case X86::COND_NP: return X86::JNP_1;
3883 case X86::COND_O: return X86::JO_1;
3884 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3885 }
3886}
3887
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3888/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3889/// e.g. turning COND_E to COND_NE.
3890X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3891 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3892 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3893 case X86::COND_E: return X86::COND_NE;
3894 case X86::COND_NE: return X86::COND_E;
3895 case X86::COND_L: return X86::COND_GE;
3896 case X86::COND_LE: return X86::COND_G;
3897 case X86::COND_G: return X86::COND_LE;
3898 case X86::COND_GE: return X86::COND_L;
3899 case X86::COND_B: return X86::COND_AE;
3900 case X86::COND_BE: return X86::COND_A;
3901 case X86::COND_A: return X86::COND_BE;
3902 case X86::COND_AE: return X86::COND_B;
3903 case X86::COND_S: return X86::COND_NS;
3904 case X86::COND_NS: return X86::COND_S;
3905 case X86::COND_P: return X86::COND_NP;
3906 case X86::COND_NP: return X86::COND_P;
3907 case X86::COND_O: return X86::COND_NO;
3908 case X86::COND_NO: return X86::COND_O;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3909 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
3910 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3911 }
3912}
3913
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3914/// Assuming the flags are set by MI(a,b), return the condition code if we
3915/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3916static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3917 switch (CC) {
3918 default: return X86::COND_INVALID;
3919 case X86::COND_E: return X86::COND_E;
3920 case X86::COND_NE: return X86::COND_NE;
3921 case X86::COND_L: return X86::COND_G;
3922 case X86::COND_LE: return X86::COND_GE;
3923 case X86::COND_G: return X86::COND_L;
3924 case X86::COND_GE: return X86::COND_LE;
3925 case X86::COND_B: return X86::COND_A;
3926 case X86::COND_BE: return X86::COND_AE;
3927 case X86::COND_A: return X86::COND_B;
3928 case X86::COND_AE: return X86::COND_BE;
3929 }
3930}
3931
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3932/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3933/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3934unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3935 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3936 { X86::SETAr, X86::SETAm },
3937 { X86::SETAEr, X86::SETAEm },
3938 { X86::SETBr, X86::SETBm },
3939 { X86::SETBEr, X86::SETBEm },
3940 { X86::SETEr, X86::SETEm },
3941 { X86::SETGr, X86::SETGm },
3942 { X86::SETGEr, X86::SETGEm },
3943 { X86::SETLr, X86::SETLm },
3944 { X86::SETLEr, X86::SETLEm },
3945 { X86::SETNEr, X86::SETNEm },
3946 { X86::SETNOr, X86::SETNOm },
3947 { X86::SETNPr, X86::SETNPm },
3948 { X86::SETNSr, X86::SETNSm },
3949 { X86::SETOr, X86::SETOm },
3950 { X86::SETPr, X86::SETPm },
3951 { X86::SETSr, X86::SETSm }
3952 };
3953
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3954 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3955 return Opc[CC][HasMemoryOperand ? 1 : 0];
3956}
3957
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3958/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3959/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3960unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3961 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3962 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3963 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3964 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3965 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3966 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3967 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3968 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3969 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3970 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3971 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3972 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3973 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3974 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3975 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3976 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3977 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3978 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3979 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3980 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3981 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3982 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3983 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3984 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3985 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3986 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3987 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3988 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3989 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3990 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3991 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3992 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3993 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3994 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3995 };
3996
3997 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3998 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3999 switch(RegBytes) {
4000 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4001 case 2: return Opc[Idx][0];
4002 case 4: return Opc[Idx][1];
4003 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4004 }
4005}
4006
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4007bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4008 if (!MI.isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4009
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4010 // Conditional branch is a special case.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4011 if (MI.isBranch() && !MI.isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4012 return true;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4013 if (!MI.isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4014 return true;
4015 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]4016}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4017
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4018// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
4019// not be a fallthrough MBB now due to layout changes). Return nullptr if the
4020// fallthrough MBB cannot be identified.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4021static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
4022 MachineBasicBlock *TBB) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4023 // Look for non-EHPad successors other than TBB. If we find exactly one, it
4024 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
4025 // and fallthrough MBB. If we find more than one, we cannot identify the
4026 // fallthrough MBB and should return nullptr.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4027 MachineBasicBlock *FallthroughBB = nullptr;
4028 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4029 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4030 continue;
4031 // Return a nullptr if we found more than one fallthrough successor.
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4032 if (FallthroughBB && FallthroughBB != TBB)
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4033 return nullptr;
4034 FallthroughBB = *SI;
4035 }
4036 return FallthroughBB;
4037}
4038
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4039bool X86InstrInfo::AnalyzeBranchImpl(
4040 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
4041 SmallVectorImpl<MachineOperand> &Cond,
4042 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
4043
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4044 // Start from the bottom of the block and work up, examining the
4045 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4046 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4047 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4048 while (I != MBB.begin()) {
4049 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4050 if (I->isDebugValue())
4051 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4052
4053 // Working from the bottom, when we see a non-terminator instruction, we're
4054 // done.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4055 if (!isUnpredicatedTerminator(*I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4056 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4057
4058 // A terminator that isn't a branch can't easily be handled by this
4059 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]4060 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4061 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4062
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4063 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4064 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4065 UnCondBrIter = I;
4066
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4067 if (!AllowModify) {
4068 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]4069 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4070 }
4071
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4072 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]4073 while (std::next(I) != MBB.end())
4074 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4075
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4076 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4077 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4078
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4079 // Delete the JMP if it's equivalent to a fall-through.
4080 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4081 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4082 I->eraseFromParent();
4083 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4084 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4085 continue;
4086 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4087
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4088 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4089 TBB = I->getOperand(0).getMBB();
4090 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4091 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4092
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4093 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4094 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4095 if (BranchCode == X86::COND_INVALID)
4096 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4097
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4098 // Working from the bottom, handle the first conditional branch.
4099 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4100 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4101 if (AllowModify && UnCondBrIter != MBB.end() &&
4102 MBB.isLayoutSuccessor(TargetBB)) {
4103 // If we can modify the code and it ends in something like:
4104 //
4105 // jCC L1
4106 // jmp L2
4107 // L1:
4108 // ...
4109 // L2:
4110 //
4111 // Then we can change this to:
4112 //
4113 // jnCC L2
4114 // L1:
4115 // ...
4116 // L2:
4117 //
4118 // Which is a bit more efficient.
4119 // We conditionally jump to the fall-through block.
4120 BranchCode = GetOppositeBranchCondition(BranchCode);
4121 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4122 MachineBasicBlock::iterator OldInst = I;
4123
4124 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4125 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4126 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4127 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4128
4129 OldInst->eraseFromParent();
4130 UnCondBrIter->eraseFromParent();
4131
4132 // Restart the analysis.
4133 UnCondBrIter = MBB.end();
4134 I = MBB.end();
4135 continue;
4136 }
4137
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4138 FBB = TBB;
4139 TBB = I->getOperand(0).getMBB();
4140 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4141 CondBranches.push_back(&*I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4142 continue;
4143 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4144
4145 // Handle subsequent conditional branches. Only handle the case where all
4146 // conditional branches branch to the same destination and their condition
4147 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4148 assert(Cond.size() == 1);
4149 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4150
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4151 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4152 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4153 auto NewTBB = I->getOperand(0).getMBB();
4154 if (OldBranchCode == BranchCode && TBB == NewTBB)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4155 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4156
4157 // If they differ, see if they fit one of the known patterns. Theoretically,
4158 // we could handle more patterns here, but we shouldn't expect to see them
4159 // if instruction selection has done a reasonable job.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4160 if (TBB == NewTBB &&
4161 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4162 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4163 BranchCode = X86::COND_NE_OR_P;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4164 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4165 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4166 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4167 return true;
4168
4169 // X86::COND_E_AND_NP usually has two different branch destinations.
4170 //
4171 // JP B1
4172 // JE B2
4173 // JMP B1
4174 // B1:
4175 // B2:
4176 //
4177 // Here this condition branches to B2 only if NP && E. It has another
4178 // equivalent form:
4179 //
4180 // JNE B1
4181 // JNP B2
4182 // JMP B1
4183 // B1:
4184 // B2:
4185 //
4186 // Similarly it branches to B2 only if E && NP. That is why this condition
4187 // is named with COND_E_AND_NP.
4188 BranchCode = X86::COND_E_AND_NP;
4189 } else
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4190 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4191
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4192 // Update the MachineOperand.
4193 Cond[0].setImm(BranchCode);
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4194 CondBranches.push_back(&*I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4195 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4196
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4197 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4198}
4199
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4200bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4201 MachineBasicBlock *&TBB,
4202 MachineBasicBlock *&FBB,
4203 SmallVectorImpl<MachineOperand> &Cond,
4204 bool AllowModify) const {
4205 SmallVector<MachineInstr *, 4> CondBranches;
4206 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4207}
4208
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4209bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4210 MachineBranchPredicate &MBP,
4211 bool AllowModify) const {
4212 using namespace std::placeholders;
4213
4214 SmallVector<MachineOperand, 4> Cond;
4215 SmallVector<MachineInstr *, 4> CondBranches;
4216 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4217 AllowModify))
4218 return true;
4219
4220 if (Cond.size() != 1)
4221 return true;
4222
4223 assert(MBP.TrueDest && "expected!");
4224
4225 if (!MBP.FalseDest)
4226 MBP.FalseDest = MBB.getNextNode();
4227
4228 const TargetRegisterInfo *TRI = &getRegisterInfo();
4229
4230 MachineInstr *ConditionDef = nullptr;
4231 bool SingleUseCondition = true;
4232
4233 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4234 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4235 ConditionDef = &*I;
4236 break;
4237 }
4238
4239 if (I->readsRegister(X86::EFLAGS, TRI))
4240 SingleUseCondition = false;
4241 }
4242
4243 if (!ConditionDef)
4244 return true;
4245
4246 if (SingleUseCondition) {
4247 for (auto *Succ : MBB.successors())
4248 if (Succ->isLiveIn(X86::EFLAGS))
4249 SingleUseCondition = false;
4250 }
4251
4252 MBP.ConditionDef = ConditionDef;
4253 MBP.SingleUseCondition = SingleUseCondition;
4254
4255 // Currently we only recognize the simple pattern:
4256 //
4257 // test %reg, %reg
4258 // je %label
4259 //
4260 const unsigned TestOpcode =
4261 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4262
4263 if (ConditionDef->getOpcode() == TestOpcode &&
4264 ConditionDef->getNumOperands() == 3 &&
4265 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4266 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4267 MBP.LHS = ConditionDef->getOperand(0);
4268 MBP.RHS = MachineOperand::CreateImm(0);
4269 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4270 ? MachineBranchPredicate::PRED_NE
4271 : MachineBranchPredicate::PRED_EQ;
4272 return false;
4273 }
4274
4275 return true;
4276}
4277
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4278unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4279 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4280 unsigned Count = 0;
4281
4282 while (I != MBB.begin()) {
4283 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4284 if (I->isDebugValue())
4285 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4286 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4287 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4288 break;
4289 // Remove the branch.
4290 I->eraseFromParent();
4291 I = MBB.end();
4292 ++Count;
4293 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4294
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4295 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4296}
4297
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4298unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4299 MachineBasicBlock *TBB,
4300 MachineBasicBlock *FBB,
4301 ArrayRef<MachineOperand> Cond,
4302 const DebugLoc &DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4303 // Shouldn't be a fall through.
4304 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4305 assert((Cond.size() == 1 || Cond.size() == 0) &&
4306 "X86 branch conditions have one component!");
4307
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4308 if (Cond.empty()) {
4309 // Unconditional branch?
4310 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4311 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4312 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4313 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4314
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4315 // If FBB is null, it is implied to be a fall-through block.
4316 bool FallThru = FBB == nullptr;
4317
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4318 // Conditional branch.
4319 unsigned Count = 0;
4320 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4321 switch (CC) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4322 case X86::COND_NE_OR_P:
4323 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4324 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4325 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4326 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4327 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4328 break;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4329 case X86::COND_E_AND_NP:
4330 // Use the next block of MBB as FBB if it is null.
4331 if (FBB == nullptr) {
4332 FBB = getFallThroughMBB(&MBB, TBB);
4333 assert(FBB && "MBB cannot be the last block in function when the false "
4334 "body is a fall-through.");
4335 }
4336 // Synthesize COND_E_AND_NP with two branches.
4337 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4338 ++Count;
4339 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4340 ++Count;
4341 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4342 default: {
4343 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4344 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4345 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4346 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4347 }
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4348 if (!FallThru) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4349 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4350 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4351 ++Count;
4352 }
4353 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4354}
4355
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4356bool X86InstrInfo::
4357canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4358 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4359 unsigned TrueReg, unsigned FalseReg,
4360 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4361 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4362 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4363 return false;
4364 if (Cond.size() != 1)
4365 return false;
4366 // We cannot do the composite conditions, at least not in SSA form.
4367 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4368 return false;
4369
4370 // Check register classes.
4371 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4372 const TargetRegisterClass *RC =
4373 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4374 if (!RC)
4375 return false;
4376
4377 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4378 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4379 X86::GR32RegClass.hasSubClassEq(RC) ||
4380 X86::GR64RegClass.hasSubClassEq(RC)) {
4381 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4382 // Bridge. Probably Ivy Bridge as well.
4383 CondCycles = 2;
4384 TrueCycles = 2;
4385 FalseCycles = 2;
4386 return true;
4387 }
4388
4389 // Can't do vectors.
4390 return false;
4391}
4392
4393void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4394 MachineBasicBlock::iterator I,
4395 const DebugLoc &DL, unsigned DstReg,
4396 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4397 unsigned FalseReg) const {
4398 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4399 assert(Cond.size() == 1 && "Invalid Cond array");
4400 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4401 MRI.getRegClass(DstReg)->getSize(),
4402 false /*HasMemoryOperand*/);
4403 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4404}
4405
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4406/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4407static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4408 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4409}
4410
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4411// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4412static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4413 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4414
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4415 // SrcReg(VR128) -> DestReg(GR64)
4416 // SrcReg(VR64) -> DestReg(GR64)
4417 // SrcReg(GR64) -> DestReg(VR128)
4418 // SrcReg(GR64) -> DestReg(VR64)
4419
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4420 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4421 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4422 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4423 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4424 // Copy from a VR128 register to a GR64 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4425 return HasAVX512 ? X86::VMOVPQIto64Zrr :
4426 HasAVX ? X86::VMOVPQIto64rr :
4427 X86::MOVPQIto64rr;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4428 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4429 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4430 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4431 } else if (X86::GR64RegClass.contains(SrcReg)) {
4432 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4433 if (X86::VR128XRegClass.contains(DestReg))
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4434 return HasAVX512 ? X86::VMOV64toPQIZrr :
4435 HasAVX ? X86::VMOV64toPQIrr :
4436 X86::MOV64toPQIrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4437 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4438 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4439 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4440 }
4441
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4442 // SrcReg(FR32) -> DestReg(GR32)
4443 // SrcReg(GR32) -> DestReg(FR32)
4444
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4445 if (X86::GR32RegClass.contains(DestReg) &&
4446 X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4447 // Copy from a FR32 register to a GR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4448 return HasAVX512 ? X86::VMOVSS2DIZrr :
4449 HasAVX ? X86::VMOVSS2DIrr :
4450 X86::MOVSS2DIrr;
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4451
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4452 if (X86::FR32XRegClass.contains(DestReg) &&
4453 X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4454 // Copy from a GR32 register to a FR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4455 return HasAVX512 ? X86::VMOVDI2SSZrr :
4456 HasAVX ? X86::VMOVDI2SSrr :
4457 X86::MOVDI2SSrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4458 return 0;
4459}
4460
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4461static bool isMaskRegClass(const TargetRegisterClass *RC) {
4462 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4463 return X86::VK16RegClass.hasSubClassEq(RC);
4464}
4465
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4466static bool MaskRegClassContains(unsigned Reg) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4467 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4468 return X86::VK16RegClass.contains(Reg);
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4469}
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4470
4471static bool GRRegClassContains(unsigned Reg) {
4472 return X86::GR64RegClass.contains(Reg) ||
4473 X86::GR32RegClass.contains(Reg) ||
4474 X86::GR16RegClass.contains(Reg) ||
4475 X86::GR8RegClass.contains(Reg);
4476}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4477static
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4478unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4479 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4480 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4481 return X86::KMOVBrk;
4482 }
4483 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4484 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4485 return X86::KMOVBkr;
4486 }
4487 return 0;
4488}
4489
4490static
4491unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4492 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4493 return X86::KMOVQkk;
4494 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4495 return X86::KMOVDrk;
4496 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4497 return X86::KMOVQrk;
4498 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4499 return X86::KMOVDkr;
4500 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4501 return X86::KMOVQkr;
4502 return 0;
4503}
4504
4505static
4506unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4507 const X86Subtarget &Subtarget)
4508{
4509 if (Subtarget.hasDQI())
4510 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4511 return Opc;
4512 if (Subtarget.hasBWI())
4513 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4514 return Opc;
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4515 if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
4516 if (Subtarget.hasVLX())
4517 return X86::VMOVAPSZ128rr;
4518 DestReg = get512BitSuperRegister(DestReg);
4519 SrcReg = get512BitSuperRegister(SrcReg);
4520 return X86::VMOVAPSZrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4521 }
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4522 if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
4523 if (Subtarget.hasVLX())
4524 return X86::VMOVAPSZ256rr;
4525 DestReg = get512BitSuperRegister(DestReg);
4526 SrcReg = get512BitSuperRegister(SrcReg);
4527 return X86::VMOVAPSZrr;
4528 }
4529 if (X86::VR512RegClass.contains(DestReg, SrcReg))
4530 return X86::VMOVAPSZrr;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4531 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4532 return X86::KMOVWkk;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4533 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4534 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4535 return X86::KMOVWkr;
4536 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4537 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4538 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4539 return X86::KMOVWrk;
4540 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4541 return 0;
4542}
4543
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4544void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4545 MachineBasicBlock::iterator MI,
4546 const DebugLoc &DL, unsigned DestReg,
4547 unsigned SrcReg, bool KillSrc) const {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4548 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4549 bool HasAVX = Subtarget.hasAVX();
4550 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4551 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4552 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4553 Opc = X86::MOV64rr;
4554 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4555 Opc = X86::MOV32rr;
4556 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4557 Opc = X86::MOV16rr;
4558 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4559 // Copying to or from a physical H register on x86-64 requires a NOREX
4560 // move. Otherwise use a normal move.
4561 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4562 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4563 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4564 // Both operands must be encodable without an REX prefix.
4565 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4566 "8-bit H register can not be copied outside GR8_NOREX");
4567 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4568 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4569 }
4570 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4571 Opc = X86::MMX_MOVQ64rr;
4572 else if (HasAVX512)
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4573 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4574 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4575 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4576 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4577 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4578 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4579 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4580
4581 if (Opc) {
4582 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4583 .addReg(SrcReg, getKillRegState(KillSrc));
4584 return;
4585 }
4586
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4587 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4588 bool ToEFLAGS = DestReg == X86::EFLAGS;
4589 int Reg = FromEFLAGS ? DestReg : SrcReg;
4590 bool is32 = X86::GR32RegClass.contains(Reg);
4591 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4592
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4593 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4594 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4595 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4596 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4597 int Pop = is64 ? X86::POP64r : X86::POP32r;
4598 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4599 int AX = is64 ? X86::RAX : X86::EAX;
4600
4601 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4602 assert(Subtarget.is64Bit() &&
4603 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4604 // Moving EFLAGS to / from another register requires a push and a pop.
4605 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemer33467632015-12-27 06:07:26 +0000[diff] [blame]4606 // first frame index. See X86FrameLowering.cpp - usesTheStack.
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4607 if (FromEFLAGS) {
4608 BuildMI(MBB, MI, DL, get(PushF));
4609 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4610 }
4611 if (ToEFLAGS) {
4612 BuildMI(MBB, MI, DL, get(Push))
4613 .addReg(SrcReg, getKillRegState(KillSrc));
4614 BuildMI(MBB, MI, DL, get(PopF));
4615 }
4616 return;
4617 }
4618
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4619 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4620 // inefficient. Instead:
4621 // - Save the overflow flag OF into AL using SETO, and restore it using a
4622 // signed 8-bit addition of AL and INT8_MAX.
4623 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4624 // using LAHF/SAHF.
4625 // - When RAX/EAX is live and isn't the destination register, make sure it
4626 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4627 // the flags.
4628 // This approach is ~2.25x faster than using PUSHF/POPF.
4629 //
4630 // This is still somewhat inefficient because we don't know which flags are
4631 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4632 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4633 //
4634 // PUSHF/POPF is also potentially incorrect because it affects other flags
4635 // such as TF/IF/DF, which LLVM doesn't model.
4636 //
4637 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemerca1c9f02016-01-04 04:49:41 +0000[diff] [blame]4638 // first frame index.
4639 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4640
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4641 const TargetRegisterInfo *TRI = &getRegisterInfo();
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4642 MachineBasicBlock::LivenessQueryResult LQR =
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4643 MBB.computeRegisterLiveness(TRI, AX, MI);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4644 // We do not want to save and restore AX if we do not have to.
4645 // Moreover, if we do so whereas AX is dead, we would need to set
4646 // an undef flag on the use of AX, otherwise the verifier will
4647 // complain that we read an undef value.
4648 // We do not want to change the behavior of the machine verifier
4649 // as this is usually wrong to read an undef value.
4650 if (MachineBasicBlock::LQR_Unknown == LQR) {
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4651 LivePhysRegs LPR(TRI);
Matthias Braund1aabb22016-05-03 00:24:32 +0000[diff] [blame]4652 LPR.addLiveOuts(MBB);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4653 MachineBasicBlock::iterator I = MBB.end();
4654 while (I != MI) {
4655 --I;
4656 LPR.stepBackward(*I);
4657 }
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4658 // AX contains the top most register in the aliasing hierarchy.
4659 // It may not be live, but one of its aliases may be.
4660 for (MCRegAliasIterator AI(AX, TRI, true);
4661 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4662 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4663 : MachineBasicBlock::LQR_Dead;
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4664 }
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4665 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4666 if (!AXDead)
4667 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4668 if (FromEFLAGS) {
4669 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4670 BuildMI(MBB, MI, DL, get(X86::LAHF));
4671 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4672 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4673 if (ToEFLAGS) {
4674 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4675 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4676 .addReg(X86::AL)
4677 .addImm(INT8_MAX);
4678 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4679 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4680 if (!AXDead)
4681 BuildMI(MBB, MI, DL, get(Pop), AX);
4682 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4683 }
4684
4685 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4686 << " to " << RI.getName(DestReg) << '\n');
4687 llvm_unreachable("Cannot emit physreg copy instruction");
4688}
4689
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4690static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4691 bool load) {
4692 switch (RC->getSize()) {
4693 default:
4694 llvm_unreachable("Unknown spill size");
4695 case 2:
4696 return load ? X86::KMOVWkm : X86::KMOVWmk;
4697 case 4:
4698 return load ? X86::KMOVDkm : X86::KMOVDmk;
4699 case 8:
4700 return load ? X86::KMOVQkm : X86::KMOVQmk;
4701 }
4702}
4703
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4704static unsigned getLoadStoreRegOpcode(unsigned Reg,
4705 const TargetRegisterClass *RC,
4706 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4707 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4708 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4709 if (STI.hasAVX512()) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4710 if (isMaskRegClass(RC))
4711 return getLoadStoreMaskRegOpcode(RC, load);
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4712 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4713 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4714 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4715 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4716 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4717 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4718 }
4719
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4720 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4721 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4722 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4723 llvm_unreachable("Unknown spill size");
4724 case 1:
4725 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4726 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4727 // Copying to or from a physical H register on x86-64 requires a NOREX
4728 // move. Otherwise use a normal move.
4729 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4730 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4731 return load ? X86::MOV8rm : X86::MOV8mr;
4732 case 2:
4733 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4734 return load ? X86::MOV16rm : X86::MOV16mr;
4735 case 4:
4736 if (X86::GR32RegClass.hasSubClassEq(RC))
4737 return load ? X86::MOV32rm : X86::MOV32mr;
4738 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4739 return load ?
4740 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4741 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4742 if (X86::RFP32RegClass.hasSubClassEq(RC))
4743 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4744 llvm_unreachable("Unknown 4-byte regclass");
4745 case 8:
4746 if (X86::GR64RegClass.hasSubClassEq(RC))
4747 return load ? X86::MOV64rm : X86::MOV64mr;
4748 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4749 return load ?
4750 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4751 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4752 if (X86::VR64RegClass.hasSubClassEq(RC))
4753 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4754 if (X86::RFP64RegClass.hasSubClassEq(RC))
4755 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4756 llvm_unreachable("Unknown 8-byte regclass");
4757 case 10:
4758 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4759 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4760 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4761 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4762 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4763 // If stack is realigned we can use aligned stores.
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4764 if (X86::VR128RegClass.hasSubClassEq(RC)) {
4765 if (isStackAligned)
4766 return load ? (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
4767 : (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4768 else
4769 return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
4770 : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4771 }
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4772 assert(STI.hasVLX() && "Using extended register requires VLX");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4773 if (isStackAligned)
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4774 return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4775 else
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4776 return load ? X86::VMOVUPSZ128rm : X86::VMOVUPSZ128mr;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4777 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4778 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4779 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4780 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4781 // If stack is realigned we can use aligned stores.
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4782 if (X86::VR256RegClass.hasSubClassEq(RC)) {
4783 if (isStackAligned)
4784 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4785 else
4786 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4787 }
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4788 assert(STI.hasVLX() && "Using extended register requires VLX");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4789 if (isStackAligned)
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4790 return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4791 else
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4792 return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4793 case 64:
4794 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4795 assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4796 if (isStackAligned)
4797 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4798 else
4799 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4800 }
4801}
4802
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4803bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
Chad Rosierc27a18f2016-03-09 16:00:35 +0000[diff] [blame]4804 int64_t &Offset,
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4805 const TargetRegisterInfo *TRI) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4806 const MCInstrDesc &Desc = MemOp.getDesc();
Craig Topper477649a2016-04-28 05:58:46 +0000[diff] [blame]4807 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4808 if (MemRefBegin < 0)
4809 return false;
4810
4811 MemRefBegin += X86II::getOperandBias(Desc);
4812
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4813 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
Sanjoy Das881de4d2016-02-02 02:32:43 +0000[diff] [blame]4814 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4815 return false;
4816
4817 BaseReg = BaseMO.getReg();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4818 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4819 return false;
4820
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4821 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4822 X86::NoRegister)
4823 return false;
4824
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4825 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4826
4827 // Displacement can be symbolic
4828 if (!DispMO.isImm())
4829 return false;
4830
4831 Offset = DispMO.getImm();
4832
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4833 return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4834 X86::NoRegister;
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4835}
4836
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4837static unsigned getStoreRegOpcode(unsigned SrcReg,
4838 const TargetRegisterClass *RC,
4839 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4840 const X86Subtarget &STI) {
4841 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4842}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4843
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4844
4845static unsigned getLoadRegOpcode(unsigned DestReg,
4846 const TargetRegisterClass *RC,
4847 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4848 const X86Subtarget &STI) {
4849 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4850}
4851
4852void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4853 MachineBasicBlock::iterator MI,
4854 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4855 const TargetRegisterClass *RC,
4856 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4857 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4858 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4859 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4860 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4861 bool isAligned =
4862 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4863 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4864 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4865 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4866 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4867 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4868}
4869
4870void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4871 bool isKill,
4872 SmallVectorImpl<MachineOperand> &Addr,
4873 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4874 MachineInstr::mmo_iterator MMOBegin,
4875 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4876 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4877 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4878 bool isAligned = MMOBegin != MMOEnd &&
4879 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4880 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4881 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4882 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4883 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4884 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4885 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4886 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4887 NewMIs.push_back(MIB);
4888}
4889
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4890
4891void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4892 MachineBasicBlock::iterator MI,
4893 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4894 const TargetRegisterClass *RC,
4895 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4896 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4897 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4898 bool isAligned =
4899 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4900 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4901 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4902 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4903 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4904}
4905
4906void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4907 SmallVectorImpl<MachineOperand> &Addr,
4908 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4909 MachineInstr::mmo_iterator MMOBegin,
4910 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4911 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4912 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4913 bool isAligned = MMOBegin != MMOEnd &&
4914 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4915 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4916 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4917 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4918 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4919 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4920 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4921 NewMIs.push_back(MIB);
4922}
4923
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4924bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
4925 unsigned &SrcReg2, int &CmpMask,
4926 int &CmpValue) const {
4927 switch (MI.getOpcode()) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4928 default: break;
4929 case X86::CMP64ri32:
4930 case X86::CMP64ri8:
4931 case X86::CMP32ri:
4932 case X86::CMP32ri8:
4933 case X86::CMP16ri:
4934 case X86::CMP16ri8:
4935 case X86::CMP8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4936 SrcReg = MI.getOperand(0).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4937 SrcReg2 = 0;
4938 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4939 CmpValue = MI.getOperand(1).getImm();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4940 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4941 // A SUB can be used to perform comparison.
4942 case X86::SUB64rm:
4943 case X86::SUB32rm:
4944 case X86::SUB16rm:
4945 case X86::SUB8rm:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4946 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4947 SrcReg2 = 0;
4948 CmpMask = ~0;
4949 CmpValue = 0;
4950 return true;
4951 case X86::SUB64rr:
4952 case X86::SUB32rr:
4953 case X86::SUB16rr:
4954 case X86::SUB8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4955 SrcReg = MI.getOperand(1).getReg();
4956 SrcReg2 = MI.getOperand(2).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4957 CmpMask = ~0;
4958 CmpValue = 0;
4959 return true;
4960 case X86::SUB64ri32:
4961 case X86::SUB64ri8:
4962 case X86::SUB32ri:
4963 case X86::SUB32ri8:
4964 case X86::SUB16ri:
4965 case X86::SUB16ri8:
4966 case X86::SUB8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4967 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4968 SrcReg2 = 0;
4969 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4970 CmpValue = MI.getOperand(2).getImm();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4971 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4972 case X86::CMP64rr:
4973 case X86::CMP32rr:
4974 case X86::CMP16rr:
4975 case X86::CMP8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4976 SrcReg = MI.getOperand(0).getReg();
4977 SrcReg2 = MI.getOperand(1).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4978 CmpMask = ~0;
4979 CmpValue = 0;
4980 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4981 case X86::TEST8rr:
4982 case X86::TEST16rr:
4983 case X86::TEST32rr:
4984 case X86::TEST64rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4985 SrcReg = MI.getOperand(0).getReg();
4986 if (MI.getOperand(1).getReg() != SrcReg)
4987 return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4988 // Compare against zero.
4989 SrcReg2 = 0;
4990 CmpMask = ~0;
4991 CmpValue = 0;
4992 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4993 }
4994 return false;
4995}
4996
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4997/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4998/// purpose is to update flags, can be made redundant.
4999/// CMPrr can be made redundant by SUBrr if the operands are the same.
5000/// This function can be extended later on.
5001/// SrcReg, SrcRegs: register operands for FlagI.
5002/// ImmValue: immediate for FlagI if it takes an immediate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5003inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5004 unsigned SrcReg2, int ImmValue,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5005 MachineInstr &OI) {
5006 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
5007 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
5008 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
5009 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
5010 ((OI.getOperand(1).getReg() == SrcReg &&
5011 OI.getOperand(2).getReg() == SrcReg2) ||
5012 (OI.getOperand(1).getReg() == SrcReg2 &&
5013 OI.getOperand(2).getReg() == SrcReg)))
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5014 return true;
5015
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5016 if (((FlagI.getOpcode() == X86::CMP64ri32 &&
5017 OI.getOpcode() == X86::SUB64ri32) ||
5018 (FlagI.getOpcode() == X86::CMP64ri8 &&
5019 OI.getOpcode() == X86::SUB64ri8) ||
5020 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
5021 (FlagI.getOpcode() == X86::CMP32ri8 &&
5022 OI.getOpcode() == X86::SUB32ri8) ||
5023 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
5024 (FlagI.getOpcode() == X86::CMP16ri8 &&
5025 OI.getOpcode() == X86::SUB16ri8) ||
5026 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
5027 OI.getOperand(1).getReg() == SrcReg &&
5028 OI.getOperand(2).getImm() == ImmValue)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5029 return true;
5030 return false;
5031}
5032
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5033/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5034/// to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5035inline static bool isDefConvertible(MachineInstr &MI) {
5036 switch (MI.getOpcode()) {
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5037 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]5038
5039 // The shift instructions only modify ZF if their shift count is non-zero.
5040 // N.B.: The processor truncates the shift count depending on the encoding.
5041 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
5042 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
5043 return getTruncatedShiftCount(MI, 2) != 0;
5044
5045 // Some left shift instructions can be turned into LEA instructions but only
5046 // if their flags aren't used. Avoid transforming such instructions.
5047 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
5048 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
5049 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
5050 return ShAmt != 0;
5051 }
5052
5053 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
5054 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
5055 return getTruncatedShiftCount(MI, 3) != 0;
5056
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5057 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
5058 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
5059 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
5060 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
5061 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5062 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5063 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
5064 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
5065 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
5066 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
5067 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5068 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5069 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
5070 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
5071 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
5072 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
5073 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
5074 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
5075 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
5076 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
5077 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
5078 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
5079 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
5080 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
5081 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
5082 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
5083 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5084 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
5085 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
5086 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
5087 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
5088 case X86::ADC32ri: case X86::ADC32ri8:
5089 case X86::ADC32rr: case X86::ADC64ri32:
5090 case X86::ADC64ri8: case X86::ADC64rr:
5091 case X86::SBB32ri: case X86::SBB32ri8:
5092 case X86::SBB32rr: case X86::SBB64ri32:
5093 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]5094 case X86::ANDN32rr: case X86::ANDN32rm:
5095 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5096 case X86::BEXTR32rr: case X86::BEXTR64rr:
5097 case X86::BEXTR32rm: case X86::BEXTR64rm:
5098 case X86::BLSI32rr: case X86::BLSI32rm:
5099 case X86::BLSI64rr: case X86::BLSI64rm:
5100 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5101 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5102 case X86::BLSR32rr: case X86::BLSR32rm:
5103 case X86::BLSR64rr: case X86::BLSR64rm:
5104 case X86::BZHI32rr: case X86::BZHI32rm:
5105 case X86::BZHI64rr: case X86::BZHI64rm:
5106 case X86::LZCNT16rr: case X86::LZCNT16rm:
5107 case X86::LZCNT32rr: case X86::LZCNT32rm:
5108 case X86::LZCNT64rr: case X86::LZCNT64rm:
5109 case X86::POPCNT16rr:case X86::POPCNT16rm:
5110 case X86::POPCNT32rr:case X86::POPCNT32rm:
5111 case X86::POPCNT64rr:case X86::POPCNT64rm:
5112 case X86::TZCNT16rr: case X86::TZCNT16rm:
5113 case X86::TZCNT32rr: case X86::TZCNT32rm:
5114 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5115 return true;
5116 }
5117}
5118
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5119/// Check whether the use can be converted to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5120static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5121 switch (MI.getOpcode()) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5122 default: return X86::COND_INVALID;
5123 case X86::LZCNT16rr: case X86::LZCNT16rm:
5124 case X86::LZCNT32rr: case X86::LZCNT32rm:
5125 case X86::LZCNT64rr: case X86::LZCNT64rm:
5126 return X86::COND_B;
5127 case X86::POPCNT16rr:case X86::POPCNT16rm:
5128 case X86::POPCNT32rr:case X86::POPCNT32rm:
5129 case X86::POPCNT64rr:case X86::POPCNT64rm:
5130 return X86::COND_E;
5131 case X86::TZCNT16rr: case X86::TZCNT16rm:
5132 case X86::TZCNT32rr: case X86::TZCNT32rm:
5133 case X86::TZCNT64rr: case X86::TZCNT64rm:
5134 return X86::COND_B;
5135 }
5136}
5137
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5138/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5139/// operates on the same source operands and sets flags in the same way as
5140/// Compare; remove Compare if possible.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5141bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5142 unsigned SrcReg2, int CmpMask,
5143 int CmpValue,
5144 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5145 // Check whether we can replace SUB with CMP.
5146 unsigned NewOpcode = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5147 switch (CmpInstr.getOpcode()) {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5148 default: break;
5149 case X86::SUB64ri32:
5150 case X86::SUB64ri8:
5151 case X86::SUB32ri:
5152 case X86::SUB32ri8:
5153 case X86::SUB16ri:
5154 case X86::SUB16ri8:
5155 case X86::SUB8ri:
5156 case X86::SUB64rm:
5157 case X86::SUB32rm:
5158 case X86::SUB16rm:
5159 case X86::SUB8rm:
5160 case X86::SUB64rr:
5161 case X86::SUB32rr:
5162 case X86::SUB16rr:
5163 case X86::SUB8rr: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5164 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5165 return false;
5166 // There is no use of the destination register, we can replace SUB with CMP.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5167 switch (CmpInstr.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5168 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5169 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5170 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5171 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5172 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5173 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5174 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5175 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5176 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5177 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5178 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5179 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5180 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5181 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5182 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5183 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5184 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5185 CmpInstr.setDesc(get(NewOpcode));
5186 CmpInstr.RemoveOperand(0);
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5187 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5188 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5189 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5190 return false;
5191 }
5192 }
5193
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5194 // Get the unique definition of SrcReg.
5195 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5196 if (!MI) return false;
5197
5198 // CmpInstr is the first instruction of the BB.
5199 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5200
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5201 // If we are comparing against zero, check whether we can use MI to update
5202 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5203 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5204 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5205 return false;
5206
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5207 // If we have a use of the source register between the def and our compare
5208 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5209 // right way.
5210 bool ShouldUpdateCC = false;
5211 X86::CondCode NewCC = X86::COND_INVALID;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5212 if (IsCmpZero && !isDefConvertible(*MI)) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5213 // Scan forward from the use until we hit the use we're looking for or the
5214 // compare instruction.
5215 for (MachineBasicBlock::iterator J = MI;; ++J) {
5216 // Do we have a convertible instruction?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5217 NewCC = isUseDefConvertible(*J);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5218 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5219 J->getOperand(1).getReg() == SrcReg) {
5220 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5221 ShouldUpdateCC = true; // Update CC later on.
5222 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5223 // with the new def.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]5224 Def = J;
5225 MI = &*Def;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5226 break;
5227 }
5228
5229 if (J == I)
5230 return false;
5231 }
5232 }
5233
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5234 // We are searching for an earlier instruction that can make CmpInstr
5235 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5236 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5237 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5238
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5239 // We iterate backward, starting from the instruction before CmpInstr and
5240 // stop when reaching the definition of a source register or done with the BB.
5241 // RI points to the instruction before CmpInstr.
5242 // If the definition is in this basic block, RE points to the definition;
5243 // otherwise, RE is the rend of the basic block.
5244 MachineBasicBlock::reverse_iterator
5245 RI = MachineBasicBlock::reverse_iterator(I),
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5246 RE = CmpInstr.getParent() == MI->getParent()
5247 ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5248 : CmpInstr.getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5249 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5250 for (; RI != RE; ++RI) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5251 MachineInstr &Instr = *RI;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5252 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5253 if (!IsCmpZero &&
5254 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5255 Sub = &Instr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5256 break;
5257 }
5258
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5259 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5260 Instr.readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5261 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5262
5263 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5264 // They are safe to move up, if the definition to EFLAGS is dead and
5265 // earlier instructions do not read or write EFLAGS.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5266 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5267 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5268 Movr0Inst = &Instr;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5269 continue;
5270 }
5271
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5272 // We can't remove CmpInstr.
5273 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5274 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5275 }
5276
5277 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5278 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5279 return false;
5280
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5281 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5282 Sub->getOperand(2).getReg() == SrcReg);
5283
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5284 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5285 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5286 // If we are done with the basic block, we need to check whether EFLAGS is
5287 // live-out.
5288 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5289 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5290 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5291 for (++I; I != E; ++I) {
5292 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5293 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5294 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5295 // We should check the usage if this instruction uses and updates EFLAGS.
5296 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5297 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5298 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5299 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5300 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5301 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5302 continue;
5303
5304 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5305 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5306 bool OpcIsSET = false;
5307 if (IsCmpZero || IsSwapped) {
5308 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5309 if (Instr.isBranch())
5310 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5311 else {
5312 OldCC = getCondFromSETOpc(Instr.getOpcode());
5313 if (OldCC != X86::COND_INVALID)
5314 OpcIsSET = true;
5315 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5316 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5317 }
5318 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5319 }
5320 if (IsCmpZero) {
5321 switch (OldCC) {
5322 default: break;
5323 case X86::COND_A: case X86::COND_AE:
5324 case X86::COND_B: case X86::COND_BE:
5325 case X86::COND_G: case X86::COND_GE:
5326 case X86::COND_L: case X86::COND_LE:
5327 case X86::COND_O: case X86::COND_NO:
5328 // CF and OF are used, we can't perform this optimization.
5329 return false;
5330 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5331
5332 // If we're updating the condition code check if we have to reverse the
5333 // condition.
5334 if (ShouldUpdateCC)
5335 switch (OldCC) {
5336 default:
5337 return false;
5338 case X86::COND_E:
5339 break;
5340 case X86::COND_NE:
5341 NewCC = GetOppositeBranchCondition(NewCC);
5342 break;
5343 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5344 } else if (IsSwapped) {
5345 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5346 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5347 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5348 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5349 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5350 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5351
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5352 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5353 // Synthesize the new opcode.
5354 bool HasMemoryOperand = Instr.hasOneMemOperand();
5355 unsigned NewOpc;
5356 if (Instr.isBranch())
5357 NewOpc = GetCondBranchFromCond(NewCC);
5358 else if(OpcIsSET)
5359 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5360 else {
5361 unsigned DstReg = Instr.getOperand(0).getReg();
5362 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5363 HasMemoryOperand);
5364 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5365
5366 // Push the MachineInstr to OpsToUpdate.
5367 // If it is safe to remove CmpInstr, the condition code of these
5368 // instructions will be modified.
5369 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5370 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5371 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5372 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5373 IsSafe = true;
5374 break;
5375 }
5376 }
5377
5378 // If EFLAGS is not killed nor re-defined, we should check whether it is
5379 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5380 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5381 MachineBasicBlock *MBB = CmpInstr.getParent();
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5382 for (MachineBasicBlock *Successor : MBB->successors())
5383 if (Successor->isLiveIn(X86::EFLAGS))
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5384 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5385 }
5386
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5387 // The instruction to be updated is either Sub or MI.
5388 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5389 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5390 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5391 // Look backwards until we find a def that doesn't use the current EFLAGS.
5392 Def = Sub;
5393 MachineBasicBlock::reverse_iterator
5394 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5395 InsertE = Sub->getParent()->rend();
5396 for (; InsertI != InsertE; ++InsertI) {
5397 MachineInstr *Instr = &*InsertI;
5398 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5399 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5400 Sub->getParent()->remove(Movr0Inst);
5401 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5402 Movr0Inst);
5403 break;
5404 }
5405 }
5406 if (InsertI == InsertE)
5407 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5408 }
5409
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5410 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5411 unsigned i = 0, e = Sub->getNumOperands();
5412 for (; i != e; ++i) {
5413 MachineOperand &MO = Sub->getOperand(i);
5414 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5415 MO.setIsDead(false);
5416 break;
5417 }
5418 }
5419 assert(i != e && "Unable to locate a def EFLAGS operand");
5420
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5421 CmpInstr.eraseFromParent();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5422
5423 // Modify the condition code of instructions in OpsToUpdate.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5424 for (auto &Op : OpsToUpdate)
5425 Op.first->setDesc(get(Op.second));
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5426 return true;
5427}
5428
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5429/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5430/// operand at the use. We fold the load instructions if load defines a virtual
5431/// register, the virtual register is used once in the same BB, and the
5432/// instructions in-between do not load or store, and have no side effects.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5433MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5434 const MachineRegisterInfo *MRI,
5435 unsigned &FoldAsLoadDefReg,
5436 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5437 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5438 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5439 // To be conservative, if there exists another load, clear the load candidate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5440 if (MI.mayLoad()) {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5441 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5442 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5443 }
5444
5445 // Check whether we can move DefMI here.
5446 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5447 assert(DefMI);
5448 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5449 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5450 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5451
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5452 // Collect information about virtual register operands of MI.
5453 unsigned SrcOperandId = 0;
5454 bool FoundSrcOperand = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5455 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5456 MachineOperand &MO = MI.getOperand(i);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5457 if (!MO.isReg())
5458 continue;
5459 unsigned Reg = MO.getReg();
5460 if (Reg != FoldAsLoadDefReg)
5461 continue;
5462 // Do not fold if we have a subreg use or a def or multiple uses.
5463 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5464 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5465
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5466 SrcOperandId = i;
5467 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5468 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5469 if (!FoundSrcOperand)
5470 return nullptr;
5471
5472 // Check whether we can fold the def into SrcOperandId.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5473 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5474 FoldAsLoadDefReg = 0;
5475 return FoldMI;
5476 }
5477
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5478 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5479}
5480
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5481/// Expand a single-def pseudo instruction to a two-addr
5482/// instruction with two undef reads of the register being defined.
5483/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5484/// %xmm4 = V_SET0
5485/// to:
5486/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5487///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5488static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5489 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5490 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5491 unsigned Reg = MIB->getOperand(0).getReg();
5492 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5493
5494 // MachineInstr::addOperand() will insert explicit operands before any
5495 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5496 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5497 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5498 assert(MIB->getOperand(1).getReg() == Reg &&
5499 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5500 return true;
5501}
5502
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5503/// Expand a single-def pseudo instruction to a two-addr
5504/// instruction with two %k0 reads.
5505/// This is used for mapping:
5506/// %k4 = K_SET1
5507/// to:
5508/// %k4 = KXNORrr %k0, %k0
5509static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5510 const MCInstrDesc &Desc, unsigned Reg) {
5511 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5512 MIB->setDesc(Desc);
5513 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5514 return true;
5515}
5516
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5517static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5518 bool MinusOne) {
5519 MachineBasicBlock &MBB = *MIB->getParent();
5520 DebugLoc DL = MIB->getDebugLoc();
5521 unsigned Reg = MIB->getOperand(0).getReg();
5522
5523 // Insert the XOR.
5524 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5525 .addReg(Reg, RegState::Undef)
5526 .addReg(Reg, RegState::Undef);
5527
5528 // Turn the pseudo into an INC or DEC.
5529 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5530 MIB.addReg(Reg);
5531
5532 return true;
5533}
5534
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5535bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5536 MachineBasicBlock &MBB = *MIB->getParent();
5537 DebugLoc DL = MIB->getDebugLoc();
5538 int64_t Imm = MIB->getOperand(1).getImm();
5539 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5540 MachineBasicBlock::iterator I = MIB.getInstr();
5541
5542 int StackAdjustment;
5543
5544 if (Subtarget.is64Bit()) {
5545 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5546 MIB->getOpcode() == X86::MOV32ImmSExti8);
5547
5548 // Can't use push/pop lowering if the function might write to the red zone.
5549 X86MachineFunctionInfo *X86FI =
5550 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5551 if (X86FI->getUsesRedZone()) {
5552 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5553 : X86::MOV64ri));
5554 return true;
5555 }
5556
5557 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5558 // widen the register if necessary.
5559 StackAdjustment = 8;
5560 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5561 MIB->setDesc(get(X86::POP64r));
5562 MIB->getOperand(0)
5563 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5564 } else {
5565 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5566 StackAdjustment = 4;
5567 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5568 MIB->setDesc(get(X86::POP32r));
5569 }
5570
5571 // Build CFI if necessary.
5572 MachineFunction &MF = *MBB.getParent();
5573 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5574 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5575 bool NeedsDwarfCFI =
5576 !IsWin64Prologue &&
5577 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5578 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5579 if (EmitCFI) {
5580 TFL->BuildCFI(MBB, I, DL,
5581 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5582 TFL->BuildCFI(MBB, std::next(I), DL,
5583 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5584 }
5585
5586 return true;
5587}
5588
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5589// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5590// code sequence is needed for other targets.
5591static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5592 const TargetInstrInfo &TII) {
5593 MachineBasicBlock &MBB = *MIB->getParent();
5594 DebugLoc DL = MIB->getDebugLoc();
5595 unsigned Reg = MIB->getOperand(0).getReg();
5596 const GlobalValue *GV =
5597 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5598 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5599 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5600 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5601 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5602
5603 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5604 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5605 .addMemOperand(MMO);
5606 MIB->setDebugLoc(DL);
5607 MIB->setDesc(TII.get(X86::MOV64rm));
5608 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5609}
5610
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5611bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5612 bool HasAVX = Subtarget.hasAVX();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5613 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5614 switch (MI.getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5615 case X86::MOV32r0:
5616 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5617 case X86::MOV32r1:
5618 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5619 case X86::MOV32r_1:
5620 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5621 case X86::MOV32ImmSExti8:
5622 case X86::MOV64ImmSExti8:
5623 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5624 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5625 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5626 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5627 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5628 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5629 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5630 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5631 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5632 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5633 case X86::FsFLD0SS:
5634 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5635 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5636 case X86::AVX_SET0:
5637 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5638 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Craig Toppere5ce84a2016-05-08 21:33:53 +0000[diff] [blame]5639 case X86::AVX512_128_SET0:
5640 return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5641 case X86::AVX512_256_SET0:
5642 return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5643 case X86::AVX512_512_SET0:
5644 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5645 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5646 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5647 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5648 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]5649 case X86::AVX512_512_SETALLONES: {
5650 unsigned Reg = MIB->getOperand(0).getReg();
5651 MIB->setDesc(get(X86::VPTERNLOGDZrri));
5652 // VPTERNLOGD needs 3 register inputs and an immediate.
5653 // 0xff will return 1s for any input.
5654 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5655 .addReg(Reg, RegState::Undef).addImm(0xff);
5656 return true;
5657 }
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5658 case X86::TEST8ri_NOREX:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5659 MI.setDesc(get(X86::TEST8ri));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5660 return true;
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5661 case X86::MOV32ri64:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5662 MI.setDesc(get(X86::MOV32ri));
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5663 return true;
5664
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5665 // KNL does not recognize dependency-breaking idioms for mask registers,
5666 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5667 // Using %k0 as the undef input register is a performance heuristic based
5668 // on the assumption that %k0 is used less frequently than the other mask
5669 // registers, since it is not usable as a write mask.
5670 // FIXME: A more advanced approach would be to choose the best input mask
5671 // register based on context.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5672 case X86::KSET0B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5673 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5674 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5675 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5676 case X86::KSET1B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5677 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5678 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5679 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5680 case TargetOpcode::LOAD_STACK_GUARD:
5681 expandLoadStackGuard(MIB, *this);
5682 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5683 }
5684 return false;
5685}
5686
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5687static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5688 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5689 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5690
5691 if (NumAddrOps < 4) {
5692 // FrameIndex only - add an immediate offset (whether its zero or not).
5693 for (unsigned i = 0; i != NumAddrOps; ++i)
5694 MIB.addOperand(MOs[i]);
5695 addOffset(MIB, PtrOffset);
5696 } else {
5697 // General Memory Addressing - we need to add any offset to an existing
5698 // offset.
5699 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5700 for (unsigned i = 0; i != NumAddrOps; ++i) {
5701 const MachineOperand &MO = MOs[i];
5702 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5703 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5704 } else {
5705 MIB.addOperand(MO);
5706 }
5707 }
5708 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5709}
5710
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5711static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5712 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5713 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5714 MachineInstr &MI,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5715 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5716 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5717 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5718 MachineInstr *NewMI =
5719 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5720 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5721 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5722
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5723 // Loop over the rest of the ri operands, converting them over.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5724 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5725 for (unsigned i = 0; i != NumOps; ++i) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5726 MachineOperand &MO = MI.getOperand(i + 2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5727 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5728 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5729 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5730 MachineOperand &MO = MI.getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5731 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5732 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5733
5734 MachineBasicBlock *MBB = InsertPt->getParent();
5735 MBB->insert(InsertPt, NewMI);
5736
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5737 return MIB;
5738}
5739
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5740static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5741 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5742 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5743 MachineInstr &MI, const TargetInstrInfo &TII,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5744 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5745 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5746 MachineInstr *NewMI =
5747 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5748 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5749
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5750 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5751 MachineOperand &MO = MI.getOperand(i);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5752 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5753 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5754 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5755 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5756 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5757 }
5758 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5759
5760 MachineBasicBlock *MBB = InsertPt->getParent();
5761 MBB->insert(InsertPt, NewMI);
5762
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5763 return MIB;
5764}
5765
5766static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5767 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5768 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5769 MachineInstr &MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5770 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5771 MI.getDebugLoc(), TII.get(Opcode));
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5772 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5773 return MIB.addImm(0);
5774}
5775
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5776MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5777 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5778 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5779 unsigned Size, unsigned Align) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5780 switch (MI.getOpcode()) {
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5781 case X86::INSERTPSrr:
5782 case X86::VINSERTPSrr:
5783 // Attempt to convert the load of inserted vector into a fold load
5784 // of a single float.
5785 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5786 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5787 unsigned ZMask = Imm & 15;
5788 unsigned DstIdx = (Imm >> 4) & 3;
5789 unsigned SrcIdx = (Imm >> 6) & 3;
5790
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5791 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5792 if (Size <= RCSize && 4 <= Align) {
5793 int PtrOffset = SrcIdx * 4;
5794 unsigned NewImm = (DstIdx << 4) | ZMask;
5795 unsigned NewOpCode =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5796 (MI.getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5797 : X86::INSERTPSrm);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5798 MachineInstr *NewMI =
5799 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5800 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5801 return NewMI;
5802 }
5803 }
5804 break;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5805 case X86::MOVHLPSrr:
5806 case X86::VMOVHLPSrr:
5807 // Move the upper 64-bits of the second operand to the lower 64-bits.
5808 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5809 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5810 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5811 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5812 if (Size <= RCSize && 8 <= Align) {
5813 unsigned NewOpCode =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5814 (MI.getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5815 : X86::MOVLPSrm);
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5816 MachineInstr *NewMI =
5817 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5818 return NewMI;
5819 }
5820 }
5821 break;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5822 };
5823
5824 return nullptr;
5825}
5826
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5827MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5828 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5829 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5830 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5831 const DenseMap<unsigned,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5832 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5833 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5834 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5835
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5836 // For CPUs that favor the register form of a call or push,
5837 // do not fold loads into calls or pushes, unless optimizing for size
5838 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5839 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5840 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5841 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5842 MI.getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5843 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5844
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5845 unsigned NumOps = MI.getDesc().getNumOperands();
5846 bool isTwoAddr =
5847 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5848
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5849 // FIXME: AsmPrinter doesn't know how to handle
5850 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5851 if (MI.getOpcode() == X86::ADD32ri &&
5852 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5853 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5854
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5855 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5856
5857 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5858 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5859 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5860 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5861
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5862 // Folding a memory location into the two-address part of a two-address
5863 // instruction is different than folding it other places. It requires
5864 // replacing the *two* registers with the memory location.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5865 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5866 MI.getOperand(1).isReg() &&
5867 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5868 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5869 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5870 } else if (OpNum == 0) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5871 if (MI.getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5872 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5873 if (NewMI)
5874 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5875 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5876
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5877 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5878 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5879 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5880 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5881 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5882 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]5883 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5884 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]5885 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5886 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5887
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5888 // If table selected...
5889 if (OpcodeTablePtr) {
5890 // Find the Opcode to fuse
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5891 auto I = OpcodeTablePtr->find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5892 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5893 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5894 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5895 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5896 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5897 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5898 if (Size) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5899 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5900 if (Size < RCSize) {
5901 // Check if it's safe to fold the load. If the size of the object is
5902 // narrower than the load width, then it's not.
5903 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5904 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5905 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5906 // a 32-bit load which is implicitly zero-extended. This likely is
5907 // due to live interval analysis remat'ing a load from stack slot.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5908 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5909 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5910 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5911 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5912 }
5913 }
5914
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5915 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5916 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5917 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5918 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5919
5920 if (NarrowToMOV32rm) {
5921 // If this is the special case where we use a MOV32rm to load a 32-bit
5922 // value and zero-extend the top bits. Change the destination register
5923 // to a 32-bit one.
5924 unsigned DstReg = NewMI->getOperand(0).getReg();
5925 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5926 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5927 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]5928 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5929 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5930 return NewMI;
5931 }
5932 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5933
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5934 // If the instruction and target operand are commutable, commute the
5935 // instruction and try again.
5936 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5937 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5938 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5939 bool HasDef = MI.getDesc().getNumDefs();
5940 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
5941 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5942 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5943 bool Tied1 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5944 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5945 bool Tied2 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5946 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5947
5948 // If either of the commutable operands are tied to the destination
5949 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5950 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5951 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5952 return nullptr;
5953
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5954 MachineInstr *CommutedMI =
5955 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5956 if (!CommutedMI) {
5957 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5958 return nullptr;
5959 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5960 if (CommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5961 // New instruction. We can't fold from this.
5962 CommutedMI->eraseFromParent();
5963 return nullptr;
5964 }
5965
5966 // Attempt to fold with the commuted version of the instruction.
5967 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5968 Size, Align, /*AllowCommute=*/false);
5969 if (NewMI)
5970 return NewMI;
5971
5972 // Folding failed again - undo the commute before returning.
5973 MachineInstr *UncommutedMI =
5974 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5975 if (!UncommutedMI) {
5976 // Unable to commute.
5977 return nullptr;
5978 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5979 if (UncommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5980 // New instruction. It doesn't need to be kept.
5981 UncommutedMI->eraseFromParent();
5982 return nullptr;
5983 }
5984
5985 // Return here to prevent duplicate fuse failure report.
5986 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5987 }
5988 }
5989
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5990 // No fusion
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5991 if (PrintFailedFusing && !MI.isCopy())
5992 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5993 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5994}
5995
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5996/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5997/// the first 32 or 64-bits of the destination register and leave the rest
5998/// unmodified. This can be used to avoid folding loads if the instructions
5999/// only update part of the destination register, and the non-updated part is
6000/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6001/// instructions breaks the partial register dependency and it can improve
6002/// performance. e.g.:
6003///
6004/// movss (%rdi), %xmm0
6005/// cvtss2sd %xmm0, %xmm0
6006///
6007/// Instead of
6008/// cvtss2sd (%rdi), %xmm0
6009///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]6010/// FIXME: This should be turned into a TSFlags.
6011///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6012static bool hasPartialRegUpdate(unsigned Opcode) {
6013 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6014 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6015 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6016 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6017 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6018 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6019 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6020 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6021 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6022 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6023 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6024 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6025 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6026 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6027 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6028 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6029 case X86::Int_CVTSS2SDrm:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]6030 case X86::MOVHPDrm:
6031 case X86::MOVHPSrm:
6032 case X86::MOVLPDrm:
6033 case X86::MOVLPSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6034 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6035 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6036 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6037 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6038 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6039 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6040 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6041 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6042 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6043 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6044 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6045 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6046 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6047 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6048 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6049 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6050 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6051 case X86::SQRTSSm_Int:
6052 case X86::SQRTSDr:
6053 case X86::SQRTSDm:
6054 case X86::SQRTSDr_Int:
6055 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6056 return true;
6057 }
6058
6059 return false;
6060}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6061
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6062/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6063/// instructions we would like before a partial register update.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6064unsigned X86InstrInfo::getPartialRegUpdateClearance(
6065 const MachineInstr &MI, unsigned OpNum,
6066 const TargetRegisterInfo *TRI) const {
6067 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6068 return 0;
6069
6070 // If MI is marked as reading Reg, the partial register update is wanted.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6071 const MachineOperand &MO = MI.getOperand(0);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6072 unsigned Reg = MO.getReg();
6073 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6074 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6075 return 0;
6076 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6077 if (MI.readsRegister(Reg, TRI))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6078 return 0;
6079 }
6080
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6081 // If any instructions in the clearance range are reading Reg, insert a
6082 // dependency breaking instruction, which is inexpensive and is likely to
6083 // be hidden in other instruction's cycles.
6084 return PartialRegUpdateClearance;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6085}
6086
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6087// Return true for any instruction the copies the high bits of the first source
6088// operand into the unused high bits of the destination operand.
6089static bool hasUndefRegUpdate(unsigned Opcode) {
6090 switch (Opcode) {
6091 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6092 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6093 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6094 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6095 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6096 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6097 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6098 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6099 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6100 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6101 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6102 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6103 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6104 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6105 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6106 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6107 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6108 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6109 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6110 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6111 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6112 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6113 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6114 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6115 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6116 case X86::VRCPSSm:
6117 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6118 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6119 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6120 case X86::VROUNDSDr_Int:
6121 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6122 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6123 case X86::VROUNDSSr_Int:
6124 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6125 case X86::VRSQRTSSm:
6126 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6127 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6128 case X86::VSQRTSSm:
6129 case X86::VSQRTSSm_Int:
6130 case X86::VSQRTSDr:
6131 case X86::VSQRTSDm:
6132 case X86::VSQRTSDm_Int:
6133 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6134 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6135 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6136 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6137 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6138 return true;
6139 }
6140
6141 return false;
6142}
6143
6144/// Inform the ExeDepsFix pass how many idle instructions we would like before
6145/// certain undef register reads.
6146///
6147/// This catches the VCVTSI2SD family of instructions:
6148///
6149/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6150///
6151/// We should to be careful *not* to catch VXOR idioms which are presumably
6152/// handled specially in the pipeline:
6153///
6154/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6155///
6156/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6157/// high bits that are passed-through are not live.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6158unsigned
6159X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6160 const TargetRegisterInfo *TRI) const {
6161 if (!hasUndefRegUpdate(MI.getOpcode()))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6162 return 0;
6163
6164 // Set the OpNum parameter to the first source operand.
6165 OpNum = 1;
6166
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6167 const MachineOperand &MO = MI.getOperand(OpNum);
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6168 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6169 return UndefRegClearance;
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6170 }
6171 return 0;
6172}
6173
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6174void X86InstrInfo::breakPartialRegDependency(
6175 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6176 unsigned Reg = MI.getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6177 // If MI kills this register, the false dependence is already broken.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6178 if (MI.killsRegister(Reg, TRI))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6179 return;
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6180
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6181 if (X86::VR128RegClass.contains(Reg)) {
6182 // These instructions are all floating point domain, so xorps is the best
6183 // choice.
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6184 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6185 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6186 .addReg(Reg, RegState::Undef)
6187 .addReg(Reg, RegState::Undef);
6188 MI.addRegisterKilled(Reg, TRI, true);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6189 } else if (X86::VR256RegClass.contains(Reg)) {
6190 // Use vxorps to clear the full ymm register.
6191 // It wants to read and write the xmm sub-register.
6192 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6193 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6194 .addReg(XReg, RegState::Undef)
6195 .addReg(XReg, RegState::Undef)
6196 .addReg(Reg, RegState::ImplicitDefine);
6197 MI.addRegisterKilled(Reg, TRI, true);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6198 }
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6199}
6200
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6201MachineInstr *
6202X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6203 ArrayRef<unsigned> Ops,
6204 MachineBasicBlock::iterator InsertPt,
6205 int FrameIndex, LiveIntervals *LIS) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6206 // Check switch flag
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6207 if (NoFusing)
6208 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6209
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6210 // Unless optimizing for size, don't fold to avoid partial
6211 // register update stalls
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6212 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6213 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6214
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6215 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6216 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6217 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]6218 // If the function stack isn't realigned we don't want to fold instructions
6219 // that need increased alignment.
6220 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6221 Alignment =
6222 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6223 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6224 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6225 unsigned RCSize = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6226 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6227 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6228 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]6229 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6230 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6231 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6232 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6233 // Check if it's safe to fold the load. If the size of the object is
6234 // narrower than the load width, then it's not.
6235 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6236 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6237 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6238 MI.setDesc(get(NewOpc));
6239 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6240 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6241 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6242
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]6243 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6244 MachineOperand::CreateFI(FrameIndex), InsertPt,
6245 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6246}
6247
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6248/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6249/// because the latter uses contents that wouldn't be defined in the folded
6250/// version. For instance, this transformation isn't legal:
6251/// movss (%rdi), %xmm0
6252/// addps %xmm0, %xmm0
6253/// ->
6254/// addps (%rdi), %xmm0
6255///
6256/// But this one is:
6257/// movss (%rdi), %xmm0
6258/// addss %xmm0, %xmm0
6259/// ->
6260/// addss (%rdi), %xmm0
6261///
6262static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6263 const MachineInstr &UserMI,
6264 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6265 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6266 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6267 unsigned RegSize =
6268 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6269
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6270 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6271 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6272 // destination register is wider than 32 bits (4 bytes), and its user
6273 // instruction isn't scalar (SS).
6274 switch (UserOpc) {
6275 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
6276 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
6277 case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
6278 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6279 case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6280 case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6281 case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6282 case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6283 case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6284 case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6285 return false;
6286 default:
6287 return true;
6288 }
6289 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6290
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6291 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6292 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6293 // destination register is wider than 64 bits (8 bytes), and its user
6294 // instruction isn't scalar (SD).
6295 switch (UserOpc) {
6296 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6297 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6298 case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6299 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6300 case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6301 case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6302 case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6303 case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6304 case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6305 case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6306 return false;
6307 default:
6308 return true;
6309 }
6310 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6311
6312 return false;
6313}
6314
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6315MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6316 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6317 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6318 LiveIntervals *LIS) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6319 // If loading from a FrameIndex, fold directly from the FrameIndex.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6320 unsigned NumOps = LoadMI.getDesc().getNumOperands();
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6321 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6322 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6323 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6324 return nullptr;
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6325 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6326 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6327
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6328 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6329 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6330
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6331 // Avoid partial register update stalls unless optimizing for size.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6332 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6333 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6334
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6335 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6336 unsigned Alignment = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6337 if (LoadMI.hasOneMemOperand())
6338 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6339 else
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6340 switch (LoadMI.getOpcode()) {
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6341 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6342 case X86::AVX512_512_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6343 Alignment = 64;
6344 break;
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6345 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6346 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6347 case X86::AVX512_256_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6348 Alignment = 32;
6349 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6350 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6351 case X86::V_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6352 case X86::AVX512_128_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6353 Alignment = 16;
6354 break;
6355 case X86::FsFLD0SD:
6356 Alignment = 8;
6357 break;
6358 case X86::FsFLD0SS:
6359 Alignment = 4;
6360 break;
6361 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6362 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6363 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6364 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6365 unsigned NewOpc = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6366 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6367 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6368 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6369 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6370 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6371 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6372 }
6373 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6374 MI.setDesc(get(NewOpc));
6375 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6376 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6377 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6378
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6379 // Make sure the subregisters match.
6380 // Otherwise we risk changing the size of the load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6381 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6382 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6383
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6384 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6385 switch (LoadMI.getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6386 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6387 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6388 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6389 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6390 case X86::AVX512_128_SET0:
6391 case X86::AVX512_256_SET0:
6392 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6393 case X86::AVX512_512_SETALLONES:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6394 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6395 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6396 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6397 // Create a constant-pool entry and operands to load from it.
6398
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6399 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6400 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6401 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6402 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6403
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6404 // x86-32 PIC requires a PIC base register for constant pools.
6405 unsigned PICBase = 0;
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]6406 if (MF.getTarget().isPositionIndependent()) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6407 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6408 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6409 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6410 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6411 // This doesn't work for several reasons.
6412 // 1. GlobalBaseReg may have been spilled.
6413 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6414 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6415 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6416
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6417 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6418 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6419 Type *Ty;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6420 unsigned Opc = LoadMI.getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6421 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6422 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6423 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6424 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6425 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6426 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6427 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6428 Opc == X86::AVX512_256_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6429 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6430 else
6431 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6432
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6433 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6434 Opc == X86::AVX512_512_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6435 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6436 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6437 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6438
6439 // Create operands to load from the constant pool entry.
6440 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6441 MOs.push_back(MachineOperand::CreateImm(1));
6442 MOs.push_back(MachineOperand::CreateReg(0, false));
6443 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6444 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6445 break;
6446 }
6447 default: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6448 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6449 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6450
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6451 // Folding a normal load. Just copy the load's address operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6452 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6453 LoadMI.operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6454 break;
6455 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6456 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6457 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6458 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6459}
6460
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6461bool X86InstrInfo::unfoldMemoryOperand(
6462 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6463 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6464 auto I = MemOp2RegOpTable.find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6465 if (I == MemOp2RegOpTable.end())
6466 return false;
6467 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6468 unsigned Index = I->second.second & TB_INDEX_MASK;
6469 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6470 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6471 if (UnfoldLoad && !FoldedLoad)
6472 return false;
6473 UnfoldLoad &= FoldedLoad;
6474 if (UnfoldStore && !FoldedStore)
6475 return false;
6476 UnfoldStore &= FoldedStore;
6477
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6478 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6479 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6480 // TODO: Check if 32-byte or greater accesses are slow too?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6481 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6482 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6483 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6484 // conservatively assume the address is unaligned. That's bad for
6485 // performance.
6486 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6487 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6488 SmallVector<MachineOperand,2> BeforeOps;
6489 SmallVector<MachineOperand,2> AfterOps;
6490 SmallVector<MachineOperand,4> ImpOps;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6491 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6492 MachineOperand &Op = MI.getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6493 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6494 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6495 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6496 ImpOps.push_back(Op);
6497 else if (i < Index)
6498 BeforeOps.push_back(Op);
6499 else if (i > Index)
6500 AfterOps.push_back(Op);
6501 }
6502
6503 // Emit the load instruction.
6504 if (UnfoldLoad) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6505 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6506 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6507 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6508 if (UnfoldStore) {
6509 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6510 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6511 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6512 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6513 MO.setIsKill(false);
6514 }
6515 }
6516 }
6517
6518 // Emit the data processing instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6519 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6520 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6521
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6522 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6523 MIB.addReg(Reg, RegState::Define);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6524 for (MachineOperand &BeforeOp : BeforeOps)
6525 MIB.addOperand(BeforeOp);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6526 if (FoldedLoad)
6527 MIB.addReg(Reg);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6528 for (MachineOperand &AfterOp : AfterOps)
6529 MIB.addOperand(AfterOp);
6530 for (MachineOperand &ImpOp : ImpOps) {
6531 MIB.addReg(ImpOp.getReg(),
6532 getDefRegState(ImpOp.isDef()) |
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6533 RegState::Implicit |
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6534 getKillRegState(ImpOp.isKill()) |
6535 getDeadRegState(ImpOp.isDead()) |
6536 getUndefRegState(ImpOp.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6537 }
6538 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6539 switch (DataMI->getOpcode()) {
6540 default: break;
6541 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6542 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6543 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6544 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6545 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6546 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6547 case X86::CMP8ri: {
6548 MachineOperand &MO0 = DataMI->getOperand(0);
6549 MachineOperand &MO1 = DataMI->getOperand(1);
6550 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6551 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6552 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6553 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6554 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6555 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6556 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6557 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6558 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6559 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6560 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6561 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6562 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6563 MO1.ChangeToRegister(MO0.getReg(), false);
6564 }
6565 }
6566 }
6567 NewMIs.push_back(DataMI);
6568
6569 // Emit the store instruction.
6570 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6571 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6572 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6573 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6574 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6575 }
6576
6577 return true;
6578}
6579
6580bool
6581X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6582 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6583 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6584 return false;
6585
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6586 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6587 if (I == MemOp2RegOpTable.end())
6588 return false;
6589 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6590 unsigned Index = I->second.second & TB_INDEX_MASK;
6591 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6592 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6593 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6594 MachineFunction &MF = DAG.getMachineFunction();
6595 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6596 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6597 std::vector<SDValue> AddrOps;
6598 std::vector<SDValue> BeforeOps;
6599 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6600 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6601 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6602 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6603 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6604 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6605 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6606 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6607 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6608 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6609 AfterOps.push_back(Op);
6610 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6611 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6612 AddrOps.push_back(Chain);
6613
6614 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6615 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6616 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6617 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6618 std::pair<MachineInstr::mmo_iterator,
6619 MachineInstr::mmo_iterator> MMOs =
6620 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6621 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6622 if (!(*MMOs.first) &&
6623 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6624 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6625 // Do not introduce a slow unaligned load.
6626 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6627 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6628 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6629 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6630 bool isAligned = (*MMOs.first) &&
6631 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6632 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6633 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6634 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6635
6636 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6637 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6638 }
6639
6640 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6641 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6642 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6643 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6644 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6645 VTs.push_back(*DstRC->vt_begin());
6646 }
6647 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6648 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6649 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6650 VTs.push_back(VT);
6651 }
6652 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6653 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6654 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6655 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6656 NewNodes.push_back(NewNode);
6657
6658 // Emit the store instruction.
6659 if (FoldedStore) {
6660 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6661 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6662 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6663 std::pair<MachineInstr::mmo_iterator,
6664 MachineInstr::mmo_iterator> MMOs =
6665 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6666 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6667 if (!(*MMOs.first) &&
6668 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6669 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6670 // Do not introduce a slow unaligned store.
6671 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6672 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6673 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6674 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6675 bool isAligned = (*MMOs.first) &&
6676 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6677 SDNode *Store =
6678 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6679 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6680 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6681
6682 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6683 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6684 }
6685
6686 return true;
6687}
6688
6689unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6690 bool UnfoldLoad, bool UnfoldStore,
6691 unsigned *LoadRegIndex) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6692 auto I = MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6693 if (I == MemOp2RegOpTable.end())
6694 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6695 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6696 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6697 if (UnfoldLoad && !FoldedLoad)
6698 return 0;
6699 if (UnfoldStore && !FoldedStore)
6700 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6701 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6702 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6703 return I->second.first;
6704}
6705
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6706bool
6707X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6708 int64_t &Offset1, int64_t &Offset2) const {
6709 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6710 return false;
6711 unsigned Opc1 = Load1->getMachineOpcode();
6712 unsigned Opc2 = Load2->getMachineOpcode();
6713 switch (Opc1) {
6714 default: return false;
6715 case X86::MOV8rm:
6716 case X86::MOV16rm:
6717 case X86::MOV32rm:
6718 case X86::MOV64rm:
6719 case X86::LD_Fp32m:
6720 case X86::LD_Fp64m:
6721 case X86::LD_Fp80m:
6722 case X86::MOVSSrm:
6723 case X86::MOVSDrm:
6724 case X86::MMX_MOVD64rm:
6725 case X86::MMX_MOVQ64rm:
6726 case X86::FsMOVAPSrm:
6727 case X86::FsMOVAPDrm:
6728 case X86::MOVAPSrm:
6729 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6730 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6731 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6732 case X86::MOVDQArm:
6733 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6734 // AVX load instructions
6735 case X86::VMOVSSrm:
6736 case X86::VMOVSDrm:
6737 case X86::FsVMOVAPSrm:
6738 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6739 case X86::VMOVAPSrm:
6740 case X86::VMOVUPSrm:
6741 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6742 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6743 case X86::VMOVDQArm:
6744 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6745 case X86::VMOVAPSYrm:
6746 case X86::VMOVUPSYrm:
6747 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6748 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6749 case X86::VMOVDQAYrm:
6750 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6751 // AVX512 load instructions
6752 case X86::VMOVSSZrm:
6753 case X86::VMOVSDZrm:
6754 case X86::VMOVAPSZ128rm:
6755 case X86::VMOVUPSZ128rm:
6756 case X86::VMOVAPDZ128rm:
6757 case X86::VMOVUPDZ128rm:
6758 case X86::VMOVDQU8Z128rm:
6759 case X86::VMOVDQU16Z128rm:
6760 case X86::VMOVDQA32Z128rm:
6761 case X86::VMOVDQU32Z128rm:
6762 case X86::VMOVDQA64Z128rm:
6763 case X86::VMOVDQU64Z128rm:
6764 case X86::VMOVAPSZ256rm:
6765 case X86::VMOVUPSZ256rm:
6766 case X86::VMOVAPDZ256rm:
6767 case X86::VMOVUPDZ256rm:
6768 case X86::VMOVDQU8Z256rm:
6769 case X86::VMOVDQU16Z256rm:
6770 case X86::VMOVDQA32Z256rm:
6771 case X86::VMOVDQU32Z256rm:
6772 case X86::VMOVDQA64Z256rm:
6773 case X86::VMOVDQU64Z256rm:
6774 case X86::VMOVAPSZrm:
6775 case X86::VMOVUPSZrm:
6776 case X86::VMOVAPDZrm:
6777 case X86::VMOVUPDZrm:
6778 case X86::VMOVDQU8Zrm:
6779 case X86::VMOVDQU16Zrm:
6780 case X86::VMOVDQA32Zrm:
6781 case X86::VMOVDQU32Zrm:
6782 case X86::VMOVDQA64Zrm:
6783 case X86::VMOVDQU64Zrm:
6784 case X86::KMOVBkm:
6785 case X86::KMOVWkm:
6786 case X86::KMOVDkm:
6787 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6788 break;
6789 }
6790 switch (Opc2) {
6791 default: return false;
6792 case X86::MOV8rm:
6793 case X86::MOV16rm:
6794 case X86::MOV32rm:
6795 case X86::MOV64rm:
6796 case X86::LD_Fp32m:
6797 case X86::LD_Fp64m:
6798 case X86::LD_Fp80m:
6799 case X86::MOVSSrm:
6800 case X86::MOVSDrm:
6801 case X86::MMX_MOVD64rm:
6802 case X86::MMX_MOVQ64rm:
6803 case X86::FsMOVAPSrm:
6804 case X86::FsMOVAPDrm:
6805 case X86::MOVAPSrm:
6806 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6807 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6808 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6809 case X86::MOVDQArm:
6810 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6811 // AVX load instructions
6812 case X86::VMOVSSrm:
6813 case X86::VMOVSDrm:
6814 case X86::FsVMOVAPSrm:
6815 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6816 case X86::VMOVAPSrm:
6817 case X86::VMOVUPSrm:
6818 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6819 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6820 case X86::VMOVDQArm:
6821 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6822 case X86::VMOVAPSYrm:
6823 case X86::VMOVUPSYrm:
6824 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6825 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6826 case X86::VMOVDQAYrm:
6827 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6828 // AVX512 load instructions
6829 case X86::VMOVSSZrm:
6830 case X86::VMOVSDZrm:
6831 case X86::VMOVAPSZ128rm:
6832 case X86::VMOVUPSZ128rm:
6833 case X86::VMOVAPDZ128rm:
6834 case X86::VMOVUPDZ128rm:
6835 case X86::VMOVDQU8Z128rm:
6836 case X86::VMOVDQU16Z128rm:
6837 case X86::VMOVDQA32Z128rm:
6838 case X86::VMOVDQU32Z128rm:
6839 case X86::VMOVDQA64Z128rm:
6840 case X86::VMOVDQU64Z128rm:
6841 case X86::VMOVAPSZ256rm:
6842 case X86::VMOVUPSZ256rm:
6843 case X86::VMOVAPDZ256rm:
6844 case X86::VMOVUPDZ256rm:
6845 case X86::VMOVDQU8Z256rm:
6846 case X86::VMOVDQU16Z256rm:
6847 case X86::VMOVDQA32Z256rm:
6848 case X86::VMOVDQU32Z256rm:
6849 case X86::VMOVDQA64Z256rm:
6850 case X86::VMOVDQU64Z256rm:
6851 case X86::VMOVAPSZrm:
6852 case X86::VMOVUPSZrm:
6853 case X86::VMOVAPDZrm:
6854 case X86::VMOVUPDZrm:
6855 case X86::VMOVDQU8Zrm:
6856 case X86::VMOVDQU16Zrm:
6857 case X86::VMOVDQA32Zrm:
6858 case X86::VMOVDQU32Zrm:
6859 case X86::VMOVDQA64Zrm:
6860 case X86::VMOVDQU64Zrm:
6861 case X86::KMOVBkm:
6862 case X86::KMOVWkm:
6863 case X86::KMOVDkm:
6864 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6865 break;
6866 }
6867
6868 // Check if chain operands and base addresses match.
6869 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6870 Load1->getOperand(5) != Load2->getOperand(5))
6871 return false;
6872 // Segment operands should match as well.
6873 if (Load1->getOperand(4) != Load2->getOperand(4))
6874 return false;
6875 // Scale should be 1, Index should be Reg0.
6876 if (Load1->getOperand(1) == Load2->getOperand(1) &&
6877 Load1->getOperand(2) == Load2->getOperand(2)) {
6878 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6879 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6880
6881 // Now let's examine the displacements.
6882 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6883 isa<ConstantSDNode>(Load2->getOperand(3))) {
6884 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6885 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6886 return true;
6887 }
6888 }
6889 return false;
6890}
6891
6892bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6893 int64_t Offset1, int64_t Offset2,
6894 unsigned NumLoads) const {
6895 assert(Offset2 > Offset1);
6896 if ((Offset2 - Offset1) / 8 > 64)
6897 return false;
6898
6899 unsigned Opc1 = Load1->getMachineOpcode();
6900 unsigned Opc2 = Load2->getMachineOpcode();
6901 if (Opc1 != Opc2)
6902 return false; // FIXME: overly conservative?
6903
6904 switch (Opc1) {
6905 default: break;
6906 case X86::LD_Fp32m:
6907 case X86::LD_Fp64m:
6908 case X86::LD_Fp80m:
6909 case X86::MMX_MOVD64rm:
6910 case X86::MMX_MOVQ64rm:
6911 return false;
6912 }
6913
6914 EVT VT = Load1->getValueType(0);
6915 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6916 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6917 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6918 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6919 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6920 if (NumLoads >= 3)
6921 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6922 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6923 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6924 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6925 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6926 case MVT::i8:
6927 case MVT::i16:
6928 case MVT::i32:
6929 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]6930 case MVT::f32:
6931 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6932 if (NumLoads)
6933 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6934 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6935 }
6936
6937 return true;
6938}
6939
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6940bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
6941 MachineInstr &Second) const {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6942 // Check if this processor supports macro-fusion. Since this is a minor
6943 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6944 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6945 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6946 return false;
6947
6948 enum {
6949 FuseTest,
6950 FuseCmp,
6951 FuseInc
6952 } FuseKind;
6953
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6954 switch (Second.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6955 default:
6956 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6957 case X86::JE_1:
6958 case X86::JNE_1:
6959 case X86::JL_1:
6960 case X86::JLE_1:
6961 case X86::JG_1:
6962 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6963 FuseKind = FuseInc;
6964 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6965 case X86::JB_1:
6966 case X86::JBE_1:
6967 case X86::JA_1:
6968 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6969 FuseKind = FuseCmp;
6970 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6971 case X86::JS_1:
6972 case X86::JNS_1:
6973 case X86::JP_1:
6974 case X86::JNP_1:
6975 case X86::JO_1:
6976 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6977 FuseKind = FuseTest;
6978 break;
6979 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6980 switch (First.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6981 default:
6982 return false;
6983 case X86::TEST8rr:
6984 case X86::TEST16rr:
6985 case X86::TEST32rr:
6986 case X86::TEST64rr:
6987 case X86::TEST8ri:
6988 case X86::TEST16ri:
6989 case X86::TEST32ri:
6990 case X86::TEST32i32:
6991 case X86::TEST64i32:
6992 case X86::TEST64ri32:
6993 case X86::TEST8rm:
6994 case X86::TEST16rm:
6995 case X86::TEST32rm:
6996 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]6997 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6998 case X86::AND16i16:
6999 case X86::AND16ri:
7000 case X86::AND16ri8:
7001 case X86::AND16rm:
7002 case X86::AND16rr:
7003 case X86::AND32i32:
7004 case X86::AND32ri:
7005 case X86::AND32ri8:
7006 case X86::AND32rm:
7007 case X86::AND32rr:
7008 case X86::AND64i32:
7009 case X86::AND64ri32:
7010 case X86::AND64ri8:
7011 case X86::AND64rm:
7012 case X86::AND64rr:
7013 case X86::AND8i8:
7014 case X86::AND8ri:
7015 case X86::AND8rm:
7016 case X86::AND8rr:
7017 return true;
7018 case X86::CMP16i16:
7019 case X86::CMP16ri:
7020 case X86::CMP16ri8:
7021 case X86::CMP16rm:
7022 case X86::CMP16rr:
7023 case X86::CMP32i32:
7024 case X86::CMP32ri:
7025 case X86::CMP32ri8:
7026 case X86::CMP32rm:
7027 case X86::CMP32rr:
7028 case X86::CMP64i32:
7029 case X86::CMP64ri32:
7030 case X86::CMP64ri8:
7031 case X86::CMP64rm:
7032 case X86::CMP64rr:
7033 case X86::CMP8i8:
7034 case X86::CMP8ri:
7035 case X86::CMP8rm:
7036 case X86::CMP8rr:
7037 case X86::ADD16i16:
7038 case X86::ADD16ri:
7039 case X86::ADD16ri8:
7040 case X86::ADD16ri8_DB:
7041 case X86::ADD16ri_DB:
7042 case X86::ADD16rm:
7043 case X86::ADD16rr:
7044 case X86::ADD16rr_DB:
7045 case X86::ADD32i32:
7046 case X86::ADD32ri:
7047 case X86::ADD32ri8:
7048 case X86::ADD32ri8_DB:
7049 case X86::ADD32ri_DB:
7050 case X86::ADD32rm:
7051 case X86::ADD32rr:
7052 case X86::ADD32rr_DB:
7053 case X86::ADD64i32:
7054 case X86::ADD64ri32:
7055 case X86::ADD64ri32_DB:
7056 case X86::ADD64ri8:
7057 case X86::ADD64ri8_DB:
7058 case X86::ADD64rm:
7059 case X86::ADD64rr:
7060 case X86::ADD64rr_DB:
7061 case X86::ADD8i8:
7062 case X86::ADD8mi:
7063 case X86::ADD8mr:
7064 case X86::ADD8ri:
7065 case X86::ADD8rm:
7066 case X86::ADD8rr:
7067 case X86::SUB16i16:
7068 case X86::SUB16ri:
7069 case X86::SUB16ri8:
7070 case X86::SUB16rm:
7071 case X86::SUB16rr:
7072 case X86::SUB32i32:
7073 case X86::SUB32ri:
7074 case X86::SUB32ri8:
7075 case X86::SUB32rm:
7076 case X86::SUB32rr:
7077 case X86::SUB64i32:
7078 case X86::SUB64ri32:
7079 case X86::SUB64ri8:
7080 case X86::SUB64rm:
7081 case X86::SUB64rr:
7082 case X86::SUB8i8:
7083 case X86::SUB8ri:
7084 case X86::SUB8rm:
7085 case X86::SUB8rr:
7086 return FuseKind == FuseCmp || FuseKind == FuseInc;
7087 case X86::INC16r:
7088 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7089 case X86::INC64r:
7090 case X86::INC8r:
7091 case X86::DEC16r:
7092 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7093 case X86::DEC64r:
7094 case X86::DEC8r:
7095 return FuseKind == FuseInc;
7096 }
7097}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7098
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7099bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]7100ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7101 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]7102 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7103 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7104 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7105}
7106
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7107bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7108isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7109 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7110 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7111 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7112 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7113}
7114
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7115/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7116/// the global base register value. Output instructions required to
7117/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7118///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7119/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7120///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7121unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7122 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7123 "X86-64 PIC uses RIP relative addressing");
7124
7125 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7126 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7127 if (GlobalBaseReg != 0)
7128 return GlobalBaseReg;
7129
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7130 // Create the register. The code to initialize it is inserted
7131 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7132 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]7133 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7134 X86FI->setGlobalBaseReg(GlobalBaseReg);
7135 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7136}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7137
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7138// These are the replaceable SSE instructions. Some of these have Int variants
7139// that we don't include here. We don't want to replace instructions selected
7140// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7141static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]7142 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7143 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
7144 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
7145 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
7146 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
7147 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]7148 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7149 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
7150 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
7151 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
7152 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
7153 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
7154 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
7155 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
7156 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
7157 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7158 // AVX 128-bit support
7159 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
7160 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
7161 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
7162 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
7163 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]7164 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7165 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7166 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
7167 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
7168 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
7169 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
7170 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
7171 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7172 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
7173 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]7174 // AVX 256-bit support
7175 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
7176 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
7177 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
7178 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
7179 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7180 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
7181};
7182
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7183static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7184 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]7185 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
7186 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
7187 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
7188 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
7189 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
7190 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
7191 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]7192 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
7193 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7194 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7195 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
7196 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
7197 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]7198 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
7199 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7200 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7201 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7202 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7203 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7204 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7205};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7206
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7207// FIXME: Some shuffle and unpack instructions have equivalents in different
7208// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7209
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7210static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7211 for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7212 if (Row[domain-1] == opcode)
7213 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7214 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7215}
7216
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7217static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7218 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7219 if (Row[domain-1] == opcode)
7220 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7221 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7222}
7223
7224std::pair<uint16_t, uint16_t>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7225X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7226 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7227 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7228 uint16_t validDomains = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7229 if (domain && lookup(MI.getOpcode(), domain))
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7230 validDomains = 0xe;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7231 else if (domain && lookupAVX2(MI.getOpcode(), domain))
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7232 validDomains = hasAVX2 ? 0xe : 0x6;
7233 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7234}
7235
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7236void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7237 assert(Domain>0 && Domain<4 && "Invalid execution domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7238 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7239 assert(dom && "Not an SSE instruction");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7240 const uint16_t *table = lookup(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7241 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7242 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7243 "256-bit vector operations only available in AVX2");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7244 table = lookupAVX2(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7245 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7246 assert(table && "Cannot change domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7247 MI.setDesc(get(table[Domain - 1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7248}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7249
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7250/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7251void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7252 NopInst.setOpcode(X86::NOOP);
7253}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7254
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7255// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7256// In particular, getJumpInstrTableEntryBound must always return an upper bound
7257// on the encoding lengths of the instructions generated by
7258// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7259void X86InstrInfo::getUnconditionalBranch(
7260 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7261 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]7262 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7263}
7264
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7265// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7266// In particular, getJumpInstrTableEntryBound must always return an upper bound
7267// on the encoding lengths of the instructions generated by
7268// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7269void X86InstrInfo::getTrap(MCInst &MI) const {
7270 MI.setOpcode(X86::TRAP);
7271}
7272
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7273// See getTrap and getUnconditionalBranch for conditions on the value returned
7274// by this function.
7275unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7276 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7277 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7278 return 5;
7279}
7280
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7281bool X86InstrInfo::isHighLatencyDef(int opc) const {
7282 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7283 default: return false;
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7284 case X86::DIVPDrm:
7285 case X86::DIVPDrr:
7286 case X86::DIVPSrm:
7287 case X86::DIVPSrr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7288 case X86::DIVSDrm:
7289 case X86::DIVSDrm_Int:
7290 case X86::DIVSDrr:
7291 case X86::DIVSDrr_Int:
7292 case X86::DIVSSrm:
7293 case X86::DIVSSrm_Int:
7294 case X86::DIVSSrr:
7295 case X86::DIVSSrr_Int:
7296 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7297 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7298 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7299 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7300 case X86::SQRTSDm:
7301 case X86::SQRTSDm_Int:
7302 case X86::SQRTSDr:
7303 case X86::SQRTSDr_Int:
7304 case X86::SQRTSSm:
7305 case X86::SQRTSSm_Int:
7306 case X86::SQRTSSr:
7307 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7308 // AVX instructions with high latency
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7309 case X86::VDIVPDrm:
7310 case X86::VDIVPDrr:
7311 case X86::VDIVPDYrm:
7312 case X86::VDIVPDYrr:
7313 case X86::VDIVPSrm:
7314 case X86::VDIVPSrr:
7315 case X86::VDIVPSYrm:
7316 case X86::VDIVPSYrr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7317 case X86::VDIVSDrm:
7318 case X86::VDIVSDrm_Int:
7319 case X86::VDIVSDrr:
7320 case X86::VDIVSDrr_Int:
7321 case X86::VDIVSSrm:
7322 case X86::VDIVSSrm_Int:
7323 case X86::VDIVSSrr:
7324 case X86::VDIVSSrr_Int:
7325 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7326 case X86::VSQRTPDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7327 case X86::VSQRTPDYm:
7328 case X86::VSQRTPDYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7329 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7330 case X86::VSQRTPSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7331 case X86::VSQRTPSYm:
7332 case X86::VSQRTPSYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7333 case X86::VSQRTSDm:
7334 case X86::VSQRTSDm_Int:
7335 case X86::VSQRTSDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7336 case X86::VSQRTSDr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7337 case X86::VSQRTSSm:
7338 case X86::VSQRTSSm_Int:
7339 case X86::VSQRTSSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7340 case X86::VSQRTSSr_Int:
7341 // AVX512 instructions with high latency
7342 case X86::VDIVPDZ128rm:
7343 case X86::VDIVPDZ128rmb:
7344 case X86::VDIVPDZ128rmbk:
7345 case X86::VDIVPDZ128rmbkz:
7346 case X86::VDIVPDZ128rmk:
7347 case X86::VDIVPDZ128rmkz:
7348 case X86::VDIVPDZ128rr:
7349 case X86::VDIVPDZ128rrk:
7350 case X86::VDIVPDZ128rrkz:
7351 case X86::VDIVPDZ256rm:
7352 case X86::VDIVPDZ256rmb:
7353 case X86::VDIVPDZ256rmbk:
7354 case X86::VDIVPDZ256rmbkz:
7355 case X86::VDIVPDZ256rmk:
7356 case X86::VDIVPDZ256rmkz:
7357 case X86::VDIVPDZ256rr:
7358 case X86::VDIVPDZ256rrk:
7359 case X86::VDIVPDZ256rrkz:
7360 case X86::VDIVPDZrb:
7361 case X86::VDIVPDZrbk:
7362 case X86::VDIVPDZrbkz:
7363 case X86::VDIVPDZrm:
7364 case X86::VDIVPDZrmb:
7365 case X86::VDIVPDZrmbk:
7366 case X86::VDIVPDZrmbkz:
7367 case X86::VDIVPDZrmk:
7368 case X86::VDIVPDZrmkz:
7369 case X86::VDIVPDZrr:
7370 case X86::VDIVPDZrrk:
7371 case X86::VDIVPDZrrkz:
7372 case X86::VDIVPSZ128rm:
7373 case X86::VDIVPSZ128rmb:
7374 case X86::VDIVPSZ128rmbk:
7375 case X86::VDIVPSZ128rmbkz:
7376 case X86::VDIVPSZ128rmk:
7377 case X86::VDIVPSZ128rmkz:
7378 case X86::VDIVPSZ128rr:
7379 case X86::VDIVPSZ128rrk:
7380 case X86::VDIVPSZ128rrkz:
7381 case X86::VDIVPSZ256rm:
7382 case X86::VDIVPSZ256rmb:
7383 case X86::VDIVPSZ256rmbk:
7384 case X86::VDIVPSZ256rmbkz:
7385 case X86::VDIVPSZ256rmk:
7386 case X86::VDIVPSZ256rmkz:
7387 case X86::VDIVPSZ256rr:
7388 case X86::VDIVPSZ256rrk:
7389 case X86::VDIVPSZ256rrkz:
7390 case X86::VDIVPSZrb:
7391 case X86::VDIVPSZrbk:
7392 case X86::VDIVPSZrbkz:
7393 case X86::VDIVPSZrm:
7394 case X86::VDIVPSZrmb:
7395 case X86::VDIVPSZrmbk:
7396 case X86::VDIVPSZrmbkz:
7397 case X86::VDIVPSZrmk:
7398 case X86::VDIVPSZrmkz:
7399 case X86::VDIVPSZrr:
7400 case X86::VDIVPSZrrk:
7401 case X86::VDIVPSZrrkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7402 case X86::VDIVSDZrm:
7403 case X86::VDIVSDZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7404 case X86::VDIVSDZrm_Int:
7405 case X86::VDIVSDZrm_Intk:
7406 case X86::VDIVSDZrm_Intkz:
7407 case X86::VDIVSDZrr_Int:
7408 case X86::VDIVSDZrr_Intk:
7409 case X86::VDIVSDZrr_Intkz:
7410 case X86::VDIVSDZrrb:
7411 case X86::VDIVSDZrrbk:
7412 case X86::VDIVSDZrrbkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7413 case X86::VDIVSSZrm:
7414 case X86::VDIVSSZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7415 case X86::VDIVSSZrm_Int:
7416 case X86::VDIVSSZrm_Intk:
7417 case X86::VDIVSSZrm_Intkz:
7418 case X86::VDIVSSZrr_Int:
7419 case X86::VDIVSSZrr_Intk:
7420 case X86::VDIVSSZrr_Intkz:
7421 case X86::VDIVSSZrrb:
7422 case X86::VDIVSSZrrbk:
7423 case X86::VDIVSSZrrbkz:
7424 case X86::VSQRTPDZ128m:
7425 case X86::VSQRTPDZ128mb:
7426 case X86::VSQRTPDZ128mbk:
7427 case X86::VSQRTPDZ128mbkz:
7428 case X86::VSQRTPDZ128mk:
7429 case X86::VSQRTPDZ128mkz:
7430 case X86::VSQRTPDZ128r:
7431 case X86::VSQRTPDZ128rk:
7432 case X86::VSQRTPDZ128rkz:
7433 case X86::VSQRTPDZ256m:
7434 case X86::VSQRTPDZ256mb:
7435 case X86::VSQRTPDZ256mbk:
7436 case X86::VSQRTPDZ256mbkz:
7437 case X86::VSQRTPDZ256mk:
7438 case X86::VSQRTPDZ256mkz:
7439 case X86::VSQRTPDZ256r:
7440 case X86::VSQRTPDZ256rk:
7441 case X86::VSQRTPDZ256rkz:
7442 case X86::VSQRTPDZm:
7443 case X86::VSQRTPDZmb:
7444 case X86::VSQRTPDZmbk:
7445 case X86::VSQRTPDZmbkz:
7446 case X86::VSQRTPDZmk:
7447 case X86::VSQRTPDZmkz:
7448 case X86::VSQRTPDZr:
7449 case X86::VSQRTPDZrb:
7450 case X86::VSQRTPDZrbk:
7451 case X86::VSQRTPDZrbkz:
7452 case X86::VSQRTPDZrk:
7453 case X86::VSQRTPDZrkz:
7454 case X86::VSQRTPSZ128m:
7455 case X86::VSQRTPSZ128mb:
7456 case X86::VSQRTPSZ128mbk:
7457 case X86::VSQRTPSZ128mbkz:
7458 case X86::VSQRTPSZ128mk:
7459 case X86::VSQRTPSZ128mkz:
7460 case X86::VSQRTPSZ128r:
7461 case X86::VSQRTPSZ128rk:
7462 case X86::VSQRTPSZ128rkz:
7463 case X86::VSQRTPSZ256m:
7464 case X86::VSQRTPSZ256mb:
7465 case X86::VSQRTPSZ256mbk:
7466 case X86::VSQRTPSZ256mbkz:
7467 case X86::VSQRTPSZ256mk:
7468 case X86::VSQRTPSZ256mkz:
7469 case X86::VSQRTPSZ256r:
7470 case X86::VSQRTPSZ256rk:
7471 case X86::VSQRTPSZ256rkz:
7472 case X86::VSQRTPSZm:
7473 case X86::VSQRTPSZmb:
7474 case X86::VSQRTPSZmbk:
7475 case X86::VSQRTPSZmbkz:
7476 case X86::VSQRTPSZmk:
7477 case X86::VSQRTPSZmkz:
7478 case X86::VSQRTPSZr:
7479 case X86::VSQRTPSZrb:
7480 case X86::VSQRTPSZrbk:
7481 case X86::VSQRTPSZrbkz:
7482 case X86::VSQRTPSZrk:
7483 case X86::VSQRTPSZrkz:
7484 case X86::VSQRTSDZm:
7485 case X86::VSQRTSDZm_Int:
7486 case X86::VSQRTSDZm_Intk:
7487 case X86::VSQRTSDZm_Intkz:
7488 case X86::VSQRTSDZr:
7489 case X86::VSQRTSDZr_Int:
7490 case X86::VSQRTSDZr_Intk:
7491 case X86::VSQRTSDZr_Intkz:
7492 case X86::VSQRTSDZrb_Int:
7493 case X86::VSQRTSDZrb_Intk:
7494 case X86::VSQRTSDZrb_Intkz:
7495 case X86::VSQRTSSZm:
7496 case X86::VSQRTSSZm_Int:
7497 case X86::VSQRTSSZm_Intk:
7498 case X86::VSQRTSSZm_Intkz:
7499 case X86::VSQRTSSZr:
7500 case X86::VSQRTSSZr_Int:
7501 case X86::VSQRTSSZr_Intk:
7502 case X86::VSQRTSSZr_Intkz:
7503 case X86::VSQRTSSZrb_Int:
7504 case X86::VSQRTSSZrb_Intk:
7505 case X86::VSQRTSSZrb_Intkz:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7506
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7507 case X86::VGATHERDPDYrm:
7508 case X86::VGATHERDPDZ128rm:
7509 case X86::VGATHERDPDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7510 case X86::VGATHERDPDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7511 case X86::VGATHERDPDrm:
7512 case X86::VGATHERDPSYrm:
7513 case X86::VGATHERDPSZ128rm:
7514 case X86::VGATHERDPSZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7515 case X86::VGATHERDPSZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7516 case X86::VGATHERDPSrm:
7517 case X86::VGATHERPF0DPDm:
7518 case X86::VGATHERPF0DPSm:
7519 case X86::VGATHERPF0QPDm:
7520 case X86::VGATHERPF0QPSm:
7521 case X86::VGATHERPF1DPDm:
7522 case X86::VGATHERPF1DPSm:
7523 case X86::VGATHERPF1QPDm:
7524 case X86::VGATHERPF1QPSm:
7525 case X86::VGATHERQPDYrm:
7526 case X86::VGATHERQPDZ128rm:
7527 case X86::VGATHERQPDZ256rm:
7528 case X86::VGATHERQPDZrm:
7529 case X86::VGATHERQPDrm:
7530 case X86::VGATHERQPSYrm:
7531 case X86::VGATHERQPSZ128rm:
7532 case X86::VGATHERQPSZ256rm:
7533 case X86::VGATHERQPSZrm:
7534 case X86::VGATHERQPSrm:
7535 case X86::VPGATHERDDYrm:
7536 case X86::VPGATHERDDZ128rm:
7537 case X86::VPGATHERDDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7538 case X86::VPGATHERDDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7539 case X86::VPGATHERDDrm:
7540 case X86::VPGATHERDQYrm:
7541 case X86::VPGATHERDQZ128rm:
7542 case X86::VPGATHERDQZ256rm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7543 case X86::VPGATHERDQZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7544 case X86::VPGATHERDQrm:
7545 case X86::VPGATHERQDYrm:
7546 case X86::VPGATHERQDZ128rm:
7547 case X86::VPGATHERQDZ256rm:
7548 case X86::VPGATHERQDZrm:
7549 case X86::VPGATHERQDrm:
7550 case X86::VPGATHERQQYrm:
7551 case X86::VPGATHERQQZ128rm:
7552 case X86::VPGATHERQQZ256rm:
7553 case X86::VPGATHERQQZrm:
7554 case X86::VPGATHERQQrm:
7555 case X86::VSCATTERDPDZ128mr:
7556 case X86::VSCATTERDPDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7557 case X86::VSCATTERDPDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7558 case X86::VSCATTERDPSZ128mr:
7559 case X86::VSCATTERDPSZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7560 case X86::VSCATTERDPSZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7561 case X86::VSCATTERPF0DPDm:
7562 case X86::VSCATTERPF0DPSm:
7563 case X86::VSCATTERPF0QPDm:
7564 case X86::VSCATTERPF0QPSm:
7565 case X86::VSCATTERPF1DPDm:
7566 case X86::VSCATTERPF1DPSm:
7567 case X86::VSCATTERPF1QPDm:
7568 case X86::VSCATTERPF1QPSm:
7569 case X86::VSCATTERQPDZ128mr:
7570 case X86::VSCATTERQPDZ256mr:
7571 case X86::VSCATTERQPDZmr:
7572 case X86::VSCATTERQPSZ128mr:
7573 case X86::VSCATTERQPSZ256mr:
7574 case X86::VSCATTERQPSZmr:
7575 case X86::VPSCATTERDDZ128mr:
7576 case X86::VPSCATTERDDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7577 case X86::VPSCATTERDDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7578 case X86::VPSCATTERDQZ128mr:
7579 case X86::VPSCATTERDQZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7580 case X86::VPSCATTERDQZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7581 case X86::VPSCATTERQDZ128mr:
7582 case X86::VPSCATTERQDZ256mr:
7583 case X86::VPSCATTERQDZmr:
7584 case X86::VPSCATTERQQZ128mr:
7585 case X86::VPSCATTERQQZ256mr:
7586 case X86::VPSCATTERQQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7587 return true;
7588 }
7589}
7590
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7591bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7592 const MachineRegisterInfo *MRI,
7593 const MachineInstr &DefMI,
7594 unsigned DefIdx,
7595 const MachineInstr &UseMI,
7596 unsigned UseIdx) const {
7597 return isHighLatencyDef(DefMI.getOpcode());
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7598}
7599
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7600bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7601 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7602 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7603 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7604
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7605 // Integer binary math/logic instructions have a third source operand:
7606 // the EFLAGS register. That operand must be both defined here and never
7607 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7608 // not change anything because rearranging the operands could affect other
7609 // instructions that depend on the exact status flags (zero, sign, etc.)
7610 // that are set by using these particular operands with this operation.
7611 if (Inst.getNumOperands() == 4) {
7612 assert(Inst.getOperand(3).isReg() &&
7613 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7614 "Unexpected operand in reassociable instruction");
7615 if (!Inst.getOperand(3).isDead())
7616 return false;
7617 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]7618
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7619 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7620}
7621
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7622// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7623// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7624// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7625// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7626bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7627 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7628 case X86::AND8rr:
7629 case X86::AND16rr:
7630 case X86::AND32rr:
7631 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]7632 case X86::OR8rr:
7633 case X86::OR16rr:
7634 case X86::OR32rr:
7635 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]7636 case X86::XOR8rr:
7637 case X86::XOR16rr:
7638 case X86::XOR32rr:
7639 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7640 case X86::IMUL16rr:
7641 case X86::IMUL32rr:
7642 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7643 case X86::PANDrr:
7644 case X86::PORrr:
7645 case X86::PXORrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame^]7646 case X86::ANDPDrr:
7647 case X86::ANDPSrr:
7648 case X86::ORPDrr:
7649 case X86::ORPSrr:
7650 case X86::XORPDrr:
7651 case X86::XORPSrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7652 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7653 case X86::VPANDYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7654 case X86::VPANDDZ128rr:
7655 case X86::VPANDDZ256rr:
7656 case X86::VPANDDZrr:
7657 case X86::VPANDQZ128rr:
7658 case X86::VPANDQZ256rr:
7659 case X86::VPANDQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7660 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7661 case X86::VPORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7662 case X86::VPORDZ128rr:
7663 case X86::VPORDZ256rr:
7664 case X86::VPORDZrr:
7665 case X86::VPORQZ128rr:
7666 case X86::VPORQZ256rr:
7667 case X86::VPORQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7668 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7669 case X86::VPXORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7670 case X86::VPXORDZ128rr:
7671 case X86::VPXORDZ256rr:
7672 case X86::VPXORDZrr:
7673 case X86::VPXORQZ128rr:
7674 case X86::VPXORQZ256rr:
7675 case X86::VPXORQZrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame^]7676 case X86::VANDPDrr:
7677 case X86::VANDPSrr:
7678 case X86::VANDPDYrr:
7679 case X86::VANDPSYrr:
7680 case X86::VANDPDZ128rr:
7681 case X86::VANDPSZ128rr:
7682 case X86::VANDPDZ256rr:
7683 case X86::VANDPSZ256rr:
7684 case X86::VANDPDZrr:
7685 case X86::VANDPSZrr:
7686 case X86::VORPDrr:
7687 case X86::VORPSrr:
7688 case X86::VORPDYrr:
7689 case X86::VORPSYrr:
7690 case X86::VORPDZ128rr:
7691 case X86::VORPSZ128rr:
7692 case X86::VORPDZ256rr:
7693 case X86::VORPSZ256rr:
7694 case X86::VORPDZrr:
7695 case X86::VORPSZrr:
7696 case X86::VXORPDrr:
7697 case X86::VXORPSrr:
7698 case X86::VXORPDYrr:
7699 case X86::VXORPSYrr:
7700 case X86::VXORPDZ128rr:
7701 case X86::VXORPSZ128rr:
7702 case X86::VXORPDZ256rr:
7703 case X86::VXORPSZ256rr:
7704 case X86::VXORPDZrr:
7705 case X86::VXORPSZrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7706 // Normal min/max instructions are not commutative because of NaN and signed
7707 // zero semantics, but these are. Thus, there's no need to check for global
7708 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7709 case X86::MAXCPDrr:
7710 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7711 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7712 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7713 case X86::MINCPDrr:
7714 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7715 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7716 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7717 case X86::VMAXCPDrr:
7718 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7719 case X86::VMAXCPDYrr:
7720 case X86::VMAXCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7721 case X86::VMAXCPDZ128rr:
7722 case X86::VMAXCPSZ128rr:
7723 case X86::VMAXCPDZ256rr:
7724 case X86::VMAXCPSZ256rr:
7725 case X86::VMAXCPDZrr:
7726 case X86::VMAXCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7727 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7728 case X86::VMAXCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7729 case X86::VMAXCSDZrr:
7730 case X86::VMAXCSSZrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7731 case X86::VMINCPDrr:
7732 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7733 case X86::VMINCPDYrr:
7734 case X86::VMINCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7735 case X86::VMINCPDZ128rr:
7736 case X86::VMINCPSZ128rr:
7737 case X86::VMINCPDZ256rr:
7738 case X86::VMINCPSZ256rr:
7739 case X86::VMINCPDZrr:
7740 case X86::VMINCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7741 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7742 case X86::VMINCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7743 case X86::VMINCSDZrr:
7744 case X86::VMINCSSZrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7745 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7746 case X86::ADDPDrr:
7747 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7748 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7749 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7750 case X86::MULPDrr:
7751 case X86::MULPSrr:
7752 case X86::MULSDrr:
7753 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7754 case X86::VADDPDrr:
7755 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7756 case X86::VADDPDYrr:
7757 case X86::VADDPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7758 case X86::VADDPDZ128rr:
7759 case X86::VADDPSZ128rr:
7760 case X86::VADDPDZ256rr:
7761 case X86::VADDPSZ256rr:
7762 case X86::VADDPDZrr:
7763 case X86::VADDPSZrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7764 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7765 case X86::VADDSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7766 case X86::VADDSDZrr:
7767 case X86::VADDSSZrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7768 case X86::VMULPDrr:
7769 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7770 case X86::VMULPDYrr:
7771 case X86::VMULPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7772 case X86::VMULPDZ128rr:
7773 case X86::VMULPSZ128rr:
7774 case X86::VMULPDZ256rr:
7775 case X86::VMULPSZ256rr:
7776 case X86::VMULPDZrr:
7777 case X86::VMULPSZrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7778 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7779 case X86::VMULSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7780 case X86::VMULSDZrr:
7781 case X86::VMULSSZrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7782 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7783 default:
7784 return false;
7785 }
7786}
7787
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7788/// This is an architecture-specific helper function of reassociateOps.
7789/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7790void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7791 MachineInstr &OldMI2,
7792 MachineInstr &NewMI1,
7793 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7794 // Integer instructions define an implicit EFLAGS source register operand as
7795 // the third source (fourth total) operand.
7796 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7797 return;
7798
7799 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7800 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7801
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7802 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7803 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7804 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7805 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7806
7807 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7808 "Must have dead EFLAGS operand in reassociable instruction");
7809 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7810 "Must have dead EFLAGS operand in reassociable instruction");
7811
7812 (void)OldOp1;
7813 (void)OldOp2;
7814
7815 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7816 "Unexpected operand in reassociable instruction");
7817 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7818 "Unexpected operand in reassociable instruction");
7819
7820 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7821 // of this pass or other passes. The EFLAGS operands must be dead in these new
7822 // instructions because the EFLAGS operands in the original instructions must
7823 // be dead in order for reassociation to occur.
7824 NewOp1.setIsDead();
7825 NewOp2.setIsDead();
7826}
7827
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7828std::pair<unsigned, unsigned>
7829X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7830 return std::make_pair(TF, 0u);
7831}
7832
7833ArrayRef<std::pair<unsigned, const char *>>
7834X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7835 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]7836 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7837 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7838 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7839 {MO_GOT, "x86-got"},
7840 {MO_GOTOFF, "x86-gotoff"},
7841 {MO_GOTPCREL, "x86-gotpcrel"},
7842 {MO_PLT, "x86-plt"},
7843 {MO_TLSGD, "x86-tlsgd"},
7844 {MO_TLSLD, "x86-tlsld"},
7845 {MO_TLSLDM, "x86-tlsldm"},
7846 {MO_GOTTPOFF, "x86-gottpoff"},
7847 {MO_INDNTPOFF, "x86-indntpoff"},
7848 {MO_TPOFF, "x86-tpoff"},
7849 {MO_DTPOFF, "x86-dtpoff"},
7850 {MO_NTPOFF, "x86-ntpoff"},
7851 {MO_GOTNTPOFF, "x86-gotntpoff"},
7852 {MO_DLLIMPORT, "x86-dllimport"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7853 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7854 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7855 {MO_TLVP, "x86-tlvp"},
7856 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7857 {MO_SECREL, "x86-secrel"}};
7858 return makeArrayRef(TargetFlags);
7859}
7860
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7861namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7862 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7863 /// global base register for x86-32.
7864 struct CGBR : public MachineFunctionPass {
7865 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]7866 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7867
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7868 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7869 const X86TargetMachine *TM =
7870 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7871 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7872
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7873 // Don't do anything if this is 64-bit as 64-bit PIC
7874 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7875 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7876 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7877
7878 // Only emit a global base reg in PIC mode.
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]7879 if (!TM->isPositionIndependent())
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7880 return false;
7881
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7882 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7883 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7884
7885 // If we didn't need a GlobalBaseReg, don't insert code.
7886 if (GlobalBaseReg == 0)
7887 return false;
7888
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7889 // Insert the set of GlobalBaseReg into the first MBB of the function
7890 MachineBasicBlock &FirstMBB = MF.front();
7891 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7892 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7893 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7894 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7895
7896 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7897 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]7898 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7899 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7900 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7901
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7902 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7903 // only used in JIT code emission as displacement to pc.
7904 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7905
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7906 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7907 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7908 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7909 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7910 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7911 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7912 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7913 }
7914
7915 return true;
7916 }
7917
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7918 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7919 return "X86 PIC Global Base Reg Initialization";
7920 }
7921
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7922 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7923 AU.setPreservesCFG();
7924 MachineFunctionPass::getAnalysisUsage(AU);
7925 }
7926 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7927}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7928
7929char CGBR::ID = 0;
7930FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]7931llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7932
7933namespace {
7934 struct LDTLSCleanup : public MachineFunctionPass {
7935 static char ID;
7936 LDTLSCleanup() : MachineFunctionPass(ID) {}
7937
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7938 bool runOnMachineFunction(MachineFunction &MF) override {
Andrew Kaylor2bee5ef2016-04-26 21:44:24 +0000[diff] [blame]7939 if (skipFunction(*MF.getFunction()))
7940 return false;
7941
7942 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7943 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7944 // No point folding accesses if there isn't at least two.
7945 return false;
7946 }
7947
7948 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7949 return VisitNode(DT->getRootNode(), 0);
7950 }
7951
7952 // Visit the dominator subtree rooted at Node in pre-order.
7953 // If TLSBaseAddrReg is non-null, then use that to replace any
7954 // TLS_base_addr instructions. Otherwise, create the register
7955 // when the first such instruction is seen, and then use it
7956 // as we encounter more instructions.
7957 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7958 MachineBasicBlock *BB = Node->getBlock();
7959 bool Changed = false;
7960
7961 // Traverse the current block.
7962 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7963 ++I) {
7964 switch (I->getOpcode()) {
7965 case X86::TLS_base_addr32:
7966 case X86::TLS_base_addr64:
7967 if (TLSBaseAddrReg)
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]7968 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7969 else
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]7970 I = SetRegister(*I, &TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7971 Changed = true;
7972 break;
7973 default:
7974 break;
7975 }
7976 }
7977
7978 // Visit the children of this block in the dominator tree.
7979 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7980 I != E; ++I) {
7981 Changed |= VisitNode(*I, TLSBaseAddrReg);
7982 }
7983
7984 return Changed;
7985 }
7986
7987 // Replace the TLS_base_addr instruction I with a copy from
7988 // TLSBaseAddrReg, returning the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]7989 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7990 unsigned TLSBaseAddrReg) {
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]7991 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7992 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7993 const bool is64Bit = STI.is64Bit();
7994 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7995
7996 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]7997 MachineInstr *Copy =
7998 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7999 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8000 .addReg(TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8001
8002 // Erase the TLS_base_addr instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8003 I.eraseFromParent();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8004
8005 return Copy;
8006 }
8007
8008 // Create a virtal register in *TLSBaseAddrReg, and populate it by
8009 // inserting a copy instruction after I. Returns the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8010 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8011 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8012 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8013 const bool is64Bit = STI.is64Bit();
8014 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8015
8016 // Create a virtual register for the TLS base address.
8017 MachineRegisterInfo &RegInfo = MF->getRegInfo();
8018 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8019 ? &X86::GR64RegClass
8020 : &X86::GR32RegClass);
8021
8022 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8023 MachineInstr *Next = I.getNextNode();
8024 MachineInstr *Copy =
8025 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8026 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8027 .addReg(is64Bit ? X86::RAX : X86::EAX);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8028
8029 return Copy;
8030 }
8031
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8032 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8033 return "Local Dynamic TLS Access Clean-up";
8034 }
8035
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8036 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8037 AU.setPreservesCFG();
8038 AU.addRequired<MachineDominatorTree>();
8039 MachineFunctionPass::getAnalysisUsage(AU);
8040 }
8041 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8042}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8043
8044char LDTLSCleanup::ID = 0;
8045FunctionPass*
8046llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }