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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 8aea3173045b9030b2c7900dd0e7166c4f5d14f3 / . / arch / arm / boot / dts / msm8226.dtsi
blob: 7d44d7d7c3e8e995490d9dfee992a84b3206c70c [file] [log] [blame]
Mitchel Humpherys85d08692012-10-23 12:56:35 -0700[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Stepan Moskovchenko7d8cdcaa2013-04-25 17:10:55 -0700[diff] [blame]14
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]15/ {
16 model = "Qualcomm MSM 8226";
17 compatible = "qcom,msm8226";
18 interrupt-parent = <&intc>;
19
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]20 aliases {
21 spi0 = &spi_0;
Sahitya Tummala9e001362013-03-28 11:00:55 +0530[diff] [blame]22 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
23 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]24 };
25
Laura Abbottf3196b22013-03-11 16:22:34 -0700[diff] [blame]26 memory {
27 secure_mem: secure_region {
28 linux,contiguous-region;
29 reg = <0 0x3800000>;
30 label = "secure_mem";
31 };
Laura Abbott429e82b2013-03-25 13:03:06 -0700[diff] [blame]32
33 qsecom_mem: qsecom_region {
34 linux,contiguous-region;
35 reg = <0 0x780000>;
36 label = "qsecom_mem";
37 };
Stepan Moskovchenko7d8cdcaa2013-04-25 17:10:55 -0700[diff] [blame]38 };
Laura Abbott429e82b2013-03-25 13:03:06 -0700[diff] [blame]39
Stepan Moskovchenko7d8cdcaa2013-04-25 17:10:55 -0700[diff] [blame]40 soc: soc { };
41};
42
43/include/ "msm8226-ion.dtsi"
44/include/ "msm8226-camera.dtsi"
45/include/ "msm-gdsc.dtsi"
46/include/ "msm8226-iommu.dtsi"
47/include/ "msm8226-pm.dtsi"
48/include/ "msm8226-smp2p.dtsi"
49/include/ "msm8226-gpu.dtsi"
50/include/ "msm8226-bus.dtsi"
51/include/ "msm8226-mdss.dtsi"
52/include/ "msm8226-coresight.dtsi"
53/include/ "msm8226-iommu-domains.dtsi"
54
55&soc {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges;
59
60 intc: interrupt-controller@f9000000 {
61 compatible = "qcom,msm-qgic2";
62 interrupt-controller;
63 #interrupt-cells = <3>;
64 reg = <0xF9000000 0x1000>,
65 <0xF9002000 0x1000>;
66 };
67
68 msmgpio: gpio@fd510000 {
69 compatible = "qcom,msm-gpio";
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 reg = <0xfd510000 0x4000>;
73 gpio-controller;
74 #gpio-cells = <2>;
75 ngpio = <117>;
76 interrupts = <0 208 0>;
77 qcom,direct-connect-irqs = <8>;
Laura Abbottf3196b22013-03-11 16:22:34 -0700[diff] [blame]78 };
79
Abhimanyu Kapur58d303a72013-04-30 16:13:41 -0700[diff] [blame]80 qcom,mpm2-sleep-counter@fc4a3000 {
81 compatible = "qcom,mpm2-sleep-counter";
82 reg = <0xfc4a3000 0x1000>;
83 clock-frequency = <32768>;
84 };
85
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]86 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -0800[diff] [blame]87 compatible = "arm,armv7-timer";
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]88 interrupts = <1 2 0 1 3 0>;
89 clock-frequency = <19200000>;
90 };
91
Stephen Boyd72759f62013-04-10 14:20:27 -0700[diff] [blame]92 timer@f9020000 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 compatible = "arm,armv7-timer-mem";
97 reg = <0xf9020000 0x1000>;
98 clock-frequency = <19200000>;
99
100 frame@f9021000 {
101 frame-number = <0>;
102 interrupts = <0 8 0x4>,
103 <0 7 0x4>;
104 reg = <0xf9021000 0x1000>,
105 <0xf9022000 0x1000>;
106 };
107
108 frame@f9023000 {
109 frame-number = <1>;
110 interrupts = <0 9 0x4>;
111 reg = <0xf9023000 0x1000>;
112 status = "disabled";
113 };
114
115 frame@f9024000 {
116 frame-number = <2>;
117 interrupts = <0 10 0x4>;
118 reg = <0xf9024000 0x1000>;
119 status = "disabled";
120 };
121
122 frame@f9025000 {
123 frame-number = <3>;
124 interrupts = <0 11 0x4>;
125 reg = <0xf9025000 0x1000>;
126 status = "disabled";
127 };
128
129 frame@f9026000 {
130 frame-number = <4>;
131 interrupts = <0 12 0x4>;
132 reg = <0xf9026000 0x1000>;
133 status = "disabled";
134 };
135
136 frame@f9027000 {
137 frame-number = <5>;
138 interrupts = <0 13 0x4>;
139 reg = <0xf9027000 0x1000>;
140 status = "disabled";
141 };
142
143 frame@f9028000 {
144 frame-number = <6>;
145 interrupts = <0 14 0x4>;
146 reg = <0xf9028000 0x1000>;
147 status = "disabled";
148 };
149 };
150
Ashray Kulkarnifbf88dbd2013-02-22 18:02:26 -0800[diff] [blame]151 qcom,vidc@fdc00000 {
152 compatible = "qcom,msm-vidc";
153 reg = <0xfdc00000 0xff000>;
154 interrupts = <0 44 0>;
155 qcom,load-freq-tbl = <352800 160000000>,
156 <244800 133330000>,
157 <108000 66700000>;
158 qcom,hfi = "venus";
159 qcom,bus-ports = <1>;
160 qcom,reg-presets = <0xE0024 0x0>,
161 <0x80124 0x3>,
162 <0xE0020 0x5555556>,
163 <0x800B0 0x10101001>,
164 <0x800B4 0x00101010>,
165 <0x800C0 0x1010100f>,
166 <0x800C4 0x00101010>,
167 <0x800D0 0x00000010>,
168 <0x800D4 0x00000010>,
169 <0x800D8 0x00000707>;
170 qcom,enc-ddr-ab-ib = <0 0>,
171 <129000 142000>,
172 <384000 422000>,
173 <866000 953000>;
174 qcom,dec-ddr-ab-ib = <0 0>,
175 <103000 134000>,
176 <268000 348000>,
177 <505000 657000>;
178 qcom,iommu-groups = <&venus_domain_ns &venus_domain_cp>;
179 qcom,iommu-group-buffer-types = <0xfff 0x1ff>;
180 qcom,buffer-type-tz-usage-table = <0x1 0x1>,
181 <0x1fe 0x2>;
Deva Ramasubramanian74b1dda2013-03-27 13:16:17 -0700[diff] [blame]182 qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
Ashray Kulkarnifbf88dbd2013-02-22 18:02:26 -0800[diff] [blame]183 };
184
185 qcom,wfd {
186 compatible = "qcom,msm-wfd";
187 };
188
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]189 serial@f991f000 {
190 compatible = "qcom,msm-lsuart-v14";
191 reg = <0xf991f000 0x1000>;
192 interrupts = <0 109 0>;
193 status = "disabled";
194 };
195
196 serial@f995e000 {
197 compatible = "qcom,msm-lsuart-v14";
198 reg = <0xf995e000 0x1000>;
199 interrupts = <0 114 0>;
200 status = "disabled";
201 };
202
Abhimanyu Kapur032b1f42013-01-18 00:10:50 -0800[diff] [blame]203 qcom,msm-imem@fe805000 {
204 compatible = "qcom,msm-imem";
205 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
206 };
207
Yan He7c06ce32012-12-03 17:12:31 -0800[diff] [blame]208 qcom,sps@f9984000 {
209 compatible = "qcom,msm_sps";
210 reg = <0xf9984000 0x15000>,
211 <0xf9999000 0xb000>;
212 interrupts = <0 94 0>;
213 };
214
Vamsi Krishna840835b2013-04-01 22:01:05 -0700[diff] [blame]215 qcom,usbbam@f9a44000 {
216 compatible = "qcom,usb-bam-msm";
217 reg = <0xf9a44000 0x11000>;
218 reg-names = "hsusb";
219 interrupts = <0 135 0>;
220 interrupt-names = "hsusb";
221 qcom,usb-bam-num-pipes = <16>;
222 qcom,usb-bam-fifo-baseaddr = <0xfe803000>;
223 qcom,ignore-core-reset-ack;
224 qcom,disable-clk-gating;
225
226 qcom,pipe0 {
227 label = "hsusb-qdss-in-0";
228 qcom,usb-bam-mem-type = <3>;
229 qcom,bam-type = <1>;
230 qcom,dir = <1>;
231 qcom,pipe-num = <0>;
232 qcom,peer-bam = <1>;
233 qcom,src-bam-physical-address = <0xfc37c000>;
234 qcom,src-bam-pipe-index = <0>;
235 qcom,dst-bam-physical-address = <0xf9a44000>;
236 qcom,dst-bam-pipe-index = <2>;
237 qcom,data-fifo-offset = <0x0>;
238 qcom,data-fifo-size = <0x600>;
239 qcom,descriptor-fifo-offset = <0x600>;
240 qcom,descriptor-fifo-size = <0x200>;
241 };
242 };
243
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]244 usb@f9a55000 {
245 compatible = "qcom,hsusb-otg";
246 reg = <0xf9a55000 0x400>;
Mayank Ranaac2a54f2013-01-17 10:14:35 +0530[diff] [blame]247 interrupts = <0 134 0>, <0 140 0>;
248 interrupt-names = "core_irq", "async_irq";
Mayank Rana8335a772013-03-06 10:12:27 +0530[diff] [blame]249 hsusb_vdd_dig-supply = <&pm8226_s1_corner>;
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]250 HSUSB_1p8-supply = <&pm8226_l10>;
251 HSUSB_3p3-supply = <&pm8226_l20>;
Mayank Rana8335a772013-03-06 10:12:27 +0530[diff] [blame]252 qcom,vdd-voltage-level = <1 5 7>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]253
Vamsi Krishna1f265912013-04-22 22:50:06 -0700[diff] [blame]254 qcom,hsusb-otg-phy-init-seq =
255 <0x44 0x80 0x68 0x81 0x24 0x82 0x13 0x83 0xffffffff>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]256 qcom,hsusb-otg-phy-type = <2>;
257 qcom,hsusb-otg-mode = <1>;
Vamsi Krishna0d564102013-03-02 15:26:55 -0800[diff] [blame]258 qcom,hsusb-otg-otg-control = <2>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]259 qcom,hsusb-otg-disable-reset;
Mayank Rana15f01b52013-03-08 18:28:56 +0530[diff] [blame]260 qcom,dp-manual-pullup;
Mayank Rana5403e2a2013-02-26 11:18:39 +0530[diff] [blame]261
262 qcom,msm-bus,name = "usb2";
263 qcom,msm-bus,num-cases = <2>;
Mayank Rana5403e2a2013-02-26 11:18:39 +0530[diff] [blame]264 qcom,msm-bus,num-paths = <1>;
265 qcom,msm-bus,vectors-KBps =
266 <87 512 0 0>,
267 <87 512 60000 960000>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]268 };
269
Mayank Rana6bd9a272013-01-29 16:23:23 +0530[diff] [blame]270 android_usb@fe8050c8 {
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]271 compatible = "qcom,android-usb";
Mayank Rana6bd9a272013-01-29 16:23:23 +0530[diff] [blame]272 reg = <0xfe8050c8 0xc8>;
Chiranjeevi Velempati9d797662013-04-22 15:45:38 +0530[diff] [blame]273 qcom,android-usb-cdrom;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]274 };
275
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]276 wcd9xxx_intc: wcd9xxx-irq {
277 compatible = "qcom,wcd9xxx-irq";
278 interrupt-controller;
279 #interrupt-cells = <1>;
280 interrupt-parent = <&msmgpio>;
281 interrupts = <68 0>;
282 interrupt-names = "cdc-int";
283 };
284
Bhalchandra Gajarefb785972012-12-06 19:25:10 -0800[diff] [blame]285 slim@fe12f000 {
286 cell-index = <1>;
287 compatible = "qcom,slim-ngd";
288 reg = <0xfe12f000 0x35000>,
289 <0xfe104000 0x20000>;
290 reg-names = "slimbus_physical", "slimbus_bam_physical";
291 interrupts = <0 163 0>, <0 164 0>;
292 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]293
294 tapan_codec {
295 compatible = "qcom,tapan-slim-pgd";
296 elemental-addr = [00 01 E0 00 17 02];
297
298 interrupt-parent = <&wcd9xxx_intc>;
299 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
300 17 18 19 20 21 22 23 24 25 26 27 28>;
301 qcom,cdc-reset-gpio = <&msmgpio 72 0>;
302
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]303 cdc-vdd-buck-supply = <&pm8226_s4>;
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]304 qcom,cdc-vdd-buck-voltage = <2100000 2100000>;
305 qcom,cdc-vdd-buck-current = <650000>;
306
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]307 cdc-vdd-h-supply = <&pm8226_l6>;
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]308 qcom,cdc-vdd-h-voltage = <1800000 1800000>;
309 qcom,cdc-vdd-h-current = <25000>;
310
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]311 cdc-vdd-px-supply = <&pm8226_l6>;
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]312 qcom,cdc-vdd-px-voltage = <1800000 1800000>;
313 qcom,cdc-vdd-px-current = <25000>;
314
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]315 cdc-vdd-a-1p2v-supply = <&pm8226_l4>;
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]316 qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
317 qcom,cdc-vdd-a-1p2v-current = <10000>;
318
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]319 cdc-vdd-cx-supply = <&pm8226_l4>;
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]320 qcom,cdc-vdd-cx-voltage = <1200000 1200000>;
321 qcom,cdc-vdd-cx-current = <10000>;
322
Joonwoo Park73239212013-04-10 15:11:06 -0700[diff] [blame]323 qcom,cdc-static-supplies = "cdc-vdd-buck",
324 "cdc-vdd-h",
325 "cdc-vdd-px",
326 "cdc-vdd-a-1p2v",
327 "cdc-vdd-cx";
328
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]329 qcom,cdc-micbias-ldoh-v = <0x3>;
330 qcom,cdc-micbias-cfilt1-mv = <1800>;
331 qcom,cdc-micbias-cfilt2-mv = <1800>;
332 qcom,cdc-micbias-cfilt3-mv = <1800>;
333
334 qcom,cdc-micbias1-cfilt-sel = <0x0>;
335 qcom,cdc-micbias2-cfilt-sel = <0x1>;
336 qcom,cdc-micbias3-cfilt-sel = <0x2>;
337
338 qcom,cdc-mclk-clk-rate = <9600000>;
339 qcom,cdc-slim-ifd = "tapan-slim-ifd";
340 qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02];
341 };
Bhalchandra Gajarefb785972012-12-06 19:25:10 -0800[diff] [blame]342 };
343
Bhalchandra Gajaree1915b82012-12-12 17:28:39 -0800[diff] [blame]344 qcom,msm-adsp-loader {
345 compatible = "qcom,adsp-loader";
346 qcom,adsp-state = <0>;
347 };
348
Bhalchandra Gajare03a40ec2012-12-17 11:38:28 -0800[diff] [blame]349 sound {
350 compatible = "qcom,msm8226-audio-tapan";
351 qcom,model = "msm8226-tapan-snd-card";
Bhalchandra Gajare03a40ec2012-12-17 11:38:28 -0800[diff] [blame]352 qcom,tapan-mclk-clk-freq = <9600000>;
353 };
354
355 qcom,msm-pcm {
356 compatible = "qcom,msm-pcm-dsp";
Bhalchandra Gajare510d4422013-03-01 21:07:12 -0800[diff] [blame]357 qcom,msm-pcm-dsp-id = <0>;
Bhalchandra Gajare03a40ec2012-12-17 11:38:28 -0800[diff] [blame]358 };
359
360 qcom,msm-pcm-routing {
361 compatible = "qcom,msm-pcm-routing";
362 };
363
Bhalchandra Gajare18468a62013-03-11 18:32:49 -0700[diff] [blame]364 qcom,msm-pcm-low-latency {
365 compatible = "qcom,msm-pcm-dsp";
366 qcom,msm-pcm-dsp-id = <1>;
367 qcom,msm-pcm-low-latency;
368 };
369
Bhalchandra Gajare03a40ec2012-12-17 11:38:28 -0800[diff] [blame]370 qcom,msm-pcm-lpa {
371 compatible = "qcom,msm-pcm-lpa";
372 };
373
374 qcom,msm-compr-dsp {
375 compatible = "qcom,msm-compr-dsp";
376 };
377
378 qcom,msm-voip-dsp {
379 compatible = "qcom,msm-voip-dsp";
380 };
381
382 qcom,msm-pcm-voice {
383 compatible = "qcom,msm-pcm-voice";
384 };
385
386 qcom,msm-stub-codec {
387 compatible = "qcom,msm-stub-codec";
388 };
389
390 qcom,msm-dai-fe {
391 compatible = "qcom,msm-dai-fe";
392 };
393
394 qcom,msm-pcm-afe {
395 compatible = "qcom,msm-pcm-afe";
396 };
397
398 qcom,msm-dai-q6-hdmi {
399 compatible = "qcom,msm-dai-q6-hdmi";
400 qcom,msm-dai-q6-dev-id = <8>;
401 };
402
403 qcom,msm-dai-q6 {
404 compatible = "qcom,msm-dai-q6";
405 qcom,msm-dai-q6-sb-0-rx {
406 compatible = "qcom,msm-dai-q6-dev";
407 qcom,msm-dai-q6-dev-id = <16384>;
408 };
409
410 qcom,msm-dai-q6-sb-0-tx {
411 compatible = "qcom,msm-dai-q6-dev";
412 qcom,msm-dai-q6-dev-id = <16385>;
413 };
414
415 qcom,msm-dai-q6-sb-1-rx {
416 compatible = "qcom,msm-dai-q6-dev";
417 qcom,msm-dai-q6-dev-id = <16386>;
418 };
419
420 qcom,msm-dai-q6-sb-1-tx {
421 compatible = "qcom,msm-dai-q6-dev";
422 qcom,msm-dai-q6-dev-id = <16387>;
423 };
424
425 qcom,msm-dai-q6-sb-3-rx {
426 compatible = "qcom,msm-dai-q6-dev";
427 qcom,msm-dai-q6-dev-id = <16390>;
428 };
429
430 qcom,msm-dai-q6-sb-3-tx {
431 compatible = "qcom,msm-dai-q6-dev";
432 qcom,msm-dai-q6-dev-id = <16391>;
433 };
434
435 qcom,msm-dai-q6-sb-4-rx {
436 compatible = "qcom,msm-dai-q6-dev";
437 qcom,msm-dai-q6-dev-id = <16392>;
438 };
439
440 qcom,msm-dai-q6-sb-4-tx {
441 compatible = "qcom,msm-dai-q6-dev";
442 qcom,msm-dai-q6-dev-id = <16393>;
443 };
444
445 qcom,msm-dai-q6-bt-sco-rx {
446 compatible = "qcom,msm-dai-q6-dev";
447 qcom,msm-dai-q6-dev-id = <12288>;
448 };
449
450 qcom,msm-dai-q6-bt-sco-tx {
451 compatible = "qcom,msm-dai-q6-dev";
452 qcom,msm-dai-q6-dev-id = <12289>;
453 };
454
455 qcom,msm-dai-q6-int-fm-rx {
456 compatible = "qcom,msm-dai-q6-dev";
457 qcom,msm-dai-q6-dev-id = <12292>;
458 };
459
460 qcom,msm-dai-q6-int-fm-tx {
461 compatible = "qcom,msm-dai-q6-dev";
462 qcom,msm-dai-q6-dev-id = <12293>;
463 };
464
465 qcom,msm-dai-q6-be-afe-pcm-rx {
466 compatible = "qcom,msm-dai-q6-dev";
467 qcom,msm-dai-q6-dev-id = <224>;
468 };
469
470 qcom,msm-dai-q6-be-afe-pcm-tx {
471 compatible = "qcom,msm-dai-q6-dev";
472 qcom,msm-dai-q6-dev-id = <225>;
473 };
474
475 qcom,msm-dai-q6-afe-proxy-rx {
476 compatible = "qcom,msm-dai-q6-dev";
477 qcom,msm-dai-q6-dev-id = <241>;
478 };
479
480 qcom,msm-dai-q6-afe-proxy-tx {
481 compatible = "qcom,msm-dai-q6-dev";
482 qcom,msm-dai-q6-dev-id = <240>;
483 };
Vicky Sehrawat2ef554c2013-03-12 17:24:20 -0700[diff] [blame]484
485 qcom,msm-dai-q6-incall-record-rx {
486 compatible = "qcom,msm-dai-q6-dev";
487 qcom,msm-dai-q6-dev-id = <32771>;
488 };
489
490 qcom,msm-dai-q6-incall-record-tx {
491 compatible = "qcom,msm-dai-q6-dev";
492 qcom,msm-dai-q6-dev-id = <32772>;
493 };
494
495 qcom,msm-dai-q6-incall-music-rx {
496 compatible = "qcom,msm-dai-q6-dev";
497 qcom,msm-dai-q6-dev-id = <32773>;
498 };
Bhalchandra Gajare03a40ec2012-12-17 11:38:28 -0800[diff] [blame]499 };
500
501 qcom,msm-pcm-hostless {
502 compatible = "qcom,msm-pcm-hostless";
503 };
504
Sheng Fangb6a06482013-03-20 13:21:36 +0800[diff] [blame]505 qcom,wcnss-wlan@fb000000 {
506 compatible = "qcom,wcnss_wlan";
Sameer Thalappil58281ca2013-04-10 18:50:18 -0700[diff] [blame]507 reg = <0xfb000000 0x280000>,
508 <0xf9011008 0x04>;
509 reg-names = "wcnss_mmio", "wcnss_fiq";
Sheng Fangb6a06482013-03-20 13:21:36 +0800[diff] [blame]510 interrupts = <0 145 0 0 146 0>;
511 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
512
513 qcom,pronto-vddmx-supply = <&pm8226_l3>;
514 qcom,pronto-vddcx-supply = <&pm8226_s1>;
515 qcom,pronto-vddpx-supply = <&pm8226_l6>;
516 qcom,iris-vddxo-supply = <&pm8226_l10>;
517 qcom,iris-vddrfa-supply = <&pm8226_l24>;
518 qcom,iris-vddpa-supply = <&pm8226_l16>;
519 qcom,iris-vdddig-supply = <&pm8226_l24>;
520
521 gpios = <&msmgpio 40 0>, <&msmgpio 41 0>, <&msmgpio 42 0>, <&msmgpio 43 0>, <&msmgpio 44 0>;
522 qcom,has_pronto_hw;
523 };
rockiec44833a32013-03-21 02:06:14 +0800[diff] [blame]524
525 qcom,msm-adsp-sensors {
526 compatible = "qcom,msm-adsp-sensors";
527 qcom,src-id = <11>;
528 qcom,dst-id = <604>;
529 qcom,ab = <32505856>;
530 qcom,ib = <32505856>;
531 };
532
Mitchel Humpherys5fe1c9b2012-10-09 17:30:19 -0700[diff] [blame]533 qcom,wdt@f9017000 {
534 compatible = "qcom,msm-watchdog";
535 reg = <0xf9017000 0x1000>;
536 interrupts = <0 3 0>, <0 4 0>;
537 qcom,bark-time = <11000>;
538 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800[diff] [blame]539 qcom,ipi-ping;
Mitchel Humpherys5fe1c9b2012-10-09 17:30:19 -0700[diff] [blame]540 };
541
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]542 qcom,smem@fa00000 {
543 compatible = "qcom,smem";
Jeff Hugo41e5c2f2013-04-26 11:38:32 -0600[diff] [blame]544 reg = <0xfa00000 0x100000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800[diff] [blame]545 <0xf9011000 0x1000>,
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]546 <0xfc428000 0x4000>;
547 reg-names = "smem", "irq-reg-base", "aux-mem1";
548
549 qcom,smd-modem {
550 compatible = "qcom,smd";
551 qcom,smd-edge = <0>;
552 qcom,smd-irq-offset = <0x8>;
553 qcom,smd-irq-bitmask = <0x1000>;
554 qcom,pil-string = "modem";
555 interrupts = <0 25 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]556 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]557
558 qcom,smsm-modem {
559 compatible = "qcom,smsm";
560 qcom,smsm-edge = <0>;
561 qcom,smsm-irq-offset = <0x8>;
562 qcom,smsm-irq-bitmask = <0x2000>;
563 interrupts = <0 26 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]564 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]565
566 qcom,smd-adsp {
567 compatible = "qcom,smd";
568 qcom,smd-edge = <1>;
569 qcom,smd-irq-offset = <0x8>;
570 qcom,smd-irq-bitmask = <0x100>;
571 qcom,pil-string = "adsp";
572 interrupts = <0 156 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]573 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]574
575 qcom,smsm-adsp {
576 compatible = "qcom,smsm";
577 qcom,smsm-edge = <1>;
578 qcom,smsm-irq-offset = <0x8>;
579 qcom,smsm-irq-bitmask = <0x200>;
580 interrupts = <0 157 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]581 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]582
583 qcom,smd-wcnss {
584 compatible = "qcom,smd";
585 qcom,smd-edge = <6>;
586 qcom,smd-irq-offset = <0x8>;
587 qcom,smd-irq-bitmask = <0x20000>;
588 qcom,pil-string = "wcnss";
589 interrupts = <0 142 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]590 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]591
592 qcom,smsm-wcnss {
593 compatible = "qcom,smsm";
594 qcom,smsm-edge = <6>;
595 qcom,smsm-irq-offset = <0x8>;
596 qcom,smsm-irq-bitmask = <0x80000>;
597 interrupts = <0 144 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]598 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]599
600 qcom,smd-rpm {
601 compatible = "qcom,smd";
602 qcom,smd-edge = <15>;
603 qcom,smd-irq-offset = <0x8>;
604 qcom,smd-irq-bitmask = <0x1>;
605 interrupts = <0 168 1>;
606 qcom,irq-no-suspend;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]607 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]608 };
609
Praveen Chidambaramc8af25e2012-12-19 11:27:36 -0700[diff] [blame]610 rpm_bus: qcom,rpm-smd {
611 compatible = "qcom,rpm-smd";
612 rpm-channel-name = "rpm_requests";
613 rpm-channel-type = <15>; /* SMD_APPS_RPM */
Praveen Chidambaramc8af25e2012-12-19 11:27:36 -0700[diff] [blame]614 };
615
Asutosh Das99912e62012-12-06 12:38:46 +0530[diff] [blame]616 sdcc1: qcom,sdcc@f9824000 {
617 cell-index = <1>; /* SDC1 eMMC slot */
618 compatible = "qcom,msm-sdcc";
619
Asutosh Das6b82fc52012-11-23 12:00:26 +0530[diff] [blame]620 reg = <0xf9824000 0x800>,
621 <0xf9824800 0x100>,
622 <0xf9804000 0x7000>;
623 reg-names = "core_mem", "dml_mem", "bam_mem";
624 interrupts = <0 123 0>, <0 137 0>;
625 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530[diff] [blame]626
627 qcom,bus-width = <8>;
628 status = "disabled";
629 };
630
Sahitya Tummala9e001362013-03-28 11:00:55 +0530[diff] [blame]631 sdhc_1: sdhci@f9824900 {
632 compatible = "qcom,sdhci-msm";
633 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
634 reg-names = "hc_mem", "core_mem";
635
636 interrupts = <0 123 0>, <0 138 0>;
637 interrupt-names = "hc_irq", "pwr_irq";
638
639 qcom,bus-width = <8>;
640 status = "disabled";
641 };
642
Asutosh Das99912e62012-12-06 12:38:46 +0530[diff] [blame]643 sdcc2: qcom,sdcc@f98a4000 {
644 cell-index = <2>; /* SDC2 SD card slot */
645 compatible = "qcom,msm-sdcc";
646
Asutosh Das6b82fc52012-11-23 12:00:26 +0530[diff] [blame]647 reg = <0xf98a4000 0x800>,
648 <0xf98a4800 0x100>,
649 <0xf9884000 0x7000>;
650 reg-names = "core_mem", "dml_mem", "bam_mem";
651 interrupts = <0 125 0>, <0 220 0>;
652 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530[diff] [blame]653
654 qcom,bus-width = <4>;
655 status = "disabled";
656 };
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]657
Sahitya Tummala9e001362013-03-28 11:00:55 +0530[diff] [blame]658 sdhc_2: sdhci@f98a4900 {
659 compatible = "qcom,sdhci-msm";
660 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
661 reg-names = "hc_mem", "core_mem";
662
663 interrupts = <0 125 0>, <0 221 0>;
664 interrupt-names = "hc_irq", "pwr_irq";
665
666 qcom,bus-width = <4>;
667 status = "disabled";
668 };
669
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]670 spmi_bus: qcom,spmi@fc4c0000 {
671 cell-index = <0>;
672 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]673 reg-names = "core", "intr", "cnfg";
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]674 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]675 <0Xfc4cb000 0x1000>,
676 <0Xfc4ca000 0x1000>;
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]677 /* 190,ee0_krait_hlos_spmi_periph_irq */
678 /* 187,channel_0_krait_hlos_trans_done_irq */
679 interrupts = <0 190 0>, <0 187 0>;
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]680 qcom,pmic-arb-ee = <0>;
681 qcom,pmic-arb-channel = <0>;
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]682 };
683
Gilad Avidov28e18eb2012-11-21 18:13:25 -0700[diff] [blame]684 i2c@f9926000 { /* BLSP-1 QUP-4 */
685 cell-index = <0>;
686 compatible = "qcom,i2c-qup";
687 reg = <0xf9926000 0x1000>;
688 #address-cells = <1>;
689 #size-cells = <0>;
690 reg-names = "qup_phys_addr";
691 interrupts = <0 98 0>;
692 interrupt-names = "qup_err_intr";
693 qcom,i2c-bus-freq = <100000>;
694 };
Patrick Daly99a52ca2012-10-23 12:00:45 -0700[diff] [blame]695
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]696 i2c@f9927000 { /* BLSP1 QUP5 */
697 cell-index = <5>;
698 compatible = "qcom,i2c-qup";
699 #address-cells = <1>;
700 #size-cells = <0>;
701 reg-names = "qup_phys_addr";
702 reg = <0xf9927000 0x1000>;
703 interrupt-names = "qup_err_intr";
704 interrupts = <0 99 0>;
Amy Maloche118e5d62013-05-01 14:53:35 -0700[diff] [blame]705 qcom,i2c-bus-freq = <384000>;
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]706 qcom,i2c-src-freq = <19200000>;
707 };
708
Patrick Daly99a52ca2012-10-23 12:00:45 -0700[diff] [blame]709 qcom,acpuclk@f9011050 {
710 compatible = "qcom,acpuclk-a7";
711 reg = <0xf9011050 0x8>;
712 reg-names = "rcg_base";
Patrick Dalyf9451d22013-03-20 14:20:12 -0700[diff] [blame]713 a7_cpu-supply = <&apc_vreg_corner>;
Patrick Daly99a52ca2012-10-23 12:00:45 -0700[diff] [blame]714 };
Mitchel Humpherys00beacf2012-10-11 13:53:43 -0700[diff] [blame]715
716 qcom,ocmem@fdd00000 {
717 compatible = "qcom,msm-ocmem";
718 reg = <0xfdd00000 0x2000>,
719 <0xfdd02000 0x2000>,
720 <0xfe039000 0x400>,
Mitchel Humpherys1da744d2013-03-08 17:20:41 -0800[diff] [blame]721 <0xfec00000 0x20000>;
Mitchel Humpherys00beacf2012-10-11 13:53:43 -0700[diff] [blame]722 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
723 interrupts = <0 76 0 0 77 0>;
724 interrupt-names = "ocmem_irq", "dm_irq";
725 qcom,ocmem-num-regions = <0x1>;
726 qcom,ocmem-num-macros = <0x2>;
727 qcom,resource-type = <0x706d636f>;
728 #address-cells = <1>;
729 #size-cells = <1>;
Mitchel Humpherys1da744d2013-03-08 17:20:41 -0800[diff] [blame]730 ranges = <0x0 0xfec00000 0x20000>;
Mitchel Humpherys00beacf2012-10-11 13:53:43 -0700[diff] [blame]731
732 partition@0 {
Mitchel Humpherys1da744d2013-03-08 17:20:41 -0800[diff] [blame]733 reg = <0x0 0x20000>;
Mitchel Humpherys00beacf2012-10-11 13:53:43 -0700[diff] [blame]734 qcom,ocmem-part-name = "graphics";
Mitchel Humpherys1da744d2013-03-08 17:20:41 -0800[diff] [blame]735 qcom,ocmem-part-min = <0x20000>;
Mitchel Humpherys00beacf2012-10-11 13:53:43 -0700[diff] [blame]736 };
737 };
738
Patrick Dalyb83f0b02013-01-09 12:36:19 -0800[diff] [blame]739 qcom,venus@fdce0000 {
740 compatible = "qcom,pil-venus";
741 reg = <0xfdce0000 0x4000>,
742 <0xfdc80000 0x400>;
743 reg-names = "wrapper_base", "vbif_base";
744 vdd-supply = <&gdsc_venus>;
745
746 qcom,firmware-name = "venus";
747 };
Patrick Daly1e3bc6c2013-01-09 12:34:25 -0800[diff] [blame]748
749 qcom,pronto@fb21b000 {
750 compatible = "qcom,pil-pronto";
751 reg = <0xfb21b000 0x3000>,
752 <0xfc401700 0x4>,
753 <0xfd485300 0xc>;
754 reg-names = "pmu_base", "clk_base", "halt_base";
755 interrupts = <0 149 1>;
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]756 vdd_pronto_pll-supply = <&pm8226_l8>;
Patrick Daly1e3bc6c2013-01-09 12:34:25 -0800[diff] [blame]757
758 qcom,firmware-name = "wcnss";
Sameer Thalappil5c2c41b2013-04-02 11:08:21 -0700[diff] [blame]759
Sameer Thalappil4ba86302013-04-05 17:36:54 -0700[diff] [blame]760 /* GPIO inputs from wcnss */
Sameer Thalappil5c2c41b2013-04-02 11:08:21 -0700[diff] [blame]761 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
Sameer Thalappilb1e03c02013-04-29 14:52:00 -0700[diff] [blame]762 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;
Sameer Thalappil4ba86302013-04-05 17:36:54 -0700[diff] [blame]763 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
Sameer Thalappil5c2c41b2013-04-02 11:08:21 -0700[diff] [blame]764
765 /* GPIO output to wcnss */
766 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
Patrick Daly1e3bc6c2013-01-09 12:34:25 -0800[diff] [blame]767 };
Neeti Desai1f7ca2d2012-11-21 13:25:57 -0800[diff] [blame]768
Sheng Fang0a85b0d2013-03-19 08:16:51 +0800[diff] [blame]769 qcom,iris-fm {
770 compatible = "qcom,iris_fm";
771 };
772
Patrick Daly4df59842013-01-09 12:31:40 -0800[diff] [blame]773 qcom,lpass@fe200000 {
774 compatible = "qcom,pil-q6v5-lpass";
775 reg = <0xfe200000 0x00100>,
Matt Wagantall015b50af2013-03-05 18:51:16 -0800[diff] [blame]776 <0xfd485100 0x00010>,
777 <0xfc4016c0 0x00004>;
778 reg-names = "qdsp6_base", "halt_base", "restart_reg";
David Keitelf4c8b8b2013-02-25 15:25:27 -0800[diff] [blame]779 vdd_cx-supply = <&pm8226_s1_corner>;
Patrick Daly4df59842013-01-09 12:31:40 -0800[diff] [blame]780 interrupts = <0 162 1>;
781
782 qcom,firmware-name = "adsp";
Ravishankar Sarawadi2e8ac7d2013-03-28 15:23:30 -0700[diff] [blame]783
Ravishankar Sarawadiab203a82013-04-09 18:46:11 -0700[diff] [blame]784 /* GPIO inputs from lpass */
Ravishankar Sarawadi2e8ac7d2013-03-28 15:23:30 -0700[diff] [blame]785 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
Ravishankar Sarawadiab203a82013-04-09 18:46:11 -0700[diff] [blame]786 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
Ravishankar Sarawadi2e8ac7d2013-03-28 15:23:30 -0700[diff] [blame]787
788 /* GPIO output to lpass */
789 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
Patrick Daly4df59842013-01-09 12:31:40 -0800[diff] [blame]790 };
791
Patrick Daly742337f2013-01-29 12:06:06 -0800[diff] [blame]792 qcom,mss@fc880000 {
793 compatible = "qcom,pil-q6v5-mss";
794 reg = <0xfc880000 0x100>,
795 <0xfd485000 0x400>,
796 <0xfc820000 0x020>,
797 <0xfc401680 0x004>,
Patrick Daly742337f2013-01-29 12:06:06 -0800[diff] [blame]798 <0xfd485194 0x4>;
799 reg-names = "qdsp6_base", "halt_base", "rmb_base",
Matt Wagantall724b2bb2013-03-18 14:54:06 -0700[diff] [blame]800 "restart_reg", "cxrail_bhs_reg";
Patrick Daly742337f2013-01-29 12:06:06 -0800[diff] [blame]801
802 interrupts = <0 24 1>;
Patrick Daly742337f2013-01-29 12:06:06 -0800[diff] [blame]803 vdd_cx-supply = <&pm8226_s1_corner>;
804 vdd_mx-supply = <&pm8226_l3>;
805 vdd_pll-supply = <&pm8226_l8>;
806 qcom,vdd_pll = <1800000>;
807
808 qcom,is-loadable;
809 qcom,firmware-name = "mba";
810 qcom,pil-self-auth;
Patrick Dalyfe258e22013-03-22 21:02:14 -0700[diff] [blame]811
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800[diff] [blame]812 /* GPIO inputs from mss */
Patrick Dalyfe258e22013-03-22 21:02:14 -0700[diff] [blame]813 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
Seemanta Dutta9fb72ed2013-01-25 14:22:15 -0800[diff] [blame]814 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
Seemanta Duttaa0f253e2013-01-16 18:54:40 -0800[diff] [blame]815 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
Patrick Dalyfe258e22013-03-22 21:02:14 -0700[diff] [blame]816
817 /* GPIO output to mss */
818 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Patrick Daly742337f2013-01-29 12:06:06 -0800[diff] [blame]819 };
820
Neeti Desai1f7ca2d2012-11-21 13:25:57 -0800[diff] [blame]821 qcom,msm-mem-hole {
822 compatible = "qcom,msm-mem-hole";
Neeti Desai3d0a98b2013-04-10 10:41:03 -0700[diff] [blame]823 qcom,memblock-remove = <0x6400000 0x9b00000>; /* Address and Size of Hole */
Neeti Desai1f7ca2d2012-11-21 13:25:57 -0800[diff] [blame]824 };
Siddartha Mohanadossfcd98562013-02-13 08:53:22 -0800[diff] [blame]825
826 tsens: tsens@fc4a8000 {
827 compatible = "qcom,msm-tsens";
828 reg = <0xfc4a8000 0x2000>,
829 <0xfc4b8000 0x1000>;
830 reg-names = "tsens_physical", "tsens_eeprom_physical";
831 interrupts = <0 184 0>;
Siddartha Mohanadoss9a4e94a2013-03-06 19:15:59 -0800[diff] [blame]832 qcom,sensors = <4>;
833 qcom,slope = <2901 2846 3038 2955>;
Siddartha Mohanadossfcd98562013-02-13 08:53:22 -0800[diff] [blame]834 qcom,calib-mode = "fuse_map2";
835 };
Praveen Chidambarama03bda52013-02-12 21:23:13 -0700[diff] [blame]836
837 qcom,msm-thermal {
838 compatible = "qcom,msm-thermal";
839 qcom,sensor-id = <0>;
840 qcom,poll-ms = <250>;
841 qcom,limit-temp = <60>;
842 qcom,temp-hysteresis = <10>;
843 qcom,freq-step = <2>;
844 };
845
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]846 spi_0: spi@f9923000 { /* BLSP1 QUP1 */
847 compatible = "qcom,spi-qup-v2";
848 #address-cells = <1>;
849 #size-cells = <0>;
850 reg-names = "spi_physical", "spi_bam_physical";
851 reg = <0xf9923000 0x1000>,
852 <0xf9904000 0xF000>;
853 interrupt-names = "spi_irq", "spi_bam_irq";
854 interrupts = <0 95 0>, <0 238 0>;
855 spi-max-frequency = <19200000>;
856
857 gpios = <&msmgpio 3 0>, /* CLK */
858 <&msmgpio 1 0>, /* MISO */
859 <&msmgpio 0 0>; /* MOSI */
aiqunyb1e82f32013-03-13 15:35:53 -0700[diff] [blame]860 cs-gpios = <&msmgpio 22 0>;
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]861
862 qcom,infinite-mode = <0>;
863 qcom,use-bam;
864 qcom,ver-reg-exists;
865 qcom,bam-consumer-pipe-index = <12>;
866 qcom,bam-producer-pipe-index = <13>;
867 };
868
Jeff Hugo72e10912013-03-05 11:17:38 -0700[diff] [blame]869 qcom,bam_dmux@fc834000 {
870 compatible = "qcom,bam_dmux";
871 reg = <0xfc834000 0x7000>;
872 interrupts = <0 29 1>;
873 };
Pushkar Joshi4f3aa0b2013-03-07 22:44:04 -0800[diff] [blame]874
875 qcom,msm-rtb {
876 compatible = "qcom,msm-rtb";
877 qcom,memory-reservation-type = "EBI1";
878 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
879 };
Hariprasad Dhalinarasimhaadf89cc2013-03-13 13:41:05 -0700[diff] [blame]880
Hariprasad Dhalinarasimhab548ee52013-03-11 19:06:30 -0700[diff] [blame]881 qcom,msm-rng@f9bff000 {
882 compatible = "qcom,msm-rng";
883 reg = <0xf9bff000 0x200>;
884 qcom,msm-rng-iface-clk;
885 };
Hariprasad Dhalinarasimhaadf89cc2013-03-13 13:41:05 -0700[diff] [blame]886
Hariprasad Dhalinarasimha4ba4d802013-03-21 13:03:09 -0700[diff] [blame]887 qcom,tz-log@fe805720 {
Hariprasad Dhalinarasimhaadf89cc2013-03-13 13:41:05 -0700[diff] [blame]888 compatible = "qcom,tz-log";
Hariprasad Dhalinarasimha4ba4d802013-03-21 13:03:09 -0700[diff] [blame]889 reg = <0x0fe805720 0x1000>;
Hariprasad Dhalinarasimhaadf89cc2013-03-13 13:41:05 -0700[diff] [blame]890 };
Pushkar Joshi85a53192013-03-11 11:15:15 -0700[diff] [blame]891
892 jtag_mm0: jtagmm@fc33c000 {
893 compatible = "qcom,jtag-mm";
894 reg = <0xfc33c000 0x1000>,
895 <0xfc330000 0x1000>;
896 reg-names = "etm-base","debug-base";
897 };
898
899 jtag_mm1: jtagmm@fc33d000 {
900 compatible = "qcom,jtag-mm";
901 reg = <0xfc33d000 0x1000>,
902 <0xfc332000 0x1000>;
903 reg-names = "etm-base","debug-base";
904 };
905
906 jtag_mm2: jtagmm@fc33e000 {
907 compatible = "qcom,jtag-mm";
908 reg = <0xfc33e000 0x1000>,
909 <0xfc334000 0x1000>;
910 reg-names = "etm-base","debug-base";
911 };
912
913 jtag_mm3: jtagmm@fc33f000 {
914 compatible = "qcom,jtag-mm";
915 reg = <0xfc33f000 0x1000>,
916 <0xfc336000 0x1000>;
917 reg-names = "etm-base","debug-base";
918 };
Jeff Hugo2be6bb022013-03-11 10:17:34 -0600[diff] [blame]919
920 qcom,ipc-spinlock@fd484000 {
921 compatible = "qcom,ipc-spinlock-sfpb";
922 reg = <0xfd484000 0x400>;
923 qcom,num-locks = <8>;
924 };
Hariprasad Dhalinarasimha805ea4d2013-03-14 11:16:12 -0700[diff] [blame]925
926 qcom,qseecom@d980000 {
927 compatible = "qcom,qseecom";
928 reg = <0xd980000 0x256000>;
929 reg-names = "secapp-region";
930 qcom,disk-encrypt-pipe-pair = <2>;
931 qcom,hlos-ce-hw-instance = <0>;
932 qcom,qsee-ce-hw-instance = <0>;
933 qcom,msm-bus,name = "qseecom-noc";
934 qcom,msm-bus,num-cases = <4>;
935 qcom,msm-bus,active-only = <0>;
936 qcom,msm-bus,num-paths = <1>;
937 qcom,msm-bus,vectors-KBps =
938 <55 512 0 0>,
939 <55 512 3936000 393600>,
940 <55 512 3936000 393600>,
941 <55 512 3936000 393600>;
942 };
Hariprasad Dhalinarasimha75051f22013-03-19 15:08:50 -0700[diff] [blame]943
944 qcom,qcrypto@fd404000 {
945 compatible = "qcom,qcrypto";
946 reg = <0xfd400000 0x20000>,
947 <0xfd404000 0x8000>;
948 reg-names = "crypto-base","crypto-bam-base";
949 interrupts = <0 207 0>;
950 qcom,bam-pipe-pair = <2>;
951 qcom,ce-hw-instance = <0>;
952 qcom,ce-hw-shared;
953 qcom,msm-bus,name = "qcrypto-noc";
954 qcom,msm-bus,num-cases = <2>;
955 qcom,msm-bus,active-only = <0>;
956 qcom,msm-bus,num-paths = <1>;
957 qcom,msm-bus,vectors-KBps =
958 <56 512 0 0>,
959 <56 512 3936000 393600>;
960 };
961
962 qcom,qcedev@fd400000 {
963 compatible = "qcom,qcedev";
964 reg = <0xfd400000 0x20000>,
965 <0xfd404000 0x8000>;
966 reg-names = "crypto-base","crypto-bam-base";
967 interrupts = <0 207 0>;
968 qcom,bam-pipe-pair = <1>;
969 qcom,ce-hw-instance = <0>;
970 qcom,ce-hw-shared;
971 qcom,msm-bus,name = "qcedev-noc";
972 qcom,msm-bus,num-cases = <2>;
973 qcom,msm-bus,active-only = <0>;
974 qcom,msm-bus,num-paths = <1>;
975 qcom,msm-bus,vectors-KBps =
976 <56 512 0 0>,
977 <56 512 3936000 393600>;
978 };
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]979};
David Collins37ddb972012-10-17 15:00:26 -0700[diff] [blame]980
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]981&gdsc_venus {
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]982 qcom,clock-names = "core_clk";
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]983 status = "ok";
984};
985
986&gdsc_mdss {
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]987 qcom,clock-names = "core_clk", "lut_clk";
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]988 status = "ok";
989};
990
991&gdsc_jpeg {
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]992 qcom,clock-names = "core_clk";
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]993 status = "ok";
994};
995
996&gdsc_vfe {
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]997 qcom,clock-names = "core_clk", "csi_clk", "cpp_clk";
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]998 status = "ok";
999};
1000
1001&gdsc_oxili_cx {
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]1002 qcom,clock-names = "core_clk";
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]1003 status = "ok";
1004};
1005
1006&gdsc_usb_hsic {
1007 status = "ok";
1008};
1009
David Keitel376b2682013-03-05 18:40:01 -0800[diff] [blame]1010/include/ "msm-pm8226-rpm-regulator.dtsi"
Kenneth Heitkebea6ca22013-02-07 17:23:21 -0700[diff] [blame]1011/include/ "msm-pm8226.dtsi"
David Keitel7184c6e2013-02-11 13:23:04 -0800[diff] [blame]1012/include/ "msm8226-regulator.dtsi"
Siddartha Mohanadossae99e772013-02-19 15:44:40 -0800[diff] [blame]1013
1014&pm8226_vadc {
1015 chan@0 {
1016 label = "usb_in";
1017 reg = <0>;
1018 qcom,decimation = <0>;
1019 qcom,pre-div-channel-scaling = <4>;
1020 qcom,calibration-type = "absolute";
1021 qcom,scale-function = <0>;
1022 qcom,hw-settle-time = <0>;
1023 qcom,fast-avg-setup = <0>;
1024 };
1025
1026 chan@2 {
1027 label = "vchg_sns";
1028 reg = <2>;
1029 qcom,decimation = <0>;
1030 qcom,pre-div-channel-scaling = <3>;
1031 qcom,calibration-type = "absolute";
1032 qcom,scale-function = <0>;
1033 qcom,hw-settle-time = <0>;
1034 qcom,fast-avg-setup = <0>;
1035 };
1036
1037 chan@5 {
1038 label = "vcoin";
1039 reg = <5>;
1040 qcom,decimation = <0>;
1041 qcom,pre-div-channel-scaling = <1>;
1042 qcom,calibration-type = "absolute";
1043 qcom,scale-function = <0>;
1044 qcom,hw-settle-time = <0>;
1045 qcom,fast-avg-setup = <0>;
1046 };
1047
1048 chan@6 {
1049 label = "vbat_sns";
1050 reg = <6>;
1051 qcom,decimation = <0>;
1052 qcom,pre-div-channel-scaling = <1>;
1053 qcom,calibration-type = "absolute";
1054 qcom,scale-function = <0>;
1055 qcom,hw-settle-time = <0>;
1056 qcom,fast-avg-setup = <0>;
1057 };
1058
1059 chan@7 {
1060 label = "vph_pwr";
1061 reg = <7>;
1062 qcom,decimation = <0>;
1063 qcom,pre-div-channel-scaling = <1>;
1064 qcom,calibration-type = "absolute";
1065 qcom,scale-function = <0>;
1066 qcom,hw-settle-time = <0>;
1067 qcom,fast-avg-setup = <0>;
1068 };
1069
1070 chan@30 {
1071 label = "batt_therm";
1072 reg = <0x30>;
1073 qcom,decimation = <0>;
1074 qcom,pre-div-channel-scaling = <0>;
1075 qcom,calibration-type = "ratiometric";
1076 qcom,scale-function = <1>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800[diff] [blame]1077 qcom,hw-settle-time = <2>;
Siddartha Mohanadossae99e772013-02-19 15:44:40 -0800[diff] [blame]1078 qcom,fast-avg-setup = <0>;
1079 };
1080
1081 chan@31 {
1082 label = "batt_id";
1083 reg = <0x31>;
1084 qcom,decimation = <0>;
1085 qcom,pre-div-channel-scaling = <0>;
1086 qcom,calibration-type = "ratiometric";
1087 qcom,scale-function = <0>;
1088 qcom,hw-settle-time = <2>;
1089 qcom,fast-avg-setup = <0>;
1090 };
1091
1092 chan@b2 {
1093 label = "xo_therm_pu2";
1094 reg = <0xb2>;
1095 qcom,decimation = <0>;
1096 qcom,pre-div-channel-scaling = <0>;
1097 qcom,calibration-type = "ratiometric";
1098 qcom,scale-function = <4>;
Siddartha Mohanadoss74cece62013-02-22 10:07:30 -0800[diff] [blame]1099 qcom,hw-settle-time = <2>;
Siddartha Mohanadossae99e772013-02-19 15:44:40 -0800[diff] [blame]1100 qcom,fast-avg-setup = <0>;
1101 };
David Keitelc51a7e52013-03-02 00:14:48 -0800[diff] [blame]1102
Siddartha Mohanadoss3cb76152013-04-12 16:17:02 -0700[diff] [blame]1103 chan@39 {
1104 label = "usb_id_nopull";
1105 reg = <0x39>;
1106 qcom,decimation = <0>;
1107 qcom,pre-div-channel-scaling = <0>;
1108 qcom,calibration-type = "ratiometric";
1109 qcom,scale-function = <0>;
1110 qcom,hw-settle-time = <2>;
1111 qcom,fast-avg-setup = <0>;
1112 };
David Keitelc51a7e52013-03-02 00:14:48 -0800[diff] [blame]1113};
1114
Siddartha Mohanadoss8aea3172013-05-09 11:49:37 -0700[diff] [blame^]1115&pm8226_adc_tm {
1116 /* Channel Node */
1117 chan@30 {
1118 label = "batt_therm";
1119 reg = <0x30>;
1120 qcom,decimation = <0>;
1121 qcom,pre-div-channel-scaling = <0>;
1122 qcom,calibration-type = "ratiometric";
1123 qcom,scale-function = <1>;
1124 qcom,hw-settle-time = <2>;
1125 qcom,fast-avg-setup = <3>;
1126 qcom,btm-channel-number = <0x48>;
1127 };
1128
1129 chan@8 {
1130 label = "die_temp";
1131 reg = <8>;
1132 qcom,decimation = <0>;
1133 qcom,pre-div-channel-scaling = <0>;
1134 qcom,calibration-type = "absolute";
1135 qcom,scale-function = <3>;
1136 qcom,hw-settle-time = <0>;
1137 qcom,fast-avg-setup = <3>;
1138 qcom,btm-channel-number = <0x68>;
1139 };
1140
1141 chan@6 {
1142 label = "vbat_sns";
1143 reg = <6>;
1144 qcom,decimation = <0>;
1145 qcom,pre-div-channel-scaling = <1>;
1146 qcom,calibration-type = "absolute";
1147 qcom,scale-function = <0>;
1148 qcom,hw-settle-time = <0>;
1149 qcom,fast-avg-setup = <3>;
1150 qcom,btm-channel-number = <0x70>;
1151 };
1152
1153 chan@14 {
1154 label = "pa_therm0";
1155 reg = <0x14>;
1156 qcom,decimation = <0>;
1157 qcom,pre-div-channel-scaling = <0>;
1158 qcom,calibration-type = "ratiometric";
1159 qcom,scale-function = <2>;
1160 qcom,hw-settle-time = <2>;
1161 qcom,fast-avg-setup = <0>;
1162 qcom,btm-channel-number = <0x78>;
1163 qcom,thermal-node;
1164 };
1165
1166 chan@17 {
1167 label = "pa_therm1";
1168 reg = <0x17>;
1169 qcom,decimation = <0>;
1170 qcom,pre-div-channel-scaling = <0>;
1171 qcom,calibration-type = "ratiometric";
1172 qcom,scale-function = <2>;
1173 qcom,hw-settle-time = <2>;
1174 qcom,fast-avg-setup = <0>;
1175 qcom,btm-channel-number = <0x80>;
1176 qcom,thermal-node;
1177 };
1178};
1179
David Keitelc51a7e52013-03-02 00:14:48 -0800[diff] [blame]1180&pm8226_chg {
1181 status = "ok";
1182
David Keitele89d4782013-03-27 11:29:59 -0700[diff] [blame]1183 qcom,chgr@1000 {
David Keitelc51a7e52013-03-02 00:14:48 -0800[diff] [blame]1184 status = "ok";
1185 };
1186
David Keitele89d4782013-03-27 11:29:59 -0700[diff] [blame]1187 qcom,buck@1100 {
David Keitelc51a7e52013-03-02 00:14:48 -0800[diff] [blame]1188 status = "ok";
1189 };
1190
David Keitele89d4782013-03-27 11:29:59 -0700[diff] [blame]1191 qcom,bat-if@1200 {
Fenglin Wu009098a2013-03-08 15:50:51 -0800[diff] [blame]1192 status = "ok";
1193 };
1194
David Keitele89d4782013-03-27 11:29:59 -0700[diff] [blame]1195 qcom,usb-chgpth@1300 {
David Keitelc51a7e52013-03-02 00:14:48 -0800[diff] [blame]1196 status = "ok";
1197 };
1198
David Keitele89d4782013-03-27 11:29:59 -0700[diff] [blame]1199 qcom,boost@1500 {
David Keitelc51a7e52013-03-02 00:14:48 -0800[diff] [blame]1200 status = "ok";
1201 };
1202
1203 qcom,chg-misc@1600 {
1204 status = "ok";
1205 };
Siddartha Mohanadossae99e772013-02-19 15:44:40 -0800[diff] [blame]1206};