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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
38STATISTIC(NumStores, "Number of stores added");
39STATISTIC(NumLoads , "Number of loads added");
40STATISTIC(NumReused, "Number of values reused");
41STATISTIC(NumDSE , "Number of dead stores elided");
42STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000043
Chris Lattnercd3245a2006-12-19 22:41:21 +000044namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000045 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000046
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000047 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000048 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000049 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 cl::Prefix,
51 cl::values(clEnumVal(simple, " simple spiller"),
52 clEnumVal(local, " local spiller"),
53 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000054 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000055}
56
Chris Lattner8c4d88d2004-09-30 01:54:45 +000057//===----------------------------------------------------------------------===//
58// VirtRegMap implementation
59//===----------------------------------------------------------------------===//
60
Chris Lattner29268692006-09-05 02:12:02 +000061VirtRegMap::VirtRegMap(MachineFunction &mf)
62 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
63 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
64 grow();
65}
66
Chris Lattner8c4d88d2004-09-30 01:54:45 +000067void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000068 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
69 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000070}
71
Chris Lattner8c4d88d2004-09-30 01:54:45 +000072int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
73 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000074 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000075 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000076 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
77 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
78 RC->getAlignment());
79 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000080 ++NumSpills;
81 return frameIndex;
82}
83
84void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
85 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000086 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000087 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000088 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000089}
90
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000091void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000092 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000093 // Move previous memory references folded to new instruction.
94 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000095 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000096 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
97 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000098 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000099 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000100
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000101 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000102 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
103 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000104 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000105 // Folded a two-address operand.
106 MRInfo = isModRef;
107 } else if (OldMI->getOperand(OpNo).isDef()) {
108 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000109 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000110 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000111 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000112
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000113 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000114 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000115}
116
Chris Lattner7f690e62004-09-30 02:15:18 +0000117void VirtRegMap::print(std::ostream &OS) const {
118 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000119
Chris Lattner7f690e62004-09-30 02:15:18 +0000120 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000121 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000122 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
123 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
124 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000125
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000126 }
127
128 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000129 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
130 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
131 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
132 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000133}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000134
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000135void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000136 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000137}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000138
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000139
140//===----------------------------------------------------------------------===//
141// Simple Spiller Implementation
142//===----------------------------------------------------------------------===//
143
144Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000145
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000146namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000147 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000148 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000149 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000150}
151
Chris Lattner35f27052006-05-01 21:16:03 +0000152bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000153 DOUT << "********** REWRITE MACHINE CODE **********\n";
154 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000155 const TargetMachine &TM = MF.getTarget();
156 const MRegisterInfo &MRI = *TM.getRegisterInfo();
157 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000158
Chris Lattner4ea1b822004-09-30 02:33:48 +0000159 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
160 // each vreg once (in the case where a spilled vreg is used by multiple
161 // operands). This is always smaller than the number of operands to the
162 // current machine instr, so it should be small.
163 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000164
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000165 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
166 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000167 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000168 MachineBasicBlock &MBB = *MBBI;
169 for (MachineBasicBlock::iterator MII = MBB.begin(),
170 E = MBB.end(); MII != E; ++MII) {
171 MachineInstr &MI = *MII;
172 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000173 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000174 if (MO.isRegister() && MO.getReg())
175 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
176 unsigned VirtReg = MO.getReg();
177 unsigned PhysReg = VRM.getPhys(VirtReg);
178 if (VRM.hasStackSlot(VirtReg)) {
179 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000180 const TargetRegisterClass* RC =
181 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000182
Chris Lattner886dd912005-04-04 21:35:34 +0000183 if (MO.isUse() &&
184 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
185 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000186 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000187 LoadedRegs.push_back(VirtReg);
188 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000189 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000190 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000191
Chris Lattner886dd912005-04-04 21:35:34 +0000192 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000193 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000194 ++NumStores;
195 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000196 }
Chris Lattner886dd912005-04-04 21:35:34 +0000197 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000198 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000199 } else {
200 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000201 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000202 }
Chris Lattner886dd912005-04-04 21:35:34 +0000203
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000204 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000205 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000206 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000207 }
208 return true;
209}
210
211//===----------------------------------------------------------------------===//
212// Local Spiller Implementation
213//===----------------------------------------------------------------------===//
214
215namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000216 /// LocalSpiller - This spiller does a simple pass over the machine basic
217 /// block to attempt to keep spills in registers as much as possible for
218 /// blocks that have low register pressure (the vreg may be spilled due to
219 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000220 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000222 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000223 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000224 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000225 MRI = MF.getTarget().getRegisterInfo();
226 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000227 DOUT << "\n**** Local spiller rewriting function '"
228 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000229
Chris Lattner7fb64342004-10-01 19:04:51 +0000230 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
231 MBB != E; ++MBB)
232 RewriteMBB(*MBB, VRM);
233 return true;
234 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000235 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000236 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000237 };
238}
239
Chris Lattner66cf80f2006-02-03 23:13:58 +0000240/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
241/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000242///
243/// Note that not all physregs are created equal here. In particular, some
244/// physregs are reloads that we are allowed to clobber or ignore at any time.
245/// Other physregs are values that the register allocated program is using that
246/// we cannot CHANGE, but we can read if we like. We keep track of this on a
247/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
248/// entries. The predicate 'canClobberPhysReg()' checks this bit and
249/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000250namespace {
251class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000252 const MRegisterInfo *MRI;
253 const TargetInstrInfo *TII;
254
255 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
256 // register values that are still available, due to being loaded or stored to,
257 // but not invalidated yet.
Evan Cheng91e23902007-02-23 01:13:26 +0000258 typedef std::pair<unsigned, MachineInstr*> SSInfo;
259 std::map<int, SSInfo> SpillSlotsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000260
261 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
262 // which stack slot values are currently held by a physreg. This is used to
263 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
264 std::multimap<unsigned, int> PhysRegsAvailable;
265
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000266 void disallowClobberPhysRegOnly(unsigned PhysReg);
267
Chris Lattner66cf80f2006-02-03 23:13:58 +0000268 void ClobberPhysRegOnly(unsigned PhysReg);
269public:
270 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
271 : MRI(mri), TII(tii) {
272 }
273
Evan Cheng91e23902007-02-23 01:13:26 +0000274 const MRegisterInfo *getRegInfo() const { return MRI; }
275
Chris Lattner66cf80f2006-02-03 23:13:58 +0000276 /// getSpillSlotPhysReg - If the specified stack slot is available in a
Evan Cheng91e23902007-02-23 01:13:26 +0000277 /// physical register, return that PhysReg, otherwise return 0. It also
278 /// returns by reference the instruction that either defines or last uses
279 /// the register.
280 unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const {
281 std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot);
282 if (I != SpillSlotsAvailable.end()) {
283 SSMI = I->second.second;
284 return I->second.first >> 1; // Remove the CanClobber bit.
285 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000286 return 0;
287 }
Chris Lattner540fec62006-02-25 01:51:33 +0000288
Chris Lattner66cf80f2006-02-03 23:13:58 +0000289 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000290 /// specified physreg. If CanClobber is true, the physreg can be modified at
291 /// any time without changing the semantics of the program.
Evan Cheng91e23902007-02-23 01:13:26 +0000292 void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
293 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000294 // If this stack slot is thought to be available in some other physreg,
295 // remove its record.
296 ModifyStackSlot(Slot);
297
Chris Lattner66cf80f2006-02-03 23:13:58 +0000298 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Evan Cheng91e23902007-02-23 01:13:26 +0000299 SpillSlotsAvailable[Slot] =
300 std::make_pair((Reg << 1) | (unsigned)CanClobber, MI);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000301
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000302 DOUT << "Remembering SS#" << Slot << " in physreg "
303 << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000304 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000305
Chris Lattner593c9582006-02-03 23:28:46 +0000306 /// canClobberPhysReg - Return true if the spiller is allowed to change the
307 /// value of the specified stackslot register if it desires. The specified
308 /// stack slot must be available in a physreg for this query to make sense.
309 bool canClobberPhysReg(int Slot) const {
310 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
Evan Cheng91e23902007-02-23 01:13:26 +0000311 return SpillSlotsAvailable.find(Slot)->second.first & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000312 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000313
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000314 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
315 /// stackslot register. The register is still available but is no longer
316 /// allowed to be modifed.
317 void disallowClobberPhysReg(unsigned PhysReg);
318
Chris Lattner66cf80f2006-02-03 23:13:58 +0000319 /// ClobberPhysReg - This is called when the specified physreg changes
320 /// value. We use this to invalidate any info about stuff we thing lives in
321 /// it and any of its aliases.
322 void ClobberPhysReg(unsigned PhysReg);
323
324 /// ModifyStackSlot - This method is called when the value in a stack slot
325 /// changes. This removes information about which register the previous value
326 /// for this slot lives in (as the previous value is dead now).
327 void ModifyStackSlot(int Slot);
328};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000329}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000330
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000331/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
332/// stackslot register. The register is still available but is no longer
333/// allowed to be modifed.
334void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
335 std::multimap<unsigned, int>::iterator I =
336 PhysRegsAvailable.lower_bound(PhysReg);
337 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
338 int Slot = I->second;
339 I++;
Evan Cheng91e23902007-02-23 01:13:26 +0000340 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000341 "Bidirectional map mismatch!");
Evan Cheng91e23902007-02-23 01:13:26 +0000342 SpillSlotsAvailable[Slot].first &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000343 DOUT << "PhysReg " << MRI->getName(PhysReg)
344 << " copied, it is available for use but can no longer be modified\n";
345 }
346}
347
348/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
349/// stackslot register and its aliases. The register and its aliases may
350/// still available but is no longer allowed to be modifed.
351void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
352 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
353 disallowClobberPhysRegOnly(*AS);
354 disallowClobberPhysRegOnly(PhysReg);
355}
356
Chris Lattner66cf80f2006-02-03 23:13:58 +0000357/// ClobberPhysRegOnly - This is called when the specified physreg changes
358/// value. We use this to invalidate any info about stuff we thing lives in it.
359void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
360 std::multimap<unsigned, int>::iterator I =
361 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000362 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000363 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000364 PhysRegsAvailable.erase(I++);
Evan Cheng91e23902007-02-23 01:13:26 +0000365 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000366 "Bidirectional map mismatch!");
367 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000368 DOUT << "PhysReg " << MRI->getName(PhysReg)
369 << " clobbered, invalidating SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000370 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000371}
372
Chris Lattner66cf80f2006-02-03 23:13:58 +0000373/// ClobberPhysReg - This is called when the specified physreg changes
374/// value. We use this to invalidate any info about stuff we thing lives in
375/// it and any of its aliases.
376void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000377 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000378 ClobberPhysRegOnly(*AS);
379 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000380}
381
Chris Lattner07cf1412006-02-03 00:36:31 +0000382/// ModifyStackSlot - This method is called when the value in a stack slot
383/// changes. This removes information about which register the previous value
384/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000385void AvailableSpills::ModifyStackSlot(int Slot) {
Evan Cheng91e23902007-02-23 01:13:26 +0000386 std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000387 if (It == SpillSlotsAvailable.end()) return;
Evan Cheng91e23902007-02-23 01:13:26 +0000388 unsigned Reg = It->second.first >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000389 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000390
391 // This register may hold the value of multiple stack slots, only remove this
392 // stack slot from the set of values the register contains.
393 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
394 for (; ; ++I) {
395 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
396 "Map inverse broken!");
397 if (I->second == Slot) break;
398 }
399 PhysRegsAvailable.erase(I);
400}
401
402
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000403
Chris Lattner7fb64342004-10-01 19:04:51 +0000404// ReusedOp - For each reused operand, we keep track of a bit of information, in
405// case we need to rollback upon processing a new operand. See comments below.
406namespace {
407 struct ReusedOp {
408 // The MachineInstr operand that reused an available value.
409 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000410
Chris Lattner7fb64342004-10-01 19:04:51 +0000411 // StackSlot - The spill slot of the value being reused.
412 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000413
Chris Lattner7fb64342004-10-01 19:04:51 +0000414 // PhysRegReused - The physical register the value was available in.
415 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000416
Chris Lattner7fb64342004-10-01 19:04:51 +0000417 // AssignedPhysReg - The physreg that was assigned for use by the reload.
418 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000419
420 // VirtReg - The virtual register itself.
421 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000422
Chris Lattner8a61a752005-10-06 17:19:06 +0000423 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
424 unsigned vreg)
425 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
426 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000427 };
Chris Lattner540fec62006-02-25 01:51:33 +0000428
429 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
430 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000431 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000432 MachineInstr &MI;
433 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000434 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000435 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000436 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000437 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000438 }
Chris Lattner540fec62006-02-25 01:51:33 +0000439
440 bool hasReuses() const {
441 return !Reuses.empty();
442 }
443
444 /// addReuse - If we choose to reuse a virtual register that is already
445 /// available instead of reloading it, remember that we did so.
446 void addReuse(unsigned OpNo, unsigned StackSlot,
447 unsigned PhysRegReused, unsigned AssignedPhysReg,
448 unsigned VirtReg) {
449 // If the reload is to the assigned register anyway, no undo will be
450 // required.
451 if (PhysRegReused == AssignedPhysReg) return;
452
453 // Otherwise, remember this.
454 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
455 AssignedPhysReg, VirtReg));
456 }
Evan Chenge077ef62006-11-04 00:21:55 +0000457
458 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000459 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000460 }
461
462 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000463 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000464 }
Chris Lattner540fec62006-02-25 01:51:33 +0000465
466 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
467 /// is some other operand that is using the specified register, either pick
468 /// a new register to use, or evict the previous reload and use this reg.
469 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
470 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000471 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000472 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000473 if (Reuses.empty()) return PhysReg; // This is most often empty.
474
475 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
476 ReusedOp &Op = Reuses[ro];
477 // If we find some other reuse that was supposed to use this register
478 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000479 // register. That is, unless its reload register has already been
480 // considered and subsequently rejected because it has also been reused
481 // by another operand.
482 if (Op.PhysRegReused == PhysReg &&
483 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000484 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000485 unsigned NewReg = Op.AssignedPhysReg;
486 Rejected.insert(PhysReg);
487 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000488 } else {
489 // Otherwise, we might also have a problem if a previously reused
490 // value aliases the new register. If so, codegen the previous reload
491 // and use this one.
492 unsigned PRRU = Op.PhysRegReused;
493 const MRegisterInfo *MRI = Spills.getRegInfo();
494 if (MRI->areAliases(PRRU, PhysReg)) {
495 // Okay, we found out that an alias of a reused register
496 // was used. This isn't good because it means we have
497 // to undo a previous reuse.
498 MachineBasicBlock *MBB = MI->getParent();
499 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000500 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
501
502 // Copy Op out of the vector and remove it, we're going to insert an
503 // explicit load for it.
504 ReusedOp NewOp = Op;
505 Reuses.erase(Reuses.begin()+ro);
506
507 // Ok, we're going to try to reload the assigned physreg into the
508 // slot that we were supposed to in the first place. However, that
509 // register could hold a reuse. Check to see if it conflicts or
510 // would prefer us to use a different register.
511 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000512 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000513
514 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
515 NewOp.StackSlot, AliasRC);
516 Spills.ClobberPhysReg(NewPhysReg);
517 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000518
519 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000520 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000521
Chris Lattnere53f4a02006-05-04 17:52:23 +0000522 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000523
Evan Cheng91e23902007-02-23 01:13:26 +0000524 Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000525 ++NumLoads;
526 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000527 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000528
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000529 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000530 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000531
532 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000533 return PhysReg;
534 }
535 }
536 }
537 return PhysReg;
538 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000539
540 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
541 /// 'Rejected' set to remember which registers have been considered and
542 /// rejected for the reload. This avoids infinite looping in case like
543 /// this:
544 /// t1 := op t2, t3
545 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
546 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
547 /// t1 <- desires r1
548 /// sees r1 is taken by t2, tries t2's reload register r0
549 /// sees r0 is taken by t3, tries t3's reload register r1
550 /// sees r1 is taken by t2, tries t2's reload register r0 ...
551 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
552 AvailableSpills &Spills,
553 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000554 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000555 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
556 }
Chris Lattner540fec62006-02-25 01:51:33 +0000557 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000558}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000559
Chris Lattner7fb64342004-10-01 19:04:51 +0000560
561/// rewriteMBB - Keep track of which spills are available even after the
562/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000563void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000564
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000565 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000566
Chris Lattner66cf80f2006-02-03 23:13:58 +0000567 // Spills - Keep track of which spilled values are available in physregs so
568 // that we can choose to reuse the physregs instead of emitting reloads.
569 AvailableSpills Spills(MRI, TII);
570
Chris Lattner52b25db2004-10-01 19:47:12 +0000571 // MaybeDeadStores - When we need to write a value back into a stack slot,
572 // keep track of the inserted store. If the stack slot value is never read
573 // (because the value was used from some available register, for example), and
574 // subsequently stored to, the original store is dead. This map keeps track
575 // of inserted stores that are not used. If we see a subsequent store to the
576 // same stack slot, the original store is deleted.
577 std::map<int, MachineInstr*> MaybeDeadStores;
578
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000579 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
580
Chris Lattner7fb64342004-10-01 19:04:51 +0000581 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
582 MII != E; ) {
583 MachineInstr &MI = *MII;
584 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
585
Chris Lattner540fec62006-02-25 01:51:33 +0000586 /// ReusedOperands - Keep track of operand reuse in case we need to undo
587 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000588 ReuseInfo ReusedOperands(MI, MRI);
589
590 // Loop over all of the implicit defs, clearing them from our available
591 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000592 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
593 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000594 if (ImpDef) {
595 for ( ; *ImpDef; ++ImpDef) {
596 PhysRegsUsed[*ImpDef] = true;
597 ReusedOperands.markClobbered(*ImpDef);
598 Spills.ClobberPhysReg(*ImpDef);
599 }
600 }
601
Chris Lattner7fb64342004-10-01 19:04:51 +0000602 // Process all of the spilled uses and all non spilled reg references.
603 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
604 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000605 if (!MO.isRegister() || MO.getReg() == 0)
606 continue; // Ignore non-register operands.
607
608 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
609 // Ignore physregs for spilling, but remember that it is used by this
610 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000611 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000612 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000613 continue;
614 }
615
616 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
617 "Not a virtual or a physical register?");
618
619 unsigned VirtReg = MO.getReg();
620 if (!VRM.hasStackSlot(VirtReg)) {
621 // This virtual register was assigned a physreg!
622 unsigned Phys = VRM.getPhys(VirtReg);
623 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000624 if (MO.isDef())
625 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000626 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000627 continue;
628 }
629
630 // This virtual register is now known to be a spilled value.
631 if (!MO.isUse())
632 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000633
Chris Lattner50ea01e2005-09-09 20:29:51 +0000634 int StackSlot = VRM.getStackSlot(VirtReg);
635 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000636
Chris Lattner50ea01e2005-09-09 20:29:51 +0000637 // Check to see if this stack slot is available.
Evan Cheng91e23902007-02-23 01:13:26 +0000638 MachineInstr *SSMI = NULL;
639 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) {
Chris Lattner29268692006-09-05 02:12:02 +0000640 // This spilled operand might be part of a two-address operand. If this
641 // is the case, then changing it will necessarily require changing the
642 // def part of the instruction as well. However, in some cases, we
643 // aren't allowed to modify the reused register. If none of these cases
644 // apply, reuse it.
645 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000646 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000647 if (ti != -1 &&
648 MI.getOperand(ti).isReg() &&
649 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000650 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000651 // long as we are allowed to clobber the value and there isn't an
652 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000653 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
654 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000655 }
656
657 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000658 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000659 DOUT << "Reusing SS#" << StackSlot << " from physreg "
660 << MRI->getName(PhysReg) << " for vreg"
661 << VirtReg <<" instead of reloading into physreg "
662 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000663 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000664
Evan Cheng91e23902007-02-23 01:13:26 +0000665 // Extend the live range of the MI that last kill the register if
666 // necessary.
667 MachineOperand *MOK = SSMI->findRegisterUseOperand(PhysReg, true);
668 if (MOK)
669 MOK->unsetIsKill();
670
Chris Lattneraddc55a2006-04-28 01:46:50 +0000671 // The only technical detail we have is that we don't know that
672 // PhysReg won't be clobbered by a reloaded stack slot that occurs
673 // later in the instruction. In particular, consider 'op V1, V2'.
674 // If V1 is available in physreg R0, we would choose to reuse it
675 // here, instead of reloading it into the register the allocator
676 // indicated (say R1). However, V2 might have to be reloaded
677 // later, and it might indicate that it needs to live in R0. When
678 // this occurs, we need to have information available that
679 // indicates it is safe to use R1 for the reload instead of R0.
680 //
681 // To further complicate matters, we might conflict with an alias,
682 // or R0 and R1 might not be compatible with each other. In this
683 // case, we actually insert a reload for V1 in R1, ensuring that
684 // we can get at R0 or its alias.
685 ReusedOperands.addReuse(i, StackSlot, PhysReg,
686 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000687 if (ti != -1)
688 // Only mark it clobbered if this is a use&def operand.
689 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000690 ++NumReused;
691 continue;
692 }
693
694 // Otherwise we have a situation where we have a two-address instruction
695 // whose mod/ref operand needs to be reloaded. This reload is already
696 // available in some register "PhysReg", but if we used PhysReg as the
697 // operand to our 2-addr instruction, the instruction would modify
698 // PhysReg. This isn't cool if something later uses PhysReg and expects
699 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000700 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000701 // To avoid this problem, and to avoid doing a load right after a store,
702 // we emit a copy from PhysReg into the designated register for this
703 // operand.
704 unsigned DesignatedReg = VRM.getPhys(VirtReg);
705 assert(DesignatedReg && "Must map virtreg to physreg!");
706
707 // Note that, if we reused a register for a previous operand, the
708 // register we want to reload into might not actually be
709 // available. If this occurs, use the register indicated by the
710 // reuser.
711 if (ReusedOperands.hasReuses())
712 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
713 Spills, MaybeDeadStores);
714
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000715 // If the mapped designated register is actually the physreg we have
716 // incoming, we don't need to inserted a dead copy.
717 if (DesignatedReg == PhysReg) {
718 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000719 DOUT << "Reusing SS#" << StackSlot << " from physreg "
720 << MRI->getName(PhysReg) << " for vreg"
721 << VirtReg
722 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000723 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000724 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000725 ++NumReused;
726 continue;
727 }
728
Chris Lattneraddc55a2006-04-28 01:46:50 +0000729 const TargetRegisterClass* RC =
730 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
731
732 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000733 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000734 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
735
736 // This invalidates DesignatedReg.
737 Spills.ClobberPhysReg(DesignatedReg);
738
Evan Cheng91e23902007-02-23 01:13:26 +0000739 Spills.addAvailable(StackSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000740 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000741 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000742 ++NumReused;
743 continue;
744 }
745
746 // Otherwise, reload it and remember that we have it.
747 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000748 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000749 const TargetRegisterClass* RC =
750 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000751
Chris Lattner50ea01e2005-09-09 20:29:51 +0000752 // Note that, if we reused a register for a previous operand, the
753 // register we want to reload into might not actually be
754 // available. If this occurs, use the register indicated by the
755 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000756 if (ReusedOperands.hasReuses())
757 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
758 Spills, MaybeDeadStores);
759
Chris Lattner50ea01e2005-09-09 20:29:51 +0000760 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000761 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000762 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000763 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000764 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000765
766 // Any stores to this stack slot are not dead anymore.
767 MaybeDeadStores.erase(StackSlot);
Evan Cheng91e23902007-02-23 01:13:26 +0000768 Spills.addAvailable(StackSlot, &MI, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000769 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000770 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000771 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000772 }
773
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000774 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000775
Chris Lattner7fb64342004-10-01 19:04:51 +0000776 // If we have folded references to memory operands, make sure we clear all
777 // physical registers that may contain the value of the spilled virtual
778 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000779 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
780 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000781 DOUT << "Folded vreg: " << I->second.first << " MR: "
782 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000783 unsigned VirtReg = I->second.first;
784 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000785 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000786 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000787 continue;
788 }
789 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000790 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000791
792 // If this folded instruction is just a use, check to see if it's a
793 // straight load from the virt reg slot.
794 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
795 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000796 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000797 if (FrameIdx == SS) {
798 // If this spill slot is available, turn it into a copy (or nothing)
799 // instead of leaving it as a load!
Evan Cheng91e23902007-02-23 01:13:26 +0000800 MachineInstr *Dummy = NULL;
801 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, Dummy)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000802 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000803 MachineFunction &MF = *MBB.getParent();
804 if (DestReg != InReg) {
805 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
806 MF.getSSARegMap()->getRegClass(VirtReg));
807 // Revisit the copy so we make sure to notice the effects of the
808 // operation on the destreg (either needing to RA it if it's
809 // virtual or needing to clobber any values if it's physical).
810 NextMII = &MI;
811 --NextMII; // backtrack to the copy.
812 }
813 VRM.RemoveFromFoldedVirtMap(&MI);
814 MBB.erase(&MI);
815 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000816 }
Chris Lattnercea86882005-09-19 06:56:21 +0000817 }
818 }
819 }
820
821 // If this reference is not a use, any previous store is now dead.
822 // Otherwise, the store to this stack slot is not dead anymore.
823 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
824 if (MDSI != MaybeDeadStores.end()) {
825 if (MR & VirtRegMap::isRef) // Previous store is not dead.
826 MaybeDeadStores.erase(MDSI);
827 else {
828 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000829 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000830 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000831 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000832 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000833 MaybeDeadStores.erase(MDSI);
834 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000835 }
836 }
837
838 // If the spill slot value is available, and this is a new definition of
839 // the value, the value is not available anymore.
840 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000841 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000842 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000843
844 // If this is *just* a mod of the value, check to see if this is just a
845 // store to the spill slot (i.e. the spill got merged into the copy). If
846 // so, realize that the vreg is available now, and add the store to the
847 // MaybeDeadStore info.
848 int StackSlot;
849 if (!(MR & VirtRegMap::isRef)) {
850 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
851 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
852 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000853 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000854 // this as a potentially dead store in case there is a subsequent
855 // store into the stack slot without a read from it.
856 MaybeDeadStores[StackSlot] = &MI;
857
Chris Lattnercd816392006-02-02 23:29:36 +0000858 // If the stack slot value was previously available in some other
859 // register, change it now. Otherwise, make the register available,
860 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +0000861 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000862 }
863 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000864 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000865 }
866
Chris Lattner7fb64342004-10-01 19:04:51 +0000867 // Process all of the spilled defs.
868 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
869 MachineOperand &MO = MI.getOperand(i);
870 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
871 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000872
Chris Lattner7fb64342004-10-01 19:04:51 +0000873 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000874 // Check to see if this is a noop copy. If so, eliminate the
875 // instruction before considering the dest reg to be changed.
876 unsigned Src, Dst;
877 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
878 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000879 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +0000880 MBB.erase(&MI);
881 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000882 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +0000883 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000884 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000885
886 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000887 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000888 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000889
890 // Check to see if this instruction is a load from a stack slot into
891 // a register. If so, this provides the stack slot value in the reg.
892 int FrameIdx;
893 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
894 assert(DestReg == VirtReg && "Unknown load situation!");
895
896 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +0000897 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000898 goto ProcessNextInst;
899 }
900
Chris Lattner29268692006-09-05 02:12:02 +0000901 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000902 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000903
Chris Lattner84e752a2006-02-03 03:06:49 +0000904 // The only vregs left are stack slot definitions.
905 int StackSlot = VRM.getStackSlot(VirtReg);
906 const TargetRegisterClass *RC =
907 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000908
Chris Lattner29268692006-09-05 02:12:02 +0000909 // If this def is part of a two-address operand, make sure to execute
910 // the store from the correct physical register.
911 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +0000912 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000913 if (TiedOp != -1)
914 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +0000915 else {
Chris Lattner29268692006-09-05 02:12:02 +0000916 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000917 if (ReusedOperands.isClobbered(PhysReg)) {
918 // Another def has taken the assigned physreg. It must have been a
919 // use&def which got it due to reuse. Undo the reuse!
920 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
921 Spills, MaybeDeadStores);
922 }
923 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000924
Chris Lattner84e752a2006-02-03 03:06:49 +0000925 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000926 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000927 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000928 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000929 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000930
Chris Lattner84e752a2006-02-03 03:06:49 +0000931 // If there is a dead store to this stack slot, nuke it now.
932 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
933 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000934 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +0000935 ++NumDSE;
936 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000937 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000938 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000939 LastStore = next(MII);
940
941 // If the stack slot value was previously available in some other
942 // register, change it now. Otherwise, make the register available,
943 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000944 Spills.ModifyStackSlot(StackSlot);
945 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +0000946 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000947 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +0000948
949 // Check to see if this is a noop copy. If so, eliminate the
950 // instruction before considering the dest reg to be changed.
951 {
952 unsigned Src, Dst;
953 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
954 ++NumDCE;
955 DOUT << "Removing now-noop copy: " << MI;
956 MBB.erase(&MI);
957 VRM.RemoveFromFoldedVirtMap(&MI);
958 goto ProcessNextInst;
959 }
960 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000961 }
962 }
Chris Lattnercea86882005-09-19 06:56:21 +0000963 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000964 MII = NextMII;
965 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000966}
967
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000968
969
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000970llvm::Spiller* llvm::createSpiller() {
971 switch (SpillerOpt) {
972 default: assert(0 && "Unreachable!");
973 case local:
974 return new LocalSpiller();
975 case simple:
976 return new SimpleSpiller();
977 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000978}