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Jia Liu31d157a2012-02-18 12:03:15 +00001//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
Misha Brukmanb5f662f2005-04-21 23:30:14 +00002//
Misha Brukmanf2ccb772004-08-17 04:55:41 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanb5f662f2005-04-21 23:30:14 +00007//
Misha Brukmanf2ccb772004-08-17 04:55:41 +00008//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner16e71f22005-10-14 23:59:06 +000014#include "PPCInstrInfo.h"
Evan Cheng59ee62d2011-07-11 03:57:24 +000015#include "PPC.h"
Owen Andersonf6372aa2008-01-01 21:11:32 +000016#include "PPCInstrBuilder.h"
Bill Wendling7194aaf2008-03-03 22:19:16 +000017#include "PPCMachineFunctionInfo.h"
Chris Lattnerb1d26f62006-06-17 00:01:04 +000018#include "PPCTargetMachine.h"
Andrew Trick2da8bc82010-12-24 05:03:26 +000019#include "PPCHazardRecognizers.h"
Evan Cheng94b95502011-07-26 00:24:13 +000020#include "MCTargetDesc/PPCPredicates.h"
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +000021#include "llvm/CodeGen/MachineFrameInfo.h"
Misha Brukmanf2ccb772004-08-17 04:55:41 +000022#include "llvm/CodeGen/MachineInstrBuilder.h"
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +000023#include "llvm/CodeGen/MachineMemOperand.h"
Jakob Stoklund Olesen24329662010-02-26 21:09:24 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
Hal Finkel4d989ac2012-04-01 19:22:40 +000025#include "llvm/CodeGen/PseudoSourceValue.h"
Evan Cheng59ee62d2011-07-11 03:57:24 +000026#include "llvm/MC/MCAsmInfo.h"
Bill Wendling880d0f62008-03-04 23:13:51 +000027#include "llvm/Support/CommandLine.h"
Torok Edwindac237e2009-07-08 20:53:28 +000028#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +000029#include "llvm/Support/TargetRegistry.h"
Torok Edwindac237e2009-07-08 20:53:28 +000030#include "llvm/Support/raw_ostream.h"
Evan Cheng59ee62d2011-07-11 03:57:24 +000031#include "llvm/ADT/STLExtras.h"
Misha Brukmanf2ccb772004-08-17 04:55:41 +000032
Evan Cheng4db3cff2011-07-01 17:57:27 +000033#define GET_INSTRINFO_CTOR
Evan Cheng22fee2d2011-06-28 20:07:07 +000034#include "PPCGenInstrInfo.inc"
35
Dan Gohman82bcd232010-04-15 17:20:57 +000036namespace llvm {
Hal Finkel3fd00182011-12-05 17:55:17 +000037extern cl::opt<bool> DisablePPC32RS;
38extern cl::opt<bool> DisablePPC64RS;
Dan Gohman82bcd232010-04-15 17:20:57 +000039}
40
41using namespace llvm;
Bill Wendling880d0f62008-03-04 23:13:51 +000042
Hal Finkel09fdc7b2012-06-08 15:38:25 +000043static cl::
Hal Finkel7255d2a2012-06-08 19:19:53 +000044opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
45 cl::desc("Disable analysis for CTR loops"));
Hal Finkel09fdc7b2012-06-08 15:38:25 +000046
Chris Lattnerb1d26f62006-06-17 00:01:04 +000047PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
Evan Cheng4db3cff2011-07-01 17:57:27 +000048 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
Evan Chengd5b03f22011-06-28 21:14:33 +000049 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
Chris Lattnerb1d26f62006-06-17 00:01:04 +000050
Andrew Trick2da8bc82010-12-24 05:03:26 +000051/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
52/// this target when scheduling the DAG.
53ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
54 const TargetMachine *TM,
55 const ScheduleDAG *DAG) const {
Hal Finkelc6d08f12011-10-17 04:03:49 +000056 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
Hal Finkel4d989ac2012-04-01 19:22:40 +000057 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2) {
Hal Finkel768c65f2011-11-22 16:21:04 +000058 const InstrItineraryData *II = TM->getInstrItineraryData();
Hal Finkel5b00cea2012-03-31 14:45:15 +000059 return new PPCScoreboardHazardRecognizer(II, DAG);
Hal Finkelc6d08f12011-10-17 04:03:49 +000060 }
Hal Finkel64c34e22011-12-02 04:58:02 +000061
62 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
Andrew Trick2da8bc82010-12-24 05:03:26 +000063}
64
Hal Finkel64c34e22011-12-02 04:58:02 +000065/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
66/// to use for this target when scheduling the DAG.
67ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
68 const InstrItineraryData *II,
69 const ScheduleDAG *DAG) const {
70 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
71
72 // Most subtargets use a PPC970 recognizer.
Hal Finkel4d989ac2012-04-01 19:22:40 +000073 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2) {
Hal Finkel64c34e22011-12-02 04:58:02 +000074 const TargetInstrInfo *TII = TM.getInstrInfo();
75 assert(TII && "No InstrInfo?");
76
77 return new PPCHazardRecognizer970(*TII);
78 }
79
Hal Finkel4d989ac2012-04-01 19:22:40 +000080 return new PPCScoreboardHazardRecognizer(II, DAG);
Hal Finkel64c34e22011-12-02 04:58:02 +000081}
Jakob Stoklund Olesen71642882012-06-19 21:14:34 +000082
83// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
84bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
85 unsigned &SrcReg, unsigned &DstReg,
86 unsigned &SubIdx) const {
87 switch (MI.getOpcode()) {
88 default: return false;
89 case PPC::EXTSW:
90 case PPC::EXTSW_32_64:
91 SrcReg = MI.getOperand(1).getReg();
92 DstReg = MI.getOperand(0).getReg();
93 SubIdx = PPC::sub_32;
94 return true;
95 }
96}
97
Andrew Trick6e8f4c42010-12-24 04:28:06 +000098unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
Chris Lattner9c09c9e2006-03-16 22:24:02 +000099 int &FrameIndex) const {
Chris Lattner40839602006-02-02 20:12:32 +0000100 switch (MI->getOpcode()) {
101 default: break;
102 case PPC::LD:
103 case PPC::LWZ:
104 case PPC::LFS:
105 case PPC::LFD:
Dan Gohmand735b802008-10-03 15:45:36 +0000106 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
107 MI->getOperand(2).isFI()) {
Chris Lattner8aa797a2007-12-30 23:10:15 +0000108 FrameIndex = MI->getOperand(2).getIndex();
Chris Lattner40839602006-02-02 20:12:32 +0000109 return MI->getOperand(0).getReg();
110 }
111 break;
112 }
113 return 0;
Chris Lattner65242872006-02-02 20:16:12 +0000114}
Chris Lattner40839602006-02-02 20:12:32 +0000115
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000116unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattner65242872006-02-02 20:16:12 +0000117 int &FrameIndex) const {
118 switch (MI->getOpcode()) {
119 default: break;
Nate Begeman3b478b32006-02-02 21:07:50 +0000120 case PPC::STD:
Chris Lattner65242872006-02-02 20:16:12 +0000121 case PPC::STW:
122 case PPC::STFS:
123 case PPC::STFD:
Dan Gohmand735b802008-10-03 15:45:36 +0000124 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
125 MI->getOperand(2).isFI()) {
Chris Lattner8aa797a2007-12-30 23:10:15 +0000126 FrameIndex = MI->getOperand(2).getIndex();
Chris Lattner65242872006-02-02 20:16:12 +0000127 return MI->getOperand(0).getReg();
128 }
129 break;
130 }
131 return 0;
132}
Chris Lattner40839602006-02-02 20:12:32 +0000133
Chris Lattner043870d2005-09-09 18:17:41 +0000134// commuteInstruction - We can commute rlwimi instructions, but only if the
135// rotate amt is zero. We also have to munge the immediates a bit.
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000136MachineInstr *
137PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000138 MachineFunction &MF = *MI->getParent()->getParent();
139
Chris Lattner043870d2005-09-09 18:17:41 +0000140 // Normal instructions can be commuted the obvious way.
141 if (MI->getOpcode() != PPC::RLWIMI)
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000142 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000143
Chris Lattner043870d2005-09-09 18:17:41 +0000144 // Cannot commute if it has a non-zero rotate count.
Chris Lattner9a1ceae2007-12-30 20:49:49 +0000145 if (MI->getOperand(3).getImm() != 0)
Chris Lattner043870d2005-09-09 18:17:41 +0000146 return 0;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000147
Chris Lattner043870d2005-09-09 18:17:41 +0000148 // If we have a zero rotate count, we have:
149 // M = mask(MB,ME)
150 // Op0 = (Op1 & ~M) | (Op2 & M)
151 // Change this to:
152 // M = mask((ME+1)&31, (MB-1)&31)
153 // Op0 = (Op2 & ~M) | (Op1 & M)
154
155 // Swap op1/op2
Evan Chenga4d16a12008-02-13 02:46:49 +0000156 unsigned Reg0 = MI->getOperand(0).getReg();
Chris Lattner043870d2005-09-09 18:17:41 +0000157 unsigned Reg1 = MI->getOperand(1).getReg();
158 unsigned Reg2 = MI->getOperand(2).getReg();
Evan Cheng6ce7dc22006-11-15 20:58:11 +0000159 bool Reg1IsKill = MI->getOperand(1).isKill();
160 bool Reg2IsKill = MI->getOperand(2).isKill();
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000161 bool ChangeReg0 = false;
Evan Chenga4d16a12008-02-13 02:46:49 +0000162 // If machine instrs are no longer in two-address forms, update
163 // destination register as well.
164 if (Reg0 == Reg1) {
165 // Must be two address instruction!
Evan Chenge837dea2011-06-28 19:10:37 +0000166 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
Evan Chenga4d16a12008-02-13 02:46:49 +0000167 "Expecting a two-address instruction!");
Evan Chenga4d16a12008-02-13 02:46:49 +0000168 Reg2IsKill = false;
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000169 ChangeReg0 = true;
Evan Chenga4d16a12008-02-13 02:46:49 +0000170 }
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000171
172 // Masks.
173 unsigned MB = MI->getOperand(4).getImm();
174 unsigned ME = MI->getOperand(5).getImm();
175
176 if (NewMI) {
177 // Create a new instruction.
178 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
179 bool Reg0IsDead = MI->getOperand(0).isDead();
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000180 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
Bill Wendling587daed2009-05-13 21:33:08 +0000181 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
182 .addReg(Reg2, getKillRegState(Reg2IsKill))
183 .addReg(Reg1, getKillRegState(Reg1IsKill))
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000184 .addImm((ME+1) & 31)
185 .addImm((MB-1) & 31);
186 }
187
188 if (ChangeReg0)
189 MI->getOperand(0).setReg(Reg2);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000190 MI->getOperand(2).setReg(Reg1);
191 MI->getOperand(1).setReg(Reg2);
Chris Lattnerf7382302007-12-30 21:56:09 +0000192 MI->getOperand(2).setIsKill(Reg1IsKill);
193 MI->getOperand(1).setIsKill(Reg2IsKill);
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000194
Chris Lattner043870d2005-09-09 18:17:41 +0000195 // Swap the mask around.
Chris Lattner9a1ceae2007-12-30 20:49:49 +0000196 MI->getOperand(4).setImm((ME+1) & 31);
197 MI->getOperand(5).setImm((MB-1) & 31);
Chris Lattner043870d2005-09-09 18:17:41 +0000198 return MI;
199}
Chris Lattnerbbf1c722006-03-05 23:49:55 +0000200
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000201void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
Chris Lattnerbbf1c722006-03-05 23:49:55 +0000202 MachineBasicBlock::iterator MI) const {
Chris Lattnerc7f3ace2010-04-02 20:16:16 +0000203 DebugLoc DL;
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000204 BuildMI(MBB, MI, DL, get(PPC::NOP));
Chris Lattnerbbf1c722006-03-05 23:49:55 +0000205}
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000206
207
208// Branch analysis.
Hal Finkel99f823f2012-06-08 15:38:21 +0000209// Note: If the condition register is set to CTR or CTR8 then this is a
210// BDNZ (imm == 1) or BDZ (imm == 0) branch.
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000211bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
212 MachineBasicBlock *&FBB,
Evan Chengdc54d312009-02-09 07:14:22 +0000213 SmallVectorImpl<MachineOperand> &Cond,
214 bool AllowModify) const {
Hal Finkel99f823f2012-06-08 15:38:21 +0000215 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
216
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000217 // If the block has no terminators, it just falls into the block after it.
218 MachineBasicBlock::iterator I = MBB.end();
Dale Johannesen93d6a7e2010-04-02 01:38:09 +0000219 if (I == MBB.begin())
220 return false;
221 --I;
222 while (I->isDebugValue()) {
223 if (I == MBB.begin())
224 return false;
225 --I;
226 }
227 if (!isUnpredicatedTerminator(I))
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000228 return false;
229
230 // Get the last instruction in the block.
231 MachineInstr *LastInst = I;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000232
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000233 // If there is only one terminator instruction, process it.
Evan Chengbfd2ec42007-06-08 21:59:56 +0000234 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000235 if (LastInst->getOpcode() == PPC::B) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000236 if (!LastInst->getOperand(0).isMBB())
237 return true;
Chris Lattner8aa797a2007-12-30 23:10:15 +0000238 TBB = LastInst->getOperand(0).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000239 return false;
Chris Lattner289c2d52006-11-17 22:14:47 +0000240 } else if (LastInst->getOpcode() == PPC::BCC) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000241 if (!LastInst->getOperand(2).isMBB())
242 return true;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000243 // Block ends with fall-through condbranch.
Chris Lattner8aa797a2007-12-30 23:10:15 +0000244 TBB = LastInst->getOperand(2).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000245 Cond.push_back(LastInst->getOperand(0));
246 Cond.push_back(LastInst->getOperand(1));
Chris Lattner7c4fe252006-10-21 06:03:11 +0000247 return false;
Hal Finkel99f823f2012-06-08 15:38:21 +0000248 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
249 LastInst->getOpcode() == PPC::BDNZ) {
250 if (!LastInst->getOperand(0).isMBB())
251 return true;
Hal Finkel7255d2a2012-06-08 19:19:53 +0000252 if (DisableCTRLoopAnal)
Hal Finkel09fdc7b2012-06-08 15:38:25 +0000253 return true;
Hal Finkel99f823f2012-06-08 15:38:21 +0000254 TBB = LastInst->getOperand(0).getMBB();
255 Cond.push_back(MachineOperand::CreateImm(1));
256 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
257 true));
258 return false;
259 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
260 LastInst->getOpcode() == PPC::BDZ) {
261 if (!LastInst->getOperand(0).isMBB())
262 return true;
Hal Finkel7255d2a2012-06-08 19:19:53 +0000263 if (DisableCTRLoopAnal)
Hal Finkel09fdc7b2012-06-08 15:38:25 +0000264 return true;
Hal Finkel99f823f2012-06-08 15:38:21 +0000265 TBB = LastInst->getOperand(0).getMBB();
266 Cond.push_back(MachineOperand::CreateImm(0));
267 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
268 true));
269 return false;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000270 }
Hal Finkel99f823f2012-06-08 15:38:21 +0000271
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000272 // Otherwise, don't know what this is.
273 return true;
274 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000275
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000276 // Get the instruction before it if it's a terminator.
277 MachineInstr *SecondLastInst = I;
278
279 // If there are three terminators, we don't know what sort of block this is.
280 if (SecondLastInst && I != MBB.begin() &&
Evan Chengbfd2ec42007-06-08 21:59:56 +0000281 isUnpredicatedTerminator(--I))
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000282 return true;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000283
Chris Lattner289c2d52006-11-17 22:14:47 +0000284 // If the block ends with PPC::B and PPC:BCC, handle it.
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000285 if (SecondLastInst->getOpcode() == PPC::BCC &&
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000286 LastInst->getOpcode() == PPC::B) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000287 if (!SecondLastInst->getOperand(2).isMBB() ||
288 !LastInst->getOperand(0).isMBB())
289 return true;
Chris Lattner8aa797a2007-12-30 23:10:15 +0000290 TBB = SecondLastInst->getOperand(2).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000291 Cond.push_back(SecondLastInst->getOperand(0));
292 Cond.push_back(SecondLastInst->getOperand(1));
Chris Lattner8aa797a2007-12-30 23:10:15 +0000293 FBB = LastInst->getOperand(0).getMBB();
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000294 return false;
Hal Finkel99f823f2012-06-08 15:38:21 +0000295 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
296 SecondLastInst->getOpcode() == PPC::BDNZ) &&
297 LastInst->getOpcode() == PPC::B) {
298 if (!SecondLastInst->getOperand(0).isMBB() ||
299 !LastInst->getOperand(0).isMBB())
300 return true;
Hal Finkel7255d2a2012-06-08 19:19:53 +0000301 if (DisableCTRLoopAnal)
Hal Finkel09fdc7b2012-06-08 15:38:25 +0000302 return true;
Hal Finkel99f823f2012-06-08 15:38:21 +0000303 TBB = SecondLastInst->getOperand(0).getMBB();
304 Cond.push_back(MachineOperand::CreateImm(1));
305 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
306 true));
307 FBB = LastInst->getOperand(0).getMBB();
308 return false;
309 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
310 SecondLastInst->getOpcode() == PPC::BDZ) &&
311 LastInst->getOpcode() == PPC::B) {
312 if (!SecondLastInst->getOperand(0).isMBB() ||
313 !LastInst->getOperand(0).isMBB())
314 return true;
Hal Finkel7255d2a2012-06-08 19:19:53 +0000315 if (DisableCTRLoopAnal)
Hal Finkel09fdc7b2012-06-08 15:38:25 +0000316 return true;
Hal Finkel99f823f2012-06-08 15:38:21 +0000317 TBB = SecondLastInst->getOperand(0).getMBB();
318 Cond.push_back(MachineOperand::CreateImm(0));
319 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
320 true));
321 FBB = LastInst->getOperand(0).getMBB();
322 return false;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000323 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000324
Dale Johannesen13e8b512007-06-13 17:59:52 +0000325 // If the block ends with two PPC:Bs, handle it. The second one is not
326 // executed, so remove it.
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000327 if (SecondLastInst->getOpcode() == PPC::B &&
Dale Johannesen13e8b512007-06-13 17:59:52 +0000328 LastInst->getOpcode() == PPC::B) {
Evan Cheng82ae9332009-05-08 23:09:25 +0000329 if (!SecondLastInst->getOperand(0).isMBB())
330 return true;
Chris Lattner8aa797a2007-12-30 23:10:15 +0000331 TBB = SecondLastInst->getOperand(0).getMBB();
Dale Johannesen13e8b512007-06-13 17:59:52 +0000332 I = LastInst;
Evan Chengdc54d312009-02-09 07:14:22 +0000333 if (AllowModify)
334 I->eraseFromParent();
Dale Johannesen13e8b512007-06-13 17:59:52 +0000335 return false;
336 }
337
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000338 // Otherwise, can't handle this.
339 return true;
340}
341
Evan Chengb5cdaa22007-05-18 00:05:48 +0000342unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000343 MachineBasicBlock::iterator I = MBB.end();
Evan Chengb5cdaa22007-05-18 00:05:48 +0000344 if (I == MBB.begin()) return 0;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000345 --I;
Dale Johannesen93d6a7e2010-04-02 01:38:09 +0000346 while (I->isDebugValue()) {
347 if (I == MBB.begin())
348 return 0;
349 --I;
350 }
Hal Finkel99f823f2012-06-08 15:38:21 +0000351 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
352 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
353 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
Evan Chengb5cdaa22007-05-18 00:05:48 +0000354 return 0;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000355
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000356 // Remove the branch.
357 I->eraseFromParent();
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000358
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000359 I = MBB.end();
360
Evan Chengb5cdaa22007-05-18 00:05:48 +0000361 if (I == MBB.begin()) return 1;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000362 --I;
Hal Finkel99f823f2012-06-08 15:38:21 +0000363 if (I->getOpcode() != PPC::BCC &&
364 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
365 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
Evan Chengb5cdaa22007-05-18 00:05:48 +0000366 return 1;
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000367
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000368 // Remove the branch.
369 I->eraseFromParent();
Evan Chengb5cdaa22007-05-18 00:05:48 +0000370 return 2;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000371}
372
Evan Chengb5cdaa22007-05-18 00:05:48 +0000373unsigned
374PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
375 MachineBasicBlock *FBB,
Stuart Hastings3bf91252010-06-17 22:43:56 +0000376 const SmallVectorImpl<MachineOperand> &Cond,
377 DebugLoc DL) const {
Chris Lattner2dc77232006-10-17 18:06:55 +0000378 // Shouldn't be a fall through.
379 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000380 assert((Cond.size() == 2 || Cond.size() == 0) &&
Chris Lattner54108062006-10-21 05:36:13 +0000381 "PPC branch conditions have two components!");
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000382
Hal Finkel99f823f2012-06-08 15:38:21 +0000383 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
384
Chris Lattner54108062006-10-21 05:36:13 +0000385 // One-way branch.
Chris Lattner2dc77232006-10-17 18:06:55 +0000386 if (FBB == 0) {
Chris Lattner54108062006-10-21 05:36:13 +0000387 if (Cond.empty()) // Unconditional branch
Stuart Hastings3bf91252010-06-17 22:43:56 +0000388 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
Hal Finkel99f823f2012-06-08 15:38:21 +0000389 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
390 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
391 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
392 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
Chris Lattner54108062006-10-21 05:36:13 +0000393 else // Conditional branch
Stuart Hastings3bf91252010-06-17 22:43:56 +0000394 BuildMI(&MBB, DL, get(PPC::BCC))
Chris Lattner18258c62006-11-17 22:37:34 +0000395 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
Evan Chengb5cdaa22007-05-18 00:05:48 +0000396 return 1;
Chris Lattner2dc77232006-10-17 18:06:55 +0000397 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000398
Chris Lattner879d09c2006-10-21 05:42:09 +0000399 // Two-way Conditional Branch.
Hal Finkel99f823f2012-06-08 15:38:21 +0000400 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
401 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
402 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
403 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
404 else
405 BuildMI(&MBB, DL, get(PPC::BCC))
406 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
Stuart Hastings3bf91252010-06-17 22:43:56 +0000407 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
Evan Chengb5cdaa22007-05-18 00:05:48 +0000408 return 2;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000409}
410
Jakob Stoklund Olesen27689b02010-07-11 07:31:00 +0000411void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I, DebugLoc DL,
413 unsigned DestReg, unsigned SrcReg,
414 bool KillSrc) const {
415 unsigned Opc;
416 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
417 Opc = PPC::OR;
418 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
419 Opc = PPC::OR8;
420 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
421 Opc = PPC::FMR;
422 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
423 Opc = PPC::MCRF;
424 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
425 Opc = PPC::VOR;
426 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
427 Opc = PPC::CROR;
428 else
429 llvm_unreachable("Impossible reg-to-reg copy");
Owen Andersond10fd972007-12-31 06:32:00 +0000430
Evan Chenge837dea2011-06-28 19:10:37 +0000431 const MCInstrDesc &MCID = get(Opc);
432 if (MCID.getNumOperands() == 3)
433 BuildMI(MBB, I, DL, MCID, DestReg)
Jakob Stoklund Olesen27689b02010-07-11 07:31:00 +0000434 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
435 else
Evan Chenge837dea2011-06-28 19:10:37 +0000436 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
Owen Andersond10fd972007-12-31 06:32:00 +0000437}
438
Hal Finkel3fd00182011-12-05 17:55:17 +0000439// This function returns true if a CR spill is necessary and false otherwise.
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000440bool
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000441PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
442 unsigned SrcReg, bool isKill,
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000443 int FrameIdx,
444 const TargetRegisterClass *RC,
445 SmallVectorImpl<MachineInstr*> &NewMIs) const{
Chris Lattnerc7f3ace2010-04-02 20:16:16 +0000446 DebugLoc DL;
Craig Topperc9099502012-04-20 06:31:50 +0000447 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000448 if (SrcReg != PPC::LR) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000449 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
Bill Wendling587daed2009-05-13 21:33:08 +0000450 .addReg(SrcReg,
451 getKillRegState(isKill)),
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000452 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000453 } else {
454 // FIXME: this spills LR immediately to memory in one step. To do this,
455 // we use R11, which we know cannot be used in the prolog/epilog. This is
456 // a hack.
Dale Johannesen21b55412009-02-12 23:08:38 +0000457 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
458 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
Bill Wendling587daed2009-05-13 21:33:08 +0000459 .addReg(PPC::R11,
460 getKillRegState(isKill)),
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000461 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000462 }
Craig Topperc9099502012-04-20 06:31:50 +0000463 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000464 if (SrcReg != PPC::LR8) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000465 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
Bill Wendling587daed2009-05-13 21:33:08 +0000466 .addReg(SrcReg,
467 getKillRegState(isKill)),
468 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000469 } else {
470 // FIXME: this spills LR immediately to memory in one step. To do this,
Hal Finkel7ad6b7d2011-12-07 06:32:37 +0000471 // we use X11, which we know cannot be used in the prolog/epilog. This is
Owen Andersonf6372aa2008-01-01 21:11:32 +0000472 // a hack.
Dale Johannesen21b55412009-02-12 23:08:38 +0000473 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
474 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
Bill Wendling587daed2009-05-13 21:33:08 +0000475 .addReg(PPC::X11,
476 getKillRegState(isKill)),
477 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000478 }
Craig Topperc9099502012-04-20 06:31:50 +0000479 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000480 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
Bill Wendling587daed2009-05-13 21:33:08 +0000481 .addReg(SrcReg,
482 getKillRegState(isKill)),
483 FrameIdx));
Craig Topperc9099502012-04-20 06:31:50 +0000484 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000485 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
Bill Wendling587daed2009-05-13 21:33:08 +0000486 .addReg(SrcReg,
487 getKillRegState(isKill)),
488 FrameIdx));
Craig Topperc9099502012-04-20 06:31:50 +0000489 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
Hal Finkel3fd00182011-12-05 17:55:17 +0000490 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
491 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
Dale Johannesen21b55412009-02-12 23:08:38 +0000492 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
Bill Wendling587daed2009-05-13 21:33:08 +0000493 .addReg(SrcReg,
494 getKillRegState(isKill)),
Chris Lattner71a2cb22008-03-20 01:22:40 +0000495 FrameIdx));
Bill Wendling7194aaf2008-03-03 22:19:16 +0000496 return true;
497 } else {
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000498 // FIXME: We need a scatch reg here. The trouble with using R0 is that
499 // it's possible for the stack frame to be so big the save location is
500 // out of range of immediate offsets, necessitating another register.
501 // We hack this on Darwin by reserving R2. It's probably broken on Linux
502 // at the moment.
503
Hal Finkel234bb382011-12-07 06:34:06 +0000504 bool is64Bit = TM.getSubtargetImpl()->isPPC64();
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000505 // We need to store the CR in the low 4-bits of the saved value. First,
506 // issue a MFCR to save all of the CRBits.
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000507 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
Hal Finkel234bb382011-12-07 06:34:06 +0000508 (is64Bit ? PPC::X2 : PPC::R2) :
509 (is64Bit ? PPC::X0 : PPC::R0);
510 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
511 PPC::MFCRpseud), ScratchReg)
Dale Johannesen5f07d522010-05-20 17:48:26 +0000512 .addReg(SrcReg, getKillRegState(isKill)));
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000513
Bill Wendling7194aaf2008-03-03 22:19:16 +0000514 // If the saved register wasn't CR0, shift the bits left so that they are
515 // in CR0's slot.
516 if (SrcReg != PPC::CR0) {
Evan Cheng966aeb52011-07-25 19:53:23 +0000517 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000518 // rlwinm scratch, scratch, ShiftBits, 0, 31.
Hal Finkel234bb382011-12-07 06:34:06 +0000519 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
520 PPC::RLWINM), ScratchReg)
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000521 .addReg(ScratchReg).addImm(ShiftBits)
522 .addImm(0).addImm(31));
Bill Wendling7194aaf2008-03-03 22:19:16 +0000523 }
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000524
Hal Finkel234bb382011-12-07 06:34:06 +0000525 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
526 PPC::STW8 : PPC::STW))
Dale Johannesenc12da8d2010-02-12 21:35:34 +0000527 .addReg(ScratchReg,
Bill Wendling587daed2009-05-13 21:33:08 +0000528 getKillRegState(isKill)),
Bill Wendling7194aaf2008-03-03 22:19:16 +0000529 FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000530 }
Craig Topperc9099502012-04-20 06:31:50 +0000531 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
Nicolas Geoffray0404cd92008-03-10 14:12:10 +0000532 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
533 // backend currently only uses CR1EQ as an individual bit, this should
534 // not cause any bug. If we need other uses of CR bits, the following
535 // code may be invalid.
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000536 unsigned Reg = 0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000537 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
538 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000539 Reg = PPC::CR0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000540 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
541 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000542 Reg = PPC::CR1;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000543 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
544 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000545 Reg = PPC::CR2;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000546 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
547 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000548 Reg = PPC::CR3;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000549 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
550 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000551 Reg = PPC::CR4;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000552 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
553 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000554 Reg = PPC::CR5;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000555 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
556 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000557 Reg = PPC::CR6;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000558 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
559 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000560 Reg = PPC::CR7;
561
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000562 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
Craig Topperc9099502012-04-20 06:31:50 +0000563 &PPC::CRRCRegClass, NewMIs);
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000564
Craig Topperc9099502012-04-20 06:31:50 +0000565 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000566 // We don't have indexed addressing for vector loads. Emit:
567 // R0 = ADDI FI#
568 // STVX VAL, 0, R0
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000569 //
Owen Andersonf6372aa2008-01-01 21:11:32 +0000570 // FIXME: We use R0 here, because it isn't available for RA.
Dale Johannesen21b55412009-02-12 23:08:38 +0000571 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000572 FrameIdx, 0, 0));
Dale Johannesen21b55412009-02-12 23:08:38 +0000573 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
Bill Wendling587daed2009-05-13 21:33:08 +0000574 .addReg(SrcReg, getKillRegState(isKill))
575 .addReg(PPC::R0)
576 .addReg(PPC::R0));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000577 } else {
Torok Edwinc23197a2009-07-14 16:55:14 +0000578 llvm_unreachable("Unknown regclass!");
Owen Andersonf6372aa2008-01-01 21:11:32 +0000579 }
Bill Wendling7194aaf2008-03-03 22:19:16 +0000580
581 return false;
Owen Andersonf6372aa2008-01-01 21:11:32 +0000582}
583
584void
585PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Bill Wendling7194aaf2008-03-03 22:19:16 +0000586 MachineBasicBlock::iterator MI,
587 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Cheng746ad692010-05-06 19:06:44 +0000588 const TargetRegisterClass *RC,
589 const TargetRegisterInfo *TRI) const {
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000590 MachineFunction &MF = *MBB.getParent();
Owen Andersonf6372aa2008-01-01 21:11:32 +0000591 SmallVector<MachineInstr*, 4> NewMIs;
Bill Wendling7194aaf2008-03-03 22:19:16 +0000592
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000593 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
594 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
Bill Wendling7194aaf2008-03-03 22:19:16 +0000595 FuncInfo->setSpillsCR();
596 }
597
Owen Andersonf6372aa2008-01-01 21:11:32 +0000598 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
599 MBB.insert(MI, NewMIs[i]);
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000600
601 const MachineFrameInfo &MFI = *MF.getFrameInfo();
602 MachineMemOperand *MMO =
Jay Foad978e0df2011-11-15 07:34:52 +0000603 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
Chris Lattner59db5492010-09-21 04:39:43 +0000604 MachineMemOperand::MOStore,
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000605 MFI.getObjectSize(FrameIdx),
606 MFI.getObjectAlignment(FrameIdx));
607 NewMIs.back()->addMemOperand(MF, MMO);
Owen Andersonf6372aa2008-01-01 21:11:32 +0000608}
609
Hal Finkeld21e9302011-12-06 20:55:36 +0000610bool
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000611PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000612 unsigned DestReg, int FrameIdx,
Bill Wendling4a66e9a2008-03-10 22:49:16 +0000613 const TargetRegisterClass *RC,
614 SmallVectorImpl<MachineInstr*> &NewMIs)const{
Craig Topperc9099502012-04-20 06:31:50 +0000615 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000616 if (DestReg != PPC::LR) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000617 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
618 DestReg), FrameIdx));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000619 } else {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000620 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
621 PPC::R11), FrameIdx));
622 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000623 }
Craig Topperc9099502012-04-20 06:31:50 +0000624 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000625 if (DestReg != PPC::LR8) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000626 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000627 FrameIdx));
628 } else {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000629 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
Hal Finkel7ad6b7d2011-12-07 06:32:37 +0000630 PPC::X11), FrameIdx));
631 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000632 }
Craig Topperc9099502012-04-20 06:31:50 +0000633 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000634 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000635 FrameIdx));
Craig Topperc9099502012-04-20 06:31:50 +0000636 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000637 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000638 FrameIdx));
Craig Topperc9099502012-04-20 06:31:50 +0000639 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
Hal Finkeld21e9302011-12-06 20:55:36 +0000640 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
641 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
642 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
643 get(PPC::RESTORE_CR), DestReg)
644 , FrameIdx));
645 return true;
646 } else {
647 // FIXME: We need a scatch reg here. The trouble with using R0 is that
648 // it's possible for the stack frame to be so big the save location is
649 // out of range of immediate offsets, necessitating another register.
650 // We hack this on Darwin by reserving R2. It's probably broken on Linux
651 // at the moment.
652 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
653 PPC::R2 : PPC::R0;
654 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
655 ScratchReg), FrameIdx));
656
657 // If the reloaded register isn't CR0, shift the bits right so that they are
658 // in the right CR's slot.
659 if (DestReg != PPC::CR0) {
660 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
661 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
662 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
663 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
664 .addImm(31));
665 }
666
Hal Finkel234bb382011-12-07 06:34:06 +0000667 NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
668 PPC::MTCRF8 : PPC::MTCRF), DestReg)
Hal Finkeld21e9302011-12-06 20:55:36 +0000669 .addReg(ScratchReg));
Owen Andersonf6372aa2008-01-01 21:11:32 +0000670 }
Craig Topperc9099502012-04-20 06:31:50 +0000671 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000672
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000673 unsigned Reg = 0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000674 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
675 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000676 Reg = PPC::CR0;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000677 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
678 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000679 Reg = PPC::CR1;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000680 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
681 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000682 Reg = PPC::CR2;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000683 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
684 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000685 Reg = PPC::CR3;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000686 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
687 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000688 Reg = PPC::CR4;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000689 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
690 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000691 Reg = PPC::CR5;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000692 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
693 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000694 Reg = PPC::CR6;
Tilmann Scheller6a3a1ba2009-07-03 06:47:55 +0000695 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
696 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000697 Reg = PPC::CR7;
698
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000699 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
Craig Topperc9099502012-04-20 06:31:50 +0000700 &PPC::CRRCRegClass, NewMIs);
Nicolas Geoffray9348c692008-03-10 17:46:45 +0000701
Craig Topperc9099502012-04-20 06:31:50 +0000702 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000703 // We don't have indexed addressing for vector loads. Emit:
704 // R0 = ADDI FI#
705 // Dest = LVX 0, R0
Andrew Trick6e8f4c42010-12-24 04:28:06 +0000706 //
Owen Andersonf6372aa2008-01-01 21:11:32 +0000707 // FIXME: We use R0 here, because it isn't available for RA.
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000708 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
Owen Andersonf6372aa2008-01-01 21:11:32 +0000709 FrameIdx, 0, 0));
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000710 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
Owen Andersonf6372aa2008-01-01 21:11:32 +0000711 .addReg(PPC::R0));
712 } else {
Torok Edwinc23197a2009-07-14 16:55:14 +0000713 llvm_unreachable("Unknown regclass!");
Owen Andersonf6372aa2008-01-01 21:11:32 +0000714 }
Hal Finkeld21e9302011-12-06 20:55:36 +0000715
716 return false;
Owen Andersonf6372aa2008-01-01 21:11:32 +0000717}
718
719void
720PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Bill Wendling7194aaf2008-03-03 22:19:16 +0000721 MachineBasicBlock::iterator MI,
722 unsigned DestReg, int FrameIdx,
Evan Cheng746ad692010-05-06 19:06:44 +0000723 const TargetRegisterClass *RC,
724 const TargetRegisterInfo *TRI) const {
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000725 MachineFunction &MF = *MBB.getParent();
Owen Andersonf6372aa2008-01-01 21:11:32 +0000726 SmallVector<MachineInstr*, 4> NewMIs;
Chris Lattnerc7f3ace2010-04-02 20:16:16 +0000727 DebugLoc DL;
Bill Wendlingd1c321a2009-02-12 00:02:55 +0000728 if (MI != MBB.end()) DL = MI->getDebugLoc();
Hal Finkeld21e9302011-12-06 20:55:36 +0000729 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
730 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
731 FuncInfo->setSpillsCR();
732 }
Owen Andersonf6372aa2008-01-01 21:11:32 +0000733 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
734 MBB.insert(MI, NewMIs[i]);
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000735
736 const MachineFrameInfo &MFI = *MF.getFrameInfo();
737 MachineMemOperand *MMO =
Jay Foad978e0df2011-11-15 07:34:52 +0000738 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
Chris Lattner59db5492010-09-21 04:39:43 +0000739 MachineMemOperand::MOLoad,
Jakob Stoklund Olesen7a79fcb2010-07-16 18:22:00 +0000740 MFI.getObjectSize(FrameIdx),
741 MFI.getObjectAlignment(FrameIdx));
742 NewMIs.back()->addMemOperand(MF, MMO);
Owen Andersonf6372aa2008-01-01 21:11:32 +0000743}
744
Evan Cheng09652172010-04-26 07:39:36 +0000745MachineInstr*
746PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
Evan Cheng8601a3d2010-04-29 01:13:30 +0000747 int FrameIx, uint64_t Offset,
Evan Cheng09652172010-04-26 07:39:36 +0000748 const MDNode *MDPtr,
749 DebugLoc DL) const {
750 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
751 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
752 return &*MIB;
753}
754
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000755bool PPCInstrInfo::
Owen Anderson44eb65c2008-08-14 22:49:33 +0000756ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner7c4fe252006-10-21 06:03:11 +0000757 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
Hal Finkel99f823f2012-06-08 15:38:21 +0000758 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
759 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
760 else
761 // Leave the CR# the same, but invert the condition.
762 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
Chris Lattner7c4fe252006-10-21 06:03:11 +0000763 return false;
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000764}
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000765
766/// GetInstSize - Return the number of bytes of code the specified
767/// instruction may be. This returns the maximum number of bytes.
768///
769unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
770 switch (MI->getOpcode()) {
771 case PPC::INLINEASM: { // Inline Asm: Variable size.
772 const MachineFunction *MF = MI->getParent()->getParent();
773 const char *AsmStr = MI->getOperand(0).getSymbolName();
Chris Lattneraf76e592009-08-22 20:48:53 +0000774 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000775 }
Bill Wendling7431bea2010-07-16 22:20:36 +0000776 case PPC::PROLOG_LABEL:
Dan Gohman44066042008-07-01 00:05:16 +0000777 case PPC::EH_LABEL:
778 case PPC::GC_LABEL:
Dale Johannesen375be772010-04-07 19:51:44 +0000779 case PPC::DBG_VALUE:
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000780 return 0;
Hal Finkel5b00cea2012-03-31 14:45:15 +0000781 case PPC::BL8_NOP_ELF:
782 case PPC::BLA8_NOP_ELF:
783 return 8;
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000784 default:
785 return 4; // PowerPC instructions are all 4 bytes
786 }
787}