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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / e3ec87a6f7b718596697727e699a62aed0d40b25 / . / lib / Target / ARM / ARMISelLowering.h
blob: 4c8bd0ece3a9ee50415ef62a5ff4b17c48493e6e [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Craig Topperc1f6f422012-03-17 07:33:42 +0000[diff] [blame]18#include "ARM.h"
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]19#include "ARMSubtarget.h"
Chandler Carrutha1514e22012-12-04 07:12:27 +0000[diff] [blame]20#include "llvm/CodeGen/CallingConvLower.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]21#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]22#include "llvm/CodeGen/SelectionDAG.h"
Chandler Carrutha1514e22012-12-04 07:12:27 +0000[diff] [blame]23#include "llvm/Target/TargetLowering.h"
24#include "llvm/Target/TargetRegisterInfo.h"
Evan Chenge07f85e2012-12-11 23:26:14 +0000[diff] [blame]25#include "llvm/Target/TargetTransformImpl.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]26#include <vector>
27
28namespace llvm {
29 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]30
31 namespace ARMISD {
32 // ARM Specific DAG Nodes
33 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]34 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]35 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]36
37 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
38 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng53519f02011-01-21 18:55:51 +0000[diff] [blame]39 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
40 // DYN mode.
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000[diff] [blame]41 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
42 // PIC mode.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]43 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]44
Manman Ren763a75d2012-06-01 02:44:42 +0000[diff] [blame]45 // Add pseudo op to model memcpy for struct byval.
46 COPY_STRUCT_BYVAL,
47
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]48 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]49 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]50 CALL_NOLINK, // Function call with branch not branch-and-link.
51 tCALL, // Thumb function call.
52 BRCOND, // Conditional branch.
53 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]54 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]55 RET_FLAG, // Return with a flag operand.
56
57 PIC_ADD, // Add with a PC operand and a PIC label.
58
59 CMP, // ARM compare instructions.
Bill Wendlingad5c8802012-06-11 08:07:26 +0000[diff] [blame]60 CMN, // ARM CMN instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]61 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]62 CMPFP, // ARM VFP compare instruction, sets FPSCR.
63 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
64 FMSTAT, // ARM fmstat instruction.
Evan Chengc892aeb2012-02-23 01:19:06 +0000[diff] [blame]65
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]66 CMOV, // ARM conditional move instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]67
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]68 BCC_i64,
69
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]70 RBIT, // ARM bitreverse instruction
71
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]72 FTOSI, // FP to sint within a FP register.
73 FTOUI, // FP to uint within a FP register.
74 SITOF, // sint to FP within a FP register.
75 UITOF, // uint to FP within a FP register.
76
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]77 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
78 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
79 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]80
Evan Cheng342e3162011-08-30 01:34:54 +0000[diff] [blame]81 ADDC, // Add with carry
82 ADDE, // Add using carry
83 SUBC, // Sub with carry
84 SUBE, // Sub using carry
85
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]86 VMOVRRD, // double to two gprs.
87 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]88
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]89 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
90 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]91
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]92 TC_RETURN, // Tail call return pseudo.
93
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]94 THREAD_POINTER,
95
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]96 DYN_ALLOC, // Dynamic allocation on the stack.
97
Bob Wilsonf74a4292010-10-30 00:54:37 +0000[diff] [blame]98 MEMBARRIER, // Memory barrier (DMB)
99 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Chengdfed19f2010-11-03 06:34:55 +0000[diff] [blame]100
101 PRELOAD, // Preload
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]102
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]103 VCEQ, // Vector compare equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]104 VCEQZ, // Vector compare equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]105 VCGE, // Vector compare greater than or equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]106 VCGEZ, // Vector compare greater than or equal to zero.
107 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]108 VCGEU, // Vector compare unsigned greater than or equal.
109 VCGT, // Vector compare greater than.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]110 VCGTZ, // Vector compare greater than zero.
111 VCLTZ, // Vector compare less than zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]112 VCGTU, // Vector compare unsigned greater than.
113 VTST, // Vector test bits.
114
115 // Vector shift by immediate:
116 VSHL, // ...left
117 VSHRs, // ...right (signed)
118 VSHRu, // ...right (unsigned)
119 VSHLLs, // ...left long (signed)
120 VSHLLu, // ...left long (unsigned)
121 VSHLLi, // ...left long (with maximum shift count)
122 VSHRN, // ...right narrow
123
124 // Vector rounding shift by immediate:
125 VRSHRs, // ...right (signed)
126 VRSHRu, // ...right (unsigned)
127 VRSHRN, // ...right narrow
128
129 // Vector saturating shift by immediate:
130 VQSHLs, // ...left (signed)
131 VQSHLu, // ...left (unsigned)
132 VQSHLsu, // ...left (signed to unsigned)
133 VQSHRNs, // ...right narrow (signed)
134 VQSHRNu, // ...right narrow (unsigned)
135 VQSHRNsu, // ...right narrow (signed to unsigned)
136
137 // Vector saturating rounding shift by immediate:
138 VQRSHRNs, // ...right narrow (signed)
139 VQRSHRNu, // ...right narrow (unsigned)
140 VQRSHRNsu, // ...right narrow (signed to unsigned)
141
142 // Vector shift and insert:
143 VSLI, // ...left
144 VSRI, // ...right
145
146 // Vector get lane (VMOV scalar to ARM core register)
147 // (These are used for 8- and 16-bit element types only.)
148 VGETLANEu, // zero-extend vector extract element
149 VGETLANEs, // sign-extend vector extract element
150
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]151 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]152 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]153 VMVNIMM,
154
Evan Chengeaa192a2011-11-15 02:12:34 +0000[diff] [blame]155 // Vector move f32 immediate:
156 VMOVFPIMM,
157
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]158 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]159 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]160 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]161
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]162 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]163 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]164 VREV64, // reverse elements within 64-bit doublewords
165 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]166 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]167 VZIP, // zip (interleave)
168 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]169 VTRN, // transpose
Bill Wendling69a05a72011-03-14 23:02:38 +0000[diff] [blame]170 VTBL1, // 1-register shuffle with mask
171 VTBL2, // 2-register shuffle with mask
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]172
Bob Wilsond0b69cf2010-09-01 23:50:19 +0000[diff] [blame]173 // Vector multiply long:
174 VMULLs, // ...signed
175 VMULLu, // ...unsigned
176
Arnold Schwaighofer67514e92012-09-04 14:37:49 +0000[diff] [blame]177 UMLAL, // 64bit Unsigned Accumulate Multiply
178 SMLAL, // 64bit Signed Accumulate Multiply
179
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]180 // Operands of the standard BUILD_VECTOR node are not legalized, which
181 // is fine if BUILD_VECTORs are always lowered to shuffles or other
182 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
183 // operands need to be legalized. Define an ARM-specific version of
184 // BUILD_VECTOR for this purpose.
185 BUILD_VECTOR,
186
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]187 // Floating-point max and min:
188 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]189 FMIN,
190
191 // Bit-field insert
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]192 BFI,
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]193
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]194 // Vector OR with immediate
Owen Anderson080c0922010-11-05 19:27:46 +0000[diff] [blame]195 VORRIMM,
196 // Vector AND with NOT of immediate
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]197 VBICIMM,
198
Cameron Zwarichc0e6d782011-03-30 23:01:21 +0000[diff] [blame]199 // Vector bitwise select
200 VBSL,
201
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]202 // Vector load N-element structure to all lanes:
203 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
204 VLD3DUP,
Bob Wilson1c3ef902011-02-07 17:43:21 +0000[diff] [blame]205 VLD4DUP,
206
207 // NEON loads with post-increment base updates:
208 VLD1_UPD,
209 VLD2_UPD,
210 VLD3_UPD,
211 VLD4_UPD,
212 VLD2LN_UPD,
213 VLD3LN_UPD,
214 VLD4LN_UPD,
215 VLD2DUP_UPD,
216 VLD3DUP_UPD,
217 VLD4DUP_UPD,
218
219 // NEON stores with post-increment base updates:
220 VST1_UPD,
221 VST2_UPD,
222 VST3_UPD,
223 VST4_UPD,
224 VST2LN_UPD,
225 VST3LN_UPD,
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]226 VST4LN_UPD,
227
228 // 64-bit atomic ops (value split into two registers)
229 ATOMADD64_DAG,
230 ATOMSUB64_DAG,
231 ATOMOR64_DAG,
232 ATOMXOR64_DAG,
233 ATOMAND64_DAG,
234 ATOMNAND64_DAG,
235 ATOMSWAP64_DAG,
Silviu Baranga35b3df62012-11-29 14:41:25 +0000[diff] [blame]236 ATOMCMPXCHG64_DAG,
237 ATOMMIN64_DAG,
238 ATOMUMIN64_DAG,
239 ATOMMAX64_DAG,
240 ATOMUMAX64_DAG
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]241 };
242 }
243
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]244 /// Define some predicates that are used for node matching.
245 namespace ARM {
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]246 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]247 }
248
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]249 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]250 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]251
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]252 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]253 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]254 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]255
Dmitri Gribenko79c07d22012-11-15 16:51:49 +0000[diff] [blame]256 virtual unsigned getJumpTableEncoding() const;
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]257
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]258 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]259
260 /// ReplaceNodeResults - Replace the results of node with an illegal result
261 /// type with new values built out of custom code.
262 ///
263 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]264 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]265
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]266 virtual const char *getTargetNodeName(unsigned Opcode) const;
267
Nadav Rotem9f40cb32012-09-02 12:10:19 +0000[diff] [blame]268 virtual bool isSelectSupported(SelectSupportKind Kind) const {
269 // ARM does not support scalar condition selects on vectors.
270 return (Kind != ScalarCondVectorVal);
271 }
272
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]273 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
274 virtual EVT getSetCCResultType(EVT VT) const;
275
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]276 virtual MachineBasicBlock *
277 EmitInstrWithCustomInserter(MachineInstr *MI,
278 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]279
Evan Cheng37fefc22011-08-30 19:09:48 +0000[diff] [blame]280 virtual void
281 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
282
Evan Chenge721f5c2011-07-13 00:42:17 +0000[diff] [blame]283 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Evan Cheng31959b12011-02-02 01:06:55 +0000[diff] [blame]284 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
285
286 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
287
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]288 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
Evan Cheng376642e2012-12-10 23:21:26 +0000[diff] [blame]289 /// unaligned memory accesses of the specified type. Returns whether it
290 /// is "fast" by reference in the second argument.
291 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]292
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]293 virtual EVT getOptimalMemOpType(uint64_t Size,
294 unsigned DstAlign, unsigned SrcAlign,
Evan Cheng946a3a92012-12-12 02:34:41 +0000[diff] [blame]295 bool IsMemset, bool ZeroMemset,
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]296 bool MemcpyStrSrc,
297 MachineFunction &MF) const;
298
Matt Beaumont-Gayc4e8ddf2012-12-06 23:15:36 +0000[diff] [blame]299 using TargetLowering::isZExtFree;
Evan Cheng2766a472012-12-06 19:13:27 +0000[diff] [blame]300 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
301
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]302 /// isLegalAddressingMode - Return true if the addressing mode represented
303 /// by AM is legal for this target, for a load/store of the specified type.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]304 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]305 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]306
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]307 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]308 /// icmp immediate, that is the target has icmp instructions which can
309 /// compare a register against the immediate without having to materialize
310 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]311 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]312
Dan Gohmancca82142011-05-03 00:46:49 +0000[diff] [blame]313 /// isLegalAddImmediate - Return true if the specified immediate is legal
314 /// add immediate, that is the target has add instructions which can
315 /// add a register and the immediate without having to materialize
316 /// the immediate into a register.
317 virtual bool isLegalAddImmediate(int64_t Imm) const;
318
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]319 /// getPreIndexedAddressParts - returns true by value, base pointer and
320 /// offset pointer and addressing mode by reference if the node's address
321 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]322 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
323 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]324 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]325 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]326
327 /// getPostIndexedAddressParts - returns true by value, base pointer and
328 /// offset pointer and addressing mode by reference if this node can be
329 /// combined with a load / store to form a post-indexed load / store.
330 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]331 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]332 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]333 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]334
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]335 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]336 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]337 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]338 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]339 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]340
341
Evan Cheng55d42002011-01-08 01:24:27 +0000[diff] [blame]342 virtual bool ExpandInlineAsm(CallInst *CI) const;
343
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]344 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]345
346 /// Examine constraint string and operand type and determine a weight value.
347 /// The operand object must already have been set up with the operand type.
348 ConstraintWeight getSingleConstraintMatchWeight(
349 AsmOperandInfo &info, const char *constraint) const;
350
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]351 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]352 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]353 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]354
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]355 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
356 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
357 /// true it means one of the asm constraint of the inline asm instruction
358 /// being processed is 'm'.
359 virtual void LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]360 std::string &Constraint,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]361 std::vector<SDValue> &Ops,
362 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]363
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]364 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]365 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]366 }
367
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]368 /// getRegClassFor - Return the register class that should be used for the
369 /// specified value type.
Patrik Hagglund34525f92012-12-11 11:14:33 +0000[diff] [blame]370 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]371
Anton Korobeynikovcec36f42010-07-24 21:52:08 +0000[diff] [blame]372 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
373 /// be used for loads / stores from the global.
374 virtual unsigned getMaximalGlobalOffset() const;
375
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]376 /// createFastISel - This method returns a target specific FastISel object,
377 /// or null if the target does not support "fast" ISel.
Bob Wilsond49edb72012-08-03 04:06:28 +0000[diff] [blame]378 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
379 const TargetLibraryInfo *libInfo) const;
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]380
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]381 Sched::Preference getSchedulingPreference(SDNode *N) const;
382
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]383 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]384 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]385
386 /// isFPImmLegal - Returns true if the target can instruction select the
387 /// specified FP immediate natively. If false, the legalizer will
388 /// materialize the FP immediate as a load from a constant pool.
389 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
390
Bob Wilson65ffec42010-09-21 17:56:22 +0000[diff] [blame]391 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
392 const CallInst &I,
393 unsigned Intrinsic) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]394 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]395 std::pair<const TargetRegisterClass*, uint8_t>
Patrik Hagglund34525f92012-12-11 11:14:33 +0000[diff] [blame]396 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]397
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]398 private:
399 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
400 /// make the right decision when generating code for different targets.
401 const ARMSubtarget *Subtarget;
402
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]403 const TargetRegisterInfo *RegInfo;
404
Evan Cheng3ef1c872010-09-10 01:29:16 +0000[diff] [blame]405 const InstrItineraryData *Itins;
406
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]407 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]408 ///
409 unsigned ARMPCLabelIndex;
410
Craig Topper0faf46c2012-08-12 03:16:37 +0000[diff] [blame]411 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
412 void addDRTypeForNEON(MVT VT);
413 void addQRTypeForNEON(MVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]414
415 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]416 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]417 SDValue Chain, SDValue &Arg,
418 RegsToPassVector &RegsToPass,
419 CCValAssign &VA, CCValAssign &NextVA,
420 SDValue &StackPtr,
421 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]422 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]423 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]424 SDValue &Root, SelectionDAG &DAG,
425 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]426
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]427 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
428 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]429 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
430 DebugLoc dl, SelectionDAG &DAG,
431 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]432 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]433 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]434 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]435 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]436 const ARMSubtarget *Subtarget) const;
437 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]441 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]442 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]443 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgfd5abd52012-05-04 09:40:39 +0000[diff] [blame]444 SelectionDAG &DAG,
445 TLSModel::Model model) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]446 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
447 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendlingde2b1512010-08-11 08:43:16 +0000[diff] [blame]448 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]449 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
450 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]451 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]452 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]453 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]454 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
455 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemand1fb5832010-08-03 21:31:55 +0000[diff] [blame]456 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hames45b5f882012-03-15 18:49:02 +0000[diff] [blame]457 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
458 const ARMSubtarget *ST) const;
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]459 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson11a1dff2011-01-07 21:37:30 +0000[diff] [blame]460 const ARMSubtarget *ST) const;
461
462 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]463
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]464 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]465 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]466 const SmallVectorImpl<ISD::InputArg> &Ins,
467 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]468 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]469
470 virtual SDValue
471 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]472 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]473 const SmallVectorImpl<ISD::InputArg> &Ins,
474 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]475 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]476
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]477 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
Stepan Dyatkovskiy661afe72012-10-10 11:37:36 +0000[diff] [blame]478 DebugLoc dl, SDValue &Chain,
479 const Value *OrigArg,
480 unsigned OffsetFromOrigArg,
Stepan Dyatkovskiy0d3c8d52012-10-19 08:23:06 +0000[diff] [blame]481 unsigned ArgOffset,
482 bool ForceMutable = false)
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]483 const;
484
485 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
486 unsigned &VARegSize, unsigned &VARegSaveSize) const;
487
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]488 virtual SDValue
Justin Holewinskid2ea0e12012-05-25 16:35:28 +0000[diff] [blame]489 LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]490 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]491
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]492 /// HandleByVal - Target-specific cleanup for ByVal support.
Stepan Dyatkovskiyb52ba9f2012-10-16 07:16:47 +0000[diff] [blame]493 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]494
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]495 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
496 /// for tail call optimization. Targets which want to do tail call
497 /// optimization should implement this function.
498 bool IsEligibleForTailCallOptimization(SDValue Callee,
499 CallingConv::ID CalleeCC,
500 bool isVarArg,
501 bool isCalleeStructRet,
502 bool isCallerStructRet,
503 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]504 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]505 const SmallVectorImpl<ISD::InputArg> &Ins,
506 SelectionDAG& DAG) const;
Benjamin Kramer350c0082012-11-28 20:55:10 +0000[diff] [blame]507
508 virtual bool CanLowerReturn(CallingConv::ID CallConv,
509 MachineFunction &MF, bool isVarArg,
510 const SmallVectorImpl<ISD::OutputArg> &Outs,
511 LLVMContext &Context) const;
512
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]513 virtual SDValue
514 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]515 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]516 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]517 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]518 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]519
Evan Chengbf010eb2012-04-10 01:51:00 +0000[diff] [blame]520 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
Evan Cheng3d2125c2010-11-30 23:55:39 +0000[diff] [blame]521
Evan Cheng485fafc2011-03-21 01:19:09 +0000[diff] [blame]522 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
523
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]524 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]525 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
526 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
527 SelectionDAG &DAG, DebugLoc dl) const;
Bob Wilson79f56c92011-03-08 01:17:20 +0000[diff] [blame]528 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]529
530 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]531
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]532 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
533 MachineBasicBlock *BB,
534 unsigned Size) const;
535 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
536 MachineBasicBlock *BB,
537 unsigned Size,
538 unsigned BinOpcode) const;
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]539 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
540 MachineBasicBlock *BB,
541 unsigned Op1,
542 unsigned Op2,
Eli Friedman4d3f3292011-08-31 17:52:22 +0000[diff] [blame]543 bool NeedsCarry = false,
Silviu Baranga35b3df62012-11-29 14:41:25 +0000[diff] [blame]544 bool IsCmpxchg = false,
545 bool IsMinMax = false,
546 ARMCC::CondCodes CC = ARMCC::AL) const;
Jim Grosbachf7da8822011-04-26 19:44:18 +0000[diff] [blame]547 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
548 MachineBasicBlock *BB,
549 unsigned Size,
550 bool signExtend,
551 ARMCC::CondCodes Cond) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]552
Bill Wendlinge29fa1d2011-10-06 22:18:16 +0000[diff] [blame]553 void SetupEntryBlockForSjLj(MachineInstr *MI,
554 MachineBasicBlock *MBB,
555 MachineBasicBlock *DispatchBB, int FI) const;
556
Bill Wendlingf7e4aef2011-10-03 21:25:38 +0000[diff] [blame]557 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
558 MachineBasicBlock *MBB) const;
559
Andrew Trick1c3af772011-04-23 03:55:32 +0000[diff] [blame]560 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Manman Ren68f25572012-06-01 19:33:18 +0000[diff] [blame]561
562 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
563 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]564 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]565
Owen Anderson36fa3ea2010-11-05 21:57:54 +0000[diff] [blame]566 enum NEONModImmType {
567 VMOVModImm,
568 VMVNModImm,
569 OtherModImm
570 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]571
572
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]573 namespace ARM {
Bob Wilsond49edb72012-08-03 04:06:28 +0000[diff] [blame]574 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
575 const TargetLibraryInfo *libInfo);
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]576 }
Evan Chenge07f85e2012-12-11 23:26:14 +0000[diff] [blame]577
578 class ARMScalarTargetTransformImpl : public ScalarTargetTransformImpl {
579 const ARMSubtarget *Subtarget;
580 public:
581 explicit ARMScalarTargetTransformImpl(const TargetLowering *TL) :
582 ScalarTargetTransformImpl(TL),
583 Subtarget(&TL->getTargetMachine().getSubtarget<ARMSubtarget>()) {};
584
585 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
586 };
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]587}
588
589#endif // ARMISELLOWERING_H