Jim Grosbach | 31c24bf | 2009-11-07 22:00:39 +0000 | [diff] [blame] | 1 | //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===// |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the Base ARM implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARMBaseInstrInfo.h" |
| 15 | #include "ARM.h" |
| 16 | #include "ARMAddressingModes.h" |
Evan Cheng | d457e6e | 2009-11-07 04:04:34 +0000 | [diff] [blame] | 17 | #include "ARMConstantPoolValue.h" |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 18 | #include "ARMMachineFunctionInfo.h" |
Anton Korobeynikov | f95215f | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 19 | #include "ARMRegisterInfo.h" |
Chris Lattner | 4dbbe34 | 2010-07-20 21:17:29 +0000 | [diff] [blame] | 20 | #include "ARMGenInstrInfo.inc" |
Evan Cheng | fdc8340 | 2009-11-08 00:15:23 +0000 | [diff] [blame] | 21 | #include "llvm/Constants.h" |
| 22 | #include "llvm/Function.h" |
| 23 | #include "llvm/GlobalValue.h" |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 24 | #include "llvm/ADT/STLExtras.h" |
| 25 | #include "llvm/CodeGen/LiveVariables.h" |
Evan Cheng | d457e6e | 2009-11-07 04:04:34 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineConstantPool.h" |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 27 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 28 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 29 | #include "llvm/CodeGen/MachineJumpTableInfo.h" |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 30 | #include "llvm/CodeGen/MachineMemOperand.h" |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 31 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 32 | #include "llvm/CodeGen/PseudoSourceValue.h" |
Chris Lattner | af76e59 | 2009-08-22 20:48:53 +0000 | [diff] [blame] | 33 | #include "llvm/MC/MCAsmInfo.h" |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 34 | #include "llvm/Support/CommandLine.h" |
Anton Korobeynikov | f95215f | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 35 | #include "llvm/Support/Debug.h" |
Torok Edwin | c25e758 | 2009-07-11 20:10:48 +0000 | [diff] [blame] | 36 | #include "llvm/Support/ErrorHandling.h" |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 37 | using namespace llvm; |
| 38 | |
| 39 | static cl::opt<bool> |
| 40 | EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, |
| 41 | cl::desc("Enable ARM 2-addr to 3-addr conv")); |
| 42 | |
Owen Anderson | b3c04ec | 2010-09-30 23:48:38 +0000 | [diff] [blame] | 43 | static cl::opt<bool> |
Owen Anderson | 00d4f48 | 2010-10-01 20:33:47 +0000 | [diff] [blame] | 44 | OldARMIfCvt("old-arm-ifcvt", cl::Hidden, |
Owen Anderson | b3c04ec | 2010-09-30 23:48:38 +0000 | [diff] [blame] | 45 | cl::desc("Use old-style ARM if-conversion heuristics")); |
| 46 | |
Anton Korobeynikov | f95215f | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 47 | ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) |
| 48 | : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), |
| 49 | Subtarget(STI) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 50 | } |
| 51 | |
| 52 | MachineInstr * |
| 53 | ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, |
| 54 | MachineBasicBlock::iterator &MBBI, |
| 55 | LiveVariables *LV) const { |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 56 | // FIXME: Thumb2 support. |
| 57 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 58 | if (!EnableARM3Addr) |
| 59 | return NULL; |
| 60 | |
| 61 | MachineInstr *MI = MBBI; |
| 62 | MachineFunction &MF = *MI->getParent()->getParent(); |
Bruno Cardoso Lopes | 99405df | 2010-06-08 22:51:23 +0000 | [diff] [blame] | 63 | uint64_t TSFlags = MI->getDesc().TSFlags; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 64 | bool isPre = false; |
| 65 | switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { |
| 66 | default: return NULL; |
| 67 | case ARMII::IndexModePre: |
| 68 | isPre = true; |
| 69 | break; |
| 70 | case ARMII::IndexModePost: |
| 71 | break; |
| 72 | } |
| 73 | |
| 74 | // Try splitting an indexed load/store to an un-indexed one plus an add/sub |
| 75 | // operation. |
| 76 | unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); |
| 77 | if (MemOpc == 0) |
| 78 | return NULL; |
| 79 | |
| 80 | MachineInstr *UpdateMI = NULL; |
| 81 | MachineInstr *MemMI = NULL; |
| 82 | unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); |
| 83 | const TargetInstrDesc &TID = MI->getDesc(); |
| 84 | unsigned NumOps = TID.getNumOperands(); |
| 85 | bool isLoad = !TID.mayStore(); |
| 86 | const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); |
| 87 | const MachineOperand &Base = MI->getOperand(2); |
| 88 | const MachineOperand &Offset = MI->getOperand(NumOps-3); |
| 89 | unsigned WBReg = WB.getReg(); |
| 90 | unsigned BaseReg = Base.getReg(); |
| 91 | unsigned OffReg = Offset.getReg(); |
| 92 | unsigned OffImm = MI->getOperand(NumOps-2).getImm(); |
| 93 | ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); |
| 94 | switch (AddrMode) { |
| 95 | default: |
| 96 | assert(false && "Unknown indexed op!"); |
| 97 | return NULL; |
| 98 | case ARMII::AddrMode2: { |
| 99 | bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; |
| 100 | unsigned Amt = ARM_AM::getAM2Offset(OffImm); |
| 101 | if (OffReg == 0) { |
Evan Cheng | e7cbe41 | 2009-07-08 21:03:57 +0000 | [diff] [blame] | 102 | if (ARM_AM::getSOImmVal(Amt) == -1) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 103 | // Can't encode it in a so_imm operand. This transformation will |
| 104 | // add more than 1 instruction. Abandon! |
| 105 | return NULL; |
| 106 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 107 | get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) |
Evan Cheng | e7cbe41 | 2009-07-08 21:03:57 +0000 | [diff] [blame] | 108 | .addReg(BaseReg).addImm(Amt) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 109 | .addImm(Pred).addReg(0).addReg(0); |
| 110 | } else if (Amt != 0) { |
| 111 | ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); |
| 112 | unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); |
| 113 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 114 | get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 115 | .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) |
| 116 | .addImm(Pred).addReg(0).addReg(0); |
| 117 | } else |
| 118 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 119 | get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 120 | .addReg(BaseReg).addReg(OffReg) |
| 121 | .addImm(Pred).addReg(0).addReg(0); |
| 122 | break; |
| 123 | } |
| 124 | case ARMII::AddrMode3 : { |
| 125 | bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; |
| 126 | unsigned Amt = ARM_AM::getAM3Offset(OffImm); |
| 127 | if (OffReg == 0) |
| 128 | // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. |
| 129 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 130 | get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 131 | .addReg(BaseReg).addImm(Amt) |
| 132 | .addImm(Pred).addReg(0).addReg(0); |
| 133 | else |
| 134 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 135 | get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 136 | .addReg(BaseReg).addReg(OffReg) |
| 137 | .addImm(Pred).addReg(0).addReg(0); |
| 138 | break; |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | std::vector<MachineInstr*> NewMIs; |
| 143 | if (isPre) { |
| 144 | if (isLoad) |
| 145 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 146 | get(MemOpc), MI->getOperand(0).getReg()) |
| 147 | .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); |
| 148 | else |
| 149 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 150 | get(MemOpc)).addReg(MI->getOperand(1).getReg()) |
| 151 | .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); |
| 152 | NewMIs.push_back(MemMI); |
| 153 | NewMIs.push_back(UpdateMI); |
| 154 | } else { |
| 155 | if (isLoad) |
| 156 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 157 | get(MemOpc), MI->getOperand(0).getReg()) |
| 158 | .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); |
| 159 | else |
| 160 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 161 | get(MemOpc)).addReg(MI->getOperand(1).getReg()) |
| 162 | .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); |
| 163 | if (WB.isDead()) |
| 164 | UpdateMI->getOperand(0).setIsDead(); |
| 165 | NewMIs.push_back(UpdateMI); |
| 166 | NewMIs.push_back(MemMI); |
| 167 | } |
| 168 | |
| 169 | // Transfer LiveVariables states, kill / dead info. |
| 170 | if (LV) { |
| 171 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 172 | MachineOperand &MO = MI->getOperand(i); |
| 173 | if (MO.isReg() && MO.getReg() && |
| 174 | TargetRegisterInfo::isVirtualRegister(MO.getReg())) { |
| 175 | unsigned Reg = MO.getReg(); |
| 176 | |
| 177 | LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); |
| 178 | if (MO.isDef()) { |
| 179 | MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; |
| 180 | if (MO.isDead()) |
| 181 | LV->addVirtualRegisterDead(Reg, NewMI); |
| 182 | } |
| 183 | if (MO.isUse() && MO.isKill()) { |
| 184 | for (unsigned j = 0; j < 2; ++j) { |
| 185 | // Look at the two new MI's in reverse order. |
| 186 | MachineInstr *NewMI = NewMIs[j]; |
| 187 | if (!NewMI->readsRegister(Reg)) |
| 188 | continue; |
| 189 | LV->addVirtualRegisterKilled(Reg, NewMI); |
| 190 | if (VI.removeKill(MI)) |
| 191 | VI.Kills.push_back(NewMI); |
| 192 | break; |
| 193 | } |
| 194 | } |
| 195 | } |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | MFI->insert(MBBI, NewMIs[1]); |
| 200 | MFI->insert(MBBI, NewMIs[0]); |
| 201 | return NewMIs[0]; |
| 202 | } |
| 203 | |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 204 | bool |
| 205 | ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
Jim Grosbach | 18f30e6 | 2010-06-02 21:53:11 +0000 | [diff] [blame] | 206 | MachineBasicBlock::iterator MI, |
| 207 | const std::vector<CalleeSavedInfo> &CSI, |
| 208 | const TargetRegisterInfo *TRI) const { |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 209 | if (CSI.empty()) |
| 210 | return false; |
| 211 | |
| 212 | DebugLoc DL; |
| 213 | if (MI != MBB.end()) DL = MI->getDebugLoc(); |
| 214 | |
| 215 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 216 | unsigned Reg = CSI[i].getReg(); |
| 217 | bool isKill = true; |
| 218 | |
| 219 | // Add the callee-saved register as live-in unless it's LR and |
| 220 | // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress |
| 221 | // then it's already added to the function and entry block live-in sets. |
| 222 | if (Reg == ARM::LR) { |
| 223 | MachineFunction &MF = *MBB.getParent(); |
| 224 | if (MF.getFrameInfo()->isReturnAddressTaken() && |
| 225 | MF.getRegInfo().isLiveIn(Reg)) |
| 226 | isKill = false; |
| 227 | } |
| 228 | |
| 229 | if (isKill) |
| 230 | MBB.addLiveIn(Reg); |
| 231 | |
| 232 | // Insert the spill to the stack frame. The register is killed at the spill |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 233 | // |
Rafael Espindola | 42d075c | 2010-06-02 20:02:30 +0000 | [diff] [blame] | 234 | const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 235 | storeRegToStackSlot(MBB, MI, Reg, isKill, |
Rafael Espindola | 42d075c | 2010-06-02 20:02:30 +0000 | [diff] [blame] | 236 | CSI[i].getFrameIdx(), RC, TRI); |
Evan Cheng | 2457f2c | 2010-05-22 01:47:14 +0000 | [diff] [blame] | 237 | } |
| 238 | return true; |
| 239 | } |
| 240 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 241 | // Branch analysis. |
| 242 | bool |
| 243 | ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, |
| 244 | MachineBasicBlock *&FBB, |
| 245 | SmallVectorImpl<MachineOperand> &Cond, |
| 246 | bool AllowModify) const { |
| 247 | // If the block has no terminators, it just falls into the block after it. |
| 248 | MachineBasicBlock::iterator I = MBB.end(); |
Dale Johannesen | 93d6a7e | 2010-04-02 01:38:09 +0000 | [diff] [blame] | 249 | if (I == MBB.begin()) |
| 250 | return false; |
| 251 | --I; |
| 252 | while (I->isDebugValue()) { |
| 253 | if (I == MBB.begin()) |
| 254 | return false; |
| 255 | --I; |
| 256 | } |
| 257 | if (!isUnpredicatedTerminator(I)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 258 | return false; |
| 259 | |
| 260 | // Get the last instruction in the block. |
| 261 | MachineInstr *LastInst = I; |
| 262 | |
| 263 | // If there is only one terminator instruction, process it. |
| 264 | unsigned LastOpc = LastInst->getOpcode(); |
| 265 | if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 266 | if (isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 267 | TBB = LastInst->getOperand(0).getMBB(); |
| 268 | return false; |
| 269 | } |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 270 | if (isCondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 271 | // Block ends with fall-through condbranch. |
| 272 | TBB = LastInst->getOperand(0).getMBB(); |
| 273 | Cond.push_back(LastInst->getOperand(1)); |
| 274 | Cond.push_back(LastInst->getOperand(2)); |
| 275 | return false; |
| 276 | } |
| 277 | return true; // Can't handle indirect branch. |
| 278 | } |
| 279 | |
| 280 | // Get the instruction before it if it is a terminator. |
| 281 | MachineInstr *SecondLastInst = I; |
Evan Cheng | 108c872 | 2010-09-23 06:54:40 +0000 | [diff] [blame] | 282 | unsigned SecondLastOpc = SecondLastInst->getOpcode(); |
| 283 | |
| 284 | // If AllowModify is true and the block ends with two or more unconditional |
| 285 | // branches, delete all but the first unconditional branch. |
| 286 | if (AllowModify && isUncondBranchOpcode(LastOpc)) { |
| 287 | while (isUncondBranchOpcode(SecondLastOpc)) { |
| 288 | LastInst->eraseFromParent(); |
| 289 | LastInst = SecondLastInst; |
| 290 | LastOpc = LastInst->getOpcode(); |
Evan Cheng | 676e258 | 2010-09-23 19:42:03 +0000 | [diff] [blame] | 291 | if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { |
| 292 | // Return now the only terminator is an unconditional branch. |
| 293 | TBB = LastInst->getOperand(0).getMBB(); |
| 294 | return false; |
| 295 | } else { |
Evan Cheng | 108c872 | 2010-09-23 06:54:40 +0000 | [diff] [blame] | 296 | SecondLastInst = I; |
| 297 | SecondLastOpc = SecondLastInst->getOpcode(); |
| 298 | } |
| 299 | } |
| 300 | } |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 301 | |
| 302 | // If there are three terminators, we don't know what sort of block this is. |
| 303 | if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) |
| 304 | return true; |
| 305 | |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 306 | // If the block ends with a B and a Bcc, handle it. |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 307 | if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 308 | TBB = SecondLastInst->getOperand(0).getMBB(); |
| 309 | Cond.push_back(SecondLastInst->getOperand(1)); |
| 310 | Cond.push_back(SecondLastInst->getOperand(2)); |
| 311 | FBB = LastInst->getOperand(0).getMBB(); |
| 312 | return false; |
| 313 | } |
| 314 | |
| 315 | // If the block ends with two unconditional branches, handle it. The second |
| 316 | // one is not executed, so remove it. |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 317 | if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 318 | TBB = SecondLastInst->getOperand(0).getMBB(); |
| 319 | I = LastInst; |
| 320 | if (AllowModify) |
| 321 | I->eraseFromParent(); |
| 322 | return false; |
| 323 | } |
| 324 | |
| 325 | // ...likewise if it ends with a branch table followed by an unconditional |
| 326 | // branch. The branch folder can create these, and we must get rid of them for |
| 327 | // correctness of Thumb constant islands. |
Bob Wilson | 8d4de5a | 2009-10-28 18:26:41 +0000 | [diff] [blame] | 328 | if ((isJumpTableBranchOpcode(SecondLastOpc) || |
| 329 | isIndirectBranchOpcode(SecondLastOpc)) && |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 330 | isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 331 | I = LastInst; |
| 332 | if (AllowModify) |
| 333 | I->eraseFromParent(); |
| 334 | return true; |
| 335 | } |
| 336 | |
| 337 | // Otherwise, can't handle this. |
| 338 | return true; |
| 339 | } |
| 340 | |
| 341 | |
| 342 | unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 343 | MachineBasicBlock::iterator I = MBB.end(); |
| 344 | if (I == MBB.begin()) return 0; |
| 345 | --I; |
Dale Johannesen | 93d6a7e | 2010-04-02 01:38:09 +0000 | [diff] [blame] | 346 | while (I->isDebugValue()) { |
| 347 | if (I == MBB.begin()) |
| 348 | return 0; |
| 349 | --I; |
| 350 | } |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 351 | if (!isUncondBranchOpcode(I->getOpcode()) && |
| 352 | !isCondBranchOpcode(I->getOpcode())) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 353 | return 0; |
| 354 | |
| 355 | // Remove the branch. |
| 356 | I->eraseFromParent(); |
| 357 | |
| 358 | I = MBB.end(); |
| 359 | |
| 360 | if (I == MBB.begin()) return 1; |
| 361 | --I; |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 362 | if (!isCondBranchOpcode(I->getOpcode())) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 363 | return 1; |
| 364 | |
| 365 | // Remove the branch. |
| 366 | I->eraseFromParent(); |
| 367 | return 2; |
| 368 | } |
| 369 | |
| 370 | unsigned |
| 371 | ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
Stuart Hastings | 3bf9125 | 2010-06-17 22:43:56 +0000 | [diff] [blame] | 372 | MachineBasicBlock *FBB, |
| 373 | const SmallVectorImpl<MachineOperand> &Cond, |
| 374 | DebugLoc DL) const { |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 375 | ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); |
| 376 | int BOpc = !AFI->isThumbFunction() |
| 377 | ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); |
| 378 | int BccOpc = !AFI->isThumbFunction() |
| 379 | ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 380 | |
| 381 | // Shouldn't be a fall through. |
| 382 | assert(TBB && "InsertBranch must not be told to insert a fallthrough"); |
| 383 | assert((Cond.size() == 2 || Cond.size() == 0) && |
| 384 | "ARM branch conditions have two components!"); |
| 385 | |
| 386 | if (FBB == 0) { |
| 387 | if (Cond.empty()) // Unconditional branch? |
Stuart Hastings | 3bf9125 | 2010-06-17 22:43:56 +0000 | [diff] [blame] | 388 | BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 389 | else |
Stuart Hastings | 3bf9125 | 2010-06-17 22:43:56 +0000 | [diff] [blame] | 390 | BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 391 | .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); |
| 392 | return 1; |
| 393 | } |
| 394 | |
| 395 | // Two-way conditional branch. |
Stuart Hastings | 3bf9125 | 2010-06-17 22:43:56 +0000 | [diff] [blame] | 396 | BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 397 | .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); |
Stuart Hastings | 3bf9125 | 2010-06-17 22:43:56 +0000 | [diff] [blame] | 398 | BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 399 | return 2; |
| 400 | } |
| 401 | |
| 402 | bool ARMBaseInstrInfo:: |
| 403 | ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { |
| 404 | ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); |
| 405 | Cond[0].setImm(ARMCC::getOppositeCondition(CC)); |
| 406 | return false; |
| 407 | } |
| 408 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 409 | bool ARMBaseInstrInfo:: |
| 410 | PredicateInstruction(MachineInstr *MI, |
| 411 | const SmallVectorImpl<MachineOperand> &Pred) const { |
| 412 | unsigned Opc = MI->getOpcode(); |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 413 | if (isUncondBranchOpcode(Opc)) { |
| 414 | MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 415 | MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); |
| 416 | MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); |
| 417 | return true; |
| 418 | } |
| 419 | |
| 420 | int PIdx = MI->findFirstPredOperandIdx(); |
| 421 | if (PIdx != -1) { |
| 422 | MachineOperand &PMO = MI->getOperand(PIdx); |
| 423 | PMO.setImm(Pred[0].getImm()); |
| 424 | MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); |
| 425 | return true; |
| 426 | } |
| 427 | return false; |
| 428 | } |
| 429 | |
| 430 | bool ARMBaseInstrInfo:: |
| 431 | SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, |
| 432 | const SmallVectorImpl<MachineOperand> &Pred2) const { |
| 433 | if (Pred1.size() > 2 || Pred2.size() > 2) |
| 434 | return false; |
| 435 | |
| 436 | ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); |
| 437 | ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); |
| 438 | if (CC1 == CC2) |
| 439 | return true; |
| 440 | |
| 441 | switch (CC1) { |
| 442 | default: |
| 443 | return false; |
| 444 | case ARMCC::AL: |
| 445 | return true; |
| 446 | case ARMCC::HS: |
| 447 | return CC2 == ARMCC::HI; |
| 448 | case ARMCC::LS: |
| 449 | return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; |
| 450 | case ARMCC::GE: |
| 451 | return CC2 == ARMCC::GT; |
| 452 | case ARMCC::LE: |
| 453 | return CC2 == ARMCC::LT; |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, |
| 458 | std::vector<MachineOperand> &Pred) const { |
Evan Cheng | 8fb9036 | 2009-08-08 03:20:32 +0000 | [diff] [blame] | 459 | // FIXME: This confuses implicit_def with optional CPSR def. |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 460 | const TargetInstrDesc &TID = MI->getDesc(); |
| 461 | if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) |
| 462 | return false; |
| 463 | |
| 464 | bool Found = false; |
| 465 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 466 | const MachineOperand &MO = MI->getOperand(i); |
| 467 | if (MO.isReg() && MO.getReg() == ARM::CPSR) { |
| 468 | Pred.push_back(MO); |
| 469 | Found = true; |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | return Found; |
| 474 | } |
| 475 | |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 476 | /// isPredicable - Return true if the specified instruction can be predicated. |
| 477 | /// By default, this returns true for every instruction with a |
| 478 | /// PredicateOperand. |
| 479 | bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { |
| 480 | const TargetInstrDesc &TID = MI->getDesc(); |
| 481 | if (!TID.isPredicable()) |
| 482 | return false; |
| 483 | |
| 484 | if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { |
| 485 | ARMFunctionInfo *AFI = |
| 486 | MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); |
Evan Cheng | d7f0810 | 2009-11-24 08:06:15 +0000 | [diff] [blame] | 487 | return AFI->isThumb2Function(); |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 488 | } |
| 489 | return true; |
| 490 | } |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 491 | |
Chris Lattner | 56856b1 | 2009-12-03 06:58:32 +0000 | [diff] [blame] | 492 | /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. |
| 493 | DISABLE_INLINE |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 494 | static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, |
Chris Lattner | 56856b1 | 2009-12-03 06:58:32 +0000 | [diff] [blame] | 495 | unsigned JTI); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 496 | static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, |
| 497 | unsigned JTI) { |
Chris Lattner | 56856b1 | 2009-12-03 06:58:32 +0000 | [diff] [blame] | 498 | assert(JTI < JT.size()); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 499 | return JT[JTI].MBBs.size(); |
| 500 | } |
| 501 | |
| 502 | /// GetInstSize - Return the size of the specified MachineInstr. |
| 503 | /// |
| 504 | unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { |
| 505 | const MachineBasicBlock &MBB = *MI->getParent(); |
| 506 | const MachineFunction *MF = MBB.getParent(); |
Chris Lattner | 33adcfb | 2009-08-22 21:43:10 +0000 | [diff] [blame] | 507 | const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 508 | |
| 509 | // Basic size info comes from the TSFlags field. |
| 510 | const TargetInstrDesc &TID = MI->getDesc(); |
Bruno Cardoso Lopes | 99405df | 2010-06-08 22:51:23 +0000 | [diff] [blame] | 511 | uint64_t TSFlags = TID.TSFlags; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 512 | |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 513 | unsigned Opc = MI->getOpcode(); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 514 | switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { |
| 515 | default: { |
| 516 | // If this machine instr is an inline asm, measure it. |
| 517 | if (MI->getOpcode() == ARM::INLINEASM) |
Chris Lattner | 33adcfb | 2009-08-22 21:43:10 +0000 | [diff] [blame] | 518 | return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 519 | if (MI->isLabel()) |
| 520 | return 0; |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 521 | switch (Opc) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 522 | default: |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 523 | llvm_unreachable("Unknown or unset size field for instr!"); |
Chris Lattner | 518bb53 | 2010-02-09 19:54:29 +0000 | [diff] [blame] | 524 | case TargetOpcode::IMPLICIT_DEF: |
| 525 | case TargetOpcode::KILL: |
Bill Wendling | 7431bea | 2010-07-16 22:20:36 +0000 | [diff] [blame] | 526 | case TargetOpcode::PROLOG_LABEL: |
Chris Lattner | 518bb53 | 2010-02-09 19:54:29 +0000 | [diff] [blame] | 527 | case TargetOpcode::EH_LABEL: |
Dale Johannesen | 375be77 | 2010-04-07 19:51:44 +0000 | [diff] [blame] | 528 | case TargetOpcode::DBG_VALUE: |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 529 | return 0; |
| 530 | } |
| 531 | break; |
| 532 | } |
Evan Cheng | 7894762 | 2009-07-24 18:20:44 +0000 | [diff] [blame] | 533 | case ARMII::Size8Bytes: return 8; // ARM instruction x 2. |
| 534 | case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. |
| 535 | case ARMII::Size2Bytes: return 2; // Thumb1 instruction. |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 536 | case ARMII::SizeSpecial: { |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 537 | switch (Opc) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 538 | case ARM::CONSTPOOL_ENTRY: |
| 539 | // If this machine instr is a constant pool entry, its size is recorded as |
| 540 | // operand #2. |
| 541 | return MI->getOperand(2).getImm(); |
Jim Grosbach | 5eb1951 | 2010-05-22 01:06:18 +0000 | [diff] [blame] | 542 | case ARM::Int_eh_sjlj_longjmp: |
| 543 | return 16; |
| 544 | case ARM::tInt_eh_sjlj_longjmp: |
| 545 | return 10; |
Evan Cheng | 7894762 | 2009-07-24 18:20:44 +0000 | [diff] [blame] | 546 | case ARM::Int_eh_sjlj_setjmp: |
Jim Grosbach | d100755 | 2010-04-28 20:33:09 +0000 | [diff] [blame] | 547 | case ARM::Int_eh_sjlj_setjmp_nofp: |
Jim Grosbach | 0798edd | 2010-05-27 23:49:24 +0000 | [diff] [blame] | 548 | return 20; |
Jim Grosbach | d122874 | 2009-12-01 18:10:36 +0000 | [diff] [blame] | 549 | case ARM::tInt_eh_sjlj_setjmp: |
Jim Grosbach | 5aa1684 | 2009-08-11 19:42:21 +0000 | [diff] [blame] | 550 | case ARM::t2Int_eh_sjlj_setjmp: |
Jim Grosbach | d100755 | 2010-04-28 20:33:09 +0000 | [diff] [blame] | 551 | case ARM::t2Int_eh_sjlj_setjmp_nofp: |
Jim Grosbach | 0798edd | 2010-05-27 23:49:24 +0000 | [diff] [blame] | 552 | return 12; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 553 | case ARM::BR_JTr: |
| 554 | case ARM::BR_JTm: |
| 555 | case ARM::BR_JTadd: |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 556 | case ARM::tBR_JTr: |
Evan Cheng | d26b14c | 2009-07-31 18:28:05 +0000 | [diff] [blame] | 557 | case ARM::t2BR_JT: |
| 558 | case ARM::t2TBB: |
| 559 | case ARM::t2TBH: { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 560 | // These are jumptable branches, i.e. a branch followed by an inlined |
Evan Cheng | d26b14c | 2009-07-31 18:28:05 +0000 | [diff] [blame] | 561 | // jumptable. The size is 4 + 4 * number of entries. For TBB, each |
| 562 | // entry is one byte; TBH two byte each. |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 563 | unsigned EntrySize = (Opc == ARM::t2TBB) |
| 564 | ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 565 | unsigned NumOps = TID.getNumOperands(); |
| 566 | MachineOperand JTOP = |
| 567 | MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); |
| 568 | unsigned JTI = JTOP.getIndex(); |
| 569 | const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); |
Chris Lattner | b1e8039 | 2010-01-25 23:22:00 +0000 | [diff] [blame] | 570 | assert(MJTI != 0); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 571 | const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); |
| 572 | assert(JTI < JT.size()); |
| 573 | // Thumb instructions are 2 byte aligned, but JT entries are 4 byte |
| 574 | // 4 aligned. The assembler / linker may add 2 byte padding just before |
| 575 | // the JT entries. The size does not include this padding; the |
| 576 | // constant islands pass does separate bookkeeping for it. |
| 577 | // FIXME: If we know the size of the function is less than (1 << 16) *2 |
| 578 | // bytes, we can use 16-bit entries instead. Then there won't be an |
| 579 | // alignment issue. |
Evan Cheng | 25f7cfc | 2009-08-01 06:13:52 +0000 | [diff] [blame] | 580 | unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; |
| 581 | unsigned NumEntries = getNumJTEntries(JT, JTI); |
| 582 | if (Opc == ARM::t2TBB && (NumEntries & 1)) |
| 583 | // Make sure the instruction that follows TBB is 2-byte aligned. |
| 584 | // FIXME: Constant island pass should insert an "ALIGN" instruction |
| 585 | // instead. |
| 586 | ++NumEntries; |
| 587 | return NumEntries * EntrySize + InstSize; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 588 | } |
| 589 | default: |
| 590 | // Otherwise, pseudo-instruction sizes are zero. |
| 591 | return 0; |
| 592 | } |
| 593 | } |
| 594 | } |
| 595 | return 0; // Not reached |
| 596 | } |
| 597 | |
Jakob Stoklund Olesen | ac27366 | 2010-07-11 06:33:54 +0000 | [diff] [blame] | 598 | void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, |
| 599 | MachineBasicBlock::iterator I, DebugLoc DL, |
| 600 | unsigned DestReg, unsigned SrcReg, |
| 601 | bool KillSrc) const { |
| 602 | bool GPRDest = ARM::GPRRegClass.contains(DestReg); |
| 603 | bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); |
Bob Wilson | 1665b0a | 2010-02-16 17:24:15 +0000 | [diff] [blame] | 604 | |
Jakob Stoklund Olesen | ac27366 | 2010-07-11 06:33:54 +0000 | [diff] [blame] | 605 | if (GPRDest && GPRSrc) { |
| 606 | AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) |
| 607 | .addReg(SrcReg, getKillRegState(KillSrc)))); |
| 608 | return; |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 609 | } |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 610 | |
Jakob Stoklund Olesen | ac27366 | 2010-07-11 06:33:54 +0000 | [diff] [blame] | 611 | bool SPRDest = ARM::SPRRegClass.contains(DestReg); |
| 612 | bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); |
| 613 | |
| 614 | unsigned Opc; |
| 615 | if (SPRDest && SPRSrc) |
| 616 | Opc = ARM::VMOVS; |
| 617 | else if (GPRDest && SPRSrc) |
| 618 | Opc = ARM::VMOVRS; |
| 619 | else if (SPRDest && GPRSrc) |
| 620 | Opc = ARM::VMOVSR; |
| 621 | else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) |
| 622 | Opc = ARM::VMOVD; |
| 623 | else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) |
| 624 | Opc = ARM::VMOVQ; |
| 625 | else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) |
| 626 | Opc = ARM::VMOVQQ; |
| 627 | else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) |
| 628 | Opc = ARM::VMOVQQQQ; |
| 629 | else |
| 630 | llvm_unreachable("Impossible reg-to-reg copy"); |
| 631 | |
| 632 | MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); |
| 633 | MIB.addReg(SrcReg, getKillRegState(KillSrc)); |
| 634 | if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) |
| 635 | AddDefaultPred(MIB); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 636 | } |
| 637 | |
Evan Cheng | c10b5af | 2010-05-07 00:24:52 +0000 | [diff] [blame] | 638 | static const |
| 639 | MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, |
| 640 | unsigned Reg, unsigned SubIdx, unsigned State, |
| 641 | const TargetRegisterInfo *TRI) { |
| 642 | if (!SubIdx) |
| 643 | return MIB.addReg(Reg, State); |
| 644 | |
| 645 | if (TargetRegisterInfo::isPhysicalRegister(Reg)) |
| 646 | return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); |
| 647 | return MIB.addReg(Reg, State, SubIdx); |
| 648 | } |
| 649 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 650 | void ARMBaseInstrInfo:: |
| 651 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 652 | unsigned SrcReg, bool isKill, int FI, |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 653 | const TargetRegisterClass *RC, |
| 654 | const TargetRegisterInfo *TRI) const { |
Chris Lattner | c7f3ace | 2010-04-02 20:16:16 +0000 | [diff] [blame] | 655 | DebugLoc DL; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 656 | if (I != MBB.end()) DL = I->getDebugLoc(); |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 657 | MachineFunction &MF = *MBB.getParent(); |
| 658 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 659 | unsigned Align = MFI.getObjectAlignment(FI); |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 660 | |
| 661 | MachineMemOperand *MMO = |
Chris Lattner | 59db549 | 2010-09-21 04:39:43 +0000 | [diff] [blame] | 662 | MF.getMachineMemOperand(MachinePointerInfo( |
| 663 | PseudoSourceValue::getFixedStack(FI)), |
| 664 | MachineMemOperand::MOStore, |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 665 | MFI.getObjectSize(FI), |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 666 | Align); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 667 | |
Bob Wilson | 0eb0c74 | 2010-02-16 22:01:59 +0000 | [diff] [blame] | 668 | // tGPR is used sometimes in ARM instructions that need to avoid using |
Jim Grosbach | 6ccfc50 | 2010-07-30 02:41:01 +0000 | [diff] [blame] | 669 | // certain registers. Just treat it as GPR here. Likewise, rGPR. |
| 670 | if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass |
| 671 | || RC == ARM::rGPRRegisterClass) |
Bob Wilson | 0eb0c74 | 2010-02-16 22:01:59 +0000 | [diff] [blame] | 672 | RC = ARM::GPRRegisterClass; |
| 673 | |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 674 | switch (RC->getID()) { |
| 675 | case ARM::GPRRegClassID: |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 676 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 677 | .addReg(SrcReg, getKillRegState(isKill)) |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 678 | .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 679 | break; |
| 680 | case ARM::SPRRegClassID: |
Evan Cheng | d31c549 | 2010-05-06 01:34:11 +0000 | [diff] [blame] | 681 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) |
| 682 | .addReg(SrcReg, getKillRegState(isKill)) |
| 683 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 684 | break; |
| 685 | case ARM::DPRRegClassID: |
| 686 | case ARM::DPR_VFP2RegClassID: |
| 687 | case ARM::DPR_8RegClassID: |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 688 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 689 | .addReg(SrcReg, getKillRegState(isKill)) |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 690 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 691 | break; |
| 692 | case ARM::QPRRegClassID: |
| 693 | case ARM::QPR_VFP2RegClassID: |
| 694 | case ARM::QPR_8RegClassID: |
Jim Grosbach | 0cfcf93 | 2010-09-08 00:26:59 +0000 | [diff] [blame] | 695 | if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { |
Bob Wilson | 168f382 | 2010-09-15 01:48:05 +0000 | [diff] [blame] | 696 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) |
Bob Wilson | f967ca0 | 2010-07-06 21:26:18 +0000 | [diff] [blame] | 697 | .addFrameIndex(FI).addImm(16) |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 698 | .addReg(SrcReg, getKillRegState(isKill)) |
| 699 | .addMemOperand(MMO)); |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 700 | } else { |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 701 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) |
| 702 | .addReg(SrcReg, getKillRegState(isKill)) |
| 703 | .addFrameIndex(FI) |
Bob Wilson | d4bfd54 | 2010-08-27 23:18:17 +0000 | [diff] [blame] | 704 | .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 705 | .addMemOperand(MMO)); |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 706 | } |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 707 | break; |
| 708 | case ARM::QQPRRegClassID: |
| 709 | case ARM::QQPR_VFP2RegClassID: |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 710 | if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 711 | // FIXME: It's possible to only store part of the QQ register if the |
| 712 | // spilled def has a sub-register index. |
Bob Wilson | 168f382 | 2010-09-15 01:48:05 +0000 | [diff] [blame] | 713 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) |
| 714 | .addFrameIndex(FI).addImm(16) |
| 715 | .addReg(SrcReg, getKillRegState(isKill)) |
| 716 | .addMemOperand(MMO)); |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 717 | } else { |
| 718 | MachineInstrBuilder MIB = |
| 719 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) |
| 720 | .addFrameIndex(FI) |
Bob Wilson | d4bfd54 | 2010-08-27 23:18:17 +0000 | [diff] [blame] | 721 | .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 722 | .addMemOperand(MMO); |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 723 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); |
| 724 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); |
| 725 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); |
| 726 | AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 727 | } |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 728 | break; |
| 729 | case ARM::QQQQPRRegClassID: { |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 730 | MachineInstrBuilder MIB = |
| 731 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) |
| 732 | .addFrameIndex(FI) |
Bob Wilson | d4bfd54 | 2010-08-27 23:18:17 +0000 | [diff] [blame] | 733 | .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 734 | .addMemOperand(MMO); |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 735 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); |
| 736 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); |
| 737 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); |
| 738 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); |
| 739 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); |
| 740 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); |
| 741 | MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); |
| 742 | AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 743 | break; |
| 744 | } |
| 745 | default: |
| 746 | llvm_unreachable("Unknown regclass!"); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 747 | } |
| 748 | } |
| 749 | |
Jakob Stoklund Olesen | 3432785 | 2010-09-15 16:36:26 +0000 | [diff] [blame] | 750 | unsigned |
| 751 | ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, |
| 752 | int &FrameIndex) const { |
| 753 | switch (MI->getOpcode()) { |
| 754 | default: break; |
| 755 | case ARM::STR: |
| 756 | case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. |
| 757 | if (MI->getOperand(1).isFI() && |
| 758 | MI->getOperand(2).isReg() && |
| 759 | MI->getOperand(3).isImm() && |
| 760 | MI->getOperand(2).getReg() == 0 && |
| 761 | MI->getOperand(3).getImm() == 0) { |
| 762 | FrameIndex = MI->getOperand(1).getIndex(); |
| 763 | return MI->getOperand(0).getReg(); |
| 764 | } |
| 765 | break; |
| 766 | case ARM::t2STRi12: |
| 767 | case ARM::tSpill: |
| 768 | case ARM::VSTRD: |
| 769 | case ARM::VSTRS: |
| 770 | if (MI->getOperand(1).isFI() && |
| 771 | MI->getOperand(2).isImm() && |
| 772 | MI->getOperand(2).getImm() == 0) { |
| 773 | FrameIndex = MI->getOperand(1).getIndex(); |
| 774 | return MI->getOperand(0).getReg(); |
| 775 | } |
| 776 | break; |
Jakob Stoklund Olesen | d64816a | 2010-09-15 17:27:09 +0000 | [diff] [blame] | 777 | case ARM::VST1q64Pseudo: |
| 778 | if (MI->getOperand(0).isFI() && |
| 779 | MI->getOperand(2).getSubReg() == 0) { |
| 780 | FrameIndex = MI->getOperand(0).getIndex(); |
| 781 | return MI->getOperand(2).getReg(); |
| 782 | } |
Jakob Stoklund Olesen | 31bbc51 | 2010-09-15 21:40:09 +0000 | [diff] [blame] | 783 | break; |
Jakob Stoklund Olesen | d64816a | 2010-09-15 17:27:09 +0000 | [diff] [blame] | 784 | case ARM::VSTMQ: |
| 785 | if (MI->getOperand(1).isFI() && |
| 786 | MI->getOperand(2).isImm() && |
| 787 | MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && |
| 788 | MI->getOperand(0).getSubReg() == 0) { |
| 789 | FrameIndex = MI->getOperand(1).getIndex(); |
| 790 | return MI->getOperand(0).getReg(); |
| 791 | } |
| 792 | break; |
Jakob Stoklund Olesen | 3432785 | 2010-09-15 16:36:26 +0000 | [diff] [blame] | 793 | } |
| 794 | |
| 795 | return 0; |
| 796 | } |
| 797 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 798 | void ARMBaseInstrInfo:: |
| 799 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 800 | unsigned DestReg, int FI, |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 801 | const TargetRegisterClass *RC, |
| 802 | const TargetRegisterInfo *TRI) const { |
Chris Lattner | c7f3ace | 2010-04-02 20:16:16 +0000 | [diff] [blame] | 803 | DebugLoc DL; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 804 | if (I != MBB.end()) DL = I->getDebugLoc(); |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 805 | MachineFunction &MF = *MBB.getParent(); |
| 806 | MachineFrameInfo &MFI = *MF.getFrameInfo(); |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 807 | unsigned Align = MFI.getObjectAlignment(FI); |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 808 | MachineMemOperand *MMO = |
Chris Lattner | 59db549 | 2010-09-21 04:39:43 +0000 | [diff] [blame] | 809 | MF.getMachineMemOperand( |
| 810 | MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), |
| 811 | MachineMemOperand::MOLoad, |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 812 | MFI.getObjectSize(FI), |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 813 | Align); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 814 | |
Bob Wilson | 0eb0c74 | 2010-02-16 22:01:59 +0000 | [diff] [blame] | 815 | // tGPR is used sometimes in ARM instructions that need to avoid using |
| 816 | // certain registers. Just treat it as GPR here. |
Jim Grosbach | 6ccfc50 | 2010-07-30 02:41:01 +0000 | [diff] [blame] | 817 | if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass |
| 818 | || RC == ARM::rGPRRegisterClass) |
Bob Wilson | 0eb0c74 | 2010-02-16 22:01:59 +0000 | [diff] [blame] | 819 | RC = ARM::GPRRegisterClass; |
| 820 | |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 821 | switch (RC->getID()) { |
| 822 | case ARM::GPRRegClassID: |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 823 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 824 | .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 825 | break; |
| 826 | case ARM::SPRRegClassID: |
Evan Cheng | d31c549 | 2010-05-06 01:34:11 +0000 | [diff] [blame] | 827 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) |
| 828 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 829 | break; |
| 830 | case ARM::DPRRegClassID: |
| 831 | case ARM::DPR_VFP2RegClassID: |
| 832 | case ARM::DPR_8RegClassID: |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 833 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) |
Anton Korobeynikov | 249fb33 | 2009-10-07 00:06:35 +0000 | [diff] [blame] | 834 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 835 | break; |
| 836 | case ARM::QPRRegClassID: |
| 837 | case ARM::QPR_VFP2RegClassID: |
| 838 | case ARM::QPR_8RegClassID: |
Jim Grosbach | 0cfcf93 | 2010-09-08 00:26:59 +0000 | [diff] [blame] | 839 | if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { |
Bob Wilson | 168f382 | 2010-09-15 01:48:05 +0000 | [diff] [blame] | 840 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) |
Bob Wilson | f967ca0 | 2010-07-06 21:26:18 +0000 | [diff] [blame] | 841 | .addFrameIndex(FI).addImm(16) |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 842 | .addMemOperand(MMO)); |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 843 | } else { |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 844 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) |
| 845 | .addFrameIndex(FI) |
Bob Wilson | d4bfd54 | 2010-08-27 23:18:17 +0000 | [diff] [blame] | 846 | .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 847 | .addMemOperand(MMO)); |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 848 | } |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 849 | break; |
| 850 | case ARM::QQPRRegClassID: |
| 851 | case ARM::QQPR_VFP2RegClassID: |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 852 | if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { |
Bob Wilson | 168f382 | 2010-09-15 01:48:05 +0000 | [diff] [blame] | 853 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) |
| 854 | .addFrameIndex(FI).addImm(16) |
| 855 | .addMemOperand(MMO)); |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 856 | } else { |
| 857 | MachineInstrBuilder MIB = |
| 858 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) |
| 859 | .addFrameIndex(FI) |
Bob Wilson | d4bfd54 | 2010-08-27 23:18:17 +0000 | [diff] [blame] | 860 | .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 861 | .addMemOperand(MMO); |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 862 | MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); |
| 863 | MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); |
| 864 | MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); |
| 865 | AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); |
Evan Cheng | 435d499 | 2010-05-07 02:04:02 +0000 | [diff] [blame] | 866 | } |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 867 | break; |
| 868 | case ARM::QQQQPRRegClassID: { |
| 869 | MachineInstrBuilder MIB = |
| 870 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) |
| 871 | .addFrameIndex(FI) |
Bob Wilson | d4bfd54 | 2010-08-27 23:18:17 +0000 | [diff] [blame] | 872 | .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) |
Bob Wilson | ebe99b2 | 2010-06-18 21:32:42 +0000 | [diff] [blame] | 873 | .addMemOperand(MMO); |
| 874 | MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); |
| 875 | MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); |
| 876 | MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); |
| 877 | MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); |
| 878 | MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI); |
| 879 | MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI); |
| 880 | MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI); |
| 881 | AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI); |
| 882 | break; |
| 883 | } |
| 884 | default: |
| 885 | llvm_unreachable("Unknown regclass!"); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 886 | } |
| 887 | } |
| 888 | |
Jakob Stoklund Olesen | 3432785 | 2010-09-15 16:36:26 +0000 | [diff] [blame] | 889 | unsigned |
| 890 | ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, |
| 891 | int &FrameIndex) const { |
| 892 | switch (MI->getOpcode()) { |
| 893 | default: break; |
| 894 | case ARM::LDR: |
| 895 | case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. |
| 896 | if (MI->getOperand(1).isFI() && |
| 897 | MI->getOperand(2).isReg() && |
| 898 | MI->getOperand(3).isImm() && |
| 899 | MI->getOperand(2).getReg() == 0 && |
| 900 | MI->getOperand(3).getImm() == 0) { |
| 901 | FrameIndex = MI->getOperand(1).getIndex(); |
| 902 | return MI->getOperand(0).getReg(); |
| 903 | } |
| 904 | break; |
| 905 | case ARM::t2LDRi12: |
| 906 | case ARM::tRestore: |
| 907 | case ARM::VLDRD: |
| 908 | case ARM::VLDRS: |
| 909 | if (MI->getOperand(1).isFI() && |
| 910 | MI->getOperand(2).isImm() && |
| 911 | MI->getOperand(2).getImm() == 0) { |
| 912 | FrameIndex = MI->getOperand(1).getIndex(); |
| 913 | return MI->getOperand(0).getReg(); |
| 914 | } |
| 915 | break; |
Jakob Stoklund Olesen | d64816a | 2010-09-15 17:27:09 +0000 | [diff] [blame] | 916 | case ARM::VLD1q64Pseudo: |
| 917 | if (MI->getOperand(1).isFI() && |
| 918 | MI->getOperand(0).getSubReg() == 0) { |
| 919 | FrameIndex = MI->getOperand(1).getIndex(); |
| 920 | return MI->getOperand(0).getReg(); |
| 921 | } |
| 922 | break; |
Jakob Stoklund Olesen | 06f264e | 2010-09-15 21:40:11 +0000 | [diff] [blame] | 923 | case ARM::VLDMQ: |
| 924 | if (MI->getOperand(1).isFI() && |
| 925 | MI->getOperand(2).isImm() && |
| 926 | MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && |
| 927 | MI->getOperand(0).getSubReg() == 0) { |
| 928 | FrameIndex = MI->getOperand(1).getIndex(); |
| 929 | return MI->getOperand(0).getReg(); |
| 930 | } |
| 931 | break; |
Jakob Stoklund Olesen | 3432785 | 2010-09-15 16:36:26 +0000 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | return 0; |
| 935 | } |
| 936 | |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 937 | MachineInstr* |
| 938 | ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, |
Evan Cheng | 8601a3d | 2010-04-29 01:13:30 +0000 | [diff] [blame] | 939 | int FrameIx, uint64_t Offset, |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 940 | const MDNode *MDPtr, |
| 941 | DebugLoc DL) const { |
| 942 | MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) |
| 943 | .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); |
| 944 | return &*MIB; |
| 945 | } |
| 946 | |
Jakob Stoklund Olesen | 30ac046 | 2010-01-06 23:47:07 +0000 | [diff] [blame] | 947 | /// Create a copy of a const pool value. Update CPI to the new index and return |
| 948 | /// the label UID. |
| 949 | static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { |
| 950 | MachineConstantPool *MCP = MF.getConstantPool(); |
| 951 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 952 | |
| 953 | const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; |
| 954 | assert(MCPE.isMachineConstantPoolEntry() && |
| 955 | "Expecting a machine constantpool entry!"); |
| 956 | ARMConstantPoolValue *ACPV = |
| 957 | static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); |
| 958 | |
| 959 | unsigned PCLabelId = AFI->createConstPoolEntryUId(); |
| 960 | ARMConstantPoolValue *NewCPV = 0; |
Jim Grosbach | 51f5b67 | 2010-09-10 21:38:22 +0000 | [diff] [blame] | 961 | // FIXME: The below assumes PIC relocation model and that the function |
| 962 | // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and |
| 963 | // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR |
| 964 | // instructions, so that's probably OK, but is PIC always correct when |
| 965 | // we get here? |
Jakob Stoklund Olesen | 30ac046 | 2010-01-06 23:47:07 +0000 | [diff] [blame] | 966 | if (ACPV->isGlobalValue()) |
| 967 | NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, |
| 968 | ARMCP::CPValue, 4); |
| 969 | else if (ACPV->isExtSymbol()) |
| 970 | NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(), |
| 971 | ACPV->getSymbol(), PCLabelId, 4); |
| 972 | else if (ACPV->isBlockAddress()) |
| 973 | NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, |
| 974 | ARMCP::CPBlockAddress, 4); |
Jim Grosbach | 51f5b67 | 2010-09-10 21:38:22 +0000 | [diff] [blame] | 975 | else if (ACPV->isLSDA()) |
| 976 | NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, |
| 977 | ARMCP::CPLSDA, 4); |
Jakob Stoklund Olesen | 30ac046 | 2010-01-06 23:47:07 +0000 | [diff] [blame] | 978 | else |
| 979 | llvm_unreachable("Unexpected ARM constantpool value type!!"); |
| 980 | CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); |
| 981 | return PCLabelId; |
| 982 | } |
| 983 | |
Evan Cheng | fdc8340 | 2009-11-08 00:15:23 +0000 | [diff] [blame] | 984 | void ARMBaseInstrInfo:: |
| 985 | reMaterialize(MachineBasicBlock &MBB, |
| 986 | MachineBasicBlock::iterator I, |
| 987 | unsigned DestReg, unsigned SubIdx, |
Evan Cheng | d57cdd5 | 2009-11-14 02:55:43 +0000 | [diff] [blame] | 988 | const MachineInstr *Orig, |
Jakob Stoklund Olesen | 9edf7de | 2010-06-02 22:47:25 +0000 | [diff] [blame] | 989 | const TargetRegisterInfo &TRI) const { |
Evan Cheng | fdc8340 | 2009-11-08 00:15:23 +0000 | [diff] [blame] | 990 | unsigned Opcode = Orig->getOpcode(); |
| 991 | switch (Opcode) { |
| 992 | default: { |
| 993 | MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); |
Jakob Stoklund Olesen | 9edf7de | 2010-06-02 22:47:25 +0000 | [diff] [blame] | 994 | MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); |
Evan Cheng | fdc8340 | 2009-11-08 00:15:23 +0000 | [diff] [blame] | 995 | MBB.insert(I, MI); |
| 996 | break; |
| 997 | } |
| 998 | case ARM::tLDRpci_pic: |
| 999 | case ARM::t2LDRpci_pic: { |
| 1000 | MachineFunction &MF = *MBB.getParent(); |
Evan Cheng | fdc8340 | 2009-11-08 00:15:23 +0000 | [diff] [blame] | 1001 | unsigned CPI = Orig->getOperand(1).getIndex(); |
Jakob Stoklund Olesen | 30ac046 | 2010-01-06 23:47:07 +0000 | [diff] [blame] | 1002 | unsigned PCLabelId = duplicateCPV(MF, CPI); |
Evan Cheng | fdc8340 | 2009-11-08 00:15:23 +0000 | [diff] [blame] | 1003 | MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), |
| 1004 | DestReg) |
| 1005 | .addConstantPoolIndex(CPI).addImm(PCLabelId); |
| 1006 | (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); |
| 1007 | break; |
| 1008 | } |
| 1009 | } |
Evan Cheng | fdc8340 | 2009-11-08 00:15:23 +0000 | [diff] [blame] | 1010 | } |
| 1011 | |
Jakob Stoklund Olesen | 30ac046 | 2010-01-06 23:47:07 +0000 | [diff] [blame] | 1012 | MachineInstr * |
| 1013 | ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { |
| 1014 | MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); |
| 1015 | switch(Orig->getOpcode()) { |
| 1016 | case ARM::tLDRpci_pic: |
| 1017 | case ARM::t2LDRpci_pic: { |
| 1018 | unsigned CPI = Orig->getOperand(1).getIndex(); |
| 1019 | unsigned PCLabelId = duplicateCPV(MF, CPI); |
| 1020 | Orig->getOperand(1).setIndex(CPI); |
| 1021 | Orig->getOperand(2).setImm(PCLabelId); |
| 1022 | break; |
| 1023 | } |
| 1024 | } |
| 1025 | return MI; |
| 1026 | } |
| 1027 | |
Evan Cheng | 506049f | 2010-03-03 01:44:33 +0000 | [diff] [blame] | 1028 | bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, |
| 1029 | const MachineInstr *MI1) const { |
Evan Cheng | d457e6e | 2009-11-07 04:04:34 +0000 | [diff] [blame] | 1030 | int Opcode = MI0->getOpcode(); |
Evan Cheng | 9b82425 | 2009-11-20 02:10:27 +0000 | [diff] [blame] | 1031 | if (Opcode == ARM::t2LDRpci || |
| 1032 | Opcode == ARM::t2LDRpci_pic || |
| 1033 | Opcode == ARM::tLDRpci || |
| 1034 | Opcode == ARM::tLDRpci_pic) { |
Evan Cheng | d457e6e | 2009-11-07 04:04:34 +0000 | [diff] [blame] | 1035 | if (MI1->getOpcode() != Opcode) |
| 1036 | return false; |
| 1037 | if (MI0->getNumOperands() != MI1->getNumOperands()) |
| 1038 | return false; |
| 1039 | |
| 1040 | const MachineOperand &MO0 = MI0->getOperand(1); |
| 1041 | const MachineOperand &MO1 = MI1->getOperand(1); |
| 1042 | if (MO0.getOffset() != MO1.getOffset()) |
| 1043 | return false; |
| 1044 | |
| 1045 | const MachineFunction *MF = MI0->getParent()->getParent(); |
| 1046 | const MachineConstantPool *MCP = MF->getConstantPool(); |
| 1047 | int CPI0 = MO0.getIndex(); |
| 1048 | int CPI1 = MO1.getIndex(); |
| 1049 | const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; |
| 1050 | const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; |
| 1051 | ARMConstantPoolValue *ACPV0 = |
| 1052 | static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); |
| 1053 | ARMConstantPoolValue *ACPV1 = |
| 1054 | static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); |
| 1055 | return ACPV0->hasSameValue(ACPV1); |
| 1056 | } |
| 1057 | |
Evan Cheng | 506049f | 2010-03-03 01:44:33 +0000 | [diff] [blame] | 1058 | return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); |
Evan Cheng | d457e6e | 2009-11-07 04:04:34 +0000 | [diff] [blame] | 1059 | } |
| 1060 | |
Bill Wendling | 4b72210 | 2010-06-23 23:00:16 +0000 | [diff] [blame] | 1061 | /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to |
| 1062 | /// determine if two loads are loading from the same base address. It should |
| 1063 | /// only return true if the base pointers are the same and the only differences |
| 1064 | /// between the two addresses is the offset. It also returns the offsets by |
| 1065 | /// reference. |
| 1066 | bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, |
| 1067 | int64_t &Offset1, |
| 1068 | int64_t &Offset2) const { |
| 1069 | // Don't worry about Thumb: just ARM and Thumb2. |
| 1070 | if (Subtarget.isThumb1Only()) return false; |
| 1071 | |
| 1072 | if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) |
| 1073 | return false; |
| 1074 | |
| 1075 | switch (Load1->getMachineOpcode()) { |
| 1076 | default: |
| 1077 | return false; |
| 1078 | case ARM::LDR: |
| 1079 | case ARM::LDRB: |
| 1080 | case ARM::LDRD: |
| 1081 | case ARM::LDRH: |
| 1082 | case ARM::LDRSB: |
| 1083 | case ARM::LDRSH: |
| 1084 | case ARM::VLDRD: |
| 1085 | case ARM::VLDRS: |
| 1086 | case ARM::t2LDRi8: |
| 1087 | case ARM::t2LDRDi8: |
| 1088 | case ARM::t2LDRSHi8: |
| 1089 | case ARM::t2LDRi12: |
| 1090 | case ARM::t2LDRSHi12: |
| 1091 | break; |
| 1092 | } |
| 1093 | |
| 1094 | switch (Load2->getMachineOpcode()) { |
| 1095 | default: |
| 1096 | return false; |
| 1097 | case ARM::LDR: |
| 1098 | case ARM::LDRB: |
| 1099 | case ARM::LDRD: |
| 1100 | case ARM::LDRH: |
| 1101 | case ARM::LDRSB: |
| 1102 | case ARM::LDRSH: |
| 1103 | case ARM::VLDRD: |
| 1104 | case ARM::VLDRS: |
| 1105 | case ARM::t2LDRi8: |
| 1106 | case ARM::t2LDRDi8: |
| 1107 | case ARM::t2LDRSHi8: |
| 1108 | case ARM::t2LDRi12: |
| 1109 | case ARM::t2LDRSHi12: |
| 1110 | break; |
| 1111 | } |
| 1112 | |
| 1113 | // Check if base addresses and chain operands match. |
| 1114 | if (Load1->getOperand(0) != Load2->getOperand(0) || |
| 1115 | Load1->getOperand(4) != Load2->getOperand(4)) |
| 1116 | return false; |
| 1117 | |
| 1118 | // Index should be Reg0. |
| 1119 | if (Load1->getOperand(3) != Load2->getOperand(3)) |
| 1120 | return false; |
| 1121 | |
| 1122 | // Determine the offsets. |
| 1123 | if (isa<ConstantSDNode>(Load1->getOperand(1)) && |
| 1124 | isa<ConstantSDNode>(Load2->getOperand(1))) { |
| 1125 | Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); |
| 1126 | Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); |
| 1127 | return true; |
| 1128 | } |
| 1129 | |
| 1130 | return false; |
| 1131 | } |
| 1132 | |
| 1133 | /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to |
| 1134 | /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should |
| 1135 | /// be scheduled togther. On some targets if two loads are loading from |
| 1136 | /// addresses in the same cache line, it's better if they are scheduled |
| 1137 | /// together. This function takes two integers that represent the load offsets |
| 1138 | /// from the common base address. It returns true if it decides it's desirable |
| 1139 | /// to schedule the two loads together. "NumLoads" is the number of loads that |
| 1140 | /// have already been scheduled after Load1. |
| 1141 | bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, |
| 1142 | int64_t Offset1, int64_t Offset2, |
| 1143 | unsigned NumLoads) const { |
| 1144 | // Don't worry about Thumb: just ARM and Thumb2. |
| 1145 | if (Subtarget.isThumb1Only()) return false; |
| 1146 | |
| 1147 | assert(Offset2 > Offset1); |
| 1148 | |
| 1149 | if ((Offset2 - Offset1) / 8 > 64) |
| 1150 | return false; |
| 1151 | |
| 1152 | if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) |
| 1153 | return false; // FIXME: overly conservative? |
| 1154 | |
| 1155 | // Four loads in a row should be sufficient. |
| 1156 | if (NumLoads >= 3) |
| 1157 | return false; |
| 1158 | |
| 1159 | return true; |
| 1160 | } |
| 1161 | |
Evan Cheng | 86050dc | 2010-06-18 23:09:54 +0000 | [diff] [blame] | 1162 | bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, |
| 1163 | const MachineBasicBlock *MBB, |
| 1164 | const MachineFunction &MF) const { |
Jim Grosbach | 57bb394 | 2010-06-25 18:43:14 +0000 | [diff] [blame] | 1165 | // Debug info is never a scheduling boundary. It's necessary to be explicit |
| 1166 | // due to the special treatment of IT instructions below, otherwise a |
| 1167 | // dbg_value followed by an IT will result in the IT instruction being |
| 1168 | // considered a scheduling hazard, which is wrong. It should be the actual |
| 1169 | // instruction preceding the dbg_value instruction(s), just like it is |
| 1170 | // when debug info is not present. |
| 1171 | if (MI->isDebugValue()) |
| 1172 | return false; |
| 1173 | |
Evan Cheng | 86050dc | 2010-06-18 23:09:54 +0000 | [diff] [blame] | 1174 | // Terminators and labels can't be scheduled around. |
| 1175 | if (MI->getDesc().isTerminator() || MI->isLabel()) |
| 1176 | return true; |
| 1177 | |
| 1178 | // Treat the start of the IT block as a scheduling boundary, but schedule |
| 1179 | // t2IT along with all instructions following it. |
| 1180 | // FIXME: This is a big hammer. But the alternative is to add all potential |
| 1181 | // true and anti dependencies to IT block instructions as implicit operands |
| 1182 | // to the t2IT instruction. The added compile time and complexity does not |
| 1183 | // seem worth it. |
| 1184 | MachineBasicBlock::const_iterator I = MI; |
Jim Grosbach | 57bb394 | 2010-06-25 18:43:14 +0000 | [diff] [blame] | 1185 | // Make sure to skip any dbg_value instructions |
| 1186 | while (++I != MBB->end() && I->isDebugValue()) |
| 1187 | ; |
| 1188 | if (I != MBB->end() && I->getOpcode() == ARM::t2IT) |
Evan Cheng | 86050dc | 2010-06-18 23:09:54 +0000 | [diff] [blame] | 1189 | return true; |
| 1190 | |
| 1191 | // Don't attempt to schedule around any instruction that defines |
| 1192 | // a stack-oriented pointer, as it's unlikely to be profitable. This |
| 1193 | // saves compile time, because it doesn't require every single |
| 1194 | // stack slot reference to depend on the instruction that does the |
| 1195 | // modification. |
| 1196 | if (MI->definesRegister(ARM::SP)) |
| 1197 | return true; |
| 1198 | |
| 1199 | return false; |
| 1200 | } |
| 1201 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1202 | bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, |
| 1203 | unsigned NumInstrs, |
Owen Anderson | e3cc84a | 2010-10-01 22:45:50 +0000 | [diff] [blame] | 1204 | float Probability, |
| 1205 | float Confidence) const { |
Evan Cheng | 1315143 | 2010-06-25 22:42:03 +0000 | [diff] [blame] | 1206 | if (!NumInstrs) |
| 1207 | return false; |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1208 | |
Owen Anderson | b3c04ec | 2010-09-30 23:48:38 +0000 | [diff] [blame] | 1209 | // Use old-style heuristics |
Owen Anderson | 00d4f48 | 2010-10-01 20:33:47 +0000 | [diff] [blame] | 1210 | if (OldARMIfCvt) { |
Owen Anderson | b3c04ec | 2010-09-30 23:48:38 +0000 | [diff] [blame] | 1211 | if (Subtarget.getCPUString() == "generic") |
| 1212 | // Generic (and overly aggressive) if-conversion limits for testing. |
| 1213 | return NumInstrs <= 10; |
Owen Anderson | 00d4f48 | 2010-10-01 20:33:47 +0000 | [diff] [blame] | 1214 | if (Subtarget.hasV7Ops()) |
Owen Anderson | b3c04ec | 2010-09-30 23:48:38 +0000 | [diff] [blame] | 1215 | return NumInstrs <= 3; |
| 1216 | return NumInstrs <= 2; |
| 1217 | } |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1218 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1219 | // Attempt to estimate the relative costs of predication versus branching. |
| 1220 | float UnpredCost = Probability * NumInstrs; |
Owen Anderson | 654d544 | 2010-09-28 21:57:50 +0000 | [diff] [blame] | 1221 | UnpredCost += 1.0; // The branch itself |
Owen Anderson | e3cc84a | 2010-10-01 22:45:50 +0000 | [diff] [blame] | 1222 | UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1223 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1224 | float PredCost = NumInstrs; |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1225 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1226 | return PredCost < UnpredCost; |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1227 | |
Evan Cheng | 1315143 | 2010-06-25 22:42:03 +0000 | [diff] [blame] | 1228 | } |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1229 | |
Evan Cheng | 1315143 | 2010-06-25 22:42:03 +0000 | [diff] [blame] | 1230 | bool ARMBaseInstrInfo:: |
| 1231 | isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1232 | MachineBasicBlock &FMBB, unsigned NumF, |
Owen Anderson | e3cc84a | 2010-10-01 22:45:50 +0000 | [diff] [blame] | 1233 | float Probability, float Confidence) const { |
Owen Anderson | b3c04ec | 2010-09-30 23:48:38 +0000 | [diff] [blame] | 1234 | // Use old-style if-conversion heuristics |
Owen Anderson | 00d4f48 | 2010-10-01 20:33:47 +0000 | [diff] [blame] | 1235 | if (OldARMIfCvt) { |
Owen Anderson | b3c04ec | 2010-09-30 23:48:38 +0000 | [diff] [blame] | 1236 | return NumT && NumF && NumT <= 2 && NumF <= 2; |
| 1237 | } |
| 1238 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1239 | if (!NumT || !NumF) |
| 1240 | return false; |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1241 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1242 | // Attempt to estimate the relative costs of predication versus branching. |
| 1243 | float UnpredCost = Probability * NumT + (1.0 - Probability) * NumF; |
Owen Anderson | 654d544 | 2010-09-28 21:57:50 +0000 | [diff] [blame] | 1244 | UnpredCost += 1.0; // The branch itself |
Owen Anderson | e3cc84a | 2010-10-01 22:45:50 +0000 | [diff] [blame] | 1245 | UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1246 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1247 | float PredCost = NumT + NumF; |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1248 | |
Owen Anderson | b20b851 | 2010-09-28 18:32:13 +0000 | [diff] [blame] | 1249 | return PredCost < UnpredCost; |
Evan Cheng | 1315143 | 2010-06-25 22:42:03 +0000 | [diff] [blame] | 1250 | } |
| 1251 | |
Evan Cheng | 8fb9036 | 2009-08-08 03:20:32 +0000 | [diff] [blame] | 1252 | /// getInstrPredicate - If instruction is predicated, returns its predicate |
| 1253 | /// condition, otherwise returns AL. It also returns the condition code |
| 1254 | /// register by reference. |
Evan Cheng | 5adb66a | 2009-09-28 09:14:39 +0000 | [diff] [blame] | 1255 | ARMCC::CondCodes |
| 1256 | llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { |
Evan Cheng | 8fb9036 | 2009-08-08 03:20:32 +0000 | [diff] [blame] | 1257 | int PIdx = MI->findFirstPredOperandIdx(); |
| 1258 | if (PIdx == -1) { |
| 1259 | PredReg = 0; |
| 1260 | return ARMCC::AL; |
| 1261 | } |
| 1262 | |
| 1263 | PredReg = MI->getOperand(PIdx+1).getReg(); |
| 1264 | return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); |
| 1265 | } |
| 1266 | |
| 1267 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1268 | int llvm::getMatchingCondBranchOpcode(int Opc) { |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 1269 | if (Opc == ARM::B) |
| 1270 | return ARM::Bcc; |
| 1271 | else if (Opc == ARM::tB) |
| 1272 | return ARM::tBcc; |
| 1273 | else if (Opc == ARM::t2B) |
| 1274 | return ARM::t2Bcc; |
| 1275 | |
| 1276 | llvm_unreachable("Unknown unconditional branch opcode!"); |
| 1277 | return 0; |
| 1278 | } |
| 1279 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1280 | |
| 1281 | void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, |
| 1282 | MachineBasicBlock::iterator &MBBI, DebugLoc dl, |
| 1283 | unsigned DestReg, unsigned BaseReg, int NumBytes, |
| 1284 | ARMCC::CondCodes Pred, unsigned PredReg, |
| 1285 | const ARMBaseInstrInfo &TII) { |
| 1286 | bool isSub = NumBytes < 0; |
| 1287 | if (isSub) NumBytes = -NumBytes; |
| 1288 | |
| 1289 | while (NumBytes) { |
| 1290 | unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); |
| 1291 | unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); |
| 1292 | assert(ThisVal && "Didn't extract field correctly"); |
| 1293 | |
| 1294 | // We will handle these bits from offset, clear them. |
| 1295 | NumBytes &= ~ThisVal; |
| 1296 | |
| 1297 | assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); |
| 1298 | |
| 1299 | // Build the new ADD / SUB. |
| 1300 | unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; |
| 1301 | BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) |
| 1302 | .addReg(BaseReg, RegState::Kill).addImm(ThisVal) |
| 1303 | .addImm((unsigned)Pred).addReg(PredReg).addReg(0); |
| 1304 | BaseReg = DestReg; |
| 1305 | } |
| 1306 | } |
| 1307 | |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1308 | bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, |
| 1309 | unsigned FrameReg, int &Offset, |
| 1310 | const ARMBaseInstrInfo &TII) { |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1311 | unsigned Opcode = MI.getOpcode(); |
| 1312 | const TargetInstrDesc &Desc = MI.getDesc(); |
| 1313 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 1314 | bool isSub = false; |
Jim Grosbach | 764ab52 | 2009-08-11 15:33:49 +0000 | [diff] [blame] | 1315 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1316 | // Memory operands in inline assembly always use AddrMode2. |
| 1317 | if (Opcode == ARM::INLINEASM) |
| 1318 | AddrMode = ARMII::AddrMode2; |
Jim Grosbach | 764ab52 | 2009-08-11 15:33:49 +0000 | [diff] [blame] | 1319 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1320 | if (Opcode == ARM::ADDri) { |
| 1321 | Offset += MI.getOperand(FrameRegIdx+1).getImm(); |
| 1322 | if (Offset == 0) { |
| 1323 | // Turn it into a move. |
| 1324 | MI.setDesc(TII.get(ARM::MOVr)); |
| 1325 | MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); |
| 1326 | MI.RemoveOperand(FrameRegIdx+1); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1327 | Offset = 0; |
| 1328 | return true; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1329 | } else if (Offset < 0) { |
| 1330 | Offset = -Offset; |
| 1331 | isSub = true; |
| 1332 | MI.setDesc(TII.get(ARM::SUBri)); |
| 1333 | } |
| 1334 | |
| 1335 | // Common case: small offset, fits into instruction. |
| 1336 | if (ARM_AM::getSOImmVal(Offset) != -1) { |
| 1337 | // Replace the FrameIndex with sp / fp |
| 1338 | MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); |
| 1339 | MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1340 | Offset = 0; |
| 1341 | return true; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1342 | } |
| 1343 | |
| 1344 | // Otherwise, pull as much of the immedidate into this ADDri/SUBri |
| 1345 | // as possible. |
| 1346 | unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); |
| 1347 | unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); |
| 1348 | |
| 1349 | // We will handle these bits from offset, clear them. |
| 1350 | Offset &= ~ThisImmVal; |
| 1351 | |
| 1352 | // Get the properly encoded SOImmVal field. |
| 1353 | assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && |
| 1354 | "Bit extraction didn't work?"); |
| 1355 | MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); |
| 1356 | } else { |
| 1357 | unsigned ImmIdx = 0; |
| 1358 | int InstrOffs = 0; |
| 1359 | unsigned NumBits = 0; |
| 1360 | unsigned Scale = 1; |
| 1361 | switch (AddrMode) { |
| 1362 | case ARMII::AddrMode2: { |
| 1363 | ImmIdx = FrameRegIdx+2; |
| 1364 | InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); |
| 1365 | if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1366 | InstrOffs *= -1; |
| 1367 | NumBits = 12; |
| 1368 | break; |
| 1369 | } |
| 1370 | case ARMII::AddrMode3: { |
| 1371 | ImmIdx = FrameRegIdx+2; |
| 1372 | InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); |
| 1373 | if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1374 | InstrOffs *= -1; |
| 1375 | NumBits = 8; |
| 1376 | break; |
| 1377 | } |
Anton Korobeynikov | baf3108 | 2009-08-08 13:35:48 +0000 | [diff] [blame] | 1378 | case ARMII::AddrMode4: |
Jim Grosbach | a443217 | 2009-11-15 21:45:34 +0000 | [diff] [blame] | 1379 | case ARMII::AddrMode6: |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1380 | // Can't fold any offset even if it's zero. |
| 1381 | return false; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1382 | case ARMII::AddrMode5: { |
| 1383 | ImmIdx = FrameRegIdx+1; |
| 1384 | InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); |
| 1385 | if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1386 | InstrOffs *= -1; |
| 1387 | NumBits = 8; |
| 1388 | Scale = 4; |
| 1389 | break; |
| 1390 | } |
| 1391 | default: |
| 1392 | llvm_unreachable("Unsupported addressing mode!"); |
| 1393 | break; |
| 1394 | } |
| 1395 | |
| 1396 | Offset += InstrOffs * Scale; |
| 1397 | assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); |
| 1398 | if (Offset < 0) { |
| 1399 | Offset = -Offset; |
| 1400 | isSub = true; |
| 1401 | } |
| 1402 | |
| 1403 | // Attempt to fold address comp. if opcode has offset bits |
| 1404 | if (NumBits > 0) { |
| 1405 | // Common case: small offset, fits into instruction. |
| 1406 | MachineOperand &ImmOp = MI.getOperand(ImmIdx); |
| 1407 | int ImmedOffset = Offset / Scale; |
| 1408 | unsigned Mask = (1 << NumBits) - 1; |
| 1409 | if ((unsigned)Offset <= Mask * Scale) { |
| 1410 | // Replace the FrameIndex with sp |
| 1411 | MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); |
| 1412 | if (isSub) |
| 1413 | ImmedOffset |= 1 << NumBits; |
| 1414 | ImmOp.ChangeToImmediate(ImmedOffset); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1415 | Offset = 0; |
| 1416 | return true; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1417 | } |
Jim Grosbach | 764ab52 | 2009-08-11 15:33:49 +0000 | [diff] [blame] | 1418 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1419 | // Otherwise, it didn't fit. Pull in what we can to simplify the immed. |
| 1420 | ImmedOffset = ImmedOffset & Mask; |
| 1421 | if (isSub) |
| 1422 | ImmedOffset |= 1 << NumBits; |
| 1423 | ImmOp.ChangeToImmediate(ImmedOffset); |
| 1424 | Offset &= ~(Mask*Scale); |
| 1425 | } |
| 1426 | } |
| 1427 | |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1428 | Offset = (isSub) ? -Offset : Offset; |
| 1429 | return Offset == 0; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1430 | } |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1431 | |
| 1432 | bool ARMBaseInstrInfo:: |
Eric Christopher | a99c3e9 | 2010-09-28 04:18:29 +0000 | [diff] [blame] | 1433 | AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, |
| 1434 | int &CmpValue) const { |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1435 | switch (MI->getOpcode()) { |
| 1436 | default: break; |
Bill Wendling | 38ae997 | 2010-08-11 00:23:00 +0000 | [diff] [blame] | 1437 | case ARM::CMPri: |
| 1438 | case ARM::CMPzri: |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1439 | case ARM::t2CMPri: |
| 1440 | case ARM::t2CMPzri: |
| 1441 | SrcReg = MI->getOperand(0).getReg(); |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1442 | CmpMask = ~0; |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1443 | CmpValue = MI->getOperand(1).getImm(); |
| 1444 | return true; |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1445 | case ARM::TSTri: |
| 1446 | case ARM::t2TSTri: |
| 1447 | SrcReg = MI->getOperand(0).getReg(); |
| 1448 | CmpMask = MI->getOperand(1).getImm(); |
| 1449 | CmpValue = 0; |
| 1450 | return true; |
| 1451 | } |
| 1452 | |
| 1453 | return false; |
| 1454 | } |
| 1455 | |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1456 | /// isSuitableForMask - Identify a suitable 'and' instruction that |
| 1457 | /// operates on the given source register and applies the same mask |
| 1458 | /// as a 'tst' instruction. Provide a limited look-through for copies. |
| 1459 | /// When successful, MI will hold the found instruction. |
| 1460 | static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, |
Gabor Greif | 8ff9bb1 | 2010-09-21 13:30:57 +0000 | [diff] [blame] | 1461 | int CmpMask, bool CommonUse) { |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1462 | switch (MI->getOpcode()) { |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1463 | case ARM::ANDri: |
| 1464 | case ARM::t2ANDri: |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1465 | if (CmpMask != MI->getOperand(2).getImm()) |
Gabor Greif | 8ff9bb1 | 2010-09-21 13:30:57 +0000 | [diff] [blame] | 1466 | return false; |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1467 | if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1468 | return true; |
| 1469 | break; |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1470 | case ARM::COPY: { |
| 1471 | // Walk down one instruction which is potentially an 'and'. |
| 1472 | const MachineInstr &Copy = *MI; |
Michael J. Spencer | f000a7a | 2010-10-05 06:00:43 +0000 | [diff] [blame^] | 1473 | MachineBasicBlock::iterator AND( |
| 1474 | llvm::next(MachineBasicBlock::iterator(MI))); |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1475 | if (AND == MI->getParent()->end()) return false; |
| 1476 | MI = AND; |
| 1477 | return isSuitableForMask(MI, Copy.getOperand(0).getReg(), |
| 1478 | CmpMask, true); |
| 1479 | } |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1480 | } |
| 1481 | |
| 1482 | return false; |
| 1483 | } |
| 1484 | |
Bill Wendling | a655686 | 2010-09-11 00:13:50 +0000 | [diff] [blame] | 1485 | /// OptimizeCompareInstr - Convert the instruction supplying the argument to the |
Bill Wendling | 92ad57f | 2010-09-10 23:34:19 +0000 | [diff] [blame] | 1486 | /// comparison into one that sets the zero bit in the flags register. Update the |
| 1487 | /// iterator *only* if a transformation took place. |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1488 | bool ARMBaseInstrInfo:: |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1489 | OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, |
| 1490 | int CmpValue, MachineBasicBlock::iterator &MII) const { |
Bill Wendling | 3665661 | 2010-09-10 23:46:12 +0000 | [diff] [blame] | 1491 | if (CmpValue != 0) |
Bill Wendling | 92ad57f | 2010-09-10 23:34:19 +0000 | [diff] [blame] | 1492 | return false; |
| 1493 | |
| 1494 | MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo(); |
| 1495 | MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg); |
| 1496 | if (llvm::next(DI) != MRI.def_end()) |
| 1497 | // Only support one definition. |
| 1498 | return false; |
| 1499 | |
| 1500 | MachineInstr *MI = &*DI; |
| 1501 | |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1502 | // Masked compares sometimes use the same register as the corresponding 'and'. |
| 1503 | if (CmpMask != ~0) { |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1504 | if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1505 | MI = 0; |
| 1506 | for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg), |
| 1507 | UE = MRI.use_end(); UI != UE; ++UI) { |
| 1508 | if (UI->getParent() != CmpInstr->getParent()) continue; |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1509 | MachineInstr *PotentialAND = &*UI; |
Gabor Greif | 8ff9bb1 | 2010-09-21 13:30:57 +0000 | [diff] [blame] | 1510 | if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1511 | continue; |
Gabor Greif | 05642a3 | 2010-09-29 10:12:08 +0000 | [diff] [blame] | 1512 | MI = PotentialAND; |
Gabor Greif | 04ac81d | 2010-09-21 12:01:15 +0000 | [diff] [blame] | 1513 | break; |
| 1514 | } |
| 1515 | if (!MI) return false; |
| 1516 | } |
| 1517 | } |
| 1518 | |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1519 | // Conservatively refuse to convert an instruction which isn't in the same BB |
| 1520 | // as the comparison. |
| 1521 | if (MI->getParent() != CmpInstr->getParent()) |
| 1522 | return false; |
| 1523 | |
| 1524 | // Check that CPSR isn't set between the comparison instruction and the one we |
| 1525 | // want to change. |
Evan Cheng | 691e64a | 2010-09-21 23:49:07 +0000 | [diff] [blame] | 1526 | MachineBasicBlock::const_iterator I = CmpInstr, E = MI, |
| 1527 | B = MI->getParent()->begin(); |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1528 | --I; |
| 1529 | for (; I != E; --I) { |
| 1530 | const MachineInstr &Instr = *I; |
| 1531 | |
| 1532 | for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { |
| 1533 | const MachineOperand &MO = Instr.getOperand(IO); |
Bill Wendling | 75486db | 2010-08-10 21:38:11 +0000 | [diff] [blame] | 1534 | if (!MO.isReg() || !MO.isDef()) continue; |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1535 | |
| 1536 | // This instruction modifies CPSR before the one we want to change. We |
| 1537 | // can't do this transformation. |
| 1538 | if (MO.getReg() == ARM::CPSR) |
| 1539 | return false; |
| 1540 | } |
Evan Cheng | 691e64a | 2010-09-21 23:49:07 +0000 | [diff] [blame] | 1541 | |
| 1542 | if (I == B) |
| 1543 | // The 'and' is below the comparison instruction. |
| 1544 | return false; |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1545 | } |
| 1546 | |
| 1547 | // Set the "zero" bit in CPSR. |
| 1548 | switch (MI->getOpcode()) { |
| 1549 | default: break; |
Bill Wendling | 38ae997 | 2010-08-11 00:23:00 +0000 | [diff] [blame] | 1550 | case ARM::ADDri: |
Bob Wilson | 3a95182 | 2010-09-15 17:12:08 +0000 | [diff] [blame] | 1551 | case ARM::ANDri: |
| 1552 | case ARM::t2ANDri: |
Bill Wendling | 38ae997 | 2010-08-11 00:23:00 +0000 | [diff] [blame] | 1553 | case ARM::SUBri: |
| 1554 | case ARM::t2ADDri: |
Bill Wendling | ad42271 | 2010-08-18 21:32:07 +0000 | [diff] [blame] | 1555 | case ARM::t2SUBri: |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1556 | MI->RemoveOperand(5); |
Bill Wendling | ad42271 | 2010-08-18 21:32:07 +0000 | [diff] [blame] | 1557 | MachineInstrBuilder(MI) |
| 1558 | .addReg(ARM::CPSR, RegState::Define | RegState::Implicit); |
Bill Wendling | 220e240 | 2010-09-10 21:55:43 +0000 | [diff] [blame] | 1559 | MII = llvm::next(MachineBasicBlock::iterator(CmpInstr)); |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1560 | CmpInstr->eraseFromParent(); |
| 1561 | return true; |
| 1562 | } |
Bill Wendling | e4ddbdf | 2010-08-06 01:32:48 +0000 | [diff] [blame] | 1563 | |
| 1564 | return false; |
| 1565 | } |
Evan Cheng | 5f54ce3 | 2010-09-09 18:18:55 +0000 | [diff] [blame] | 1566 | |
| 1567 | unsigned |
| 1568 | ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI, |
Evan Cheng | 3ef1c87 | 2010-09-10 01:29:16 +0000 | [diff] [blame] | 1569 | const InstrItineraryData *ItinData) const { |
| 1570 | if (!ItinData || ItinData->isEmpty()) |
Evan Cheng | 5f54ce3 | 2010-09-09 18:18:55 +0000 | [diff] [blame] | 1571 | return 1; |
| 1572 | |
| 1573 | const TargetInstrDesc &Desc = MI->getDesc(); |
| 1574 | unsigned Class = Desc.getSchedClass(); |
Bob Wilson | 064312d | 2010-09-15 16:28:21 +0000 | [diff] [blame] | 1575 | unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; |
Evan Cheng | 5f54ce3 | 2010-09-09 18:18:55 +0000 | [diff] [blame] | 1576 | if (UOps) |
| 1577 | return UOps; |
| 1578 | |
| 1579 | unsigned Opc = MI->getOpcode(); |
| 1580 | switch (Opc) { |
| 1581 | default: |
| 1582 | llvm_unreachable("Unexpected multi-uops instruction!"); |
| 1583 | break; |
Evan Cheng | 3ef1c87 | 2010-09-10 01:29:16 +0000 | [diff] [blame] | 1584 | case ARM::VLDMQ: |
Evan Cheng | 5f54ce3 | 2010-09-09 18:18:55 +0000 | [diff] [blame] | 1585 | case ARM::VSTMQ: |
| 1586 | return 2; |
| 1587 | |
| 1588 | // The number of uOps for load / store multiple are determined by the number |
| 1589 | // registers. |
Evan Cheng | 3ef1c87 | 2010-09-10 01:29:16 +0000 | [diff] [blame] | 1590 | // On Cortex-A8, each pair of register loads / stores can be scheduled on the |
| 1591 | // same cycle. The scheduling for the first load / store must be done |
| 1592 | // separately by assuming the the address is not 64-bit aligned. |
| 1593 | // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address |
| 1594 | // is not 64-bit aligned, then AGU would take an extra cycle. |
| 1595 | // For VFP / NEON load / store multiple, the formula is |
Evan Cheng | 5f54ce3 | 2010-09-09 18:18:55 +0000 | [diff] [blame] | 1596 | // (#reg / 2) + (#reg % 2) + 1. |
Evan Cheng | 5f54ce3 | 2010-09-09 18:18:55 +0000 | [diff] [blame] | 1597 | case ARM::VLDMD: |
| 1598 | case ARM::VLDMS: |
| 1599 | case ARM::VLDMD_UPD: |
| 1600 | case ARM::VLDMS_UPD: |
| 1601 | case ARM::VSTMD: |
| 1602 | case ARM::VSTMS: |
| 1603 | case ARM::VSTMD_UPD: |
| 1604 | case ARM::VSTMS_UPD: { |
| 1605 | unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); |
| 1606 | return (NumRegs / 2) + (NumRegs % 2) + 1; |
| 1607 | } |
| 1608 | case ARM::LDM_RET: |
| 1609 | case ARM::LDM: |
| 1610 | case ARM::LDM_UPD: |
| 1611 | case ARM::STM: |
| 1612 | case ARM::STM_UPD: |
| 1613 | case ARM::tLDM: |
| 1614 | case ARM::tLDM_UPD: |
| 1615 | case ARM::tSTM_UPD: |
| 1616 | case ARM::tPOP_RET: |
| 1617 | case ARM::tPOP: |
| 1618 | case ARM::tPUSH: |
| 1619 | case ARM::t2LDM_RET: |
| 1620 | case ARM::t2LDM: |
| 1621 | case ARM::t2LDM_UPD: |
| 1622 | case ARM::t2STM: |
| 1623 | case ARM::t2STM_UPD: { |
Evan Cheng | 3ef1c87 | 2010-09-10 01:29:16 +0000 | [diff] [blame] | 1624 | unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; |
| 1625 | if (Subtarget.isCortexA8()) { |
| 1626 | // 4 registers would be issued: 1, 2, 1. |
| 1627 | // 5 registers would be issued: 1, 2, 2. |
| 1628 | return 1 + (NumRegs / 2); |
| 1629 | } else if (Subtarget.isCortexA9()) { |
| 1630 | UOps = (NumRegs / 2); |
| 1631 | // If there are odd number of registers or if it's not 64-bit aligned, |
| 1632 | // then it takes an extra AGU (Address Generation Unit) cycle. |
| 1633 | if ((NumRegs % 2) || |
| 1634 | !MI->hasOneMemOperand() || |
| 1635 | (*MI->memoperands_begin())->getAlignment() < 8) |
| 1636 | ++UOps; |
| 1637 | return UOps; |
| 1638 | } else { |
| 1639 | // Assume the worst. |
| 1640 | return NumRegs; |
Michael J. Spencer | 2bbb769 | 2010-10-05 06:00:33 +0000 | [diff] [blame] | 1641 | } |
Evan Cheng | 5f54ce3 | 2010-09-09 18:18:55 +0000 | [diff] [blame] | 1642 | } |
| 1643 | } |
| 1644 | } |