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gerrit-public.fairphone.software / kernel / msm-4.19 / cab82b76f30cecfc09eeeb8a7b1bb78de2e0dadc / . / arch / arm / boot / dts / am33xx.dtsi
blob: 2fbafb83507203f6609ab798b80024b079290514 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]86 am33xx_pinmux: pinmux@44e10800 {
87 compatible = "pinctrl-single";
88 reg = <0x44e10800 0x0238>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-single,register-width = <32>;
92 pinctrl-single,function-mask = <0x7f>;
93 };
94
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]95 /*
96 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]97 * The real AM33XX interconnect network is quite complex. Since
98 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]99 * for the moment, just use a fake OCP bus entry to represent
100 * the whole bus hierarchy.
101 */
102 ocp {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges;
107 ti,hwmods = "l3_main";
108
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]109 prcm: prcm@44e00000 {
110 compatible = "ti,am3-prcm";
111 reg = <0x44e00000 0x4000>;
112
113 prcm_clocks: clocks {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 };
117
118 prcm_clockdomains: clockdomains {
119 };
120 };
121
122 scrm: scrm@44e10000 {
123 compatible = "ti,am3-scrm";
124 reg = <0x44e10000 0x2000>;
125
126 scrm_clocks: clocks {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
130
131 scrm_clockdomains: clockdomains {
132 };
133 };
134
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]135 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame^]136 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]137 interrupt-controller;
138 #interrupt-cells = <1>;
139 ti,intc-size = <128>;
140 reg = <0x48200000 0x1000>;
141 };
142
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]143 edma: edma@49000000 {
144 compatible = "ti,edma3";
145 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
146 reg = <0x49000000 0x10000>,
Thomas Gleixnercf7eb972014-04-13 20:44:46 +0200[diff] [blame]147 <0x44e10f90 0x40>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]148 interrupts = <12 13 14>;
149 #dma-cells = <1>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]150 };
151
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]152 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]153 compatible = "ti,omap4-gpio";
154 ti,hwmods = "gpio1";
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]158 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]159 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]160 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]161 };
162
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]163 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]164 compatible = "ti,omap4-gpio";
165 ti,hwmods = "gpio2";
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]169 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]170 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]171 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]172 };
173
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]174 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]175 compatible = "ti,omap4-gpio";
176 ti,hwmods = "gpio3";
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]180 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]181 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]182 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]183 };
184
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]185 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 compatible = "ti,omap4-gpio";
187 ti,hwmods = "gpio4";
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]191 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]192 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]193 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]194 };
195
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]196 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]197 compatible = "ti,omap3-uart";
198 ti,hwmods = "uart1";
199 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]200 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]201 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]202 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]203 };
204
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]205 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]206 compatible = "ti,omap3-uart";
207 ti,hwmods = "uart2";
208 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]209 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]210 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]211 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]212 };
213
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]214 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]215 compatible = "ti,omap3-uart";
216 ti,hwmods = "uart3";
217 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]218 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]219 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]220 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]221 };
222
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]223 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]224 compatible = "ti,omap3-uart";
225 ti,hwmods = "uart4";
226 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]227 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]228 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]229 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]230 };
231
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]232 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]233 compatible = "ti,omap3-uart";
234 ti,hwmods = "uart5";
235 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]236 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]237 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]238 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]239 };
240
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]241 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]242 compatible = "ti,omap3-uart";
243 ti,hwmods = "uart6";
244 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]245 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]246 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]247 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]248 };
249
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]250 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]251 compatible = "ti,omap4-i2c";
252 #address-cells = <1>;
253 #size-cells = <0>;
254 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]255 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]256 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]257 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]258 };
259
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]260 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]261 compatible = "ti,omap4-i2c";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]265 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]266 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]267 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]268 };
269
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]270 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]271 compatible = "ti,omap4-i2c";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]275 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]276 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]277 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]278 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]279
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]280 mmc1: mmc@48060000 {
281 compatible = "ti,omap4-hsmmc";
282 ti,hwmods = "mmc1";
283 ti,dual-volt;
284 ti,needs-special-reset;
285 ti,needs-special-hs-handling;
286 dmas = <&edma 24
287 &edma 25>;
288 dma-names = "tx", "rx";
289 interrupts = <64>;
290 interrupt-parent = <&intc>;
291 reg = <0x48060000 0x1000>;
292 status = "disabled";
293 };
294
295 mmc2: mmc@481d8000 {
296 compatible = "ti,omap4-hsmmc";
297 ti,hwmods = "mmc2";
298 ti,needs-special-reset;
299 dmas = <&edma 2
300 &edma 3>;
301 dma-names = "tx", "rx";
302 interrupts = <28>;
303 interrupt-parent = <&intc>;
304 reg = <0x481d8000 0x1000>;
305 status = "disabled";
306 };
307
308 mmc3: mmc@47810000 {
309 compatible = "ti,omap4-hsmmc";
310 ti,hwmods = "mmc3";
311 ti,needs-special-reset;
312 interrupts = <29>;
313 interrupt-parent = <&intc>;
314 reg = <0x47810000 0x1000>;
315 status = "disabled";
316 };
317
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]318 hwspinlock: spinlock@480ca000 {
319 compatible = "ti,omap4-hwspinlock";
320 reg = <0x480ca000 0x1000>;
321 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]322 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]323 };
324
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]325 wdt2: wdt@44e35000 {
326 compatible = "ti,omap3-wdt";
327 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]328 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]329 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]330 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]331
332 dcan0: d_can@481cc000 {
333 compatible = "bosch,d_can";
334 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]335 reg = <0x481cc000 0x2000
336 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]337 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]338 status = "disabled";
339 };
340
341 dcan1: d_can@481d0000 {
342 compatible = "bosch,d_can";
343 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]344 reg = <0x481d0000 0x2000
345 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]346 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]347 status = "disabled";
348 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]349
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]350 mailbox: mailbox@480C8000 {
351 compatible = "ti,omap4-mailbox";
352 reg = <0x480C8000 0x200>;
353 interrupts = <77>;
354 ti,hwmods = "mailbox";
355 ti,mbox-num-users = <4>;
356 ti,mbox-num-fifos = <8>;
357 };
358
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]359 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]360 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]361 reg = <0x44e31000 0x400>;
362 interrupts = <67>;
363 ti,hwmods = "timer1";
364 ti,timer-alwon;
365 };
366
367 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]368 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]369 reg = <0x48040000 0x400>;
370 interrupts = <68>;
371 ti,hwmods = "timer2";
372 };
373
374 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]375 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]376 reg = <0x48042000 0x400>;
377 interrupts = <69>;
378 ti,hwmods = "timer3";
379 };
380
381 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]382 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]383 reg = <0x48044000 0x400>;
384 interrupts = <92>;
385 ti,hwmods = "timer4";
386 ti,timer-pwm;
387 };
388
389 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]390 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]391 reg = <0x48046000 0x400>;
392 interrupts = <93>;
393 ti,hwmods = "timer5";
394 ti,timer-pwm;
395 };
396
397 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]398 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]399 reg = <0x48048000 0x400>;
400 interrupts = <94>;
401 ti,hwmods = "timer6";
402 ti,timer-pwm;
403 };
404
405 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]406 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]407 reg = <0x4804a000 0x400>;
408 interrupts = <95>;
409 ti,hwmods = "timer7";
410 ti,timer-pwm;
411 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]412
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]413 rtc: rtc@44e3e000 {
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]414 compatible = "ti,da830-rtc";
415 reg = <0x44e3e000 0x1000>;
416 interrupts = <75
417 76>;
418 ti,hwmods = "rtc";
419 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]420
421 spi0: spi@48030000 {
422 compatible = "ti,omap4-mcspi";
423 #address-cells = <1>;
424 #size-cells = <0>;
425 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]426 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]427 ti,spi-num-cs = <2>;
428 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]429 dmas = <&edma 16
430 &edma 17
431 &edma 18
432 &edma 19>;
433 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]434 status = "disabled";
435 };
436
437 spi1: spi@481a0000 {
438 compatible = "ti,omap4-mcspi";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]442 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]443 ti,spi-num-cs = <2>;
444 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]445 dmas = <&edma 42
446 &edma 43
447 &edma 44
448 &edma 45>;
449 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]450 status = "disabled";
451 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]452
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]453 usb: usb@47400000 {
454 compatible = "ti,am33xx-usb";
455 reg = <0x47400000 0x1000>;
456 ranges;
457 #address-cells = <1>;
458 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]459 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]460 status = "disabled";
461
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]462 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]463 compatible = "ti,am335x-usb-ctrl-module";
464 reg = <0x44e10620 0x10
465 0x44e10648 0x4>;
466 reg-names = "phy_ctrl", "wakeup";
467 status = "disabled";
468 };
469
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]470 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]471 compatible = "ti,am335x-usb-phy";
472 reg = <0x47401300 0x100>;
473 reg-names = "phy";
474 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]475 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]476 };
477
478 usb0: usb@47401000 {
479 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]480 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]481 reg = <0x47401400 0x400
482 0x47401000 0x200>;
483 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]484
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]485 interrupts = <18>;
486 interrupt-names = "mc";
487 dr_mode = "otg";
488 mentor,multipoint = <1>;
489 mentor,num-eps = <16>;
490 mentor,ram-bits = <12>;
491 mentor,power = <500>;
492 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]493
494 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
495 &cppi41dma 2 0 &cppi41dma 3 0
496 &cppi41dma 4 0 &cppi41dma 5 0
497 &cppi41dma 6 0 &cppi41dma 7 0
498 &cppi41dma 8 0 &cppi41dma 9 0
499 &cppi41dma 10 0 &cppi41dma 11 0
500 &cppi41dma 12 0 &cppi41dma 13 0
501 &cppi41dma 14 0 &cppi41dma 0 1
502 &cppi41dma 1 1 &cppi41dma 2 1
503 &cppi41dma 3 1 &cppi41dma 4 1
504 &cppi41dma 5 1 &cppi41dma 6 1
505 &cppi41dma 7 1 &cppi41dma 8 1
506 &cppi41dma 9 1 &cppi41dma 10 1
507 &cppi41dma 11 1 &cppi41dma 12 1
508 &cppi41dma 13 1 &cppi41dma 14 1>;
509 dma-names =
510 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
511 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
512 "rx14", "rx15",
513 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
514 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
515 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]516 };
517
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]518 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]519 compatible = "ti,am335x-usb-phy";
520 reg = <0x47401b00 0x100>;
521 reg-names = "phy";
522 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]523 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]524 };
525
526 usb1: usb@47401800 {
527 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]528 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]529 reg = <0x47401c00 0x400
530 0x47401800 0x200>;
531 reg-names = "mc", "control";
532 interrupts = <19>;
533 interrupt-names = "mc";
534 dr_mode = "otg";
535 mentor,multipoint = <1>;
536 mentor,num-eps = <16>;
537 mentor,ram-bits = <12>;
538 mentor,power = <500>;
539 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]540
541 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
542 &cppi41dma 17 0 &cppi41dma 18 0
543 &cppi41dma 19 0 &cppi41dma 20 0
544 &cppi41dma 21 0 &cppi41dma 22 0
545 &cppi41dma 23 0 &cppi41dma 24 0
546 &cppi41dma 25 0 &cppi41dma 26 0
547 &cppi41dma 27 0 &cppi41dma 28 0
548 &cppi41dma 29 0 &cppi41dma 15 1
549 &cppi41dma 16 1 &cppi41dma 17 1
550 &cppi41dma 18 1 &cppi41dma 19 1
551 &cppi41dma 20 1 &cppi41dma 21 1
552 &cppi41dma 22 1 &cppi41dma 23 1
553 &cppi41dma 24 1 &cppi41dma 25 1
554 &cppi41dma 26 1 &cppi41dma 27 1
555 &cppi41dma 28 1 &cppi41dma 29 1>;
556 dma-names =
557 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
558 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
559 "rx14", "rx15",
560 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
561 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
562 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]563 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]564
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]565 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]566 compatible = "ti,am3359-cppi41";
567 reg = <0x47400000 0x1000
568 0x47402000 0x1000
569 0x47403000 0x1000
570 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]571 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]572 interrupts = <17>;
573 interrupt-names = "glue";
574 #dma-cells = <2>;
575 #dma-channels = <30>;
576 #dma-requests = <256>;
577 status = "disabled";
578 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]579 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]580
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]581 epwmss0: epwmss@48300000 {
582 compatible = "ti,am33xx-pwmss";
583 reg = <0x48300000 0x10>;
584 ti,hwmods = "epwmss0";
585 #address-cells = <1>;
586 #size-cells = <1>;
587 status = "disabled";
588 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
589 0x48300180 0x48300180 0x80 /* EQEP */
590 0x48300200 0x48300200 0x80>; /* EHRPWM */
591
592 ecap0: ecap@48300100 {
593 compatible = "ti,am33xx-ecap";
594 #pwm-cells = <3>;
595 reg = <0x48300100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]596 interrupts = <31>;
597 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]598 ti,hwmods = "ecap0";
599 status = "disabled";
600 };
601
602 ehrpwm0: ehrpwm@48300200 {
603 compatible = "ti,am33xx-ehrpwm";
604 #pwm-cells = <3>;
605 reg = <0x48300200 0x80>;
606 ti,hwmods = "ehrpwm0";
607 status = "disabled";
608 };
609 };
610
611 epwmss1: epwmss@48302000 {
612 compatible = "ti,am33xx-pwmss";
613 reg = <0x48302000 0x10>;
614 ti,hwmods = "epwmss1";
615 #address-cells = <1>;
616 #size-cells = <1>;
617 status = "disabled";
618 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
619 0x48302180 0x48302180 0x80 /* EQEP */
620 0x48302200 0x48302200 0x80>; /* EHRPWM */
621
622 ecap1: ecap@48302100 {
623 compatible = "ti,am33xx-ecap";
624 #pwm-cells = <3>;
625 reg = <0x48302100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]626 interrupts = <47>;
627 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]628 ti,hwmods = "ecap1";
629 status = "disabled";
630 };
631
632 ehrpwm1: ehrpwm@48302200 {
633 compatible = "ti,am33xx-ehrpwm";
634 #pwm-cells = <3>;
635 reg = <0x48302200 0x80>;
636 ti,hwmods = "ehrpwm1";
637 status = "disabled";
638 };
639 };
640
641 epwmss2: epwmss@48304000 {
642 compatible = "ti,am33xx-pwmss";
643 reg = <0x48304000 0x10>;
644 ti,hwmods = "epwmss2";
645 #address-cells = <1>;
646 #size-cells = <1>;
647 status = "disabled";
648 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
649 0x48304180 0x48304180 0x80 /* EQEP */
650 0x48304200 0x48304200 0x80>; /* EHRPWM */
651
652 ecap2: ecap@48304100 {
653 compatible = "ti,am33xx-ecap";
654 #pwm-cells = <3>;
655 reg = <0x48304100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]656 interrupts = <61>;
657 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]658 ti,hwmods = "ecap2";
659 status = "disabled";
660 };
661
662 ehrpwm2: ehrpwm@48304200 {
663 compatible = "ti,am33xx-ehrpwm";
664 #pwm-cells = <3>;
665 reg = <0x48304200 0x80>;
666 ti,hwmods = "ehrpwm2";
667 status = "disabled";
668 };
669 };
670
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]671 mac: ethernet@4a100000 {
672 compatible = "ti,cpsw";
673 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]674 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
675 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]676 cpdma_channels = <8>;
677 ale_entries = <1024>;
678 bd_ram_size = <0x2000>;
679 no_bd_ram = <0>;
680 rx_descs = <64>;
681 mac_control = <0x20>;
682 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]683 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]684 cpts_clock_mult = <0x80000000>;
685 cpts_clock_shift = <29>;
686 reg = <0x4a100000 0x800
687 0x4a101200 0x100>;
688 #address-cells = <1>;
689 #size-cells = <1>;
690 interrupt-parent = <&intc>;
691 /*
692 * c0_rx_thresh_pend
693 * c0_rx_pend
694 * c0_tx_pend
695 * c0_misc_pend
696 */
697 interrupts = <40 41 42 43>;
698 ranges;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]699 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]700
701 davinci_mdio: mdio@4a101000 {
702 compatible = "ti,davinci_mdio";
703 #address-cells = <1>;
704 #size-cells = <0>;
705 ti,hwmods = "davinci_mdio";
706 bus_freq = <1000000>;
707 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]708 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]709 };
710
711 cpsw_emac0: slave@4a100200 {
712 /* Filled in by U-Boot */
713 mac-address = [ 00 00 00 00 00 00 ];
714 };
715
716 cpsw_emac1: slave@4a100300 {
717 /* Filled in by U-Boot */
718 mac-address = [ 00 00 00 00 00 00 ];
719 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]720
721 phy_sel: cpsw-phy-sel@44e10650 {
722 compatible = "ti,am3352-cpsw-phy-sel";
723 reg= <0x44e10650 0x4>;
724 reg-names = "gmii-sel";
725 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]726 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]727
728 ocmcram: ocmcram@40300000 {
729 compatible = "ti,am3352-ocmcram";
730 reg = <0x40300000 0x10000>;
731 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]732 };
733
734 wkup_m3: wkup_m3@44d00000 {
735 compatible = "ti,am3353-wkup-m3";
736 reg = <0x44d00000 0x4000 /* M3 UMEM */
737 0x44d80000 0x2000>; /* M3 DMEM */
738 ti,hwmods = "wkup_m3";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]739 ti,no-reset-on-init;
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]740 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]741
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]742 elm: elm@48080000 {
743 compatible = "ti,am3352-elm";
744 reg = <0x48080000 0x2000>;
745 interrupts = <4>;
746 ti,hwmods = "elm";
747 status = "disabled";
748 };
749
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]750 lcdc: lcdc@4830e000 {
751 compatible = "ti,am33xx-tilcdc";
752 reg = <0x4830e000 0x1000>;
753 interrupt-parent = <&intc>;
754 interrupts = <36>;
755 ti,hwmods = "lcdc";
756 status = "disabled";
757 };
758
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]759 tscadc: tscadc@44e0d000 {
760 compatible = "ti,am3359-tscadc";
761 reg = <0x44e0d000 0x1000>;
762 interrupt-parent = <&intc>;
763 interrupts = <16>;
764 ti,hwmods = "adc_tsc";
765 status = "disabled";
766
767 tsc {
768 compatible = "ti,am3359-tsc";
769 };
770 am335x_adc: adc {
771 #io-channel-cells = <1>;
772 compatible = "ti,am3359-adc";
773 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]774 };
775
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]776 gpmc: gpmc@50000000 {
777 compatible = "ti,am3352-gpmc";
778 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]779 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]780 reg = <0x50000000 0x2000>;
781 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]782 gpmc,num-cs = <7>;
783 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]784 #address-cells = <2>;
785 #size-cells = <1>;
786 status = "disabled";
787 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]788
789 sham: sham@53100000 {
790 compatible = "ti,omap4-sham";
791 ti,hwmods = "sham";
792 reg = <0x53100000 0x200>;
793 interrupts = <109>;
794 dmas = <&edma 36>;
795 dma-names = "rx";
796 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]797
798 aes: aes@53500000 {
799 compatible = "ti,omap4-aes";
800 ti,hwmods = "aes";
801 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]802 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]803 dmas = <&edma 6>,
804 <&edma 5>;
805 dma-names = "tx", "rx";
806 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]807
808 mcasp0: mcasp@48038000 {
809 compatible = "ti,am33xx-mcasp-audio";
810 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]811 reg = <0x48038000 0x2000>,
812 <0x46000000 0x400000>;
813 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]814 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]815 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]816 status = "disabled";
817 dmas = <&edma 8>,
818 <&edma 9>;
819 dma-names = "tx", "rx";
820 };
821
822 mcasp1: mcasp@4803C000 {
823 compatible = "ti,am33xx-mcasp-audio";
824 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]825 reg = <0x4803C000 0x2000>,
826 <0x46400000 0x400000>;
827 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]828 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]829 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]830 status = "disabled";
831 dmas = <&edma 10>,
832 <&edma 11>;
833 dma-names = "tx", "rx";
834 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]835
836 rng: rng@48310000 {
837 compatible = "ti,omap4-rng";
838 ti,hwmods = "rng";
839 reg = <0x48310000 0x2000>;
840 interrupts = <111>;
841 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]842 };
843};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]844
845/include/ "am33xx-clocks.dtsi"