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Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +01001/*
Ivo van Doorn96481b22010-08-06 20:47:57 +02002 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
Ivo van Doorna5ea2f02010-06-14 22:13:15 +02003 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
Gertjan van Wingerde9c9a0d12009-11-08 16:39:55 +01004 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Gertjan van Wingerdecce5fc42009-11-10 22:42:40 +01005 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +01006
Gertjan van Wingerde9c9a0d12009-11-08 16:39:55 +01007 Based on the original rt2800pci.c and rt2800usb.c.
Gertjan van Wingerde9c9a0d12009-11-08 16:39:55 +01008 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +010014 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
Ivo van Doornf31c9a82010-07-11 12:30:37 +020037#include <linux/crc-ccitt.h>
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +010038#include <linux/kernel.h>
39#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090040#include <linux/slab.h>
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +010041
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +010046/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
Helmut Schaabaff8002010-04-28 09:58:59 +020070static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +010087static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +010089{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
Ivo van Doornefc7d362010-06-29 21:49:26 +0200104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100111
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +0100112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
Ivo van Doornefc7d362010-06-29 21:49:26 +0200132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100143
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +0100144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100167
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +0100168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100198
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +0100199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
Gertjan van Wingerdeee303e52009-11-23 22:44:49 +0100230 /*
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +0100231 * SOC devices don't support MCU requests.
Gertjan van Wingerdeee303e52009-11-23 22:44:49 +0100232 */
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +0100233 if (rt2x00_is_soc(rt2x00dev))
Gertjan van Wingerdeee303e52009-11-23 22:44:49 +0100234 return;
Bartlomiej Zolnierkiewicz89297422009-11-04 18:36:24 +0100235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100257
Ivo van Doorn5ffddc42010-08-30 21:13:08 +0200258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
Gertjan van Wingerde67a4c1e2009-12-30 11:36:32 +0100275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
Helmut Schaa08e53102010-11-04 20:37:47 +0100280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
Gertjan van Wingerde67a4c1e2009-12-30 11:36:32 +0100284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
Helmut Schaa08e53102010-11-04 20:37:47 +0100290 msleep(10);
Gertjan van Wingerde67a4c1e2009-12-30 11:36:32 +0100291 }
292
Jakub Kicinski52b82432012-04-03 03:40:49 +0200293 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
Gertjan van Wingerde67a4c1e2009-12-30 11:36:32 +0100294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
Jakub Kicinskif7b395e2012-04-03 03:40:47 +0200298void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
299{
300 u32 reg;
301
302 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
303 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
304 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
309}
310EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
311
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200312static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
313{
314 u16 fw_crc;
315 u16 crc;
316
317 /*
318 * The last 2 bytes in the firmware array are the crc checksum itself,
319 * this means that we should never pass those 2 bytes to the crc
320 * algorithm.
321 */
322 fw_crc = (data[len - 2] << 8 | data[len - 1]);
323
324 /*
325 * Use the crc ccitt algorithm.
326 * This will return the same value as the legacy driver which
327 * used bit ordering reversion on the both the firmware bytes
328 * before input input as well as on the final output.
329 * Obviously using crc ccitt directly is much more efficient.
330 */
331 crc = crc_ccitt(~0, data, len - 2);
332
333 /*
334 * There is a small difference between the crc-itu-t + bitrev and
335 * the crc-ccitt crc calculation. In the latter method the 2 bytes
336 * will be swapped, use swab16 to convert the crc to the correct
337 * value.
338 */
339 crc = swab16(crc);
340
341 return fw_crc == crc;
342}
343
344int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
345 const u8 *data, const size_t len)
346{
347 size_t offset = 0;
348 size_t fw_len;
349 bool multiple;
350
351 /*
352 * PCI(e) & SOC devices require firmware with a length
353 * of 8kb. USB devices require firmware files with a length
354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length
Woody Hunga89534e2012-06-13 15:01:16 +0800357 * which is a multiple of 4kb. The firmware for rt3290 chip also
358 * have a length which is a multiple of 4kb.
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200359 */
Woody Hunga89534e2012-06-13 15:01:16 +0800360 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200361 fw_len = 4096;
Woody Hunga89534e2012-06-13 15:01:16 +0800362 else
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200363 fw_len = 8192;
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200364
Woody Hunga89534e2012-06-13 15:01:16 +0800365 multiple = true;
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200366 /*
367 * Validate the firmware length
368 */
369 if (len != fw_len && (!multiple || (len % fw_len) != 0))
370 return FW_BAD_LENGTH;
371
372 /*
373 * Check if the chipset requires one of the upper parts
374 * of the firmware.
375 */
376 if (rt2x00_is_usb(rt2x00dev) &&
377 !rt2x00_rt(rt2x00dev, RT2860) &&
378 !rt2x00_rt(rt2x00dev, RT2872) &&
379 !rt2x00_rt(rt2x00dev, RT3070) &&
380 ((len / fw_len) == 1))
381 return FW_BAD_VERSION;
382
383 /*
384 * 8kb firmware files must be checked as if it were
385 * 2 separate firmware files.
386 */
387 while (offset < len) {
388 if (!rt2800_check_firmware_crc(data + offset, fw_len))
389 return FW_BAD_CRC;
390
391 offset += fw_len;
392 }
393
394 return FW_OK;
395}
396EXPORT_SYMBOL_GPL(rt2800_check_firmware);
397
398int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
399 const u8 *data, const size_t len)
400{
401 unsigned int i;
402 u32 reg;
403
404 /*
Ivo van Doornb9eca242010-08-30 21:13:54 +0200405 * If driver doesn't wake up firmware here,
406 * rt2800_load_firmware will hang forever when interface is up again.
407 */
408 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
409
410 /*
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200411 * Wait for stable hardware.
412 */
Ivo van Doorn5ffddc42010-08-30 21:13:08 +0200413 if (rt2800_wait_csr_ready(rt2x00dev))
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200414 return -EBUSY;
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200415
Gabor Juhosadde5882011-03-03 11:46:45 +0100416 if (rt2x00_is_pci(rt2x00dev)) {
Woody Hunga89534e2012-06-13 15:01:16 +0800417 if (rt2x00_rt(rt2x00dev, RT3290) ||
418 rt2x00_rt(rt2x00dev, RT3572) ||
John Li2ed71882012-02-17 17:33:06 +0800419 rt2x00_rt(rt2x00dev, RT5390) ||
420 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +0100421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
422 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
423 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
424 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
425 }
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200426 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
Gabor Juhosadde5882011-03-03 11:46:45 +0100427 }
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200428
Jakub Kicinskib7e1d222012-04-03 03:40:48 +0200429 rt2800_disable_wpdma(rt2x00dev);
430
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200431 /*
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200432 * Write firmware to the device.
433 */
434 rt2800_drv_write_firmware(rt2x00dev, data, len);
435
436 /*
437 * Wait for device to stabilize.
438 */
439 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
440 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
441 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
442 break;
443 msleep(1);
444 }
445
446 if (i == REGISTER_BUSY_COUNT) {
447 ERROR(rt2x00dev, "PBF system register not ready.\n");
448 return -EBUSY;
449 }
450
451 /*
Stanislaw Gruszka4ed1dd22012-01-24 14:09:07 +0100452 * Disable DMA, will be reenabled later when enabling
453 * the radio.
454 */
Jakub Kicinskif7b395e2012-04-03 03:40:47 +0200455 rt2800_disable_wpdma(rt2x00dev);
Stanislaw Gruszka4ed1dd22012-01-24 14:09:07 +0100456
457 /*
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200458 * Initialize firmware.
459 */
460 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
461 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
Stanislaw Gruszka0c17cf92012-01-24 14:09:06 +0100462 if (rt2x00_is_usb(rt2x00dev))
463 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
Ivo van Doornf31c9a82010-07-11 12:30:37 +0200464 msleep(1);
465
466 return 0;
467}
468EXPORT_SYMBOL_GPL(rt2800_load_firmware);
469
Ivo van Doorn0c5879b2010-08-06 20:47:20 +0200470void rt2800_write_tx_data(struct queue_entry *entry,
471 struct txentry_desc *txdesc)
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200472{
Ivo van Doorn0c5879b2010-08-06 20:47:20 +0200473 __le32 *txwi = rt2800_drv_get_txwi(entry);
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200474 u32 word;
475
476 /*
477 * Initialize TX Info descriptor
478 */
479 rt2x00_desc_read(txwi, 0, &word);
480 rt2x00_set_field32(&word, TXWI_W0_FRAG,
481 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
Ivo van Doorn84804cd2010-08-06 20:46:19 +0200482 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
483 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200484 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
485 rt2x00_set_field32(&word, TXWI_W0_TS,
486 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
487 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
488 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
Helmut Schaa26a1d072011-03-03 19:42:35 +0100489 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
490 txdesc->u.ht.mpdu_density);
491 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
492 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200493 rt2x00_set_field32(&word, TXWI_W0_BW,
494 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
495 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
496 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
Helmut Schaa26a1d072011-03-03 19:42:35 +0100497 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200498 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
499 rt2x00_desc_write(txwi, 0, word);
500
501 rt2x00_desc_read(txwi, 1, &word);
502 rt2x00_set_field32(&word, TXWI_W1_ACK,
503 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
504 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
505 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
Helmut Schaa26a1d072011-03-03 19:42:35 +0100506 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200507 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
508 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
Helmut Schaaa2b13282011-09-08 14:38:01 +0200509 txdesc->key_idx : txdesc->u.ht.wcid);
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200510 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
511 txdesc->length);
Helmut Schaa2b23cda2010-11-04 20:38:15 +0100512 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
Ivo van Doornbc8a9792010-10-02 11:32:43 +0200513 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200514 rt2x00_desc_write(txwi, 1, word);
515
516 /*
517 * Always write 0 to IV/EIV fields, hardware will insert the IV
518 * from the IVEIV register when TXD_W3_WIV is set to 0.
519 * When TXD_W3_WIV is set to 1 it will use the IV data
520 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
521 * crypto entry in the registers should be used to encrypt the frame.
522 */
523 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
524 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
525}
Ivo van Doorn0c5879b2010-08-06 20:47:20 +0200526EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
Gertjan van Wingerde59679b92010-05-08 23:40:21 +0200527
Helmut Schaaff6133b2010-10-09 13:34:11 +0200528static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200529{
Luigi Tarenga7fc41752012-01-31 18:51:23 +0100530 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
531 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
532 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
Ivo van Doorn74861922010-07-11 12:23:50 +0200533 u16 eeprom;
534 u8 offset0;
535 u8 offset1;
536 u8 offset2;
537
Ivo van Doorne5ef5ba2010-08-06 20:49:27 +0200538 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
Ivo van Doorn74861922010-07-11 12:23:50 +0200539 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
540 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
541 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
542 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
543 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
544 } else {
545 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
546 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
547 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
548 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
549 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
550 }
551
552 /*
553 * Convert the value from the descriptor into the RSSI value
554 * If the value in the descriptor is 0, it is considered invalid
555 * and the default (extremely low) rssi value is assumed
556 */
557 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
558 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
559 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
560
561 /*
562 * mac80211 only accepts a single RSSI value. Calculating the
563 * average doesn't deliver a fair answer either since -60:-60 would
564 * be considered equally good as -50:-70 while the second is the one
565 * which gives less energy...
566 */
567 rssi0 = max(rssi0, rssi1);
Luigi Tarenga7fc41752012-01-31 18:51:23 +0100568 return (int)max(rssi0, rssi2);
Ivo van Doorn74861922010-07-11 12:23:50 +0200569}
570
571void rt2800_process_rxwi(struct queue_entry *entry,
572 struct rxdone_entry_desc *rxdesc)
573{
574 __le32 *rxwi = (__le32 *) entry->skb->data;
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200575 u32 word;
576
577 rt2x00_desc_read(rxwi, 0, &word);
578
579 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
580 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
581
582 rt2x00_desc_read(rxwi, 1, &word);
583
584 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
585 rxdesc->flags |= RX_FLAG_SHORT_GI;
586
587 if (rt2x00_get_field32(word, RXWI_W1_BW))
588 rxdesc->flags |= RX_FLAG_40MHZ;
589
590 /*
591 * Detect RX rate, always use MCS as signal type.
592 */
593 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
594 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
595 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
596
597 /*
598 * Mask of 0x8 bit to remove the short preamble flag.
599 */
600 if (rxdesc->rate_mode == RATE_MODE_CCK)
601 rxdesc->signal &= ~0x8;
602
603 rt2x00_desc_read(rxwi, 2, &word);
604
Ivo van Doorn74861922010-07-11 12:23:50 +0200605 /*
606 * Convert descriptor AGC value to RSSI value.
607 */
608 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200609
610 /*
611 * Remove RXWI descriptor from start of buffer.
612 */
Ivo van Doorn74861922010-07-11 12:23:50 +0200613 skb_pull(entry->skb, RXWI_DESC_SIZE);
Gertjan van Wingerde2de64dd2010-05-08 23:40:22 +0200614}
615EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
616
Helmut Schaa31937c42011-09-07 20:10:02 +0200617void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
Helmut Schaa14433332010-10-02 11:27:03 +0200618{
619 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
Helmut Schaab34793e2010-10-02 11:34:56 +0200620 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
Helmut Schaa14433332010-10-02 11:27:03 +0200621 struct txdone_entry_desc txdesc;
622 u32 word;
623 u16 mcs, real_mcs;
Helmut Schaab34793e2010-10-02 11:34:56 +0200624 int aggr, ampdu;
Helmut Schaa14433332010-10-02 11:27:03 +0200625
626 /*
627 * Obtain the status about this packet.
628 */
629 txdesc.flags = 0;
Helmut Schaa14433332010-10-02 11:27:03 +0200630 rt2x00_desc_read(txwi, 0, &word);
Helmut Schaab34793e2010-10-02 11:34:56 +0200631
Helmut Schaa14433332010-10-02 11:27:03 +0200632 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
Helmut Schaab34793e2010-10-02 11:34:56 +0200633 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
634
Helmut Schaa14433332010-10-02 11:27:03 +0200635 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
Helmut Schaab34793e2010-10-02 11:34:56 +0200636 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
637
638 /*
639 * If a frame was meant to be sent as a single non-aggregated MPDU
640 * but ended up in an aggregate the used tx rate doesn't correlate
641 * with the one specified in the TXWI as the whole aggregate is sent
642 * with the same rate.
643 *
644 * For example: two frames are sent to rt2x00, the first one sets
645 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
646 * and requests MCS15. If the hw aggregates both frames into one
647 * AMDPU the tx status for both frames will contain MCS7 although
648 * the frame was sent successfully.
649 *
650 * Hence, replace the requested rate with the real tx rate to not
651 * confuse the rate control algortihm by providing clearly wrong
652 * data.
653 */
Helmut Schaa5356d962011-03-03 19:40:33 +0100654 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
Helmut Schaab34793e2010-10-02 11:34:56 +0200655 skbdesc->tx_rate_idx = real_mcs;
656 mcs = real_mcs;
657 }
Helmut Schaa14433332010-10-02 11:27:03 +0200658
Helmut Schaaf16d2db2011-03-28 13:35:21 +0200659 if (aggr == 1 || ampdu == 1)
660 __set_bit(TXDONE_AMPDU, &txdesc.flags);
661
Helmut Schaa14433332010-10-02 11:27:03 +0200662 /*
663 * Ralink has a retry mechanism using a global fallback
664 * table. We setup this fallback table to try the immediate
665 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
666 * always contains the MCS used for the last transmission, be
667 * it successful or not.
668 */
669 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
670 /*
671 * Transmission succeeded. The number of retries is
672 * mcs - real_mcs
673 */
674 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
675 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
676 } else {
677 /*
678 * Transmission failed. The number of retries is
679 * always 7 in this case (for a total number of 8
680 * frames sent).
681 */
682 __set_bit(TXDONE_FAILURE, &txdesc.flags);
683 txdesc.retry = rt2x00dev->long_retry;
684 }
685
686 /*
687 * the frame was retried at least once
688 * -> hw used fallback rates
689 */
690 if (txdesc.retry)
691 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
692
693 rt2x00lib_txdone(entry, &txdesc);
694}
695EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
696
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200697void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
698{
699 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
700 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
701 unsigned int beacon_base;
Wolfgang Kufner739fd942010-12-13 12:39:12 +0100702 unsigned int padding_len;
Seth Forsheed76dfc62011-02-14 08:52:25 -0600703 u32 orig_reg, reg;
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200704
705 /*
706 * Disable beaconing while we are reloading the beacon data,
707 * otherwise we might be sending out invalid data.
708 */
709 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
Seth Forsheed76dfc62011-02-14 08:52:25 -0600710 orig_reg = reg;
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200711 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
712 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
713
714 /*
715 * Add space for the TXWI in front of the skb.
716 */
Stanislaw Gruszkab52398b2011-07-30 13:32:56 +0200717 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200718
719 /*
720 * Register descriptor details in skb frame descriptor.
721 */
722 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
723 skbdesc->desc = entry->skb->data;
724 skbdesc->desc_len = TXWI_DESC_SIZE;
725
726 /*
727 * Add the TXWI for the beacon to the skb.
728 */
Ivo van Doorn0c5879b2010-08-06 20:47:20 +0200729 rt2800_write_tx_data(entry, txdesc);
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200730
731 /*
732 * Dump beacon to userspace through debugfs.
733 */
734 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
735
736 /*
Wolfgang Kufner739fd942010-12-13 12:39:12 +0100737 * Write entire beacon with TXWI and padding to register.
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200738 */
Wolfgang Kufner739fd942010-12-13 12:39:12 +0100739 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
Seth Forsheed76dfc62011-02-14 08:52:25 -0600740 if (padding_len && skb_pad(entry->skb, padding_len)) {
741 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
742 /* skb freed by skb_pad() on failure */
743 entry->skb = NULL;
744 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
745 return;
746 }
747
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200748 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
Wolfgang Kufner739fd942010-12-13 12:39:12 +0100749 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
750 entry->skb->len + padding_len);
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200751
752 /*
753 * Enable beaconing again.
754 */
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200755 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
756 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
757
758 /*
759 * Clean up beacon skb.
760 */
761 dev_kfree_skb_any(entry->skb);
762 entry->skb = NULL;
763}
Ivo van Doorn50e888e2010-07-11 12:26:12 +0200764EXPORT_SYMBOL_GPL(rt2800_write_beacon);
Gertjan van Wingerdef0194b22010-06-03 10:51:53 +0200765
Helmut Schaa69cf36a2011-01-30 13:16:03 +0100766static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
767 unsigned int beacon_base)
Helmut Schaafdb87252010-06-29 21:48:06 +0200768{
769 int i;
770
771 /*
772 * For the Beacon base registers we only need to clear
773 * the whole TXWI which (when set to 0) will invalidate
774 * the entire beacon.
775 */
776 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
777 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
778}
779
Helmut Schaa69cf36a2011-01-30 13:16:03 +0100780void rt2800_clear_beacon(struct queue_entry *entry)
781{
782 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
783 u32 reg;
784
785 /*
786 * Disable beaconing while we are reloading the beacon data,
787 * otherwise we might be sending out invalid data.
788 */
789 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
790 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
791 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
792
793 /*
794 * Clear beacon.
795 */
796 rt2800_clear_beacon_register(rt2x00dev,
797 HW_BEACON_OFFSET(entry->entry_idx));
798
799 /*
800 * Enabled beaconing again.
801 */
802 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
803 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
804}
805EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
806
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100807#ifdef CONFIG_RT2X00_LIB_DEBUGFS
808const struct rt2x00debug rt2800_rt2x00debug = {
809 .owner = THIS_MODULE,
810 .csr = {
811 .read = rt2800_register_read,
812 .write = rt2800_register_write,
813 .flags = RT2X00DEBUGFS_OFFSET,
814 .word_base = CSR_REG_BASE,
815 .word_size = sizeof(u32),
816 .word_count = CSR_REG_SIZE / sizeof(u32),
817 },
818 .eeprom = {
819 .read = rt2x00_eeprom_read,
820 .write = rt2x00_eeprom_write,
821 .word_base = EEPROM_BASE,
822 .word_size = sizeof(u16),
823 .word_count = EEPROM_SIZE / sizeof(u16),
824 },
825 .bbp = {
826 .read = rt2800_bbp_read,
827 .write = rt2800_bbp_write,
828 .word_base = BBP_BASE,
829 .word_size = sizeof(u8),
830 .word_count = BBP_SIZE / sizeof(u8),
831 },
832 .rf = {
833 .read = rt2x00_rf_read,
834 .write = rt2800_rf_write,
835 .word_base = RF_BASE,
836 .word_size = sizeof(u32),
837 .word_count = RF_SIZE / sizeof(u32),
838 },
Anisse Astierf2bd7f12012-04-19 15:53:10 +0200839 .rfcsr = {
840 .read = rt2800_rfcsr_read,
841 .write = rt2800_rfcsr_write,
842 .word_base = RFCSR_BASE,
843 .word_size = sizeof(u8),
844 .word_count = RFCSR_SIZE / sizeof(u8),
845 },
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100846};
847EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
848#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
849
850int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
851{
852 u32 reg;
853
Woody Hunga89534e2012-06-13 15:01:16 +0800854 if (rt2x00_rt(rt2x00dev, RT3290)) {
855 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
856 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
857 } else {
858 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
859 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
860 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100861}
862EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
863
864#ifdef CONFIG_RT2X00_LIB_LEDS
865static void rt2800_brightness_set(struct led_classdev *led_cdev,
866 enum led_brightness brightness)
867{
868 struct rt2x00_led *led =
869 container_of(led_cdev, struct rt2x00_led, led_dev);
870 unsigned int enabled = brightness != LED_OFF;
871 unsigned int bg_mode =
872 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
873 unsigned int polarity =
874 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
875 EEPROM_FREQ_LED_POLARITY);
876 unsigned int ledmode =
877 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
878 EEPROM_FREQ_LED_MODE);
Layne Edwards44704e52011-04-18 15:26:00 +0200879 u32 reg;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100880
Layne Edwards44704e52011-04-18 15:26:00 +0200881 /* Check for SoC (SOC devices don't support MCU requests) */
882 if (rt2x00_is_soc(led->rt2x00dev)) {
883 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
884
885 /* Set LED Polarity */
886 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
887
888 /* Set LED Mode */
889 if (led->type == LED_TYPE_RADIO) {
890 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
891 enabled ? 3 : 0);
892 } else if (led->type == LED_TYPE_ASSOC) {
893 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
894 enabled ? 3 : 0);
895 } else if (led->type == LED_TYPE_QUALITY) {
896 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
897 enabled ? 3 : 0);
898 }
899
900 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
901
902 } else {
903 if (led->type == LED_TYPE_RADIO) {
904 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
905 enabled ? 0x20 : 0);
906 } else if (led->type == LED_TYPE_ASSOC) {
907 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
908 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
909 } else if (led->type == LED_TYPE_QUALITY) {
910 /*
911 * The brightness is divided into 6 levels (0 - 5),
912 * The specs tell us the following levels:
913 * 0, 1 ,3, 7, 15, 31
914 * to determine the level in a simple way we can simply
915 * work with bitshifting:
916 * (1 << level) - 1
917 */
918 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
919 (1 << brightness / (LED_FULL / 6)) - 1,
920 polarity);
921 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100922 }
923}
924
Gertjan van Wingerdeb3579d62009-12-30 11:36:34 +0100925static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100926 struct rt2x00_led *led, enum led_type type)
927{
928 led->rt2x00dev = rt2x00dev;
929 led->type = type;
930 led->led_dev.brightness_set = rt2800_brightness_set;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100931 led->flags = LED_INITIALIZED;
932}
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100933#endif /* CONFIG_RT2X00_LIB_LEDS */
934
935/*
936 * Configuration handlers.
937 */
Helmut Schaaa2b13282011-09-08 14:38:01 +0200938static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
939 const u8 *address,
940 int wcid)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100941{
942 struct mac_wcid_entry wcid_entry;
Helmut Schaaa2b13282011-09-08 14:38:01 +0200943 u32 offset;
944
945 offset = MAC_WCID_ENTRY(wcid);
946
947 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
948 if (address)
949 memcpy(wcid_entry.mac, address, ETH_ALEN);
950
951 rt2800_register_multiwrite(rt2x00dev, offset,
952 &wcid_entry, sizeof(wcid_entry));
953}
954
955static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
956{
957 u32 offset;
958 offset = MAC_WCID_ATTR_ENTRY(wcid);
959 rt2800_register_write(rt2x00dev, offset, 0);
960}
961
962static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
963 int wcid, u32 bssidx)
964{
965 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
966 u32 reg;
967
968 /*
969 * The BSS Idx numbers is split in a main value of 3 bits,
970 * and a extended field for adding one additional bit to the value.
971 */
972 rt2800_register_read(rt2x00dev, offset, &reg);
973 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
974 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
975 (bssidx & 0x8) >> 3);
976 rt2800_register_write(rt2x00dev, offset, reg);
977}
978
979static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
980 struct rt2x00lib_crypto *crypto,
981 struct ieee80211_key_conf *key)
982{
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +0100983 struct mac_iveiv_entry iveiv_entry;
984 u32 offset;
985 u32 reg;
986
987 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
988
Ivo van Doorne4a0ab32010-06-14 22:14:19 +0200989 if (crypto->cmd == SET_KEY) {
990 rt2800_register_read(rt2x00dev, offset, &reg);
991 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
992 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
993 /*
994 * Both the cipher as the BSS Idx numbers are split in a main
995 * value of 3 bits, and a extended field for adding one additional
996 * bit to the value.
997 */
998 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
999 (crypto->cipher & 0x7));
1000 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1001 (crypto->cipher & 0x8) >> 3);
Ivo van Doorne4a0ab32010-06-14 22:14:19 +02001002 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1003 rt2800_register_write(rt2x00dev, offset, reg);
1004 } else {
Helmut Schaaa2b13282011-09-08 14:38:01 +02001005 /* Delete the cipher without touching the bssidx */
1006 rt2800_register_read(rt2x00dev, offset, &reg);
1007 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1008 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1009 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1010 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1011 rt2800_register_write(rt2x00dev, offset, reg);
Ivo van Doorne4a0ab32010-06-14 22:14:19 +02001012 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001013
1014 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1015
1016 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1017 if ((crypto->cipher == CIPHER_TKIP) ||
1018 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1019 (crypto->cipher == CIPHER_AES))
1020 iveiv_entry.iv[3] |= 0x20;
1021 iveiv_entry.iv[3] |= key->keyidx << 6;
1022 rt2800_register_multiwrite(rt2x00dev, offset,
1023 &iveiv_entry, sizeof(iveiv_entry));
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001024}
1025
1026int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1027 struct rt2x00lib_crypto *crypto,
1028 struct ieee80211_key_conf *key)
1029{
1030 struct hw_key_entry key_entry;
1031 struct rt2x00_field32 field;
1032 u32 offset;
1033 u32 reg;
1034
1035 if (crypto->cmd == SET_KEY) {
1036 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1037
1038 memcpy(key_entry.key, crypto->key,
1039 sizeof(key_entry.key));
1040 memcpy(key_entry.tx_mic, crypto->tx_mic,
1041 sizeof(key_entry.tx_mic));
1042 memcpy(key_entry.rx_mic, crypto->rx_mic,
1043 sizeof(key_entry.rx_mic));
1044
1045 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1046 rt2800_register_multiwrite(rt2x00dev, offset,
1047 &key_entry, sizeof(key_entry));
1048 }
1049
1050 /*
1051 * The cipher types are stored over multiple registers
1052 * starting with SHARED_KEY_MODE_BASE each word will have
1053 * 32 bits and contains the cipher types for 2 bssidx each.
1054 * Using the correct defines correctly will cause overhead,
1055 * so just calculate the correct offset.
1056 */
1057 field.bit_offset = 4 * (key->hw_key_idx % 8);
1058 field.bit_mask = 0x7 << field.bit_offset;
1059
1060 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1061
1062 rt2800_register_read(rt2x00dev, offset, &reg);
1063 rt2x00_set_field32(&reg, field,
1064 (crypto->cmd == SET_KEY) * crypto->cipher);
1065 rt2800_register_write(rt2x00dev, offset, reg);
1066
1067 /*
1068 * Update WCID information
1069 */
Helmut Schaaa2b13282011-09-08 14:38:01 +02001070 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1071 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1072 crypto->bssidx);
1073 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001074
1075 return 0;
1076}
1077EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1078
Helmut Schaaa2b13282011-09-08 14:38:01 +02001079static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
Helmut Schaa1ed38112011-03-03 19:44:33 +01001080{
Helmut Schaaa2b13282011-09-08 14:38:01 +02001081 struct mac_wcid_entry wcid_entry;
Helmut Schaa1ed38112011-03-03 19:44:33 +01001082 int idx;
Helmut Schaaa2b13282011-09-08 14:38:01 +02001083 u32 offset;
Helmut Schaa1ed38112011-03-03 19:44:33 +01001084
1085 /*
Helmut Schaaa2b13282011-09-08 14:38:01 +02001086 * Search for the first free WCID entry and return the corresponding
1087 * index.
Helmut Schaa1ed38112011-03-03 19:44:33 +01001088 *
1089 * Make sure the WCID starts _after_ the last possible shared key
1090 * entry (>32).
1091 *
1092 * Since parts of the pairwise key table might be shared with
1093 * the beacon frame buffers 6 & 7 we should only write into the
1094 * first 222 entries.
1095 */
1096 for (idx = 33; idx <= 222; idx++) {
Helmut Schaaa2b13282011-09-08 14:38:01 +02001097 offset = MAC_WCID_ENTRY(idx);
1098 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1099 sizeof(wcid_entry));
1100 if (is_broadcast_ether_addr(wcid_entry.mac))
Helmut Schaa1ed38112011-03-03 19:44:33 +01001101 return idx;
1102 }
Helmut Schaaa2b13282011-09-08 14:38:01 +02001103
1104 /*
1105 * Use -1 to indicate that we don't have any more space in the WCID
1106 * table.
1107 */
Helmut Schaa1ed38112011-03-03 19:44:33 +01001108 return -1;
1109}
1110
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001111int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1112 struct rt2x00lib_crypto *crypto,
1113 struct ieee80211_key_conf *key)
1114{
1115 struct hw_key_entry key_entry;
1116 u32 offset;
1117
1118 if (crypto->cmd == SET_KEY) {
Helmut Schaaa2b13282011-09-08 14:38:01 +02001119 /*
1120 * Allow key configuration only for STAs that are
1121 * known by the hw.
1122 */
1123 if (crypto->wcid < 0)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001124 return -ENOSPC;
Helmut Schaaa2b13282011-09-08 14:38:01 +02001125 key->hw_key_idx = crypto->wcid;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001126
1127 memcpy(key_entry.key, crypto->key,
1128 sizeof(key_entry.key));
1129 memcpy(key_entry.tx_mic, crypto->tx_mic,
1130 sizeof(key_entry.tx_mic));
1131 memcpy(key_entry.rx_mic, crypto->rx_mic,
1132 sizeof(key_entry.rx_mic));
1133
1134 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1135 rt2800_register_multiwrite(rt2x00dev, offset,
1136 &key_entry, sizeof(key_entry));
1137 }
1138
1139 /*
1140 * Update WCID information
1141 */
Helmut Schaaa2b13282011-09-08 14:38:01 +02001142 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001143
1144 return 0;
1145}
1146EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1147
Helmut Schaaa2b13282011-09-08 14:38:01 +02001148int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1149 struct ieee80211_sta *sta)
1150{
1151 int wcid;
1152 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1153
1154 /*
1155 * Find next free WCID.
1156 */
1157 wcid = rt2800_find_wcid(rt2x00dev);
1158
1159 /*
1160 * Store selected wcid even if it is invalid so that we can
1161 * later decide if the STA is uploaded into the hw.
1162 */
1163 sta_priv->wcid = wcid;
1164
1165 /*
1166 * No space left in the device, however, we can still communicate
1167 * with the STA -> No error.
1168 */
1169 if (wcid < 0)
1170 return 0;
1171
1172 /*
1173 * Clean up WCID attributes and write STA address to the device.
1174 */
1175 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1176 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1177 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1178 rt2x00lib_get_bssidx(rt2x00dev, vif));
1179 return 0;
1180}
1181EXPORT_SYMBOL_GPL(rt2800_sta_add);
1182
1183int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1184{
1185 /*
1186 * Remove WCID entry, no need to clean the attributes as they will
1187 * get renewed when the WCID is reused.
1188 */
1189 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1190
1191 return 0;
1192}
1193EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1194
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001195void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1196 const unsigned int filter_flags)
1197{
1198 u32 reg;
1199
1200 /*
1201 * Start configuration steps.
1202 * Note that the version error will always be dropped
1203 * and broadcast frames will always be accepted since
1204 * there is no filter for it at this time.
1205 */
1206 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1207 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1208 !(filter_flags & FIF_FCSFAIL));
1209 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1210 !(filter_flags & FIF_PLCPFAIL));
1211 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1212 !(filter_flags & FIF_PROMISC_IN_BSS));
1213 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1214 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1215 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1216 !(filter_flags & FIF_ALLMULTI));
1217 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1218 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1219 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1220 !(filter_flags & FIF_CONTROL));
1221 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1222 !(filter_flags & FIF_CONTROL));
1223 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1224 !(filter_flags & FIF_CONTROL));
1225 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1226 !(filter_flags & FIF_CONTROL));
1227 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1228 !(filter_flags & FIF_CONTROL));
1229 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1230 !(filter_flags & FIF_PSPOLL));
Helmut Schaa48839932011-11-24 09:13:26 +01001231 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1232 !(filter_flags & FIF_CONTROL));
1233 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1234 !(filter_flags & FIF_CONTROL));
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001235 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1236 !(filter_flags & FIF_CONTROL));
1237 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1238}
1239EXPORT_SYMBOL_GPL(rt2800_config_filter);
1240
1241void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1242 struct rt2x00intf_conf *conf, const unsigned int flags)
1243{
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001244 u32 reg;
Helmut Schaafa8b4b22010-11-04 20:42:36 +01001245 bool update_bssid = false;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001246
1247 if (flags & CONFIG_UPDATE_TYPE) {
1248 /*
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001249 * Enable synchronisation.
1250 */
1251 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001252 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001253 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
Helmut Schaa15a533c2011-04-18 15:28:04 +02001254
1255 if (conf->sync == TSF_SYNC_AP_NONE) {
1256 /*
1257 * Tune beacon queue transmit parameters for AP mode
1258 */
1259 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1260 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1261 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1262 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1263 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1264 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1265 } else {
1266 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1267 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1268 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1269 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1270 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1271 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1272 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001273 }
1274
1275 if (flags & CONFIG_UPDATE_MAC) {
Helmut Schaafa8b4b22010-11-04 20:42:36 +01001276 if (flags & CONFIG_UPDATE_TYPE &&
1277 conf->sync == TSF_SYNC_AP_NONE) {
1278 /*
1279 * The BSSID register has to be set to our own mac
1280 * address in AP mode.
1281 */
1282 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1283 update_bssid = true;
1284 }
1285
Ivo van Doornc600c822010-08-30 21:14:15 +02001286 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1287 reg = le32_to_cpu(conf->mac[1]);
1288 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1289 conf->mac[1] = cpu_to_le32(reg);
1290 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001291
1292 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1293 conf->mac, sizeof(conf->mac));
1294 }
1295
Helmut Schaafa8b4b22010-11-04 20:42:36 +01001296 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
Ivo van Doornc600c822010-08-30 21:14:15 +02001297 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1298 reg = le32_to_cpu(conf->bssid[1]);
1299 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1300 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1301 conf->bssid[1] = cpu_to_le32(reg);
1302 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001303
1304 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1305 conf->bssid, sizeof(conf->bssid));
1306 }
1307}
1308EXPORT_SYMBOL_GPL(rt2800_config_intf);
1309
Helmut Schaa87c19152010-10-02 11:28:34 +02001310static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1311 struct rt2x00lib_erp *erp)
1312{
1313 bool any_sta_nongf = !!(erp->ht_opmode &
1314 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1315 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1316 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1317 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1318 u32 reg;
1319
1320 /* default protection rate for HT20: OFDM 24M */
1321 mm20_rate = gf20_rate = 0x4004;
1322
1323 /* default protection rate for HT40: duplicate OFDM 24M */
1324 mm40_rate = gf40_rate = 0x4084;
1325
1326 switch (protection) {
1327 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1328 /*
1329 * All STAs in this BSS are HT20/40 but there might be
1330 * STAs not supporting greenfield mode.
1331 * => Disable protection for HT transmissions.
1332 */
1333 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1334
1335 break;
1336 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1337 /*
1338 * All STAs in this BSS are HT20 or HT20/40 but there
1339 * might be STAs not supporting greenfield mode.
1340 * => Protect all HT40 transmissions.
1341 */
1342 mm20_mode = gf20_mode = 0;
1343 mm40_mode = gf40_mode = 2;
1344
1345 break;
1346 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1347 /*
1348 * Nonmember protection:
1349 * According to 802.11n we _should_ protect all
1350 * HT transmissions (but we don't have to).
1351 *
1352 * But if cts_protection is enabled we _shall_ protect
1353 * all HT transmissions using a CCK rate.
1354 *
1355 * And if any station is non GF we _shall_ protect
1356 * GF transmissions.
1357 *
1358 * We decide to protect everything
1359 * -> fall through to mixed mode.
1360 */
1361 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1362 /*
1363 * Legacy STAs are present
1364 * => Protect all HT transmissions.
1365 */
1366 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1367
1368 /*
1369 * If erp protection is needed we have to protect HT
1370 * transmissions with CCK 11M long preamble.
1371 */
1372 if (erp->cts_protection) {
1373 /* don't duplicate RTS/CTS in CCK mode */
1374 mm20_rate = mm40_rate = 0x0003;
1375 gf20_rate = gf40_rate = 0x0003;
1376 }
1377 break;
Joe Perches6403eab2011-06-03 11:51:20 +00001378 }
Helmut Schaa87c19152010-10-02 11:28:34 +02001379
1380 /* check for STAs not supporting greenfield mode */
1381 if (any_sta_nongf)
1382 gf20_mode = gf40_mode = 2;
1383
1384 /* Update HT protection config */
1385 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1386 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1387 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1388 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1389
1390 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1391 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1392 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1393 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1394
1395 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1396 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1397 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1398 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1399
1400 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1401 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1402 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1403 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1404}
1405
Helmut Schaa02044642010-09-08 20:56:32 +02001406void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1407 u32 changed)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001408{
1409 u32 reg;
1410
Helmut Schaa02044642010-09-08 20:56:32 +02001411 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1412 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1413 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1414 !!erp->short_preamble);
1415 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1416 !!erp->short_preamble);
1417 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1418 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001419
Helmut Schaa02044642010-09-08 20:56:32 +02001420 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1421 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1422 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1423 erp->cts_protection ? 2 : 0);
1424 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1425 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001426
Helmut Schaa02044642010-09-08 20:56:32 +02001427 if (changed & BSS_CHANGED_BASIC_RATES) {
1428 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1429 erp->basic_rates);
1430 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1431 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001432
Helmut Schaa02044642010-09-08 20:56:32 +02001433 if (changed & BSS_CHANGED_ERP_SLOT) {
1434 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1435 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1436 erp->slot_time);
1437 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001438
Helmut Schaa02044642010-09-08 20:56:32 +02001439 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1440 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1441 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1442 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001443
Helmut Schaa02044642010-09-08 20:56:32 +02001444 if (changed & BSS_CHANGED_BEACON_INT) {
1445 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1446 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1447 erp->beacon_int * 16);
1448 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1449 }
Helmut Schaa87c19152010-10-02 11:28:34 +02001450
1451 if (changed & BSS_CHANGED_HT)
1452 rt2800_config_ht_opmode(rt2x00dev, erp);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001453}
1454EXPORT_SYMBOL_GPL(rt2800_config_erp);
1455
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001456static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1457{
1458 u32 reg;
1459 u16 eeprom;
1460 u8 led_ctrl, led_g_mode, led_r_mode;
1461
1462 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1463 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1464 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1465 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1466 } else {
1467 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1468 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1469 }
1470 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1471
1472 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1473 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1474 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1475 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1476 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1478 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1479 if (led_ctrl == 0 || led_ctrl > 0x40) {
1480 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1481 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1482 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1483 } else {
1484 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1485 (led_g_mode << 2) | led_r_mode, 1);
1486 }
1487 }
1488}
1489
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001490static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1491 enum antenna ant)
1492{
1493 u32 reg;
1494 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1495 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1496
1497 if (rt2x00_is_pci(rt2x00dev)) {
1498 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1499 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1500 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1501 } else if (rt2x00_is_usb(rt2x00dev))
1502 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1503 eesk_pin, 0);
1504
1505 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
Shiang Tufe591472011-02-20 13:57:22 +01001506 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001507 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1508 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1509}
1510
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001511void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1512{
1513 u8 r1;
1514 u8 r3;
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001515 u16 eeprom;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001516
1517 rt2800_bbp_read(rt2x00dev, 1, &r1);
1518 rt2800_bbp_read(rt2x00dev, 3, &r3);
1519
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001520 if (rt2x00_rt(rt2x00dev, RT3572) &&
1521 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1522 rt2800_config_3572bt_ant(rt2x00dev);
1523
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001524 /*
1525 * Configure the TX antenna.
1526 */
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001527 switch (ant->tx_chain_num) {
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001528 case 1:
1529 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001530 break;
1531 case 2:
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001532 if (rt2x00_rt(rt2x00dev, RT3572) &&
1533 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1534 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1535 else
1536 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001537 break;
1538 case 3:
Ivo van Doorne22557f2010-06-29 21:49:05 +02001539 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001540 break;
1541 }
1542
1543 /*
1544 * Configure the RX antenna.
1545 */
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001546 switch (ant->rx_chain_num) {
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001547 case 1:
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001548 if (rt2x00_rt(rt2x00dev, RT3070) ||
1549 rt2x00_rt(rt2x00dev, RT3090) ||
1550 rt2x00_rt(rt2x00dev, RT3390)) {
1551 rt2x00_eeprom_read(rt2x00dev,
1552 EEPROM_NIC_CONF1, &eeprom);
1553 if (rt2x00_get_field16(eeprom,
1554 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1555 rt2800_set_ant_diversity(rt2x00dev,
1556 rt2x00dev->default_ant.rx);
1557 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001558 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1559 break;
1560 case 2:
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001561 if (rt2x00_rt(rt2x00dev, RT3572) &&
1562 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1563 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1564 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1565 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1566 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1567 } else {
1568 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1569 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001570 break;
1571 case 3:
1572 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1573 break;
1574 }
1575
1576 rt2800_bbp_write(rt2x00dev, 3, r3);
1577 rt2800_bbp_write(rt2x00dev, 1, r1);
1578}
1579EXPORT_SYMBOL_GPL(rt2800_config_ant);
1580
1581static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1582 struct rt2x00lib_conf *libconf)
1583{
1584 u16 eeprom;
1585 short lna_gain;
1586
1587 if (libconf->rf.channel <= 14) {
1588 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1589 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1590 } else if (libconf->rf.channel <= 64) {
1591 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1592 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1593 } else if (libconf->rf.channel <= 128) {
1594 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1595 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1596 } else {
1597 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1598 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1599 }
1600
1601 rt2x00dev->lna_gain = lna_gain;
1602}
1603
Gertjan van Wingerde06855ef2010-04-11 14:31:07 +02001604static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1605 struct ieee80211_conf *conf,
1606 struct rf_channel *rf,
1607 struct channel_info *info)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001608{
1609 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1610
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001611 if (rt2x00dev->default_ant.tx_chain_num == 1)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001612 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1613
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001614 if (rt2x00dev->default_ant.rx_chain_num == 1) {
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001615 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1616 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
RA-Jay Hungd96aa642011-02-20 13:54:52 +01001617 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001618 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1619
1620 if (rf->channel > 14) {
1621 /*
1622 * When TX power is below 0, we should increase it by 7 to
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001623 * make it a positive value (Minimum value is -7).
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001624 * However this means that values between 0 and 7 have
1625 * double meaning, and we should set a 7DBm boost flag.
1626 */
1627 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001628 (info->default_power1 >= 0));
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001629
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001630 if (info->default_power1 < 0)
1631 info->default_power1 += 7;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001632
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001633 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001634
1635 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001636 (info->default_power2 >= 0));
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001637
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001638 if (info->default_power2 < 0)
1639 info->default_power2 += 7;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001640
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001641 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001642 } else {
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001643 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1644 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001645 }
1646
1647 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1648
1649 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1650 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1651 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1652 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1653
1654 udelay(200);
1655
1656 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1657 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1658 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1659 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1660
1661 udelay(200);
1662
1663 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1664 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1665 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1666 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1667}
1668
Gertjan van Wingerde06855ef2010-04-11 14:31:07 +02001669static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1670 struct ieee80211_conf *conf,
1671 struct rf_channel *rf,
1672 struct channel_info *info)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001673{
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01001674 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
Stanislaw Gruszkaf1f12f92012-01-30 16:17:59 +01001675 u8 rfcsr, calib_tx, calib_rx;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001676
1677 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
Stanislaw Gruszka7f4666a2012-01-30 16:17:56 +01001678
1679 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1680 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1681 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001682
1683 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
Gertjan van Wingerdefab799c2010-04-11 14:31:08 +02001684 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001685 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1686
1687 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001688 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001689 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1690
Helmut Schaa5a673962010-04-23 15:54:43 +02001691 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02001692 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
Helmut Schaa5a673962010-04-23 15:54:43 +02001693 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1694
Stanislaw Gruszkae3bab192012-01-30 16:17:57 +01001695 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1696 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1697 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1698 if (rt2x00_rt(rt2x00dev, RT3390)) {
1699 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1700 rt2x00dev->default_ant.rx_chain_num == 1);
1701 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1702 rt2x00dev->default_ant.tx_chain_num == 1);
1703 } else {
1704 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1705 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1706 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1707 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1708
1709 switch (rt2x00dev->default_ant.tx_chain_num) {
1710 case 1:
1711 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1712 /* fall through */
1713 case 2:
1714 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1715 break;
1716 }
1717
1718 switch (rt2x00dev->default_ant.rx_chain_num) {
1719 case 1:
1720 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1721 /* fall through */
1722 case 2:
1723 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1724 break;
1725 }
1726 }
1727 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1728
Stanislaw Gruszka3e0c7642012-01-30 16:17:58 +01001729 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1730 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1731 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1732 msleep(1);
1733 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1734 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1735
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001736 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1737 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1738 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1739
Stanislaw Gruszkaf1f12f92012-01-30 16:17:59 +01001740 if (rt2x00_rt(rt2x00dev, RT3390)) {
1741 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1742 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1743 } else {
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01001744 if (conf_is_ht40(conf)) {
1745 calib_tx = drv_data->calibration_bw40;
1746 calib_rx = drv_data->calibration_bw40;
1747 } else {
1748 calib_tx = drv_data->calibration_bw20;
1749 calib_rx = drv_data->calibration_bw20;
1750 }
Stanislaw Gruszkaf1f12f92012-01-30 16:17:59 +01001751 }
1752
1753 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1754 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1755 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1756
1757 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1758 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1759 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001760
Gertjan van Wingerde71976902010-03-24 21:42:36 +01001761 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001762 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
Gertjan van Wingerde71976902010-03-24 21:42:36 +01001763 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
Stanislaw Gruszka3e0c7642012-01-30 16:17:58 +01001764
1765 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1766 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1767 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1768 msleep(1);
1769 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1770 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01001771}
1772
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001773static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1774 struct ieee80211_conf *conf,
1775 struct rf_channel *rf,
1776 struct channel_info *info)
1777{
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01001778 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001779 u8 rfcsr;
1780 u32 reg;
1781
1782 if (rf->channel <= 14) {
Gertjan van Wingerde5d137df2012-02-06 23:45:09 +01001783 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1784 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001785 } else {
1786 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1787 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1788 }
1789
1790 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1791 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1792
1793 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1794 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1795 if (rf->channel <= 14)
1796 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1797 else
1798 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1799 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1800
1801 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1802 if (rf->channel <= 14)
1803 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1804 else
1805 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1806 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1807
1808 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1809 if (rf->channel <= 14) {
1810 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1811 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
Gertjan van Wingerde569ffa52012-02-06 23:45:10 +01001812 info->default_power1);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001813 } else {
1814 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1815 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1816 (info->default_power1 & 0x3) |
1817 ((info->default_power1 & 0xC) << 1));
1818 }
1819 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1820
1821 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1822 if (rf->channel <= 14) {
1823 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1824 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
Gertjan van Wingerde569ffa52012-02-06 23:45:10 +01001825 info->default_power2);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001826 } else {
1827 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1828 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1829 (info->default_power2 & 0x3) |
1830 ((info->default_power2 & 0xC) << 1));
1831 }
1832 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1833
1834 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001835 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1836 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1837 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1838 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
Gertjan van Wingerde0cd461e2012-02-06 23:45:11 +01001839 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1840 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001841 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1842 if (rf->channel <= 14) {
1843 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1844 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1845 }
1846 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1847 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1848 } else {
1849 switch (rt2x00dev->default_ant.tx_chain_num) {
1850 case 1:
1851 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1852 case 2:
1853 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1854 break;
1855 }
1856
1857 switch (rt2x00dev->default_ant.rx_chain_num) {
1858 case 1:
1859 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1860 case 2:
1861 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1862 break;
1863 }
1864 }
1865 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1866
1867 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1868 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1869 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1870
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01001871 if (conf_is_ht40(conf)) {
1872 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1873 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1874 } else {
1875 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1876 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1877 }
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001878
1879 if (rf->channel <= 14) {
1880 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1881 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1882 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1883 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1884 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
Gertjan van Wingerde77c06c22012-02-06 23:45:13 +01001885 rfcsr = 0x4c;
1886 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1887 drv_data->txmixer_gain_24g);
1888 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001889 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1890 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1891 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1892 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1893 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1894 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1895 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1896 } else {
Gertjan van Wingerde58b8ae12012-02-06 23:45:12 +01001897 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1898 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1899 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1900 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1901 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1902 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001903 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1904 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1905 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1906 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
Gertjan van Wingerde77c06c22012-02-06 23:45:13 +01001907 rfcsr = 0x7a;
1908 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1909 drv_data->txmixer_gain_5g);
1910 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02001911 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1912 if (rf->channel <= 64) {
1913 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1914 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1915 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1916 } else if (rf->channel <= 128) {
1917 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1918 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1919 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1920 } else {
1921 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1922 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1923 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1924 }
1925 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1926 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1927 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1928 }
1929
1930 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1931 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1932 if (rf->channel <= 14)
1933 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1934 else
1935 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1936 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1937
1938 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1939 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1940 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1941}
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01001942
Woody Hunga89534e2012-06-13 15:01:16 +08001943#define RT3290_POWER_BOUND 0x27
1944#define RT3290_FREQ_OFFSET_BOUND 0x5f
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01001945#define RT5390_POWER_BOUND 0x27
1946#define RT5390_FREQ_OFFSET_BOUND 0x5f
1947
Woody Hunga89534e2012-06-13 15:01:16 +08001948static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1949 struct ieee80211_conf *conf,
1950 struct rf_channel *rf,
1951 struct channel_info *info)
1952{
1953 u8 rfcsr;
1954
1955 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1956 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1957 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1958 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1959 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1960
1961 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1962 if (info->default_power1 > RT3290_POWER_BOUND)
1963 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT3290_POWER_BOUND);
1964 else
1965 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1966 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1967
1968 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1969 if (rt2x00dev->freq_offset > RT3290_FREQ_OFFSET_BOUND)
1970 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1971 RT3290_FREQ_OFFSET_BOUND);
1972 else
1973 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1974 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1975
1976 if (rf->channel <= 14) {
1977 if (rf->channel == 6)
1978 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
1979 else
1980 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
1981
1982 if (rf->channel >= 1 && rf->channel <= 6)
1983 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
1984 else if (rf->channel >= 7 && rf->channel <= 11)
1985 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
1986 else if (rf->channel >= 12 && rf->channel <= 14)
1987 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
1988 }
1989}
1990
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01001991static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
Gabor Juhosadde5882011-03-03 11:46:45 +01001992 struct ieee80211_conf *conf,
1993 struct rf_channel *rf,
1994 struct channel_info *info)
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01001995{
Gabor Juhosadde5882011-03-03 11:46:45 +01001996 u8 rfcsr;
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01001997
Gabor Juhosadde5882011-03-03 11:46:45 +01001998 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1999 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2000 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2001 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2002 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002003
Gabor Juhosadde5882011-03-03 11:46:45 +01002004 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2005 if (info->default_power1 > RT5390_POWER_BOUND)
2006 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
2007 else
2008 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2009 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002010
Zero.Lincff3d1f2012-05-29 16:11:09 +08002011 if (rt2x00_rt(rt2x00dev, RT5392)) {
2012 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2013 if (info->default_power1 > RT5390_POWER_BOUND)
2014 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2015 RT5390_POWER_BOUND);
2016 else
2017 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2018 info->default_power2);
2019 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2020 }
2021
Gabor Juhosadde5882011-03-03 11:46:45 +01002022 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
Zero.Lincff3d1f2012-05-29 16:11:09 +08002023 if (rt2x00_rt(rt2x00dev, RT5392)) {
2024 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2025 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2026 }
Gabor Juhosadde5882011-03-03 11:46:45 +01002027 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2028 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2029 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2030 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2031 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002032
Gabor Juhosadde5882011-03-03 11:46:45 +01002033 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2034 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
2035 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
2036 RT5390_FREQ_OFFSET_BOUND);
2037 else
2038 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2039 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002040
Gabor Juhosadde5882011-03-03 11:46:45 +01002041 if (rf->channel <= 14) {
2042 int idx = rf->channel-1;
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002043
Gertjan van Wingerdefdbc7b02011-04-30 17:15:37 +02002044 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01002045 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2046 /* r55/r59 value array of channel 1~14 */
2047 static const char r55_bt_rev[] = {0x83, 0x83,
2048 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2049 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2050 static const char r59_bt_rev[] = {0x0e, 0x0e,
2051 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2052 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002053
Gabor Juhosadde5882011-03-03 11:46:45 +01002054 rt2800_rfcsr_write(rt2x00dev, 55,
2055 r55_bt_rev[idx]);
2056 rt2800_rfcsr_write(rt2x00dev, 59,
2057 r59_bt_rev[idx]);
2058 } else {
2059 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2060 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2061 0x88, 0x88, 0x86, 0x85, 0x84};
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002062
Gabor Juhosadde5882011-03-03 11:46:45 +01002063 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2064 }
2065 } else {
2066 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2067 static const char r55_nonbt_rev[] = {0x23, 0x23,
2068 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2069 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2070 static const char r59_nonbt_rev[] = {0x07, 0x07,
2071 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2072 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002073
Gabor Juhosadde5882011-03-03 11:46:45 +01002074 rt2800_rfcsr_write(rt2x00dev, 55,
2075 r55_nonbt_rev[idx]);
2076 rt2800_rfcsr_write(rt2x00dev, 59,
2077 r59_nonbt_rev[idx]);
John Li2ed71882012-02-17 17:33:06 +08002078 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2079 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01002080 static const char r59_non_bt[] = {0x8f, 0x8f,
2081 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2082 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002083
Gabor Juhosadde5882011-03-03 11:46:45 +01002084 rt2800_rfcsr_write(rt2x00dev, 59,
2085 r59_non_bt[idx]);
2086 }
2087 }
2088 }
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01002089}
2090
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002091static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2092 struct ieee80211_conf *conf,
2093 struct rf_channel *rf,
2094 struct channel_info *info)
2095{
2096 u32 reg;
2097 unsigned int tx_pin;
Woody Hunga89534e2012-06-13 15:01:16 +08002098 u8 bbp, rfcsr;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002099
Ivo van Doorn46323e12010-08-23 19:55:43 +02002100 if (rf->channel <= 14) {
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02002101 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2102 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
Ivo van Doorn46323e12010-08-23 19:55:43 +02002103 } else {
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02002104 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2105 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
Ivo van Doorn46323e12010-08-23 19:55:43 +02002106 }
2107
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01002108 switch (rt2x00dev->chip.rf) {
2109 case RF2020:
2110 case RF3020:
2111 case RF3021:
2112 case RF3022:
2113 case RF3320:
Gertjan van Wingerde06855ef2010-04-11 14:31:07 +02002114 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01002115 break;
2116 case RF3052:
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02002117 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01002118 break;
Woody Hunga89534e2012-06-13 15:01:16 +08002119 case RF3290:
2120 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2121 break;
villacis@palosanto.comccf91bd2012-05-16 21:07:12 +02002122 case RF5360:
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01002123 case RF5370:
John Li2ed71882012-02-17 17:33:06 +08002124 case RF5372:
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01002125 case RF5390:
Zero.Lincff3d1f2012-05-29 16:11:09 +08002126 case RF5392:
Gabor Juhosadde5882011-03-03 11:46:45 +01002127 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01002128 break;
2129 default:
Gertjan van Wingerde06855ef2010-04-11 14:31:07 +02002130 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01002131 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002132
Woody Hunga89534e2012-06-13 15:01:16 +08002133 if (rt2x00_rf(rt2x00dev, RF3290) ||
2134 rt2x00_rf(rt2x00dev, RF5360) ||
2135 rt2x00_rf(rt2x00dev, RF5370) ||
2136 rt2x00_rf(rt2x00dev, RF5372) ||
2137 rt2x00_rf(rt2x00dev, RF5390) ||
2138 rt2x00_rf(rt2x00dev, RF5392)) {
2139 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2140 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2141 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2142 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2143
2144 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2145 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2146 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2147 }
2148
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002149 /*
2150 * Change BBP settings
2151 */
2152 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2153 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2154 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2155 rt2800_bbp_write(rt2x00dev, 86, 0);
2156
2157 if (rf->channel <= 14) {
John Li2ed71882012-02-17 17:33:06 +08002158 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2159 !rt2x00_rt(rt2x00dev, RT5392)) {
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02002160 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2161 &rt2x00dev->cap_flags)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01002162 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2163 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2164 } else {
2165 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2166 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2167 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002168 }
2169 } else {
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02002170 if (rt2x00_rt(rt2x00dev, RT3572))
2171 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2172 else
2173 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002174
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02002175 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002176 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2177 else
2178 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2179 }
2180
2181 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
Gertjan van Wingerdea21ee722010-05-03 22:43:04 +02002182 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002183 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2184 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2185 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2186
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02002187 if (rt2x00_rt(rt2x00dev, RT3572))
2188 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2189
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002190 tx_pin = 0;
2191
2192 /* Turn on unused PA or LNA when not using 1T or 1R */
RA-Jay Hungd96aa642011-02-20 13:54:52 +01002193 if (rt2x00dev->default_ant.tx_chain_num == 2) {
Gertjan van Wingerde65f31b52011-05-18 20:25:05 +02002194 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2195 rf->channel > 14);
2196 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2197 rf->channel <= 14);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002198 }
2199
2200 /* Turn on unused PA or LNA when not using 1T or 1R */
RA-Jay Hungd96aa642011-02-20 13:54:52 +01002201 if (rt2x00dev->default_ant.rx_chain_num == 2) {
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002202 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2203 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2204 }
2205
2206 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2207 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2208 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2209 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
Gertjan van Wingerde8f96e912011-05-18 20:25:18 +02002210 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2211 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2212 else
2213 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2214 rf->channel <= 14);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002215 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2216
2217 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2218
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02002219 if (rt2x00_rt(rt2x00dev, RT3572))
2220 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2221
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002222 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2223 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2224 rt2800_bbp_write(rt2x00dev, 4, bbp);
2225
2226 rt2800_bbp_read(rt2x00dev, 3, &bbp);
Gertjan van Wingerdea21ee722010-05-03 22:43:04 +02002227 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002228 rt2800_bbp_write(rt2x00dev, 3, bbp);
2229
Gertjan van Wingerde8d0c9b62010-04-11 14:31:10 +02002230 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002231 if (conf_is_ht40(conf)) {
2232 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2233 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2234 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2235 } else {
2236 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2237 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2238 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2239 }
2240 }
2241
2242 msleep(1);
Helmut Schaa977206d2010-12-13 12:31:58 +01002243
2244 /*
2245 * Clear channel statistic counters
2246 */
2247 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2248 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2249 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002250}
2251
Helmut Schaa9e33a352011-03-28 13:33:40 +02002252static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2253{
2254 u8 tssi_bounds[9];
2255 u8 current_tssi;
2256 u16 eeprom;
2257 u8 step;
2258 int i;
2259
2260 /*
2261 * Read TSSI boundaries for temperature compensation from
2262 * the EEPROM.
2263 *
2264 * Array idx 0 1 2 3 4 5 6 7 8
2265 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2266 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2267 */
2268 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2269 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2270 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2271 EEPROM_TSSI_BOUND_BG1_MINUS4);
2272 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2273 EEPROM_TSSI_BOUND_BG1_MINUS3);
2274
2275 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2276 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2277 EEPROM_TSSI_BOUND_BG2_MINUS2);
2278 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2279 EEPROM_TSSI_BOUND_BG2_MINUS1);
2280
2281 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2282 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2283 EEPROM_TSSI_BOUND_BG3_REF);
2284 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2285 EEPROM_TSSI_BOUND_BG3_PLUS1);
2286
2287 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2288 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2289 EEPROM_TSSI_BOUND_BG4_PLUS2);
2290 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2291 EEPROM_TSSI_BOUND_BG4_PLUS3);
2292
2293 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2294 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2295 EEPROM_TSSI_BOUND_BG5_PLUS4);
2296
2297 step = rt2x00_get_field16(eeprom,
2298 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2299 } else {
2300 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2301 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2302 EEPROM_TSSI_BOUND_A1_MINUS4);
2303 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2304 EEPROM_TSSI_BOUND_A1_MINUS3);
2305
2306 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2307 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2308 EEPROM_TSSI_BOUND_A2_MINUS2);
2309 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2310 EEPROM_TSSI_BOUND_A2_MINUS1);
2311
2312 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2313 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2314 EEPROM_TSSI_BOUND_A3_REF);
2315 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2316 EEPROM_TSSI_BOUND_A3_PLUS1);
2317
2318 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2319 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2320 EEPROM_TSSI_BOUND_A4_PLUS2);
2321 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2322 EEPROM_TSSI_BOUND_A4_PLUS3);
2323
2324 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2325 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2326 EEPROM_TSSI_BOUND_A5_PLUS4);
2327
2328 step = rt2x00_get_field16(eeprom,
2329 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2330 }
2331
2332 /*
2333 * Check if temperature compensation is supported.
2334 */
2335 if (tssi_bounds[4] == 0xff)
2336 return 0;
2337
2338 /*
2339 * Read current TSSI (BBP 49).
2340 */
2341 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2342
2343 /*
2344 * Compare TSSI value (BBP49) with the compensation boundaries
2345 * from the EEPROM and increase or decrease tx power.
2346 */
2347 for (i = 0; i <= 3; i++) {
2348 if (current_tssi > tssi_bounds[i])
2349 break;
2350 }
2351
2352 if (i == 4) {
2353 for (i = 8; i >= 5; i--) {
2354 if (current_tssi < tssi_bounds[i])
2355 break;
2356 }
2357 }
2358
2359 return (i - 4) * step;
2360}
2361
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002362static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2363 enum ieee80211_band band)
2364{
2365 u16 eeprom;
2366 u8 comp_en;
2367 u8 comp_type;
Helmut Schaa75faae82011-03-28 13:31:30 +02002368 int comp_value = 0;
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002369
2370 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2371
Helmut Schaa75faae82011-03-28 13:31:30 +02002372 /*
2373 * HT40 compensation not required.
2374 */
2375 if (eeprom == 0xffff ||
2376 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002377 return 0;
2378
2379 if (band == IEEE80211_BAND_2GHZ) {
2380 comp_en = rt2x00_get_field16(eeprom,
2381 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2382 if (comp_en) {
2383 comp_type = rt2x00_get_field16(eeprom,
2384 EEPROM_TXPOWER_DELTA_TYPE_2G);
2385 comp_value = rt2x00_get_field16(eeprom,
2386 EEPROM_TXPOWER_DELTA_VALUE_2G);
2387 if (!comp_type)
2388 comp_value = -comp_value;
2389 }
2390 } else {
2391 comp_en = rt2x00_get_field16(eeprom,
2392 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2393 if (comp_en) {
2394 comp_type = rt2x00_get_field16(eeprom,
2395 EEPROM_TXPOWER_DELTA_TYPE_5G);
2396 comp_value = rt2x00_get_field16(eeprom,
2397 EEPROM_TXPOWER_DELTA_VALUE_5G);
2398 if (!comp_type)
2399 comp_value = -comp_value;
2400 }
2401 }
2402
2403 return comp_value;
2404}
2405
Helmut Schaafa71a162011-03-28 13:32:32 +02002406static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2407 enum ieee80211_band band, int power_level,
2408 u8 txpower, int delta)
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002409{
2410 u32 reg;
2411 u16 eeprom;
2412 u8 criterion;
2413 u8 eirp_txpower;
2414 u8 eirp_txpower_criterion;
2415 u8 reg_limit;
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002416
2417 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2418 return txpower;
2419
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02002420 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002421 /*
2422 * Check if eirp txpower exceed txpower_limit.
2423 * We use OFDM 6M as criterion and its eirp txpower
2424 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2425 * .11b data rate need add additional 4dbm
2426 * when calculating eirp txpower.
2427 */
2428 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2429 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2430
2431 rt2x00_eeprom_read(rt2x00dev,
2432 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2433
2434 if (band == IEEE80211_BAND_2GHZ)
2435 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2436 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2437 else
2438 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2439 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2440
2441 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
Helmut Schaa2af242e2011-03-28 13:32:01 +02002442 (is_rate_b ? 4 : 0) + delta;
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002443
2444 reg_limit = (eirp_txpower > power_level) ?
2445 (eirp_txpower - power_level) : 0;
2446 } else
2447 reg_limit = 0;
2448
Helmut Schaa2af242e2011-03-28 13:32:01 +02002449 return txpower + delta - reg_limit;
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002450}
2451
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002452static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
Helmut Schaa9e33a352011-03-28 13:33:40 +02002453 enum ieee80211_band band,
2454 int power_level)
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002455{
Helmut Schaa5e846002010-07-11 12:23:09 +02002456 u8 txpower;
Helmut Schaa5e846002010-07-11 12:23:09 +02002457 u16 eeprom;
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002458 int i, is_rate_b;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002459 u32 reg;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002460 u8 r1;
Helmut Schaa5e846002010-07-11 12:23:09 +02002461 u32 offset;
Helmut Schaa2af242e2011-03-28 13:32:01 +02002462 int delta;
2463
2464 /*
2465 * Calculate HT40 compensation delta
2466 */
2467 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002468
Helmut Schaa5e846002010-07-11 12:23:09 +02002469 /*
Helmut Schaa9e33a352011-03-28 13:33:40 +02002470 * calculate temperature compensation delta
2471 */
2472 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002473
Helmut Schaa5e846002010-07-11 12:23:09 +02002474 /*
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002475 * set to normal bbp tx power control mode: +/- 0dBm
Helmut Schaa5e846002010-07-11 12:23:09 +02002476 */
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002477 rt2800_bbp_read(rt2x00dev, 1, &r1);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002478 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002479 rt2800_bbp_write(rt2x00dev, 1, r1);
Helmut Schaa5e846002010-07-11 12:23:09 +02002480 offset = TX_PWR_CFG_0;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002481
Helmut Schaa5e846002010-07-11 12:23:09 +02002482 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2483 /* just to be safe */
2484 if (offset > TX_PWR_CFG_4)
2485 break;
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002486
Helmut Schaa5e846002010-07-11 12:23:09 +02002487 rt2800_register_read(rt2x00dev, offset, &reg);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002488
Helmut Schaa5e846002010-07-11 12:23:09 +02002489 /* read the next four txpower values */
2490 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2491 &eeprom);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002492
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002493 is_rate_b = i ? 0 : 1;
2494 /*
2495 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
Helmut Schaa5e846002010-07-11 12:23:09 +02002496 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002497 * TX_PWR_CFG_4: unknown
2498 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002499 txpower = rt2x00_get_field16(eeprom,
2500 EEPROM_TXPOWER_BYRATE_RATE0);
Helmut Schaafa71a162011-03-28 13:32:32 +02002501 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002502 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002503 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002504
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002505 /*
2506 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
Helmut Schaa5e846002010-07-11 12:23:09 +02002507 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002508 * TX_PWR_CFG_4: unknown
2509 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002510 txpower = rt2x00_get_field16(eeprom,
2511 EEPROM_TXPOWER_BYRATE_RATE1);
Helmut Schaafa71a162011-03-28 13:32:32 +02002512 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002513 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002514 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002515
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002516 /*
2517 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
Helmut Schaa5e846002010-07-11 12:23:09 +02002518 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002519 * TX_PWR_CFG_4: unknown
2520 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002521 txpower = rt2x00_get_field16(eeprom,
2522 EEPROM_TXPOWER_BYRATE_RATE2);
Helmut Schaafa71a162011-03-28 13:32:32 +02002523 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002524 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002525 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002526
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002527 /*
2528 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
Helmut Schaa5e846002010-07-11 12:23:09 +02002529 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002530 * TX_PWR_CFG_4: unknown
2531 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002532 txpower = rt2x00_get_field16(eeprom,
2533 EEPROM_TXPOWER_BYRATE_RATE3);
Helmut Schaafa71a162011-03-28 13:32:32 +02002534 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002535 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002536 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002537
2538 /* read the next four txpower values */
2539 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2540 &eeprom);
2541
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002542 is_rate_b = 0;
2543 /*
2544 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
Helmut Schaa5e846002010-07-11 12:23:09 +02002545 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002546 * TX_PWR_CFG_4: unknown
2547 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002548 txpower = rt2x00_get_field16(eeprom,
2549 EEPROM_TXPOWER_BYRATE_RATE0);
Helmut Schaafa71a162011-03-28 13:32:32 +02002550 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002551 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002552 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002553
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002554 /*
2555 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
Helmut Schaa5e846002010-07-11 12:23:09 +02002556 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002557 * TX_PWR_CFG_4: unknown
2558 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002559 txpower = rt2x00_get_field16(eeprom,
2560 EEPROM_TXPOWER_BYRATE_RATE1);
Helmut Schaafa71a162011-03-28 13:32:32 +02002561 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002562 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002563 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002564
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002565 /*
2566 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
Helmut Schaa5e846002010-07-11 12:23:09 +02002567 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002568 * TX_PWR_CFG_4: unknown
2569 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002570 txpower = rt2x00_get_field16(eeprom,
2571 EEPROM_TXPOWER_BYRATE_RATE2);
Helmut Schaafa71a162011-03-28 13:32:32 +02002572 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002573 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002574 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002575
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002576 /*
2577 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
Helmut Schaa5e846002010-07-11 12:23:09 +02002578 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002579 * TX_PWR_CFG_4: unknown
2580 */
Helmut Schaa5e846002010-07-11 12:23:09 +02002581 txpower = rt2x00_get_field16(eeprom,
2582 EEPROM_TXPOWER_BYRATE_RATE3);
Helmut Schaafa71a162011-03-28 13:32:32 +02002583 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
Helmut Schaa2af242e2011-03-28 13:32:01 +02002584 power_level, txpower, delta);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002585 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
Helmut Schaa5e846002010-07-11 12:23:09 +02002586
2587 rt2800_register_write(rt2x00dev, offset, reg);
2588
2589 /* next TX_PWR_CFG register */
2590 offset += 4;
2591 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002592}
2593
Helmut Schaa9e33a352011-03-28 13:33:40 +02002594void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2595{
2596 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2597 rt2x00dev->tx_power);
2598}
2599EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2600
John Li2e9c43d2012-02-16 21:40:57 +08002601void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2602{
2603 u32 tx_pin;
2604 u8 rfcsr;
2605
2606 /*
2607 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2608 * designed to be controlled in oscillation frequency by a voltage
2609 * input. Maybe the temperature will affect the frequency of
2610 * oscillation to be shifted. The VCO calibration will be called
2611 * periodically to adjust the frequency to be precision.
2612 */
2613
2614 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2615 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2616 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2617
2618 switch (rt2x00dev->chip.rf) {
2619 case RF2020:
2620 case RF3020:
2621 case RF3021:
2622 case RF3022:
2623 case RF3320:
2624 case RF3052:
2625 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2626 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2627 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2628 break;
Woody Hunga89534e2012-06-13 15:01:16 +08002629 case RF3290:
villacis@palosanto.comccf91bd2012-05-16 21:07:12 +02002630 case RF5360:
John Li2e9c43d2012-02-16 21:40:57 +08002631 case RF5370:
2632 case RF5372:
2633 case RF5390:
Zero.Lincff3d1f2012-05-29 16:11:09 +08002634 case RF5392:
John Li2e9c43d2012-02-16 21:40:57 +08002635 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2636 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2637 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2638 break;
2639 default:
2640 return;
2641 }
2642
2643 mdelay(1);
2644
2645 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2646 if (rt2x00dev->rf_channel <= 14) {
2647 switch (rt2x00dev->default_ant.tx_chain_num) {
2648 case 3:
2649 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2650 /* fall through */
2651 case 2:
2652 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2653 /* fall through */
2654 case 1:
2655 default:
2656 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2657 break;
2658 }
2659 } else {
2660 switch (rt2x00dev->default_ant.tx_chain_num) {
2661 case 3:
2662 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2663 /* fall through */
2664 case 2:
2665 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2666 /* fall through */
2667 case 1:
2668 default:
2669 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2670 break;
2671 }
2672 }
2673 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2674
2675}
2676EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2677
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002678static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2679 struct rt2x00lib_conf *libconf)
2680{
2681 u32 reg;
2682
2683 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2684 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2685 libconf->conf->short_frame_max_tx_count);
2686 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2687 libconf->conf->long_frame_max_tx_count);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002688 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2689}
2690
2691static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2692 struct rt2x00lib_conf *libconf)
2693{
2694 enum dev_state state =
2695 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2696 STATE_SLEEP : STATE_AWAKE;
2697 u32 reg;
2698
2699 if (state == STATE_SLEEP) {
2700 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2701
2702 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2703 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2704 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2705 libconf->conf->listen_interval - 1);
2706 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2707 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2708
2709 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2710 } else {
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002711 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2712 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2713 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2714 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2715 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
Gertjan van Wingerde57318582010-03-30 23:50:23 +02002716
2717 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002718 }
2719}
2720
2721void rt2800_config(struct rt2x00_dev *rt2x00dev,
2722 struct rt2x00lib_conf *libconf,
2723 const unsigned int flags)
2724{
2725 /* Always recalculate LNA gain before changing configuration */
2726 rt2800_config_lna_gain(rt2x00dev, libconf);
2727
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002728 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002729 rt2800_config_channel(rt2x00dev, libconf->conf,
2730 &libconf->rf, &libconf->channel);
Helmut Schaa9e33a352011-03-28 13:33:40 +02002731 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2732 libconf->conf->power_level);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01002733 }
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002734 if (flags & IEEE80211_CONF_CHANGE_POWER)
Helmut Schaa9e33a352011-03-28 13:33:40 +02002735 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2736 libconf->conf->power_level);
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002737 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2738 rt2800_config_retry_limit(rt2x00dev, libconf);
2739 if (flags & IEEE80211_CONF_CHANGE_PS)
2740 rt2800_config_ps(rt2x00dev, libconf);
2741}
2742EXPORT_SYMBOL_GPL(rt2800_config);
2743
2744/*
2745 * Link tuning
2746 */
2747void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2748{
2749 u32 reg;
2750
2751 /*
2752 * Update FCS error count from register.
2753 */
2754 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2755 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2756}
2757EXPORT_SYMBOL_GPL(rt2800_link_stats);
2758
2759static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2760{
2761 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02002762 if (rt2x00_rt(rt2x00dev, RT3070) ||
Gertjan van Wingerde64522952010-04-11 14:31:14 +02002763 rt2x00_rt(rt2x00dev, RT3071) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02002764 rt2x00_rt(rt2x00dev, RT3090) ||
Woody Hunga89534e2012-06-13 15:01:16 +08002765 rt2x00_rt(rt2x00dev, RT3290) ||
Gabor Juhosadde5882011-03-03 11:46:45 +01002766 rt2x00_rt(rt2x00dev, RT3390) ||
John Li2ed71882012-02-17 17:33:06 +08002767 rt2x00_rt(rt2x00dev, RT5390) ||
2768 rt2x00_rt(rt2x00dev, RT5392))
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002769 return 0x1c + (2 * rt2x00dev->lna_gain);
2770 else
2771 return 0x2e + rt2x00dev->lna_gain;
2772 }
2773
2774 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2775 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2776 else
2777 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2778}
2779
2780static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2781 struct link_qual *qual, u8 vgc_level)
2782{
2783 if (qual->vgc_level != vgc_level) {
2784 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2785 qual->vgc_level = vgc_level;
2786 qual->vgc_level_reg = vgc_level;
2787 }
2788}
2789
2790void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2791{
2792 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2793}
2794EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2795
2796void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2797 const u32 count)
2798{
Gertjan van Wingerde8d0c9b62010-04-11 14:31:10 +02002799 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
Bartlomiej Zolnierkiewiczf4450612009-11-04 18:36:40 +01002800 return;
2801
2802 /*
2803 * When RSSI is better then -80 increase VGC level with 0x10
2804 */
2805 rt2800_set_vgc(rt2x00dev, qual,
2806 rt2800_get_default_vgc(rt2x00dev) +
2807 ((qual->rssi > -80) * 0x10));
2808}
2809EXPORT_SYMBOL_GPL(rt2800_link_tuner);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002810
2811/*
2812 * Initialization functions.
2813 */
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02002814static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002815{
2816 u32 reg;
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02002817 u16 eeprom;
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002818 unsigned int i;
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +02002819 int ret;
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002820
Jakub Kicinskif7b395e2012-04-03 03:40:47 +02002821 rt2800_disable_wpdma(rt2x00dev);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02002822
Gertjan van Wingerdee3a896b2010-06-03 10:52:04 +02002823 ret = rt2800_drv_init_registers(rt2x00dev);
2824 if (ret)
2825 return ret;
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002826
2827 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2828 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2829 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2830 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2831 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2832 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2833
2834 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2835 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2836 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2837 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2838 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2839 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2840
2841 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2842 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2843
2844 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2845
2846 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
Helmut Schaa8544df32010-07-11 12:29:49 +02002847 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002848 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2849 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2850 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2851 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2852 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2853 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2854
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02002855 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2856
2857 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2858 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2859 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2860 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2861
Woody Hunga89534e2012-06-13 15:01:16 +08002862 if (rt2x00_rt(rt2x00dev, RT3290)) {
2863 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
2864 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
2865 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
2866 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
2867 }
2868
2869 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
2870 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
2871 rt2x00_set_field32(&reg, LDO0_EN, 1);
2872 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
2873 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
2874 }
2875
2876 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
2877 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
2878 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
2879 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
2880 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
2881
2882 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
2883 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
2884 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
2885
2886 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
2887 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
2888 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
2889 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
2890 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
2891 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
2892
2893 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
2894 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
2895 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
2896 }
2897
Gertjan van Wingerde64522952010-04-11 14:31:14 +02002898 if (rt2x00_rt(rt2x00dev, RT3071) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02002899 rt2x00_rt(rt2x00dev, RT3090) ||
Woody Hunga89534e2012-06-13 15:01:16 +08002900 rt2x00_rt(rt2x00dev, RT3290) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02002901 rt2x00_rt(rt2x00dev, RT3390)) {
Woody Hunga89534e2012-06-13 15:01:16 +08002902
2903 if (rt2x00_rt(rt2x00dev, RT3290))
2904 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2905 0x00000404);
2906 else
2907 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2908 0x00000400);
2909
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002910 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
Gertjan van Wingerde64522952010-04-11 14:31:14 +02002911 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02002912 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2913 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
RA-Jay Hung38c8a562010-12-13 12:31:27 +01002914 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2915 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02002916 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2917 0x0000002c);
2918 else
2919 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2920 0x0000000f);
2921 } else {
2922 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2923 }
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02002924 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002925 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02002926
2927 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2928 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2929 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2930 } else {
2931 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2932 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2933 }
Helmut Schaac295a812010-06-03 10:52:13 +02002934 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2935 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2936 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
Helmut Schaa961636b2011-04-18 15:28:27 +02002937 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02002938 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2939 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2940 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
John Li2ed71882012-02-17 17:33:06 +08002941 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2942 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01002943 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2944 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2945 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002946 } else {
2947 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2948 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2949 }
2950
2951 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2952 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2953 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2954 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2955 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2956 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2957 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2958 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2959 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2960 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2961
2962 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2963 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02002964 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002965 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2966 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2967
2968 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2969 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
Gertjan van Wingerde8d0c9b62010-04-11 14:31:10 +02002970 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
Gertjan van Wingerde49e721e2010-02-13 20:55:49 +01002971 rt2x00_rt(rt2x00dev, RT2883) ||
Gertjan van Wingerde8d0c9b62010-04-11 14:31:10 +02002972 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002973 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2974 else
2975 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2976 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2977 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2978 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2979
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02002980 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2981 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2982 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2983 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2984 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2985 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2986 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2987 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2988 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2989
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01002990 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2991
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02002992 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2993 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2994 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2995 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2996 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2997 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2998 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2999 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3000
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003001 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3002 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003003 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003004 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3005 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003006 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003007 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3008 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3009 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3010
3011 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003012 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003013 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
Shiang Tu6f492b62011-02-20 13:56:54 +01003014 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003015 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3016 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3017 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003018 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003019 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003020 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3021 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003022 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3023
3024 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003025 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003026 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
Shiang Tu6f492b62011-02-20 13:56:54 +01003027 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003028 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3029 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3030 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003031 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003032 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003033 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3034 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003035 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3036
3037 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3038 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3039 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
Shiang Tu6f492b62011-02-20 13:56:54 +01003040 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003041 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3042 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3043 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3044 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3045 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3046 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003047 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003048 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3049
3050 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3051 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
Helmut Schaad13a97f2010-10-02 11:29:08 +02003052 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
Shiang Tu6f492b62011-02-20 13:56:54 +01003053 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003054 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3055 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3056 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3057 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3058 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3059 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003060 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003061 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3062
3063 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3064 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3065 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
Shiang Tu6f492b62011-02-20 13:56:54 +01003066 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003067 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3068 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3069 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3070 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3071 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3072 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003073 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003074 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3075
3076 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3077 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3078 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
Shiang Tu6f492b62011-02-20 13:56:54 +01003079 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003080 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3081 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3082 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3083 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3084 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3085 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003086 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003087 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3088
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +01003089 if (rt2x00_is_usb(rt2x00dev)) {
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003090 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3091
3092 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3093 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3094 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3095 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3096 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3097 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3098 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3099 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3100 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3101 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3102 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3103 }
3104
Helmut Schaa961621a2010-11-04 20:36:59 +01003105 /*
3106 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3107 * although it is reserved.
3108 */
3109 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3110 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3111 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3112 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3113 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3114 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3115 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3116 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3117 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3118 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3119 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3120 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3121
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003122 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
3123
3124 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3125 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3126 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3127 IEEE80211_MAX_RTS_THRESHOLD);
3128 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3129 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3130
3131 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003132
Helmut Schaaa21c2ab2010-05-06 12:29:04 +02003133 /*
3134 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3135 * time should be set to 16. However, the original Ralink driver uses
3136 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3137 * connection problems with 11g + CTS protection. Hence, use the same
3138 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3139 */
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003140 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
Helmut Schaaa21c2ab2010-05-06 12:29:04 +02003141 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3142 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003143 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3144 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3145 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3146 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3147
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003148 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3149
3150 /*
3151 * ASIC will keep garbage value after boot, clear encryption keys.
3152 */
3153 for (i = 0; i < 4; i++)
3154 rt2800_register_write(rt2x00dev,
3155 SHARED_KEY_MODE_ENTRY(i), 0);
3156
3157 for (i = 0; i < 256; i++) {
Helmut Schaad7d259d2011-09-08 14:39:04 +02003158 rt2800_config_wcid(rt2x00dev, NULL, i);
3159 rt2800_delete_wcid_attr(rt2x00dev, i);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003160 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3161 }
3162
3163 /*
3164 * Clear all beacons
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003165 */
Helmut Schaa69cf36a2011-01-30 13:16:03 +01003166 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3167 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3168 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3169 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3170 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3171 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3172 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3173 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003174
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +01003175 if (rt2x00_is_usb(rt2x00dev)) {
Gertjan van Wingerde785c3c02010-06-03 10:51:59 +02003176 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3177 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3178 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
RA-Jay Hungc6fcc0e2011-01-30 13:21:22 +01003179 } else if (rt2x00_is_pcie(rt2x00dev)) {
3180 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3181 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3182 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003183 }
3184
3185 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3186 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3187 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3188 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3189 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3190 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3191 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3192 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3193 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3194 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3195
3196 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3197 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3198 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3199 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3200 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3201 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3202 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3203 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3204 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3205 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3206
3207 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3208 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3209 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3210 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3211 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3212 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3213 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3214 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3215 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3216 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3217
3218 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3219 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3220 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3221 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3222 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3223 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3224
3225 /*
Helmut Schaa47ee3eb2010-09-08 20:56:04 +02003226 * Do not force the BA window size, we use the TXWI to set it
3227 */
3228 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3229 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3230 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3231 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3232
3233 /*
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003234 * We must clear the error counters.
3235 * These registers are cleared on read,
3236 * so we may pass a useless variable to store the value.
3237 */
3238 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3239 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3240 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3241 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3242 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3243 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3244
Helmut Schaa9f926fb2010-07-11 12:28:23 +02003245 /*
3246 * Setup leadtime for pre tbtt interrupt to 6ms
3247 */
3248 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3249 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3250 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3251
Helmut Schaa977206d2010-12-13 12:31:58 +01003252 /*
3253 * Set up channel statistics timer
3254 */
3255 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3256 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3257 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3258 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3259 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3260 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3261 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3262
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003263 return 0;
3264}
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003265
3266static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3267{
3268 unsigned int i;
3269 u32 reg;
3270
3271 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3272 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3273 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3274 return 0;
3275
3276 udelay(REGISTER_BUSY_DELAY);
3277 }
3278
3279 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3280 return -EACCES;
3281}
3282
3283static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3284{
3285 unsigned int i;
3286 u8 value;
3287
3288 /*
3289 * BBP was enabled after firmware was loaded,
3290 * but we need to reactivate it now.
3291 */
3292 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3293 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3294 msleep(1);
3295
3296 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3297 rt2800_bbp_read(rt2x00dev, 0, &value);
3298 if ((value != 0xff) && (value != 0x00))
3299 return 0;
3300 udelay(REGISTER_BUSY_DELAY);
3301 }
3302
3303 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3304 return -EACCES;
3305}
3306
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02003307static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003308{
3309 unsigned int i;
3310 u16 eeprom;
3311 u8 reg_id;
3312 u8 value;
3313
3314 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3315 rt2800_wait_bbp_ready(rt2x00dev)))
3316 return -EACCES;
3317
Woody Hunga89534e2012-06-13 15:01:16 +08003318 if (rt2x00_rt(rt2x00dev, RT3290) ||
3319 rt2x00_rt(rt2x00dev, RT5390) ||
3320 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01003321 rt2800_bbp_read(rt2x00dev, 4, &value);
3322 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3323 rt2800_bbp_write(rt2x00dev, 4, value);
3324 }
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003325
Gabor Juhosadde5882011-03-03 11:46:45 +01003326 if (rt2800_is_305x_soc(rt2x00dev) ||
Woody Hunga89534e2012-06-13 15:01:16 +08003327 rt2x00_rt(rt2x00dev, RT3290) ||
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02003328 rt2x00_rt(rt2x00dev, RT3572) ||
John Li2ed71882012-02-17 17:33:06 +08003329 rt2x00_rt(rt2x00dev, RT5390) ||
3330 rt2x00_rt(rt2x00dev, RT5392))
Helmut Schaabaff8002010-04-28 09:58:59 +02003331 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3332
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003333 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3334 rt2800_bbp_write(rt2x00dev, 66, 0x38);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003335
Woody Hunga89534e2012-06-13 15:01:16 +08003336 if (rt2x00_rt(rt2x00dev, RT3290) ||
3337 rt2x00_rt(rt2x00dev, RT5390) ||
3338 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003339 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003340
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003341 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3342 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3343 rt2800_bbp_write(rt2x00dev, 73, 0x12);
Woody Hunga89534e2012-06-13 15:01:16 +08003344 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3345 rt2x00_rt(rt2x00dev, RT5390) ||
3346 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01003347 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3348 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3349 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3350 rt2800_bbp_write(rt2x00dev, 76, 0x28);
Woody Hunga89534e2012-06-13 15:01:16 +08003351
3352 if (rt2x00_rt(rt2x00dev, RT3290))
3353 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3354 else
3355 rt2800_bbp_write(rt2x00dev, 77, 0x59);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003356 } else {
3357 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3358 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3359 }
3360
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003361 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003362
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003363 if (rt2x00_rt(rt2x00dev, RT3070) ||
Gertjan van Wingerde64522952010-04-11 14:31:14 +02003364 rt2x00_rt(rt2x00dev, RT3071) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003365 rt2x00_rt(rt2x00dev, RT3090) ||
Gabor Juhosadde5882011-03-03 11:46:45 +01003366 rt2x00_rt(rt2x00dev, RT3390) ||
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02003367 rt2x00_rt(rt2x00dev, RT3572) ||
John Li2ed71882012-02-17 17:33:06 +08003368 rt2x00_rt(rt2x00dev, RT5390) ||
3369 rt2x00_rt(rt2x00dev, RT5392)) {
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003370 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3371 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3372 rt2800_bbp_write(rt2x00dev, 81, 0x33);
Helmut Schaabaff8002010-04-28 09:58:59 +02003373 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3374 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3375 rt2800_bbp_write(rt2x00dev, 80, 0x08);
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003376 } else {
3377 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3378 }
3379
Woody Hunga89534e2012-06-13 15:01:16 +08003380 if (rt2x00_rt(rt2x00dev, RT3290)) {
3381 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3382 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3383 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3384 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3385 }
3386
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003387 rt2800_bbp_write(rt2x00dev, 82, 0x62);
Woody Hunga89534e2012-06-13 15:01:16 +08003388 if (rt2x00_rt(rt2x00dev, RT3290) ||
3389 rt2x00_rt(rt2x00dev, RT5390) ||
3390 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003391 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3392 else
3393 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003394
Gertjan van Wingerde5ed8f452010-06-03 10:51:57 +02003395 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003396 rt2800_bbp_write(rt2x00dev, 84, 0x19);
Woody Hunga89534e2012-06-13 15:01:16 +08003397 else if (rt2x00_rt(rt2x00dev, RT3290) ||
3398 rt2x00_rt(rt2x00dev, RT5390) ||
3399 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003400 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
Gertjan van Wingerdea9dce142010-04-11 14:31:11 +02003401 else
3402 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3403
Woody Hunga89534e2012-06-13 15:01:16 +08003404 if (rt2x00_rt(rt2x00dev, RT3290) ||
3405 rt2x00_rt(rt2x00dev, RT5390) ||
3406 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003407 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3408 else
3409 rt2800_bbp_write(rt2x00dev, 86, 0x00);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003410
John Li2ed71882012-02-17 17:33:06 +08003411 if (rt2x00_rt(rt2x00dev, RT5392))
3412 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3413
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003414 rt2800_bbp_write(rt2x00dev, 91, 0x04);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003415
Woody Hunga89534e2012-06-13 15:01:16 +08003416 if (rt2x00_rt(rt2x00dev, RT3290) ||
3417 rt2x00_rt(rt2x00dev, RT5390) ||
3418 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003419 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3420 else
3421 rt2800_bbp_write(rt2x00dev, 92, 0x00);
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003422
John Li2ed71882012-02-17 17:33:06 +08003423 if (rt2x00_rt(rt2x00dev, RT5392)) {
3424 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3425 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3426 }
3427
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003428 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
Gertjan van Wingerde64522952010-04-11 14:31:14 +02003429 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003430 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
Helmut Schaabaff8002010-04-28 09:58:59 +02003431 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
Woody Hunga89534e2012-06-13 15:01:16 +08003432 rt2x00_rt(rt2x00dev, RT3290) ||
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02003433 rt2x00_rt(rt2x00dev, RT3572) ||
Gabor Juhosadde5882011-03-03 11:46:45 +01003434 rt2x00_rt(rt2x00dev, RT5390) ||
John Li2ed71882012-02-17 17:33:06 +08003435 rt2x00_rt(rt2x00dev, RT5392) ||
Helmut Schaabaff8002010-04-28 09:58:59 +02003436 rt2800_is_305x_soc(rt2x00dev))
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003437 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3438 else
3439 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3440
Woody Hunga89534e2012-06-13 15:01:16 +08003441 if (rt2x00_rt(rt2x00dev, RT3290) ||
3442 rt2x00_rt(rt2x00dev, RT5390) ||
3443 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003444 rt2800_bbp_write(rt2x00dev, 104, 0x92);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003445
Helmut Schaabaff8002010-04-28 09:58:59 +02003446 if (rt2800_is_305x_soc(rt2x00dev))
3447 rt2800_bbp_write(rt2x00dev, 105, 0x01);
Woody Hunga89534e2012-06-13 15:01:16 +08003448 else if (rt2x00_rt(rt2x00dev, RT3290))
3449 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
John Li2ed71882012-02-17 17:33:06 +08003450 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3451 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003452 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
Helmut Schaabaff8002010-04-28 09:58:59 +02003453 else
3454 rt2800_bbp_write(rt2x00dev, 105, 0x05);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003455
Woody Hunga89534e2012-06-13 15:01:16 +08003456 if (rt2x00_rt(rt2x00dev, RT3290) ||
3457 rt2x00_rt(rt2x00dev, RT5390))
Gabor Juhosadde5882011-03-03 11:46:45 +01003458 rt2800_bbp_write(rt2x00dev, 106, 0x03);
John Li2ed71882012-02-17 17:33:06 +08003459 else if (rt2x00_rt(rt2x00dev, RT5392))
3460 rt2800_bbp_write(rt2x00dev, 106, 0x12);
Gabor Juhosadde5882011-03-03 11:46:45 +01003461 else
3462 rt2800_bbp_write(rt2x00dev, 106, 0x35);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003463
Woody Hunga89534e2012-06-13 15:01:16 +08003464 if (rt2x00_rt(rt2x00dev, RT3290) ||
3465 rt2x00_rt(rt2x00dev, RT5390) ||
3466 rt2x00_rt(rt2x00dev, RT5392))
Gabor Juhosadde5882011-03-03 11:46:45 +01003467 rt2800_bbp_write(rt2x00dev, 128, 0x12);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003468
John Li2ed71882012-02-17 17:33:06 +08003469 if (rt2x00_rt(rt2x00dev, RT5392)) {
3470 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3471 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3472 }
3473
Gertjan van Wingerde64522952010-04-11 14:31:14 +02003474 if (rt2x00_rt(rt2x00dev, RT3071) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003475 rt2x00_rt(rt2x00dev, RT3090) ||
Gabor Juhosadde5882011-03-03 11:46:45 +01003476 rt2x00_rt(rt2x00dev, RT3390) ||
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02003477 rt2x00_rt(rt2x00dev, RT3572) ||
John Li2ed71882012-02-17 17:33:06 +08003478 rt2x00_rt(rt2x00dev, RT5390) ||
3479 rt2x00_rt(rt2x00dev, RT5392)) {
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003480 rt2800_bbp_read(rt2x00dev, 138, &value);
3481
RA-Jay Hung38c8a562010-12-13 12:31:27 +01003482 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3483 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003484 value |= 0x20;
RA-Jay Hung38c8a562010-12-13 12:31:27 +01003485 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003486 value &= ~0x02;
3487
3488 rt2800_bbp_write(rt2x00dev, 138, value);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003489 }
3490
Woody Hunga89534e2012-06-13 15:01:16 +08003491 if (rt2x00_rt(rt2x00dev, RT3290)) {
3492 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3493 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3494 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3495 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3496 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3497 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3498 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3499 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3500 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3501 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3502
3503 rt2800_bbp_read(rt2x00dev, 47, &value);
3504 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3505 rt2800_bbp_write(rt2x00dev, 47, value);
3506
3507 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3508 rt2800_bbp_read(rt2x00dev, 3, &value);
3509 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3510 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3511 rt2800_bbp_write(rt2x00dev, 3, value);
3512 }
3513
John Li2ed71882012-02-17 17:33:06 +08003514 if (rt2x00_rt(rt2x00dev, RT5390) ||
3515 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01003516 int ant, div_mode;
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003517
Gabor Juhosadde5882011-03-03 11:46:45 +01003518 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3519 div_mode = rt2x00_get_field16(eeprom,
3520 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3521 ant = (div_mode == 3) ? 1 : 0;
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003522
Gabor Juhosadde5882011-03-03 11:46:45 +01003523 /* check if this is a Bluetooth combo card */
Gertjan van Wingerdefdbc7b02011-04-30 17:15:37 +02003524 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01003525 u32 reg;
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003526
Gabor Juhosadde5882011-03-03 11:46:45 +01003527 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3528 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3529 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3530 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3531 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3532 if (ant == 0)
3533 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3534 else if (ant == 1)
3535 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3536 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3537 }
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003538
Anisse Astier0586a112012-04-23 12:33:11 +02003539 /* This chip has hardware antenna diversity*/
3540 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3541 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3542 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3543 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3544 }
3545
Gabor Juhosadde5882011-03-03 11:46:45 +01003546 rt2800_bbp_read(rt2x00dev, 152, &value);
3547 if (ant == 0)
3548 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3549 else
3550 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3551 rt2800_bbp_write(rt2x00dev, 152, value);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003552
Gabor Juhosadde5882011-03-03 11:46:45 +01003553 /* Init frequency calibration */
3554 rt2800_bbp_write(rt2x00dev, 142, 1);
3555 rt2800_bbp_write(rt2x00dev, 143, 57);
3556 }
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003557
3558 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3559 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3560
3561 if (eeprom != 0xffff && eeprom != 0x0000) {
3562 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3563 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3564 rt2800_bbp_write(rt2x00dev, reg_id, value);
3565 }
3566 }
3567
3568 return 0;
3569}
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003570
3571static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3572 bool bw40, u8 rfcsr24, u8 filter_target)
3573{
3574 unsigned int i;
3575 u8 bbp;
3576 u8 rfcsr;
3577 u8 passband;
3578 u8 stopband;
3579 u8 overtuned = 0;
3580
3581 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3582
3583 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3584 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3585 rt2800_bbp_write(rt2x00dev, 4, bbp);
3586
RA-Jay Hung80d184e2011-01-10 11:28:10 +01003587 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3588 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3589 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3590
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003591 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3592 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3593 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3594
3595 /*
3596 * Set power & frequency of passband test tone
3597 */
3598 rt2800_bbp_write(rt2x00dev, 24, 0);
3599
3600 for (i = 0; i < 100; i++) {
3601 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3602 msleep(1);
3603
3604 rt2800_bbp_read(rt2x00dev, 55, &passband);
3605 if (passband)
3606 break;
3607 }
3608
3609 /*
3610 * Set power & frequency of stopband test tone
3611 */
3612 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3613
3614 for (i = 0; i < 100; i++) {
3615 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3616 msleep(1);
3617
3618 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3619
3620 if ((passband - stopband) <= filter_target) {
3621 rfcsr24++;
3622 overtuned += ((passband - stopband) == filter_target);
3623 } else
3624 break;
3625
3626 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3627 }
3628
3629 rfcsr24 -= !!overtuned;
3630
3631 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3632 return rfcsr24;
3633}
3634
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02003635static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003636{
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01003637 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003638 u8 rfcsr;
3639 u8 bbp;
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003640 u32 reg;
3641 u16 eeprom;
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003642
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003643 if (!rt2x00_rt(rt2x00dev, RT3070) &&
Gertjan van Wingerde64522952010-04-11 14:31:14 +02003644 !rt2x00_rt(rt2x00dev, RT3071) &&
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003645 !rt2x00_rt(rt2x00dev, RT3090) &&
Woody Hunga89534e2012-06-13 15:01:16 +08003646 !rt2x00_rt(rt2x00dev, RT3290) &&
Helmut Schaa23812382010-04-26 13:48:45 +02003647 !rt2x00_rt(rt2x00dev, RT3390) &&
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02003648 !rt2x00_rt(rt2x00dev, RT3572) &&
Gabor Juhosadde5882011-03-03 11:46:45 +01003649 !rt2x00_rt(rt2x00dev, RT5390) &&
John Li2ed71882012-02-17 17:33:06 +08003650 !rt2x00_rt(rt2x00dev, RT5392) &&
Helmut Schaabaff8002010-04-28 09:58:59 +02003651 !rt2800_is_305x_soc(rt2x00dev))
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003652 return 0;
3653
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003654 /*
3655 * Init RF calibration.
3656 */
Woody Hunga89534e2012-06-13 15:01:16 +08003657 if (rt2x00_rt(rt2x00dev, RT3290) ||
3658 rt2x00_rt(rt2x00dev, RT5390) ||
3659 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01003660 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3661 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3662 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3663 msleep(1);
3664 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3665 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3666 } else {
3667 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3668 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3669 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3670 msleep(1);
3671 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3672 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3673 }
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003674
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003675 if (rt2x00_rt(rt2x00dev, RT3070) ||
Gertjan van Wingerde64522952010-04-11 14:31:14 +02003676 rt2x00_rt(rt2x00dev, RT3071) ||
3677 rt2x00_rt(rt2x00dev, RT3090)) {
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003678 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3679 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3680 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
RA-Jay Hung80d184e2011-01-10 11:28:10 +01003681 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003682 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003683 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003684 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3685 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3686 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3687 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3688 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3689 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3690 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3691 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3692 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3693 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3694 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3695 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003696 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
Woody Hunga89534e2012-06-13 15:01:16 +08003697 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3698 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3699 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3700 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3701 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3702 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3703 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3704 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3705 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3706 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3707 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3708 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3709 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3710 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3711 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3712 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3713 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3714 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3715 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3716 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3717 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3718 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3719 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3720 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3721 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3722 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3723 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3724 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3725 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3726 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3727 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3728 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3729 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3730 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3731 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3732 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3733 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3734 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3735 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3736 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3737 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3738 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3739 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3740 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3741 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3742 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3743 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003744 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3745 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3746 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3747 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3748 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003749 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003750 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3751 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3752 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3753 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3754 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3755 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003756 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003757 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3758 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003759 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003760 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3761 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3762 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3763 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3764 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3765 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3766 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003767 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003768 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01003769 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02003770 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3771 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3772 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3773 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3774 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3775 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3776 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02003777 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3778 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3779 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3780 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3781 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3782 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3783 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3784 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3785 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3786 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3787 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3788 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3789 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3790 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3791 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3792 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3793 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3794 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3795 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3796 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3797 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3798 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3799 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3800 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3801 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3802 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3803 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3804 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3805 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3806 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3807 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3808 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
Helmut Schaabaff8002010-04-28 09:58:59 +02003809 } else if (rt2800_is_305x_soc(rt2x00dev)) {
Helmut Schaa23812382010-04-26 13:48:45 +02003810 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3811 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3812 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3813 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3814 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3815 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3816 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3817 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3818 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3819 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3820 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3821 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3822 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3823 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3824 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3825 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3826 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3827 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3828 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3829 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3830 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3831 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3832 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3833 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3834 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3835 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3836 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3837 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3838 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3839 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
Helmut Schaabaff8002010-04-28 09:58:59 +02003840 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3841 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3842 return 0;
Gabor Juhosadde5882011-03-03 11:46:45 +01003843 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3844 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3845 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3846 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3847 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3848 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3849 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3850 else
3851 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3852 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3853 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3854 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3855 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3856 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3857 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3858 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3859 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3860 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3861 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003862
Gabor Juhosadde5882011-03-03 11:46:45 +01003863 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3864 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3865 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3866 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3867 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3868 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3869 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3870 else
3871 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3872 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3873 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3874 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3875 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003876
Gabor Juhosadde5882011-03-03 11:46:45 +01003877 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3878 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3879 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3880 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3881 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3882 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3883 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3884 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3885 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3886 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003887
Gabor Juhosadde5882011-03-03 11:46:45 +01003888 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3889 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3890 else
3891 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3892 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3893 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3894 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3895 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3896 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3897 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3898 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3899 else
3900 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3901 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3902 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3903 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003904
Gabor Juhosadde5882011-03-03 11:46:45 +01003905 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3906 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3907 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3908 else
3909 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3910 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3911 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3912 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3913 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3914 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3915 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01003916
Gabor Juhosadde5882011-03-03 11:46:45 +01003917 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3918 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3919 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3920 else
3921 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3922 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3923 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
John Li2ed71882012-02-17 17:33:06 +08003924 } else if (rt2x00_rt(rt2x00dev, RT5392)) {
3925 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3926 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3927 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3928 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3929 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3930 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3931 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3932 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3933 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3934 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3935 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3936 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3937 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3938 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3939 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
3940 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3941 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
3942 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3943 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
3944 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
3945 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3946 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3947 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3948 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3949 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3950 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3951 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3952 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
3953 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
3954 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3955 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3956 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3957 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3958 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3959 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3960 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
3961 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3962 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3963 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
3964 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3965 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3966 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3967 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
3968 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3969 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3970 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
3971 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
3972 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3973 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
3974 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3975 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3976 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
3977 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3978 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3979 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
3980 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3981 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3982 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3983 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02003984 }
3985
3986 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3987 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3988 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3989 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3990 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
Gertjan van Wingerde64522952010-04-11 14:31:14 +02003991 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3992 rt2x00_rt(rt2x00dev, RT3090)) {
RA-Jay Hung80d184e2011-01-10 11:28:10 +01003993 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3994
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003995 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3996 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3997 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3998
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02003999 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4000 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
Gertjan van Wingerde64522952010-04-11 14:31:14 +02004001 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4002 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004003 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4004 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02004005 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4006 else
4007 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4008 }
4009 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
RA-Jay Hung80d184e2011-01-10 11:28:10 +01004010
4011 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4012 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4013 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02004014 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4015 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4016 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4017 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02004018 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4019 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4020 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4021 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4022
4023 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4024 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4025 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4026 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4027 msleep(1);
4028 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4029 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4030 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01004031 }
4032
4033 /*
4034 * Set RX Filter calibration for 20MHz and 40MHz
4035 */
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004036 if (rt2x00_rt(rt2x00dev, RT3070)) {
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01004037 drv_data->calibration_bw20 =
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004038 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01004039 drv_data->calibration_bw40 =
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004040 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
Gertjan van Wingerde64522952010-04-11 14:31:14 +02004041 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02004042 rt2x00_rt(rt2x00dev, RT3090) ||
Gertjan van Wingerde872834d2011-05-18 20:25:31 +02004043 rt2x00_rt(rt2x00dev, RT3390) ||
4044 rt2x00_rt(rt2x00dev, RT3572)) {
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01004045 drv_data->calibration_bw20 =
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02004046 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
Gertjan van Wingerde3a1c0122012-02-06 23:45:07 +01004047 drv_data->calibration_bw40 =
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02004048 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004049 }
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01004050
Gertjan van Wingerde5d137df2012-02-06 23:45:09 +01004051 /*
4052 * Save BBP 25 & 26 values for later use in channel switching
4053 */
4054 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4055 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4056
John Li2ed71882012-02-17 17:33:06 +08004057 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4058 !rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01004059 /*
4060 * Set back to initial state
4061 */
4062 rt2800_bbp_write(rt2x00dev, 24, 0);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01004063
Gabor Juhosadde5882011-03-03 11:46:45 +01004064 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4065 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4066 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01004067
Gabor Juhosadde5882011-03-03 11:46:45 +01004068 /*
4069 * Set BBP back to BW20
4070 */
4071 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4072 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4073 rt2800_bbp_write(rt2x00dev, 4, bbp);
4074 }
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01004075
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02004076 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
Gertjan van Wingerde64522952010-04-11 14:31:14 +02004077 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02004078 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4079 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004080 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4081
4082 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4083 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4084 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4085
John Li2ed71882012-02-17 17:33:06 +08004086 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4087 !rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01004088 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4089 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4090 if (rt2x00_rt(rt2x00dev, RT3070) ||
4091 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4092 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4093 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02004094 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4095 &rt2x00dev->cap_flags))
Gabor Juhosadde5882011-03-03 11:46:45 +01004096 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4097 }
Gertjan van Wingerde77c06c22012-02-06 23:45:13 +01004098 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4099 drv_data->txmixer_gain_24g);
Gabor Juhosadde5882011-03-03 11:46:45 +01004100 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4101 }
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004102
Gertjan van Wingerde64522952010-04-11 14:31:14 +02004103 if (rt2x00_rt(rt2x00dev, RT3090)) {
4104 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4105
RA-Jay Hung80d184e2011-01-10 11:28:10 +01004106 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004107 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4108 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
Gertjan van Wingerde64522952010-04-11 14:31:14 +02004109 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004110 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
Gertjan van Wingerde64522952010-04-11 14:31:14 +02004111 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4112
4113 rt2800_bbp_write(rt2x00dev, 138, bbp);
4114 }
4115
4116 if (rt2x00_rt(rt2x00dev, RT3071) ||
Gertjan van Wingerdecc78e902010-04-11 14:31:15 +02004117 rt2x00_rt(rt2x00dev, RT3090) ||
4118 rt2x00_rt(rt2x00dev, RT3390)) {
Gertjan van Wingerded5385bf2010-04-11 14:31:13 +02004119 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4120 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4121 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4122 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4123 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4124 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4125 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4126
4127 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4128 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4129 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4130
4131 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4132 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4133 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4134
4135 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4136 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4137 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4138 }
4139
RA-Jay Hung80d184e2011-01-10 11:28:10 +01004140 if (rt2x00_rt(rt2x00dev, RT3070)) {
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004141 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
RA-Jay Hung80d184e2011-01-10 11:28:10 +01004142 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
Gertjan van Wingerde8cdd15e2010-04-11 14:31:12 +02004143 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4144 else
4145 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4146 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4147 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4148 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4149 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4150 }
4151
Woody Hunga89534e2012-06-13 15:01:16 +08004152 if (rt2x00_rt(rt2x00dev, RT3290)) {
4153 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4154 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4155 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4156 }
4157
John Li2ed71882012-02-17 17:33:06 +08004158 if (rt2x00_rt(rt2x00dev, RT5390) ||
4159 rt2x00_rt(rt2x00dev, RT5392)) {
Gabor Juhosadde5882011-03-03 11:46:45 +01004160 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4161 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4162 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01004163
Gabor Juhosadde5882011-03-03 11:46:45 +01004164 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4165 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4166 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01004167
Gabor Juhosadde5882011-03-03 11:46:45 +01004168 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4169 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4170 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4171 }
RA-Shiang Tu60687ba2011-02-20 13:57:46 +01004172
Bartlomiej Zolnierkiewiczfcf51542009-11-04 18:36:57 +01004173 return 0;
4174}
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02004175
4176int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4177{
4178 u32 reg;
4179 u16 word;
4180
4181 /*
4182 * Initialize all registers.
4183 */
4184 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4185 rt2800_init_registers(rt2x00dev) ||
4186 rt2800_init_bbp(rt2x00dev) ||
4187 rt2800_init_rfcsr(rt2x00dev)))
4188 return -EIO;
4189
4190 /*
4191 * Send signal to firmware during boot time.
4192 */
4193 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4194
4195 if (rt2x00_is_usb(rt2x00dev) &&
4196 (rt2x00_rt(rt2x00dev, RT3070) ||
4197 rt2x00_rt(rt2x00dev, RT3071) ||
4198 rt2x00_rt(rt2x00dev, RT3572))) {
4199 udelay(200);
4200 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4201 udelay(10);
4202 }
4203
4204 /*
4205 * Enable RX.
4206 */
4207 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4208 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4209 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4210 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4211
4212 udelay(50);
4213
4214 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4215 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4216 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4217 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4218 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4219 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4220
4221 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4222 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4223 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4224 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4225
4226 /*
4227 * Initialize LED control
4228 */
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004229 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4230 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02004231 word & 0xff, (word >> 8) & 0xff);
4232
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004233 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4234 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02004235 word & 0xff, (word >> 8) & 0xff);
4236
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004237 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4238 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02004239 word & 0xff, (word >> 8) & 0xff);
4240
4241 return 0;
4242}
4243EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4244
4245void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4246{
4247 u32 reg;
4248
Jakub Kicinskif7b395e2012-04-03 03:40:47 +02004249 rt2800_disable_wpdma(rt2x00dev);
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02004250
4251 /* Wait for DMA, ignore error */
4252 rt2800_wait_wpdma_ready(rt2x00dev);
4253
4254 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4255 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4256 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4257 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
Ivo van Doornb9a07ae2010-08-23 19:55:22 +02004258}
4259EXPORT_SYMBOL_GPL(rt2800_disable_radio);
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004260
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004261int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4262{
4263 u32 reg;
Woody Hunga89534e2012-06-13 15:01:16 +08004264 u16 efuse_ctrl_reg;
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004265
Woody Hunga89534e2012-06-13 15:01:16 +08004266 if (rt2x00_rt(rt2x00dev, RT3290))
4267 efuse_ctrl_reg = EFUSE_CTRL_3290;
4268 else
4269 efuse_ctrl_reg = EFUSE_CTRL;
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004270
Woody Hunga89534e2012-06-13 15:01:16 +08004271 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004272 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4273}
4274EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4275
4276static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4277{
4278 u32 reg;
Woody Hunga89534e2012-06-13 15:01:16 +08004279 u16 efuse_ctrl_reg;
4280 u16 efuse_data0_reg;
4281 u16 efuse_data1_reg;
4282 u16 efuse_data2_reg;
4283 u16 efuse_data3_reg;
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004284
Woody Hunga89534e2012-06-13 15:01:16 +08004285 if (rt2x00_rt(rt2x00dev, RT3290)) {
4286 efuse_ctrl_reg = EFUSE_CTRL_3290;
4287 efuse_data0_reg = EFUSE_DATA0_3290;
4288 efuse_data1_reg = EFUSE_DATA1_3290;
4289 efuse_data2_reg = EFUSE_DATA2_3290;
4290 efuse_data3_reg = EFUSE_DATA3_3290;
4291 } else {
4292 efuse_ctrl_reg = EFUSE_CTRL;
4293 efuse_data0_reg = EFUSE_DATA0;
4294 efuse_data1_reg = EFUSE_DATA1;
4295 efuse_data2_reg = EFUSE_DATA2;
4296 efuse_data3_reg = EFUSE_DATA3;
4297 }
Gertjan van Wingerde31a4cf12009-11-14 20:20:36 +01004298 mutex_lock(&rt2x00dev->csr_mutex);
4299
Woody Hunga89534e2012-06-13 15:01:16 +08004300 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004301 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4302 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4303 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
Woody Hunga89534e2012-06-13 15:01:16 +08004304 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004305
4306 /* Wait until the EEPROM has been loaded */
Woody Hunga89534e2012-06-13 15:01:16 +08004307 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004308 /* Apparently the data is read from end to start */
Woody Hunga89534e2012-06-13 15:01:16 +08004309 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
Larry Fingerdaabead2011-09-14 16:50:23 -05004310 /* The returned value is in CPU order, but eeprom is le */
Gertjan van Wingerde68fa64e2011-11-16 23:16:15 +01004311 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
Woody Hunga89534e2012-06-13 15:01:16 +08004312 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
Larry Fingerdaabead2011-09-14 16:50:23 -05004313 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
Woody Hunga89534e2012-06-13 15:01:16 +08004314 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
Larry Fingerdaabead2011-09-14 16:50:23 -05004315 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
Woody Hunga89534e2012-06-13 15:01:16 +08004316 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
Larry Fingerdaabead2011-09-14 16:50:23 -05004317 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
Gertjan van Wingerde31a4cf12009-11-14 20:20:36 +01004318
4319 mutex_unlock(&rt2x00dev->csr_mutex);
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +01004320}
4321
4322void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4323{
4324 unsigned int i;
4325
4326 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4327 rt2800_efuse_read(rt2x00dev, i);
4328}
4329EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4330
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004331int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4332{
Gertjan van Wingerde77c06c22012-02-06 23:45:13 +01004333 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004334 u16 word;
4335 u8 *mac;
4336 u8 default_lna_gain;
4337
4338 /*
4339 * Start validation of the data that has been read.
4340 */
4341 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4342 if (!is_valid_ether_addr(mac)) {
4343 random_ether_addr(mac);
4344 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4345 }
4346
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004347 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004348 if (word == 0xffff) {
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004349 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4350 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4351 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4352 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004353 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
Gertjan van Wingerde49e721e2010-02-13 20:55:49 +01004354 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
Gertjan van Wingerdee148b4c2010-04-11 14:31:09 +02004355 rt2x00_rt(rt2x00dev, RT2872)) {
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004356 /*
4357 * There is a max of 2 RX streams for RT28x0 series
4358 */
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004359 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4360 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4361 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004362 }
4363
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004364 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004365 if (word == 0xffff) {
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004366 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4367 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4368 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4369 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4370 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4371 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4372 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4373 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4374 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4375 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4376 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4377 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4378 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4379 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4380 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4381 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004382 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4383 }
4384
4385 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4386 if ((word & 0x00ff) == 0x00ff) {
4387 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
Gertjan van Wingerdeec2d1792010-06-29 21:44:50 +02004388 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4389 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4390 }
4391 if ((word & 0xff00) == 0xff00) {
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004392 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4393 LED_MODE_TXRX_ACTIVITY);
4394 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4395 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004396 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4397 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4398 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
Gertjan van Wingerdeec2d1792010-06-29 21:44:50 +02004399 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004400 }
4401
4402 /*
4403 * During the LNA validation we are going to use
4404 * lna0 as correct value. Note that EEPROM_LNA
4405 * is never validated.
4406 */
4407 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4408 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4409
4410 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4411 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4412 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4413 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4414 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4415 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4416
Gertjan van Wingerde77c06c22012-02-06 23:45:13 +01004417 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4418 if ((word & 0x00ff) != 0x00ff) {
4419 drv_data->txmixer_gain_24g =
4420 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4421 } else {
4422 drv_data->txmixer_gain_24g = 0;
4423 }
4424
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004425 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4426 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4427 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4428 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4429 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4430 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4431 default_lna_gain);
4432 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4433
Gertjan van Wingerde77c06c22012-02-06 23:45:13 +01004434 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4435 if ((word & 0x00ff) != 0x00ff) {
4436 drv_data->txmixer_gain_5g =
4437 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4438 } else {
4439 drv_data->txmixer_gain_5g = 0;
4440 }
4441
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004442 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4443 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4444 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4445 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4446 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4447 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4448
4449 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4450 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4451 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4452 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4453 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4454 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4455 default_lna_gain);
4456 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4457
4458 return 0;
4459}
4460EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4461
4462int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4463{
4464 u32 reg;
4465 u16 value;
4466 u16 eeprom;
4467
4468 /*
4469 * Read EEPROM word for configuration.
4470 */
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004471 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004472
4473 /*
Gabor Juhosadde5882011-03-03 11:46:45 +01004474 * Identify RF chipset by EEPROM value
4475 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4476 * RT53xx: defined in "EEPROM_CHIP_ID" field
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004477 */
Woody Hunga89534e2012-06-13 15:01:16 +08004478 if (rt2x00_rt(rt2x00dev, RT3290))
4479 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
4480 else
4481 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4482
4483 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4484 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4485 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
Gabor Juhosadde5882011-03-03 11:46:45 +01004486 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4487 else
4488 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004489
Gertjan van Wingerde49e721e2010-02-13 20:55:49 +01004490 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4491 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
Gertjan van Wingerde714fa662010-02-13 20:55:48 +01004492
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01004493 switch (rt2x00dev->chip.rt) {
4494 case RT2860:
4495 case RT2872:
4496 case RT2883:
4497 case RT3070:
4498 case RT3071:
4499 case RT3090:
Woody Hunga89534e2012-06-13 15:01:16 +08004500 case RT3290:
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01004501 case RT3390:
4502 case RT3572:
4503 case RT5390:
John Li2ed71882012-02-17 17:33:06 +08004504 case RT5392:
Gertjan van Wingerde5aa57012011-12-28 01:53:20 +01004505 break;
4506 default:
John Lib6df7f12012-02-08 21:25:24 +08004507 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
Gertjan van Wingerde49e721e2010-02-13 20:55:49 +01004508 return -ENODEV;
4509 }
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004510
Larry Fingerd331eb52011-09-14 16:50:22 -05004511 switch (rt2x00dev->chip.rf) {
4512 case RF2820:
4513 case RF2850:
4514 case RF2720:
4515 case RF2750:
4516 case RF3020:
4517 case RF2020:
4518 case RF3021:
4519 case RF3022:
4520 case RF3052:
Woody Hunga89534e2012-06-13 15:01:16 +08004521 case RF3290:
Larry Fingerd331eb52011-09-14 16:50:22 -05004522 case RF3320:
villacis@palosanto.comccf91bd2012-05-16 21:07:12 +02004523 case RF5360:
Larry Fingerd331eb52011-09-14 16:50:22 -05004524 case RF5370:
John Li2ed71882012-02-17 17:33:06 +08004525 case RF5372:
Larry Fingerd331eb52011-09-14 16:50:22 -05004526 case RF5390:
Zero.Lincff3d1f2012-05-29 16:11:09 +08004527 case RF5392:
Larry Fingerd331eb52011-09-14 16:50:22 -05004528 break;
4529 default:
John Lib6df7f12012-02-08 21:25:24 +08004530 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
Larry Fingerd331eb52011-09-14 16:50:22 -05004531 rt2x00dev->chip.rf);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004532 return -ENODEV;
4533 }
4534
4535 /*
4536 * Identify default antenna configuration.
4537 */
RA-Jay Hungd96aa642011-02-20 13:54:52 +01004538 rt2x00dev->default_ant.tx_chain_num =
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004539 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
RA-Jay Hungd96aa642011-02-20 13:54:52 +01004540 rt2x00dev->default_ant.rx_chain_num =
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004541 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004542
RA-Jay Hungd96aa642011-02-20 13:54:52 +01004543 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4544
4545 if (rt2x00_rt(rt2x00dev, RT3070) ||
4546 rt2x00_rt(rt2x00dev, RT3090) ||
4547 rt2x00_rt(rt2x00dev, RT3390)) {
4548 value = rt2x00_get_field16(eeprom,
4549 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4550 switch (value) {
4551 case 0:
4552 case 1:
4553 case 2:
4554 rt2x00dev->default_ant.tx = ANTENNA_A;
4555 rt2x00dev->default_ant.rx = ANTENNA_A;
4556 break;
4557 case 3:
4558 rt2x00dev->default_ant.tx = ANTENNA_A;
4559 rt2x00dev->default_ant.rx = ANTENNA_B;
4560 break;
4561 }
4562 } else {
4563 rt2x00dev->default_ant.tx = ANTENNA_A;
4564 rt2x00dev->default_ant.rx = ANTENNA_A;
4565 }
4566
Anisse Astier0586a112012-04-23 12:33:11 +02004567 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4568 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4569 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4570 }
4571
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004572 /*
Gertjan van Wingerde9328fda2011-04-30 17:15:13 +02004573 * Determine external LNA informations.
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004574 */
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004575 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02004576 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004577 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02004578 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004579
4580 /*
4581 * Detect if this device has an hardware controlled radio.
4582 */
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004583 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02004584 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004585
4586 /*
Gertjan van Wingerdefdbc7b02011-04-30 17:15:37 +02004587 * Detect if this device has Bluetooth co-existence.
4588 */
4589 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4590 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4591
4592 /*
Gertjan van Wingerde9328fda2011-04-30 17:15:13 +02004593 * Read frequency offset and RF programming sequence.
4594 */
4595 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4596 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4597
4598 /*
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004599 * Store led settings, for correct led behaviour.
4600 */
4601#ifdef CONFIG_RT2X00_LIB_LEDS
4602 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4603 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4604 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4605
Gertjan van Wingerde9328fda2011-04-30 17:15:13 +02004606 rt2x00dev->led_mcu_reg = eeprom;
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004607#endif /* CONFIG_RT2X00_LIB_LEDS */
4608
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01004609 /*
4610 * Check if support EIRP tx power limit feature.
4611 */
4612 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4613
4614 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4615 EIRP_MAX_TX_POWER_LIMIT)
Ivo van Doorn7dab73b2011-04-18 15:27:06 +02004616 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01004617
Bartlomiej Zolnierkiewicz38bd7b82009-11-08 14:39:01 +01004618 return 0;
4619}
4620EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4621
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004622/*
Ivo van Doorn55f93212010-05-06 14:45:46 +02004623 * RF value list for rt28xx
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004624 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4625 */
4626static const struct rf_channel rf_vals[] = {
4627 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4628 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4629 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4630 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4631 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4632 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4633 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4634 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4635 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4636 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4637 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4638 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4639 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4640 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4641
4642 /* 802.11 UNI / HyperLan 2 */
4643 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4644 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4645 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4646 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4647 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4648 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4649 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4650 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4651 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4652 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4653 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4654 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4655
4656 /* 802.11 HyperLan 2 */
4657 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4658 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4659 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4660 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4661 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4662 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4663 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4664 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4665 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4666 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4667 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4668 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4669 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4670 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4671 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4672 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4673
4674 /* 802.11 UNII */
4675 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4676 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4677 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4678 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4679 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4680 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4681 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4682 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4683 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4684 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4685 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4686
4687 /* 802.11 Japan */
4688 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4689 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4690 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4691 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4692 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4693 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4694 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4695};
4696
4697/*
Ivo van Doorn55f93212010-05-06 14:45:46 +02004698 * RF value list for rt3xxx
4699 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004700 */
Ivo van Doorn55f93212010-05-06 14:45:46 +02004701static const struct rf_channel rf_vals_3x[] = {
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004702 {1, 241, 2, 2 },
4703 {2, 241, 2, 7 },
4704 {3, 242, 2, 2 },
4705 {4, 242, 2, 7 },
4706 {5, 243, 2, 2 },
4707 {6, 243, 2, 7 },
4708 {7, 244, 2, 2 },
4709 {8, 244, 2, 7 },
4710 {9, 245, 2, 2 },
4711 {10, 245, 2, 7 },
4712 {11, 246, 2, 2 },
4713 {12, 246, 2, 7 },
4714 {13, 247, 2, 2 },
4715 {14, 248, 2, 4 },
Ivo van Doorn55f93212010-05-06 14:45:46 +02004716
4717 /* 802.11 UNI / HyperLan 2 */
4718 {36, 0x56, 0, 4},
4719 {38, 0x56, 0, 6},
4720 {40, 0x56, 0, 8},
4721 {44, 0x57, 0, 0},
4722 {46, 0x57, 0, 2},
4723 {48, 0x57, 0, 4},
4724 {52, 0x57, 0, 8},
4725 {54, 0x57, 0, 10},
4726 {56, 0x58, 0, 0},
4727 {60, 0x58, 0, 4},
4728 {62, 0x58, 0, 6},
4729 {64, 0x58, 0, 8},
4730
4731 /* 802.11 HyperLan 2 */
4732 {100, 0x5b, 0, 8},
4733 {102, 0x5b, 0, 10},
4734 {104, 0x5c, 0, 0},
4735 {108, 0x5c, 0, 4},
4736 {110, 0x5c, 0, 6},
4737 {112, 0x5c, 0, 8},
4738 {116, 0x5d, 0, 0},
4739 {118, 0x5d, 0, 2},
4740 {120, 0x5d, 0, 4},
4741 {124, 0x5d, 0, 8},
4742 {126, 0x5d, 0, 10},
4743 {128, 0x5e, 0, 0},
4744 {132, 0x5e, 0, 4},
4745 {134, 0x5e, 0, 6},
4746 {136, 0x5e, 0, 8},
4747 {140, 0x5f, 0, 0},
4748
4749 /* 802.11 UNII */
4750 {149, 0x5f, 0, 9},
4751 {151, 0x5f, 0, 11},
4752 {153, 0x60, 0, 1},
4753 {157, 0x60, 0, 5},
4754 {159, 0x60, 0, 7},
4755 {161, 0x60, 0, 9},
4756 {165, 0x61, 0, 1},
4757 {167, 0x61, 0, 3},
4758 {169, 0x61, 0, 5},
4759 {171, 0x61, 0, 7},
4760 {173, 0x61, 0, 9},
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004761};
4762
4763int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4764{
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004765 struct hw_mode_spec *spec = &rt2x00dev->spec;
4766 struct channel_info *info;
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02004767 char *default_power1;
4768 char *default_power2;
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004769 unsigned int i;
4770 u16 eeprom;
4771
4772 /*
Gertjan van Wingerde93b6bd22009-12-14 20:33:55 +01004773 * Disable powersaving as default on PCI devices.
4774 */
Gertjan van Wingerdecea90e52010-02-13 20:55:47 +01004775 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
Gertjan van Wingerde93b6bd22009-12-14 20:33:55 +01004776 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4777
4778 /*
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004779 * Initialize all hw fields.
4780 */
4781 rt2x00dev->hw->flags =
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004782 IEEE80211_HW_SIGNAL_DBM |
4783 IEEE80211_HW_SUPPORTS_PS |
Helmut Schaa1df90802010-06-29 21:38:12 +02004784 IEEE80211_HW_PS_NULLFUNC_STACK |
Helmut Schaa9d4f09b2012-03-14 08:56:47 +01004785 IEEE80211_HW_AMPDU_AGGREGATION |
4786 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4787
Helmut Schaa5a5b6ed2010-10-02 11:31:33 +02004788 /*
4789 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4790 * unless we are capable of sending the buffered frames out after the
4791 * DTIM transmission using rt2x00lib_beacondone. This will send out
4792 * multicast and broadcast traffic immediately instead of buffering it
4793 * infinitly and thus dropping it after some time.
4794 */
4795 if (!rt2x00_is_usb(rt2x00dev))
4796 rt2x00dev->hw->flags |=
4797 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004798
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004799 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4800 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4801 rt2x00_eeprom_addr(rt2x00dev,
4802 EEPROM_MAC_ADDR_0));
4803
Helmut Schaa3f2bee22010-06-14 22:12:01 +02004804 /*
4805 * As rt2800 has a global fallback table we cannot specify
4806 * more then one tx rate per frame but since the hw will
4807 * try several rates (based on the fallback table) we should
Helmut Schaaba3b9e52010-10-02 11:32:16 +02004808 * initialize max_report_rates to the maximum number of rates
Helmut Schaa3f2bee22010-06-14 22:12:01 +02004809 * we are going to try. Otherwise mac80211 will truncate our
4810 * reported tx rates and the rc algortihm will end up with
4811 * incorrect data.
4812 */
Helmut Schaaba3b9e52010-10-02 11:32:16 +02004813 rt2x00dev->hw->max_rates = 1;
4814 rt2x00dev->hw->max_report_rates = 7;
Helmut Schaa3f2bee22010-06-14 22:12:01 +02004815 rt2x00dev->hw->max_rate_tries = 1;
4816
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004817 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004818
4819 /*
4820 * Initialize hw_mode information.
4821 */
4822 spec->supported_bands = SUPPORT_BAND_2GHZ;
4823 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4824
Gertjan van Wingerde5122d892009-12-23 00:03:25 +01004825 if (rt2x00_rf(rt2x00dev, RF2820) ||
Ivo van Doorn55f93212010-05-06 14:45:46 +02004826 rt2x00_rf(rt2x00dev, RF2720)) {
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004827 spec->num_channels = 14;
4828 spec->channels = rf_vals;
Ivo van Doorn55f93212010-05-06 14:45:46 +02004829 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4830 rt2x00_rf(rt2x00dev, RF2750)) {
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004831 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4832 spec->num_channels = ARRAY_SIZE(rf_vals);
4833 spec->channels = rf_vals;
Gertjan van Wingerde5122d892009-12-23 00:03:25 +01004834 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4835 rt2x00_rf(rt2x00dev, RF2020) ||
4836 rt2x00_rf(rt2x00dev, RF3021) ||
Gertjan van Wingerdef93bc9b2010-11-13 19:09:50 +01004837 rt2x00_rf(rt2x00dev, RF3022) ||
Woody Hunga89534e2012-06-13 15:01:16 +08004838 rt2x00_rf(rt2x00dev, RF3290) ||
Gabor Juhosadde5882011-03-03 11:46:45 +01004839 rt2x00_rf(rt2x00dev, RF3320) ||
villacis@palosanto.comccf91bd2012-05-16 21:07:12 +02004840 rt2x00_rf(rt2x00dev, RF5360) ||
Gertjan van Wingerdeaca355b2011-05-04 21:41:36 +02004841 rt2x00_rf(rt2x00dev, RF5370) ||
John Li2ed71882012-02-17 17:33:06 +08004842 rt2x00_rf(rt2x00dev, RF5372) ||
Zero.Lincff3d1f2012-05-29 16:11:09 +08004843 rt2x00_rf(rt2x00dev, RF5390) ||
4844 rt2x00_rf(rt2x00dev, RF5392)) {
Ivo van Doorn55f93212010-05-06 14:45:46 +02004845 spec->num_channels = 14;
4846 spec->channels = rf_vals_3x;
4847 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4848 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4849 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4850 spec->channels = rf_vals_3x;
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004851 }
4852
4853 /*
4854 * Initialize HT information.
4855 */
Gertjan van Wingerde5122d892009-12-23 00:03:25 +01004856 if (!rt2x00_rf(rt2x00dev, RF2020))
Gertjan van Wingerde38a522e2009-11-23 22:44:47 +01004857 spec->ht.ht_supported = true;
4858 else
4859 spec->ht.ht_supported = false;
4860
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004861 spec->ht.cap =
Gertjan van Wingerde06443e42010-06-03 10:52:08 +02004862 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004863 IEEE80211_HT_CAP_GRN_FLD |
4864 IEEE80211_HT_CAP_SGI_20 |
Ivo van Doornaa674632010-06-29 21:48:37 +02004865 IEEE80211_HT_CAP_SGI_40;
Helmut Schaa22cabaa2010-06-03 10:52:10 +02004866
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004867 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
Helmut Schaa22cabaa2010-06-03 10:52:10 +02004868 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4869
Ivo van Doornaa674632010-06-29 21:48:37 +02004870 spec->ht.cap |=
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004871 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
Ivo van Doornaa674632010-06-29 21:48:37 +02004872 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4873
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004874 spec->ht.ampdu_factor = 3;
4875 spec->ht.ampdu_density = 4;
4876 spec->ht.mcs.tx_params =
4877 IEEE80211_HT_MCS_TX_DEFINED |
4878 IEEE80211_HT_MCS_TX_RX_DIFF |
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004879 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004880 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4881
RA-Jay Hung38c8a562010-12-13 12:31:27 +01004882 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004883 case 3:
4884 spec->ht.mcs.rx_mask[2] = 0xff;
4885 case 2:
4886 spec->ht.mcs.rx_mask[1] = 0xff;
4887 case 1:
4888 spec->ht.mcs.rx_mask[0] = 0xff;
4889 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4890 break;
4891 }
4892
4893 /*
4894 * Create channel information array
4895 */
Joe Perchesbaeb2ff2010-08-11 07:02:48 +00004896 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004897 if (!info)
4898 return -ENOMEM;
4899
4900 spec->channels_info = info;
4901
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02004902 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4903 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004904
4905 for (i = 0; i < 14; i++) {
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01004906 info[i].default_power1 = default_power1[i];
4907 info[i].default_power2 = default_power2[i];
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004908 }
4909
4910 if (spec->num_channels > 14) {
Ivo van Doorn8d1331b2010-08-23 19:56:07 +02004911 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4912 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004913
4914 for (i = 14; i < spec->num_channels; i++) {
RA-Jay Hunge90c54b2011-02-20 13:55:25 +01004915 info[i].default_power1 = default_power1[i];
4916 info[i].default_power2 = default_power2[i];
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004917 }
4918 }
4919
John Li2e9c43d2012-02-16 21:40:57 +08004920 switch (rt2x00dev->chip.rf) {
4921 case RF2020:
4922 case RF3020:
4923 case RF3021:
4924 case RF3022:
4925 case RF3320:
4926 case RF3052:
Woody Hunga89534e2012-06-13 15:01:16 +08004927 case RF3290:
villacis@palosanto.comccf91bd2012-05-16 21:07:12 +02004928 case RF5360:
John Li2e9c43d2012-02-16 21:40:57 +08004929 case RF5370:
4930 case RF5372:
4931 case RF5390:
Zero.Lincff3d1f2012-05-29 16:11:09 +08004932 case RF5392:
John Li2e9c43d2012-02-16 21:40:57 +08004933 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4934 break;
4935 }
4936
Bartlomiej Zolnierkiewicz4da29332009-11-08 14:39:32 +01004937 return 0;
4938}
4939EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4940
4941/*
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004942 * IEEE80211 stack callback functions.
4943 */
Helmut Schaae7836192010-07-11 12:28:54 +02004944void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4945 u16 *iv16)
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004946{
4947 struct rt2x00_dev *rt2x00dev = hw->priv;
4948 struct mac_iveiv_entry iveiv_entry;
4949 u32 offset;
4950
4951 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4952 rt2800_register_multiread(rt2x00dev, offset,
4953 &iveiv_entry, sizeof(iveiv_entry));
4954
Julia Lawall855da5e2009-12-13 17:07:45 +01004955 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4956 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004957}
Helmut Schaae7836192010-07-11 12:28:54 +02004958EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004959
Helmut Schaae7836192010-07-11 12:28:54 +02004960int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004961{
4962 struct rt2x00_dev *rt2x00dev = hw->priv;
4963 u32 reg;
4964 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4965
4966 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4967 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4968 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4969
4970 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4971 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4972 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4973
4974 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4975 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4976 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4977
4978 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4979 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4980 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4981
4982 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4983 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4984 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4985
4986 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4987 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4988 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4989
4990 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4991 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4992 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4993
4994 return 0;
4995}
Helmut Schaae7836192010-07-11 12:28:54 +02004996EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01004997
Eliad Peller8a3a3c82011-10-02 10:15:52 +02004998int rt2800_conf_tx(struct ieee80211_hw *hw,
4999 struct ieee80211_vif *vif, u16 queue_idx,
Helmut Schaae7836192010-07-11 12:28:54 +02005000 const struct ieee80211_tx_queue_params *params)
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01005001{
5002 struct rt2x00_dev *rt2x00dev = hw->priv;
5003 struct data_queue *queue;
5004 struct rt2x00_field32 field;
5005 int retval;
5006 u32 reg;
5007 u32 offset;
5008
5009 /*
5010 * First pass the configuration through rt2x00lib, that will
5011 * update the queue settings and validate the input. After that
5012 * we are free to update the registers based on the value
5013 * in the queue parameter.
5014 */
Eliad Peller8a3a3c82011-10-02 10:15:52 +02005015 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01005016 if (retval)
5017 return retval;
5018
5019 /*
5020 * We only need to perform additional register initialization
5021 * for WMM queues/
5022 */
5023 if (queue_idx >= 4)
5024 return 0;
5025
Helmut Schaa11f818e2011-03-03 19:38:55 +01005026 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01005027
5028 /* Update WMM TXOP register */
5029 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
5030 field.bit_offset = (queue_idx & 1) * 16;
5031 field.bit_mask = 0xffff << field.bit_offset;
5032
5033 rt2800_register_read(rt2x00dev, offset, &reg);
5034 rt2x00_set_field32(&reg, field, queue->txop);
5035 rt2800_register_write(rt2x00dev, offset, reg);
5036
5037 /* Update WMM registers */
5038 field.bit_offset = queue_idx * 4;
5039 field.bit_mask = 0xf << field.bit_offset;
5040
5041 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
5042 rt2x00_set_field32(&reg, field, queue->aifs);
5043 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
5044
5045 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
5046 rt2x00_set_field32(&reg, field, queue->cw_min);
5047 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
5048
5049 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
5050 rt2x00_set_field32(&reg, field, queue->cw_max);
5051 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
5052
5053 /* Update EDCA registers */
5054 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
5055
5056 rt2800_register_read(rt2x00dev, offset, &reg);
5057 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
5058 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
5059 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
5060 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
5061 rt2800_register_write(rt2x00dev, offset, reg);
5062
5063 return 0;
5064}
Helmut Schaae7836192010-07-11 12:28:54 +02005065EXPORT_SYMBOL_GPL(rt2800_conf_tx);
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01005066
Eliad Peller37a41b42011-09-21 14:06:11 +03005067u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01005068{
5069 struct rt2x00_dev *rt2x00dev = hw->priv;
5070 u64 tsf;
5071 u32 reg;
5072
5073 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
5074 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
5075 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
5076 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
5077
5078 return tsf;
5079}
Helmut Schaae7836192010-07-11 12:28:54 +02005080EXPORT_SYMBOL_GPL(rt2800_get_tsf);
Bartlomiej Zolnierkiewicz2ce33992009-11-04 18:37:05 +01005081
Helmut Schaae7836192010-07-11 12:28:54 +02005082int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5083 enum ieee80211_ampdu_mlme_action action,
Johannes Berg0b01f032011-01-18 13:51:05 +01005084 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5085 u8 buf_size)
Helmut Schaa1df90802010-06-29 21:38:12 +02005086{
Helmut Schaaaf353232011-09-08 14:38:36 +02005087 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
Helmut Schaa1df90802010-06-29 21:38:12 +02005088 int ret = 0;
5089
Helmut Schaaaf353232011-09-08 14:38:36 +02005090 /*
5091 * Don't allow aggregation for stations the hardware isn't aware
5092 * of because tx status reports for frames to an unknown station
5093 * always contain wcid=255 and thus we can't distinguish between
5094 * multiple stations which leads to unwanted situations when the
5095 * hw reorders frames due to aggregation.
5096 */
5097 if (sta_priv->wcid < 0)
5098 return 1;
5099
Helmut Schaa1df90802010-06-29 21:38:12 +02005100 switch (action) {
5101 case IEEE80211_AMPDU_RX_START:
5102 case IEEE80211_AMPDU_RX_STOP:
Helmut Schaa58ed8262010-10-02 11:33:17 +02005103 /*
5104 * The hw itself takes care of setting up BlockAck mechanisms.
5105 * So, we only have to allow mac80211 to nagotiate a BlockAck
5106 * agreement. Once that is done, the hw will BlockAck incoming
5107 * AMPDUs without further setup.
5108 */
Helmut Schaa1df90802010-06-29 21:38:12 +02005109 break;
5110 case IEEE80211_AMPDU_TX_START:
5111 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5112 break;
5113 case IEEE80211_AMPDU_TX_STOP:
5114 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5115 break;
5116 case IEEE80211_AMPDU_TX_OPERATIONAL:
5117 break;
5118 default:
Ivo van Doorn4e9e58c2010-06-29 21:49:50 +02005119 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
Helmut Schaa1df90802010-06-29 21:38:12 +02005120 }
5121
5122 return ret;
5123}
Helmut Schaae7836192010-07-11 12:28:54 +02005124EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
Ivo van Doorna5ea2f02010-06-14 22:13:15 +02005125
Helmut Schaa977206d2010-12-13 12:31:58 +01005126int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
5127 struct survey_info *survey)
5128{
5129 struct rt2x00_dev *rt2x00dev = hw->priv;
5130 struct ieee80211_conf *conf = &hw->conf;
5131 u32 idle, busy, busy_ext;
5132
5133 if (idx != 0)
5134 return -ENOENT;
5135
5136 survey->channel = conf->channel;
5137
5138 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
5139 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
5140 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
5141
5142 if (idle || busy) {
5143 survey->filled = SURVEY_INFO_CHANNEL_TIME |
5144 SURVEY_INFO_CHANNEL_TIME_BUSY |
5145 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
5146
5147 survey->channel_time = (idle + busy) / 1000;
5148 survey->channel_time_busy = busy / 1000;
5149 survey->channel_time_ext_busy = busy_ext / 1000;
5150 }
5151
Helmut Schaa9931df22011-12-22 09:36:29 +01005152 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
5153 survey->filled |= SURVEY_INFO_IN_USE;
5154
Helmut Schaa977206d2010-12-13 12:31:58 +01005155 return 0;
5156
5157}
5158EXPORT_SYMBOL_GPL(rt2800_get_survey);
5159
Ivo van Doorna5ea2f02010-06-14 22:13:15 +02005160MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
5161MODULE_VERSION(DRV_VERSION);
5162MODULE_DESCRIPTION("Ralink RT2800 library");
5163MODULE_LICENSE("GPL");