blob: 1d78b6b36aa72c11c8dc972c2d2c3ce76b8ca570 [file] [log] [blame]
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301/*
Sanjay Dwivedi4adc0582019-07-26 14:43:15 +05302 * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
Srinivas Ramana3cac2782017-09-13 16:31:17 +05303 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "skeleton64.dtsi"
15#include <dt-bindings/gpio/gpio.h>
Kiran Gunda0954f392017-10-16 16:24:55 +053016#include <dt-bindings/spmi/spmi.h>
Kiran Gundaaf6a0b62017-10-23 16:03:10 +053017#include <dt-bindings/interrupt-controller/arm-gic.h>
Kiran Gunda0954f392017-10-16 16:24:55 +053018#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
Shefali Jain44e24ad2017-11-23 12:27:33 +053019#include <dt-bindings/clock/msm-clocks-8953.h>
Patrick Dalyf891f372018-04-27 18:09:23 -070020#include <dt-bindings/msm/msm-bus-ids.h>
Srinivas Ramana3cac2782017-09-13 16:31:17 +053021
22/ {
Maria Yuf307a0f2017-11-24 16:34:30 +080023 model = "Qualcomm Technologies, Inc. MSM8953";
Srinivas Ramana3cac2782017-09-13 16:31:17 +053024 compatible = "qcom,msm8953";
25 qcom,msm-id = <293 0x0>;
Maria Yuf307a0f2017-11-24 16:34:30 +080026 qcom,msm-name = "MSM8953";
Raju P.L.S.S.S.N3f64cd32017-12-06 19:26:03 +053027 interrupt-parent = <&wakegic>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +053028
Maria Yu6f333b3b2018-03-06 16:10:03 +080029 chosen {
Lingutla Chandrasekhar5fb437c2018-02-27 18:04:53 +053030 bootargs = "core_ctl_disable_cpumask=0-7 kpti=0";
Maria Yu6f333b3b2018-03-06 16:10:03 +080031 };
32
Vamshi Krishna B V4279b562018-06-13 16:17:56 +053033 vendor: vendor {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges = <0 0 0 0xffffffff>;
37 compatible = "simple-bus";
38 };
39
Tingwei Zhang5ac96772018-01-04 09:54:03 +080040 firmware: firmware {
41 android {
42 compatible = "android,firmware";
Monika Singh5ce35af2018-02-24 17:25:08 +053043 vbmeta {
44 compatible = "android,vbmeta";
45 parts = "vbmeta,boot,system,vendor,dtbo,recovery";
46 };
47
Tingwei Zhang5ac96772018-01-04 09:54:03 +080048 fstab {
49 compatible = "android,fstab";
50 vendor {
51 compatible = "android,vendor";
52 dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor";
53 type = "ext4";
54 mnt_flags = "ro,barrier=1,discard";
Monika Singh5ce35af2018-02-24 17:25:08 +053055 fsmgr_flags = "wait,avb";
Tingwei Zhang5ac96772018-01-04 09:54:03 +080056 status = "ok";
57 };
Tingwei Zhang5ac96772018-01-04 09:54:03 +080058
59 };
60 };
61 };
62
Srinivas Ramana3cac2782017-09-13 16:31:17 +053063 reserved-memory {
64 #address-cells = <2>;
65 #size-cells = <2>;
66 ranges;
67
68 other_ext_mem: other_ext_region@0 {
69 compatible = "removed-dma-pool";
70 no-map;
71 reg = <0x0 0x85b00000 0x0 0xd00000>;
72 };
73
74 modem_mem: modem_region@0 {
75 compatible = "removed-dma-pool";
Zhenhua Huangcdaab092018-04-20 12:33:09 +080076 no-map;
Srinivas Ramana3cac2782017-09-13 16:31:17 +053077 reg = <0x0 0x86c00000 0x0 0x6a00000>;
78 };
79
80 adsp_fw_mem: adsp_fw_region@0 {
81 compatible = "removed-dma-pool";
82 no-map;
83 reg = <0x0 0x8d600000 0x0 0x1100000>;
84 };
85
86 wcnss_fw_mem: wcnss_fw_region@0 {
87 compatible = "removed-dma-pool";
88 no-map;
89 reg = <0x0 0x8e700000 0x0 0x700000>;
90 };
91
92 venus_mem: venus_region@0 {
93 compatible = "shared-dma-pool";
94 reusable;
95 alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
96 alignment = <0 0x400000>;
97 size = <0 0x0800000>;
98 };
99
100 secure_mem: secure_region@0 {
101 compatible = "shared-dma-pool";
102 reusable;
103 alignment = <0 0x400000>;
Zhenhua Huangf64e43f2018-06-21 13:31:25 +0800104 size = <0 0x0b400000>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530105 };
106
107 qseecom_mem: qseecom_region@0 {
108 compatible = "shared-dma-pool";
109 reusable;
110 alignment = <0 0x400000>;
mohamed sunfeer5fb3ea72018-03-07 19:58:17 +0530111 size = <0 0x1000000>;
mohamed sunfeereaba2742018-02-12 15:39:32 +0530112 };
113
114 qseecom_ta_mem: qseecom_ta_region {
115 compatible = "shared-dma-pool";
116 alloc-ranges = <0 0x00000000 0 0xffffffff>;
117 reusable;
118 alignment = <0 0x400000>;
mohamed sunfeer5fb3ea72018-03-07 19:58:17 +0530119 size = <0 0x400000>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530120 };
121
122 adsp_mem: adsp_region@0 {
123 compatible = "shared-dma-pool";
124 reusable;
125 size = <0 0x400000>;
126 };
127
128 dfps_data_mem: dfps_data_mem@90000000 {
Sachin Bhayaree25c1f02018-01-16 14:04:54 +0530129 reg = <0 0x90000000 0 0x1000>;
130 label = "dfps_data_mem";
131 status = "disabled";
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530132 };
133
134 cont_splash_mem: splash_region@0x90001000 {
135 reg = <0x0 0x90001000 0x0 0x13ff000>;
136 label = "cont_splash_mem";
137 };
138
Milen Mitkovdb26e512018-07-31 11:55:54 +0300139 adsp_shmem_device_mem: adsp_shmem_device_region@0xc0100000 {
Vijaya Kumar T M0ed78412019-11-12 15:33:17 +0530140 compatible = "shared-dma-pool";
Milen Mitkovdb26e512018-07-31 11:55:54 +0300141 label = "adsp_shmem_device_mem";
Vijaya Kumar T M0ed78412019-11-12 15:33:17 +0530142 reusable;
143 alloc-ranges = <0x0 0xc0100000 0x0 0x08200000>;
144 alignment = <0 0x400000>;
145 size = <0 0x800000>;
Milen Mitkovdb26e512018-07-31 11:55:54 +0300146 };
147
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530148 gpu_mem: gpu_region@0 {
149 compatible = "shared-dma-pool";
150 reusable;
151 alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
152 alignment = <0 0x400000>;
153 size = <0 0x800000>;
154 };
Mao Jinlong8ae9c212018-02-28 17:39:25 +0800155
156 dump_mem: mem_dump_region {
157 compatible = "shared-dma-pool";
158 reusable;
Mao Jinlong18c5b4e2018-06-05 21:11:12 +0800159 size = <0x400000>;
Mao Jinlong8ae9c212018-02-28 17:39:25 +0800160 };
Zhenhua Huanga50f9dd2018-12-12 10:35:25 +0800161
162 /* global autoconfigured region for contiguous allocations */
163 linux,cma {
164 compatible = "shared-dma-pool";
165 reusable;
166 alignment = <0 0x400000>;
167 size = <0 0x1400000>;
168 linux,cma-default;
169 };
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530170 };
171
172 aliases {
173 /* smdtty devices */
Arun Kumar Neelakantam36151aa2017-11-02 21:34:33 +0530174 smd1 = &smdtty_apps_fm;
175 smd2 = &smdtty_apps_riva_bt_acl;
176 smd3 = &smdtty_apps_riva_bt_cmd;
177 smd4 = &smdtty_mbalbridge;
178 smd5 = &smdtty_apps_riva_ant_cmd;
179 smd6 = &smdtty_apps_riva_ant_data;
180 smd7 = &smdtty_data1;
181 smd8 = &smdtty_data4;
182 smd11 = &smdtty_data11;
183 smd21 = &smdtty_data21;
184 smd36 = &smdtty_loopback;
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530185 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
186 sdhc2 = &sdhc_2; /* SDC2 for SD card */
Md Mansoor Ahmed19ca4852018-04-23 11:50:38 +0530187 i2c1 = &i2c_1;
Shrey Vijay88eddb52017-11-30 14:47:52 +0530188 i2c2 = &i2c_2;
189 i2c3 = &i2c_3;
190 i2c5 = &i2c_5;
191 spi3 = &spi_3;
Venkataraman Nerellapallia9ce2332018-07-03 14:17:42 +0530192 spi6 = &spi_6;
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530193 };
194
Patrick Dalyf891f372018-04-27 18:09:23 -0700195 soc: soc {
196 /*
197 * The ordering of these devices is important to boot time
198 * for iot projects.
199 */
200 smem: qcom,smem@86300000 {};
201 rpm_bus: qcom,rpm-smd {};
202 clock_gcc: qcom,gcc@1800000 {};
203 ad_hoc_bus: ad-hoc-bus@580000 {};
204 tlmm: pinctrl@1000000 {};
205 sdhc_1: sdhci@7824900 {};
206 };
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530207
208};
209
210#include "msm8953-pinctrl.dtsi"
211#include "msm8953-cpu.dtsi"
Raju P.L.S.S.S.Ne0b22c92017-11-02 13:42:27 +0530212#include "msm8953-pm.dtsi"
Odelu Kukatla1a811042017-10-29 17:26:44 +0530213#include "msm8953-bus.dtsi"
Mukesh Ojhae07d80e2017-11-28 20:22:44 +0530214#include "msm8953-coresight.dtsi"
Charan Teja Reddy6f1f8292017-12-26 20:54:26 +0530215#include "msm8953-ion.dtsi"
Charan Teja Reddyf20a02f2017-10-20 11:12:39 +0530216#include "msm-arm-smmu-8953.dtsi"
Deepak Kushwaha56fa312018-01-24 12:25:40 +0530217#include "msm8953-vidc.dtsi"
Sunil Khatrifc03ac62018-01-03 12:31:08 +0530218#include "msm8953-gpu.dtsi"
Sachin Bhayaree25c1f02018-01-16 14:04:54 +0530219#include "msm8953-mdss.dtsi"
220#include "msm8953-mdss-pll.dtsi"
Arun Kumar Neelakantam6eb58582018-02-12 13:46:53 +0530221#include "msm8953-smp2p.dtsi"
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530222
223&soc {
224 #address-cells = <1>;
225 #size-cells = <1>;
226 ranges = <0 0 0 0xffffffff>;
227 compatible = "simple-bus";
228
Mukesh Ojhae07d80e2017-11-28 20:22:44 +0530229 dcc: dcc@b3000 {
230 compatible = "qcom,dcc";
231 reg = <0xb3000 0x1000>,
232 <0xb4000 0x800>;
233 reg-names = "dcc-base", "dcc-ram-base";
234
235 clocks = <&clock_gcc clk_gcc_dcc_clk>;
236 clock-names = "apb_pclk";
237 qcom,save-reg;
238 };
239
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530240 apc_apm: apm@b111000 {
241 compatible = "qcom,msm8953-apm";
242 reg = <0xb111000 0x1000>;
243 reg-names = "pm-apcc-glb";
244 qcom,apm-post-halt-delay = <0x2>;
245 qcom,apm-halt-clk-delay = <0x11>;
246 qcom,apm-resume-clk-delay = <0x10>;
247 qcom,apm-sel-switch-delay = <0x01>;
248 };
249
250 intc: interrupt-controller@b000000 {
251 compatible = "qcom,msm-qgic2";
252 interrupt-controller;
Raju P.L.S.S.S.N3f64cd32017-12-06 19:26:03 +0530253 interrupt-parent = <&intc>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530254 #interrupt-cells = <3>;
255 reg = <0x0b000000 0x1000>,
256 <0x0b002000 0x1000>;
257 };
258
Raghavendra Kakarla21b96312018-02-23 08:45:00 +0530259 wakegic: wake-gic@601d4 {
260 compatible = "qcom,mpm-gic-msm8953", "qcom,mpm-gic";
Raju P.L.S.S.S.N3f64cd32017-12-06 19:26:03 +0530261 interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
262 reg = <0x601d4 0x1000>,
263 <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
264 reg-names = "vmpm", "ipc";
265 qcom,num-mpm-irqs = <96>;
Raghavendra Kakarla21b96312018-02-23 08:45:00 +0530266 interrupt-controller;
267 interrupt-parent = <&intc>;
268 #interrupt-cells = <3>;
269 };
Raju P.L.S.S.S.N3f64cd32017-12-06 19:26:03 +0530270
Raghavendra Kakarla21b96312018-02-23 08:45:00 +0530271 wakegpio: wake-gpio {
272 compatible = "qcom,mpm-gpio-msm8953", "qcom,mpm-gpio";
273 interrupt-controller;
Raghavendra Kakarla168d4822018-03-07 17:30:53 +0530274 interrupt-parent = <&intc>;
Raghavendra Kakarla21b96312018-02-23 08:45:00 +0530275 #interrupt-cells = <2>;
Raju P.L.S.S.S.N3f64cd32017-12-06 19:26:03 +0530276 };
277
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530278 qcom,msm-gladiator@b1c0000 {
279 compatible = "qcom,msm-gladiator";
280 reg = <0x0b1c0000 0x4000>;
281 reg-names = "gladiator_base";
282 interrupts = <0 22 0>;
283 };
284
285 timer {
286 compatible = "arm,armv8-timer";
287 interrupts = <1 2 0xff08>,
288 <1 3 0xff08>,
289 <1 4 0xff08>,
290 <1 1 0xff08>;
291 clock-frequency = <19200000>;
292 };
293
294 timer@b120000 {
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges;
298 compatible = "arm,armv7-timer-mem";
299 reg = <0xb120000 0x1000>;
300 clock-frequency = <19200000>;
301
302 frame@b121000 {
303 frame-number = <0>;
304 interrupts = <0 8 0x4>,
305 <0 7 0x4>;
306 reg = <0xb121000 0x1000>,
307 <0xb122000 0x1000>;
308 };
309
310 frame@b123000 {
311 frame-number = <1>;
312 interrupts = <0 9 0x4>;
313 reg = <0xb123000 0x1000>;
314 status = "disabled";
315 };
316
317 frame@b124000 {
318 frame-number = <2>;
319 interrupts = <0 10 0x4>;
320 reg = <0xb124000 0x1000>;
321 status = "disabled";
322 };
323
324 frame@b125000 {
325 frame-number = <3>;
326 interrupts = <0 11 0x4>;
327 reg = <0xb125000 0x1000>;
328 status = "disabled";
329 };
330
331 frame@b126000 {
332 frame-number = <4>;
333 interrupts = <0 12 0x4>;
334 reg = <0xb126000 0x1000>;
335 status = "disabled";
336 };
337
338 frame@b127000 {
339 frame-number = <5>;
340 interrupts = <0 13 0x4>;
341 reg = <0xb127000 0x1000>;
342 status = "disabled";
343 };
344
345 frame@b128000 {
346 frame-number = <6>;
347 interrupts = <0 14 0x4>;
348 reg = <0xb128000 0x1000>;
349 status = "disabled";
350 };
351 };
352 qcom,rmtfs_sharedmem@00000000 {
353 compatible = "qcom,sharedmem-uio";
354 reg = <0x00000000 0x00180000>;
355 reg-names = "rmtfs";
356 qcom,client-id = <0x00000001>;
357 };
358
359 restart@4ab000 {
360 compatible = "qcom,pshold";
361 reg = <0x4ab000 0x4>,
362 <0x193d100 0x4>;
363 reg-names = "pshold-base", "tcsr-boot-misc-detect";
364 };
365
366 qcom,mpm2-sleep-counter@4a3000 {
367 compatible = "qcom,mpm2-sleep-counter";
368 reg = <0x4a3000 0x1000>;
369 clock-frequency = <32768>;
370 };
371
372 cpu-pmu {
373 compatible = "arm,armv8-pmuv3";
374 interrupts = <1 7 0xff00>;
375 };
376
377 qcom,sps {
378 compatible = "qcom,msm_sps_4k";
379 qcom,pipe-attr-ee;
380 };
381
Manaf Meethalavalappu Pallikunhi4eb2b272018-01-02 17:29:37 +0530382 thermal_zones: thermal-zones {};
Ashok Jammigumpuladb43f572017-12-06 18:05:57 +0530383
Mao Jinlong8ae9c212018-02-28 17:39:25 +0800384 mem_dump {
385 compatible = "qcom,mem-dump";
386 memory-region = <&dump_mem>;
387
Mao Jinlong8ae9c212018-02-28 17:39:25 +0800388 rpm_sw_dump {
389 qcom,dump-size = <0x28000>;
390 qcom,dump-id = <0xea>;
391 };
392
393 pmic_dump {
394 qcom,dump-size = <0x10000>;
395 qcom,dump-id = <0xe4>;
396 };
397
Jinlong Maoc2268652018-03-15 11:14:58 +0530398 vsense_dump {
399 qcom,dump-size = <0x10000>;
400 qcom,dump-id = <0xe9>;
401 };
402
Mao Jinlong8ae9c212018-02-28 17:39:25 +0800403 tmc_etf_dump {
404 qcom,dump-size = <0x10000>;
405 qcom,dump-id = <0xf0>;
406 };
407
408 tmc_etr_reg_dump {
409 qcom,dump-size = <0x1000>;
410 qcom,dump-id = <0x100>;
411 };
412
413 tmc_etf_reg_dump {
414 qcom,dump-size = <0x1000>;
415 qcom,dump-id = <0x101>;
416 };
417
418 misc_data_dump {
419 qcom,dump-size = <0x1000>;
420 qcom,dump-id = <0xe8>;
421 };
422
423 };
424
Ashok Jammigumpuladb43f572017-12-06 18:05:57 +0530425 tsens0: tsens@4a8000 {
426 compatible = "qcom,msm8953-tsens";
427 reg = <0x4a8000 0x1000>,
428 <0x4a9000 0x1000>;
429 reg-names = "tsens_srot_physical",
430 "tsens_tm_physical";
431 interrupts = <0 184 0>, <0 314 0>;
432 interrupt-names = "tsens-upper-lower", "tsens-critical";
433 #thermal-sensor-cells = <1>;
434 };
435
mohamed sunfeer2bfd8c82017-11-30 13:08:36 +0530436 qcom_seecom: qseecom@85b00000 {
437 compatible = "qcom,qseecom";
438 reg = <0x85b00000 0x800000>;
439 reg-names = "secapp-region";
440 qcom,hlos-num-ce-hw-instances = <1>;
441 qcom,hlos-ce-hw-instance = <0>;
442 qcom,qsee-ce-hw-instance = <0>;
443 qcom,disk-encrypt-pipe-pair = <2>;
444 qcom,support-fde;
Ramandeep Trehancd2dc372018-08-27 19:22:08 +0530445 qcom,commonlib64-loaded-by-uefi;
mohamed sunfeer2bfd8c82017-11-30 13:08:36 +0530446 qcom,msm-bus,name = "qseecom-noc";
447 qcom,msm-bus,num-cases = <4>;
448 qcom,msm-bus,num-paths = <1>;
449 qcom,support-bus-scaling;
450 qcom,msm-bus,vectors-KBps =
451 <55 512 0 0>,
452 <55 512 0 0>,
453 <55 512 120000 1200000>,
454 <55 512 393600 3936000>;
455 clocks = <&clock_gcc clk_crypto_clk_src>,
456 <&clock_gcc clk_gcc_crypto_clk>,
457 <&clock_gcc clk_gcc_crypto_ahb_clk>,
458 <&clock_gcc clk_gcc_crypto_axi_clk>;
459 clock-names = "core_clk_src", "core_clk",
460 "iface_clk", "bus_clk";
461 qcom,ce-opp-freq = <100000000>;
Brahmaji K22191832017-12-27 13:42:35 +0530462 status = "okay";
mohamed sunfeer2bfd8c82017-11-30 13:08:36 +0530463 };
464
mohamed sunfeerd9761e62017-11-30 13:33:02 +0530465 qcom_tzlog: tz-log@08600720 {
466 compatible = "qcom,tz-log";
467 reg = <0x08600720 0x2000>;
Brahmaji K22191832017-12-27 13:42:35 +0530468 status = "okay";
mohamed sunfeerd9761e62017-11-30 13:33:02 +0530469 };
470
mohamed sunfeer0d623222017-11-30 13:51:20 +0530471 qcom_rng: qrng@e3000 {
472 compatible = "qcom,msm-rng";
473 reg = <0xe3000 0x1000>;
474 qcom,msm-rng-iface-clk;
475 qcom,no-qrng-config;
476 qcom,msm-bus,name = "msm-rng-noc";
477 qcom,msm-bus,num-cases = <2>;
478 qcom,msm-bus,num-paths = <1>;
479 qcom,msm-bus,vectors-KBps =
480 <1 618 0 0>, /* No vote */
481 <1 618 0 800>; /* 100 MB/s */
482 clocks = <&clock_gcc clk_gcc_prng_ahb_clk>;
483 clock-names = "iface_clk";
Brahmaji K22191832017-12-27 13:42:35 +0530484 status = "okay";
mohamed sunfeer0d623222017-11-30 13:51:20 +0530485 };
486
mohamed sunfeer1f6a4e02017-11-30 14:07:28 +0530487 qcom_crypto: qcrypto@720000 {
488 compatible = "qcom,qcrypto";
489 reg = <0x720000 0x20000>,
490 <0x704000 0x20000>;
491 reg-names = "crypto-base","crypto-bam-base";
492 interrupts = <0 207 0>;
493 qcom,bam-pipe-pair = <2>;
494 qcom,ce-hw-instance = <0>;
495 qcom,ce-device = <0>;
496 qcom,ce-hw-shared;
497 qcom,clk-mgmt-sus-res;
498 qcom,msm-bus,name = "qcrypto-noc";
499 qcom,msm-bus,num-cases = <2>;
500 qcom,msm-bus,num-paths = <1>;
501 qcom,msm-bus,vectors-KBps =
502 <55 512 0 0>,
503 <55 512 393600 393600>;
504 clocks = <&clock_gcc clk_crypto_clk_src>,
505 <&clock_gcc clk_gcc_crypto_clk>,
506 <&clock_gcc clk_gcc_crypto_ahb_clk>,
507 <&clock_gcc clk_gcc_crypto_axi_clk>;
508 clock-names = "core_clk_src", "core_clk",
509 "iface_clk", "bus_clk";
510 qcom,use-sw-aes-cbc-ecb-ctr-algo;
511 qcom,use-sw-aes-xts-algo;
512 qcom,use-sw-aes-ccm-algo;
513 qcom,use-sw-ahash-algo;
514 qcom,use-sw-hmac-algo;
515 qcom,use-sw-aead-algo;
516 qcom,ce-opp-freq = <100000000>;
Brahmaji K22191832017-12-27 13:42:35 +0530517 status = "okay";
mohamed sunfeer1f6a4e02017-11-30 14:07:28 +0530518 };
519
520 qcom_cedev: qcedev@720000 {
521 compatible = "qcom,qcedev";
522 reg = <0x720000 0x20000>,
523 <0x704000 0x20000>;
524 reg-names = "crypto-base","crypto-bam-base";
525 interrupts = <0 207 0>;
526 qcom,bam-pipe-pair = <1>;
527 qcom,ce-hw-instance = <0>;
528 qcom,ce-device = <0>;
529 qcom,ce-hw-shared;
530 qcom,msm-bus,name = "qcedev-noc";
531 qcom,msm-bus,num-cases = <2>;
532 qcom,msm-bus,num-paths = <1>;
533 qcom,msm-bus,vectors-KBps =
534 <55 512 0 0>,
535 <55 512 393600 393600>;
536 clocks = <&clock_gcc clk_crypto_clk_src>,
537 <&clock_gcc clk_gcc_crypto_clk>,
538 <&clock_gcc clk_gcc_crypto_ahb_clk>,
539 <&clock_gcc clk_gcc_crypto_axi_clk>;
540 clock-names = "core_clk_src", "core_clk",
541 "iface_clk", "bus_clk";
542 qcom,ce-opp-freq = <100000000>;
Brahmaji K22191832017-12-27 13:42:35 +0530543 status = "okay";
mohamed sunfeer1f6a4e02017-11-30 14:07:28 +0530544 };
545
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530546 blsp1_uart0: serial@78af000 {
547 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
548 reg = <0x78af000 0x200>;
549 interrupts = <0 107 0>;
Maria Yuaf0e9252017-11-30 19:58:44 +0800550 clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
551 <&clock_gcc clk_gcc_blsp1_ahb_clk>;
552 clock-names = "core", "iface";
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530553 status = "disabled";
554 };
555
Shrey Vijay88eddb52017-11-30 14:47:52 +0530556 blsp1_uart1: uart@78b0000 {
557 compatible = "qcom,msm-hsuart-v14";
558 reg = <0x78b0000 0x200>,
559 <0x7884000 0x1f000>;
560 reg-names = "core_mem", "bam_mem";
561
562 interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
563 #address-cells = <0>;
564 interrupt-parent = <&blsp1_uart1>;
565 interrupts = <0 1 2>;
566 #interrupt-cells = <1>;
567 interrupt-map-mask = <0xffffffff>;
568 interrupt-map = <0 &intc 0 108 0
569 1 &intc 0 238 0
570 2 &tlmm 13 0>;
571
572 qcom,inject-rx-on-wakeup;
573 qcom,rx-char-to-inject = <0xFD>;
574 qcom,master-id = <86>;
575 clock-names = "core_clk", "iface_clk";
576 clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
577 <&clock_gcc clk_gcc_blsp1_ahb_clk>;
578 pinctrl-names = "sleep", "default";
579 pinctrl-0 = <&hsuart_sleep>;
580 pinctrl-1 = <&hsuart_active>;
581 qcom,bam-tx-ep-pipe-index = <2>;
582 qcom,bam-rx-ep-pipe-index = <3>;
583 qcom,msm-bus,name = "blsp1_uart1";
584 qcom,msm-bus,num-cases = <2>;
585 qcom,msm-bus,num-paths = <1>;
586 qcom,msm-bus,vectors-KBps =
587 <86 512 0 0>,
588 <86 512 500 800>;
589 status = "disabled";
590 };
591
592 blsp2_uart0: uart@7aef000 {
593 compatible = "qcom,msm-hsuart-v14";
594 reg = <0x7aef000 0x200>,
595 <0x7ac4000 0x1f000>;
596 reg-names = "core_mem", "bam_mem";
597
598 interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
599 #address-cells = <0>;
600 interrupt-parent = <&blsp2_uart0>;
601 interrupts = <0 1 2>;
602 #interrupt-cells = <1>;
603 interrupt-map-mask = <0xffffffff>;
604 interrupt-map = <0 &intc 0 306 0
605 1 &intc 0 239 0
606 2 &tlmm 17 0>;
607
608 qcom,inject-rx-on-wakeup;
609 qcom,rx-char-to-inject = <0xFD>;
610 qcom,master-id = <84>;
611 clock-names = "core_clk", "iface_clk";
612 clocks = <&clock_gcc clk_gcc_blsp2_uart1_apps_clk>,
613 <&clock_gcc clk_gcc_blsp2_ahb_clk>;
614 pinctrl-names = "sleep", "default";
615 pinctrl-0 = <&blsp2_uart0_sleep>;
616 pinctrl-1 = <&blsp2_uart0_active>;
617 qcom,bam-tx-ep-pipe-index = <0>;
618 qcom,bam-rx-ep-pipe-index = <1>;
619 qcom,msm-bus,name = "blsp2_uart0";
620 qcom,msm-bus,num-cases = <2>;
621 qcom,msm-bus,num-paths = <1>;
622 qcom,msm-bus,vectors-KBps =
623 <84 512 0 0>,
624 <84 512 500 800>;
625 status = "disabled";
626 };
627
Venkataraman Nerellapalli5d54a0b2018-07-02 12:48:48 +0530628 blsp2_uart1: uart@7af0000 {
629 compatible = "qcom,msm-hsuart-v14";
630 reg = <0x7af0000 0x200>,
631 <0x7ac4000 0x1f000>;
632 reg-names = "core_mem", "bam_mem";
633
634 interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
635 #address-cells = <0>;
636 interrupt-parent = <&blsp2_uart1>;
637 interrupts = <0 1 2>;
638 #interrupt-cells = <1>;
639 interrupt-map-mask = <0xffffffff>;
640 interrupt-map = <0 &intc 0 307 0
641 1 &intc 0 239 0
642 2 &tlmm 21 0>;
643
644 qcom,inject-rx-on-wakeup;
645 qcom,rx-char-to-inject = <0xFD>;
646 qcom,master-id = <84>;
647 clock-names = "core_clk", "iface_clk";
648 clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
649 <&clock_gcc clk_gcc_blsp2_ahb_clk>;
650 pinctrl-names = "sleep", "default";
651 pinctrl-0 = <&blsp2_uart1_sleep>;
652 pinctrl-1 = <&blsp2_uart1_active>;
653 qcom,bam-tx-ep-pipe-index = <2>;
654 qcom,bam-rx-ep-pipe-index = <3>;
655 qcom,msm-bus,name = "blsp2_uart1";
656 qcom,msm-bus,num-cases = <2>;
657 qcom,msm-bus,num-paths = <1>;
658 qcom,msm-bus,vectors-KBps =
659 <84 512 0 0>,
660 <84 512 500 800>;
661 status = "disabled";
662 };
663
Maria Yuf16c1602017-12-22 13:05:17 +0800664 blsp1_serial1: serial@78b0000 {
665 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
666 reg = <0x78b0000 0x200>;
667 interrupts = <0 108 0>;
668 clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
669 <&clock_gcc clk_gcc_blsp1_ahb_clk>;
670 clock-names = "core", "iface";
671 status = "disabled";
672 };
673
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530674 dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
675 #dma-cells = <4>;
676 compatible = "qcom,sps-dma";
677 reg = <0x7884000 0x1f000>;
678 interrupts = <0 238 0>;
679 qcom,summing-threshold = <10>;
680 };
681
682 dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */
683 #dma-cells = <4>;
684 compatible = "qcom,sps-dma";
685 reg = <0x7ac4000 0x1f000>;
686 interrupts = <0 239 0>;
687 qcom,summing-threshold = <10>;
688 };
689
Shrey Vijay88eddb52017-11-30 14:47:52 +0530690 spi_3: spi@78b7000 { /* BLSP1 QUP3 */
691 compatible = "qcom,spi-qup-v2";
692 #address-cells = <1>;
693 #size-cells = <0>;
694 reg-names = "spi_physical", "spi_bam_physical";
695 reg = <0x78b7000 0x600>,
696 <0x7884000 0x1f000>;
697 interrupt-names = "spi_irq", "spi_bam_irq";
698 interrupts = <0 97 0>, <0 238 0>;
699 spi-max-frequency = <19200000>;
700 pinctrl-names = "spi_default", "spi_sleep";
701 pinctrl-0 = <&spi3_default &spi3_cs0_active>;
702 pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>;
703 clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
704 <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>;
705 clock-names = "iface_clk", "core_clk";
706 qcom,infinite-mode = <0>;
707 qcom,use-bam;
708 qcom,use-pinctrl;
709 qcom,ver-reg-exists;
710 qcom,bam-consumer-pipe-index = <8>;
711 qcom,bam-producer-pipe-index = <9>;
712 qcom,master-id = <86>;
713 status = "disabled";
714 };
Venkataraman Nerellapallia9ce2332018-07-03 14:17:42 +0530715
716 spi_6: spi@7af6000 { /* BLSP2 QUP2 */
717 compatible = "qcom,spi-qup-v2";
718 #address-cells = <1>;
719 #size-cells = <0>;
720 reg-names = "spi_physical", "spi_bam_physical";
721 reg = <0x7af6000 0x600>,
722 <0x7ac4000 0x1f000>;
723 interrupt-names = "spi_irq", "spi_bam_irq";
724 interrupts = <0 300 0>, <0 239 0>;
725 spi-max-frequency = <19200000>;
726 pinctrl-names = "spi_default", "spi_sleep";
727 pinctrl-0 = <&spi6_default &spi6_cs0_active>;
728 pinctrl-1 = <&spi6_sleep &spi6_cs0_sleep>;
729 clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
730 <&clock_gcc clk_gcc_blsp2_qup2_spi_apps_clk>;
731 clock-names = "iface_clk", "core_clk";
732 qcom,infinite-mode = <0>;
733 qcom,use-bam;
734 qcom,use-pinctrl;
735 qcom,ver-reg-exists;
736 qcom,bam-consumer-pipe-index = <6>;
737 qcom,bam-producer-pipe-index = <7>;
738 qcom,master-id = <84>;
739 status = "disabled";
740 };
741
Md Mansoor Ahmed19ca4852018-04-23 11:50:38 +0530742 i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */
743 compatible = "qcom,i2c-msm-v2";
744 #address-cells = <1>;
745 #size-cells = <0>;
746 reg-names = "qup_phys_addr";
747 reg = <0x78b5000 0x600>;
748 interrupt-names = "qup_irq";
749 interrupts = <0 95 0>;
750 qcom,master-id = <86>;
751 qcom,clk-freq-out = <100000>;
752 qcom,clk-freq-in = <19200000>;
753 clock-names = "iface_clk", "core_clk";
754 clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
755 <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
756 pinctrl-names = "i2c_active", "i2c_sleep";
757 pinctrl-0 = <&i2c_1_active>;
758 pinctrl-1 = <&i2c_1_sleep>;
759 qcom,noise-rjct-scl = <0>;
760 qcom,noise-rjct-sda = <0>;
761 dmas = <&dma_blsp1 4 64 0x20000020 0x20>,
762 <&dma_blsp1 5 32 0x20000020 0x20>;
763 dma-names = "tx", "rx";
764 status = "disabled";
765 };
Shrey Vijay88eddb52017-11-30 14:47:52 +0530766
767 i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
768 compatible = "qcom,i2c-msm-v2";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 reg-names = "qup_phys_addr";
772 reg = <0x78b6000 0x600>;
773 interrupt-names = "qup_irq";
774 interrupts = <0 96 0>;
775 qcom,clk-freq-out = <400000>;
776 qcom,clk-freq-in = <19200000>;
777 clock-names = "iface_clk", "core_clk";
778 clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
779 <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
780
781 pinctrl-names = "i2c_active", "i2c_sleep";
782 pinctrl-0 = <&i2c_2_active>;
783 pinctrl-1 = <&i2c_2_sleep>;
784 qcom,noise-rjct-scl = <0>;
785 qcom,noise-rjct-sda = <0>;
786 qcom,master-id = <86>;
787 dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
788 <&dma_blsp1 7 32 0x20000020 0x20>;
789 dma-names = "tx", "rx";
790 status = "disabled";
791 };
792
793 i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */
794 compatible = "qcom,i2c-msm-v2";
795 #address-cells = <1>;
796 #size-cells = <0>;
797 reg-names = "qup_phys_addr";
798 reg = <0x78b7000 0x600>;
799 interrupt-names = "qup_irq";
800 interrupts = <0 97 0>;
801 qcom,clk-freq-out = <400000>;
802 qcom,clk-freq-in = <19200000>;
803 clock-names = "iface_clk", "core_clk";
804 clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
805 <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
806
807 pinctrl-names = "i2c_active", "i2c_sleep";
808 pinctrl-0 = <&i2c_3_active>;
809 pinctrl-1 = <&i2c_3_sleep>;
810 qcom,noise-rjct-scl = <0>;
811 qcom,noise-rjct-sda = <0>;
812 qcom,master-id = <86>;
813 dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
814 <&dma_blsp1 9 32 0x20000020 0x20>;
815 dma-names = "tx", "rx";
816 status = "disabled";
817 };
818
819 i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */
820 compatible = "qcom,i2c-msm-v2";
821 #address-cells = <1>;
822 #size-cells = <0>;
823 reg-names = "qup_phys_addr";
824 reg = <0x7af5000 0x600>;
825 interrupt-names = "qup_irq";
826 interrupts = <0 299 0>;
827 qcom,clk-freq-out = <400000>;
828 qcom,clk-freq-in = <19200000>;
829 clock-names = "iface_clk", "core_clk";
830 clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
831 <&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>;
832
833 pinctrl-names = "i2c_active", "i2c_sleep";
834 pinctrl-0 = <&i2c_5_active>;
835 pinctrl-1 = <&i2c_5_sleep>;
836 qcom,noise-rjct-scl = <0>;
837 qcom,noise-rjct-sda = <0>;
838 qcom,master-id = <84>;
839 dmas = <&dma_blsp2 4 64 0x20000020 0x20>,
840 <&dma_blsp2 5 32 0x20000020 0x20>;
841 dma-names = "tx", "rx";
842 status = "disabled";
843 };
844
Srinivas Ramana3cac2782017-09-13 16:31:17 +0530845 slim_msm: slim@c140000{
846 cell-index = <1>;
847 compatible = "qcom,slim-ngd";
848 reg = <0xc140000 0x2c000>,
849 <0xc104000 0x2a000>;
850 reg-names = "slimbus_physical", "slimbus_bam_physical";
851 interrupts = <0 163 0>, <0 180 0>;
852 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
853 qcom,apps-ch-pipes = <0x600000>;
854 qcom,ea-pc = <0x200>;
855 status = "disabled";
856 };
857
Sachin Bhayaree25c1f02018-01-16 14:04:54 +0530858 clock_gcc_mdss: qcom,gcc-mdss@1800000 {
859 compatible = "qcom,gcc-mdss-8953";
860 reg = <0x1800000 0x80000>;
861 reg-names = "cc_base";
862 clock-names = "pclk0_src", "pclk1_src",
863 "byte0_src", "byte1_src";
864 clocks = <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>,
865 <&mdss_dsi1_pll clk_dsi1pll_pixel_clk_mux>,
866 <&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>,
867 <&mdss_dsi1_pll clk_dsi1pll_byte_clk_mux>;
868 #clock-cells = <1>;
869 };
870
Shefali Jain44e24ad2017-11-23 12:27:33 +0530871 clock_gcc: qcom,gcc@1800000 {
872 compatible = "qcom,gcc-8953";
873 reg = <0x1800000 0x80000>,
874 <0x00a4124 0x08>;
875 reg-names = "cc_base", "efuse";
876 vdd_dig-supply = <&pm8953_s2_level>;
877 #clock-cells = <1>;
878 #reset-cells = <1>;
879 };
880
881 clock_debug: qcom,cc-debug@1874000 {
882 compatible = "qcom,cc-debug-8953";
883 reg = <0x1874000 0x4>;
884 reg-names = "cc_base";
885 clocks = <&clock_cpu clk_cpu_debug_pri_mux>;
886 clock-names = "debug_cpu_clk";
887 #clock-cells = <1>;
888 };
889
890 clock_gcc_gfx: qcom,gcc-gfx@1800000 {
891 compatible = "qcom,gcc-gfx-8953";
892 reg = <0x1800000 0x80000>;
893 reg-names = "cc_base";
894 vdd_gfx-supply = <&gfx_vreg_corner>;
Amit Nischal6b27af62018-01-17 18:01:18 +0530895 clocks = <&clock_gcc clk_xo_clk_src>;
896 clock-names = "xo";
Amit Nischal5778fc22018-01-18 10:55:04 +0530897 qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>;
Shefali Jain44e24ad2017-11-23 12:27:33 +0530898 qcom,gfxfreq-corner =
899 < 0 0 >,
900 < 133330000 1 >, /* Min SVS */
901 < 216000000 2 >, /* Low SVS */
902 < 320000000 3 >, /* SVS */
903 < 400000000 4 >, /* SVS Plus */
904 < 510000000 5 >, /* NOM */
905 < 560000000 6 >, /* Nom Plus */
906 < 650000000 7 >; /* Turbo */
907 #clock-cells = <1>;
908 };
909
910 clock_cpu: qcom,cpu-clock-8953@b116000 {
911 compatible = "qcom,cpu-clock-8953";
912 reg = <0xb114000 0x68>,
913 <0xb014000 0x68>,
914 <0xb116000 0x400>,
915 <0xb111050 0x08>,
916 <0xb011050 0x08>,
917 <0xb1d1050 0x08>,
918 <0x00a4124 0x08>;
919 reg-names = "rcgwr-c0-base", "rcgwr-c1-base",
920 "c0-pll", "c0-mux", "c1-mux",
921 "cci-mux", "efuse";
922 vdd-mx-supply = <&pm8953_s7_level_ao>;
923 vdd-cl-supply = <&apc_vreg>;
924 clocks = <&clock_gcc clk_xo_a_clk_src>;
925 clock-names = "xo_a";
926 qcom,num-clusters = <2>;
927 qcom,speed0-bin-v0-cl =
928 < 0 0>,
929 < 652800000 1>,
930 < 1036800000 2>,
931 < 1401600000 3>,
932 < 1689600000 4>,
933 < 1804800000 5>,
934 < 1958400000 6>,
935 < 2016000000 7>;
936 qcom,speed0-bin-v0-cci =
937 < 0 0>,
938 < 261120000 1>,
939 < 414720000 2>,
940 < 560640000 3>,
941 < 675840000 4>,
942 < 721920000 5>,
943 < 783360000 6>,
944 < 806400000 7>;
945 qcom,speed2-bin-v0-cl =
946 < 0 0>,
947 < 652800000 1>,
948 < 1036800000 2>,
949 < 1401600000 3>,
950 < 1689600000 4>,
951 < 1804800000 5>,
952 < 1958400000 6>,
953 < 2016000000 7>;
954 qcom,speed2-bin-v0-cci =
955 < 0 0>,
956 < 261120000 1>,
957 < 414720000 2>,
958 < 560640000 3>,
959 < 675840000 4>,
960 < 721920000 5>,
961 < 783360000 6>,
962 < 806400000 7>;
963 qcom,speed7-bin-v0-cl =
964 < 0 0>,
965 < 652800000 1>,
966 < 1036800000 2>,
967 < 1401600000 3>,
968 < 1689600000 4>,
969 < 1804800000 5>,
970 < 1958400000 6>,
971 < 2016000000 7>,
972 < 2150400000 8>,
973 < 2208000000 9>;
974 qcom,speed7-bin-v0-cci =
975 < 0 0>,
976 < 261120000 1>,
977 < 414720000 2>,
978 < 560640000 3>,
979 < 675840000 4>,
980 < 721920000 5>,
981 < 783360000 6>,
982 < 806400000 7>,
983 < 860160000 8>,
984 < 883200000 9>;
985 qcom,speed6-bin-v0-cl =
986 < 0 0>,
987 < 652800000 1>,
988 < 1036800000 2>,
989 < 1401600000 3>,
990 < 1689600000 4>,
991 < 1804800000 5>;
992 qcom,speed6-bin-v0-cci =
993 < 0 0>,
994 < 261120000 1>,
995 < 414720000 2>,
996 < 560640000 3>,
997 < 675840000 4>,
998 < 721920000 5>;
999 #clock-cells = <1>;
Maria Yub90c5482017-12-01 13:28:56 +08001000 };
1001
1002 msm_cpufreq: qcom,msm-cpufreq {
1003 compatible = "qcom,msm-cpufreq";
1004 clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
1005 "cpu3_clk", "cpu4_clk", "cpu5_clk",
1006 "cpu6_clk", "cpu7_clk";
1007 clocks = <&clock_cpu clk_cci_clk>,
1008 <&clock_cpu clk_a53_pwr_clk>,
1009 <&clock_cpu clk_a53_pwr_clk>,
1010 <&clock_cpu clk_a53_pwr_clk>,
1011 <&clock_cpu clk_a53_pwr_clk>,
1012 <&clock_cpu clk_a53_pwr_clk>,
1013 <&clock_cpu clk_a53_pwr_clk>,
1014 <&clock_cpu clk_a53_pwr_clk>,
1015 <&clock_cpu clk_a53_pwr_clk>;
1016
1017 qcom,cpufreq-table =
1018 < 652800 >,
1019 < 1036800 >,
1020 < 1401600 >,
1021 < 1689600 >,
1022 < 1804800 >,
1023 < 1958400 >,
1024 < 2016000 >,
1025 < 2150400 >,
1026 < 2208000 >;
Shefali Jain44e24ad2017-11-23 12:27:33 +05301027 };
1028
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301029 cpubw: qcom,cpubw {
1030 compatible = "qcom,devbw";
1031 governor = "cpufreq";
1032 qcom,src-dst-ports = <1 512>;
1033 qcom,active-only;
1034 qcom,bw-tbl =
1035 < 769 /* 100.8 MHz */ >,
1036 < 1611 /* 211.2 MHz */ >, /*Low SVS*/
1037 < 2124 /* 278.4 MHz */ >,
1038 < 2929 /* 384 MHz */ >,
1039 < 3221 /* 422.4 MHz */ >, /* SVS */
1040 < 4248 /* 556.8 MHz */ >,
1041 < 5126 /* 672 MHz */ >,
1042 < 5859 /* 768 MHz */ >, /* SVS+ */
1043 < 6152 /* 806.4 MHz */ >,
1044 < 6445 /* 844.8 MHz */ >, /* NOM */
1045 < 7104 /* 931.2 MHz */ >; /* TURBO */
1046 };
1047
1048 mincpubw: qcom,mincpubw {
1049 compatible = "qcom,devbw";
1050 governor = "cpufreq";
1051 qcom,src-dst-ports = <1 512>;
1052 qcom,active-only;
1053 qcom,bw-tbl =
1054 < 769 /* 100.8 MHz */ >,
1055 < 1611 /* 211.2 MHz */ >, /*Low SVS*/
1056 < 2124 /* 278.4 MHz */ >,
1057 < 2929 /* 384 MHz */ >,
1058 < 3221 /* 422.4 MHz */ >, /* SVS */
1059 < 4248 /* 556.8 MHz */ >,
1060 < 5126 /* 672 MHz */ >,
1061 < 5859 /* 768 MHz */ >, /* SVS+ */
1062 < 6152 /* 806.4 MHz */ >,
1063 < 6445 /* 844.8 MHz */ >, /* NOM */
1064 < 7104 /* 931.2 MHz */ >; /* TURBO */
1065 };
1066
1067 qcom,cpu-bwmon {
1068 compatible = "qcom,bimc-bwmon2";
1069 reg = <0x408000 0x300>, <0x401000 0x200>;
1070 reg-names = "base", "global_base";
1071 interrupts = <0 183 4>;
1072 qcom,mport = <0>;
1073 qcom,target-dev = <&cpubw>;
1074 };
1075
1076 devfreq-cpufreq {
1077 cpubw-cpufreq {
1078 target-dev = <&cpubw>;
1079 cpu-to-dev-map =
1080 < 652800 1611>,
1081 < 1036800 3221>,
1082 < 1401600 5859>,
1083 < 1689600 6445>,
1084 < 1804800 7104>,
1085 < 1958400 7104>,
1086 < 2208000 7104>;
1087 };
1088
1089 mincpubw-cpufreq {
1090 target-dev = <&mincpubw>;
1091 cpu-to-dev-map =
1092 < 652800 1611 >,
1093 < 1401600 3221 >,
1094 < 2208000 5859 >;
1095 };
1096 };
1097
Jonathan Avilac7a6fd52017-10-12 15:24:05 -07001098 cpubw_compute: qcom,cpubw-compute {
1099 compatible = "qcom,arm-cpu-mon";
1100 qcom,cpulist = < &CPU0 &CPU1 &CPU2 &CPU3
1101 &CPU4 &CPU5 &CPU6 &CPU7 >;
1102 qcom,target-dev = <&cpubw>;
1103 qcom,core-dev-table =
1104 < 652800 1611>,
1105 < 1036800 3221>,
1106 < 1401600 5859>,
1107 < 1689600 6445>,
1108 < 1804800 7104>,
1109 < 1958400 7104>,
1110 < 2208000 7104>;
1111 };
1112
1113 mincpubw_compute: qcom,mincpubw-compute {
1114 compatible = "qcom,arm-cpu-mon";
1115 qcom,cpulist = < &CPU0 &CPU1 &CPU2 &CPU3
1116 &CPU4 &CPU5 &CPU6 &CPU7 >;
1117 qcom,target-dev = <&mincpubw>;
1118 qcom,core-dev-table =
1119 < 652800 1611 >,
1120 < 1401600 3221 >,
1121 < 2208000 5859 >;
1122 };
1123
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301124 qcom,ipc-spinlock@1905000 {
1125 compatible = "qcom,ipc-spinlock-sfpb";
1126 reg = <0x1905000 0x8000>;
1127 qcom,num-locks = <8>;
1128 };
1129
1130 qcom,smem@86300000 {
1131 compatible = "qcom,smem";
1132 reg = <0x86300000 0x100000>,
1133 <0x0b011008 0x4>,
1134 <0x60000 0x8000>,
1135 <0x193d000 0x8>;
1136 reg-names = "smem", "irq-reg-base",
1137 "aux-mem1", "smem_targ_info_reg";
1138 qcom,mpu-enabled;
1139
1140 qcom,smd-modem {
1141 compatible = "qcom,smd";
1142 qcom,smd-edge = <0>;
1143 qcom,smd-irq-offset = <0x0>;
1144 qcom,smd-irq-bitmask = <0x1000>;
1145 interrupts = <0 25 1>;
1146 label = "modem";
1147 qcom,not-loadable;
1148 };
1149
1150 qcom,smsm-modem {
1151 compatible = "qcom,smsm";
1152 qcom,smsm-edge = <0>;
1153 qcom,smsm-irq-offset = <0x0>;
1154 qcom,smsm-irq-bitmask = <0x2000>;
1155 interrupts = <0 26 1>;
1156 };
1157
1158 qcom,smd-wcnss {
1159 compatible = "qcom,smd";
1160 qcom,smd-edge = <6>;
1161 qcom,smd-irq-offset = <0x0>;
1162 qcom,smd-irq-bitmask = <0x20000>;
1163 interrupts = <0 142 1>;
1164 label = "wcnss";
1165 };
1166
1167 qcom,smsm-wcnss {
1168 compatible = "qcom,smsm";
1169 qcom,smsm-edge = <6>;
1170 qcom,smsm-irq-offset = <0x0>;
1171 qcom,smsm-irq-bitmask = <0x80000>;
1172 interrupts = <0 144 1>;
1173 };
1174
1175 qcom,smd-adsp {
1176 compatible = "qcom,smd";
1177 qcom,smd-edge = <1>;
1178 qcom,smd-irq-offset = <0x0>;
1179 qcom,smd-irq-bitmask = <0x100>;
1180 interrupts = <0 289 1>;
1181 label = "adsp";
1182 };
1183
1184 qcom,smsm-adsp {
1185 compatible = "qcom,smsm";
1186 qcom,smsm-edge = <1>;
1187 qcom,smsm-irq-offset = <0x0>;
1188 qcom,smsm-irq-bitmask = <0x200>;
1189 interrupts = <0 290 1>;
1190 };
1191
1192 qcom,smd-rpm {
1193 compatible = "qcom,smd";
1194 qcom,smd-edge = <15>;
1195 qcom,smd-irq-offset = <0x0>;
1196 qcom,smd-irq-bitmask = <0x1>;
1197 interrupts = <0 168 1>;
1198 label = "rpm";
1199 qcom,irq-no-suspend;
1200 qcom,not-loadable;
1201 };
1202 };
1203
Arun Kumar Neelakantam36151aa2017-11-02 21:34:33 +05301204 qcom,smdtty {
1205 compatible = "qcom,smdtty";
1206
1207 smdtty_apps_fm: qcom,smdtty-apps-fm {
1208 qcom,smdtty-remote = "wcnss";
1209 qcom,smdtty-port-name = "APPS_FM";
1210 };
1211
1212 smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl {
1213 qcom,smdtty-remote = "wcnss";
1214 qcom,smdtty-port-name = "APPS_RIVA_BT_ACL";
1215 };
1216
1217 smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd {
1218 qcom,smdtty-remote = "wcnss";
1219 qcom,smdtty-port-name = "APPS_RIVA_BT_CMD";
1220 };
1221
1222 smdtty_mbalbridge: qcom,smdtty-mbalbridge {
1223 qcom,smdtty-remote = "modem";
1224 qcom,smdtty-port-name = "MBALBRIDGE";
1225 };
1226
1227 smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd {
1228 qcom,smdtty-remote = "wcnss";
1229 qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD";
1230 };
1231
1232 smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data {
1233 qcom,smdtty-remote = "wcnss";
1234 qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA";
1235 };
1236
1237 smdtty_data1: qcom,smdtty-data1 {
1238 qcom,smdtty-remote = "modem";
1239 qcom,smdtty-port-name = "DATA1";
1240 };
1241
1242 smdtty_data4: qcom,smdtty-data4 {
1243 qcom,smdtty-remote = "modem";
1244 qcom,smdtty-port-name = "DATA4";
1245 };
1246
1247 smdtty_data11: qcom,smdtty-data11 {
1248 qcom,smdtty-remote = "modem";
1249 qcom,smdtty-port-name = "DATA11";
1250 };
1251
1252 smdtty_data21: qcom,smdtty-data21 {
1253 qcom,smdtty-remote = "modem";
1254 qcom,smdtty-port-name = "DATA21";
1255 };
1256
1257 smdtty_loopback: smdtty-loopback {
1258 qcom,smdtty-remote = "modem";
1259 qcom,smdtty-port-name = "LOOPBACK";
1260 qcom,smdtty-dev-name = "LOOPBACK_TTY";
1261 };
1262 };
1263
Arun Kumar Neelakantamea07e3d2017-11-02 21:27:50 +05301264 qcom,smdpkt {
1265 compatible = "qcom,smdpkt";
1266
1267 qcom,smdpkt-data5-cntl {
1268 qcom,smdpkt-remote = "modem";
1269 qcom,smdpkt-port-name = "DATA5_CNTL";
1270 qcom,smdpkt-dev-name = "smdcntl0";
1271 };
1272
1273 qcom,smdpkt-data22 {
1274 qcom,smdpkt-remote = "modem";
1275 qcom,smdpkt-port-name = "DATA22";
1276 qcom,smdpkt-dev-name = "smd22";
1277 };
1278
1279 qcom,smdpkt-data40-cntl {
1280 qcom,smdpkt-remote = "modem";
1281 qcom,smdpkt-port-name = "DATA40_CNTL";
1282 qcom,smdpkt-dev-name = "smdcntl8";
1283 };
1284
Arun Kumar Neelakantam977aa512018-03-08 17:42:47 +05301285 qcom,smdpkt-data2 {
1286 qcom,smdpkt-remote = "modem";
1287 qcom,smdpkt-port-name = "DATA2";
1288 qcom,smdpkt-dev-name = "at_mdm0";
1289 };
1290
Arun Kumar Neelakantamea07e3d2017-11-02 21:27:50 +05301291 qcom,smdpkt-apr-apps2 {
1292 qcom,smdpkt-remote = "adsp";
1293 qcom,smdpkt-port-name = "apr_apps2";
1294 qcom,smdpkt-dev-name = "apr_apps2";
1295 };
1296
1297 qcom,smdpkt-loopback {
1298 qcom,smdpkt-remote = "modem";
1299 qcom,smdpkt-port-name = "LOOPBACK";
1300 qcom,smdpkt-dev-name = "smd_pkt_loopback";
1301 };
1302 };
1303
himta ramd2cef3e2018-04-02 12:26:28 +05301304 qcom,iris-fm {
1305 compatible = "qcom,iris_fm";
1306 };
1307
Raju P.L.S.S.S.N786994d2017-11-08 17:03:56 +05301308 rpm_bus: qcom,rpm-smd {
1309 compatible = "qcom,rpm-smd";
1310 rpm-channel-name = "rpm_requests";
1311 rpm-channel-type = <15>; /* SMD_APPS_RPM */
1312 };
1313
Maria Yuf16c1602017-12-22 13:05:17 +08001314 wdog: qcom,wdt@b017000 {
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301315 compatible = "qcom,msm-watchdog";
1316 reg = <0xb017000 0x1000>;
1317 reg-names = "wdt-base";
1318 interrupts = <0 3 0>, <0 4 0>;
1319 qcom,bark-time = <11000>;
Maria Yu40db1752018-06-21 15:44:36 +08001320 qcom,pet-time = <9360>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301321 qcom,ipi-ping;
1322 qcom,wakeup-enable;
Jinlong Maoc2268652018-03-15 11:14:58 +05301323 qcom,scandump-size = <0x40000>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301324 };
1325
Teng Fei Fan04770062018-02-28 09:30:42 +08001326 qcom,chd_silver {
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301327 compatible = "qcom,core-hang-detect";
Teng Fei Fan04770062018-02-28 09:30:42 +08001328 label = "silver";
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301329 qcom,threshold-arr = <0xb1880b0 0xb1980b0 0xb1a80b0
Teng Fei Fan04770062018-02-28 09:30:42 +08001330 0xb1b80b0>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301331 qcom,config-arr = <0xb1880b8 0xb1980b8 0xb1a80b8
Teng Fei Fan04770062018-02-28 09:30:42 +08001332 0xb1b80b8>;
1333 };
1334
1335 qcom,chd_gold {
1336 compatible = "qcom,core-hang-detect";
1337 label = "gold";
1338 qcom,threshold-arr = <0xb0880b0 0xb0980b0 0xb0a80b0
1339 0xb0b80b0>;
1340 qcom,config-arr = <0xb0880b8 0xb0980b8 0xb0a80b8
1341 0xb0b80b8>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301342 };
1343
1344 qcom,msm-rtb {
1345 compatible = "qcom,msm-rtb";
1346 qcom,rtb-size = <0x100000>;
1347 };
1348
1349 qcom,msm-imem@8600000 {
1350 compatible = "qcom,msm-imem";
1351 reg = <0x08600000 0x1000>;
1352 ranges = <0x0 0x08600000 0x1000>;
1353 #address-cells = <1>;
1354 #size-cells = <1>;
1355
1356 mem_dump_table@10 {
1357 compatible = "qcom,msm-imem-mem_dump_table";
1358 reg = <0x10 8>;
1359 };
1360
Swetha Chikkaboraiah96a49812018-10-23 17:27:19 +05301361 dload_type@1c {
Maria Yu06cf96e2017-09-21 17:35:13 +08001362 compatible = "qcom,msm-imem-dload-type";
Swetha Chikkaboraiah96a49812018-10-23 17:27:19 +05301363 reg = <0x1c 4>;
Maria Yu06cf96e2017-09-21 17:35:13 +08001364 };
1365
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301366 restart_reason@65c {
1367 compatible = "qcom,msm-imem-restart_reason";
1368 reg = <0x65c 4>;
1369 };
1370
1371 boot_stats@6b0 {
1372 compatible = "qcom,msm-imem-boot_stats";
1373 reg = <0x6b0 32>;
1374 };
1375
Maria Yu575d67f2017-12-05 16:31:19 +08001376 kaslr_offset@6d0 {
1377 compatible = "qcom,msm-imem-kaslr_offset";
1378 reg = <0x6d0 12>;
1379 };
1380
1381 pil@94c {
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301382 compatible = "qcom,msm-imem-pil";
1383 reg = <0x94c 200>;
1384
1385 };
Sriharsha Allenkia5bcba72018-02-13 15:22:34 +05301386
1387 diag_dload@c8 {
1388 compatible = "qcom,msm-imem-diag-dload";
1389 reg = <0xc8 200>;
1390 };
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301391 };
1392
1393 qcom,memshare {
1394 compatible = "qcom,memshare";
1395
1396 qcom,client_1 {
1397 compatible = "qcom,memshare-peripheral";
1398 qcom,peripheral-size = <0x200000>;
1399 qcom,client-id = <0>;
1400 qcom,allocate-boot-time;
1401 label = "modem";
1402 };
1403
1404 qcom,client_2 {
1405 compatible = "qcom,memshare-peripheral";
1406 qcom,peripheral-size = <0x300000>;
1407 qcom,client-id = <2>;
1408 label = "modem";
1409 };
1410
Manoj Prabhu B4dd89f82018-02-06 12:42:52 +05301411 qcom,client_3 {
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301412 compatible = "qcom,memshare-peripheral";
Manoj Prabhu B4dd89f82018-02-06 12:42:52 +05301413 qcom,peripheral-size = <0x500000>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301414 qcom,client-id = <1>;
Manoj Prabhu B4dd89f82018-02-06 12:42:52 +05301415 qcom,allocate-boot-time;
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301416 label = "modem";
1417 };
1418 };
Mao Jinlongf77a1ca2018-03-15 14:59:57 +08001419
1420 jtag_mm0: jtagmm@619c000 {
1421 compatible = "qcom,jtagv8-mm";
1422 reg = <0x619c000 0x1000>;
1423 reg-names = "etm-base";
1424
1425 qcom,coresight-jtagmm-cpu = <&CPU0>;
1426
1427 clocks = <&clock_gcc clk_qdss_clk>,
1428 <&clock_gcc clk_qdss_a_clk>;
1429 clock-names = "core_clk";
1430 };
1431
1432 jtag_mm1: jtagmm@619d000 {
1433 compatible = "qcom,jtagv8-mm";
1434 reg = <0x619d000 0x1000>;
1435 reg-names = "etm-base";
1436
1437 qcom,coresight-jtagmm-cpu = <&CPU1>;
1438
1439 clocks = <&clock_gcc clk_qdss_clk>,
1440 <&clock_gcc clk_qdss_a_clk>;
1441 clock-names = "core_clk";
1442 };
1443
1444 jtag_mm2: jtagmm@619e000 {
1445 compatible = "qcom,jtagv8-mm";
1446 reg = <0x619e000 0x1000>;
1447 reg-names = "etm-base";
1448
1449 qcom,coresight-jtagmm-cpu = <&CPU2>;
1450
1451 clocks = <&clock_gcc clk_qdss_clk>,
1452 <&clock_gcc clk_qdss_a_clk>;
1453 clock-names = "core_clk";
1454 };
1455
1456 jtag_mm3: jtagmm@619f000 {
1457 compatible = "qcom,jtagv8-mm";
1458 reg = <0x619f000 0x1000>;
1459 reg-names = "etm-base";
1460
1461 qcom,coresight-jtagmm-cpu = <&CPU3>;
1462
1463 clocks = <&clock_gcc clk_qdss_clk>,
1464 <&clock_gcc clk_qdss_a_clk>;
1465 clock-names = "core_clk";
1466 };
1467
1468 jtag_mm4: jtagmm@61bc000 {
1469 compatible = "qcom,jtagv8-mm";
1470 reg = <0x61bc000 0x1000>;
1471 reg-names = "etm-base";
1472
1473 qcom,coresight-jtagmm-cpu = <&CPU4>;
1474
1475 clocks = <&clock_gcc clk_qdss_clk>,
1476 <&clock_gcc clk_qdss_a_clk>;
1477 clock-names = "core_clk";
1478 };
1479
1480 jtag_mm5: jtagmm@61bd000 {
1481 compatible = "qcom,jtagv8-mm";
1482 reg = <0x61bd000 0x1000>;
1483 reg-names = "etm-base";
1484
1485 qcom,coresight-jtagmm-cpu = <&CPU5>;
1486
1487 clocks = <&clock_gcc clk_qdss_clk>,
1488 <&clock_gcc clk_qdss_a_clk>;
1489 clock-names = "core_clk";
1490 };
1491
1492 jtag_mm6: jtagmm@61be000 {
1493 compatible = "qcom,jtagv8-mm";
1494 reg = <0x61be000 0x1000>;
1495 reg-names = "etm-base";
1496
1497 qcom,coresight-jtagmm-cpu = <&CPU6>;
1498
1499 clocks = <&clock_gcc clk_qdss_clk>,
1500 <&clock_gcc clk_qdss_a_clk>;
1501 clock-names = "core_clk";
1502 };
1503
1504 jtag_mm7: jtagmm@61bf000 {
1505 compatible = "qcom,jtagv8-mm";
1506 reg = <0x61bf000 0x1000>;
1507 reg-names = "etm-base";
1508
1509 qcom,coresight-jtagmm-cpu = <&CPU7>;
1510
1511 clocks = <&clock_gcc clk_qdss_clk>,
1512 <&clock_gcc clk_qdss_a_clk>;
1513 clock-names = "core_clk";
1514 };
1515
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301516 sdcc1_ice: sdcc1ice@7803000 {
1517 compatible = "qcom,ice";
1518 reg = <0x7803000 0x8000>;
1519 interrupt-names = "sdcc_ice_nonsec_level_irq",
1520 "sdcc_ice_sec_level_irq";
1521 interrupts = <0 312 0>, <0 313 0>;
1522 qcom,enable-ice-clk;
Sayali Lokhande31299932017-12-06 09:41:17 +05301523 clock-names = "ice_core_clk_src", "ice_core_clk",
1524 "bus_clk", "iface_clk";
1525 clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>,
1526 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>,
1527 <&clock_gcc clk_gcc_sdcc1_apps_clk>,
1528 <&clock_gcc clk_gcc_sdcc1_ahb_clk>;
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301529 qcom,op-freq-hz = <270000000>, <0>, <0>, <0>;
1530 qcom,msm-bus,name = "sdcc_ice_noc";
1531 qcom,msm-bus,num-cases = <2>;
1532 qcom,msm-bus,num-paths = <1>;
1533 qcom,msm-bus,vectors-KBps =
1534 <78 512 0 0>, /* No vote */
1535 <78 512 1000 0>; /* Max. bandwidth */
1536 qcom,bus-vector-names = "MIN", "MAX";
1537 qcom,instance-type = "sdcc";
1538 };
1539
1540 sdhc_1: sdhci@7824900 {
1541 compatible = "qcom,sdhci-msm";
Pradeep P V K0bf93592018-06-25 19:34:48 +05301542 reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>,
1543 <0x0119d000 0x4>;
1544 reg-names = "hc_mem", "core_mem", "cmdq_mem",
1545 "tlmm_mem";
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301546
1547 interrupts = <0 123 0>, <0 138 0>;
1548 interrupt-names = "hc_irq", "pwr_irq";
1549
1550 sdhc-msm-crypto = <&sdcc1_ice>;
1551 qcom,bus-width = <8>;
1552
1553 qcom,devfreq,freq-table = <50000000 200000000>;
1554
1555 qcom,pm-qos-irq-type = "affine_irq";
1556 qcom,pm-qos-irq-latency = <2 213>;
1557
1558 qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
1559 qcom,pm-qos-cmdq-latency-us = <2 213>, <2 213>;
1560
1561 qcom,pm-qos-legacy-latency-us = <2 213>, <2 213>;
1562
1563 qcom,msm-bus,name = "sdhc1";
1564 qcom,msm-bus,num-cases = <9>;
1565 qcom,msm-bus,num-paths = <1>;
1566 qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
1567 <78 512 1046 3200>, /* 400 KB/s*/
1568 <78 512 52286 160000>, /* 20 MB/s */
1569 <78 512 65360 200000>, /* 25 MB/s */
1570 <78 512 130718 400000>, /* 50 MB/s */
1571 <78 512 130718 400000>, /* 100 MB/s */
1572 <78 512 261438 800000>, /* 200 MB/s */
1573 <78 512 261438 800000>, /* 400 MB/s */
1574 <78 512 1338562 4096000>; /* Max. bandwidth */
1575 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
1576 100000000 200000000 400000000 4294967295>;
1577
Sayali Lokhande31299932017-12-06 09:41:17 +05301578 clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
1579 <&clock_gcc clk_gcc_sdcc1_apps_clk>,
1580 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>;
1581 clock-names = "iface_clk", "core_clk", "ice_core_clk";
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301582 qcom,ice-clk-rates = <270000000 160000000>;
1583 qcom,large-address-bus;
1584
1585 status = "disabled";
1586 };
1587
1588 sdhc_2: sdhci@7864900 {
1589 compatible = "qcom,sdhci-msm";
1590 reg = <0x7864900 0x500>, <0x7864000 0x800>;
1591 reg-names = "hc_mem", "core_mem";
1592
1593 interrupts = <0 125 0>, <0 221 0>;
1594 interrupt-names = "hc_irq", "pwr_irq";
1595
1596 qcom,bus-width = <4>;
1597
1598 qcom,pm-qos-irq-type = "affine_irq";
1599 qcom,pm-qos-irq-latency = <2 213>;
1600
1601 qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
1602 qcom,pm-qos-legacy-latency-us = <2 213>, <2 213>;
1603
1604 qcom,devfreq,freq-table = <50000000 200000000>;
1605
1606 qcom,msm-bus,name = "sdhc2";
1607 qcom,msm-bus,num-cases = <8>;
1608 qcom,msm-bus,num-paths = <1>;
1609 qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
1610 <81 512 1046 3200>, /* 400 KB/s*/
1611 <81 512 52286 160000>, /* 20 MB/s */
1612 <81 512 65360 200000>, /* 25 MB/s */
1613 <81 512 130718 400000>, /* 50 MB/s */
1614 <81 512 261438 800000>, /* 100 MB/s */
1615 <81 512 261438 800000>, /* 200 MB/s */
1616 <81 512 1338562 4096000>; /* Max. bandwidth */
1617 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
1618 100000000 200000000 4294967295>;
1619
Sayali Lokhande31299932017-12-06 09:41:17 +05301620 clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
1621 <&clock_gcc clk_gcc_sdcc2_apps_clk>;
1622 clock-names = "iface_clk", "core_clk";
1623
Srinivas Ramana3cac2782017-09-13 16:31:17 +05301624 qcom,large-address-bus;
1625 status = "disabled";
1626 };
1627
Tharun Kumar Meruguc1413e72018-01-22 19:23:58 +05301628 qcom,msm-adsprpc-mem {
1629 compatible = "qcom,msm-adsprpc-mem-region";
1630 memory-region = <&adsp_mem>;
1631 };
1632
1633 qcom,msm_fastrpc {
1634 compatible = "qcom,msm-fastrpc-legacy-compute";
1635 qcom,msm_fastrpc_compute_cb {
1636 compatible = "qcom,msm-fastrpc-legacy-compute-cb";
1637 label = "adsprpc-smd";
1638 iommus = <&apps_iommu 0x2408 0x7>;
1639 sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
1640 };
1641 };
1642
1643
Mohammed Javidf62ec622017-11-29 20:07:32 +05301644 ipa_hw: qcom,ipa@07900000 {
1645 compatible = "qcom,ipa";
1646 reg = <0x07900000 0x4effc>, <0x07904000 0x26934>;
1647 reg-names = "ipa-base", "bam-base";
1648 interrupts = <0 228 0>,
1649 <0 230 0>;
1650 interrupt-names = "ipa-irq", "bam-irq";
1651 qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */
1652 qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
1653 qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/
1654 qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/
1655 clock-names = "core_clk";
1656 clocks = <&clock_gcc clk_ipa_clk>;
1657 qcom,ee = <0>;
1658 qcom,use-ipa-tethering-bridge;
1659 qcom,modem-cfg-emb-pipe-flt;
1660 qcom,msm-bus,name = "ipa";
1661 qcom,msm-bus,num-cases = <3>;
1662 qcom,msm-bus,num-paths = <1>;
1663 qcom,msm-bus,vectors-KBps =
1664 <90 512 0 0>, /* No BIMC vote (ab=0 Mbps, ib=0 Mbps ~ 0MHZ) */
1665 <90 512 100000 800000>, /* SVS (ab=100, ib=800 ~ 50MHz) */
1666 <90 512 100000 1200000>; /* PERF (ab=100, ib=1200 ~ 75MHz) */
1667 qcom,bus-vector-names = "MIN", "SVS", "PERF";
1668 };
1669
1670 qcom,rmnet-ipa {
1671 compatible = "qcom,rmnet-ipa";
1672 qcom,rmnet-ipa-ssr;
1673 qcom,ipa-loaduC;
1674 qcom,ipa-advertise-sg-support;
1675 };
1676
Kiran Gundaaf6a0b62017-10-23 16:03:10 +05301677 spmi_bus: qcom,spmi@200f000 {
1678 compatible = "qcom,spmi-pmic-arb";
1679 reg = <0x200f000 0x1000>,
1680 <0x2400000 0x800000>,
1681 <0x2c00000 0x800000>,
1682 <0x3800000 0x200000>,
1683 <0x200a000 0x2100>;
1684 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1685 interrupt-names = "periph_irq";
1686 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
1687 qcom,ee = <0>;
1688 qcom,channel = <0>;
Anirudh Ghayald77f8f62018-03-04 20:05:25 +05301689 #address-cells = <1>;
1690 #size-cells = <1>;
Kiran Gundaaf6a0b62017-10-23 16:03:10 +05301691 interrupt-controller;
Kiran Gunda90e356a2017-11-22 17:04:46 +05301692 #interrupt-cells = <4>;
Kiran Gundaaf6a0b62017-10-23 16:03:10 +05301693 cell-index = <0>;
1694 };
Chandana Kishori Chiluveru34872ee2017-11-30 17:35:26 +05301695
1696 usb3: ssusb@7000000{
1697 compatible = "qcom,dwc-usb3-msm";
1698 reg = <0x07000000 0xfc000>,
1699 <0x0007e000 0x400>;
1700 reg-names = "core_base",
1701 "ahb2phy_base";
1702 #address-cells = <1>;
1703 #size-cells = <1>;
1704 ranges;
1705
1706 interrupts = <0 136 0>, <0 220 0>, <0 134 0>;
1707 interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
1708
1709 USB3_GDSC-supply = <&gdsc_usb30>;
1710 qcom,usb-dbm = <&dbm_1p5>;
1711 qcom,msm-bus,name = "usb3";
1712 qcom,msm-bus,num-cases = <3>;
1713 qcom,msm-bus,num-paths = <1>;
1714 qcom,msm-bus,vectors-KBps =
1715 <61 512 0 0>,
1716 <61 512 240000 800000>,
1717 <61 512 240000 800000>;
1718
1719 /* CPU-CLUSTER-WFI-LVL latency +1 */
1720 qcom,pm-qos-latency = <2>;
1721
1722 qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
1723
1724 clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
1725 <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>,
1726 <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
1727 <&clock_gcc clk_gcc_usb30_sleep_clk>,
1728 <&clock_gcc clk_xo_dwc3_clk>,
1729 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;
1730
1731 clock-names = "core_clk", "iface_clk", "utmi_clk",
1732 "sleep_clk", "xo", "cfg_ahb_clk";
1733
1734 qcom,core-clk-rate = <133333333>; /* NOM */
1735 qcom,core-clk-rate-hs = <60000000>; /* LOW SVS */
1736
1737 resets = <&clock_gcc GCC_USB_30_BCR>;
1738 reset-names = "core_reset";
1739
1740 dwc3@7000000 {
1741 compatible = "snps,dwc3";
1742 reg = <0x07000000 0xc8d0>;
1743 interrupt-parent = <&intc>;
1744 interrupts = <0 140 0>;
1745 usb-phy = <&qusb_phy>, <&ssphy>;
1746 tx-fifo-resize;
1747 snps,usb3-u1u2-disable;
Chandana Kishori Chiluveru34872ee2017-11-30 17:35:26 +05301748 snps,is-utmi-l1-suspend;
Sriharsha Allenkia727b822018-03-13 18:17:35 +05301749 snps,usb2-l1-disable;
Chandana Kishori Chiluveru34872ee2017-11-30 17:35:26 +05301750 snps,hird-threshold = /bits/ 8 <0x0>;
1751 };
1752
1753 qcom,usbbam@7104000 {
1754 compatible = "qcom,usb-bam-msm";
1755 reg = <0x07104000 0x1a934>;
1756 interrupt-parent = <&intc>;
1757 interrupts = <0 135 0>;
1758
1759 qcom,bam-type = <0>;
1760 qcom,usb-bam-fifo-baseaddr = <0x08605000>;
1761 qcom,usb-bam-num-pipes = <8>;
1762 qcom,ignore-core-reset-ack;
1763 qcom,disable-clk-gating;
1764 qcom,usb-bam-override-threshold = <0x4001>;
1765 qcom,usb-bam-max-mbps-highspeed = <400>;
1766 qcom,usb-bam-max-mbps-superspeed = <3600>;
1767 qcom,reset-bam-on-connect;
1768
1769 qcom,pipe0 {
1770 label = "ssusb-ipa-out-0";
1771 qcom,usb-bam-mem-type = <1>;
1772 qcom,dir = <0>;
1773 qcom,pipe-num = <0>;
1774 qcom,peer-bam = <1>;
1775 qcom,src-bam-pipe-index = <1>;
1776 qcom,data-fifo-size = <0x8000>;
1777 qcom,descriptor-fifo-size = <0x2000>;
1778 };
1779
1780 qcom,pipe1 {
1781 label = "ssusb-ipa-in-0";
1782 qcom,usb-bam-mem-type = <1>;
1783 qcom,dir = <1>;
1784 qcom,pipe-num = <0>;
1785 qcom,peer-bam = <1>;
1786 qcom,dst-bam-pipe-index = <0>;
1787 qcom,data-fifo-size = <0x8000>;
1788 qcom,descriptor-fifo-size = <0x2000>;
1789 };
1790
1791 qcom,pipe2 {
1792 label = "ssusb-qdss-in-0";
1793 qcom,usb-bam-mem-type = <2>;
1794 qcom,dir = <1>;
1795 qcom,pipe-num = <0>;
1796 qcom,peer-bam = <0>;
1797 qcom,peer-bam-physical-address = <0x06044000>;
1798 qcom,src-bam-pipe-index = <0>;
1799 qcom,dst-bam-pipe-index = <2>;
1800 qcom,data-fifo-offset = <0x0>;
1801 qcom,data-fifo-size = <0xe00>;
1802 qcom,descriptor-fifo-offset = <0xe00>;
1803 qcom,descriptor-fifo-size = <0x200>;
1804 };
1805
1806 qcom,pipe3 {
1807 label = "ssusb-dpl-ipa-in-1";
1808 qcom,usb-bam-mem-type = <1>;
1809 qcom,dir = <1>;
1810 qcom,pipe-num = <1>;
1811 qcom,peer-bam = <1>;
1812 qcom,dst-bam-pipe-index = <2>;
1813 qcom,data-fifo-size = <0x8000>;
1814 qcom,descriptor-fifo-size = <0x2000>;
1815 };
1816 };
1817 };
1818
1819 qusb_phy: qusb@79000 {
1820 compatible = "qcom,qusb2phy";
1821 reg = <0x079000 0x180>,
1822 <0x01841030 0x4>,
1823 <0x0193f020 0x4>;
1824 reg-names = "qusb_phy_base",
1825 "ref_clk_addr",
1826 "tcsr_clamp_dig_n_1p8";
1827
1828 USB3_GDSC-supply = <&gdsc_usb30>;
1829 vdd-supply = <&pm8953_l3>;
1830 vdda18-supply = <&pm8953_l7>;
1831 vdda33-supply = <&pm8953_l13>;
1832 qcom,vdd-voltage-level = <0 925000 925000>;
1833
1834 qcom,qusb-phy-init-seq = <0xf8 0x80
1835 0xb3 0x84
1836 0x83 0x88
1837 0xc0 0x8c
1838 0x14 0x9c
1839 0x30 0x08
1840 0x79 0x0c
1841 0x21 0x10
1842 0x00 0x90
1843 0x9f 0x1c
1844 0x00 0x18>;
1845 phy_type= "utmi";
1846 qcom,phy-clk-scheme = "cml";
1847 qcom,major-rev = <1>;
1848
1849 clocks = <&clock_gcc clk_bb_clk1>,
1850 <&clock_gcc clk_gcc_qusb_ref_clk>,
1851 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>,
1852 <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>,
1853 <&clock_gcc clk_gcc_usb30_master_clk>;
1854
1855 clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk",
1856 "iface_clk", "core_clk";
1857
1858 resets = <&clock_gcc GCC_QUSB2_PHY_BCR>;
1859 reset-names = "phy_reset";
1860 };
1861
1862 ssphy: ssphy@78000 {
1863 compatible = "qcom,usb-ssphy-qmp";
1864 reg = <0x78000 0x9f8>,
1865 <0x0193f244 0x4>;
1866 reg-names = "qmp_phy_base",
1867 "vls_clamp_reg";
1868
1869 qcom,qmp-phy-init-seq = /*<reg_offset, value, delay>*/
1870 <0xac 0x14 0x00
1871 0x34 0x08 0x00
1872 0x174 0x30 0x00
1873 0x3c 0x06 0x00
1874 0xb4 0x00 0x00
1875 0xb8 0x08 0x00
1876 0x194 0x06 0x3e8
1877 0x19c 0x01 0x00
1878 0x178 0x00 0x00
1879 0xd0 0x82 0x00
1880 0xdc 0x55 0x00
1881 0xe0 0x55 0x00
1882 0xe4 0x03 0x00
1883 0x78 0x0b 0x00
1884 0x84 0x16 0x00
1885 0x90 0x28 0x00
1886 0x108 0x80 0x00
1887 0x10c 0x00 0x00
1888 0x184 0x0a 0x00
1889 0x4c 0x15 0x00
1890 0x50 0x34 0x00
1891 0x54 0x00 0x00
1892 0xc8 0x00 0x00
1893 0x18c 0x00 0x00
1894 0xcc 0x00 0x00
1895 0x128 0x00 0x00
1896 0x0c 0x0a 0x00
1897 0x10 0x01 0x00
1898 0x1c 0x31 0x00
1899 0x20 0x01 0x00
1900 0x14 0x00 0x00
1901 0x18 0x00 0x00
1902 0x24 0xde 0x00
1903 0x28 0x07 0x00
1904 0x48 0x0f 0x00
1905 0x70 0x0f 0x00
1906 0x100 0x80 0x00
1907 0x440 0x0b 0x00
1908 0x4d8 0x02 0x00
1909 0x4dc 0x6c 0x00
1910 0x4e0 0xbb 0x00
1911 0x508 0x77 0x00
1912 0x50c 0x80 0x00
1913 0x514 0x03 0x00
1914 0x51c 0x16 0x00
1915 0x448 0x75 0x00
1916 0x454 0x00 0x00
1917 0x40c 0x0a 0x00
1918 0x41c 0x06 0x00
1919 0x510 0x00 0x00
1920 0x268 0x45 0x00
1921 0x2ac 0x12 0x00
1922 0x294 0x06 0x00
1923 0x254 0x00 0x00
1924 0x8c8 0x83 0x00
1925 0x8c4 0x02 0x00
1926 0x8cc 0x09 0x00
1927 0x8d0 0xa2 0x00
1928 0x8d4 0x85 0x00
1929 0x880 0xd1 0x00
1930 0x884 0x1f 0x00
1931 0x888 0x47 0x00
1932 0x80c 0x9f 0x00
1933 0x824 0x17 0x00
1934 0x828 0x0f 0x00
1935 0x8b8 0x75 0x00
1936 0x8bc 0x13 0x00
1937 0x8b0 0x86 0x00
1938 0x8a0 0x04 0x00
1939 0x88c 0x44 0x00
1940 0x870 0xe7 0x00
1941 0x874 0x03 0x00
1942 0x878 0x40 0x00
1943 0x87c 0x00 0x00
1944 0x9d8 0x88 0x00
1945 0xffffffff 0x00 0x00>;
1946 qcom,qmp-phy-reg-offset =
1947 <0x974 /* USB3_PHY_PCS_STATUS */
1948 0x8d8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
1949 0x8dc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
1950 0x804 /* USB3_PHY_POWER_DOWN_CONTROL */
1951 0x800 /* USB3_PHY_SW_RESET */
1952 0x808>; /* USB3_PHY_START */
1953
1954 vdd-supply = <&pm8953_l3>;
1955 core-supply = <&pm8953_l7>;
1956 qcom,vdd-voltage-level = <0 925000 925000>;
1957 qcom,core-voltage-level = <0 1800000 1800000>;
1958 qcom,vbus-valid-override;
1959
1960 clocks = <&clock_gcc clk_gcc_usb3_aux_clk>,
1961 <&clock_gcc clk_gcc_usb3_pipe_clk>,
1962 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>,
1963 <&clock_gcc clk_bb_clk1>,
1964 <&clock_gcc clk_gcc_usb_ss_ref_clk>;
1965
1966 clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
1967 "ref_clk_src", "ref_clk";
1968
1969 resets = <&clock_gcc GCC_USB3_PHY_BCR>,
1970 <&clock_gcc GCC_USB3PHY_PHY_BCR>;
1971
1972 reset-names = "phy_reset", "phy_phy_reset";
1973 };
1974
1975 dbm_1p5: dbm@70f8000 {
1976 compatible = "qcom,usb-dbm-1p5";
1977 reg = <0x070f8000 0x300>;
1978 qcom,reset-ep-after-lpm-resume;
1979 };
Jitendra Sharmac5c31972017-11-10 14:26:13 +05301980
Jingbiao Lue44c5e52018-01-03 15:26:26 +08001981 qcom,mss@4080000 {
1982 compatible = "qcom,pil-q6v55-mss";
1983 reg = <0x04080000 0x100>,
1984 <0x0194f000 0x010>,
1985 <0x01950000 0x008>,
1986 <0x01951000 0x008>,
1987 <0x04020000 0x040>,
1988 <0x01871000 0x004>;
1989 reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc",
1990 "rmb_base", "restart_reg";
1991
1992 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
1993 vdd_mss-supply = <&pm8953_s1>;
1994 vdd_cx-supply = <&pm8953_s2_level>;
1995 vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
1996 vdd_mx-supply = <&pm8953_s7_level_ao>;
1997 vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
1998 vdd_pll-supply = <&pm8953_l7>;
1999 qcom,vdd_pll = <1800000>;
2000 vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
2001
2002 clocks = <&clock_gcc clk_xo_pil_mss_clk>,
2003 <&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
2004 <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
2005 <&clock_gcc clk_gcc_boot_rom_ahb_clk>;
2006 clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
2007 qcom,proxy-clock-names = "xo";
2008 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
2009
2010 qcom,pas-id = <5>;
2011 qcom,pil-mss-memsetup;
2012 qcom,firmware-name = "modem";
2013 qcom,pil-self-auth;
Sanjay Dwivedi4adc0582019-07-26 14:43:15 +05302014 qcom,sequential-fw-load;
Jingbiao Lue44c5e52018-01-03 15:26:26 +08002015 qcom,sysmon-id = <0>;
2016 qcom,ssctl-instance-id = <0x12>;
2017 qcom,qdsp6v56-1-10;
2018 qcom,reset-clk;
2019
Jitendra Sharma1b581f72018-02-23 17:10:12 +05302020 /* GPIO inputs from mss */
2021 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2022 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2023 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2024 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2025 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2026
2027 /* GPIO output to mss */
2028 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Jingbiao Lue44c5e52018-01-03 15:26:26 +08002029 memory-region = <&modem_mem>;
2030 };
2031
Jitendra Sharmac5c31972017-11-10 14:26:13 +05302032 qcom,lpass@c200000 {
2033 compatible = "qcom,pil-tz-generic";
2034 reg = <0xc200000 0x00100>;
2035 interrupts = <0 293 1>;
2036
2037 vdd_cx-supply = <&pm8953_s2_level>;
2038 qcom,proxy-reg-names = "vdd_cx";
2039 qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
Jingbiao Lu60bda872017-12-27 10:54:21 +08002040 qcom,mas-crypto = <&mas_crypto>;
Jitendra Sharmac5c31972017-11-10 14:26:13 +05302041
2042 clocks = <&clock_gcc clk_xo_pil_lpass_clk>,
2043 <&clock_gcc clk_gcc_crypto_clk>,
2044 <&clock_gcc clk_gcc_crypto_ahb_clk>,
2045 <&clock_gcc clk_gcc_crypto_axi_clk>,
2046 <&clock_gcc clk_crypto_clk_src>;
2047 clock-names = "xo", "scm_core_clk", "scm_iface_clk",
2048 "scm_bus_clk", "scm_core_clk_src";
2049 qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
2050 "scm_bus_clk", "scm_core_clk_src";
2051 qcom,scm_core_clk_src-freq = <80000000>;
2052
2053 qcom,pas-id = <1>;
2054 qcom,complete-ramdump;
2055 qcom,proxy-timeout-ms = <10000>;
2056 qcom,smem-id = <423>;
2057 qcom,sysmon-id = <1>;
2058 qcom,ssctl-instance-id = <0x14>;
2059 qcom,firmware-name = "adsp";
2060
Jitendra Sharma1b581f72018-02-23 17:10:12 +05302061 /* GPIO inputs from lpass */
2062 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
2063 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
2064 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
2065 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
2066
2067 /* GPIO output to lpass */
2068 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
2069
Jitendra Sharmac5c31972017-11-10 14:26:13 +05302070 memory-region = <&adsp_fw_mem>;
2071 };
Jitendra Sharmaa50d8082017-11-10 14:33:32 +05302072
2073 qcom,pronto@a21b000 {
2074 compatible = "qcom,pil-tz-generic";
2075 reg = <0x0a21b000 0x3000>;
2076 interrupts = <0 149 1>;
2077
2078 vdd_pronto_pll-supply = <&pm8953_l7>;
2079 proxy-reg-names = "vdd_pronto_pll";
2080 vdd_pronto_pll-uV-uA = <1800000 18000>;
Jingbiao Lu60bda872017-12-27 10:54:21 +08002081 qcom,mas-crypto = <&mas_crypto>;
2082
Jitendra Sharmaa50d8082017-11-10 14:33:32 +05302083 clocks = <&clock_gcc clk_xo_pil_pronto_clk>,
2084 <&clock_gcc clk_gcc_crypto_clk>,
2085 <&clock_gcc clk_gcc_crypto_ahb_clk>,
2086 <&clock_gcc clk_gcc_crypto_axi_clk>,
2087 <&clock_gcc clk_crypto_clk_src>;
2088
2089 clock-names = "xo", "scm_core_clk", "scm_iface_clk",
2090 "scm_bus_clk", "scm_core_clk_src";
2091 qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
2092 "scm_bus_clk", "scm_core_clk_src";
2093 qcom,scm_core_clk_src = <80000000>;
2094
2095 qcom,pas-id = <6>;
2096 qcom,proxy-timeout-ms = <10000>;
2097 qcom,smem-id = <422>;
2098 qcom,sysmon-id = <6>;
2099 qcom,ssctl-instance-id = <0x13>;
2100 qcom,firmware-name = "wcnss";
2101
Jitendra Sharma1b581f72018-02-23 17:10:12 +05302102 /* GPIO inputs from wcnss */
2103 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
2104 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;
2105 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
2106 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_4_in 3 0>;
2107
2108 /* GPIO output to wcnss */
2109 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
Jitendra Sharmaa50d8082017-11-10 14:33:32 +05302110 memory-region = <&wcnss_fw_mem>;
2111 };
2112
Tingwei Zhang63c1b7d2017-12-22 16:38:16 +08002113 qcom,venus@1de0000 {
2114 compatible = "qcom,pil-tz-generic";
2115 reg = <0x1de0000 0x4000>;
2116
2117 vdd-supply = <&gdsc_venus>;
2118 qcom,proxy-reg-names = "vdd";
Tingwei Zhang7f3d05b2018-01-18 21:08:07 +08002119 qcom,mas-crypto = <&mas_crypto>;
Tingwei Zhang63c1b7d2017-12-22 16:38:16 +08002120
2121 clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>,
2122 <&clock_gcc clk_gcc_venus0_ahb_clk>,
2123 <&clock_gcc clk_gcc_venus0_axi_clk>,
2124 <&clock_gcc clk_gcc_crypto_clk>,
2125 <&clock_gcc clk_gcc_crypto_ahb_clk>,
2126 <&clock_gcc clk_gcc_crypto_axi_clk>,
2127 <&clock_gcc clk_crypto_clk_src>;
2128
2129 clock-names = "core_clk", "iface_clk", "bus_clk",
2130 "scm_core_clk", "scm_iface_clk",
2131 "scm_bus_clk", "scm_core_clk_src";
2132
2133 qcom,proxy-clock-names = "core_clk", "iface_clk",
2134 "bus_clk", "scm_core_clk",
2135 "scm_iface_clk", "scm_bus_clk",
2136 "scm_core_clk_src";
2137 qcom,scm_core_clk_src-freq = <80000000>;
2138
2139 qcom,msm-bus,name = "pil-venus";
2140 qcom,msm-bus,num-cases = <2>;
2141 qcom,msm-bus,num-paths = <1>;
2142 qcom,msm-bus,vectors-KBps =
2143 <63 512 0 0>,
2144 <63 512 0 304000>;
2145 qcom,pas-id = <9>;
2146 qcom,proxy-timeout-ms = <100>;
2147 qcom,firmware-name = "venus";
2148 memory-region = <&venus_mem>;
2149 };
Anurag Chouhan0c6dba82018-01-08 15:20:30 +05302150
2151 qcom,wcnss-wlan@0a000000 {
2152 compatible = "qcom,wcnss_wlan";
2153 reg = <0x0a000000 0x280000>,
2154 <0x0b011008 0x04>,
2155 <0x0a21b000 0x3000>,
2156 <0x03204000 0x00000100>,
2157 <0x03200800 0x00000200>,
2158 <0x0a100400 0x00000200>,
2159 <0x0a205050 0x00000200>,
2160 <0x0a219000 0x00000020>,
2161 <0x0a080488 0x00000008>,
2162 <0x0a080fb0 0x00000008>,
2163 <0x0a08040c 0x00000008>,
2164 <0x0a0120a8 0x00000008>,
2165 <0x0a012448 0x00000008>,
2166 <0x0a080c00 0x00000001>;
2167
2168 reg-names = "wcnss_mmio", "wcnss_fiq",
2169 "pronto_phy_base", "riva_phy_base",
2170 "riva_ccu_base", "pronto_a2xb_base",
2171 "pronto_ccpu_base", "pronto_saw2_base",
2172 "wlan_tx_phy_aborts","wlan_brdg_err_source",
2173 "wlan_tx_status", "alarms_txctl",
2174 "alarms_tactl", "pronto_mcu_base";
2175
2176 interrupts = <0 145 0 0 146 0>;
2177 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
2178
2179 qcom,pronto-vddmx-supply = <&pm8953_s7_level_ao>;
2180 qcom,pronto-vddcx-supply = <&pm8953_s2_level>;
2181 qcom,pronto-vddpx-supply = <&pm8953_l5>;
2182 qcom,iris-vddxo-supply = <&pm8953_l7>;
2183 qcom,iris-vddrfa-supply = <&pm8953_l19>;
2184 qcom,iris-vddpa-supply = <&pm8953_l9>;
2185 qcom,iris-vdddig-supply = <&pm8953_l5>;
2186
2187 qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
2188 qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>;
2189 qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
2190 qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;
2191
2192 qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO
2193 RPM_SMD_REGULATOR_LEVEL_NONE
2194 RPM_SMD_REGULATOR_LEVEL_TURBO>;
2195 qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM
2196 RPM_SMD_REGULATOR_LEVEL_NONE
2197 RPM_SMD_REGULATOR_LEVEL_TURBO>;
2198 qcom,vddpx-voltage-level = <1800000 0 1800000>;
2199
2200 qcom,iris-vddxo-current = <10000>;
2201 qcom,iris-vddrfa-current = <100000>;
2202 qcom,iris-vddpa-current = <515000>;
2203 qcom,iris-vdddig-current = <10000>;
2204
2205 qcom,pronto-vddmx-current = <0>;
2206 qcom,pronto-vddcx-current = <0>;
2207 qcom,pronto-vddpx-current = <0>;
2208
2209 pinctrl-names = "wcnss_default", "wcnss_sleep",
2210 "wcnss_gpio_default";
2211 pinctrl-0 = <&wcnss_default>;
2212 pinctrl-1 = <&wcnss_sleep>;
2213 pinctrl-2 = <&wcnss_gpio_default>;
2214
2215 gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>,
2216 <&tlmm 79 0>, <&tlmm 80 0>;
2217
2218 clocks = <&clock_gcc clk_xo_wlan_clk>,
2219 <&clock_gcc clk_rf_clk2>,
2220 <&clock_debug clk_gcc_debug_mux>,
2221 <&clock_gcc clk_wcnss_m_clk>;
2222
2223 clock-names = "xo", "rf_clk", "measure", "wcnss_debug";
2224
2225 qcom,has-autodetect-xo;
2226 qcom,is-pronto-v3;
2227 qcom,has-pronto-hw;
2228 qcom,has-vsys-adc-channel;
2229 qcom,has-a2xb-split-reg;
2230 qcom,wcnss-adc_tm = <&pm8953_adc_tm>;
2231 };
2232
Shaikh Shadulf38749c2018-02-09 18:06:28 +05302233 ssc_sensors: qcom,msm-ssc-sensors {
2234 compatible = "qcom,msm-ssc-sensors";
2235 status = "ok";
2236 };
2237
Srinivas Ramana3cac2782017-09-13 16:31:17 +05302238};
Kiran Gunda0954f392017-10-16 16:24:55 +05302239
2240#include "pm8953-rpm-regulator.dtsi"
2241#include "pm8953.dtsi"
2242#include "msm8953-regulator.dtsi"
Shefali Jain44e24ad2017-11-23 12:27:33 +05302243#include "msm-gdsc-8916.dtsi"
Manaf Meethalavalappu Pallikunhi4eb2b272018-01-02 17:29:37 +05302244#include "msm8953-thermal.dtsi"
Pratap Nirujogi6e759912018-01-17 17:51:17 +05302245#include "msm8953-camera.dtsi"
Soumya Managoli91ec9502018-01-18 16:53:47 +05302246#include "msm8953-audio.dtsi"
Shefali Jain44e24ad2017-11-23 12:27:33 +05302247
2248&gdsc_venus {
2249 clock-names = "bus_clk", "core_clk";
2250 clocks = <&clock_gcc clk_gcc_venus0_axi_clk>,
2251 <&clock_gcc clk_gcc_venus0_vcodec0_clk>;
2252 status = "okay";
2253};
2254
2255&gdsc_venus_core0 {
2256 qcom,support-hw-trigger;
2257 clock-names ="core0_clk";
2258 clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>;
2259 status = "okay";
2260};
2261
2262&gdsc_mdss {
2263 clock-names = "core_clk", "bus_clk";
2264 clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
2265 <&clock_gcc clk_gcc_mdss_axi_clk>;
2266 proxy-supply = <&gdsc_mdss>;
2267 qcom,proxy-consumer-enable;
2268 status = "okay";
2269};
2270
2271&gdsc_oxili_gx {
2272 clock-names = "core_root_clk";
2273 clocks =<&clock_gcc_gfx clk_gfx3d_clk_src>;
2274 qcom,force-enable-root-clk;
2275 parent-supply = <&gfx_vreg_corner>;
2276 status = "okay";
2277};
2278
2279&gdsc_jpeg {
2280 clock-names = "core_clk", "bus_clk";
2281 clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,
2282 <&clock_gcc clk_gcc_camss_jpeg_axi_clk>;
2283 status = "okay";
2284};
2285
2286&gdsc_vfe {
2287 clock-names = "core_clk", "bus_clk", "micro_clk",
2288 "csi_clk";
2289 clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>,
2290 <&clock_gcc clk_gcc_camss_vfe_axi_clk>,
2291 <&clock_gcc clk_gcc_camss_micro_ahb_clk>,
2292 <&clock_gcc clk_gcc_camss_csi_vfe0_clk>;
2293 status = "okay";
2294};
2295
2296&gdsc_vfe1 {
2297 clock-names = "core_clk", "bus_clk", "micro_clk",
2298 "csi_clk";
2299 clocks = <&clock_gcc clk_gcc_camss_vfe1_clk>,
2300 <&clock_gcc clk_gcc_camss_vfe1_axi_clk>,
2301 <&clock_gcc clk_gcc_camss_micro_ahb_clk>,
2302 <&clock_gcc clk_gcc_camss_csi_vfe1_clk>;
2303 status = "okay";
2304};
2305
2306&gdsc_cpp {
2307 clock-names = "core_clk", "bus_clk";
2308 clocks = <&clock_gcc clk_gcc_camss_cpp_clk>,
2309 <&clock_gcc clk_gcc_camss_cpp_axi_clk>;
2310 status = "okay";
2311};
2312
2313&gdsc_oxili_cx {
2314 clock-names = "core_clk";
2315 clocks = <&clock_gcc_gfx clk_gcc_oxili_gfx3d_clk>;
2316 status = "okay";
2317};
2318
2319&gdsc_usb30 {
2320 status = "okay";
2321};