Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dss.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * Some code and ideas taken from drivers/video/omap/ driver |
| 8 | * by Imre Deak. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License version 2 as published by |
| 12 | * the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 17 | * more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along with |
| 20 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #define DSS_SUBSYS_NAME "DSS" |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/io.h> |
Paul Gortmaker | a8a3593 | 2011-07-10 13:20:26 -0400 | [diff] [blame] | 27 | #include <linux/export.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 28 | #include <linux/err.h> |
| 29 | #include <linux/delay.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 30 | #include <linux/seq_file.h> |
| 31 | #include <linux/clk.h> |
Tomi Valkeinen | 24e6289 | 2011-05-23 11:51:18 +0300 | [diff] [blame] | 32 | #include <linux/platform_device.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 33 | #include <linux/pm_runtime.h> |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 34 | #include <linux/gfp.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 35 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 36 | #include <video/omapdss.h> |
Tony Lindgren | 2c799ce | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 37 | |
| 38 | #include <plat/cpu.h> |
Tony Lindgren | 2c799ce | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 39 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 40 | #include "dss.h" |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 41 | #include "dss_features.h" |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 42 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 43 | #define DSS_SZ_REGS SZ_512 |
| 44 | |
| 45 | struct dss_reg { |
| 46 | u16 idx; |
| 47 | }; |
| 48 | |
| 49 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) |
| 50 | |
| 51 | #define DSS_REVISION DSS_REG(0x0000) |
| 52 | #define DSS_SYSCONFIG DSS_REG(0x0010) |
| 53 | #define DSS_SYSSTATUS DSS_REG(0x0014) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 54 | #define DSS_CONTROL DSS_REG(0x0040) |
| 55 | #define DSS_SDI_CONTROL DSS_REG(0x0044) |
| 56 | #define DSS_PLL_CONTROL DSS_REG(0x0048) |
| 57 | #define DSS_SDI_STATUS DSS_REG(0x005C) |
| 58 | |
| 59 | #define REG_GET(idx, start, end) \ |
| 60 | FLD_GET(dss_read_reg(idx), start, end) |
| 61 | |
| 62 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 63 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) |
| 64 | |
Tomi Valkeinen | 852f083 | 2012-02-17 17:58:04 +0200 | [diff] [blame] | 65 | static int dss_runtime_get(void); |
| 66 | static void dss_runtime_put(void); |
| 67 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 68 | struct dss_features { |
| 69 | u8 fck_div_max; |
| 70 | u8 dss_fck_multiplier; |
| 71 | const char *clk_name; |
| 72 | }; |
| 73 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 74 | static struct { |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 75 | struct platform_device *pdev; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 76 | void __iomem *base; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 77 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 78 | struct clk *dpll4_m4_ck; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 79 | struct clk *dss_clk; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 80 | |
| 81 | unsigned long cache_req_pck; |
| 82 | unsigned long cache_prate; |
| 83 | struct dss_clock_info cache_dss_cinfo; |
| 84 | struct dispc_clock_info cache_dispc_cinfo; |
| 85 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 86 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 87 | enum omap_dss_clk_source dispc_clk_source; |
| 88 | enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 89 | |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 90 | bool ctx_valid; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 91 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 92 | |
| 93 | const struct dss_features *feat; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 94 | } dss; |
| 95 | |
Taneja, Archit | 235e7db | 2011-03-14 23:28:21 -0500 | [diff] [blame] | 96 | static const char * const dss_generic_clk_source_names[] = { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 97 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", |
| 98 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", |
| 99 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 100 | }; |
| 101 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 102 | static const struct dss_features omap24xx_dss_feats __initconst = { |
| 103 | .fck_div_max = 16, |
| 104 | .dss_fck_multiplier = 2, |
| 105 | .clk_name = NULL, |
| 106 | }; |
| 107 | |
| 108 | static const struct dss_features omap34xx_dss_feats __initconst = { |
| 109 | .fck_div_max = 16, |
| 110 | .dss_fck_multiplier = 2, |
| 111 | .clk_name = "dpll4_m4_ck", |
| 112 | }; |
| 113 | |
| 114 | static const struct dss_features omap3630_dss_feats __initconst = { |
| 115 | .fck_div_max = 32, |
| 116 | .dss_fck_multiplier = 1, |
| 117 | .clk_name = "dpll4_m4_ck", |
| 118 | }; |
| 119 | |
| 120 | static const struct dss_features omap44xx_dss_feats __initconst = { |
| 121 | .fck_div_max = 32, |
| 122 | .dss_fck_multiplier = 1, |
| 123 | .clk_name = "dpll_per_m5x2_ck", |
| 124 | }; |
| 125 | |
Archit Taneja | 2336283 | 2012-04-08 16:47:01 +0530 | [diff] [blame^] | 126 | static const struct dss_features omap54xx_dss_feats __initconst = { |
| 127 | .fck_div_max = 64, |
| 128 | .dss_fck_multiplier = 1, |
| 129 | .clk_name = "dpll_per_h12x2_ck", |
| 130 | }; |
| 131 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 132 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
| 133 | { |
| 134 | __raw_writel(val, dss.base + idx.idx); |
| 135 | } |
| 136 | |
| 137 | static inline u32 dss_read_reg(const struct dss_reg idx) |
| 138 | { |
| 139 | return __raw_readl(dss.base + idx.idx); |
| 140 | } |
| 141 | |
| 142 | #define SR(reg) \ |
| 143 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) |
| 144 | #define RR(reg) \ |
| 145 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) |
| 146 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 147 | static void dss_save_context(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 148 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 149 | DSSDBG("dss_save_context\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 150 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 151 | SR(CONTROL); |
| 152 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 153 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 154 | OMAP_DISPLAY_TYPE_SDI) { |
| 155 | SR(SDI_CONTROL); |
| 156 | SR(PLL_CONTROL); |
| 157 | } |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 158 | |
| 159 | dss.ctx_valid = true; |
| 160 | |
| 161 | DSSDBG("context saved\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 162 | } |
| 163 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 164 | static void dss_restore_context(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 165 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 166 | DSSDBG("dss_restore_context\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 167 | |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 168 | if (!dss.ctx_valid) |
| 169 | return; |
| 170 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 171 | RR(CONTROL); |
| 172 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 173 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 174 | OMAP_DISPLAY_TYPE_SDI) { |
| 175 | RR(SDI_CONTROL); |
| 176 | RR(PLL_CONTROL); |
| 177 | } |
Tomi Valkeinen | 69f0605 | 2011-06-01 15:56:39 +0300 | [diff] [blame] | 178 | |
| 179 | DSSDBG("context restored\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | #undef SR |
| 183 | #undef RR |
| 184 | |
Archit Taneja | 889b4fd | 2012-07-20 17:18:49 +0530 | [diff] [blame] | 185 | void dss_sdi_init(int datapairs) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 186 | { |
| 187 | u32 l; |
| 188 | |
| 189 | BUG_ON(datapairs > 3 || datapairs < 1); |
| 190 | |
| 191 | l = dss_read_reg(DSS_SDI_CONTROL); |
| 192 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ |
| 193 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ |
| 194 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ |
| 195 | dss_write_reg(DSS_SDI_CONTROL, l); |
| 196 | |
| 197 | l = dss_read_reg(DSS_PLL_CONTROL); |
| 198 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ |
| 199 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ |
| 200 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ |
| 201 | dss_write_reg(DSS_PLL_CONTROL, l); |
| 202 | } |
| 203 | |
| 204 | int dss_sdi_enable(void) |
| 205 | { |
| 206 | unsigned long timeout; |
| 207 | |
| 208 | dispc_pck_free_enable(1); |
| 209 | |
| 210 | /* Reset SDI PLL */ |
| 211 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ |
| 212 | udelay(1); /* wait 2x PCLK */ |
| 213 | |
| 214 | /* Lock SDI PLL */ |
| 215 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ |
| 216 | |
| 217 | /* Waiting for PLL lock request to complete */ |
| 218 | timeout = jiffies + msecs_to_jiffies(500); |
| 219 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { |
| 220 | if (time_after_eq(jiffies, timeout)) { |
| 221 | DSSERR("PLL lock request timed out\n"); |
| 222 | goto err1; |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | /* Clearing PLL_GO bit */ |
| 227 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); |
| 228 | |
| 229 | /* Waiting for PLL to lock */ |
| 230 | timeout = jiffies + msecs_to_jiffies(500); |
| 231 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { |
| 232 | if (time_after_eq(jiffies, timeout)) { |
| 233 | DSSERR("PLL lock timed out\n"); |
| 234 | goto err1; |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | dispc_lcd_enable_signal(1); |
| 239 | |
| 240 | /* Waiting for SDI reset to complete */ |
| 241 | timeout = jiffies + msecs_to_jiffies(500); |
| 242 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { |
| 243 | if (time_after_eq(jiffies, timeout)) { |
| 244 | DSSERR("SDI reset timed out\n"); |
| 245 | goto err2; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | return 0; |
| 250 | |
| 251 | err2: |
| 252 | dispc_lcd_enable_signal(0); |
| 253 | err1: |
| 254 | /* Reset SDI PLL */ |
| 255 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 256 | |
| 257 | dispc_pck_free_enable(0); |
| 258 | |
| 259 | return -ETIMEDOUT; |
| 260 | } |
| 261 | |
| 262 | void dss_sdi_disable(void) |
| 263 | { |
| 264 | dispc_lcd_enable_signal(0); |
| 265 | |
| 266 | dispc_pck_free_enable(0); |
| 267 | |
| 268 | /* Reset SDI PLL */ |
| 269 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 270 | } |
| 271 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 272 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 273 | { |
Taneja, Archit | 235e7db | 2011-03-14 23:28:21 -0500 | [diff] [blame] | 274 | return dss_generic_clk_source_names[clk_src]; |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 275 | } |
| 276 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 277 | void dss_dump_clocks(struct seq_file *s) |
| 278 | { |
| 279 | unsigned long dpll4_ck_rate; |
| 280 | unsigned long dpll4_m4_ck_rate; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 281 | const char *fclk_name, *fclk_real_name; |
| 282 | unsigned long fclk_rate; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 283 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 284 | if (dss_runtime_get()) |
| 285 | return; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 286 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 287 | seq_printf(s, "- DSS -\n"); |
| 288 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 289 | fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
| 290 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 291 | fclk_rate = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 292 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 293 | if (dss.dpll4_m4_ck) { |
| 294 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 295 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); |
| 296 | |
| 297 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); |
| 298 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 299 | seq_printf(s, "%s (%s) = %lu / %lu * %d = %lu\n", |
| 300 | fclk_name, fclk_real_name, dpll4_ck_rate, |
| 301 | dpll4_ck_rate / dpll4_m4_ck_rate, |
| 302 | dss.feat->dss_fck_multiplier, fclk_rate); |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 303 | } else { |
| 304 | seq_printf(s, "%s (%s) = %lu\n", |
| 305 | fclk_name, fclk_real_name, |
| 306 | fclk_rate); |
| 307 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 308 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 309 | dss_runtime_put(); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 310 | } |
| 311 | |
Tomi Valkeinen | e40402c | 2012-03-02 18:01:07 +0200 | [diff] [blame] | 312 | static void dss_dump_regs(struct seq_file *s) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 313 | { |
| 314 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) |
| 315 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 316 | if (dss_runtime_get()) |
| 317 | return; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 318 | |
| 319 | DUMPREG(DSS_REVISION); |
| 320 | DUMPREG(DSS_SYSCONFIG); |
| 321 | DUMPREG(DSS_SYSSTATUS); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 322 | DUMPREG(DSS_CONTROL); |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 323 | |
| 324 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 325 | OMAP_DISPLAY_TYPE_SDI) { |
| 326 | DUMPREG(DSS_SDI_CONTROL); |
| 327 | DUMPREG(DSS_PLL_CONTROL); |
| 328 | DUMPREG(DSS_SDI_STATUS); |
| 329 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 330 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 331 | dss_runtime_put(); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 332 | #undef DUMPREG |
| 333 | } |
| 334 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 335 | void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 336 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 337 | struct platform_device *dsidev; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 338 | int b; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 339 | u8 start, end; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 340 | |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 341 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 342 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 343 | b = 0; |
| 344 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 345 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 346 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 347 | dsidev = dsi_get_dsidev_from_id(0); |
| 348 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 349 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 350 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
| 351 | b = 2; |
| 352 | dsidev = dsi_get_dsidev_from_id(1); |
| 353 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
| 354 | break; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 355 | default: |
| 356 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 357 | return; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 358 | } |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 359 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 360 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
| 361 | |
| 362 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 363 | |
| 364 | dss.dispc_clk_source = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 365 | } |
| 366 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 367 | void dss_select_dsi_clk_source(int dsi_module, |
| 368 | enum omap_dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 369 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 370 | struct platform_device *dsidev; |
Archit Taneja | a2e5d82 | 2012-05-07 16:51:35 +0530 | [diff] [blame] | 371 | int b, pos; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 372 | |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 373 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 374 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 375 | b = 0; |
| 376 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 377 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 378 | BUG_ON(dsi_module != 0); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 379 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 380 | dsidev = dsi_get_dsidev_from_id(0); |
| 381 | dsi_wait_pll_hsdiv_dsi_active(dsidev); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 382 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 383 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: |
| 384 | BUG_ON(dsi_module != 1); |
| 385 | b = 1; |
| 386 | dsidev = dsi_get_dsidev_from_id(1); |
| 387 | dsi_wait_pll_hsdiv_dsi_active(dsidev); |
| 388 | break; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 389 | default: |
| 390 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 391 | return; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 392 | } |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 393 | |
Archit Taneja | a2e5d82 | 2012-05-07 16:51:35 +0530 | [diff] [blame] | 394 | pos = dsi_module == 0 ? 1 : 10; |
| 395 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 396 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 397 | dss.dsi_clk_source[dsi_module] = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 398 | } |
| 399 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 400 | void dss_select_lcd_clk_source(enum omap_channel channel, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 401 | enum omap_dss_clk_source clk_src) |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 402 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 403 | struct platform_device *dsidev; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 404 | int b, ix, pos; |
| 405 | |
| 406 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) |
| 407 | return; |
| 408 | |
| 409 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 410 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 411 | b = 0; |
| 412 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 413 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 414 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
| 415 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 416 | dsidev = dsi_get_dsidev_from_id(0); |
| 417 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 418 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 419 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
Chandrabhanu Mahapatra | e86d456 | 2012-06-29 10:43:13 +0530 | [diff] [blame] | 420 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 && |
| 421 | channel != OMAP_DSS_CHANNEL_LCD3); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 422 | b = 1; |
| 423 | dsidev = dsi_get_dsidev_from_id(1); |
| 424 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
| 425 | break; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 426 | default: |
| 427 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 428 | return; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 429 | } |
| 430 | |
Chandrabhanu Mahapatra | e86d456 | 2012-06-29 10:43:13 +0530 | [diff] [blame] | 431 | pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : |
| 432 | (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19); |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 433 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ |
| 434 | |
Chandrabhanu Mahapatra | e86d456 | 2012-06-29 10:43:13 +0530 | [diff] [blame] | 435 | ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : |
| 436 | (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2); |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 437 | dss.lcd_clk_source[ix] = clk_src; |
| 438 | } |
| 439 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 440 | enum omap_dss_clk_source dss_get_dispc_clk_source(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 441 | { |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 442 | return dss.dispc_clk_source; |
| 443 | } |
| 444 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 445 | enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module) |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 446 | { |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 447 | return dss.dsi_clk_source[dsi_module]; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 448 | } |
| 449 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 450 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 451 | { |
Archit Taneja | 89976f2 | 2011-03-31 13:23:35 +0530 | [diff] [blame] | 452 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
Chandrabhanu Mahapatra | e86d456 | 2012-06-29 10:43:13 +0530 | [diff] [blame] | 453 | int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : |
| 454 | (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2); |
Archit Taneja | 89976f2 | 2011-03-31 13:23:35 +0530 | [diff] [blame] | 455 | return dss.lcd_clk_source[ix]; |
| 456 | } else { |
| 457 | /* LCD_CLK source is the same as DISPC_FCLK source for |
| 458 | * OMAP2 and OMAP3 */ |
| 459 | return dss.dispc_clk_source; |
| 460 | } |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 461 | } |
| 462 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 463 | int dss_set_clock_div(struct dss_clock_info *cinfo) |
| 464 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 465 | if (dss.dpll4_m4_ck) { |
| 466 | unsigned long prate; |
| 467 | int r; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 468 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 469 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 470 | DSSDBG("dpll4_m4 = %ld\n", prate); |
| 471 | |
| 472 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); |
| 473 | if (r) |
| 474 | return r; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 475 | } else { |
| 476 | if (cinfo->fck_div != 0) |
| 477 | return -EINVAL; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 478 | } |
| 479 | |
| 480 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); |
| 481 | |
| 482 | return 0; |
| 483 | } |
| 484 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 485 | unsigned long dss_get_dpll4_rate(void) |
| 486 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 487 | if (dss.dpll4_m4_ck) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 488 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 489 | else |
| 490 | return 0; |
| 491 | } |
| 492 | |
Archit Taneja | 6d523e7 | 2012-06-21 09:33:55 +0530 | [diff] [blame] | 493 | int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo, |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 494 | struct dispc_clock_info *dispc_cinfo) |
| 495 | { |
| 496 | unsigned long prate; |
| 497 | struct dss_clock_info best_dss; |
| 498 | struct dispc_clock_info best_dispc; |
| 499 | |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 500 | unsigned long fck, max_dss_fck; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 501 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 502 | u16 fck_div; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 503 | |
| 504 | int match = 0; |
| 505 | int min_fck_per_pck; |
| 506 | |
| 507 | prate = dss_get_dpll4_rate(); |
| 508 | |
Taneja, Archit | 31ef823 | 2011-03-14 23:28:22 -0500 | [diff] [blame] | 509 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 510 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 511 | fck = clk_get_rate(dss.dss_clk); |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 512 | if (req_pck == dss.cache_req_pck && prate == dss.cache_prate && |
| 513 | dss.cache_dss_cinfo.fck == fck) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 514 | DSSDBG("dispc clock info found from cache.\n"); |
| 515 | *dss_cinfo = dss.cache_dss_cinfo; |
| 516 | *dispc_cinfo = dss.cache_dispc_cinfo; |
| 517 | return 0; |
| 518 | } |
| 519 | |
| 520 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 521 | |
| 522 | if (min_fck_per_pck && |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 523 | req_pck * min_fck_per_pck > max_dss_fck) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 524 | DSSERR("Requested pixel clock not possible with the current " |
| 525 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 526 | "the constraint off.\n"); |
| 527 | min_fck_per_pck = 0; |
| 528 | } |
| 529 | |
| 530 | retry: |
| 531 | memset(&best_dss, 0, sizeof(best_dss)); |
| 532 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 533 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 534 | if (dss.dpll4_m4_ck == NULL) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 535 | struct dispc_clock_info cur_dispc; |
| 536 | /* XXX can we change the clock on omap2? */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 537 | fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 538 | fck_div = 1; |
| 539 | |
Archit Taneja | 6d523e7 | 2012-06-21 09:33:55 +0530 | [diff] [blame] | 540 | dispc_find_clk_divs(req_pck, fck, &cur_dispc); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 541 | match = 1; |
| 542 | |
| 543 | best_dss.fck = fck; |
| 544 | best_dss.fck_div = fck_div; |
| 545 | |
| 546 | best_dispc = cur_dispc; |
| 547 | |
| 548 | goto found; |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 549 | } else { |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 550 | for (fck_div = dss.feat->fck_div_max; fck_div > 0; --fck_div) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 551 | struct dispc_clock_info cur_dispc; |
| 552 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 553 | fck = prate / fck_div * dss.feat->dss_fck_multiplier; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 554 | |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 555 | if (fck > max_dss_fck) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 556 | continue; |
| 557 | |
| 558 | if (min_fck_per_pck && |
| 559 | fck < req_pck * min_fck_per_pck) |
| 560 | continue; |
| 561 | |
| 562 | match = 1; |
| 563 | |
Archit Taneja | 6d523e7 | 2012-06-21 09:33:55 +0530 | [diff] [blame] | 564 | dispc_find_clk_divs(req_pck, fck, &cur_dispc); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 565 | |
| 566 | if (abs(cur_dispc.pck - req_pck) < |
| 567 | abs(best_dispc.pck - req_pck)) { |
| 568 | |
| 569 | best_dss.fck = fck; |
| 570 | best_dss.fck_div = fck_div; |
| 571 | |
| 572 | best_dispc = cur_dispc; |
| 573 | |
| 574 | if (cur_dispc.pck == req_pck) |
| 575 | goto found; |
| 576 | } |
| 577 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | found: |
| 581 | if (!match) { |
| 582 | if (min_fck_per_pck) { |
| 583 | DSSERR("Could not find suitable clock settings.\n" |
| 584 | "Turning FCK/PCK constraint off and" |
| 585 | "trying again.\n"); |
| 586 | min_fck_per_pck = 0; |
| 587 | goto retry; |
| 588 | } |
| 589 | |
| 590 | DSSERR("Could not find suitable clock settings.\n"); |
| 591 | |
| 592 | return -EINVAL; |
| 593 | } |
| 594 | |
| 595 | if (dss_cinfo) |
| 596 | *dss_cinfo = best_dss; |
| 597 | if (dispc_cinfo) |
| 598 | *dispc_cinfo = best_dispc; |
| 599 | |
| 600 | dss.cache_req_pck = req_pck; |
| 601 | dss.cache_prate = prate; |
| 602 | dss.cache_dss_cinfo = best_dss; |
| 603 | dss.cache_dispc_cinfo = best_dispc; |
| 604 | |
| 605 | return 0; |
| 606 | } |
| 607 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 608 | void dss_set_venc_output(enum omap_dss_venc_type type) |
| 609 | { |
| 610 | int l = 0; |
| 611 | |
| 612 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) |
| 613 | l = 0; |
| 614 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) |
| 615 | l = 1; |
| 616 | else |
| 617 | BUG(); |
| 618 | |
| 619 | /* venc out selection. 0 = comp, 1 = svideo */ |
| 620 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); |
| 621 | } |
| 622 | |
| 623 | void dss_set_dac_pwrdn_bgz(bool enable) |
| 624 | { |
| 625 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ |
| 626 | } |
| 627 | |
Ricardo Neri | 8aa2eed | 2012-08-01 07:56:40 -0500 | [diff] [blame] | 628 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) |
Mythri P K | 7ed024a | 2011-03-09 16:31:38 +0530 | [diff] [blame] | 629 | { |
Ricardo Neri | 8aa2eed | 2012-08-01 07:56:40 -0500 | [diff] [blame] | 630 | enum omap_display_type dp; |
| 631 | dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); |
| 632 | |
| 633 | /* Complain about invalid selections */ |
| 634 | WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC)); |
| 635 | WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI)); |
| 636 | |
| 637 | /* Select only if we have options */ |
| 638 | if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI)) |
| 639 | REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ |
Mythri P K | 7ed024a | 2011-03-09 16:31:38 +0530 | [diff] [blame] | 640 | } |
| 641 | |
Tomi Valkeinen | 4a61e26 | 2011-08-31 14:33:31 +0300 | [diff] [blame] | 642 | enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) |
| 643 | { |
| 644 | enum omap_display_type displays; |
| 645 | |
| 646 | displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); |
| 647 | if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) |
| 648 | return DSS_VENC_TV_CLK; |
| 649 | |
Ricardo Neri | 8aa2eed | 2012-08-01 07:56:40 -0500 | [diff] [blame] | 650 | if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0) |
| 651 | return DSS_HDMI_M_PCLK; |
| 652 | |
Tomi Valkeinen | 4a61e26 | 2011-08-31 14:33:31 +0300 | [diff] [blame] | 653 | return REG_GET(DSS_CONTROL, 15, 15); |
| 654 | } |
| 655 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 656 | static int dss_get_clocks(void) |
| 657 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 658 | struct clk *clk; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 659 | int r; |
| 660 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 661 | clk = clk_get(&dss.pdev->dev, "fck"); |
| 662 | if (IS_ERR(clk)) { |
| 663 | DSSERR("can't get clock fck\n"); |
| 664 | r = PTR_ERR(clk); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 665 | goto err; |
Semwal, Sumit | a1a0dcc | 2011-03-01 02:42:14 -0600 | [diff] [blame] | 666 | } |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 667 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 668 | dss.dss_clk = clk; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 669 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 670 | clk = clk_get(NULL, dss.feat->clk_name); |
| 671 | if (IS_ERR(clk)) { |
| 672 | DSSERR("Failed to get %s\n", dss.feat->clk_name); |
| 673 | r = PTR_ERR(clk); |
| 674 | goto err; |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 675 | } |
| 676 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 677 | dss.dpll4_m4_ck = clk; |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 678 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 679 | return 0; |
| 680 | |
| 681 | err: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 682 | if (dss.dss_clk) |
| 683 | clk_put(dss.dss_clk); |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 684 | if (dss.dpll4_m4_ck) |
| 685 | clk_put(dss.dpll4_m4_ck); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 686 | |
| 687 | return r; |
| 688 | } |
| 689 | |
| 690 | static void dss_put_clocks(void) |
| 691 | { |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 692 | if (dss.dpll4_m4_ck) |
| 693 | clk_put(dss.dpll4_m4_ck); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 694 | clk_put(dss.dss_clk); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 695 | } |
| 696 | |
Tomi Valkeinen | 852f083 | 2012-02-17 17:58:04 +0200 | [diff] [blame] | 697 | static int dss_runtime_get(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 698 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 699 | int r; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 700 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 701 | DSSDBG("dss_runtime_get\n"); |
| 702 | |
| 703 | r = pm_runtime_get_sync(&dss.pdev->dev); |
| 704 | WARN_ON(r < 0); |
| 705 | return r < 0 ? r : 0; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 706 | } |
| 707 | |
Tomi Valkeinen | 852f083 | 2012-02-17 17:58:04 +0200 | [diff] [blame] | 708 | static void dss_runtime_put(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 709 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 710 | int r; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 711 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 712 | DSSDBG("dss_runtime_put\n"); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 713 | |
Tomi Valkeinen | 0eaf9f5 | 2012-01-23 13:23:08 +0200 | [diff] [blame] | 714 | r = pm_runtime_put_sync(&dss.pdev->dev); |
Tomi Valkeinen | 5be3aeb | 2012-06-27 16:37:18 +0300 | [diff] [blame] | 715 | WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 716 | } |
| 717 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 718 | /* DEBUGFS */ |
| 719 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) |
| 720 | void dss_debug_dump_clocks(struct seq_file *s) |
| 721 | { |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 722 | dss_dump_clocks(s); |
| 723 | dispc_dump_clocks(s); |
| 724 | #ifdef CONFIG_OMAP2_DSS_DSI |
| 725 | dsi_dump_clocks(s); |
| 726 | #endif |
| 727 | } |
| 728 | #endif |
| 729 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 730 | static int __init dss_init_features(struct device *dev) |
| 731 | { |
| 732 | const struct dss_features *src; |
| 733 | struct dss_features *dst; |
| 734 | |
| 735 | dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL); |
| 736 | if (!dst) { |
| 737 | dev_err(dev, "Failed to allocate local DSS Features\n"); |
| 738 | return -ENOMEM; |
| 739 | } |
| 740 | |
| 741 | if (cpu_is_omap24xx()) |
| 742 | src = &omap24xx_dss_feats; |
| 743 | else if (cpu_is_omap34xx()) |
| 744 | src = &omap34xx_dss_feats; |
| 745 | else if (cpu_is_omap3630()) |
| 746 | src = &omap3630_dss_feats; |
| 747 | else if (cpu_is_omap44xx()) |
| 748 | src = &omap44xx_dss_feats; |
Archit Taneja | 2336283 | 2012-04-08 16:47:01 +0530 | [diff] [blame^] | 749 | else if (soc_is_omap54xx()) |
| 750 | src = &omap54xx_dss_feats; |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 751 | else |
| 752 | return -ENODEV; |
| 753 | |
| 754 | memcpy(dst, src, sizeof(*dst)); |
| 755 | dss.feat = dst; |
| 756 | |
| 757 | return 0; |
| 758 | } |
| 759 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 760 | /* DSS HW IP initialisation */ |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 761 | static int __init omap_dsshw_probe(struct platform_device *pdev) |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 762 | { |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 763 | struct resource *dss_mem; |
| 764 | u32 rev; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 765 | int r; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 766 | |
| 767 | dss.pdev = pdev; |
| 768 | |
Chandrabhanu Mahapatra | 185bae1 | 2012-07-11 18:36:18 +0530 | [diff] [blame] | 769 | r = dss_init_features(&dss.pdev->dev); |
| 770 | if (r) |
| 771 | return r; |
| 772 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 773 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
| 774 | if (!dss_mem) { |
| 775 | DSSERR("can't get IORESOURCE_MEM DSS\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 776 | return -EINVAL; |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 777 | } |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 778 | |
Julia Lawall | 6e2a14d | 2012-01-24 14:00:45 +0100 | [diff] [blame] | 779 | dss.base = devm_ioremap(&pdev->dev, dss_mem->start, |
| 780 | resource_size(dss_mem)); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 781 | if (!dss.base) { |
| 782 | DSSERR("can't ioremap DSS\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 783 | return -ENOMEM; |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 784 | } |
| 785 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 786 | r = dss_get_clocks(); |
| 787 | if (r) |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 788 | return r; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 789 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 790 | pm_runtime_enable(&pdev->dev); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 791 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 792 | r = dss_runtime_get(); |
| 793 | if (r) |
| 794 | goto err_runtime_get; |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 795 | |
| 796 | /* Select DPLL */ |
| 797 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); |
| 798 | |
| 799 | #ifdef CONFIG_OMAP2_DSS_VENC |
| 800 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ |
| 801 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ |
| 802 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ |
| 803 | #endif |
| 804 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
| 805 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
| 806 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; |
| 807 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
| 808 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 809 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 810 | rev = dss_read_reg(DSS_REVISION); |
| 811 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", |
| 812 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 813 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 814 | dss_runtime_put(); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 815 | |
Tomi Valkeinen | e40402c | 2012-03-02 18:01:07 +0200 | [diff] [blame] | 816 | dss_debugfs_create_file("dss", dss_dump_regs); |
| 817 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 818 | return 0; |
Tomi Valkeinen | a57dd4f | 2012-02-20 16:57:37 +0200 | [diff] [blame] | 819 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 820 | err_runtime_get: |
| 821 | pm_runtime_disable(&pdev->dev); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 822 | dss_put_clocks(); |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 823 | return r; |
| 824 | } |
| 825 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 826 | static int __exit omap_dsshw_remove(struct platform_device *pdev) |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 827 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 828 | pm_runtime_disable(&pdev->dev); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 829 | |
| 830 | dss_put_clocks(); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 831 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 832 | return 0; |
| 833 | } |
| 834 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 835 | static int dss_runtime_suspend(struct device *dev) |
| 836 | { |
| 837 | dss_save_context(); |
Tomi Valkeinen | a8081d3 | 2012-03-08 12:52:38 +0200 | [diff] [blame] | 838 | dss_set_min_bus_tput(dev, 0); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | static int dss_runtime_resume(struct device *dev) |
| 843 | { |
Tomi Valkeinen | a8081d3 | 2012-03-08 12:52:38 +0200 | [diff] [blame] | 844 | int r; |
| 845 | /* |
| 846 | * Set an arbitrarily high tput request to ensure OPP100. |
| 847 | * What we should really do is to make a request to stay in OPP100, |
| 848 | * without any tput requirements, but that is not currently possible |
| 849 | * via the PM layer. |
| 850 | */ |
| 851 | |
| 852 | r = dss_set_min_bus_tput(dev, 1000000000); |
| 853 | if (r) |
| 854 | return r; |
| 855 | |
Tomi Valkeinen | 3902071 | 2011-05-26 14:54:05 +0300 | [diff] [blame] | 856 | dss_restore_context(); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 857 | return 0; |
| 858 | } |
| 859 | |
| 860 | static const struct dev_pm_ops dss_pm_ops = { |
| 861 | .runtime_suspend = dss_runtime_suspend, |
| 862 | .runtime_resume = dss_runtime_resume, |
| 863 | }; |
| 864 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 865 | static struct platform_driver omap_dsshw_driver = { |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 866 | .remove = __exit_p(omap_dsshw_remove), |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 867 | .driver = { |
| 868 | .name = "omapdss_dss", |
| 869 | .owner = THIS_MODULE, |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 870 | .pm = &dss_pm_ops, |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 871 | }, |
| 872 | }; |
| 873 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 874 | int __init dss_init_platform_driver(void) |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 875 | { |
Tomi Valkeinen | 11436e1 | 2012-03-07 12:53:18 +0200 | [diff] [blame] | 876 | return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe); |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 877 | } |
| 878 | |
| 879 | void dss_uninit_platform_driver(void) |
| 880 | { |
Tomi Valkeinen | 04c742c | 2012-02-23 15:32:37 +0200 | [diff] [blame] | 881 | platform_driver_unregister(&omap_dsshw_driver); |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 882 | } |