Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 13 | #include "skeleton.dtsi" |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 14 | |
| 15 | / { |
| 16 | aliases { |
Shawn Guo | 5230f8f | 2012-08-05 14:01:28 +0800 | [diff] [blame] | 17 | gpio0 = &gpio1; |
| 18 | gpio1 = &gpio2; |
| 19 | gpio2 = &gpio3; |
| 20 | gpio3 = &gpio4; |
| 21 | gpio4 = &gpio5; |
| 22 | gpio5 = &gpio6; |
| 23 | gpio6 = &gpio7; |
Sascha Hauer | 80fa058 | 2013-06-25 15:51:57 +0200 | [diff] [blame] | 24 | i2c0 = &i2c1; |
| 25 | i2c1 = &i2c2; |
| 26 | i2c2 = &i2c3; |
| 27 | serial0 = &uart1; |
| 28 | serial1 = &uart2; |
| 29 | serial2 = &uart3; |
| 30 | serial3 = &uart4; |
| 31 | serial4 = &uart5; |
| 32 | spi0 = &ecspi1; |
| 33 | spi1 = &ecspi2; |
| 34 | spi2 = &ecspi3; |
| 35 | spi3 = &ecspi4; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 36 | }; |
| 37 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 38 | intc: interrupt-controller@00a01000 { |
| 39 | compatible = "arm,cortex-a9-gic"; |
| 40 | #interrupt-cells = <3>; |
| 41 | #address-cells = <1>; |
| 42 | #size-cells = <1>; |
| 43 | interrupt-controller; |
| 44 | reg = <0x00a01000 0x1000>, |
| 45 | <0x00a00100 0x100>; |
| 46 | }; |
| 47 | |
| 48 | clocks { |
| 49 | #address-cells = <1>; |
| 50 | #size-cells = <0>; |
| 51 | |
| 52 | ckil { |
| 53 | compatible = "fsl,imx-ckil", "fixed-clock"; |
| 54 | clock-frequency = <32768>; |
| 55 | }; |
| 56 | |
| 57 | ckih1 { |
| 58 | compatible = "fsl,imx-ckih1", "fixed-clock"; |
| 59 | clock-frequency = <0>; |
| 60 | }; |
| 61 | |
| 62 | osc { |
| 63 | compatible = "fsl,imx-osc", "fixed-clock"; |
| 64 | clock-frequency = <24000000>; |
| 65 | }; |
| 66 | }; |
| 67 | |
| 68 | soc { |
| 69 | #address-cells = <1>; |
| 70 | #size-cells = <1>; |
| 71 | compatible = "simple-bus"; |
| 72 | interrupt-parent = <&intc>; |
| 73 | ranges; |
| 74 | |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 75 | dma_apbh: dma-apbh@00110000 { |
Huang Shijie | e5d0f9f | 2012-06-06 21:22:57 -0400 | [diff] [blame] | 76 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 77 | reg = <0x00110000 0x2000>; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 78 | interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; |
| 79 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| 80 | #dma-cells = <1>; |
| 81 | dma-channels = <4>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 82 | clocks = <&clks 106>; |
Huang Shijie | e5d0f9f | 2012-06-06 21:22:57 -0400 | [diff] [blame] | 83 | }; |
| 84 | |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 85 | gpmi: gpmi-nand@00112000 { |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 86 | compatible = "fsl,imx6q-gpmi-nand"; |
| 87 | #address-cells = <1>; |
| 88 | #size-cells = <1>; |
| 89 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| 90 | reg-names = "gpmi-nand", "bch"; |
Shawn Guo | c7aa12a | 2013-07-16 17:13:00 +0800 | [diff] [blame] | 91 | interrupts = <0 15 0x04>; |
| 92 | interrupt-names = "bch"; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 93 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| 94 | <&clks 150>, <&clks 149>; |
| 95 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 96 | "gpmi_bch_apb", "per1_bch"; |
Shawn Guo | f30fb03 | 2013-02-25 21:56:56 +0800 | [diff] [blame] | 97 | dmas = <&dma_apbh 0>; |
| 98 | dma-names = "rx-tx"; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 99 | status = "disabled"; |
Huang Shijie | cf922fa | 2012-07-01 23:38:46 -0400 | [diff] [blame] | 100 | }; |
| 101 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 102 | timer@00a00600 { |
Marc Zyngier | 58458e0 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 103 | compatible = "arm,cortex-a9-twd-timer"; |
| 104 | reg = <0x00a00600 0x20>; |
| 105 | interrupts = <1 13 0xf01>; |
Shawn Guo | 2bb4b70 | 2013-04-03 23:50:09 +0800 | [diff] [blame] | 106 | clocks = <&clks 15>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 107 | }; |
| 108 | |
| 109 | L2: l2-cache@00a02000 { |
| 110 | compatible = "arm,pl310-cache"; |
| 111 | reg = <0x00a02000 0x1000>; |
| 112 | interrupts = <0 92 0x04>; |
| 113 | cache-unified; |
| 114 | cache-level = <2>; |
Dirk Behme | 5a5ca56 | 2013-04-26 10:13:55 +0200 | [diff] [blame] | 115 | arm,tag-latency = <4 2 3>; |
| 116 | arm,data-latency = <4 2 3>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 117 | }; |
| 118 | |
Sean Cross | 3a57291 | 2013-09-26 10:51:09 +0800 | [diff] [blame] | 119 | pcie: pcie@0x01000000 { |
| 120 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; |
| 121 | reg = <0x01ffc000 0x4000>; /* DBI */ |
| 122 | #address-cells = <3>; |
| 123 | #size-cells = <2>; |
| 124 | device_type = "pci"; |
| 125 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ |
| 126 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ |
| 127 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ |
| 128 | num-lanes = <1>; |
| 129 | interrupts = <0 123 0x04>; |
| 130 | clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; |
| 131 | clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; |
| 132 | status = "disabled"; |
| 133 | }; |
| 134 | |
Dirk Behme | 218abe6 | 2013-02-15 15:10:01 +0100 | [diff] [blame] | 135 | pmu { |
| 136 | compatible = "arm,cortex-a9-pmu"; |
| 137 | interrupts = <0 94 0x04>; |
| 138 | }; |
| 139 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 140 | aips-bus@02000000 { /* AIPS1 */ |
| 141 | compatible = "fsl,aips-bus", "simple-bus"; |
| 142 | #address-cells = <1>; |
| 143 | #size-cells = <1>; |
| 144 | reg = <0x02000000 0x100000>; |
| 145 | ranges; |
| 146 | |
| 147 | spba-bus@02000000 { |
| 148 | compatible = "fsl,spba-bus", "simple-bus"; |
| 149 | #address-cells = <1>; |
| 150 | #size-cells = <1>; |
| 151 | reg = <0x02000000 0x40000>; |
| 152 | ranges; |
| 153 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 154 | spdif: spdif@02004000 { |
Fabio Estevam | c9d96df | 2013-09-02 23:51:41 -0300 | [diff] [blame] | 155 | compatible = "fsl,imx35-spdif"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 156 | reg = <0x02004000 0x4000>; |
| 157 | interrupts = <0 52 0x04>; |
Fabio Estevam | c9d96df | 2013-09-02 23:51:41 -0300 | [diff] [blame] | 158 | dmas = <&sdma 14 18 0>, |
| 159 | <&sdma 15 18 0>; |
| 160 | dma-names = "rx", "tx"; |
| 161 | clocks = <&clks 197>, <&clks 3>, |
| 162 | <&clks 197>, <&clks 107>, |
| 163 | <&clks 0>, <&clks 118>, |
Shawn Guo | 793b4b1 | 2013-11-16 22:38:29 +0800 | [diff] [blame] | 164 | <&clks 0>, <&clks 139>, |
Fabio Estevam | c9d96df | 2013-09-02 23:51:41 -0300 | [diff] [blame] | 165 | <&clks 0>; |
| 166 | clock-names = "core", "rxtx0", |
| 167 | "rxtx1", "rxtx2", |
| 168 | "rxtx3", "rxtx4", |
| 169 | "rxtx5", "rxtx6", |
| 170 | "rxtx7"; |
| 171 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 172 | }; |
| 173 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 174 | ecspi1: ecspi@02008000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 175 | #address-cells = <1>; |
| 176 | #size-cells = <0>; |
| 177 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 178 | reg = <0x02008000 0x4000>; |
| 179 | interrupts = <0 31 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 180 | clocks = <&clks 112>, <&clks 112>; |
| 181 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 182 | status = "disabled"; |
| 183 | }; |
| 184 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 185 | ecspi2: ecspi@0200c000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 186 | #address-cells = <1>; |
| 187 | #size-cells = <0>; |
| 188 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 189 | reg = <0x0200c000 0x4000>; |
| 190 | interrupts = <0 32 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 191 | clocks = <&clks 113>, <&clks 113>; |
| 192 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 193 | status = "disabled"; |
| 194 | }; |
| 195 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 196 | ecspi3: ecspi@02010000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 197 | #address-cells = <1>; |
| 198 | #size-cells = <0>; |
| 199 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 200 | reg = <0x02010000 0x4000>; |
| 201 | interrupts = <0 33 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 202 | clocks = <&clks 114>, <&clks 114>; |
| 203 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 204 | status = "disabled"; |
| 205 | }; |
| 206 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 207 | ecspi4: ecspi@02014000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 208 | #address-cells = <1>; |
| 209 | #size-cells = <0>; |
| 210 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 211 | reg = <0x02014000 0x4000>; |
| 212 | interrupts = <0 34 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 213 | clocks = <&clks 115>, <&clks 115>; |
| 214 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 215 | status = "disabled"; |
| 216 | }; |
| 217 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 218 | uart1: serial@02020000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 219 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 220 | reg = <0x02020000 0x4000>; |
| 221 | interrupts = <0 26 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 222 | clocks = <&clks 160>, <&clks 161>; |
| 223 | clock-names = "ipg", "per"; |
Huang Shijie | 72a5ceb | 2013-07-12 18:02:09 +0800 | [diff] [blame] | 224 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| 225 | dma-names = "rx", "tx"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 226 | status = "disabled"; |
| 227 | }; |
| 228 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 229 | esai: esai@02024000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 230 | reg = <0x02024000 0x4000>; |
| 231 | interrupts = <0 51 0x04>; |
| 232 | }; |
| 233 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 234 | ssi1: ssi@02028000 { |
| 235 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 236 | reg = <0x02028000 0x4000>; |
| 237 | interrupts = <0 46 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 238 | clocks = <&clks 178>; |
Shawn Guo | 5da826a | 2013-07-17 13:50:54 +0800 | [diff] [blame] | 239 | dmas = <&sdma 37 1 0>, |
| 240 | <&sdma 38 1 0>; |
| 241 | dma-names = "rx", "tx"; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 242 | fsl,fifo-depth = <15>; |
| 243 | fsl,ssi-dma-events = <38 37>; |
| 244 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 245 | }; |
| 246 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 247 | ssi2: ssi@0202c000 { |
| 248 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 249 | reg = <0x0202c000 0x4000>; |
| 250 | interrupts = <0 47 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 251 | clocks = <&clks 179>; |
Shawn Guo | 5da826a | 2013-07-17 13:50:54 +0800 | [diff] [blame] | 252 | dmas = <&sdma 41 1 0>, |
| 253 | <&sdma 42 1 0>; |
| 254 | dma-names = "rx", "tx"; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 255 | fsl,fifo-depth = <15>; |
| 256 | fsl,ssi-dma-events = <42 41>; |
| 257 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 258 | }; |
| 259 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 260 | ssi3: ssi@02030000 { |
| 261 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 262 | reg = <0x02030000 0x4000>; |
| 263 | interrupts = <0 48 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 264 | clocks = <&clks 180>; |
Shawn Guo | 5da826a | 2013-07-17 13:50:54 +0800 | [diff] [blame] | 265 | dmas = <&sdma 45 1 0>, |
| 266 | <&sdma 46 1 0>; |
| 267 | dma-names = "rx", "tx"; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 268 | fsl,fifo-depth = <15>; |
| 269 | fsl,ssi-dma-events = <46 45>; |
| 270 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 271 | }; |
| 272 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 273 | asrc: asrc@02034000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 274 | reg = <0x02034000 0x4000>; |
| 275 | interrupts = <0 50 0x04>; |
| 276 | }; |
| 277 | |
| 278 | spba@0203c000 { |
| 279 | reg = <0x0203c000 0x4000>; |
| 280 | }; |
| 281 | }; |
| 282 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 283 | vpu: vpu@02040000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 284 | reg = <0x02040000 0x3c000>; |
| 285 | interrupts = <0 3 0x04 0 12 0x04>; |
| 286 | }; |
| 287 | |
| 288 | aipstz@0207c000 { /* AIPSTZ1 */ |
| 289 | reg = <0x0207c000 0x4000>; |
| 290 | }; |
| 291 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 292 | pwm1: pwm@02080000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 293 | #pwm-cells = <2>; |
| 294 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 295 | reg = <0x02080000 0x4000>; |
| 296 | interrupts = <0 83 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 297 | clocks = <&clks 62>, <&clks 145>; |
| 298 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 299 | }; |
| 300 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 301 | pwm2: pwm@02084000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 302 | #pwm-cells = <2>; |
| 303 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 304 | reg = <0x02084000 0x4000>; |
| 305 | interrupts = <0 84 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 306 | clocks = <&clks 62>, <&clks 146>; |
| 307 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 308 | }; |
| 309 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 310 | pwm3: pwm@02088000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 311 | #pwm-cells = <2>; |
| 312 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 313 | reg = <0x02088000 0x4000>; |
| 314 | interrupts = <0 85 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 315 | clocks = <&clks 62>, <&clks 147>; |
| 316 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 317 | }; |
| 318 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 319 | pwm4: pwm@0208c000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 320 | #pwm-cells = <2>; |
| 321 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 322 | reg = <0x0208c000 0x4000>; |
| 323 | interrupts = <0 86 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 324 | clocks = <&clks 62>, <&clks 148>; |
| 325 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 326 | }; |
| 327 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 328 | can1: flexcan@02090000 { |
Sascha Hauer | 0f22521 | 2013-06-25 15:51:46 +0200 | [diff] [blame] | 329 | compatible = "fsl,imx6q-flexcan"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 330 | reg = <0x02090000 0x4000>; |
| 331 | interrupts = <0 110 0x04>; |
Sascha Hauer | 0f22521 | 2013-06-25 15:51:46 +0200 | [diff] [blame] | 332 | clocks = <&clks 108>, <&clks 109>; |
| 333 | clock-names = "ipg", "per"; |
Tim Harvey | a113533 | 2013-10-22 21:51:27 -0700 | [diff] [blame^] | 334 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 335 | }; |
| 336 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 337 | can2: flexcan@02094000 { |
Sascha Hauer | 0f22521 | 2013-06-25 15:51:46 +0200 | [diff] [blame] | 338 | compatible = "fsl,imx6q-flexcan"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 339 | reg = <0x02094000 0x4000>; |
| 340 | interrupts = <0 111 0x04>; |
Sascha Hauer | 0f22521 | 2013-06-25 15:51:46 +0200 | [diff] [blame] | 341 | clocks = <&clks 110>, <&clks 111>; |
| 342 | clock-names = "ipg", "per"; |
Tim Harvey | a113533 | 2013-10-22 21:51:27 -0700 | [diff] [blame^] | 343 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 344 | }; |
| 345 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 346 | gpt: gpt@02098000 { |
Sascha Hauer | 97b108f | 2013-06-25 15:51:47 +0200 | [diff] [blame] | 347 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 348 | reg = <0x02098000 0x4000>; |
| 349 | interrupts = <0 55 0x04>; |
Sascha Hauer | 4efccad | 2013-03-14 13:09:01 +0100 | [diff] [blame] | 350 | clocks = <&clks 119>, <&clks 120>; |
| 351 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 352 | }; |
| 353 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 354 | gpio1: gpio@0209c000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 355 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 356 | reg = <0x0209c000 0x4000>; |
| 357 | interrupts = <0 66 0x04 0 67 0x04>; |
| 358 | gpio-controller; |
| 359 | #gpio-cells = <2>; |
| 360 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 361 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 362 | }; |
| 363 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 364 | gpio2: gpio@020a0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 365 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 366 | reg = <0x020a0000 0x4000>; |
| 367 | interrupts = <0 68 0x04 0 69 0x04>; |
| 368 | gpio-controller; |
| 369 | #gpio-cells = <2>; |
| 370 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 371 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 372 | }; |
| 373 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 374 | gpio3: gpio@020a4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 375 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 376 | reg = <0x020a4000 0x4000>; |
| 377 | interrupts = <0 70 0x04 0 71 0x04>; |
| 378 | gpio-controller; |
| 379 | #gpio-cells = <2>; |
| 380 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 381 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 382 | }; |
| 383 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 384 | gpio4: gpio@020a8000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 385 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 386 | reg = <0x020a8000 0x4000>; |
| 387 | interrupts = <0 72 0x04 0 73 0x04>; |
| 388 | gpio-controller; |
| 389 | #gpio-cells = <2>; |
| 390 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 391 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 392 | }; |
| 393 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 394 | gpio5: gpio@020ac000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 395 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 396 | reg = <0x020ac000 0x4000>; |
| 397 | interrupts = <0 74 0x04 0 75 0x04>; |
| 398 | gpio-controller; |
| 399 | #gpio-cells = <2>; |
| 400 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 401 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 402 | }; |
| 403 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 404 | gpio6: gpio@020b0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 405 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 406 | reg = <0x020b0000 0x4000>; |
| 407 | interrupts = <0 76 0x04 0 77 0x04>; |
| 408 | gpio-controller; |
| 409 | #gpio-cells = <2>; |
| 410 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 411 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 412 | }; |
| 413 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 414 | gpio7: gpio@020b4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 415 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 416 | reg = <0x020b4000 0x4000>; |
| 417 | interrupts = <0 78 0x04 0 79 0x04>; |
| 418 | gpio-controller; |
| 419 | #gpio-cells = <2>; |
| 420 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 421 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 422 | }; |
| 423 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 424 | kpp: kpp@020b8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 425 | reg = <0x020b8000 0x4000>; |
| 426 | interrupts = <0 82 0x04>; |
| 427 | }; |
| 428 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 429 | wdog1: wdog@020bc000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 430 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 431 | reg = <0x020bc000 0x4000>; |
| 432 | interrupts = <0 80 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 433 | clocks = <&clks 0>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 434 | }; |
| 435 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 436 | wdog2: wdog@020c0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 437 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 438 | reg = <0x020c0000 0x4000>; |
| 439 | interrupts = <0 81 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 440 | clocks = <&clks 0>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 441 | status = "disabled"; |
| 442 | }; |
| 443 | |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 444 | clks: ccm@020c4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 445 | compatible = "fsl,imx6q-ccm"; |
| 446 | reg = <0x020c4000 0x4000>; |
| 447 | interrupts = <0 87 0x04 0 88 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 448 | #clock-cells = <1>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 449 | }; |
| 450 | |
Dong Aisheng | baa6415 | 2012-09-05 10:57:15 +0800 | [diff] [blame] | 451 | anatop: anatop@020c8000 { |
| 452 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 453 | reg = <0x020c8000 0x1000>; |
| 454 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 455 | |
| 456 | regulator-1p1@110 { |
| 457 | compatible = "fsl,anatop-regulator"; |
| 458 | regulator-name = "vdd1p1"; |
| 459 | regulator-min-microvolt = <800000>; |
| 460 | regulator-max-microvolt = <1375000>; |
| 461 | regulator-always-on; |
| 462 | anatop-reg-offset = <0x110>; |
| 463 | anatop-vol-bit-shift = <8>; |
| 464 | anatop-vol-bit-width = <5>; |
| 465 | anatop-min-bit-val = <4>; |
| 466 | anatop-min-voltage = <800000>; |
| 467 | anatop-max-voltage = <1375000>; |
| 468 | }; |
| 469 | |
| 470 | regulator-3p0@120 { |
| 471 | compatible = "fsl,anatop-regulator"; |
| 472 | regulator-name = "vdd3p0"; |
| 473 | regulator-min-microvolt = <2800000>; |
| 474 | regulator-max-microvolt = <3150000>; |
| 475 | regulator-always-on; |
| 476 | anatop-reg-offset = <0x120>; |
| 477 | anatop-vol-bit-shift = <8>; |
| 478 | anatop-vol-bit-width = <5>; |
| 479 | anatop-min-bit-val = <0>; |
| 480 | anatop-min-voltage = <2625000>; |
| 481 | anatop-max-voltage = <3400000>; |
| 482 | }; |
| 483 | |
| 484 | regulator-2p5@130 { |
| 485 | compatible = "fsl,anatop-regulator"; |
| 486 | regulator-name = "vdd2p5"; |
| 487 | regulator-min-microvolt = <2000000>; |
| 488 | regulator-max-microvolt = <2750000>; |
| 489 | regulator-always-on; |
| 490 | anatop-reg-offset = <0x130>; |
| 491 | anatop-vol-bit-shift = <8>; |
| 492 | anatop-vol-bit-width = <5>; |
| 493 | anatop-min-bit-val = <0>; |
| 494 | anatop-min-voltage = <2000000>; |
| 495 | anatop-max-voltage = <2750000>; |
| 496 | }; |
| 497 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 498 | reg_arm: regulator-vddcore@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 499 | compatible = "fsl,anatop-regulator"; |
| 500 | regulator-name = "cpu"; |
| 501 | regulator-min-microvolt = <725000>; |
| 502 | regulator-max-microvolt = <1450000>; |
| 503 | regulator-always-on; |
| 504 | anatop-reg-offset = <0x140>; |
| 505 | anatop-vol-bit-shift = <0>; |
| 506 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame] | 507 | anatop-delay-reg-offset = <0x170>; |
| 508 | anatop-delay-bit-shift = <24>; |
| 509 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 510 | anatop-min-bit-val = <1>; |
| 511 | anatop-min-voltage = <725000>; |
| 512 | anatop-max-voltage = <1450000>; |
| 513 | }; |
| 514 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 515 | reg_pu: regulator-vddpu@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 516 | compatible = "fsl,anatop-regulator"; |
| 517 | regulator-name = "vddpu"; |
| 518 | regulator-min-microvolt = <725000>; |
| 519 | regulator-max-microvolt = <1450000>; |
| 520 | regulator-always-on; |
| 521 | anatop-reg-offset = <0x140>; |
| 522 | anatop-vol-bit-shift = <9>; |
| 523 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame] | 524 | anatop-delay-reg-offset = <0x170>; |
| 525 | anatop-delay-bit-shift = <26>; |
| 526 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 527 | anatop-min-bit-val = <1>; |
| 528 | anatop-min-voltage = <725000>; |
| 529 | anatop-max-voltage = <1450000>; |
| 530 | }; |
| 531 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 532 | reg_soc: regulator-vddsoc@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 533 | compatible = "fsl,anatop-regulator"; |
| 534 | regulator-name = "vddsoc"; |
| 535 | regulator-min-microvolt = <725000>; |
| 536 | regulator-max-microvolt = <1450000>; |
| 537 | regulator-always-on; |
| 538 | anatop-reg-offset = <0x140>; |
| 539 | anatop-vol-bit-shift = <18>; |
| 540 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame] | 541 | anatop-delay-reg-offset = <0x170>; |
| 542 | anatop-delay-bit-shift = <28>; |
| 543 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 544 | anatop-min-bit-val = <1>; |
| 545 | anatop-min-voltage = <725000>; |
| 546 | anatop-max-voltage = <1450000>; |
| 547 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 548 | }; |
| 549 | |
Shawn Guo | 3fe6373 | 2013-07-16 21:16:36 +0800 | [diff] [blame] | 550 | tempmon: tempmon { |
| 551 | compatible = "fsl,imx6q-tempmon"; |
| 552 | interrupts = <0 49 0x04>; |
| 553 | fsl,tempmon = <&anatop>; |
| 554 | fsl,tempmon-data = <&ocotp>; |
| 555 | }; |
| 556 | |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 557 | usbphy1: usbphy@020c9000 { |
| 558 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 559 | reg = <0x020c9000 0x1000>; |
| 560 | interrupts = <0 44 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 561 | clocks = <&clks 182>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 562 | }; |
| 563 | |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 564 | usbphy2: usbphy@020ca000 { |
| 565 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 566 | reg = <0x020ca000 0x1000>; |
| 567 | interrupts = <0 45 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 568 | clocks = <&clks 183>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 569 | }; |
| 570 | |
| 571 | snvs@020cc000 { |
Shawn Guo | c925038 | 2012-07-02 20:13:03 +0800 | [diff] [blame] | 572 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| 573 | #address-cells = <1>; |
| 574 | #size-cells = <1>; |
| 575 | ranges = <0 0x020cc000 0x4000>; |
| 576 | |
| 577 | snvs-rtc-lp@34 { |
| 578 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| 579 | reg = <0x34 0x58>; |
| 580 | interrupts = <0 19 0x04 0 20 0x04>; |
| 581 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 582 | }; |
| 583 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 584 | epit1: epit@020d0000 { /* EPIT1 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 585 | reg = <0x020d0000 0x4000>; |
| 586 | interrupts = <0 56 0x04>; |
| 587 | }; |
| 588 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 589 | epit2: epit@020d4000 { /* EPIT2 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 590 | reg = <0x020d4000 0x4000>; |
| 591 | interrupts = <0 57 0x04>; |
| 592 | }; |
| 593 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 594 | src: src@020d8000 { |
Philipp Zabel | bd3d924 | 2013-03-28 17:35:22 +0100 | [diff] [blame] | 595 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 596 | reg = <0x020d8000 0x4000>; |
| 597 | interrupts = <0 91 0x04 0 96 0x04>; |
Philipp Zabel | 09ebf36 | 2013-03-28 17:35:20 +0100 | [diff] [blame] | 598 | #reset-cells = <1>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 599 | }; |
| 600 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 601 | gpc: gpc@020dc000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 602 | compatible = "fsl,imx6q-gpc"; |
| 603 | reg = <0x020dc000 0x4000>; |
| 604 | interrupts = <0 89 0x04 0 90 0x04>; |
| 605 | }; |
| 606 | |
Dong Aisheng | df37e0c | 2012-09-05 10:57:14 +0800 | [diff] [blame] | 607 | gpr: iomuxc-gpr@020e0000 { |
| 608 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; |
| 609 | reg = <0x020e0000 0x38>; |
| 610 | }; |
| 611 | |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 612 | iomuxc: iomuxc@020e0000 { |
| 613 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; |
| 614 | reg = <0x020e0000 0x4000>; |
| 615 | |
| 616 | audmux { |
| 617 | pinctrl_audmux_1: audmux-1 { |
| 618 | fsl,pins = < |
| 619 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 |
| 620 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 |
| 621 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 |
| 622 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 |
| 623 | >; |
| 624 | }; |
| 625 | |
| 626 | pinctrl_audmux_2: audmux-2 { |
| 627 | fsl,pins = < |
| 628 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 |
| 629 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 |
| 630 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 |
| 631 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 |
| 632 | >; |
| 633 | }; |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 634 | |
| 635 | pinctrl_audmux_3: audmux-3 { |
| 636 | fsl,pins = < |
| 637 | MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 |
| 638 | MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 |
| 639 | MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 |
| 640 | >; |
| 641 | }; |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 642 | }; |
| 643 | |
| 644 | ecspi1 { |
| 645 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 646 | fsl,pins = < |
| 647 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |
| 648 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 |
| 649 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |
| 650 | >; |
| 651 | }; |
| 652 | |
| 653 | pinctrl_ecspi1_2: ecspi1grp-2 { |
| 654 | fsl,pins = < |
| 655 | MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 |
| 656 | MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 |
| 657 | MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 |
| 658 | >; |
| 659 | }; |
| 660 | }; |
| 661 | |
| 662 | ecspi3 { |
| 663 | pinctrl_ecspi3_1: ecspi3grp-1 { |
| 664 | fsl,pins = < |
| 665 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 |
| 666 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 |
| 667 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 |
| 668 | >; |
| 669 | }; |
| 670 | }; |
| 671 | |
| 672 | enet { |
| 673 | pinctrl_enet_1: enetgrp-1 { |
| 674 | fsl,pins = < |
| 675 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| 676 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| 677 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 678 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 679 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 680 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 681 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 682 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 683 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 684 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 685 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 686 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 687 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 688 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 689 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 690 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
| 691 | >; |
| 692 | }; |
| 693 | |
| 694 | pinctrl_enet_2: enetgrp-2 { |
| 695 | fsl,pins = < |
| 696 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 |
| 697 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 |
| 698 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 699 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 700 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 701 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 702 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 703 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 704 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 705 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 706 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 707 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 708 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 709 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 710 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 711 | >; |
| 712 | }; |
| 713 | |
| 714 | pinctrl_enet_3: enetgrp-3 { |
| 715 | fsl,pins = < |
| 716 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| 717 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| 718 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 719 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 720 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 721 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 722 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 723 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 724 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 725 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 726 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 727 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 728 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 729 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 730 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 731 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 |
| 732 | >; |
| 733 | }; |
| 734 | }; |
| 735 | |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 736 | esai { |
| 737 | pinctrl_esai_1: esaigrp-1 { |
| 738 | fsl,pins = < |
| 739 | MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 |
| 740 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 |
| 741 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 |
| 742 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 |
| 743 | MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 |
| 744 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 |
| 745 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 |
| 746 | MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 |
| 747 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 |
| 748 | >; |
| 749 | }; |
| 750 | |
| 751 | pinctrl_esai_2: esaigrp-2 { |
| 752 | fsl,pins = < |
| 753 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 |
| 754 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 |
| 755 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 |
| 756 | MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 |
| 757 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 |
| 758 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 |
| 759 | MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 |
| 760 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 |
| 761 | MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 |
| 762 | MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 |
| 763 | >; |
| 764 | }; |
| 765 | }; |
| 766 | |
| 767 | flexcan1 { |
| 768 | pinctrl_flexcan1_1: flexcan1grp-1 { |
| 769 | fsl,pins = < |
| 770 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 |
| 771 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 |
| 772 | >; |
| 773 | }; |
| 774 | |
| 775 | pinctrl_flexcan1_2: flexcan1grp-2 { |
| 776 | fsl,pins = < |
| 777 | MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 |
| 778 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 |
| 779 | >; |
| 780 | }; |
| 781 | }; |
| 782 | |
| 783 | flexcan2 { |
| 784 | pinctrl_flexcan2_1: flexcan2grp-1 { |
| 785 | fsl,pins = < |
| 786 | MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 |
| 787 | MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 |
| 788 | >; |
| 789 | }; |
| 790 | }; |
| 791 | |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 792 | gpmi-nand { |
| 793 | pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| 794 | fsl,pins = < |
| 795 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
| 796 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 |
| 797 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 |
| 798 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
| 799 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
| 800 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 |
| 801 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
| 802 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
| 803 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
| 804 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 |
| 805 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 |
| 806 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 |
| 807 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 |
| 808 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 |
| 809 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 |
| 810 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 |
| 811 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 |
| 812 | >; |
| 813 | }; |
| 814 | }; |
| 815 | |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 816 | hdmi_hdcp { |
| 817 | pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { |
| 818 | fsl,pins = < |
| 819 | MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 |
| 820 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 |
| 821 | >; |
| 822 | }; |
| 823 | |
| 824 | pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { |
| 825 | fsl,pins = < |
| 826 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 |
| 827 | MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 |
| 828 | >; |
| 829 | }; |
| 830 | |
| 831 | pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { |
| 832 | fsl,pins = < |
| 833 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 |
| 834 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 |
| 835 | >; |
| 836 | }; |
| 837 | }; |
| 838 | |
| 839 | hdmi_cec { |
| 840 | pinctrl_hdmi_cec_1: hdmicecgrp-1 { |
| 841 | fsl,pins = < |
| 842 | MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 |
| 843 | >; |
| 844 | }; |
| 845 | |
| 846 | pinctrl_hdmi_cec_2: hdmicecgrp-2 { |
| 847 | fsl,pins = < |
| 848 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 |
| 849 | >; |
| 850 | }; |
| 851 | }; |
| 852 | |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 853 | i2c1 { |
| 854 | pinctrl_i2c1_1: i2c1grp-1 { |
| 855 | fsl,pins = < |
| 856 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
| 857 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
| 858 | >; |
| 859 | }; |
| 860 | |
| 861 | pinctrl_i2c1_2: i2c1grp-2 { |
| 862 | fsl,pins = < |
| 863 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 |
| 864 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 |
| 865 | >; |
| 866 | }; |
| 867 | }; |
| 868 | |
| 869 | i2c2 { |
| 870 | pinctrl_i2c2_1: i2c2grp-1 { |
| 871 | fsl,pins = < |
| 872 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 |
| 873 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 |
| 874 | >; |
| 875 | }; |
| 876 | |
| 877 | pinctrl_i2c2_2: i2c2grp-2 { |
| 878 | fsl,pins = < |
| 879 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
| 880 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
| 881 | >; |
| 882 | }; |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 883 | |
| 884 | pinctrl_i2c2_3: i2c2grp-3 { |
| 885 | fsl,pins = < |
| 886 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 |
| 887 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
| 888 | >; |
| 889 | }; |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 890 | }; |
| 891 | |
| 892 | i2c3 { |
| 893 | pinctrl_i2c3_1: i2c3grp-1 { |
| 894 | fsl,pins = < |
| 895 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 |
| 896 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 |
| 897 | >; |
| 898 | }; |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 899 | |
| 900 | pinctrl_i2c3_2: i2c3grp-2 { |
| 901 | fsl,pins = < |
| 902 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
| 903 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 |
| 904 | >; |
| 905 | }; |
| 906 | |
| 907 | pinctrl_i2c3_3: i2c3grp-3 { |
| 908 | fsl,pins = < |
| 909 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 |
| 910 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 |
| 911 | >; |
| 912 | }; |
| 913 | |
| 914 | pinctrl_i2c3_4: i2c3grp-4 { |
| 915 | fsl,pins = < |
| 916 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
| 917 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 |
| 918 | >; |
| 919 | }; |
| 920 | }; |
| 921 | |
| 922 | ipu1 { |
| 923 | pinctrl_ipu1_1: ipu1grp-1 { |
| 924 | fsl,pins = < |
| 925 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 |
| 926 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 |
| 927 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 |
| 928 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 |
| 929 | MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 |
| 930 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 |
| 931 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 |
| 932 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 |
| 933 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 |
| 934 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 |
| 935 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 |
| 936 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 |
| 937 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 |
| 938 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 |
| 939 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 |
| 940 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 |
| 941 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 |
| 942 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 |
| 943 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 |
| 944 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 |
| 945 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 |
| 946 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 |
| 947 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 |
| 948 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 |
| 949 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 |
| 950 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 |
| 951 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 |
| 952 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 |
| 953 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 |
| 954 | >; |
| 955 | }; |
| 956 | |
| 957 | pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ |
| 958 | fsl,pins = < |
| 959 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 |
| 960 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 |
| 961 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 |
| 962 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 |
| 963 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 |
| 964 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 |
| 965 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 |
| 966 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 |
| 967 | MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 |
| 968 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 |
| 969 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 |
| 970 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 |
| 971 | >; |
| 972 | }; |
| 973 | |
| 974 | pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ |
| 975 | fsl,pins = < |
| 976 | MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 |
| 977 | MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 |
| 978 | MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 |
| 979 | MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 |
| 980 | MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 |
| 981 | MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 |
| 982 | MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 |
| 983 | MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 |
| 984 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 |
| 985 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 |
| 986 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 |
| 987 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 |
| 988 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 |
| 989 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 |
| 990 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 |
| 991 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 |
| 992 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 |
| 993 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 |
| 994 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 |
| 995 | >; |
| 996 | }; |
| 997 | }; |
| 998 | |
| 999 | mlb { |
| 1000 | pinctrl_mlb_1: mlbgrp-1 { |
| 1001 | fsl,pins = < |
| 1002 | MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 |
| 1003 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 |
| 1004 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 |
| 1005 | >; |
| 1006 | }; |
| 1007 | |
| 1008 | pinctrl_mlb_2: mlbgrp-2 { |
| 1009 | fsl,pins = < |
| 1010 | MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 |
| 1011 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 |
| 1012 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 |
| 1013 | >; |
| 1014 | }; |
| 1015 | }; |
| 1016 | |
| 1017 | pwm0 { |
| 1018 | pinctrl_pwm0_1: pwm0grp-1 { |
| 1019 | fsl,pins = < |
| 1020 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 |
| 1021 | >; |
| 1022 | }; |
| 1023 | }; |
| 1024 | |
| 1025 | pwm3 { |
| 1026 | pinctrl_pwm3_1: pwm3grp-1 { |
| 1027 | fsl,pins = < |
| 1028 | MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 |
| 1029 | >; |
| 1030 | }; |
| 1031 | }; |
| 1032 | |
| 1033 | spdif { |
| 1034 | pinctrl_spdif_1: spdifgrp-1 { |
| 1035 | fsl,pins = < |
| 1036 | MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 |
| 1037 | >; |
| 1038 | }; |
| 1039 | |
| 1040 | pinctrl_spdif_2: spdifgrp-2 { |
| 1041 | fsl,pins = < |
| 1042 | MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 |
| 1043 | MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 |
| 1044 | >; |
| 1045 | }; |
Fabio Estevam | c9d96df | 2013-09-02 23:51:41 -0300 | [diff] [blame] | 1046 | |
| 1047 | pinctrl_spdif_3: spdifgrp-3 { |
| 1048 | fsl,pins = < |
| 1049 | MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 |
| 1050 | >; |
| 1051 | }; |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 1052 | }; |
| 1053 | |
| 1054 | uart1 { |
| 1055 | pinctrl_uart1_1: uart1grp-1 { |
| 1056 | fsl,pins = < |
| 1057 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 |
| 1058 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 |
| 1059 | >; |
| 1060 | }; |
| 1061 | }; |
| 1062 | |
| 1063 | uart2 { |
| 1064 | pinctrl_uart2_1: uart2grp-1 { |
| 1065 | fsl,pins = < |
| 1066 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 |
| 1067 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 |
| 1068 | >; |
| 1069 | }; |
| 1070 | |
| 1071 | pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ |
| 1072 | fsl,pins = < |
| 1073 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 |
| 1074 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 |
| 1075 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 |
| 1076 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 |
| 1077 | >; |
| 1078 | }; |
| 1079 | }; |
| 1080 | |
Huang Shijie | c279798 | 2013-07-12 15:56:11 +0800 | [diff] [blame] | 1081 | uart3 { |
| 1082 | pinctrl_uart3_1: uart3grp-1 { |
| 1083 | fsl,pins = < |
| 1084 | MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 |
| 1085 | MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 |
| 1086 | MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 |
| 1087 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 |
| 1088 | >; |
| 1089 | }; |
Fabio Estevam | 5ff88341 | 2013-07-12 09:49:31 -0300 | [diff] [blame] | 1090 | |
| 1091 | pinctrl_uart3_2: uart3grp-2 { |
| 1092 | fsl,pins = < |
| 1093 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |
| 1094 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 |
| 1095 | MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 |
| 1096 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 |
| 1097 | >; |
| 1098 | }; |
Huang Shijie | c279798 | 2013-07-12 15:56:11 +0800 | [diff] [blame] | 1099 | }; |
| 1100 | |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 1101 | uart4 { |
| 1102 | pinctrl_uart4_1: uart4grp-1 { |
| 1103 | fsl,pins = < |
| 1104 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |
| 1105 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 |
| 1106 | >; |
| 1107 | }; |
| 1108 | }; |
| 1109 | |
| 1110 | usbotg { |
| 1111 | pinctrl_usbotg_1: usbotggrp-1 { |
| 1112 | fsl,pins = < |
| 1113 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 |
| 1114 | >; |
| 1115 | }; |
| 1116 | |
| 1117 | pinctrl_usbotg_2: usbotggrp-2 { |
| 1118 | fsl,pins = < |
| 1119 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 |
| 1120 | >; |
| 1121 | }; |
| 1122 | }; |
| 1123 | |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 1124 | usbh2 { |
| 1125 | pinctrl_usbh2_1: usbh2grp-1 { |
| 1126 | fsl,pins = < |
| 1127 | MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 |
| 1128 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 |
| 1129 | >; |
| 1130 | }; |
| 1131 | |
| 1132 | pinctrl_usbh2_2: usbh2grp-2 { |
| 1133 | fsl,pins = < |
| 1134 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 |
| 1135 | >; |
| 1136 | }; |
| 1137 | }; |
| 1138 | |
| 1139 | usbh3 { |
| 1140 | pinctrl_usbh3_1: usbh3grp-1 { |
| 1141 | fsl,pins = < |
| 1142 | MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 |
| 1143 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 |
| 1144 | >; |
| 1145 | }; |
| 1146 | |
| 1147 | pinctrl_usbh3_2: usbh3grp-2 { |
| 1148 | fsl,pins = < |
| 1149 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 |
| 1150 | >; |
| 1151 | }; |
| 1152 | }; |
| 1153 | |
Fabio Estevam | 26c3b65 | 2013-07-12 09:49:30 -0300 | [diff] [blame] | 1154 | usdhc1 { |
| 1155 | pinctrl_usdhc1_1: usdhc1grp-1 { |
| 1156 | fsl,pins = < |
| 1157 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 |
| 1158 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 |
| 1159 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 |
| 1160 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 |
| 1161 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 |
| 1162 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 |
| 1163 | MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 |
| 1164 | MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 |
| 1165 | MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 |
| 1166 | MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 |
| 1167 | >; |
| 1168 | }; |
| 1169 | |
| 1170 | pinctrl_usdhc1_2: usdhc1grp-2 { |
| 1171 | fsl,pins = < |
| 1172 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 |
| 1173 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 |
| 1174 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 |
| 1175 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 |
| 1176 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 |
| 1177 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 |
| 1178 | >; |
| 1179 | }; |
| 1180 | }; |
| 1181 | |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 1182 | usdhc2 { |
| 1183 | pinctrl_usdhc2_1: usdhc2grp-1 { |
| 1184 | fsl,pins = < |
| 1185 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| 1186 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| 1187 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| 1188 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| 1189 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| 1190 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| 1191 | MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 |
| 1192 | MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 |
| 1193 | MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 |
| 1194 | MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 |
| 1195 | >; |
| 1196 | }; |
| 1197 | |
| 1198 | pinctrl_usdhc2_2: usdhc2grp-2 { |
| 1199 | fsl,pins = < |
| 1200 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| 1201 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| 1202 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| 1203 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| 1204 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| 1205 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| 1206 | >; |
| 1207 | }; |
| 1208 | }; |
| 1209 | |
| 1210 | usdhc3 { |
| 1211 | pinctrl_usdhc3_1: usdhc3grp-1 { |
| 1212 | fsl,pins = < |
| 1213 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 1214 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 1215 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 1216 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 1217 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 1218 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 1219 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| 1220 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| 1221 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| 1222 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| 1223 | >; |
| 1224 | }; |
| 1225 | |
Dong Aisheng | 93e2ca0 | 2013-09-13 19:11:38 +0800 | [diff] [blame] | 1226 | pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ |
| 1227 | fsl,pins = < |
| 1228 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 |
| 1229 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 |
| 1230 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 |
| 1231 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 |
| 1232 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 |
| 1233 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 |
| 1234 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 |
| 1235 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 |
| 1236 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 |
| 1237 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 |
| 1238 | >; |
| 1239 | }; |
| 1240 | |
| 1241 | pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ |
| 1242 | fsl,pins = < |
| 1243 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 |
| 1244 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 |
| 1245 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 |
| 1246 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 |
| 1247 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 |
| 1248 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 |
| 1249 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 |
| 1250 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 |
| 1251 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 |
| 1252 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 |
| 1253 | >; |
| 1254 | }; |
| 1255 | |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 1256 | pinctrl_usdhc3_2: usdhc3grp-2 { |
| 1257 | fsl,pins = < |
| 1258 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 1259 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 1260 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 1261 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 1262 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 1263 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 1264 | >; |
| 1265 | }; |
| 1266 | }; |
| 1267 | |
| 1268 | usdhc4 { |
| 1269 | pinctrl_usdhc4_1: usdhc4grp-1 { |
| 1270 | fsl,pins = < |
| 1271 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 1272 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 1273 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 1274 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 1275 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 1276 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| 1277 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 |
| 1278 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 |
| 1279 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 |
| 1280 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 |
| 1281 | >; |
| 1282 | }; |
| 1283 | |
| 1284 | pinctrl_usdhc4_2: usdhc4grp-2 { |
| 1285 | fsl,pins = < |
| 1286 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 1287 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 1288 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 1289 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 1290 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 1291 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| 1292 | >; |
| 1293 | }; |
| 1294 | }; |
| 1295 | |
| 1296 | weim { |
| 1297 | pinctrl_weim_cs0_1: weim_cs0grp-1 { |
| 1298 | fsl,pins = < |
| 1299 | MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 |
| 1300 | >; |
| 1301 | }; |
| 1302 | |
| 1303 | pinctrl_weim_nor_1: weim_norgrp-1 { |
| 1304 | fsl,pins = < |
| 1305 | MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 |
| 1306 | MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 |
| 1307 | MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 |
| 1308 | /* data */ |
| 1309 | MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 |
| 1310 | MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 |
| 1311 | MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 |
| 1312 | MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 |
| 1313 | MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 |
| 1314 | MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 |
| 1315 | MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 |
| 1316 | MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 |
| 1317 | MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 |
| 1318 | MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 |
| 1319 | MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 |
| 1320 | MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 |
| 1321 | MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 |
| 1322 | MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 |
| 1323 | MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 |
| 1324 | MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 |
| 1325 | /* address */ |
| 1326 | MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 |
| 1327 | MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 |
| 1328 | MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 |
| 1329 | MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 |
| 1330 | MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 |
| 1331 | MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 |
| 1332 | MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 |
| 1333 | MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 |
| 1334 | MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 |
| 1335 | MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 |
| 1336 | MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 |
| 1337 | MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 |
| 1338 | MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 |
| 1339 | MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 |
| 1340 | MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 |
| 1341 | MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 |
| 1342 | MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 |
| 1343 | MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 |
| 1344 | MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 |
| 1345 | MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 |
| 1346 | MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 |
| 1347 | MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 |
| 1348 | MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 |
| 1349 | MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 |
| 1350 | >; |
| 1351 | }; |
| 1352 | }; |
| 1353 | }; |
| 1354 | |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 1355 | ldb: ldb@020e0008 { |
| 1356 | #address-cells = <1>; |
| 1357 | #size-cells = <0>; |
| 1358 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; |
| 1359 | gpr = <&gpr>; |
| 1360 | status = "disabled"; |
| 1361 | |
| 1362 | lvds-channel@0 { |
| 1363 | reg = <0>; |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 1364 | status = "disabled"; |
| 1365 | }; |
| 1366 | |
| 1367 | lvds-channel@1 { |
| 1368 | reg = <1>; |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 1369 | status = "disabled"; |
| 1370 | }; |
| 1371 | }; |
| 1372 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1373 | dcic1: dcic@020e4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1374 | reg = <0x020e4000 0x4000>; |
| 1375 | interrupts = <0 124 0x04>; |
| 1376 | }; |
| 1377 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1378 | dcic2: dcic@020e8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1379 | reg = <0x020e8000 0x4000>; |
| 1380 | interrupts = <0 125 0x04>; |
| 1381 | }; |
| 1382 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1383 | sdma: sdma@020ec000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1384 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 1385 | reg = <0x020ec000 0x4000>; |
| 1386 | interrupts = <0 2 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1387 | clocks = <&clks 155>, <&clks 155>; |
| 1388 | clock-names = "ipg", "ahb"; |
Huang Shijie | fb72bb2 | 2013-07-02 10:15:29 +0800 | [diff] [blame] | 1389 | #dma-cells = <3>; |
Fabio Estevam | d6b9c59 | 2013-01-17 12:13:25 -0200 | [diff] [blame] | 1390 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1391 | }; |
| 1392 | }; |
| 1393 | |
| 1394 | aips-bus@02100000 { /* AIPS2 */ |
| 1395 | compatible = "fsl,aips-bus", "simple-bus"; |
| 1396 | #address-cells = <1>; |
| 1397 | #size-cells = <1>; |
| 1398 | reg = <0x02100000 0x100000>; |
| 1399 | ranges; |
| 1400 | |
| 1401 | caam@02100000 { |
| 1402 | reg = <0x02100000 0x40000>; |
| 1403 | interrupts = <0 105 0x04 0 106 0x04>; |
| 1404 | }; |
| 1405 | |
| 1406 | aipstz@0217c000 { /* AIPSTZ2 */ |
| 1407 | reg = <0x0217c000 0x4000>; |
| 1408 | }; |
| 1409 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1410 | usbotg: usb@02184000 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1411 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1412 | reg = <0x02184000 0x200>; |
| 1413 | interrupts = <0 43 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1414 | clocks = <&clks 162>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1415 | fsl,usbphy = <&usbphy1>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 1416 | fsl,usbmisc = <&usbmisc 0>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1417 | status = "disabled"; |
| 1418 | }; |
| 1419 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1420 | usbh1: usb@02184200 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1421 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1422 | reg = <0x02184200 0x200>; |
| 1423 | interrupts = <0 40 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1424 | clocks = <&clks 162>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1425 | fsl,usbphy = <&usbphy2>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 1426 | fsl,usbmisc = <&usbmisc 1>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1427 | status = "disabled"; |
| 1428 | }; |
| 1429 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1430 | usbh2: usb@02184400 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1431 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1432 | reg = <0x02184400 0x200>; |
| 1433 | interrupts = <0 41 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1434 | clocks = <&clks 162>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 1435 | fsl,usbmisc = <&usbmisc 2>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1436 | status = "disabled"; |
| 1437 | }; |
| 1438 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1439 | usbh3: usb@02184600 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1440 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 1441 | reg = <0x02184600 0x200>; |
| 1442 | interrupts = <0 42 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1443 | clocks = <&clks 162>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 1444 | fsl,usbmisc = <&usbmisc 3>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 1445 | status = "disabled"; |
| 1446 | }; |
| 1447 | |
Shawn Guo | 60984bd | 2013-04-28 09:59:54 +0800 | [diff] [blame] | 1448 | usbmisc: usbmisc@02184800 { |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 1449 | #index-cells = <1>; |
| 1450 | compatible = "fsl,imx6q-usbmisc"; |
| 1451 | reg = <0x02184800 0x200>; |
| 1452 | clocks = <&clks 162>; |
| 1453 | }; |
| 1454 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1455 | fec: ethernet@02188000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1456 | compatible = "fsl,imx6q-fec"; |
| 1457 | reg = <0x02188000 0x4000>; |
| 1458 | interrupts = <0 118 0x04 0 119 0x04>; |
Frank Li | 8dd5c66 | 2013-02-05 14:21:06 +0800 | [diff] [blame] | 1459 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
Frank Li | 7629838 | 2012-10-30 18:24:57 +0000 | [diff] [blame] | 1460 | clock-names = "ipg", "ahb", "ptp"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1461 | status = "disabled"; |
| 1462 | }; |
| 1463 | |
| 1464 | mlb@0218c000 { |
| 1465 | reg = <0x0218c000 0x4000>; |
| 1466 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; |
| 1467 | }; |
| 1468 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1469 | usdhc1: usdhc@02190000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1470 | compatible = "fsl,imx6q-usdhc"; |
| 1471 | reg = <0x02190000 0x4000>; |
| 1472 | interrupts = <0 22 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1473 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
| 1474 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 1475 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1476 | status = "disabled"; |
| 1477 | }; |
| 1478 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1479 | usdhc2: usdhc@02194000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1480 | compatible = "fsl,imx6q-usdhc"; |
| 1481 | reg = <0x02194000 0x4000>; |
| 1482 | interrupts = <0 23 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1483 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
| 1484 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 1485 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1486 | status = "disabled"; |
| 1487 | }; |
| 1488 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1489 | usdhc3: usdhc@02198000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1490 | compatible = "fsl,imx6q-usdhc"; |
| 1491 | reg = <0x02198000 0x4000>; |
| 1492 | interrupts = <0 24 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1493 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
| 1494 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 1495 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1496 | status = "disabled"; |
| 1497 | }; |
| 1498 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1499 | usdhc4: usdhc@0219c000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1500 | compatible = "fsl,imx6q-usdhc"; |
| 1501 | reg = <0x0219c000 0x4000>; |
| 1502 | interrupts = <0 25 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1503 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
| 1504 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 1505 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1506 | status = "disabled"; |
| 1507 | }; |
| 1508 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1509 | i2c1: i2c@021a0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1510 | #address-cells = <1>; |
| 1511 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 1512 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1513 | reg = <0x021a0000 0x4000>; |
| 1514 | interrupts = <0 36 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1515 | clocks = <&clks 125>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1516 | status = "disabled"; |
| 1517 | }; |
| 1518 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1519 | i2c2: i2c@021a4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1520 | #address-cells = <1>; |
| 1521 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 1522 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1523 | reg = <0x021a4000 0x4000>; |
| 1524 | interrupts = <0 37 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1525 | clocks = <&clks 126>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1526 | status = "disabled"; |
| 1527 | }; |
| 1528 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1529 | i2c3: i2c@021a8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1530 | #address-cells = <1>; |
| 1531 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 1532 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1533 | reg = <0x021a8000 0x4000>; |
| 1534 | interrupts = <0 38 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1535 | clocks = <&clks 127>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1536 | status = "disabled"; |
| 1537 | }; |
| 1538 | |
| 1539 | romcp@021ac000 { |
| 1540 | reg = <0x021ac000 0x4000>; |
| 1541 | }; |
| 1542 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1543 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1544 | compatible = "fsl,imx6q-mmdc"; |
| 1545 | reg = <0x021b0000 0x4000>; |
| 1546 | }; |
| 1547 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1548 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1549 | reg = <0x021b4000 0x4000>; |
| 1550 | }; |
| 1551 | |
Huang Shijie | 05e3f8e | 2013-05-28 14:20:09 +0800 | [diff] [blame] | 1552 | weim: weim@021b8000 { |
| 1553 | compatible = "fsl,imx6q-weim"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1554 | reg = <0x021b8000 0x4000>; |
| 1555 | interrupts = <0 14 0x04>; |
Huang Shijie | 05e3f8e | 2013-05-28 14:20:09 +0800 | [diff] [blame] | 1556 | clocks = <&clks 196>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1557 | }; |
| 1558 | |
Shawn Guo | 3fe6373 | 2013-07-16 21:16:36 +0800 | [diff] [blame] | 1559 | ocotp: ocotp@021bc000 { |
| 1560 | compatible = "fsl,imx6q-ocotp", "syscon"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1561 | reg = <0x021bc000 0x4000>; |
| 1562 | }; |
| 1563 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1564 | tzasc@021d0000 { /* TZASC1 */ |
| 1565 | reg = <0x021d0000 0x4000>; |
| 1566 | interrupts = <0 108 0x04>; |
| 1567 | }; |
| 1568 | |
| 1569 | tzasc@021d4000 { /* TZASC2 */ |
| 1570 | reg = <0x021d4000 0x4000>; |
| 1571 | interrupts = <0 109 0x04>; |
| 1572 | }; |
| 1573 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1574 | audmux: audmux@021d8000 { |
Richard Zhao | f965cd5 | 2012-05-02 10:32:26 +0800 | [diff] [blame] | 1575 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1576 | reg = <0x021d8000 0x4000>; |
Richard Zhao | f965cd5 | 2012-05-02 10:32:26 +0800 | [diff] [blame] | 1577 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1578 | }; |
| 1579 | |
| 1580 | mipi@021dc000 { /* MIPI-CSI */ |
| 1581 | reg = <0x021dc000 0x4000>; |
| 1582 | }; |
| 1583 | |
| 1584 | mipi@021e0000 { /* MIPI-DSI */ |
| 1585 | reg = <0x021e0000 0x4000>; |
| 1586 | }; |
| 1587 | |
| 1588 | vdoa@021e4000 { |
| 1589 | reg = <0x021e4000 0x4000>; |
| 1590 | interrupts = <0 18 0x04>; |
| 1591 | }; |
| 1592 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1593 | uart2: serial@021e8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1594 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1595 | reg = <0x021e8000 0x4000>; |
| 1596 | interrupts = <0 27 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1597 | clocks = <&clks 160>, <&clks 161>; |
| 1598 | clock-names = "ipg", "per"; |
Huang Shijie | 72a5ceb | 2013-07-12 18:02:09 +0800 | [diff] [blame] | 1599 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| 1600 | dma-names = "rx", "tx"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1601 | status = "disabled"; |
| 1602 | }; |
| 1603 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1604 | uart3: serial@021ec000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1605 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1606 | reg = <0x021ec000 0x4000>; |
| 1607 | interrupts = <0 28 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1608 | clocks = <&clks 160>, <&clks 161>; |
| 1609 | clock-names = "ipg", "per"; |
Huang Shijie | 72a5ceb | 2013-07-12 18:02:09 +0800 | [diff] [blame] | 1610 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| 1611 | dma-names = "rx", "tx"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1612 | status = "disabled"; |
| 1613 | }; |
| 1614 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1615 | uart4: serial@021f0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1616 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1617 | reg = <0x021f0000 0x4000>; |
| 1618 | interrupts = <0 29 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1619 | clocks = <&clks 160>, <&clks 161>; |
| 1620 | clock-names = "ipg", "per"; |
Huang Shijie | 72a5ceb | 2013-07-12 18:02:09 +0800 | [diff] [blame] | 1621 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| 1622 | dma-names = "rx", "tx"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1623 | status = "disabled"; |
| 1624 | }; |
| 1625 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1626 | uart5: serial@021f4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1627 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1628 | reg = <0x021f4000 0x4000>; |
| 1629 | interrupts = <0 30 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1630 | clocks = <&clks 160>, <&clks 161>; |
| 1631 | clock-names = "ipg", "per"; |
Huang Shijie | 72a5ceb | 2013-07-12 18:02:09 +0800 | [diff] [blame] | 1632 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| 1633 | dma-names = "rx", "tx"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1634 | status = "disabled"; |
| 1635 | }; |
| 1636 | }; |
Sascha Hauer | 91660d7 | 2012-11-12 15:52:21 +0100 | [diff] [blame] | 1637 | |
| 1638 | ipu1: ipu@02400000 { |
| 1639 | #crtc-cells = <1>; |
| 1640 | compatible = "fsl,imx6q-ipu"; |
| 1641 | reg = <0x02400000 0x400000>; |
| 1642 | interrupts = <0 6 0x4 0 5 0x4>; |
| 1643 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; |
| 1644 | clock-names = "bus", "di0", "di1"; |
Philipp Zabel | 09ebf36 | 2013-03-28 17:35:20 +0100 | [diff] [blame] | 1645 | resets = <&src 2>; |
Sascha Hauer | 91660d7 | 2012-11-12 15:52:21 +0100 | [diff] [blame] | 1646 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1647 | }; |
| 1648 | }; |