Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __MSM_DRV_H__ |
| 20 | #define __MSM_DRV_H__ |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/cpufreq.h> |
| 25 | #include <linux/module.h> |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 26 | #include <linux/component.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/pm.h> |
| 29 | #include <linux/pm_runtime.h> |
| 30 | #include <linux/slab.h> |
| 31 | #include <linux/list.h> |
| 32 | #include <linux/iommu.h> |
| 33 | #include <linux/types.h> |
Archit Taneja | 3d6df06 | 2015-06-09 14:17:22 +0530 | [diff] [blame] | 34 | #include <linux/of_graph.h> |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 35 | #include <linux/of_device.h> |
Dhaval Patel | 1ac9103 | 2016-09-26 19:25:39 -0700 | [diff] [blame] | 36 | #include <linux/sde_io_util.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 37 | #include <asm/sizes.h> |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 38 | #include <linux/kthread.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 39 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 40 | #include <drm/drmP.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 41 | #include <drm/drm_atomic.h> |
| 42 | #include <drm/drm_atomic_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 43 | #include <drm/drm_crtc_helper.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 44 | #include <drm/drm_plane_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 45 | #include <drm/drm_fb_helper.h> |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 46 | #include <drm/msm_drm.h> |
Daniel Vetter | d9fc941 | 2014-09-23 15:46:53 +0200 | [diff] [blame] | 47 | #include <drm/drm_gem.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 48 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 49 | #include "sde_power_handle.h" |
| 50 | |
| 51 | #define GET_MAJOR_REV(rev) ((rev) >> 28) |
| 52 | #define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF) |
| 53 | #define GET_STEP_REV(rev) ((rev) & 0xFFFF) |
Lloyd Atkinson | 154b6aa | 2016-05-24 17:11:37 -0400 | [diff] [blame] | 54 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 55 | struct msm_kms; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 56 | struct msm_gpu; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 57 | struct msm_mmu; |
Archit Taneja | 990a400 | 2016-05-07 23:11:25 +0530 | [diff] [blame] | 58 | struct msm_mdss; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 59 | struct msm_rd_state; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 60 | struct msm_perf_state; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 61 | struct msm_gem_submit; |
Rob Clark | ca762a8 | 2016-03-15 17:22:13 -0400 | [diff] [blame] | 62 | struct msm_fence_context; |
Rob Clark | fde5de6 | 2016-03-15 15:35:08 -0400 | [diff] [blame] | 63 | struct msm_fence_cb; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 64 | |
Alan Kwong | 112a84f | 2016-05-24 20:49:21 -0400 | [diff] [blame] | 65 | #define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 66 | #define MAX_CRTCS 8 |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 67 | #define MAX_PLANES 20 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 68 | #define MAX_ENCODERS 8 |
| 69 | #define MAX_BRIDGES 8 |
| 70 | #define MAX_CONNECTORS 8 |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 71 | |
| 72 | struct msm_file_private { |
| 73 | /* currently we don't do anything useful with this.. but when |
| 74 | * per-context address spaces are supported we'd keep track of |
| 75 | * the context's page-tables here. |
| 76 | */ |
| 77 | int dummy; |
| 78 | }; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 79 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 80 | enum msm_mdp_plane_property { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 81 | /* blob properties, always put these first */ |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 82 | PLANE_PROP_SCALER_V1, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 83 | PLANE_PROP_SCALER_V2, |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 84 | PLANE_PROP_CSC_V1, |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 85 | PLANE_PROP_INFO, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 86 | PLANE_PROP_SCALER_LUT_ED, |
| 87 | PLANE_PROP_SCALER_LUT_CIR, |
| 88 | PLANE_PROP_SCALER_LUT_SEP, |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 89 | PLANE_PROP_SKIN_COLOR, |
| 90 | PLANE_PROP_SKY_COLOR, |
| 91 | PLANE_PROP_FOLIAGE_COLOR, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 92 | |
| 93 | /* # of blob properties */ |
| 94 | PLANE_PROP_BLOBCOUNT, |
| 95 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 96 | /* range properties */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 97 | PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT, |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 98 | PLANE_PROP_ALPHA, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 99 | PLANE_PROP_COLOR_FILL, |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 100 | PLANE_PROP_H_DECIMATE, |
| 101 | PLANE_PROP_V_DECIMATE, |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 102 | PLANE_PROP_INPUT_FENCE, |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 103 | PLANE_PROP_HUE_ADJUST, |
| 104 | PLANE_PROP_SATURATION_ADJUST, |
| 105 | PLANE_PROP_VALUE_ADJUST, |
| 106 | PLANE_PROP_CONTRAST_ADJUST, |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 107 | PLANE_PROP_EXCL_RECT_V1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 108 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 109 | /* enum/bitmask properties */ |
| 110 | PLANE_PROP_ROTATION, |
| 111 | PLANE_PROP_BLEND_OP, |
| 112 | PLANE_PROP_SRC_CONFIG, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 113 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 114 | /* total # of properties */ |
| 115 | PLANE_PROP_COUNT |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 116 | }; |
| 117 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 118 | enum msm_mdp_crtc_property { |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 119 | CRTC_PROP_INFO, |
| 120 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 121 | /* # of blob properties */ |
| 122 | CRTC_PROP_BLOBCOUNT, |
| 123 | |
| 124 | /* range properties */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 125 | CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT, |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 126 | CRTC_PROP_OUTPUT_FENCE, |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 127 | CRTC_PROP_OUTPUT_FENCE_OFFSET, |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 128 | CRTC_PROP_DIM_LAYER_V1, |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 129 | CRTC_PROP_CORE_CLK, |
| 130 | CRTC_PROP_CORE_AB, |
| 131 | CRTC_PROP_CORE_IB, |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 132 | |
| 133 | /* total # of properties */ |
| 134 | CRTC_PROP_COUNT |
| 135 | }; |
| 136 | |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 137 | enum msm_mdp_conn_property { |
| 138 | /* blob properties, always put these first */ |
| 139 | CONNECTOR_PROP_SDE_INFO, |
| 140 | |
| 141 | /* # of blob properties */ |
| 142 | CONNECTOR_PROP_BLOBCOUNT, |
| 143 | |
| 144 | /* range properties */ |
| 145 | CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT, |
| 146 | CONNECTOR_PROP_RETIRE_FENCE, |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 147 | CONNECTOR_PROP_DST_X, |
| 148 | CONNECTOR_PROP_DST_Y, |
| 149 | CONNECTOR_PROP_DST_W, |
| 150 | CONNECTOR_PROP_DST_H, |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 151 | |
| 152 | /* enum/bitmask properties */ |
Lloyd Atkinson | b619197 | 2016-08-10 18:31:46 -0400 | [diff] [blame] | 153 | CONNECTOR_PROP_TOPOLOGY_NAME, |
| 154 | CONNECTOR_PROP_TOPOLOGY_CONTROL, |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 155 | |
| 156 | /* total # of properties */ |
| 157 | CONNECTOR_PROP_COUNT |
| 158 | }; |
| 159 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 160 | struct msm_vblank_ctrl { |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 161 | struct kthread_work work; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 162 | struct list_head event_list; |
| 163 | spinlock_t lock; |
| 164 | }; |
| 165 | |
Clarence Ip | a403932 | 2016-07-15 16:23:59 -0400 | [diff] [blame] | 166 | #define MAX_H_TILES_PER_DISPLAY 2 |
| 167 | |
| 168 | /** |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 169 | * enum msm_display_compression_type - compression method used for pixel stream |
| 170 | * @MSM_DISPLAY_COMPRESSION_NONE: Pixel data is not compressed |
| 171 | * @MSM_DISPLAY_COMPRESSION_DSC: DSC compresison is used |
Clarence Ip | a403932 | 2016-07-15 16:23:59 -0400 | [diff] [blame] | 172 | */ |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 173 | enum msm_display_compression_type { |
| 174 | MSM_DISPLAY_COMPRESSION_NONE, |
| 175 | MSM_DISPLAY_COMPRESSION_DSC, |
Clarence Ip | a403932 | 2016-07-15 16:23:59 -0400 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | /** |
| 179 | * enum msm_display_caps - features/capabilities supported by displays |
| 180 | * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported |
| 181 | * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported |
| 182 | * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported |
| 183 | * @MSM_DISPLAY_CAP_EDID: EDID supported |
| 184 | */ |
| 185 | enum msm_display_caps { |
| 186 | MSM_DISPLAY_CAP_VID_MODE = BIT(0), |
| 187 | MSM_DISPLAY_CAP_CMD_MODE = BIT(1), |
| 188 | MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), |
| 189 | MSM_DISPLAY_CAP_EDID = BIT(3), |
| 190 | }; |
| 191 | |
| 192 | /** |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 193 | * struct msm_display_dsc_info - defines dsc configuration |
| 194 | * @version: DSC version. |
| 195 | * @scr_rev: DSC revision. |
| 196 | * @pic_height: Picture height in pixels. |
| 197 | * @pic_width: Picture width in pixels. |
| 198 | * @initial_lines: Number of initial lines stored in encoder. |
| 199 | * @pkt_per_line: Number of packets per line. |
| 200 | * @bytes_in_slice: Number of bytes in slice. |
| 201 | * @eol_byte_num: Valid bytes at the end of line. |
| 202 | * @pclk_per_line: Compressed width. |
| 203 | * @full_frame_slices: Number of slice per interface. |
| 204 | * @slice_height: Slice height in pixels. |
| 205 | * @slice_width: Slice width in pixels. |
| 206 | * @chunk_size: Chunk size in bytes for slice multiplexing. |
| 207 | * @slice_last_group_size: Size of last group in pixels. |
| 208 | * @bpp: Target bits per pixel. |
| 209 | * @bpc: Number of bits per component. |
| 210 | * @line_buf_depth: Line buffer bit depth. |
| 211 | * @block_pred_enable: Block prediction enabled/disabled. |
| 212 | * @vbr_enable: VBR mode. |
| 213 | * @enable_422: Indicates if input uses 4:2:2 sampling. |
| 214 | * @convert_rgb: DSC color space conversion. |
| 215 | * @input_10_bits: 10 bit per component input. |
| 216 | * @slice_per_pkt: Number of slices per packet. |
| 217 | * @initial_dec_delay: Initial decoding delay. |
| 218 | * @initial_xmit_delay: Initial transmission delay. |
| 219 | * @initial_scale_value: Scale factor value at the beginning of a slice. |
| 220 | * @scale_decrement_interval: Scale set up at the beginning of a slice. |
| 221 | * @scale_increment_interval: Scale set up at the end of a slice. |
| 222 | * @first_line_bpg_offset: Extra bits allocated on the first line of a slice. |
| 223 | * @nfl_bpg_offset: Slice specific settings. |
| 224 | * @slice_bpg_offset: Slice specific settings. |
| 225 | * @initial_offset: Initial offset at the start of a slice. |
| 226 | * @final_offset: Maximum end-of-slice value. |
| 227 | * @rc_model_size: Number of bits in RC model. |
| 228 | * @det_thresh_flatness: Flatness threshold. |
| 229 | * @max_qp_flatness: Maximum QP for flatness adjustment. |
| 230 | * @min_qp_flatness: Minimum QP for flatness adjustment. |
| 231 | * @edge_factor: Ratio to detect presence of edge. |
| 232 | * @quant_incr_limit0: QP threshold. |
| 233 | * @quant_incr_limit1: QP threshold. |
| 234 | * @tgt_offset_hi: Upper end of variability range. |
| 235 | * @tgt_offset_lo: Lower end of variability range. |
| 236 | * @buf_thresh: Thresholds in RC model |
| 237 | * @range_min_qp: Min QP allowed. |
| 238 | * @range_max_qp: Max QP allowed. |
| 239 | * @range_bpg_offset: Bits per group adjustment. |
| 240 | */ |
| 241 | struct msm_display_dsc_info { |
| 242 | u8 version; |
| 243 | u8 scr_rev; |
| 244 | |
| 245 | int pic_height; |
| 246 | int pic_width; |
| 247 | int slice_height; |
| 248 | int slice_width; |
| 249 | |
| 250 | int initial_lines; |
| 251 | int pkt_per_line; |
| 252 | int bytes_in_slice; |
| 253 | int bytes_per_pkt; |
| 254 | int eol_byte_num; |
| 255 | int pclk_per_line; |
| 256 | int full_frame_slices; |
| 257 | int slice_last_group_size; |
| 258 | int bpp; |
| 259 | int bpc; |
| 260 | int line_buf_depth; |
| 261 | |
| 262 | int slice_per_pkt; |
| 263 | int chunk_size; |
| 264 | bool block_pred_enable; |
| 265 | int vbr_enable; |
| 266 | int enable_422; |
| 267 | int convert_rgb; |
| 268 | int input_10_bits; |
| 269 | |
| 270 | int initial_dec_delay; |
| 271 | int initial_xmit_delay; |
| 272 | int initial_scale_value; |
| 273 | int scale_decrement_interval; |
| 274 | int scale_increment_interval; |
| 275 | int first_line_bpg_offset; |
| 276 | int nfl_bpg_offset; |
| 277 | int slice_bpg_offset; |
| 278 | int initial_offset; |
| 279 | int final_offset; |
| 280 | |
| 281 | int rc_model_size; |
| 282 | int det_thresh_flatness; |
| 283 | int max_qp_flatness; |
| 284 | int min_qp_flatness; |
| 285 | int edge_factor; |
| 286 | int quant_incr_limit0; |
| 287 | int quant_incr_limit1; |
| 288 | int tgt_offset_hi; |
| 289 | int tgt_offset_lo; |
| 290 | |
| 291 | u32 *buf_thresh; |
| 292 | char *range_min_qp; |
| 293 | char *range_max_qp; |
| 294 | char *range_bpg_offset; |
| 295 | }; |
| 296 | |
| 297 | /** |
| 298 | * struct msm_compression_info - defined panel compression |
| 299 | * @comp_type: type of compression supported |
| 300 | * @dsc_info: dsc configuration if the compression |
| 301 | * supported is DSC |
| 302 | */ |
| 303 | struct msm_compression_info { |
| 304 | enum msm_display_compression_type comp_type; |
| 305 | |
| 306 | union{ |
| 307 | struct msm_display_dsc_info dsc_info; |
| 308 | }; |
| 309 | }; |
| 310 | |
| 311 | /** |
Clarence Ip | a403932 | 2016-07-15 16:23:59 -0400 | [diff] [blame] | 312 | * struct msm_display_info - defines display properties |
| 313 | * @intf_type: DRM_MODE_CONNECTOR_ display type |
| 314 | * @capabilities: Bitmask of display flags |
| 315 | * @num_of_h_tiles: Number of horizontal tiles in case of split interface |
| 316 | * @h_tile_instance: Controller instance used per tile. Number of elements is |
| 317 | * based on num_of_h_tiles |
| 318 | * @is_connected: Set to true if display is connected |
| 319 | * @width_mm: Physical width |
| 320 | * @height_mm: Physical height |
| 321 | * @max_width: Max width of display. In case of hot pluggable display |
| 322 | * this is max width supported by controller |
| 323 | * @max_height: Max height of display. In case of hot pluggable display |
| 324 | * this is max height supported by controller |
Dhaval Patel | 60e1ff5 | 2017-02-18 21:03:40 -0800 | [diff] [blame] | 325 | * @is_primary: Set to true if display is primary display |
| 326 | * @frame_rate: Display frame rate |
| 327 | * @prefill_lines: prefill lines based on porches. |
| 328 | * @vtotal: display vertical total |
| 329 | * @jitter: display jitter configuration |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 330 | * @comp_info: Compression supported by the display |
Clarence Ip | a403932 | 2016-07-15 16:23:59 -0400 | [diff] [blame] | 331 | */ |
| 332 | struct msm_display_info { |
| 333 | int intf_type; |
| 334 | uint32_t capabilities; |
| 335 | |
| 336 | uint32_t num_of_h_tiles; |
| 337 | uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; |
| 338 | |
| 339 | bool is_connected; |
| 340 | |
| 341 | unsigned int width_mm; |
| 342 | unsigned int height_mm; |
| 343 | |
| 344 | uint32_t max_width; |
| 345 | uint32_t max_height; |
| 346 | |
Dhaval Patel | 60e1ff5 | 2017-02-18 21:03:40 -0800 | [diff] [blame] | 347 | bool is_primary; |
| 348 | uint32_t frame_rate; |
| 349 | uint32_t prefill_lines; |
| 350 | uint32_t vtotal; |
| 351 | uint32_t jitter; |
| 352 | |
Alexander Beykun | ac18235 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 353 | struct msm_compression_info comp_info; |
Clarence Ip | a403932 | 2016-07-15 16:23:59 -0400 | [diff] [blame] | 354 | }; |
| 355 | |
Clarence Ip | 3649f8b | 2016-10-31 09:59:44 -0400 | [diff] [blame] | 356 | /** |
| 357 | * struct msm_drm_event - defines custom event notification struct |
| 358 | * @base: base object required for event notification by DRM framework. |
| 359 | * @event: event object required for event notification by DRM framework. |
| 360 | * @info: contains information of DRM object for which events has been |
| 361 | * requested. |
| 362 | * @data: memory location which contains response payload for event. |
| 363 | */ |
| 364 | struct msm_drm_event { |
| 365 | struct drm_pending_event base; |
| 366 | struct drm_event event; |
Clarence Ip | 3649f8b | 2016-10-31 09:59:44 -0400 | [diff] [blame] | 367 | u8 data[]; |
| 368 | }; |
Ajay Singh Parmar | 64c1919 | 2016-06-10 16:44:56 -0700 | [diff] [blame] | 369 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 370 | /* Commit thread specific structure */ |
| 371 | struct msm_drm_commit { |
| 372 | struct drm_device *dev; |
| 373 | struct task_struct *thread; |
| 374 | unsigned int crtc_id; |
| 375 | struct kthread_worker worker; |
| 376 | }; |
| 377 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 378 | struct msm_drm_private { |
| 379 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 380 | struct drm_device *dev; |
| 381 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 382 | struct msm_kms *kms; |
| 383 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 384 | struct sde_power_handle phandle; |
| 385 | struct sde_power_client *pclient; |
| 386 | |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 387 | /* subordinate devices, if present: */ |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 388 | struct platform_device *gpu_pdev; |
| 389 | |
Archit Taneja | 990a400 | 2016-05-07 23:11:25 +0530 | [diff] [blame] | 390 | /* top level MDSS wrapper device (for MDP5 only) */ |
| 391 | struct msm_mdss *mdss; |
| 392 | |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 393 | /* possibly this should be in the kms component, but it is |
| 394 | * shared by both mdp4 and mdp5.. |
| 395 | */ |
| 396 | struct hdmi *hdmi; |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 397 | |
Hai Li | ab5b010 | 2015-01-07 18:47:44 -0500 | [diff] [blame] | 398 | /* eDP is for mdp5 only, but kms has not been created |
| 399 | * when edp_bind() and edp_init() are called. Here is the only |
| 400 | * place to keep the edp instance. |
| 401 | */ |
| 402 | struct msm_edp *edp; |
| 403 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 404 | /* DSI is shared by mdp4 and mdp5 */ |
| 405 | struct msm_dsi *dsi[2]; |
| 406 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 407 | /* when we have more than one 'msm_gpu' these need to be an array: */ |
| 408 | struct msm_gpu *gpu; |
| 409 | struct msm_file_private *lastctx; |
| 410 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 411 | struct drm_fb_helper *fbdev; |
| 412 | |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 413 | struct msm_rd_state *rd; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 414 | struct msm_perf_state *perf; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 415 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 416 | /* list of GEM objects: */ |
| 417 | struct list_head inactive_list; |
| 418 | |
| 419 | struct workqueue_struct *wq; |
| 420 | |
Rob Clark | f86afec | 2014-11-25 12:41:18 -0500 | [diff] [blame] | 421 | /* crtcs pending async atomic updates: */ |
| 422 | uint32_t pending_crtcs; |
| 423 | wait_queue_head_t pending_crtcs_event; |
| 424 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 425 | /* registered MMUs: */ |
| 426 | unsigned int num_mmus; |
| 427 | struct msm_mmu *mmus[NUM_DOMAINS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 428 | |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 429 | unsigned int num_planes; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 430 | struct drm_plane *planes[MAX_PLANES]; |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 431 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 432 | unsigned int num_crtcs; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 433 | struct drm_crtc *crtcs[MAX_CRTCS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 434 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 435 | struct msm_drm_commit disp_thread[MAX_CRTCS]; |
| 436 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 437 | unsigned int num_encoders; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 438 | struct drm_encoder *encoders[MAX_ENCODERS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 439 | |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 440 | unsigned int num_bridges; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 441 | struct drm_bridge *bridges[MAX_BRIDGES]; |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 442 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 443 | unsigned int num_connectors; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 444 | struct drm_connector *connectors[MAX_CONNECTORS]; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 445 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 446 | /* Properties */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 447 | struct drm_property *plane_property[PLANE_PROP_COUNT]; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 448 | struct drm_property *crtc_property[CRTC_PROP_COUNT]; |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 449 | struct drm_property *conn_property[CONNECTOR_PROP_COUNT]; |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 450 | |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 451 | /* Color processing properties for the crtc */ |
| 452 | struct drm_property **cp_property; |
| 453 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 454 | /* VRAM carveout, used when no IOMMU: */ |
| 455 | struct { |
| 456 | unsigned long size; |
| 457 | dma_addr_t paddr; |
| 458 | /* NOTE: mm managed at the page level, size is in # of pages |
| 459 | * and position mm_node->start is in # of pages: |
| 460 | */ |
| 461 | struct drm_mm mm; |
| 462 | } vram; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 463 | |
Rob Clark | e1e9db2 | 2016-05-27 11:16:28 -0400 | [diff] [blame] | 464 | struct notifier_block vmap_notifier; |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 465 | struct shrinker shrinker; |
| 466 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 467 | struct msm_vblank_ctrl vblank_ctrl; |
Rob Clark | d78d383 | 2016-08-22 15:28:38 -0400 | [diff] [blame] | 468 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 469 | /* task holding struct_mutex.. currently only used in submit path |
| 470 | * to detect and reject faults from copy_from_user() for submit |
| 471 | * ioctl. |
| 472 | */ |
| 473 | struct task_struct *struct_mutex_task; |
| 474 | |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 475 | /* saved atomic state during system suspend */ |
| 476 | struct drm_atomic_state *suspend_state; |
Clarence Ip | a65cba5 | 2017-03-17 15:18:29 -0400 | [diff] [blame^] | 477 | bool suspend_block; |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 478 | |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 479 | /* list of clients waiting for events */ |
| 480 | struct list_head client_event_list; |
Lloyd Atkinson | ab3dd30 | 2017-02-13 10:44:55 -0800 | [diff] [blame] | 481 | |
| 482 | /* whether registered and drm_dev_unregister should be called */ |
| 483 | bool registered; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 484 | }; |
| 485 | |
| 486 | struct msm_format { |
| 487 | uint32_t pixel_format; |
| 488 | }; |
| 489 | |
Daniel Vetter | b4274fb | 2014-11-26 17:02:18 +0100 | [diff] [blame] | 490 | int msm_atomic_check(struct drm_device *dev, |
| 491 | struct drm_atomic_state *state); |
Dhaval Patel | 7a7d85d | 2016-08-26 16:35:34 -0700 | [diff] [blame] | 492 | /* callback from wq once fence has passed: */ |
| 493 | struct msm_fence_cb { |
| 494 | struct work_struct work; |
| 495 | uint32_t fence; |
| 496 | void (*func)(struct msm_fence_cb *cb); |
| 497 | }; |
| 498 | |
| 499 | void __msm_fence_worker(struct work_struct *work); |
| 500 | |
| 501 | #define INIT_FENCE_CB(_cb, _func) do { \ |
| 502 | INIT_WORK(&(_cb)->work, __msm_fence_worker); \ |
| 503 | (_cb)->func = _func; \ |
| 504 | } while (0) |
| 505 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 506 | static inline bool msm_is_suspend_state(struct drm_device *dev) |
| 507 | { |
| 508 | if (!dev || !dev->dev_private) |
| 509 | return false; |
| 510 | |
| 511 | return ((struct msm_drm_private *)dev->dev_private)->suspend_state != 0; |
| 512 | } |
| 513 | |
Clarence Ip | a65cba5 | 2017-03-17 15:18:29 -0400 | [diff] [blame^] | 514 | static inline bool msm_is_suspend_blocked(struct drm_device *dev) |
| 515 | { |
| 516 | if (!dev || !dev->dev_private) |
| 517 | return false; |
| 518 | |
| 519 | if (!msm_is_suspend_state(dev)) |
| 520 | return false; |
| 521 | |
| 522 | return ((struct msm_drm_private *)dev->dev_private)->suspend_block != 0; |
| 523 | } |
| 524 | |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 525 | int msm_atomic_commit(struct drm_device *dev, |
Maarten Lankhorst | a3ccfb9 | 2016-04-26 16:11:38 +0200 | [diff] [blame] | 526 | struct drm_atomic_state *state, bool nonblock); |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 527 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 528 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); |
Lloyd Atkinson | 1e2497e | 2016-09-26 17:55:48 -0400 | [diff] [blame] | 529 | void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 530 | |
Rob Clark | 40e6815 | 2016-05-03 09:50:26 -0400 | [diff] [blame] | 531 | void msm_gem_submit_free(struct msm_gem_submit *submit); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 532 | int msm_ioctl_gem_submit(struct drm_device *dev, void *data, |
| 533 | struct drm_file *file); |
| 534 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 535 | void msm_gem_shrinker_init(struct drm_device *dev); |
| 536 | void msm_gem_shrinker_cleanup(struct drm_device *dev); |
| 537 | |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 538 | int msm_gem_mmap_obj(struct drm_gem_object *obj, |
| 539 | struct vm_area_struct *vma); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 540 | int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); |
| 541 | int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
| 542 | uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); |
| 543 | int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, |
| 544 | uint32_t *iova); |
| 545 | int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 546 | uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 547 | struct page **msm_gem_get_pages(struct drm_gem_object *obj); |
| 548 | void msm_gem_put_pages(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 549 | void msm_gem_put_iova(struct drm_gem_object *obj, int id); |
| 550 | int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, |
| 551 | struct drm_mode_create_dumb *args); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 552 | int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, |
| 553 | uint32_t handle, uint64_t *offset); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 554 | struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); |
| 555 | void *msm_gem_prime_vmap(struct drm_gem_object *obj); |
| 556 | void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 557 | int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 558 | struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, |
Maarten Lankhorst | b5e9c1a | 2014-01-09 11:03:14 +0100 | [diff] [blame] | 559 | struct dma_buf_attachment *attach, struct sg_table *sg); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 560 | int msm_gem_prime_pin(struct drm_gem_object *obj); |
| 561 | void msm_gem_prime_unpin(struct drm_gem_object *obj); |
Rob Clark | 18f2304 | 2016-05-26 16:24:35 -0400 | [diff] [blame] | 562 | void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj); |
| 563 | void *msm_gem_get_vaddr(struct drm_gem_object *obj); |
| 564 | void msm_gem_put_vaddr_locked(struct drm_gem_object *obj); |
| 565 | void msm_gem_put_vaddr(struct drm_gem_object *obj); |
Rob Clark | 4cd33c4 | 2016-05-17 15:44:49 -0400 | [diff] [blame] | 566 | int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 567 | void msm_gem_purge(struct drm_gem_object *obj); |
Rob Clark | e1e9db2 | 2016-05-27 11:16:28 -0400 | [diff] [blame] | 568 | void msm_gem_vunmap(struct drm_gem_object *obj); |
Rob Clark | b6295f9 | 2016-03-15 18:26:28 -0400 | [diff] [blame] | 569 | int msm_gem_sync_object(struct drm_gem_object *obj, |
| 570 | struct msm_fence_context *fctx, bool exclusive); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 571 | void msm_gem_move_to_active(struct drm_gem_object *obj, |
Rob Clark | b6295f9 | 2016-03-15 18:26:28 -0400 | [diff] [blame] | 572 | struct msm_gpu *gpu, bool exclusive, struct fence *fence); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 573 | void msm_gem_move_to_inactive(struct drm_gem_object *obj); |
Rob Clark | ba00c3f | 2016-03-16 18:18:17 -0400 | [diff] [blame] | 574 | int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 575 | int msm_gem_cpu_fini(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 576 | void msm_gem_free_object(struct drm_gem_object *obj); |
| 577 | int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, |
| 578 | uint32_t size, uint32_t flags, uint32_t *handle); |
| 579 | struct drm_gem_object *msm_gem_new(struct drm_device *dev, |
| 580 | uint32_t size, uint32_t flags); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 581 | struct drm_gem_object *msm_gem_import(struct drm_device *dev, |
Rob Clark | 79f0e20 | 2016-03-16 12:40:35 -0400 | [diff] [blame] | 582 | struct dma_buf *dmabuf, struct sg_table *sgt); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 583 | |
Alan Kwong | 578cdaf | 2017-01-28 17:25:43 -0800 | [diff] [blame] | 584 | void msm_framebuffer_set_kmap(struct drm_framebuffer *fb, bool enable); |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 585 | int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); |
| 586 | void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); |
| 587 | uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 588 | struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); |
| 589 | const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); |
| 590 | struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 591 | const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 592 | struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 593 | struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 594 | |
| 595 | struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 596 | void msm_fbdev_free(struct drm_device *dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 597 | |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 598 | struct hdmi; |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 599 | int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 600 | struct drm_encoder *encoder); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 601 | void __init msm_hdmi_register(void); |
| 602 | void __exit msm_hdmi_unregister(void); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 603 | |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 604 | struct msm_edp; |
| 605 | void __init msm_edp_register(void); |
| 606 | void __exit msm_edp_unregister(void); |
| 607 | int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, |
| 608 | struct drm_encoder *encoder); |
| 609 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 610 | struct msm_dsi; |
| 611 | enum msm_dsi_encoder_id { |
| 612 | MSM_DSI_VIDEO_ENCODER_ID = 0, |
| 613 | MSM_DSI_CMD_ENCODER_ID = 1, |
| 614 | MSM_DSI_ENCODER_NUM = 2 |
| 615 | }; |
| 616 | #ifdef CONFIG_DRM_MSM_DSI |
| 617 | void __init msm_dsi_register(void); |
| 618 | void __exit msm_dsi_unregister(void); |
| 619 | int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, |
| 620 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]); |
| 621 | #else |
| 622 | static inline void __init msm_dsi_register(void) |
| 623 | { |
| 624 | } |
| 625 | static inline void __exit msm_dsi_unregister(void) |
| 626 | { |
| 627 | } |
| 628 | static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, |
| 629 | struct drm_device *dev, |
| 630 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]) |
| 631 | { |
| 632 | return -EINVAL; |
| 633 | } |
| 634 | #endif |
| 635 | |
Archit Taneja | 1dd0a0b | 2016-05-30 16:36:50 +0530 | [diff] [blame] | 636 | void __init msm_mdp_register(void); |
| 637 | void __exit msm_mdp_unregister(void); |
| 638 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 639 | #ifdef CONFIG_DEBUG_FS |
| 640 | void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); |
| 641 | void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); |
| 642 | void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 643 | int msm_debugfs_late_init(struct drm_device *dev); |
| 644 | int msm_rd_debugfs_init(struct drm_minor *minor); |
| 645 | void msm_rd_debugfs_cleanup(struct drm_minor *minor); |
| 646 | void msm_rd_dump_submit(struct msm_gem_submit *submit); |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 647 | int msm_perf_debugfs_init(struct drm_minor *minor); |
| 648 | void msm_perf_debugfs_cleanup(struct drm_minor *minor); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 649 | #else |
| 650 | static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } |
| 651 | static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 652 | #endif |
| 653 | |
| 654 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
| 655 | const char *dbgname); |
Lloyd Atkinson | 1a0c917 | 2016-10-04 10:01:24 -0400 | [diff] [blame] | 656 | void msm_iounmap(struct platform_device *dev, void __iomem *addr); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 657 | void msm_writel(u32 data, void __iomem *addr); |
| 658 | u32 msm_readl(const void __iomem *addr); |
| 659 | |
| 660 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 661 | #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 662 | |
| 663 | static inline int align_pitch(int width, int bpp) |
| 664 | { |
| 665 | int bytespp = (bpp + 7) / 8; |
| 666 | /* adreno needs pitch aligned to 32 pixels: */ |
| 667 | return bytespp * ALIGN(width, 32); |
| 668 | } |
| 669 | |
| 670 | /* for the generated headers: */ |
| 671 | #define INVALID_IDX(idx) ({BUG(); 0;}) |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 672 | #define fui(x) ({BUG(); 0;}) |
| 673 | #define util_float_to_half(x) ({BUG(); 0;}) |
| 674 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 675 | |
| 676 | #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) |
| 677 | |
| 678 | /* for conditionally setting boolean flag(s): */ |
| 679 | #define COND(bool, val) ((bool) ? (val) : 0) |
| 680 | |
Rob Clark | 340ff41 | 2016-03-16 14:57:22 -0400 | [diff] [blame] | 681 | static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) |
| 682 | { |
| 683 | ktime_t now = ktime_get(); |
| 684 | unsigned long remaining_jiffies; |
| 685 | |
| 686 | if (ktime_compare(*timeout, now) < 0) { |
| 687 | remaining_jiffies = 0; |
| 688 | } else { |
| 689 | ktime_t rem = ktime_sub(*timeout, now); |
| 690 | struct timespec ts = ktime_to_timespec(rem); |
| 691 | remaining_jiffies = timespec_to_jiffies(&ts); |
| 692 | } |
| 693 | |
| 694 | return remaining_jiffies; |
| 695 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 696 | |
| 697 | #endif /* __MSM_DRV_H__ */ |