Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 29 | #include <linux/sysrq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "i915_drm.h" |
| 33 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 34 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 39 | /** |
| 40 | * Interrupts that are always left unmasked. |
| 41 | * |
| 42 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
| 43 | * we leave them always unmasked in IMR and then control enabling them through |
| 44 | * PIPESTAT alone. |
| 45 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 46 | #define I915_INTERRUPT_ENABLE_FIX \ |
| 47 | (I915_ASLE_INTERRUPT | \ |
| 48 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 49 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
| 50 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ |
| 51 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ |
| 52 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 53 | |
| 54 | /** Interrupts that we mask and unmask at runtime. */ |
| 55 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) |
| 56 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 57 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 58 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 59 | |
| 60 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 61 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 62 | |
| 63 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 64 | DRM_I915_VBLANK_PIPE_B) |
| 65 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 66 | void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 67 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 68 | { |
| 69 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { |
| 70 | dev_priv->gt_irq_mask_reg &= ~mask; |
| 71 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 72 | (void) I915_READ(GTIMR); |
| 73 | } |
| 74 | } |
| 75 | |
| 76 | static inline void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 77 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 78 | { |
| 79 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { |
| 80 | dev_priv->gt_irq_mask_reg |= mask; |
| 81 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 82 | (void) I915_READ(GTIMR); |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | /* For display hotplug interrupt */ |
| 87 | void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 88 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 89 | { |
| 90 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 91 | dev_priv->irq_mask_reg &= ~mask; |
| 92 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 93 | (void) I915_READ(DEIMR); |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | static inline void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 98 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 99 | { |
| 100 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 101 | dev_priv->irq_mask_reg |= mask; |
| 102 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 103 | (void) I915_READ(DEIMR); |
| 104 | } |
| 105 | } |
| 106 | |
| 107 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 108 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 109 | { |
| 110 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 111 | dev_priv->irq_mask_reg &= ~mask; |
| 112 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 113 | (void) I915_READ(IMR); |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | static inline void |
| 118 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 119 | { |
| 120 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 121 | dev_priv->irq_mask_reg |= mask; |
| 122 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 123 | (void) I915_READ(IMR); |
| 124 | } |
| 125 | } |
| 126 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 127 | static inline u32 |
| 128 | i915_pipestat(int pipe) |
| 129 | { |
| 130 | if (pipe == 0) |
| 131 | return PIPEASTAT; |
| 132 | if (pipe == 1) |
| 133 | return PIPEBSTAT; |
Andrew Morton | 9c84ba4 | 2008-12-01 13:14:08 -0800 | [diff] [blame] | 134 | BUG(); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | void |
| 138 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 139 | { |
| 140 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
| 141 | u32 reg = i915_pipestat(pipe); |
| 142 | |
| 143 | dev_priv->pipestat[pipe] |= mask; |
| 144 | /* Enable the interrupt, clear any pending status */ |
| 145 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
| 146 | (void) I915_READ(reg); |
| 147 | } |
| 148 | } |
| 149 | |
| 150 | void |
| 151 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 152 | { |
| 153 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
| 154 | u32 reg = i915_pipestat(pipe); |
| 155 | |
| 156 | dev_priv->pipestat[pipe] &= ~mask; |
| 157 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
| 158 | (void) I915_READ(reg); |
| 159 | } |
| 160 | } |
| 161 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 162 | /** |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 163 | * intel_enable_asle - enable ASLE interrupt for OpRegion |
| 164 | */ |
| 165 | void intel_enable_asle (struct drm_device *dev) |
| 166 | { |
| 167 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 168 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 169 | if (IS_IRONLAKE(dev)) |
| 170 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 171 | else |
| 172 | i915_enable_pipestat(dev_priv, 1, |
| 173 | I915_LEGACY_BLC_EVENT_ENABLE); |
| 174 | } |
| 175 | |
| 176 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 177 | * i915_pipe_enabled - check if a pipe is enabled |
| 178 | * @dev: DRM device |
| 179 | * @pipe: pipe to check |
| 180 | * |
| 181 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 182 | * Use this routine to make sure the PLL is running and the pipe is active |
| 183 | * before reading such registers if unsure. |
| 184 | */ |
| 185 | static int |
| 186 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 187 | { |
| 188 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 189 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; |
| 190 | |
| 191 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) |
| 192 | return 1; |
| 193 | |
| 194 | return 0; |
| 195 | } |
| 196 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 197 | /* Called from drm generic code, passed a 'crtc', which |
| 198 | * we use as a pipe index |
| 199 | */ |
| 200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 201 | { |
| 202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 203 | unsigned long high_frame; |
| 204 | unsigned long low_frame; |
| 205 | u32 high1, high2, low, count; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 206 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 207 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
| 208 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
| 209 | |
| 210 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 211 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 212 | "pipe %d\n", pipe); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | /* |
| 217 | * High & low register fields aren't synchronized, so make sure |
| 218 | * we get a low value that's stable across two reads of the high |
| 219 | * register. |
| 220 | */ |
| 221 | do { |
| 222 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 223 | PIPE_FRAME_HIGH_SHIFT); |
| 224 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> |
| 225 | PIPE_FRAME_LOW_SHIFT); |
| 226 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 227 | PIPE_FRAME_HIGH_SHIFT); |
| 228 | } while (high1 != high2); |
| 229 | |
| 230 | count = (high1 << 8) | low; |
| 231 | |
| 232 | return count; |
| 233 | } |
| 234 | |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 235 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
| 236 | { |
| 237 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 238 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; |
| 239 | |
| 240 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 241 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
| 242 | "pipe %d\n", pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | return I915_READ(reg); |
| 247 | } |
| 248 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 249 | /* |
| 250 | * Handle hotplug events outside the interrupt handler proper. |
| 251 | */ |
| 252 | static void i915_hotplug_work_func(struct work_struct *work) |
| 253 | { |
| 254 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 255 | hotplug_work); |
| 256 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 257 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 258 | struct drm_connector *connector; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 259 | |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 260 | if (mode_config->num_connector) { |
| 261 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 262 | struct intel_output *intel_output = to_intel_output(connector); |
| 263 | |
| 264 | if (intel_output->hot_plug) |
| 265 | (*intel_output->hot_plug) (intel_output); |
| 266 | } |
| 267 | } |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 268 | /* Just fire off a uevent and let userspace tell us what to do */ |
| 269 | drm_sysfs_hotplug_event(dev); |
| 270 | } |
| 271 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 272 | static void i915_handle_rps_change(struct drm_device *dev) |
| 273 | { |
| 274 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 275 | u32 busy_up, busy_down, max_avg, min_avg; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 276 | u16 rgvswctl; |
| 277 | u8 new_delay = dev_priv->cur_delay; |
| 278 | |
| 279 | I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 280 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 281 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 282 | max_avg = I915_READ(RCBMAXAVG); |
| 283 | min_avg = I915_READ(RCBMINAVG); |
| 284 | |
| 285 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 286 | if (busy_up > max_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 287 | if (dev_priv->cur_delay != dev_priv->max_delay) |
| 288 | new_delay = dev_priv->cur_delay - 1; |
| 289 | if (new_delay < dev_priv->max_delay) |
| 290 | new_delay = dev_priv->max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 291 | } else if (busy_down < min_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 292 | if (dev_priv->cur_delay != dev_priv->min_delay) |
| 293 | new_delay = dev_priv->cur_delay + 1; |
| 294 | if (new_delay > dev_priv->min_delay) |
| 295 | new_delay = dev_priv->min_delay; |
| 296 | } |
| 297 | |
| 298 | DRM_DEBUG("rps change requested: %d -> %d\n", |
| 299 | dev_priv->cur_delay, new_delay); |
| 300 | |
| 301 | rgvswctl = I915_READ(MEMSWCTL); |
| 302 | if (rgvswctl & MEMCTL_CMD_STS) { |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 303 | DRM_ERROR("gpu busy, RCS change rejected\n"); |
| 304 | return; /* still busy with another command */ |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /* Program the new state */ |
| 308 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 309 | (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 310 | I915_WRITE(MEMSWCTL, rgvswctl); |
| 311 | POSTING_READ(MEMSWCTL); |
| 312 | |
| 313 | rgvswctl |= MEMCTL_CMD_STS; |
| 314 | I915_WRITE(MEMSWCTL, rgvswctl); |
| 315 | |
| 316 | dev_priv->cur_delay = new_delay; |
| 317 | |
| 318 | DRM_DEBUG("rps changed\n"); |
| 319 | |
| 320 | return; |
| 321 | } |
| 322 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 323 | irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 324 | { |
| 325 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 326 | int ret = IRQ_NONE; |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 327 | u32 de_iir, gt_iir, de_ier, pch_iir; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 328 | struct drm_i915_master_private *master_priv; |
| 329 | |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 330 | /* disable master interrupt before clearing iir */ |
| 331 | de_ier = I915_READ(DEIER); |
| 332 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
| 333 | (void)I915_READ(DEIER); |
| 334 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 335 | de_iir = I915_READ(DEIIR); |
| 336 | gt_iir = I915_READ(GTIIR); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 337 | pch_iir = I915_READ(SDEIIR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 338 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 339 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
| 340 | goto done; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 341 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 342 | ret = IRQ_HANDLED; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 343 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 344 | if (dev->primary->master) { |
| 345 | master_priv = dev->primary->master->driver_priv; |
| 346 | if (master_priv->sarea_priv) |
| 347 | master_priv->sarea_priv->last_dispatch = |
| 348 | READ_BREADCRUMB(dev_priv); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 349 | } |
| 350 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 351 | if (gt_iir & GT_USER_INTERRUPT) { |
| 352 | u32 seqno = i915_get_gem_seqno(dev); |
| 353 | dev_priv->mm.irq_gem_seqno = seqno; |
| 354 | trace_i915_gem_request_complete(dev, seqno); |
| 355 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 356 | dev_priv->hangcheck_count = 0; |
| 357 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 358 | } |
| 359 | |
| 360 | if (de_iir & DE_GSE) |
| 361 | ironlake_opregion_gse_intr(dev); |
| 362 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 363 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 364 | intel_prepare_page_flip(dev, 0); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 365 | intel_finish_page_flip(dev, 0); |
| 366 | } |
| 367 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 368 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
| 369 | intel_prepare_page_flip(dev, 1); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 370 | intel_finish_page_flip(dev, 1); |
| 371 | } |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 372 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 373 | if (de_iir & DE_PIPEA_VBLANK) |
| 374 | drm_handle_vblank(dev, 0); |
| 375 | |
| 376 | if (de_iir & DE_PIPEB_VBLANK) |
| 377 | drm_handle_vblank(dev, 1); |
| 378 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 379 | /* check event from PCH */ |
| 380 | if ((de_iir & DE_PCH_EVENT) && |
| 381 | (pch_iir & SDE_HOTPLUG_MASK)) { |
| 382 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
| 383 | } |
| 384 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 385 | if (de_iir & DE_PCU_EVENT) { |
| 386 | I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
| 387 | i915_handle_rps_change(dev); |
| 388 | } |
| 389 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 390 | /* should clear PCH hotplug event before clear CPU irq */ |
| 391 | I915_WRITE(SDEIIR, pch_iir); |
| 392 | I915_WRITE(GTIIR, gt_iir); |
| 393 | I915_WRITE(DEIIR, de_iir); |
| 394 | |
| 395 | done: |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 396 | I915_WRITE(DEIER, de_ier); |
| 397 | (void)I915_READ(DEIER); |
| 398 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 399 | return ret; |
| 400 | } |
| 401 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 402 | /** |
| 403 | * i915_error_work_func - do process context error handling work |
| 404 | * @work: work struct |
| 405 | * |
| 406 | * Fire an error uevent so userspace can see that a hang or error |
| 407 | * was detected. |
| 408 | */ |
| 409 | static void i915_error_work_func(struct work_struct *work) |
| 410 | { |
| 411 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 412 | error_work); |
| 413 | struct drm_device *dev = dev_priv->dev; |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 414 | char *error_event[] = { "ERROR=1", NULL }; |
| 415 | char *reset_event[] = { "RESET=1", NULL }; |
| 416 | char *reset_done_event[] = { "ERROR=0", NULL }; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 417 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 418 | DRM_DEBUG_DRIVER("generating error event\n"); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 419 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 420 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 421 | if (atomic_read(&dev_priv->mm.wedged)) { |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 422 | if (IS_I965G(dev)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 423 | DRM_DEBUG_DRIVER("resetting chip\n"); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 424 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
| 425 | if (!i965_reset(dev, GDRST_RENDER)) { |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 426 | atomic_set(&dev_priv->mm.wedged, 0); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 427 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
| 428 | } |
| 429 | } else { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 430 | DRM_DEBUG_DRIVER("reboot required\n"); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 431 | } |
| 432 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | /** |
| 436 | * i915_capture_error_state - capture an error record for later analysis |
| 437 | * @dev: drm device |
| 438 | * |
| 439 | * Should be called when an error is detected (either a hang or an error |
| 440 | * interrupt) to capture error state from the time of the error. Fills |
| 441 | * out a structure which becomes available in debugfs for user level tools |
| 442 | * to pick up. |
| 443 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 444 | static void i915_capture_error_state(struct drm_device *dev) |
| 445 | { |
| 446 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 447 | struct drm_i915_error_state *error; |
| 448 | unsigned long flags; |
| 449 | |
| 450 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
| 451 | if (dev_priv->first_error) |
| 452 | goto out; |
| 453 | |
| 454 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 455 | if (!error) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 456 | DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n"); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 457 | goto out; |
| 458 | } |
| 459 | |
| 460 | error->eir = I915_READ(EIR); |
| 461 | error->pgtbl_er = I915_READ(PGTBL_ER); |
| 462 | error->pipeastat = I915_READ(PIPEASTAT); |
| 463 | error->pipebstat = I915_READ(PIPEBSTAT); |
| 464 | error->instpm = I915_READ(INSTPM); |
| 465 | if (!IS_I965G(dev)) { |
| 466 | error->ipeir = I915_READ(IPEIR); |
| 467 | error->ipehr = I915_READ(IPEHR); |
| 468 | error->instdone = I915_READ(INSTDONE); |
| 469 | error->acthd = I915_READ(ACTHD); |
| 470 | } else { |
| 471 | error->ipeir = I915_READ(IPEIR_I965); |
| 472 | error->ipehr = I915_READ(IPEHR_I965); |
| 473 | error->instdone = I915_READ(INSTDONE_I965); |
| 474 | error->instps = I915_READ(INSTPS); |
| 475 | error->instdone1 = I915_READ(INSTDONE1); |
| 476 | error->acthd = I915_READ(ACTHD_I965); |
| 477 | } |
| 478 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 479 | do_gettimeofday(&error->time); |
| 480 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 481 | dev_priv->first_error = error; |
| 482 | |
| 483 | out: |
| 484 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
| 485 | } |
| 486 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 487 | /** |
| 488 | * i915_handle_error - handle an error interrupt |
| 489 | * @dev: drm device |
| 490 | * |
| 491 | * Do some basic checking of regsiter state at error interrupt time and |
| 492 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 493 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 494 | * so userspace knows something bad happened (should trigger collection |
| 495 | * of a ring dump etc.). |
| 496 | */ |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 497 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 498 | { |
| 499 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 500 | u32 eir = I915_READ(EIR); |
| 501 | u32 pipea_stats = I915_READ(PIPEASTAT); |
| 502 | u32 pipeb_stats = I915_READ(PIPEBSTAT); |
| 503 | |
| 504 | i915_capture_error_state(dev); |
| 505 | |
| 506 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", |
| 507 | eir); |
| 508 | |
| 509 | if (IS_G4X(dev)) { |
| 510 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 511 | u32 ipeir = I915_READ(IPEIR_I965); |
| 512 | |
| 513 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 514 | I915_READ(IPEIR_I965)); |
| 515 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 516 | I915_READ(IPEHR_I965)); |
| 517 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 518 | I915_READ(INSTDONE_I965)); |
| 519 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 520 | I915_READ(INSTPS)); |
| 521 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 522 | I915_READ(INSTDONE1)); |
| 523 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 524 | I915_READ(ACTHD_I965)); |
| 525 | I915_WRITE(IPEIR_I965, ipeir); |
| 526 | (void)I915_READ(IPEIR_I965); |
| 527 | } |
| 528 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 529 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 530 | printk(KERN_ERR "page table error\n"); |
| 531 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 532 | pgtbl_err); |
| 533 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 534 | (void)I915_READ(PGTBL_ER); |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | if (IS_I9XX(dev)) { |
| 539 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 540 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
| 541 | printk(KERN_ERR "page table error\n"); |
| 542 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", |
| 543 | pgtbl_err); |
| 544 | I915_WRITE(PGTBL_ER, pgtbl_err); |
| 545 | (void)I915_READ(PGTBL_ER); |
| 546 | } |
| 547 | } |
| 548 | |
| 549 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
| 550 | printk(KERN_ERR "memory refresh error\n"); |
| 551 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", |
| 552 | pipea_stats); |
| 553 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", |
| 554 | pipeb_stats); |
| 555 | /* pipestat has already been acked */ |
| 556 | } |
| 557 | if (eir & I915_ERROR_INSTRUCTION) { |
| 558 | printk(KERN_ERR "instruction error\n"); |
| 559 | printk(KERN_ERR " INSTPM: 0x%08x\n", |
| 560 | I915_READ(INSTPM)); |
| 561 | if (!IS_I965G(dev)) { |
| 562 | u32 ipeir = I915_READ(IPEIR); |
| 563 | |
| 564 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 565 | I915_READ(IPEIR)); |
| 566 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 567 | I915_READ(IPEHR)); |
| 568 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 569 | I915_READ(INSTDONE)); |
| 570 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 571 | I915_READ(ACTHD)); |
| 572 | I915_WRITE(IPEIR, ipeir); |
| 573 | (void)I915_READ(IPEIR); |
| 574 | } else { |
| 575 | u32 ipeir = I915_READ(IPEIR_I965); |
| 576 | |
| 577 | printk(KERN_ERR " IPEIR: 0x%08x\n", |
| 578 | I915_READ(IPEIR_I965)); |
| 579 | printk(KERN_ERR " IPEHR: 0x%08x\n", |
| 580 | I915_READ(IPEHR_I965)); |
| 581 | printk(KERN_ERR " INSTDONE: 0x%08x\n", |
| 582 | I915_READ(INSTDONE_I965)); |
| 583 | printk(KERN_ERR " INSTPS: 0x%08x\n", |
| 584 | I915_READ(INSTPS)); |
| 585 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", |
| 586 | I915_READ(INSTDONE1)); |
| 587 | printk(KERN_ERR " ACTHD: 0x%08x\n", |
| 588 | I915_READ(ACTHD_I965)); |
| 589 | I915_WRITE(IPEIR_I965, ipeir); |
| 590 | (void)I915_READ(IPEIR_I965); |
| 591 | } |
| 592 | } |
| 593 | |
| 594 | I915_WRITE(EIR, eir); |
| 595 | (void)I915_READ(EIR); |
| 596 | eir = I915_READ(EIR); |
| 597 | if (eir) { |
| 598 | /* |
| 599 | * some errors might have become stuck, |
| 600 | * mask them. |
| 601 | */ |
| 602 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 603 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 604 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 605 | } |
| 606 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 607 | if (wedged) { |
| 608 | atomic_set(&dev_priv->mm.wedged, 1); |
| 609 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 610 | /* |
| 611 | * Wakeup waiting processes so they don't hang |
| 612 | */ |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 613 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 614 | } |
| 615 | |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 616 | queue_work(dev_priv->wq, &dev_priv->error_work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 617 | } |
| 618 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
| 620 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 621 | struct drm_device *dev = (struct drm_device *) arg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 623 | struct drm_i915_master_private *master_priv; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 624 | u32 iir, new_iir; |
| 625 | u32 pipea_stats, pipeb_stats; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 626 | u32 vblank_status; |
| 627 | u32 vblank_enable; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 628 | int vblank = 0; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 629 | unsigned long irqflags; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 630 | int irq_received; |
| 631 | int ret = IRQ_NONE; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 632 | |
Eric Anholt | 630681d | 2008-10-06 15:14:12 -0700 | [diff] [blame] | 633 | atomic_inc(&dev_priv->irq_received); |
| 634 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 635 | if (IS_IRONLAKE(dev)) |
| 636 | return ironlake_irq_handler(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 637 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 638 | iir = I915_READ(IIR); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 639 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 640 | if (IS_I965G(dev)) { |
| 641 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; |
| 642 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; |
| 643 | } else { |
| 644 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; |
| 645 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; |
| 646 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 648 | for (;;) { |
| 649 | irq_received = iir != 0; |
| 650 | |
| 651 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 652 | * have been cleared after the pipestat interrupt was received. |
| 653 | * It doesn't set the bit in iir again, but it still produces |
| 654 | * interrupts (for non-MSI). |
| 655 | */ |
| 656 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
| 657 | pipea_stats = I915_READ(PIPEASTAT); |
| 658 | pipeb_stats = I915_READ(PIPEBSTAT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 659 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 660 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 661 | i915_handle_error(dev, false); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 662 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 663 | /* |
| 664 | * Clear the PIPE(A|B)STAT regs before the IIR |
| 665 | */ |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 666 | if (pipea_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 667 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 668 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 669 | I915_WRITE(PIPEASTAT, pipea_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 670 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 671 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 672 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 673 | if (pipeb_stats & 0x8000ffff) { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 674 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 675 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 676 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 677 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 678 | } |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 679 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
| 680 | |
| 681 | if (!irq_received) |
| 682 | break; |
| 683 | |
| 684 | ret = IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 685 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 686 | /* Consume port. Then clear IIR or we'll miss events */ |
| 687 | if ((I915_HAS_HOTPLUG(dev)) && |
| 688 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 689 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 690 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 691 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 692 | hotplug_status); |
| 693 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 694 | queue_work(dev_priv->wq, |
| 695 | &dev_priv->hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 696 | |
| 697 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 698 | I915_READ(PORT_HOTPLUG_STAT); |
| 699 | } |
| 700 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 701 | I915_WRITE(IIR, iir); |
| 702 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 703 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 704 | if (dev->primary->master) { |
| 705 | master_priv = dev->primary->master->driver_priv; |
| 706 | if (master_priv->sarea_priv) |
| 707 | master_priv->sarea_priv->last_dispatch = |
| 708 | READ_BREADCRUMB(dev_priv); |
| 709 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 710 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 711 | if (iir & I915_USER_INTERRUPT) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 712 | u32 seqno = i915_get_gem_seqno(dev); |
| 713 | dev_priv->mm.irq_gem_seqno = seqno; |
| 714 | trace_i915_gem_request_complete(dev, seqno); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 715 | DRM_WAKEUP(&dev_priv->irq_queue); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 716 | dev_priv->hangcheck_count = 0; |
| 717 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 718 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 719 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 720 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) |
| 721 | intel_prepare_page_flip(dev, 0); |
| 722 | |
| 723 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) |
| 724 | intel_prepare_page_flip(dev, 1); |
| 725 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 726 | if (pipea_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 727 | vblank++; |
| 728 | drm_handle_vblank(dev, 0); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 729 | intel_finish_page_flip(dev, 0); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 730 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 731 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 732 | if (pipeb_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 733 | vblank++; |
| 734 | drm_handle_vblank(dev, 1); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 735 | intel_finish_page_flip(dev, 1); |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 736 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 737 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 738 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
| 739 | (iir & I915_ASLE_INTERRUPT)) |
| 740 | opregion_asle_intr(dev); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 741 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 742 | /* With MSI, interrupts are only generated when iir |
| 743 | * transitions from zero to nonzero. If another bit got |
| 744 | * set while we were handling the existing iir bits, then |
| 745 | * we would never get another interrupt. |
| 746 | * |
| 747 | * This is fine on non-MSI as well, as if we hit this path |
| 748 | * we avoid exiting the interrupt handler only to generate |
| 749 | * another one. |
| 750 | * |
| 751 | * Note that for MSI this could cause a stray interrupt report |
| 752 | * if an interrupt landed in the time between writing IIR and |
| 753 | * the posting read. This should be rare enough to never |
| 754 | * trigger the 99% of 100,000 interrupts test for disabling |
| 755 | * stray interrupts. |
| 756 | */ |
| 757 | iir = new_iir; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 758 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 759 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 760 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 761 | } |
| 762 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 763 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | { |
| 765 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 766 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | RING_LOCALS; |
| 768 | |
| 769 | i915_kernel_lost_context(dev); |
| 770 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 771 | DRM_DEBUG_DRIVER("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 772 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 773 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 774 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 775 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 776 | if (master_priv->sarea_priv) |
| 777 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 778 | |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 779 | BEGIN_LP_RING(4); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 780 | OUT_RING(MI_STORE_DWORD_INDEX); |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 781 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 782 | OUT_RING(dev_priv->counter); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 783 | OUT_RING(MI_USER_INTERRUPT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | ADVANCE_LP_RING(); |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 785 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 786 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | } |
| 788 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 789 | void i915_user_irq_get(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 790 | { |
| 791 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 792 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 793 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 794 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 795 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 796 | if (IS_IRONLAKE(dev)) |
| 797 | ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 798 | else |
| 799 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 800 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 801 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 802 | } |
| 803 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 804 | void i915_user_irq_put(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 805 | { |
| 806 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 807 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 808 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 809 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 810 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 811 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 812 | if (IS_IRONLAKE(dev)) |
| 813 | ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 814 | else |
| 815 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 816 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 817 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 818 | } |
| 819 | |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 820 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
| 821 | { |
| 822 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 823 | |
| 824 | if (dev_priv->trace_irq_seqno == 0) |
| 825 | i915_user_irq_get(dev); |
| 826 | |
| 827 | dev_priv->trace_irq_seqno = seqno; |
| 828 | } |
| 829 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 830 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 831 | { |
| 832 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 833 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | int ret = 0; |
| 835 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 836 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 837 | READ_BREADCRUMB(dev_priv)); |
| 838 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 839 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 840 | if (master_priv->sarea_priv) |
| 841 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 842 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 843 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 844 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 845 | if (master_priv->sarea_priv) |
| 846 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 847 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 848 | i915_user_irq_get(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 849 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
| 850 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 851 | i915_user_irq_put(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 852 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 853 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 854 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 855 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 856 | } |
| 857 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 858 | return ret; |
| 859 | } |
| 860 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 861 | /* Needs the lock as it touches the ring. |
| 862 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 863 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 864 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 866 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 867 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 868 | int result; |
| 869 | |
Eric Anholt | 07f4f8b | 2009-04-16 13:46:12 -0700 | [diff] [blame] | 870 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 871 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 872 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 873 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 874 | |
| 875 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 876 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 877 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 879 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 880 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 881 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 882 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 883 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | } |
| 885 | |
| 886 | return 0; |
| 887 | } |
| 888 | |
| 889 | /* Doesn't need the hardware lock. |
| 890 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 891 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 892 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 893 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 895 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | |
| 897 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 898 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 899 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 900 | } |
| 901 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 902 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | } |
| 904 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 905 | /* Called from drm generic code, passed 'crtc' which |
| 906 | * we use as a pipe index |
| 907 | */ |
| 908 | int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 909 | { |
| 910 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 911 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 912 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 913 | u32 pipeconf; |
| 914 | |
| 915 | pipeconf = I915_READ(pipeconf_reg); |
| 916 | if (!(pipeconf & PIPEACONF_ENABLE)) |
| 917 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 918 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 919 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 920 | if (IS_IRONLAKE(dev)) |
| 921 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
| 922 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
| 923 | else if (IS_I965G(dev)) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 924 | i915_enable_pipestat(dev_priv, pipe, |
| 925 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 926 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 927 | i915_enable_pipestat(dev_priv, pipe, |
| 928 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 929 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 930 | return 0; |
| 931 | } |
| 932 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 933 | /* Called from drm generic code, passed 'crtc' which |
| 934 | * we use as a pipe index |
| 935 | */ |
| 936 | void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 937 | { |
| 938 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 939 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 940 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 941 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 942 | if (IS_IRONLAKE(dev)) |
| 943 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
| 944 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
| 945 | else |
| 946 | i915_disable_pipestat(dev_priv, pipe, |
| 947 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 948 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 949 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 950 | } |
| 951 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 952 | void i915_enable_interrupt (struct drm_device *dev) |
| 953 | { |
| 954 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | e170b03 | 2009-06-05 15:38:40 +0800 | [diff] [blame] | 955 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 956 | if (!IS_IRONLAKE(dev)) |
Zhenyu Wang | e170b03 | 2009-06-05 15:38:40 +0800 | [diff] [blame] | 957 | opregion_enable_asle(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 958 | dev_priv->irq_enabled = 1; |
| 959 | } |
| 960 | |
| 961 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 962 | /* Set the vblank monitor pipe |
| 963 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 964 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 965 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 966 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 967 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 968 | |
| 969 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 970 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 971 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 972 | } |
| 973 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 974 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 975 | } |
| 976 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 977 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 978 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 979 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 980 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 981 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 982 | |
| 983 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 984 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 985 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 986 | } |
| 987 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 988 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 989 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 990 | return 0; |
| 991 | } |
| 992 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 993 | /** |
| 994 | * Schedule buffer swap at given vertical blank. |
| 995 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 996 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 997 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 998 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 999 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 1000 | * removed. The model was that the client requested a delayed flip/swap |
| 1001 | * from the kernel, then waited for vblank before continuing to perform |
| 1002 | * rendering. The problem was that the kernel might wake the client |
| 1003 | * up before it dispatched the vblank swap (since the lock has to be |
| 1004 | * held while touching the ringbuffer), in which case the client would |
| 1005 | * clear and start the next frame before the swap occurred, and |
| 1006 | * flicker would occur in addition to likely missing the vblank. |
| 1007 | * |
| 1008 | * In the absence of this ioctl, userland falls back to a correct path |
| 1009 | * of waiting for a vblank, then dispatching the swap on its own. |
| 1010 | * Context switching to userland and back is plenty fast enough for |
| 1011 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1012 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1013 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1014 | } |
| 1015 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1016 | struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) { |
| 1017 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1018 | return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list); |
| 1019 | } |
| 1020 | |
| 1021 | /** |
| 1022 | * This is called when the chip hasn't reported back with completed |
| 1023 | * batchbuffers in a long time. The first time this is called we simply record |
| 1024 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses |
| 1025 | * again, we assume the chip is wedged and try to fix it. |
| 1026 | */ |
| 1027 | void i915_hangcheck_elapsed(unsigned long data) |
| 1028 | { |
| 1029 | struct drm_device *dev = (struct drm_device *)data; |
| 1030 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1031 | uint32_t acthd; |
| 1032 | |
| 1033 | if (!IS_I965G(dev)) |
| 1034 | acthd = I915_READ(ACTHD); |
| 1035 | else |
| 1036 | acthd = I915_READ(ACTHD_I965); |
| 1037 | |
| 1038 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
| 1039 | if (list_empty(&dev_priv->mm.request_list) || |
| 1040 | i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) { |
| 1041 | dev_priv->hangcheck_count = 0; |
| 1042 | return; |
| 1043 | } |
| 1044 | |
| 1045 | if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) { |
| 1046 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1047 | i915_handle_error(dev, true); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1048 | return; |
| 1049 | } |
| 1050 | |
| 1051 | /* Reset timer case chip hangs without another request being added */ |
| 1052 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 1053 | |
| 1054 | if (acthd != dev_priv->last_acthd) |
| 1055 | dev_priv->hangcheck_count = 0; |
| 1056 | else |
| 1057 | dev_priv->hangcheck_count++; |
| 1058 | |
| 1059 | dev_priv->last_acthd = acthd; |
| 1060 | } |
| 1061 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1062 | /* drm_dma.h hooks |
| 1063 | */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1064 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1065 | { |
| 1066 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1067 | |
| 1068 | I915_WRITE(HWSTAM, 0xeffe); |
| 1069 | |
| 1070 | /* XXX hotplug from PCH */ |
| 1071 | |
| 1072 | I915_WRITE(DEIMR, 0xffffffff); |
| 1073 | I915_WRITE(DEIER, 0x0); |
| 1074 | (void) I915_READ(DEIER); |
| 1075 | |
| 1076 | /* and GT */ |
| 1077 | I915_WRITE(GTIMR, 0xffffffff); |
| 1078 | I915_WRITE(GTIER, 0x0); |
| 1079 | (void) I915_READ(GTIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1080 | |
| 1081 | /* south display irq */ |
| 1082 | I915_WRITE(SDEIMR, 0xffffffff); |
| 1083 | I915_WRITE(SDEIER, 0x0); |
| 1084 | (void) I915_READ(SDEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1085 | } |
| 1086 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1087 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1088 | { |
| 1089 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1090 | /* enable kind of interrupts always enabled */ |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 1091 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 1092 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1093 | u32 render_mask = GT_USER_INTERRUPT; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1094 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
| 1095 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1096 | |
| 1097 | dev_priv->irq_mask_reg = ~display_mask; |
Li Peng | 643ced9 | 2010-01-28 01:05:09 +0800 | [diff] [blame] | 1098 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1099 | |
| 1100 | /* should always can generate irq */ |
| 1101 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1102 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 1103 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); |
| 1104 | (void) I915_READ(DEIER); |
| 1105 | |
| 1106 | /* user interrupt should be enabled, but masked initial */ |
| 1107 | dev_priv->gt_irq_mask_reg = 0xffffffff; |
| 1108 | dev_priv->gt_irq_enable_reg = render_mask; |
| 1109 | |
| 1110 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1111 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 1112 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
| 1113 | (void) I915_READ(GTIER); |
| 1114 | |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1115 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
| 1116 | dev_priv->pch_irq_enable_reg = hotplug_mask; |
| 1117 | |
| 1118 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 1119 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); |
| 1120 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); |
| 1121 | (void) I915_READ(SDEIER); |
| 1122 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1123 | if (IS_IRONLAKE_M(dev)) { |
| 1124 | /* Clear & enable PCU event interrupts */ |
| 1125 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 1126 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); |
| 1127 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
| 1128 | } |
| 1129 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1130 | return 0; |
| 1131 | } |
| 1132 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1133 | void i915_driver_irq_preinstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | { |
| 1135 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1136 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1137 | atomic_set(&dev_priv->irq_received, 0); |
| 1138 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1139 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1140 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1141 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1142 | if (IS_IRONLAKE(dev)) { |
| 1143 | ironlake_irq_preinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1144 | return; |
| 1145 | } |
| 1146 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1147 | if (I915_HAS_HOTPLUG(dev)) { |
| 1148 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1149 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1150 | } |
| 1151 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1152 | I915_WRITE(HWSTAM, 0xeffe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1153 | I915_WRITE(PIPEASTAT, 0); |
| 1154 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1155 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1156 | I915_WRITE(IER, 0x0); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1157 | (void) I915_READ(IER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1158 | } |
| 1159 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1160 | /* |
| 1161 | * Must be called after intel_modeset_init or hotplug interrupts won't be |
| 1162 | * enabled correctly. |
| 1163 | */ |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1164 | int i915_driver_irq_postinstall(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1165 | { |
| 1166 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1167 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1168 | u32 error_mask; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1169 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1170 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
| 1171 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1172 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1173 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1174 | if (IS_IRONLAKE(dev)) |
| 1175 | return ironlake_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1176 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1177 | /* Unmask the interrupts that we always want on. */ |
| 1178 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1179 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1180 | dev_priv->pipestat[0] = 0; |
| 1181 | dev_priv->pipestat[1] = 0; |
| 1182 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1183 | if (I915_HAS_HOTPLUG(dev)) { |
| 1184 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 1185 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1186 | /* Note HDMI and DP share bits */ |
| 1187 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
| 1188 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; |
| 1189 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) |
| 1190 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; |
| 1191 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) |
| 1192 | hotplug_en |= HDMID_HOTPLUG_INT_EN; |
| 1193 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) |
| 1194 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
| 1195 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) |
| 1196 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
| 1197 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) |
| 1198 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
| 1199 | /* Ignore TV since it's buggy */ |
| 1200 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1201 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 1202 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1203 | /* Enable in IER... */ |
| 1204 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 1205 | /* and unmask in IMR */ |
| 1206 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); |
| 1207 | } |
| 1208 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1209 | /* |
| 1210 | * Enable some error detection, note the instruction error mask |
| 1211 | * bit is reserved, so we leave it masked. |
| 1212 | */ |
| 1213 | if (IS_G4X(dev)) { |
| 1214 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 1215 | GM45_ERROR_MEM_PRIV | |
| 1216 | GM45_ERROR_CP_PRIV | |
| 1217 | I915_ERROR_MEMORY_REFRESH); |
| 1218 | } else { |
| 1219 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 1220 | I915_ERROR_MEMORY_REFRESH); |
| 1221 | } |
| 1222 | I915_WRITE(EMR, error_mask); |
| 1223 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1224 | /* Disable pipe interrupt enables, clear pending pipe status */ |
| 1225 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1226 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1227 | /* Clear pending interrupt status */ |
| 1228 | I915_WRITE(IIR, I915_READ(IIR)); |
| 1229 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1230 | I915_WRITE(IER, enable_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1231 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1232 | (void) I915_READ(IER); |
| 1233 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1234 | opregion_enable_asle(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1235 | |
| 1236 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1237 | } |
| 1238 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1239 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1240 | { |
| 1241 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1242 | I915_WRITE(HWSTAM, 0xffffffff); |
| 1243 | |
| 1244 | I915_WRITE(DEIMR, 0xffffffff); |
| 1245 | I915_WRITE(DEIER, 0x0); |
| 1246 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1247 | |
| 1248 | I915_WRITE(GTIMR, 0xffffffff); |
| 1249 | I915_WRITE(GTIER, 0x0); |
| 1250 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1251 | } |
| 1252 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1253 | void i915_driver_irq_uninstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1254 | { |
| 1255 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1257 | if (!dev_priv) |
| 1258 | return; |
| 1259 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1260 | dev_priv->vblank_pipe = 0; |
| 1261 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1262 | if (IS_IRONLAKE(dev)) { |
| 1263 | ironlake_irq_uninstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1264 | return; |
| 1265 | } |
| 1266 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1267 | if (I915_HAS_HOTPLUG(dev)) { |
| 1268 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1269 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1270 | } |
| 1271 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1272 | I915_WRITE(HWSTAM, 0xffffffff); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1273 | I915_WRITE(PIPEASTAT, 0); |
| 1274 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1275 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1276 | I915_WRITE(IER, 0x0); |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 1277 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1278 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 1279 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 1280 | I915_WRITE(IIR, I915_READ(IIR)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1281 | } |