blob: eee1a7b4adc467250d7d531b9cd594de8db47427 [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Jassi Brar230d42d2009-11-30 07:39:42 +00002 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
Mark Brownc2573122011-11-10 10:57:32 +000023#include <linux/interrupt.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000024#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
Arnd Bergmann78843722013-04-11 22:42:03 +020027#include <linux/dmaengine.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000028#include <linux/platform_device.h>
Mark Brownb97b6622011-12-04 00:58:06 +000029#include <linux/pm_runtime.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000030#include <linux/spi/spi.h>
Thomas Abraham1c20c202012-07-13 07:15:14 +090031#include <linux/gpio.h>
Thomas Abraham2b908072012-07-13 07:15:15 +090032#include <linux/of.h>
33#include <linux/of_gpio.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000034
Arnd Bergmann436d42c2012-08-24 15:22:12 +020035#include <linux/platform_data/spi-s3c64xx.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000036
Mark Brown563b4442013-04-18 18:06:05 +010037#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +020038#include <mach/dma.h>
39#endif
40
Thomas Abrahama5238e32012-07-13 07:15:14 +090041#define MAX_SPI_PORTS 3
Girish K S7e995552013-05-20 12:21:32 +053042#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
Thomas Abrahama5238e32012-07-13 07:15:14 +090043
Jassi Brar230d42d2009-11-30 07:39:42 +000044/* Registers and bit-fields */
45
46#define S3C64XX_SPI_CH_CFG 0x00
47#define S3C64XX_SPI_CLK_CFG 0x04
48#define S3C64XX_SPI_MODE_CFG 0x08
49#define S3C64XX_SPI_SLAVE_SEL 0x0C
50#define S3C64XX_SPI_INT_EN 0x10
51#define S3C64XX_SPI_STATUS 0x14
52#define S3C64XX_SPI_TX_DATA 0x18
53#define S3C64XX_SPI_RX_DATA 0x1C
54#define S3C64XX_SPI_PACKET_CNT 0x20
55#define S3C64XX_SPI_PENDING_CLR 0x24
56#define S3C64XX_SPI_SWAP_CFG 0x28
57#define S3C64XX_SPI_FB_CLK 0x2C
58
59#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
60#define S3C64XX_SPI_CH_SW_RST (1<<5)
61#define S3C64XX_SPI_CH_SLAVE (1<<4)
62#define S3C64XX_SPI_CPOL_L (1<<3)
63#define S3C64XX_SPI_CPHA_B (1<<2)
64#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
65#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
66
67#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
68#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
69#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
Jingoo Han75bf3362013-01-31 15:25:01 +090070#define S3C64XX_SPI_PSR_MASK 0xff
Jassi Brar230d42d2009-11-30 07:39:42 +000071
72#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
73#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
74#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
75#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
76#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
77#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
78#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
79#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
80#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
81#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
82#define S3C64XX_SPI_MODE_4BURST (1<<0)
83
84#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
85#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
86
Jassi Brar230d42d2009-11-30 07:39:42 +000087#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
88#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
89#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
90#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
91#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
92#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
93#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
94
95#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
96#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
97#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
98#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
99#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
100#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
101
102#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
103
104#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
105#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
106#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
107#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
108#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
109
110#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
111#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
112#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
113#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
114#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
115#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
116#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
117#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
118
119#define S3C64XX_SPI_FBCLK_MSK (3<<0)
120
Thomas Abrahama5238e32012-07-13 07:15:14 +0900121#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
122#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
123 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
124#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
125#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
126 FIFO_LVL_MASK(i))
Jassi Brar230d42d2009-11-30 07:39:42 +0000127
128#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
129#define S3C64XX_SPI_TRAILCNT_OFF 19
130
131#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
132
133#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
Girish K S7e995552013-05-20 12:21:32 +0530134#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
Jassi Brar230d42d2009-11-30 07:39:42 +0000135
Jassi Brar230d42d2009-11-30 07:39:42 +0000136#define RXBUSY (1<<2)
137#define TXBUSY (1<<3)
138
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900139struct s3c64xx_spi_dma_data {
Arnd Bergmann78843722013-04-11 22:42:03 +0200140 struct dma_chan *ch;
Arnd Bergmannc10356b2012-04-30 16:31:27 +0000141 enum dma_transfer_direction direction;
Arnd Bergmann78843722013-04-11 22:42:03 +0200142 unsigned int dmach;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900143};
144
Jassi Brar230d42d2009-11-30 07:39:42 +0000145/**
Thomas Abrahama5238e32012-07-13 07:15:14 +0900146 * struct s3c64xx_spi_info - SPI Controller hardware info
147 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
148 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
149 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
150 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
151 * @clk_from_cmu: True, if the controller does not include a clock mux and
152 * prescaler unit.
153 *
154 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
155 * differ in some aspects such as the size of the fifo and spi bus clock
156 * setup. Such differences are specified to the driver using this structure
157 * which is provided as driver data to the driver.
158 */
159struct s3c64xx_spi_port_config {
160 int fifo_lvl_mask[MAX_SPI_PORTS];
161 int rx_lvl_offset;
162 int tx_st_done;
Girish K S7e995552013-05-20 12:21:32 +0530163 int quirks;
Thomas Abrahama5238e32012-07-13 07:15:14 +0900164 bool high_speed;
165 bool clk_from_cmu;
166};
167
168/**
Jassi Brar230d42d2009-11-30 07:39:42 +0000169 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
170 * @clk: Pointer to the spi clock.
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700171 * @src_clk: Pointer to the clock used to generate SPI signals.
Jassi Brar230d42d2009-11-30 07:39:42 +0000172 * @master: Pointer to the SPI Protocol master.
Jassi Brar230d42d2009-11-30 07:39:42 +0000173 * @cntrlr_info: Platform specific data for the controller this driver manages.
174 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
Jassi Brar230d42d2009-11-30 07:39:42 +0000175 * @lock: Controller specific lock.
176 * @state: Set of FLAGS to indicate status.
177 * @rx_dmach: Controller's DMA channel for Rx.
178 * @tx_dmach: Controller's DMA channel for Tx.
179 * @sfr_start: BUS address of SPI controller regs.
180 * @regs: Pointer to ioremap'ed controller registers.
Mark Brownc2573122011-11-10 10:57:32 +0000181 * @irq: interrupt
Jassi Brar230d42d2009-11-30 07:39:42 +0000182 * @xfer_completion: To indicate completion of xfer task.
183 * @cur_mode: Stores the active configuration of the controller.
184 * @cur_bpw: Stores the active bits per word settings.
185 * @cur_speed: Stores the active xfer clock speed.
186 */
187struct s3c64xx_spi_driver_data {
188 void __iomem *regs;
189 struct clk *clk;
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700190 struct clk *src_clk;
Jassi Brar230d42d2009-11-30 07:39:42 +0000191 struct platform_device *pdev;
192 struct spi_master *master;
Jassi Brarad7de722010-01-20 13:49:44 -0700193 struct s3c64xx_spi_info *cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000194 struct spi_device *tgl_spi;
Jassi Brar230d42d2009-11-30 07:39:42 +0000195 spinlock_t lock;
Jassi Brar230d42d2009-11-30 07:39:42 +0000196 unsigned long sfr_start;
197 struct completion xfer_completion;
198 unsigned state;
199 unsigned cur_mode, cur_bpw;
200 unsigned cur_speed;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900201 struct s3c64xx_spi_dma_data rx_dma;
202 struct s3c64xx_spi_dma_data tx_dma;
Mark Brown563b4442013-04-18 18:06:05 +0100203#ifdef CONFIG_S3C_DMA
Boojin Kim39d3e802011-09-02 09:44:41 +0900204 struct samsung_dma_ops *ops;
Arnd Bergmann78843722013-04-11 22:42:03 +0200205#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +0900206 struct s3c64xx_spi_port_config *port_conf;
207 unsigned int port_id;
Thomas Abraham2b908072012-07-13 07:15:15 +0900208 unsigned long gpios[4];
Girish K S3146bee2013-06-21 11:26:12 +0530209 bool cs_gpio;
Jassi Brar230d42d2009-11-30 07:39:42 +0000210};
211
Jassi Brar230d42d2009-11-30 07:39:42 +0000212static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
213{
Jassi Brar230d42d2009-11-30 07:39:42 +0000214 void __iomem *regs = sdd->regs;
215 unsigned long loops;
216 u32 val;
217
218 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
219
220 val = readl(regs + S3C64XX_SPI_CH_CFG);
Kyoungil Kim7d859ff2012-05-23 21:29:51 +0900221 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
222 writel(val, regs + S3C64XX_SPI_CH_CFG);
223
224 val = readl(regs + S3C64XX_SPI_CH_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000225 val |= S3C64XX_SPI_CH_SW_RST;
226 val &= ~S3C64XX_SPI_CH_HS_EN;
227 writel(val, regs + S3C64XX_SPI_CH_CFG);
228
229 /* Flush TxFIFO*/
230 loops = msecs_to_loops(1);
231 do {
232 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900233 } while (TX_FIFO_LVL(val, sdd) && loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000234
Mark Brownbe7852a2010-08-23 17:40:56 +0100235 if (loops == 0)
236 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
237
Jassi Brar230d42d2009-11-30 07:39:42 +0000238 /* Flush RxFIFO*/
239 loops = msecs_to_loops(1);
240 do {
241 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900242 if (RX_FIFO_LVL(val, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000243 readl(regs + S3C64XX_SPI_RX_DATA);
244 else
245 break;
246 } while (loops--);
247
Mark Brownbe7852a2010-08-23 17:40:56 +0100248 if (loops == 0)
249 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
250
Jassi Brar230d42d2009-11-30 07:39:42 +0000251 val = readl(regs + S3C64XX_SPI_CH_CFG);
252 val &= ~S3C64XX_SPI_CH_SW_RST;
253 writel(val, regs + S3C64XX_SPI_CH_CFG);
254
255 val = readl(regs + S3C64XX_SPI_MODE_CFG);
256 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
257 writel(val, regs + S3C64XX_SPI_MODE_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000258}
259
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900260static void s3c64xx_spi_dmacb(void *data)
Boojin Kim39d3e802011-09-02 09:44:41 +0900261{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900262 struct s3c64xx_spi_driver_data *sdd;
263 struct s3c64xx_spi_dma_data *dma = data;
Boojin Kim39d3e802011-09-02 09:44:41 +0900264 unsigned long flags;
265
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900266 if (dma->direction == DMA_DEV_TO_MEM)
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900267 sdd = container_of(data,
268 struct s3c64xx_spi_driver_data, rx_dma);
269 else
270 sdd = container_of(data,
271 struct s3c64xx_spi_driver_data, tx_dma);
272
Boojin Kim39d3e802011-09-02 09:44:41 +0900273 spin_lock_irqsave(&sdd->lock, flags);
274
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900275 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900276 sdd->state &= ~RXBUSY;
277 if (!(sdd->state & TXBUSY))
278 complete(&sdd->xfer_completion);
279 } else {
280 sdd->state &= ~TXBUSY;
281 if (!(sdd->state & RXBUSY))
282 complete(&sdd->xfer_completion);
283 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900284
285 spin_unlock_irqrestore(&sdd->lock, flags);
286}
287
Mark Brown563b4442013-04-18 18:06:05 +0100288#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +0200289/* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
290
291static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
292 .name = "samsung-spi-dma",
293};
294
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900295static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
296 unsigned len, dma_addr_t buf)
Boojin Kim39d3e802011-09-02 09:44:41 +0900297{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900298 struct s3c64xx_spi_driver_data *sdd;
Boojin Kim4969c322012-06-19 13:27:03 +0900299 struct samsung_dma_prep info;
300 struct samsung_dma_config config;
Boojin Kim39d3e802011-09-02 09:44:41 +0900301
Boojin Kim4969c322012-06-19 13:27:03 +0900302 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900303 sdd = container_of((void *)dma,
304 struct s3c64xx_spi_driver_data, rx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900305 config.direction = sdd->rx_dma.direction;
306 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
307 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200308 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900309 } else {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900310 sdd = container_of((void *)dma,
311 struct s3c64xx_spi_driver_data, tx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900312 config.direction = sdd->tx_dma.direction;
313 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
314 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200315 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900316 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900317
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900318 info.cap = DMA_SLAVE;
319 info.len = len;
320 info.fp = s3c64xx_spi_dmacb;
321 info.fp_param = dma;
322 info.direction = dma->direction;
323 info.buf = buf;
Boojin Kim39d3e802011-09-02 09:44:41 +0900324
Arnd Bergmann78843722013-04-11 22:42:03 +0200325 sdd->ops->prepare((enum dma_ch)dma->ch, &info);
326 sdd->ops->trigger((enum dma_ch)dma->ch);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900327}
328
329static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
330{
Boojin Kim4969c322012-06-19 13:27:03 +0900331 struct samsung_dma_req req;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +0530332 struct device *dev = &sdd->pdev->dev;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900333
334 sdd->ops = samsung_dma_get_ops();
335
Boojin Kim4969c322012-06-19 13:27:03 +0900336 req.cap = DMA_SLAVE;
337 req.client = &s3c64xx_spi_dma_client;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900338
Jingoo Hanb998aca82013-07-17 17:54:11 +0900339 sdd->rx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
340 sdd->rx_dma.dmach, &req, dev, "rx");
341 sdd->tx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
342 sdd->tx_dma.dmach, &req, dev, "tx");
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900343
344 return 1;
Boojin Kim39d3e802011-09-02 09:44:41 +0900345}
346
Arnd Bergmann78843722013-04-11 22:42:03 +0200347static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
348{
349 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
350
Girish K S7e995552013-05-20 12:21:32 +0530351 /*
352 * If DMA resource was not available during
353 * probe, no need to continue with dma requests
354 * else Acquire DMA channels
355 */
356 while (!is_polling(sdd) && !acquire_dma(sdd))
Arnd Bergmann78843722013-04-11 22:42:03 +0200357 usleep_range(10000, 11000);
358
359 pm_runtime_get_sync(&sdd->pdev->dev);
360
361 return 0;
362}
363
364static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
365{
366 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
367
368 /* Free DMA channels */
Girish K S7e995552013-05-20 12:21:32 +0530369 if (!is_polling(sdd)) {
370 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
371 &s3c64xx_spi_dma_client);
372 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
373 &s3c64xx_spi_dma_client);
374 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200375 pm_runtime_put(&sdd->pdev->dev);
376
377 return 0;
378}
379
380static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
381 struct s3c64xx_spi_dma_data *dma)
382{
383 sdd->ops->stop((enum dma_ch)dma->ch);
384}
385#else
386
387static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
388 unsigned len, dma_addr_t buf)
389{
390 struct s3c64xx_spi_driver_data *sdd;
391 struct dma_slave_config config;
Arnd Bergmann78843722013-04-11 22:42:03 +0200392 struct dma_async_tx_descriptor *desc;
393
Tomasz Figab1a8e782013-08-11 02:33:28 +0200394 memset(&config, 0, sizeof(config));
395
Arnd Bergmann78843722013-04-11 22:42:03 +0200396 if (dma->direction == DMA_DEV_TO_MEM) {
397 sdd = container_of((void *)dma,
398 struct s3c64xx_spi_driver_data, rx_dma);
399 config.direction = dma->direction;
400 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
401 config.src_addr_width = sdd->cur_bpw / 8;
402 config.src_maxburst = 1;
403 dmaengine_slave_config(dma->ch, &config);
404 } else {
405 sdd = container_of((void *)dma,
406 struct s3c64xx_spi_driver_data, tx_dma);
407 config.direction = dma->direction;
408 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
409 config.dst_addr_width = sdd->cur_bpw / 8;
410 config.dst_maxburst = 1;
411 dmaengine_slave_config(dma->ch, &config);
412 }
413
Tomasz Figa90438c42013-08-11 02:33:30 +0200414 desc = dmaengine_prep_slave_single(dma->ch, buf, len,
415 dma->direction, DMA_PREP_INTERRUPT);
Arnd Bergmann78843722013-04-11 22:42:03 +0200416
417 desc->callback = s3c64xx_spi_dmacb;
418 desc->callback_param = dma;
419
420 dmaengine_submit(desc);
421 dma_async_issue_pending(dma->ch);
422}
423
424static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
425{
426 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
427 dma_filter_fn filter = sdd->cntrlr_info->filter;
428 struct device *dev = &sdd->pdev->dev;
429 dma_cap_mask_t mask;
Mark Brownfb9d0442013-04-18 18:12:00 +0100430 int ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200431
Mark Brownc12f9642013-08-13 19:03:01 +0100432 if (!is_polling(sdd)) {
433 dma_cap_zero(mask);
434 dma_cap_set(DMA_SLAVE, mask);
Girish K S9f4b3232013-06-27 12:26:53 +0530435
Mark Brownc12f9642013-08-13 19:03:01 +0100436 /* Acquire DMA channels */
437 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
438 (void *)sdd->rx_dma.dmach, dev, "rx");
439 if (!sdd->rx_dma.ch) {
440 dev_err(dev, "Failed to get RX DMA channel\n");
441 ret = -EBUSY;
442 goto out;
443 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200444
Mark Brownc12f9642013-08-13 19:03:01 +0100445 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
446 (void *)sdd->tx_dma.dmach, dev, "tx");
447 if (!sdd->tx_dma.ch) {
448 dev_err(dev, "Failed to get TX DMA channel\n");
449 ret = -EBUSY;
450 goto out_rx;
451 }
Mark Brownfb9d0442013-04-18 18:12:00 +0100452 }
453
454 ret = pm_runtime_get_sync(&sdd->pdev->dev);
Sylwester Nawrocki6c6cf642013-06-10 18:22:26 +0200455 if (ret < 0) {
Mark Brownfb9d0442013-04-18 18:12:00 +0100456 dev_err(dev, "Failed to enable device: %d\n", ret);
457 goto out_tx;
458 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200459
460 return 0;
Mark Brownfb9d0442013-04-18 18:12:00 +0100461
462out_tx:
463 dma_release_channel(sdd->tx_dma.ch);
464out_rx:
465 dma_release_channel(sdd->rx_dma.ch);
466out:
467 return ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200468}
469
470static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
471{
472 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
473
474 /* Free DMA channels */
Girish K S7e995552013-05-20 12:21:32 +0530475 if (!is_polling(sdd)) {
476 dma_release_channel(sdd->rx_dma.ch);
477 dma_release_channel(sdd->tx_dma.ch);
478 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200479
480 pm_runtime_put(&sdd->pdev->dev);
481 return 0;
482}
483
484static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
485 struct s3c64xx_spi_dma_data *dma)
486{
487 dmaengine_terminate_all(dma->ch);
488}
489#endif
490
Jassi Brar230d42d2009-11-30 07:39:42 +0000491static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
492 struct spi_device *spi,
493 struct spi_transfer *xfer, int dma_mode)
494{
Jassi Brar230d42d2009-11-30 07:39:42 +0000495 void __iomem *regs = sdd->regs;
496 u32 modecfg, chcfg;
497
498 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
499 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
500
501 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
502 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
503
504 if (dma_mode) {
505 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
506 } else {
507 /* Always shift in data in FIFO, even if xfer is Tx only,
508 * this helps setting PCKT_CNT value for generating clocks
509 * as exactly needed.
510 */
511 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
512 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
513 | S3C64XX_SPI_PACKET_CNT_EN,
514 regs + S3C64XX_SPI_PACKET_CNT);
515 }
516
517 if (xfer->tx_buf != NULL) {
518 sdd->state |= TXBUSY;
519 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
520 if (dma_mode) {
521 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900522 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000523 } else {
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900524 switch (sdd->cur_bpw) {
525 case 32:
526 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
527 xfer->tx_buf, xfer->len / 4);
528 break;
529 case 16:
530 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
531 xfer->tx_buf, xfer->len / 2);
532 break;
533 default:
534 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
535 xfer->tx_buf, xfer->len);
536 break;
537 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000538 }
539 }
540
541 if (xfer->rx_buf != NULL) {
542 sdd->state |= RXBUSY;
543
Thomas Abrahama5238e32012-07-13 07:15:14 +0900544 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
Jassi Brar230d42d2009-11-30 07:39:42 +0000545 && !(sdd->cur_mode & SPI_CPHA))
546 chcfg |= S3C64XX_SPI_CH_HS_EN;
547
548 if (dma_mode) {
549 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
550 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
551 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
552 | S3C64XX_SPI_PACKET_CNT_EN,
553 regs + S3C64XX_SPI_PACKET_CNT);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900554 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000555 }
556 }
557
558 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
559 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
560}
561
562static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
563 struct spi_device *spi)
564{
565 struct s3c64xx_spi_csinfo *cs;
566
567 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
568 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
569 /* Deselect the last toggled device */
570 cs = sdd->tgl_spi->controller_data;
Girish K S3146bee2013-06-21 11:26:12 +0530571 if (sdd->cs_gpio)
572 gpio_set_value(cs->line,
573 spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000574 }
575 sdd->tgl_spi = NULL;
576 }
577
578 cs = spi->controller_data;
Girish K S3146bee2013-06-21 11:26:12 +0530579 if (sdd->cs_gpio)
580 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
Girish K S7e995552013-05-20 12:21:32 +0530581
582 /* Start the signals */
583 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
584}
585
Mark Brown79617072013-06-19 19:12:39 +0100586static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
Girish K S7e995552013-05-20 12:21:32 +0530587 int timeout_ms)
588{
589 void __iomem *regs = sdd->regs;
590 unsigned long val = 1;
591 u32 status;
592
593 /* max fifo depth available */
594 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
595
596 if (timeout_ms)
597 val = msecs_to_loops(timeout_ms);
598
599 do {
600 status = readl(regs + S3C64XX_SPI_STATUS);
601 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
602
603 /* return the actual received data length */
604 return RX_FIFO_LVL(status, sdd);
Jassi Brar230d42d2009-11-30 07:39:42 +0000605}
606
607static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
608 struct spi_transfer *xfer, int dma_mode)
609{
Jassi Brar230d42d2009-11-30 07:39:42 +0000610 void __iomem *regs = sdd->regs;
611 unsigned long val;
612 int ms;
613
614 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
615 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
Mark Brown9d8f86b2010-09-07 16:37:52 +0100616 ms += 10; /* some tolerance */
Jassi Brar230d42d2009-11-30 07:39:42 +0000617
618 if (dma_mode) {
619 val = msecs_to_jiffies(ms) + 10;
620 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
621 } else {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900622 u32 status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000623 val = msecs_to_loops(ms);
624 do {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900625 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900626 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
Jassi Brar230d42d2009-11-30 07:39:42 +0000627 }
628
Jassi Brar230d42d2009-11-30 07:39:42 +0000629 if (dma_mode) {
630 u32 status;
631
632 /*
Girish K S7e995552013-05-20 12:21:32 +0530633 * If the previous xfer was completed within timeout, then
634 * proceed further else return -EIO.
Jassi Brar230d42d2009-11-30 07:39:42 +0000635 * DmaTx returns after simply writing data in the FIFO,
636 * w/o waiting for real transmission on the bus to finish.
637 * DmaRx returns only after Dma read data from FIFO which
638 * needs bus transmission to finish, so we don't worry if
639 * Xfer involved Rx(with or without Tx).
640 */
Girish K S7e995552013-05-20 12:21:32 +0530641 if (val && !xfer->rx_buf) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000642 val = msecs_to_loops(10);
643 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900644 while ((TX_FIFO_LVL(status, sdd)
645 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000646 && --val) {
647 cpu_relax();
648 status = readl(regs + S3C64XX_SPI_STATUS);
649 }
650
Jassi Brar230d42d2009-11-30 07:39:42 +0000651 }
Girish K S7e995552013-05-20 12:21:32 +0530652
653 /* If timed out while checking rx/tx status return error */
654 if (!val)
655 return -EIO;
Jassi Brar230d42d2009-11-30 07:39:42 +0000656 } else {
Girish K S7e995552013-05-20 12:21:32 +0530657 int loops;
658 u32 cpy_len;
659 u8 *buf;
660
Jassi Brar230d42d2009-11-30 07:39:42 +0000661 /* If it was only Tx */
Girish K S7e995552013-05-20 12:21:32 +0530662 if (!xfer->rx_buf) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000663 sdd->state &= ~TXBUSY;
664 return 0;
665 }
666
Girish K S7e995552013-05-20 12:21:32 +0530667 /*
668 * If the receive length is bigger than the controller fifo
669 * size, calculate the loops and read the fifo as many times.
670 * loops = length / max fifo size (calculated by using the
671 * fifo mask).
672 * For any size less than the fifo size the below code is
673 * executed atleast once.
674 */
675 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
676 buf = xfer->rx_buf;
677 do {
678 /* wait for data to be received in the fifo */
Mark Brown79617072013-06-19 19:12:39 +0100679 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
680 (loops ? ms : 0));
Girish K S7e995552013-05-20 12:21:32 +0530681
682 switch (sdd->cur_bpw) {
683 case 32:
684 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
685 buf, cpy_len / 4);
686 break;
687 case 16:
688 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
689 buf, cpy_len / 2);
690 break;
691 default:
692 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
693 buf, cpy_len);
694 break;
695 }
696
697 buf = buf + cpy_len;
698 } while (loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000699 sdd->state &= ~RXBUSY;
700 }
701
702 return 0;
703}
704
705static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
706 struct spi_device *spi)
707{
708 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
709
710 if (sdd->tgl_spi == spi)
711 sdd->tgl_spi = NULL;
712
Girish K S3146bee2013-06-21 11:26:12 +0530713 if (sdd->cs_gpio)
714 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
Girish K S7e995552013-05-20 12:21:32 +0530715
716 /* Quiese the signals */
717 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000718}
719
720static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
721{
Jassi Brar230d42d2009-11-30 07:39:42 +0000722 void __iomem *regs = sdd->regs;
723 u32 val;
724
725 /* Disable Clock */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900726 if (sdd->port_conf->clk_from_cmu) {
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900727 clk_disable_unprepare(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900728 } else {
729 val = readl(regs + S3C64XX_SPI_CLK_CFG);
730 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
731 writel(val, regs + S3C64XX_SPI_CLK_CFG);
732 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000733
734 /* Set Polarity and Phase */
735 val = readl(regs + S3C64XX_SPI_CH_CFG);
736 val &= ~(S3C64XX_SPI_CH_SLAVE |
737 S3C64XX_SPI_CPOL_L |
738 S3C64XX_SPI_CPHA_B);
739
740 if (sdd->cur_mode & SPI_CPOL)
741 val |= S3C64XX_SPI_CPOL_L;
742
743 if (sdd->cur_mode & SPI_CPHA)
744 val |= S3C64XX_SPI_CPHA_B;
745
746 writel(val, regs + S3C64XX_SPI_CH_CFG);
747
748 /* Set Channel & DMA Mode */
749 val = readl(regs + S3C64XX_SPI_MODE_CFG);
750 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
751 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
752
753 switch (sdd->cur_bpw) {
754 case 32:
755 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900756 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000757 break;
758 case 16:
759 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900760 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000761 break;
762 default:
763 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900764 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
Jassi Brar230d42d2009-11-30 07:39:42 +0000765 break;
766 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000767
768 writel(val, regs + S3C64XX_SPI_MODE_CFG);
769
Thomas Abrahama5238e32012-07-13 07:15:14 +0900770 if (sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900771 /* Configure Clock */
772 /* There is half-multiplier before the SPI */
773 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
774 /* Enable Clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900775 clk_prepare_enable(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900776 } else {
777 /* Configure Clock */
778 val = readl(regs + S3C64XX_SPI_CLK_CFG);
779 val &= ~S3C64XX_SPI_PSR_MASK;
780 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
781 & S3C64XX_SPI_PSR_MASK);
782 writel(val, regs + S3C64XX_SPI_CLK_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000783
Jassi Brarb42a81c2010-09-29 17:31:33 +0900784 /* Enable Clock */
785 val = readl(regs + S3C64XX_SPI_CLK_CFG);
786 val |= S3C64XX_SPI_ENCLK_ENABLE;
787 writel(val, regs + S3C64XX_SPI_CLK_CFG);
788 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000789}
790
Jassi Brar230d42d2009-11-30 07:39:42 +0000791#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
792
793static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
794 struct spi_message *msg)
795{
796 struct device *dev = &sdd->pdev->dev;
797 struct spi_transfer *xfer;
798
Girish K S7e995552013-05-20 12:21:32 +0530799 if (is_polling(sdd) || msg->is_dma_mapped)
Jassi Brar230d42d2009-11-30 07:39:42 +0000800 return 0;
801
802 /* First mark all xfer unmapped */
803 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
804 xfer->rx_dma = XFER_DMAADDR_INVALID;
805 xfer->tx_dma = XFER_DMAADDR_INVALID;
806 }
807
808 /* Map until end or first fail */
809 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
810
Thomas Abrahama5238e32012-07-13 07:15:14 +0900811 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900812 continue;
813
Jassi Brar230d42d2009-11-30 07:39:42 +0000814 if (xfer->tx_buf != NULL) {
Jassi Brar251ee472010-09-03 10:36:26 +0900815 xfer->tx_dma = dma_map_single(dev,
816 (void *)xfer->tx_buf, xfer->len,
817 DMA_TO_DEVICE);
Jassi Brar230d42d2009-11-30 07:39:42 +0000818 if (dma_mapping_error(dev, xfer->tx_dma)) {
819 dev_err(dev, "dma_map_single Tx failed\n");
820 xfer->tx_dma = XFER_DMAADDR_INVALID;
821 return -ENOMEM;
822 }
823 }
824
825 if (xfer->rx_buf != NULL) {
826 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
827 xfer->len, DMA_FROM_DEVICE);
828 if (dma_mapping_error(dev, xfer->rx_dma)) {
829 dev_err(dev, "dma_map_single Rx failed\n");
830 dma_unmap_single(dev, xfer->tx_dma,
831 xfer->len, DMA_TO_DEVICE);
832 xfer->tx_dma = XFER_DMAADDR_INVALID;
833 xfer->rx_dma = XFER_DMAADDR_INVALID;
834 return -ENOMEM;
835 }
836 }
837 }
838
839 return 0;
840}
841
842static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
843 struct spi_message *msg)
844{
845 struct device *dev = &sdd->pdev->dev;
846 struct spi_transfer *xfer;
847
Girish K S7e995552013-05-20 12:21:32 +0530848 if (is_polling(sdd) || msg->is_dma_mapped)
Jassi Brar230d42d2009-11-30 07:39:42 +0000849 return;
850
851 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
852
Thomas Abrahama5238e32012-07-13 07:15:14 +0900853 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900854 continue;
855
Jassi Brar230d42d2009-11-30 07:39:42 +0000856 if (xfer->rx_buf != NULL
857 && xfer->rx_dma != XFER_DMAADDR_INVALID)
858 dma_unmap_single(dev, xfer->rx_dma,
859 xfer->len, DMA_FROM_DEVICE);
860
861 if (xfer->tx_buf != NULL
862 && xfer->tx_dma != XFER_DMAADDR_INVALID)
863 dma_unmap_single(dev, xfer->tx_dma,
864 xfer->len, DMA_TO_DEVICE);
865 }
866}
867
Mark Brownad2a99a2012-02-15 14:48:32 -0800868static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
869 struct spi_message *msg)
Jassi Brar230d42d2009-11-30 07:39:42 +0000870{
Mark Brownad2a99a2012-02-15 14:48:32 -0800871 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +0000872 struct spi_device *spi = msg->spi;
873 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
874 struct spi_transfer *xfer;
875 int status = 0, cs_toggle = 0;
876 u32 speed;
877 u8 bpw;
878
879 /* If Master's(controller) state differs from that needed by Slave */
880 if (sdd->cur_speed != spi->max_speed_hz
881 || sdd->cur_mode != spi->mode
882 || sdd->cur_bpw != spi->bits_per_word) {
883 sdd->cur_bpw = spi->bits_per_word;
884 sdd->cur_speed = spi->max_speed_hz;
885 sdd->cur_mode = spi->mode;
886 s3c64xx_spi_config(sdd);
887 }
888
889 /* Map all the transfers if needed */
890 if (s3c64xx_spi_map_mssg(sdd, msg)) {
891 dev_err(&spi->dev,
892 "Xfer: Unable to map message buffers!\n");
893 status = -ENOMEM;
894 goto out;
895 }
896
897 /* Configure feedback delay */
898 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
899
900 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
901
902 unsigned long flags;
903 int use_dma;
904
905 INIT_COMPLETION(sdd->xfer_completion);
906
907 /* Only BPW and Speed may change across transfers */
Laxman Dewangan766ed702012-12-18 14:25:43 +0530908 bpw = xfer->bits_per_word;
Jassi Brar230d42d2009-11-30 07:39:42 +0000909 speed = xfer->speed_hz ? : spi->max_speed_hz;
910
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900911 if (xfer->len % (bpw / 8)) {
912 dev_err(&spi->dev,
913 "Xfer length(%u) not a multiple of word size(%u)\n",
914 xfer->len, bpw / 8);
915 status = -EIO;
916 goto out;
917 }
918
Jassi Brar230d42d2009-11-30 07:39:42 +0000919 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
920 sdd->cur_bpw = bpw;
921 sdd->cur_speed = speed;
922 s3c64xx_spi_config(sdd);
923 }
924
925 /* Polling method for xfers not bigger than FIFO capacity */
Arnd Bergmann78843722013-04-11 22:42:03 +0200926 use_dma = 0;
Girish K S7e995552013-05-20 12:21:32 +0530927 if (!is_polling(sdd) &&
928 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
929 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
Jassi Brar230d42d2009-11-30 07:39:42 +0000930 use_dma = 1;
931
932 spin_lock_irqsave(&sdd->lock, flags);
933
934 /* Pending only which is to be done */
935 sdd->state &= ~RXBUSY;
936 sdd->state &= ~TXBUSY;
937
938 enable_datapath(sdd, spi, xfer, use_dma);
939
940 /* Slave Select */
941 enable_cs(sdd, spi);
942
Jassi Brar230d42d2009-11-30 07:39:42 +0000943 spin_unlock_irqrestore(&sdd->lock, flags);
944
945 status = wait_for_xfer(sdd, xfer, use_dma);
946
Jassi Brar230d42d2009-11-30 07:39:42 +0000947 if (status) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900948 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
Jassi Brar230d42d2009-11-30 07:39:42 +0000949 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
950 (sdd->state & RXBUSY) ? 'f' : 'p',
951 (sdd->state & TXBUSY) ? 'f' : 'p',
952 xfer->len);
953
954 if (use_dma) {
955 if (xfer->tx_buf != NULL
956 && (sdd->state & TXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200957 s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000958 if (xfer->rx_buf != NULL
959 && (sdd->state & RXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200960 s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000961 }
962
963 goto out;
964 }
965
966 if (xfer->delay_usecs)
967 udelay(xfer->delay_usecs);
968
969 if (xfer->cs_change) {
970 /* Hint that the next mssg is gonna be
971 for the same device */
972 if (list_is_last(&xfer->transfer_list,
973 &msg->transfers))
974 cs_toggle = 1;
Jassi Brar230d42d2009-11-30 07:39:42 +0000975 }
976
977 msg->actual_length += xfer->len;
978
979 flush_fifo(sdd);
980 }
981
982out:
983 if (!cs_toggle || status)
984 disable_cs(sdd, spi);
985 else
986 sdd->tgl_spi = spi;
987
988 s3c64xx_spi_unmap_mssg(sdd, msg);
989
990 msg->status = status;
991
Mark Brownad2a99a2012-02-15 14:48:32 -0800992 spi_finalize_current_message(master);
993
994 return 0;
Jassi Brar230d42d2009-11-30 07:39:42 +0000995}
996
Thomas Abraham2b908072012-07-13 07:15:15 +0900997static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
Thomas Abraham2b908072012-07-13 07:15:15 +0900998 struct spi_device *spi)
999{
1000 struct s3c64xx_spi_csinfo *cs;
Arnd Bergmann4732cc62012-08-04 11:18:20 +00001001 struct device_node *slave_np, *data_np = NULL;
Girish K S3146bee2013-06-21 11:26:12 +05301002 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham2b908072012-07-13 07:15:15 +09001003 u32 fb_delay = 0;
1004
Girish K S3146bee2013-06-21 11:26:12 +05301005 sdd = spi_master_get_devdata(spi->master);
Thomas Abraham2b908072012-07-13 07:15:15 +09001006 slave_np = spi->dev.of_node;
1007 if (!slave_np) {
1008 dev_err(&spi->dev, "device node not found\n");
1009 return ERR_PTR(-EINVAL);
1010 }
1011
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001012 data_np = of_get_child_by_name(slave_np, "controller-data");
Thomas Abraham2b908072012-07-13 07:15:15 +09001013 if (!data_np) {
1014 dev_err(&spi->dev, "child node 'controller-data' not found\n");
1015 return ERR_PTR(-EINVAL);
1016 }
1017
1018 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1019 if (!cs) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001020 dev_err(&spi->dev, "could not allocate memory for controller data\n");
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001021 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001022 return ERR_PTR(-ENOMEM);
1023 }
1024
Girish K S3146bee2013-06-21 11:26:12 +05301025 /* The CS line is asserted/deasserted by the gpio pin */
1026 if (sdd->cs_gpio)
1027 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
1028
Thomas Abraham2b908072012-07-13 07:15:15 +09001029 if (!gpio_is_valid(cs->line)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001030 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001031 kfree(cs);
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001032 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001033 return ERR_PTR(-EINVAL);
1034 }
1035
1036 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
1037 cs->fb_delay = fb_delay;
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001038 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001039 return cs;
1040}
1041
Jassi Brar230d42d2009-11-30 07:39:42 +00001042/*
1043 * Here we only check the validity of requested configuration
1044 * and save the configuration in a local data-structure.
1045 * The controller is actually configured only just before we
1046 * get a message to transfer.
1047 */
1048static int s3c64xx_spi_setup(struct spi_device *spi)
1049{
1050 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
1051 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -07001052 struct s3c64xx_spi_info *sci;
Thomas Abraham2b908072012-07-13 07:15:15 +09001053 int err;
Jassi Brar230d42d2009-11-30 07:39:42 +00001054
Thomas Abraham2b908072012-07-13 07:15:15 +09001055 sdd = spi_master_get_devdata(spi->master);
1056 if (!cs && spi->dev.of_node) {
Matthias Brugger5c725b32013-03-26 10:27:35 +01001057 cs = s3c64xx_get_slave_ctrldata(spi);
Thomas Abraham2b908072012-07-13 07:15:15 +09001058 spi->controller_data = cs;
1059 }
1060
1061 if (IS_ERR_OR_NULL(cs)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001062 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
1063 return -ENODEV;
1064 }
1065
Tomasz Figa01498712013-08-11 02:33:29 +02001066 if (!spi_get_ctldata(spi)) {
1067 /* Request gpio only if cs line is asserted by gpio pins */
1068 if (sdd->cs_gpio) {
1069 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
1070 dev_name(&spi->dev));
1071 if (err) {
1072 dev_err(&spi->dev,
1073 "Failed to get /CS gpio [%d]: %d\n",
1074 cs->line, err);
1075 goto err_gpio_req;
1076 }
Thomas Abraham1c20c202012-07-13 07:15:14 +09001077 }
Thomas Abraham1c20c202012-07-13 07:15:14 +09001078
Girish K S3146bee2013-06-21 11:26:12 +05301079 spi_set_ctldata(spi, cs);
Tomasz Figa01498712013-08-11 02:33:29 +02001080 }
Girish K S3146bee2013-06-21 11:26:12 +05301081
Jassi Brar230d42d2009-11-30 07:39:42 +00001082 sci = sdd->cntrlr_info;
1083
Mark Brownb97b6622011-12-04 00:58:06 +00001084 pm_runtime_get_sync(&sdd->pdev->dev);
1085
Jassi Brar230d42d2009-11-30 07:39:42 +00001086 /* Check if we can provide the requested rate */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001087 if (!sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001088 u32 psr, speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001089
Jassi Brarb42a81c2010-09-29 17:31:33 +09001090 /* Max possible */
1091 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
Jassi Brar230d42d2009-11-30 07:39:42 +00001092
Jassi Brarb42a81c2010-09-29 17:31:33 +09001093 if (spi->max_speed_hz > speed)
1094 spi->max_speed_hz = speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001095
Jassi Brarb42a81c2010-09-29 17:31:33 +09001096 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1097 psr &= S3C64XX_SPI_PSR_MASK;
1098 if (psr == S3C64XX_SPI_PSR_MASK)
1099 psr--;
1100
1101 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1102 if (spi->max_speed_hz < speed) {
1103 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1104 psr++;
1105 } else {
1106 err = -EINVAL;
1107 goto setup_exit;
1108 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001109 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001110
Jassi Brarb42a81c2010-09-29 17:31:33 +09001111 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
Thomas Abraham2b908072012-07-13 07:15:15 +09001112 if (spi->max_speed_hz >= speed) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001113 spi->max_speed_hz = speed;
Thomas Abraham2b908072012-07-13 07:15:15 +09001114 } else {
Mark Browne1b0f0d2012-12-20 18:27:31 +00001115 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1116 spi->max_speed_hz);
Jassi Brarb42a81c2010-09-29 17:31:33 +09001117 err = -EINVAL;
Thomas Abraham2b908072012-07-13 07:15:15 +09001118 goto setup_exit;
1119 }
Jassi Brarb42a81c2010-09-29 17:31:33 +09001120 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001121
Mark Brownb97b6622011-12-04 00:58:06 +00001122 pm_runtime_put(&sdd->pdev->dev);
Thomas Abraham2b908072012-07-13 07:15:15 +09001123 disable_cs(sdd, spi);
1124 return 0;
Mark Brownb97b6622011-12-04 00:58:06 +00001125
Jassi Brar230d42d2009-11-30 07:39:42 +00001126setup_exit:
Jassi Brar230d42d2009-11-30 07:39:42 +00001127 /* setup() returns with device de-selected */
1128 disable_cs(sdd, spi);
1129
Thomas Abraham2b908072012-07-13 07:15:15 +09001130 gpio_free(cs->line);
1131 spi_set_ctldata(spi, NULL);
1132
1133err_gpio_req:
Sylwester Nawrocki5bee3b92012-09-13 16:31:30 +02001134 if (spi->dev.of_node)
1135 kfree(cs);
Thomas Abraham2b908072012-07-13 07:15:15 +09001136
Jassi Brar230d42d2009-11-30 07:39:42 +00001137 return err;
1138}
1139
Thomas Abraham1c20c202012-07-13 07:15:14 +09001140static void s3c64xx_spi_cleanup(struct spi_device *spi)
1141{
1142 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
Girish K S3146bee2013-06-21 11:26:12 +05301143 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001144
Girish K S3146bee2013-06-21 11:26:12 +05301145 sdd = spi_master_get_devdata(spi->master);
1146 if (cs && sdd->cs_gpio) {
Thomas Abraham1c20c202012-07-13 07:15:14 +09001147 gpio_free(cs->line);
Thomas Abraham2b908072012-07-13 07:15:15 +09001148 if (spi->dev.of_node)
1149 kfree(cs);
1150 }
Thomas Abraham1c20c202012-07-13 07:15:14 +09001151 spi_set_ctldata(spi, NULL);
1152}
1153
Mark Brownc2573122011-11-10 10:57:32 +00001154static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1155{
1156 struct s3c64xx_spi_driver_data *sdd = data;
1157 struct spi_master *spi = sdd->master;
Girish K S375981f2013-03-13 12:13:30 +05301158 unsigned int val, clr = 0;
Mark Brownc2573122011-11-10 10:57:32 +00001159
Girish K S375981f2013-03-13 12:13:30 +05301160 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
Mark Brownc2573122011-11-10 10:57:32 +00001161
Girish K S375981f2013-03-13 12:13:30 +05301162 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1163 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001164 dev_err(&spi->dev, "RX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301165 }
1166 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1167 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001168 dev_err(&spi->dev, "RX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301169 }
1170 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1171 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001172 dev_err(&spi->dev, "TX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301173 }
1174 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1175 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001176 dev_err(&spi->dev, "TX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301177 }
1178
1179 /* Clear the pending irq by setting and then clearing it */
1180 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1181 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
Mark Brownc2573122011-11-10 10:57:32 +00001182
1183 return IRQ_HANDLED;
1184}
1185
Jassi Brar230d42d2009-11-30 07:39:42 +00001186static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1187{
Jassi Brarad7de722010-01-20 13:49:44 -07001188 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001189 void __iomem *regs = sdd->regs;
1190 unsigned int val;
1191
1192 sdd->cur_speed = 0;
1193
Mark Brown5fc3e832012-07-19 14:36:23 +09001194 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +00001195
1196 /* Disable Interrupts - we use Polling if not DMA mode */
1197 writel(0, regs + S3C64XX_SPI_INT_EN);
1198
Thomas Abrahama5238e32012-07-13 07:15:14 +09001199 if (!sdd->port_conf->clk_from_cmu)
Jassi Brarb42a81c2010-09-29 17:31:33 +09001200 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
Jassi Brar230d42d2009-11-30 07:39:42 +00001201 regs + S3C64XX_SPI_CLK_CFG);
1202 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1203 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1204
Girish K S375981f2013-03-13 12:13:30 +05301205 /* Clear any irq pending bits, should set and clear the bits */
1206 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1207 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1208 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1209 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1210 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1211 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
Jassi Brar230d42d2009-11-30 07:39:42 +00001212
1213 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1214
1215 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1216 val &= ~S3C64XX_SPI_MODE_4BURST;
1217 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1218 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1219 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1220
1221 flush_fifo(sdd);
1222}
1223
Thomas Abraham2b908072012-07-13 07:15:15 +09001224#ifdef CONFIG_OF
Jingoo Han75bf3362013-01-31 15:25:01 +09001225static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
Thomas Abraham2b908072012-07-13 07:15:15 +09001226{
1227 struct s3c64xx_spi_info *sci;
1228 u32 temp;
1229
1230 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1231 if (!sci) {
1232 dev_err(dev, "memory allocation for spi_info failed\n");
1233 return ERR_PTR(-ENOMEM);
1234 }
1235
1236 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001237 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001238 sci->src_clk_nr = 0;
1239 } else {
1240 sci->src_clk_nr = temp;
1241 }
1242
1243 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001244 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001245 sci->num_cs = 1;
1246 } else {
1247 sci->num_cs = temp;
1248 }
1249
1250 return sci;
1251}
1252#else
1253static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1254{
1255 return dev->platform_data;
1256}
Thomas Abraham2b908072012-07-13 07:15:15 +09001257#endif
1258
1259static const struct of_device_id s3c64xx_spi_dt_match[];
1260
Thomas Abrahama5238e32012-07-13 07:15:14 +09001261static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1262 struct platform_device *pdev)
1263{
Thomas Abraham2b908072012-07-13 07:15:15 +09001264#ifdef CONFIG_OF
1265 if (pdev->dev.of_node) {
1266 const struct of_device_id *match;
1267 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1268 return (struct s3c64xx_spi_port_config *)match->data;
1269 }
1270#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +09001271 return (struct s3c64xx_spi_port_config *)
1272 platform_get_device_id(pdev)->driver_data;
1273}
1274
Grant Likely2deff8d2013-02-05 13:27:35 +00001275static int s3c64xx_spi_probe(struct platform_device *pdev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001276{
Thomas Abraham2b908072012-07-13 07:15:15 +09001277 struct resource *mem_res;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301278 struct resource *res;
Jassi Brar230d42d2009-11-30 07:39:42 +00001279 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham2b908072012-07-13 07:15:15 +09001280 struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
Jassi Brar230d42d2009-11-30 07:39:42 +00001281 struct spi_master *master;
Mark Brownc2573122011-11-10 10:57:32 +00001282 int ret, irq;
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001283 char clk_name[16];
Jassi Brar230d42d2009-11-30 07:39:42 +00001284
Thomas Abraham2b908072012-07-13 07:15:15 +09001285 if (!sci && pdev->dev.of_node) {
1286 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1287 if (IS_ERR(sci))
1288 return PTR_ERR(sci);
Jassi Brar230d42d2009-11-30 07:39:42 +00001289 }
1290
Thomas Abraham2b908072012-07-13 07:15:15 +09001291 if (!sci) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001292 dev_err(&pdev->dev, "platform_data missing!\n");
1293 return -ENODEV;
1294 }
1295
Jassi Brar230d42d2009-11-30 07:39:42 +00001296 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 if (mem_res == NULL) {
1298 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1299 return -ENXIO;
1300 }
1301
Mark Brownc2573122011-11-10 10:57:32 +00001302 irq = platform_get_irq(pdev, 0);
1303 if (irq < 0) {
1304 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1305 return irq;
1306 }
1307
Jassi Brar230d42d2009-11-30 07:39:42 +00001308 master = spi_alloc_master(&pdev->dev,
1309 sizeof(struct s3c64xx_spi_driver_data));
1310 if (master == NULL) {
1311 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1312 return -ENOMEM;
1313 }
1314
Jassi Brar230d42d2009-11-30 07:39:42 +00001315 platform_set_drvdata(pdev, master);
1316
1317 sdd = spi_master_get_devdata(master);
Thomas Abrahama5238e32012-07-13 07:15:14 +09001318 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001319 sdd->master = master;
1320 sdd->cntrlr_info = sci;
1321 sdd->pdev = pdev;
1322 sdd->sfr_start = mem_res->start;
Girish K S3146bee2013-06-21 11:26:12 +05301323 sdd->cs_gpio = true;
Thomas Abraham2b908072012-07-13 07:15:15 +09001324 if (pdev->dev.of_node) {
Girish K S3146bee2013-06-21 11:26:12 +05301325 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1326 sdd->cs_gpio = false;
1327
Thomas Abraham2b908072012-07-13 07:15:15 +09001328 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1329 if (ret < 0) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001330 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1331 ret);
Thomas Abraham2b908072012-07-13 07:15:15 +09001332 goto err0;
1333 }
1334 sdd->port_id = ret;
1335 } else {
1336 sdd->port_id = pdev->id;
1337 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001338
1339 sdd->cur_bpw = 8;
1340
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301341 if (!sdd->pdev->dev.of_node) {
1342 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1343 if (!res) {
Jingoo Handb0606e2013-07-15 15:11:57 +09001344 dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
Girish K S7e995552013-05-20 12:21:32 +05301345 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1346 } else
1347 sdd->tx_dma.dmach = res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001348
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301349 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1350 if (!res) {
Jingoo Handb0606e2013-07-15 15:11:57 +09001351 dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
Girish K S7e995552013-05-20 12:21:32 +05301352 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1353 } else
1354 sdd->rx_dma.dmach = res->start;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301355 }
1356
1357 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1358 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
Thomas Abraham2b908072012-07-13 07:15:15 +09001359
1360 master->dev.of_node = pdev->dev.of_node;
Thomas Abrahama5238e32012-07-13 07:15:14 +09001361 master->bus_num = sdd->port_id;
Jassi Brar230d42d2009-11-30 07:39:42 +00001362 master->setup = s3c64xx_spi_setup;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001363 master->cleanup = s3c64xx_spi_cleanup;
Mark Brownad2a99a2012-02-15 14:48:32 -08001364 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1365 master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1366 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
Jassi Brar230d42d2009-11-30 07:39:42 +00001367 master->num_chipselect = sci->num_cs;
1368 master->dma_alignment = 8;
Stephen Warren24778be2013-05-21 20:36:35 -06001369 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1370 SPI_BPW_MASK(8);
Jassi Brar230d42d2009-11-30 07:39:42 +00001371 /* the spi->mode bits understood by this driver: */
1372 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1373
Thierry Redingb0ee5602013-01-21 11:09:18 +01001374 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1375 if (IS_ERR(sdd->regs)) {
1376 ret = PTR_ERR(sdd->regs);
Jingoo Han4eb77002013-01-10 11:04:21 +09001377 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001378 }
1379
Thomas Abraham00ab5392013-04-15 20:42:57 -07001380 if (sci->cfg_gpio && sci->cfg_gpio()) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001381 dev_err(&pdev->dev, "Unable to config gpio\n");
1382 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001383 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001384 }
1385
1386 /* Setup clocks */
Jingoo Han4eb77002013-01-10 11:04:21 +09001387 sdd->clk = devm_clk_get(&pdev->dev, "spi");
Jassi Brar230d42d2009-11-30 07:39:42 +00001388 if (IS_ERR(sdd->clk)) {
1389 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1390 ret = PTR_ERR(sdd->clk);
Thomas Abraham00ab5392013-04-15 20:42:57 -07001391 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001392 }
1393
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001394 if (clk_prepare_enable(sdd->clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001395 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1396 ret = -EBUSY;
Thomas Abraham00ab5392013-04-15 20:42:57 -07001397 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001398 }
1399
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001400 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
Jingoo Han4eb77002013-01-10 11:04:21 +09001401 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001402 if (IS_ERR(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001403 dev_err(&pdev->dev,
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001404 "Unable to acquire clock '%s'\n", clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001405 ret = PTR_ERR(sdd->src_clk);
Jingoo Han4eb77002013-01-10 11:04:21 +09001406 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001407 }
1408
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001409 if (clk_prepare_enable(sdd->src_clk)) {
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001410 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
Jassi Brar230d42d2009-11-30 07:39:42 +00001411 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001412 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001413 }
1414
Jassi Brar230d42d2009-11-30 07:39:42 +00001415 /* Setup Deufult Mode */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001416 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001417
1418 spin_lock_init(&sdd->lock);
1419 init_completion(&sdd->xfer_completion);
Jassi Brar230d42d2009-11-30 07:39:42 +00001420
Jingoo Han4eb77002013-01-10 11:04:21 +09001421 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1422 "spi-s3c64xx", sdd);
Mark Brownc2573122011-11-10 10:57:32 +00001423 if (ret != 0) {
1424 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1425 irq, ret);
Jingoo Han4eb77002013-01-10 11:04:21 +09001426 goto err3;
Mark Brownc2573122011-11-10 10:57:32 +00001427 }
1428
1429 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1430 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1431 sdd->regs + S3C64XX_SPI_INT_EN);
1432
Jassi Brar230d42d2009-11-30 07:39:42 +00001433 if (spi_register_master(master)) {
1434 dev_err(&pdev->dev, "cannot register SPI master\n");
1435 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001436 goto err3;
Jassi Brar230d42d2009-11-30 07:39:42 +00001437 }
1438
Jingoo Han75bf3362013-01-31 15:25:01 +09001439 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
Thomas Abrahama5238e32012-07-13 07:15:14 +09001440 sdd->port_id, master->num_chipselect);
Jingoo Hanc65bc4a2013-07-16 08:53:33 +09001441 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",
1442 mem_res,
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001443 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
Jassi Brar230d42d2009-11-30 07:39:42 +00001444
Mark Brownb97b6622011-12-04 00:58:06 +00001445 pm_runtime_enable(&pdev->dev);
1446
Jassi Brar230d42d2009-11-30 07:39:42 +00001447 return 0;
1448
Jassi Brar230d42d2009-11-30 07:39:42 +00001449err3:
Jingoo Han4eb77002013-01-10 11:04:21 +09001450 clk_disable_unprepare(sdd->src_clk);
1451err2:
1452 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001453err0:
Jassi Brar230d42d2009-11-30 07:39:42 +00001454 spi_master_put(master);
1455
1456 return ret;
1457}
1458
1459static int s3c64xx_spi_remove(struct platform_device *pdev)
1460{
1461 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1462 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001463
Mark Brownb97b6622011-12-04 00:58:06 +00001464 pm_runtime_disable(&pdev->dev);
1465
Jassi Brar230d42d2009-11-30 07:39:42 +00001466 spi_unregister_master(master);
1467
Mark Brownc2573122011-11-10 10:57:32 +00001468 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1469
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001470 clk_disable_unprepare(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001471
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001472 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001473
Jassi Brar230d42d2009-11-30 07:39:42 +00001474 spi_master_put(master);
1475
1476 return 0;
1477}
1478
Jingoo Han997230d2013-03-22 02:09:08 +00001479#ifdef CONFIG_PM_SLEEP
Mark Browne25d0bf2011-12-04 00:36:18 +00001480static int s3c64xx_spi_suspend(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001481{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001482 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001483 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001484
Mark Brownad2a99a2012-02-15 14:48:32 -08001485 spi_master_suspend(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001486
1487 /* Disable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001488 clk_disable_unprepare(sdd->src_clk);
1489 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001490
1491 sdd->cur_speed = 0; /* Output Clock is stopped */
1492
1493 return 0;
1494}
1495
Mark Browne25d0bf2011-12-04 00:36:18 +00001496static int s3c64xx_spi_resume(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001497{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001498 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001499 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brarad7de722010-01-20 13:49:44 -07001500 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001501
Thomas Abraham00ab5392013-04-15 20:42:57 -07001502 if (sci->cfg_gpio)
Thomas Abraham2b908072012-07-13 07:15:15 +09001503 sci->cfg_gpio();
Jassi Brar230d42d2009-11-30 07:39:42 +00001504
1505 /* Enable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001506 clk_prepare_enable(sdd->src_clk);
1507 clk_prepare_enable(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001508
Thomas Abrahama5238e32012-07-13 07:15:14 +09001509 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001510
Mark Brownad2a99a2012-02-15 14:48:32 -08001511 spi_master_resume(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001512
1513 return 0;
1514}
Jingoo Han997230d2013-03-22 02:09:08 +00001515#endif /* CONFIG_PM_SLEEP */
Jassi Brar230d42d2009-11-30 07:39:42 +00001516
Mark Brownb97b6622011-12-04 00:58:06 +00001517#ifdef CONFIG_PM_RUNTIME
1518static int s3c64xx_spi_runtime_suspend(struct device *dev)
1519{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001520 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001521 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1522
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001523 clk_disable_unprepare(sdd->clk);
1524 clk_disable_unprepare(sdd->src_clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001525
1526 return 0;
1527}
1528
1529static int s3c64xx_spi_runtime_resume(struct device *dev)
1530{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001531 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001532 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1533
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001534 clk_prepare_enable(sdd->src_clk);
1535 clk_prepare_enable(sdd->clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001536
1537 return 0;
1538}
1539#endif /* CONFIG_PM_RUNTIME */
1540
Mark Browne25d0bf2011-12-04 00:36:18 +00001541static const struct dev_pm_ops s3c64xx_spi_pm = {
1542 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
Mark Brownb97b6622011-12-04 00:58:06 +00001543 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1544 s3c64xx_spi_runtime_resume, NULL)
Mark Browne25d0bf2011-12-04 00:36:18 +00001545};
1546
Sachin Kamat10ce0472012-08-03 10:08:12 +05301547static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001548 .fifo_lvl_mask = { 0x7f },
1549 .rx_lvl_offset = 13,
1550 .tx_st_done = 21,
1551 .high_speed = true,
1552};
1553
Sachin Kamat10ce0472012-08-03 10:08:12 +05301554static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001555 .fifo_lvl_mask = { 0x7f, 0x7F },
1556 .rx_lvl_offset = 13,
1557 .tx_st_done = 21,
1558};
1559
Sachin Kamat10ce0472012-08-03 10:08:12 +05301560static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001561 .fifo_lvl_mask = { 0x1ff, 0x7F },
1562 .rx_lvl_offset = 15,
1563 .tx_st_done = 25,
1564};
1565
Sachin Kamat10ce0472012-08-03 10:08:12 +05301566static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001567 .fifo_lvl_mask = { 0x7f, 0x7F },
1568 .rx_lvl_offset = 13,
1569 .tx_st_done = 21,
1570 .high_speed = true,
1571};
1572
Sachin Kamat10ce0472012-08-03 10:08:12 +05301573static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001574 .fifo_lvl_mask = { 0x1ff, 0x7F },
1575 .rx_lvl_offset = 15,
1576 .tx_st_done = 25,
1577 .high_speed = true,
1578};
1579
Sachin Kamat10ce0472012-08-03 10:08:12 +05301580static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001581 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1582 .rx_lvl_offset = 15,
1583 .tx_st_done = 25,
1584 .high_speed = true,
1585 .clk_from_cmu = true,
1586};
1587
Girish K Sbff82032013-06-21 11:26:13 +05301588static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1589 .fifo_lvl_mask = { 0x1ff },
1590 .rx_lvl_offset = 15,
1591 .tx_st_done = 25,
1592 .high_speed = true,
1593 .clk_from_cmu = true,
1594 .quirks = S3C64XX_SPI_QUIRK_POLL,
1595};
1596
Thomas Abrahama5238e32012-07-13 07:15:14 +09001597static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1598 {
1599 .name = "s3c2443-spi",
1600 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1601 }, {
1602 .name = "s3c6410-spi",
1603 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1604 }, {
1605 .name = "s5p64x0-spi",
1606 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1607 }, {
1608 .name = "s5pc100-spi",
1609 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1610 }, {
1611 .name = "s5pv210-spi",
1612 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1613 }, {
1614 .name = "exynos4210-spi",
1615 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1616 },
1617 { },
1618};
1619
Thomas Abraham2b908072012-07-13 07:15:15 +09001620static const struct of_device_id s3c64xx_spi_dt_match[] = {
1621 { .compatible = "samsung,exynos4210-spi",
1622 .data = (void *)&exynos4_spi_port_config,
1623 },
Girish K Sbff82032013-06-21 11:26:13 +05301624 { .compatible = "samsung,exynos5440-spi",
1625 .data = (void *)&exynos5440_spi_port_config,
1626 },
Thomas Abraham2b908072012-07-13 07:15:15 +09001627 { },
1628};
1629MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
Thomas Abraham2b908072012-07-13 07:15:15 +09001630
Jassi Brar230d42d2009-11-30 07:39:42 +00001631static struct platform_driver s3c64xx_spi_driver = {
1632 .driver = {
1633 .name = "s3c64xx-spi",
1634 .owner = THIS_MODULE,
Mark Browne25d0bf2011-12-04 00:36:18 +00001635 .pm = &s3c64xx_spi_pm,
Thomas Abraham2b908072012-07-13 07:15:15 +09001636 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
Jassi Brar230d42d2009-11-30 07:39:42 +00001637 },
1638 .remove = s3c64xx_spi_remove,
Thomas Abrahama5238e32012-07-13 07:15:14 +09001639 .id_table = s3c64xx_spi_driver_ids,
Jassi Brar230d42d2009-11-30 07:39:42 +00001640};
1641MODULE_ALIAS("platform:s3c64xx-spi");
1642
1643static int __init s3c64xx_spi_init(void)
1644{
1645 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1646}
Mark Brownd2a787f2010-09-07 11:29:17 +01001647subsys_initcall(s3c64xx_spi_init);
Jassi Brar230d42d2009-11-30 07:39:42 +00001648
1649static void __exit s3c64xx_spi_exit(void)
1650{
1651 platform_driver_unregister(&s3c64xx_spi_driver);
1652}
1653module_exit(s3c64xx_spi_exit);
1654
1655MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1656MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1657MODULE_LICENSE("GPL");