Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __AMDGPU_H__ |
| 29 | #define __AMDGPU_H__ |
| 30 | |
| 31 | #include <linux/atomic.h> |
| 32 | #include <linux/wait.h> |
| 33 | #include <linux/list.h> |
| 34 | #include <linux/kref.h> |
| 35 | #include <linux/interval_tree.h> |
| 36 | #include <linux/hashtable.h> |
| 37 | #include <linux/fence.h> |
| 38 | |
| 39 | #include <ttm/ttm_bo_api.h> |
| 40 | #include <ttm/ttm_bo_driver.h> |
| 41 | #include <ttm/ttm_placement.h> |
| 42 | #include <ttm/ttm_module.h> |
| 43 | #include <ttm/ttm_execbuf_util.h> |
| 44 | |
Chunming Zhou | d03846a | 2015-07-28 14:20:03 -0400 | [diff] [blame] | 45 | #include <drm/drmP.h> |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 46 | #include <drm/drm_gem.h> |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 47 | #include <drm/amdgpu_drm.h> |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 48 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 49 | #include "amd_shared.h" |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 50 | #include "amdgpu_mode.h" |
| 51 | #include "amdgpu_ih.h" |
| 52 | #include "amdgpu_irq.h" |
| 53 | #include "amdgpu_ucode.h" |
| 54 | #include "amdgpu_gds.h" |
Alex Deucher | 1f7371b | 2015-12-02 17:46:21 -0500 | [diff] [blame] | 55 | #include "amd_powerplay.h" |
Maruthi Bayyavarapu | a8fe58c | 2015-09-22 17:05:20 -0400 | [diff] [blame] | 56 | #include "amdgpu_acp.h" |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 57 | |
Alex Deucher | b80d847 | 2015-08-16 22:55:02 -0400 | [diff] [blame] | 58 | #include "gpu_scheduler.h" |
| 59 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 60 | /* |
| 61 | * Modules parameters. |
| 62 | */ |
| 63 | extern int amdgpu_modeset; |
| 64 | extern int amdgpu_vram_limit; |
| 65 | extern int amdgpu_gart_size; |
| 66 | extern int amdgpu_benchmarking; |
| 67 | extern int amdgpu_testing; |
| 68 | extern int amdgpu_audio; |
| 69 | extern int amdgpu_disp_priority; |
| 70 | extern int amdgpu_hw_i2c; |
| 71 | extern int amdgpu_pcie_gen2; |
| 72 | extern int amdgpu_msi; |
| 73 | extern int amdgpu_lockup_timeout; |
| 74 | extern int amdgpu_dpm; |
| 75 | extern int amdgpu_smc_load_fw; |
| 76 | extern int amdgpu_aspm; |
| 77 | extern int amdgpu_runtime_pm; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 78 | extern unsigned amdgpu_ip_block_mask; |
| 79 | extern int amdgpu_bapm; |
| 80 | extern int amdgpu_deep_color; |
| 81 | extern int amdgpu_vm_size; |
| 82 | extern int amdgpu_vm_block_size; |
Christian König | d9c1315 | 2015-09-28 12:31:26 +0200 | [diff] [blame] | 83 | extern int amdgpu_vm_fault_stop; |
Christian König | b495bd3 | 2015-09-10 14:00:35 +0200 | [diff] [blame] | 84 | extern int amdgpu_vm_debug; |
Jammy Zhou | 1333f72 | 2015-07-30 16:36:58 +0800 | [diff] [blame] | 85 | extern int amdgpu_sched_jobs; |
Jammy Zhou | 4afcb30 | 2015-07-30 16:44:05 +0800 | [diff] [blame] | 86 | extern int amdgpu_sched_hw_submission; |
Alex Deucher | 1f7371b | 2015-12-02 17:46:21 -0500 | [diff] [blame] | 87 | extern int amdgpu_powerplay; |
Alex Deucher | cd474ba | 2016-02-04 10:21:23 -0500 | [diff] [blame] | 88 | extern unsigned amdgpu_pcie_gen_cap; |
| 89 | extern unsigned amdgpu_pcie_lane_cap; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 90 | |
Chunming Zhou | 4b559c9 | 2015-07-21 15:53:04 +0800 | [diff] [blame] | 91 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 92 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 93 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
| 94 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ |
| 95 | #define AMDGPU_IB_POOL_SIZE 16 |
| 96 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 |
| 97 | #define AMDGPUFB_CONN_LIMIT 4 |
| 98 | #define AMDGPU_BIOS_NUM_SCRATCH 8 |
| 99 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 100 | /* max number of rings */ |
| 101 | #define AMDGPU_MAX_RINGS 16 |
| 102 | #define AMDGPU_MAX_GFX_RINGS 1 |
| 103 | #define AMDGPU_MAX_COMPUTE_RINGS 8 |
| 104 | #define AMDGPU_MAX_VCE_RINGS 2 |
| 105 | |
Jammy Zhou | 36f523a | 2015-09-01 12:54:27 +0800 | [diff] [blame] | 106 | /* max number of IP instances */ |
| 107 | #define AMDGPU_MAX_SDMA_INSTANCES 2 |
| 108 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 109 | /* hardcode that limit for now */ |
| 110 | #define AMDGPU_VA_RESERVED_SIZE (8 << 20) |
| 111 | |
| 112 | /* hard reset data */ |
| 113 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b |
| 114 | |
| 115 | /* reset flags */ |
| 116 | #define AMDGPU_RESET_GFX (1 << 0) |
| 117 | #define AMDGPU_RESET_COMPUTE (1 << 1) |
| 118 | #define AMDGPU_RESET_DMA (1 << 2) |
| 119 | #define AMDGPU_RESET_CP (1 << 3) |
| 120 | #define AMDGPU_RESET_GRBM (1 << 4) |
| 121 | #define AMDGPU_RESET_DMA1 (1 << 5) |
| 122 | #define AMDGPU_RESET_RLC (1 << 6) |
| 123 | #define AMDGPU_RESET_SEM (1 << 7) |
| 124 | #define AMDGPU_RESET_IH (1 << 8) |
| 125 | #define AMDGPU_RESET_VMC (1 << 9) |
| 126 | #define AMDGPU_RESET_MC (1 << 10) |
| 127 | #define AMDGPU_RESET_DISPLAY (1 << 11) |
| 128 | #define AMDGPU_RESET_UVD (1 << 12) |
| 129 | #define AMDGPU_RESET_VCE (1 << 13) |
| 130 | #define AMDGPU_RESET_VCE1 (1 << 14) |
| 131 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 132 | /* GFX current status */ |
| 133 | #define AMDGPU_GFX_NORMAL_MODE 0x00000000L |
| 134 | #define AMDGPU_GFX_SAFE_MODE 0x00000001L |
| 135 | #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L |
| 136 | #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L |
| 137 | #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L |
| 138 | |
| 139 | /* max cursor sizes (in pixels) */ |
| 140 | #define CIK_CURSOR_WIDTH 128 |
| 141 | #define CIK_CURSOR_HEIGHT 128 |
| 142 | |
| 143 | struct amdgpu_device; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 144 | struct amdgpu_ib; |
| 145 | struct amdgpu_vm; |
| 146 | struct amdgpu_ring; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 147 | struct amdgpu_cs_parser; |
Chunming Zhou | bb977d3 | 2015-08-18 15:16:40 +0800 | [diff] [blame] | 148 | struct amdgpu_job; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 149 | struct amdgpu_irq_src; |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 150 | struct amdgpu_fpriv; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 151 | |
| 152 | enum amdgpu_cp_irq { |
| 153 | AMDGPU_CP_IRQ_GFX_EOP = 0, |
| 154 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, |
| 155 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, |
| 156 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, |
| 157 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, |
| 158 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, |
| 159 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, |
| 160 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, |
| 161 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, |
| 162 | |
| 163 | AMDGPU_CP_IRQ_LAST |
| 164 | }; |
| 165 | |
| 166 | enum amdgpu_sdma_irq { |
| 167 | AMDGPU_SDMA_IRQ_TRAP0 = 0, |
| 168 | AMDGPU_SDMA_IRQ_TRAP1, |
| 169 | |
| 170 | AMDGPU_SDMA_IRQ_LAST |
| 171 | }; |
| 172 | |
| 173 | enum amdgpu_thermal_irq { |
| 174 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, |
| 175 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, |
| 176 | |
| 177 | AMDGPU_THERMAL_IRQ_LAST |
| 178 | }; |
| 179 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 180 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 181 | enum amd_ip_block_type block_type, |
| 182 | enum amd_clockgating_state state); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 183 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 184 | enum amd_ip_block_type block_type, |
| 185 | enum amd_powergating_state state); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 186 | |
| 187 | struct amdgpu_ip_block_version { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 188 | enum amd_ip_block_type type; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 189 | u32 major; |
| 190 | u32 minor; |
| 191 | u32 rev; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 192 | const struct amd_ip_funcs *funcs; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 193 | }; |
| 194 | |
| 195 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 196 | enum amd_ip_block_type type, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 197 | u32 major, u32 minor); |
| 198 | |
| 199 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( |
| 200 | struct amdgpu_device *adev, |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 201 | enum amd_ip_block_type type); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 202 | |
| 203 | /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ |
| 204 | struct amdgpu_buffer_funcs { |
| 205 | /* maximum bytes in a single operation */ |
| 206 | uint32_t copy_max_bytes; |
| 207 | |
| 208 | /* number of dw to reserve per operation */ |
| 209 | unsigned copy_num_dw; |
| 210 | |
| 211 | /* used for buffer migration */ |
Chunming Zhou | c7ae72c | 2015-08-25 17:23:45 +0800 | [diff] [blame] | 212 | void (*emit_copy_buffer)(struct amdgpu_ib *ib, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 213 | /* src addr in bytes */ |
| 214 | uint64_t src_offset, |
| 215 | /* dst addr in bytes */ |
| 216 | uint64_t dst_offset, |
| 217 | /* number of byte to transfer */ |
| 218 | uint32_t byte_count); |
| 219 | |
| 220 | /* maximum bytes in a single operation */ |
| 221 | uint32_t fill_max_bytes; |
| 222 | |
| 223 | /* number of dw to reserve per operation */ |
| 224 | unsigned fill_num_dw; |
| 225 | |
| 226 | /* used for buffer clearing */ |
Chunming Zhou | 6e7a384 | 2015-08-27 13:46:09 +0800 | [diff] [blame] | 227 | void (*emit_fill_buffer)(struct amdgpu_ib *ib, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 228 | /* value to write to memory */ |
| 229 | uint32_t src_data, |
| 230 | /* dst addr in bytes */ |
| 231 | uint64_t dst_offset, |
| 232 | /* number of byte to fill */ |
| 233 | uint32_t byte_count); |
| 234 | }; |
| 235 | |
| 236 | /* provided by hw blocks that can write ptes, e.g., sdma */ |
| 237 | struct amdgpu_vm_pte_funcs { |
| 238 | /* copy pte entries from GART */ |
| 239 | void (*copy_pte)(struct amdgpu_ib *ib, |
| 240 | uint64_t pe, uint64_t src, |
| 241 | unsigned count); |
| 242 | /* write pte one entry at a time with addr mapping */ |
| 243 | void (*write_pte)(struct amdgpu_ib *ib, |
Christian König | b07c9d2 | 2015-11-30 13:26:07 +0100 | [diff] [blame] | 244 | const dma_addr_t *pages_addr, uint64_t pe, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 245 | uint64_t addr, unsigned count, |
| 246 | uint32_t incr, uint32_t flags); |
| 247 | /* for linear pte/pde updates without addr mapping */ |
| 248 | void (*set_pte_pde)(struct amdgpu_ib *ib, |
| 249 | uint64_t pe, |
| 250 | uint64_t addr, unsigned count, |
| 251 | uint32_t incr, uint32_t flags); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | /* provided by the gmc block */ |
| 255 | struct amdgpu_gart_funcs { |
| 256 | /* flush the vm tlb via mmio */ |
| 257 | void (*flush_gpu_tlb)(struct amdgpu_device *adev, |
| 258 | uint32_t vmid); |
| 259 | /* write pte/pde updates using the cpu */ |
| 260 | int (*set_pte_pde)(struct amdgpu_device *adev, |
| 261 | void *cpu_pt_addr, /* cpu addr of page table */ |
| 262 | uint32_t gpu_page_idx, /* pte/pde to update */ |
| 263 | uint64_t addr, /* addr to write into pte/pde */ |
| 264 | uint32_t flags); /* access flags */ |
| 265 | }; |
| 266 | |
| 267 | /* provided by the ih block */ |
| 268 | struct amdgpu_ih_funcs { |
| 269 | /* ring read/write ptr handling, called from interrupt context */ |
| 270 | u32 (*get_wptr)(struct amdgpu_device *adev); |
| 271 | void (*decode_iv)(struct amdgpu_device *adev, |
| 272 | struct amdgpu_iv_entry *entry); |
| 273 | void (*set_rptr)(struct amdgpu_device *adev); |
| 274 | }; |
| 275 | |
| 276 | /* provided by hw blocks that expose a ring buffer for commands */ |
| 277 | struct amdgpu_ring_funcs { |
| 278 | /* ring read/write ptr handling */ |
| 279 | u32 (*get_rptr)(struct amdgpu_ring *ring); |
| 280 | u32 (*get_wptr)(struct amdgpu_ring *ring); |
| 281 | void (*set_wptr)(struct amdgpu_ring *ring); |
| 282 | /* validating and patching of IBs */ |
| 283 | int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); |
| 284 | /* command emit functions */ |
| 285 | void (*emit_ib)(struct amdgpu_ring *ring, |
| 286 | struct amdgpu_ib *ib); |
| 287 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 288 | uint64_t seq, unsigned flags); |
Christian König | b8c7b39 | 2016-03-01 15:42:52 +0100 | [diff] [blame] | 289 | void (*emit_pipeline_sync)(struct amdgpu_ring *ring); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 290 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, |
| 291 | uint64_t pd_addr); |
Christian König | d2edb07 | 2015-05-11 14:10:34 +0200 | [diff] [blame] | 292 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); |
Chunming Zhou | 11afbde | 2016-03-03 11:38:48 +0800 | [diff] [blame] | 293 | void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 294 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, |
| 295 | uint32_t gds_base, uint32_t gds_size, |
| 296 | uint32_t gws_base, uint32_t gws_size, |
| 297 | uint32_t oa_base, uint32_t oa_size); |
| 298 | /* testing functions */ |
| 299 | int (*test_ring)(struct amdgpu_ring *ring); |
| 300 | int (*test_ib)(struct amdgpu_ring *ring); |
Jammy Zhou | edff0e2 | 2015-09-01 13:04:08 +0800 | [diff] [blame] | 301 | /* insert NOP packets */ |
| 302 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); |
Christian König | 9e5d5309 | 2016-01-31 12:20:55 +0100 | [diff] [blame] | 303 | /* pad the indirect buffer to the necessary number of dw */ |
| 304 | void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); |
Monk Liu | 03ccf48 | 2016-01-14 19:07:38 +0800 | [diff] [blame] | 305 | unsigned (*init_cond_exec)(struct amdgpu_ring *ring); |
| 306 | void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 307 | }; |
| 308 | |
| 309 | /* |
| 310 | * BIOS. |
| 311 | */ |
| 312 | bool amdgpu_get_bios(struct amdgpu_device *adev); |
| 313 | bool amdgpu_read_bios(struct amdgpu_device *adev); |
| 314 | |
| 315 | /* |
| 316 | * Dummy page |
| 317 | */ |
| 318 | struct amdgpu_dummy_page { |
| 319 | struct page *page; |
| 320 | dma_addr_t addr; |
| 321 | }; |
| 322 | int amdgpu_dummy_page_init(struct amdgpu_device *adev); |
| 323 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev); |
| 324 | |
| 325 | |
| 326 | /* |
| 327 | * Clocks |
| 328 | */ |
| 329 | |
| 330 | #define AMDGPU_MAX_PPLL 3 |
| 331 | |
| 332 | struct amdgpu_clock { |
| 333 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; |
| 334 | struct amdgpu_pll spll; |
| 335 | struct amdgpu_pll mpll; |
| 336 | /* 10 Khz units */ |
| 337 | uint32_t default_mclk; |
| 338 | uint32_t default_sclk; |
| 339 | uint32_t default_dispclk; |
| 340 | uint32_t current_dispclk; |
| 341 | uint32_t dp_extclk; |
| 342 | uint32_t max_pixel_clock; |
| 343 | }; |
| 344 | |
| 345 | /* |
| 346 | * Fences. |
| 347 | */ |
| 348 | struct amdgpu_fence_driver { |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 349 | uint64_t gpu_addr; |
| 350 | volatile uint32_t *cpu_addr; |
| 351 | /* sync_seq is protected by ring emission lock */ |
Christian König | 742c085 | 2016-03-14 15:46:06 +0100 | [diff] [blame] | 352 | uint32_t sync_seq; |
| 353 | atomic_t last_seq; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 354 | bool initialized; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 355 | struct amdgpu_irq_src *irq_src; |
| 356 | unsigned irq_type; |
Christian König | c2776af | 2015-11-03 13:27:39 +0100 | [diff] [blame] | 357 | struct timer_list fallback_timer; |
Christian König | c89377d | 2016-03-13 19:19:48 +0100 | [diff] [blame] | 358 | unsigned num_fences_mask; |
Christian König | 4a7d74f | 2016-03-14 14:29:46 +0100 | [diff] [blame] | 359 | spinlock_t lock; |
Christian König | c89377d | 2016-03-13 19:19:48 +0100 | [diff] [blame] | 360 | struct fence **fences; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 361 | }; |
| 362 | |
| 363 | /* some special values for the owner field */ |
| 364 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) |
| 365 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) |
Chunming Zhou | 031e298 | 2016-04-25 10:19:13 +0800 | [diff] [blame] | 366 | #define AMDGPU_CLIENT_ID_RESERVED 2 |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 367 | |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 368 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) |
| 369 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) |
| 370 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 371 | struct amdgpu_user_fence { |
| 372 | /* write-back bo */ |
| 373 | struct amdgpu_bo *bo; |
| 374 | /* write-back address offset to bo start */ |
| 375 | uint32_t offset; |
| 376 | }; |
| 377 | |
| 378 | int amdgpu_fence_driver_init(struct amdgpu_device *adev); |
| 379 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev); |
| 380 | void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); |
| 381 | |
Christian König | e6151a0 | 2016-03-15 14:52:26 +0100 | [diff] [blame] | 382 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, |
| 383 | unsigned num_hw_submission); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 384 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, |
| 385 | struct amdgpu_irq_src *irq_src, |
| 386 | unsigned irq_type); |
Alex Deucher | 5ceb54c | 2015-08-05 12:41:48 -0400 | [diff] [blame] | 387 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); |
| 388 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev); |
Christian König | 364beb2 | 2016-02-16 17:39:39 +0100 | [diff] [blame] | 389 | int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 390 | void amdgpu_fence_process(struct amdgpu_ring *ring); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 391 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); |
| 392 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); |
| 393 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 394 | /* |
| 395 | * TTM. |
| 396 | */ |
Christian König | 29b3259 | 2016-04-15 17:19:16 +0200 | [diff] [blame] | 397 | |
| 398 | #define AMDGPU_TTM_LRU_SIZE 20 |
| 399 | |
| 400 | struct amdgpu_mman_lru { |
| 401 | struct list_head *lru[TTM_NUM_MEM_TYPES]; |
| 402 | struct list_head *swap_lru; |
| 403 | }; |
| 404 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 405 | struct amdgpu_mman { |
| 406 | struct ttm_bo_global_ref bo_global_ref; |
| 407 | struct drm_global_reference mem_global_ref; |
| 408 | struct ttm_bo_device bdev; |
| 409 | bool mem_global_referenced; |
| 410 | bool initialized; |
| 411 | |
| 412 | #if defined(CONFIG_DEBUG_FS) |
| 413 | struct dentry *vram; |
| 414 | struct dentry *gtt; |
| 415 | #endif |
| 416 | |
| 417 | /* buffer handling */ |
| 418 | const struct amdgpu_buffer_funcs *buffer_funcs; |
| 419 | struct amdgpu_ring *buffer_funcs_ring; |
Christian König | 703297c | 2016-02-10 14:20:50 +0100 | [diff] [blame] | 420 | /* Scheduler entity for buffer moves */ |
| 421 | struct amd_sched_entity entity; |
Christian König | 29b3259 | 2016-04-15 17:19:16 +0200 | [diff] [blame] | 422 | |
| 423 | /* custom LRU management */ |
| 424 | struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE]; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 425 | }; |
| 426 | |
| 427 | int amdgpu_copy_buffer(struct amdgpu_ring *ring, |
| 428 | uint64_t src_offset, |
| 429 | uint64_t dst_offset, |
| 430 | uint32_t byte_count, |
| 431 | struct reservation_object *resv, |
Chunming Zhou | c7ae72c | 2015-08-25 17:23:45 +0800 | [diff] [blame] | 432 | struct fence **fence); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 433 | int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); |
| 434 | |
| 435 | struct amdgpu_bo_list_entry { |
| 436 | struct amdgpu_bo *robj; |
| 437 | struct ttm_validate_buffer tv; |
| 438 | struct amdgpu_bo_va *bo_va; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 439 | uint32_t priority; |
Christian König | 2f568db | 2016-02-23 12:36:59 +0100 | [diff] [blame] | 440 | struct page **user_pages; |
| 441 | int user_invalidated; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 442 | }; |
| 443 | |
| 444 | struct amdgpu_bo_va_mapping { |
| 445 | struct list_head list; |
| 446 | struct interval_tree_node it; |
| 447 | uint64_t offset; |
| 448 | uint32_t flags; |
| 449 | }; |
| 450 | |
| 451 | /* bo virtual addresses in a specific vm */ |
| 452 | struct amdgpu_bo_va { |
| 453 | /* protected by bo being reserved */ |
| 454 | struct list_head bo_list; |
Chunming Zhou | bb1e38a4 | 2015-08-03 18:19:38 +0800 | [diff] [blame] | 455 | struct fence *last_pt_update; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 456 | unsigned ref_count; |
| 457 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 458 | /* protected by vm mutex and spinlock */ |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 459 | struct list_head vm_status; |
| 460 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 461 | /* mappings for this bo_va */ |
| 462 | struct list_head invalids; |
| 463 | struct list_head valids; |
| 464 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 465 | /* constant after initialization */ |
| 466 | struct amdgpu_vm *vm; |
| 467 | struct amdgpu_bo *bo; |
| 468 | }; |
| 469 | |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 470 | #define AMDGPU_GEM_DOMAIN_MAX 0x3 |
| 471 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 472 | struct amdgpu_bo { |
| 473 | /* Protected by gem.mutex */ |
| 474 | struct list_head list; |
| 475 | /* Protected by tbo.reserved */ |
Christian König | 1ea863f | 2015-12-18 22:13:12 +0100 | [diff] [blame] | 476 | u32 prefered_domains; |
| 477 | u32 allowed_domains; |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 478 | struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 479 | struct ttm_placement placement; |
| 480 | struct ttm_buffer_object tbo; |
| 481 | struct ttm_bo_kmap_obj kmap; |
| 482 | u64 flags; |
| 483 | unsigned pin_count; |
| 484 | void *kptr; |
| 485 | u64 tiling_flags; |
| 486 | u64 metadata_flags; |
| 487 | void *metadata; |
| 488 | u32 metadata_size; |
| 489 | /* list of all virtual address to which this bo |
| 490 | * is associated to |
| 491 | */ |
| 492 | struct list_head va; |
| 493 | /* Constant after initialization */ |
| 494 | struct amdgpu_device *adev; |
| 495 | struct drm_gem_object gem_base; |
Christian König | 82b9c55 | 2015-11-27 16:49:00 +0100 | [diff] [blame] | 496 | struct amdgpu_bo *parent; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 497 | |
| 498 | struct ttm_bo_kmap_obj dma_buf_vmap; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 499 | struct amdgpu_mn *mn; |
| 500 | struct list_head mn_list; |
| 501 | }; |
| 502 | #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) |
| 503 | |
| 504 | void amdgpu_gem_object_free(struct drm_gem_object *obj); |
| 505 | int amdgpu_gem_object_open(struct drm_gem_object *obj, |
| 506 | struct drm_file *file_priv); |
| 507 | void amdgpu_gem_object_close(struct drm_gem_object *obj, |
| 508 | struct drm_file *file_priv); |
| 509 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); |
| 510 | struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); |
| 511 | struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, |
| 512 | struct dma_buf_attachment *attach, |
| 513 | struct sg_table *sg); |
| 514 | struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, |
| 515 | struct drm_gem_object *gobj, |
| 516 | int flags); |
| 517 | int amdgpu_gem_prime_pin(struct drm_gem_object *obj); |
| 518 | void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); |
| 519 | struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); |
| 520 | void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); |
| 521 | void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); |
| 522 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); |
| 523 | |
| 524 | /* sub-allocation manager, it has to be protected by another lock. |
| 525 | * By conception this is an helper for other part of the driver |
| 526 | * like the indirect buffer or semaphore, which both have their |
| 527 | * locking. |
| 528 | * |
| 529 | * Principe is simple, we keep a list of sub allocation in offset |
| 530 | * order (first entry has offset == 0, last entry has the highest |
| 531 | * offset). |
| 532 | * |
| 533 | * When allocating new object we first check if there is room at |
| 534 | * the end total_size - (last_object_offset + last_object_size) >= |
| 535 | * alloc_size. If so we allocate new object there. |
| 536 | * |
| 537 | * When there is not enough room at the end, we start waiting for |
| 538 | * each sub object until we reach object_offset+object_size >= |
| 539 | * alloc_size, this object then become the sub object we return. |
| 540 | * |
| 541 | * Alignment can't be bigger than page size. |
| 542 | * |
| 543 | * Hole are not considered for allocation to keep things simple. |
| 544 | * Assumption is that there won't be hole (all object on same |
| 545 | * alignment). |
| 546 | */ |
Christian König | 6ba60b8 | 2016-03-11 14:50:08 +0100 | [diff] [blame] | 547 | |
| 548 | #define AMDGPU_SA_NUM_FENCE_LISTS 32 |
| 549 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 550 | struct amdgpu_sa_manager { |
| 551 | wait_queue_head_t wq; |
| 552 | struct amdgpu_bo *bo; |
| 553 | struct list_head *hole; |
Christian König | 6ba60b8 | 2016-03-11 14:50:08 +0100 | [diff] [blame] | 554 | struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 555 | struct list_head olist; |
| 556 | unsigned size; |
| 557 | uint64_t gpu_addr; |
| 558 | void *cpu_ptr; |
| 559 | uint32_t domain; |
| 560 | uint32_t align; |
| 561 | }; |
| 562 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 563 | /* sub-allocation buffer */ |
| 564 | struct amdgpu_sa_bo { |
| 565 | struct list_head olist; |
| 566 | struct list_head flist; |
| 567 | struct amdgpu_sa_manager *manager; |
| 568 | unsigned soffset; |
| 569 | unsigned eoffset; |
Chunming Zhou | 4ce9891 | 2015-08-19 16:41:19 +0800 | [diff] [blame] | 570 | struct fence *fence; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 571 | }; |
| 572 | |
| 573 | /* |
| 574 | * GEM objects. |
| 575 | */ |
Christian König | 418aa0c | 2016-02-15 16:59:57 +0100 | [diff] [blame] | 576 | void amdgpu_gem_force_release(struct amdgpu_device *adev); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 577 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, |
| 578 | int alignment, u32 initial_domain, |
| 579 | u64 flags, bool kernel, |
| 580 | struct drm_gem_object **obj); |
| 581 | |
| 582 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, |
| 583 | struct drm_device *dev, |
| 584 | struct drm_mode_create_dumb *args); |
| 585 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, |
| 586 | struct drm_device *dev, |
| 587 | uint32_t handle, uint64_t *offset_p); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 588 | /* |
| 589 | * Synchronization |
| 590 | */ |
| 591 | struct amdgpu_sync { |
Christian König | f91b3a6 | 2015-08-20 14:47:40 +0800 | [diff] [blame] | 592 | DECLARE_HASHTABLE(fences, 4); |
Chunming Zhou | 3c62338 | 2015-08-20 18:33:59 +0800 | [diff] [blame] | 593 | struct fence *last_vm_update; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 594 | }; |
| 595 | |
| 596 | void amdgpu_sync_create(struct amdgpu_sync *sync); |
Christian König | 91e1a52 | 2015-07-06 22:06:40 +0200 | [diff] [blame] | 597 | int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
| 598 | struct fence *f); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 599 | int amdgpu_sync_resv(struct amdgpu_device *adev, |
| 600 | struct amdgpu_sync *sync, |
| 601 | struct reservation_object *resv, |
| 602 | void *owner); |
Christian König | 832a902 | 2016-02-15 12:33:02 +0100 | [diff] [blame] | 603 | bool amdgpu_sync_is_idle(struct amdgpu_sync *sync); |
| 604 | int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src, |
| 605 | struct fence *fence); |
Christian König | e61235d | 2015-08-25 11:05:36 +0200 | [diff] [blame] | 606 | struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); |
Christian König | f91b3a6 | 2015-08-20 14:47:40 +0800 | [diff] [blame] | 607 | int amdgpu_sync_wait(struct amdgpu_sync *sync); |
Christian König | 8a8f0b4 | 2016-02-03 15:11:39 +0100 | [diff] [blame] | 608 | void amdgpu_sync_free(struct amdgpu_sync *sync); |
Christian König | 257bf15 | 2016-02-16 11:24:58 +0100 | [diff] [blame] | 609 | int amdgpu_sync_init(void); |
| 610 | void amdgpu_sync_fini(void); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 611 | |
| 612 | /* |
| 613 | * GART structures, functions & helpers |
| 614 | */ |
| 615 | struct amdgpu_mc; |
| 616 | |
| 617 | #define AMDGPU_GPU_PAGE_SIZE 4096 |
| 618 | #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) |
| 619 | #define AMDGPU_GPU_PAGE_SHIFT 12 |
| 620 | #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) |
| 621 | |
| 622 | struct amdgpu_gart { |
| 623 | dma_addr_t table_addr; |
| 624 | struct amdgpu_bo *robj; |
| 625 | void *ptr; |
| 626 | unsigned num_gpu_pages; |
| 627 | unsigned num_cpu_pages; |
| 628 | unsigned table_size; |
Christian König | a1d2947 | 2016-03-30 14:42:57 +0200 | [diff] [blame] | 629 | #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 630 | struct page **pages; |
Christian König | a1d2947 | 2016-03-30 14:42:57 +0200 | [diff] [blame] | 631 | #endif |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 632 | bool ready; |
| 633 | const struct amdgpu_gart_funcs *gart_funcs; |
| 634 | }; |
| 635 | |
| 636 | int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); |
| 637 | void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); |
| 638 | int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); |
| 639 | void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); |
| 640 | int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); |
| 641 | void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); |
| 642 | int amdgpu_gart_init(struct amdgpu_device *adev); |
| 643 | void amdgpu_gart_fini(struct amdgpu_device *adev); |
| 644 | void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, |
| 645 | int pages); |
| 646 | int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, |
| 647 | int pages, struct page **pagelist, |
| 648 | dma_addr_t *dma_addr, uint32_t flags); |
| 649 | |
| 650 | /* |
| 651 | * GPU MC structures, functions & helpers |
| 652 | */ |
| 653 | struct amdgpu_mc { |
| 654 | resource_size_t aper_size; |
| 655 | resource_size_t aper_base; |
| 656 | resource_size_t agp_base; |
| 657 | /* for some chips with <= 32MB we need to lie |
| 658 | * about vram size near mc fb location */ |
| 659 | u64 mc_vram_size; |
| 660 | u64 visible_vram_size; |
| 661 | u64 gtt_size; |
| 662 | u64 gtt_start; |
| 663 | u64 gtt_end; |
| 664 | u64 vram_start; |
| 665 | u64 vram_end; |
| 666 | unsigned vram_width; |
| 667 | u64 real_vram_size; |
| 668 | int vram_mtrr; |
| 669 | u64 gtt_base_align; |
| 670 | u64 mc_mask; |
| 671 | const struct firmware *fw; /* MC firmware */ |
| 672 | uint32_t fw_version; |
| 673 | struct amdgpu_irq_src vm_fault; |
Ken Wang | 81c59f5 | 2015-06-03 21:02:01 +0800 | [diff] [blame] | 674 | uint32_t vram_type; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 675 | }; |
| 676 | |
| 677 | /* |
| 678 | * GPU doorbell structures, functions & helpers |
| 679 | */ |
| 680 | typedef enum _AMDGPU_DOORBELL_ASSIGNMENT |
| 681 | { |
| 682 | AMDGPU_DOORBELL_KIQ = 0x000, |
| 683 | AMDGPU_DOORBELL_HIQ = 0x001, |
| 684 | AMDGPU_DOORBELL_DIQ = 0x002, |
| 685 | AMDGPU_DOORBELL_MEC_RING0 = 0x010, |
| 686 | AMDGPU_DOORBELL_MEC_RING1 = 0x011, |
| 687 | AMDGPU_DOORBELL_MEC_RING2 = 0x012, |
| 688 | AMDGPU_DOORBELL_MEC_RING3 = 0x013, |
| 689 | AMDGPU_DOORBELL_MEC_RING4 = 0x014, |
| 690 | AMDGPU_DOORBELL_MEC_RING5 = 0x015, |
| 691 | AMDGPU_DOORBELL_MEC_RING6 = 0x016, |
| 692 | AMDGPU_DOORBELL_MEC_RING7 = 0x017, |
| 693 | AMDGPU_DOORBELL_GFX_RING0 = 0x020, |
| 694 | AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, |
| 695 | AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, |
| 696 | AMDGPU_DOORBELL_IH = 0x1E8, |
| 697 | AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, |
| 698 | AMDGPU_DOORBELL_INVALID = 0xFFFF |
| 699 | } AMDGPU_DOORBELL_ASSIGNMENT; |
| 700 | |
| 701 | struct amdgpu_doorbell { |
| 702 | /* doorbell mmio */ |
| 703 | resource_size_t base; |
| 704 | resource_size_t size; |
| 705 | u32 __iomem *ptr; |
| 706 | u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ |
| 707 | }; |
| 708 | |
| 709 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, |
| 710 | phys_addr_t *aperture_base, |
| 711 | size_t *aperture_size, |
| 712 | size_t *start_offset); |
| 713 | |
| 714 | /* |
| 715 | * IRQS. |
| 716 | */ |
| 717 | |
| 718 | struct amdgpu_flip_work { |
| 719 | struct work_struct flip_work; |
| 720 | struct work_struct unpin_work; |
| 721 | struct amdgpu_device *adev; |
| 722 | int crtc_id; |
| 723 | uint64_t base; |
| 724 | struct drm_pending_vblank_event *event; |
| 725 | struct amdgpu_bo *old_rbo; |
Christian König | 1ffd265 | 2015-08-11 17:29:52 +0200 | [diff] [blame] | 726 | struct fence *excl; |
| 727 | unsigned shared_count; |
| 728 | struct fence **shared; |
Christian König | c3874b7 | 2016-02-11 15:48:30 +0100 | [diff] [blame] | 729 | struct fence_cb cb; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 730 | }; |
| 731 | |
| 732 | |
| 733 | /* |
| 734 | * CP & rings. |
| 735 | */ |
| 736 | |
| 737 | struct amdgpu_ib { |
| 738 | struct amdgpu_sa_bo *sa_bo; |
| 739 | uint32_t length_dw; |
| 740 | uint64_t gpu_addr; |
| 741 | uint32_t *ptr; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 742 | struct amdgpu_user_fence *user; |
Christian König | 4ff37a8 | 2016-02-26 16:18:26 +0100 | [diff] [blame] | 743 | unsigned vm_id; |
| 744 | uint64_t vm_pd_addr; |
Christian König | 3cb485f | 2015-05-11 15:34:59 +0200 | [diff] [blame] | 745 | struct amdgpu_ctx *ctx; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 746 | uint32_t gds_base, gds_size; |
| 747 | uint32_t gws_base, gws_size; |
| 748 | uint32_t oa_base, oa_size; |
Jammy Zhou | de807f8 | 2015-05-11 23:41:41 +0800 | [diff] [blame] | 749 | uint32_t flags; |
Christian König | 5430a3f | 2015-07-21 18:02:21 +0200 | [diff] [blame] | 750 | /* resulting sequence number */ |
| 751 | uint64_t sequence; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 752 | }; |
| 753 | |
| 754 | enum amdgpu_ring_type { |
| 755 | AMDGPU_RING_TYPE_GFX, |
| 756 | AMDGPU_RING_TYPE_COMPUTE, |
| 757 | AMDGPU_RING_TYPE_SDMA, |
| 758 | AMDGPU_RING_TYPE_UVD, |
| 759 | AMDGPU_RING_TYPE_VCE |
| 760 | }; |
| 761 | |
Nils Wallménius | 62250a9 | 2016-04-10 16:30:00 +0200 | [diff] [blame] | 762 | extern const struct amd_sched_backend_ops amdgpu_sched_ops; |
Chunming Zhou | c1b69ed | 2015-07-21 13:45:14 +0800 | [diff] [blame] | 763 | |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 764 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, |
Monk Liu | c563783 | 2016-04-19 20:11:32 +0800 | [diff] [blame^] | 765 | struct amdgpu_job **job, struct amdgpu_vm *vm); |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 766 | int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, |
| 767 | struct amdgpu_job **job); |
Monk Liu | b6723c8 | 2016-03-10 12:14:44 +0800 | [diff] [blame] | 768 | |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 769 | void amdgpu_job_free(struct amdgpu_job *job); |
Monk Liu | b6723c8 | 2016-03-10 12:14:44 +0800 | [diff] [blame] | 770 | void amdgpu_job_free_func(struct kref *refcount); |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 771 | int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 772 | struct amd_sched_entity *entity, void *owner, |
| 773 | struct fence **f); |
Monk Liu | 0de2479 | 2016-03-04 18:51:02 +0800 | [diff] [blame] | 774 | void amdgpu_job_timeout_func(struct work_struct *work); |
Chunming Zhou | 3c704e9 | 2015-07-29 10:33:14 +0800 | [diff] [blame] | 775 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 776 | struct amdgpu_ring { |
| 777 | struct amdgpu_device *adev; |
| 778 | const struct amdgpu_ring_funcs *funcs; |
| 779 | struct amdgpu_fence_driver fence_drv; |
Christian König | 4f839a2 | 2015-09-08 20:22:31 +0200 | [diff] [blame] | 780 | struct amd_gpu_scheduler sched; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 781 | |
Chunming Zhou | 176e1ab | 2015-07-24 10:49:47 +0800 | [diff] [blame] | 782 | spinlock_t fence_lock; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 783 | struct amdgpu_bo *ring_obj; |
| 784 | volatile uint32_t *ring; |
| 785 | unsigned rptr_offs; |
| 786 | u64 next_rptr_gpu_addr; |
| 787 | volatile u32 *next_rptr_cpu_addr; |
| 788 | unsigned wptr; |
| 789 | unsigned wptr_old; |
| 790 | unsigned ring_size; |
Christian König | c7e6be2 | 2016-01-21 13:06:05 +0100 | [diff] [blame] | 791 | unsigned max_dw; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 792 | int count_dw; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 793 | uint64_t gpu_addr; |
| 794 | uint32_t align_mask; |
| 795 | uint32_t ptr_mask; |
| 796 | bool ready; |
| 797 | u32 nop; |
| 798 | u32 idx; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 799 | u32 me; |
| 800 | u32 pipe; |
| 801 | u32 queue; |
| 802 | struct amdgpu_bo *mqd_obj; |
| 803 | u32 doorbell_index; |
| 804 | bool use_doorbell; |
| 805 | unsigned wptr_offs; |
| 806 | unsigned next_rptr_offs; |
| 807 | unsigned fence_offs; |
Christian König | 3cb485f | 2015-05-11 15:34:59 +0200 | [diff] [blame] | 808 | struct amdgpu_ctx *current_ctx; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 809 | enum amdgpu_ring_type type; |
| 810 | char name[16]; |
Monk Liu | 128cff1 | 2016-01-14 18:08:16 +0800 | [diff] [blame] | 811 | unsigned cond_exe_offs; |
| 812 | u64 cond_exe_gpu_addr; |
| 813 | volatile u32 *cond_exe_cpu_addr; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 814 | }; |
| 815 | |
| 816 | /* |
| 817 | * VM |
| 818 | */ |
| 819 | |
| 820 | /* maximum number of VMIDs */ |
| 821 | #define AMDGPU_NUM_VM 16 |
| 822 | |
| 823 | /* number of entries in page table */ |
| 824 | #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) |
| 825 | |
| 826 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
| 827 | #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 |
| 828 | #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) |
| 829 | #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) |
| 830 | |
| 831 | #define AMDGPU_PTE_VALID (1 << 0) |
| 832 | #define AMDGPU_PTE_SYSTEM (1 << 1) |
| 833 | #define AMDGPU_PTE_SNOOPED (1 << 2) |
| 834 | |
| 835 | /* VI only */ |
| 836 | #define AMDGPU_PTE_EXECUTABLE (1 << 4) |
| 837 | |
| 838 | #define AMDGPU_PTE_READABLE (1 << 5) |
| 839 | #define AMDGPU_PTE_WRITEABLE (1 << 6) |
| 840 | |
| 841 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
| 842 | #define AMDGPU_PTE_FRAG_4KB (0 << 7) |
| 843 | #define AMDGPU_PTE_FRAG_64KB (4 << 7) |
| 844 | #define AMDGPU_LOG2_PAGES_PER_FRAG 4 |
| 845 | |
Christian König | d9c1315 | 2015-09-28 12:31:26 +0200 | [diff] [blame] | 846 | /* How to programm VM fault handling */ |
| 847 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 |
| 848 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 |
| 849 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 |
| 850 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 851 | struct amdgpu_vm_pt { |
Christian König | ee1782c | 2015-12-11 21:01:23 +0100 | [diff] [blame] | 852 | struct amdgpu_bo_list_entry entry; |
| 853 | uint64_t addr; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 854 | }; |
| 855 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 856 | struct amdgpu_vm { |
Christian König | 25cfc3c | 2015-12-19 19:42:05 +0100 | [diff] [blame] | 857 | /* tree of virtual addresses mapped */ |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 858 | struct rb_root va; |
| 859 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 860 | /* protecting invalidated */ |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 861 | spinlock_t status_lock; |
| 862 | |
| 863 | /* BOs moved, but not yet updated in the PT */ |
| 864 | struct list_head invalidated; |
| 865 | |
Christian König | 7fc1195 | 2015-07-30 11:53:42 +0200 | [diff] [blame] | 866 | /* BOs cleared in the PT because of a move */ |
| 867 | struct list_head cleared; |
| 868 | |
| 869 | /* BO mappings freed, but not yet updated in the PT */ |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 870 | struct list_head freed; |
| 871 | |
| 872 | /* contains the page directory */ |
| 873 | struct amdgpu_bo *page_directory; |
| 874 | unsigned max_pde_used; |
Bas Nieuwenhuizen | 05906de | 2015-08-14 20:08:40 +0200 | [diff] [blame] | 875 | struct fence *page_directory_fence; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 876 | |
| 877 | /* array of page tables, one for each page directory entry */ |
| 878 | struct amdgpu_vm_pt *page_tables; |
| 879 | |
| 880 | /* for id and flush management per ring */ |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 881 | struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; |
Christian König | 25cfc3c | 2015-12-19 19:42:05 +0100 | [diff] [blame] | 882 | |
jimqu | 81d75a3 | 2015-12-04 17:17:00 +0800 | [diff] [blame] | 883 | /* protecting freed */ |
| 884 | spinlock_t freed_lock; |
Christian König | 2bd9ccf | 2016-02-01 12:53:58 +0100 | [diff] [blame] | 885 | |
| 886 | /* Scheduler entity for page table updates */ |
| 887 | struct amd_sched_entity entity; |
Chunming Zhou | 031e298 | 2016-04-25 10:19:13 +0800 | [diff] [blame] | 888 | |
| 889 | /* client id */ |
| 890 | u64 client_id; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 891 | }; |
| 892 | |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 893 | struct amdgpu_vm_id { |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 894 | struct list_head list; |
Christian König | 832a902 | 2016-02-15 12:33:02 +0100 | [diff] [blame] | 895 | struct fence *first; |
| 896 | struct amdgpu_sync active; |
Christian König | 41d9eb2 | 2016-03-01 16:46:18 +0100 | [diff] [blame] | 897 | struct fence *last_flush; |
Chunming Zhou | 68befeb | 2016-04-14 13:42:32 +0800 | [diff] [blame] | 898 | struct amdgpu_ring *last_user; |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 899 | atomic_long_t owner; |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 900 | |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 901 | uint64_t pd_gpu_addr; |
| 902 | /* last flushed PD/PT update */ |
| 903 | struct fence *flushed_updates; |
| 904 | |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 905 | uint32_t gds_base; |
| 906 | uint32_t gds_size; |
| 907 | uint32_t gws_base; |
| 908 | uint32_t gws_size; |
| 909 | uint32_t oa_base; |
| 910 | uint32_t oa_size; |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 911 | }; |
Christian König | 8d0a7ce | 2015-11-03 20:58:50 +0100 | [diff] [blame] | 912 | |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 913 | struct amdgpu_vm_manager { |
| 914 | /* Handling of VMIDs */ |
| 915 | struct mutex lock; |
| 916 | unsigned num_ids; |
| 917 | struct list_head ids_lru; |
Christian König | bcb1ba3 | 2016-03-08 15:40:11 +0100 | [diff] [blame] | 918 | struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; |
Christian König | 1c16c0a | 2015-11-14 21:31:40 +0100 | [diff] [blame] | 919 | |
Christian König | 8b4fb00 | 2015-11-15 16:04:16 +0100 | [diff] [blame] | 920 | uint32_t max_pfn; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 921 | /* vram base address for page table entry */ |
Christian König | 8b4fb00 | 2015-11-15 16:04:16 +0100 | [diff] [blame] | 922 | u64 vram_base_offset; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 923 | /* is vm enabled? */ |
Christian König | 8b4fb00 | 2015-11-15 16:04:16 +0100 | [diff] [blame] | 924 | bool enabled; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 925 | /* vm pte handling */ |
| 926 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; |
Christian König | 2d55e45 | 2016-02-08 17:37:38 +0100 | [diff] [blame] | 927 | struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; |
| 928 | unsigned vm_pte_num_rings; |
| 929 | atomic_t vm_pte_next_ring; |
Chunming Zhou | 031e298 | 2016-04-25 10:19:13 +0800 | [diff] [blame] | 930 | /* client id counter */ |
| 931 | atomic64_t client_counter; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 932 | }; |
| 933 | |
Christian König | a9a78b3 | 2016-01-21 10:19:11 +0100 | [diff] [blame] | 934 | void amdgpu_vm_manager_init(struct amdgpu_device *adev); |
Christian König | ea89f8c | 2015-11-15 20:52:06 +0100 | [diff] [blame] | 935 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); |
Christian König | 8b4fb00 | 2015-11-15 16:04:16 +0100 | [diff] [blame] | 936 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
| 937 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
Christian König | 56467eb | 2015-12-11 15:16:32 +0100 | [diff] [blame] | 938 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
| 939 | struct list_head *validated, |
| 940 | struct amdgpu_bo_list_entry *entry); |
Christian König | ee1782c | 2015-12-11 21:01:23 +0100 | [diff] [blame] | 941 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); |
Christian König | eceb8a1 | 2016-01-11 15:35:21 +0100 | [diff] [blame] | 942 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, |
| 943 | struct amdgpu_vm *vm); |
Christian König | 8b4fb00 | 2015-11-15 16:04:16 +0100 | [diff] [blame] | 944 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
Christian König | 4ff37a8 | 2016-02-26 16:18:26 +0100 | [diff] [blame] | 945 | struct amdgpu_sync *sync, struct fence *fence, |
| 946 | unsigned *vm_id, uint64_t *vm_pd_addr); |
Christian König | 41d9eb2 | 2016-03-01 16:46:18 +0100 | [diff] [blame] | 947 | int amdgpu_vm_flush(struct amdgpu_ring *ring, |
| 948 | unsigned vm_id, uint64_t pd_addr, |
| 949 | uint32_t gds_base, uint32_t gds_size, |
| 950 | uint32_t gws_base, uint32_t gws_size, |
| 951 | uint32_t oa_base, uint32_t oa_size); |
Christian König | 971fe9a9 | 2016-03-01 15:09:25 +0100 | [diff] [blame] | 952 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); |
Christian König | b07c9d2 | 2015-11-30 13:26:07 +0100 | [diff] [blame] | 953 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); |
Christian König | 8b4fb00 | 2015-11-15 16:04:16 +0100 | [diff] [blame] | 954 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, |
| 955 | struct amdgpu_vm *vm); |
| 956 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, |
| 957 | struct amdgpu_vm *vm); |
| 958 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 959 | struct amdgpu_sync *sync); |
| 960 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, |
| 961 | struct amdgpu_bo_va *bo_va, |
| 962 | struct ttm_mem_reg *mem); |
| 963 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, |
| 964 | struct amdgpu_bo *bo); |
| 965 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, |
| 966 | struct amdgpu_bo *bo); |
| 967 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, |
| 968 | struct amdgpu_vm *vm, |
| 969 | struct amdgpu_bo *bo); |
| 970 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, |
| 971 | struct amdgpu_bo_va *bo_va, |
| 972 | uint64_t addr, uint64_t offset, |
| 973 | uint64_t size, uint32_t flags); |
| 974 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, |
| 975 | struct amdgpu_bo_va *bo_va, |
| 976 | uint64_t addr); |
| 977 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, |
| 978 | struct amdgpu_bo_va *bo_va); |
Christian König | 8b4fb00 | 2015-11-15 16:04:16 +0100 | [diff] [blame] | 979 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 980 | /* |
| 981 | * context related structures |
| 982 | */ |
| 983 | |
Christian König | 21c16bf | 2015-07-07 17:24:49 +0200 | [diff] [blame] | 984 | struct amdgpu_ctx_ring { |
Christian König | 91404fb | 2015-08-05 18:33:21 +0200 | [diff] [blame] | 985 | uint64_t sequence; |
Chunming Zhou | 37cd0ca | 2015-12-10 15:45:11 +0800 | [diff] [blame] | 986 | struct fence **fences; |
Christian König | 91404fb | 2015-08-05 18:33:21 +0200 | [diff] [blame] | 987 | struct amd_sched_entity entity; |
Christian König | 21c16bf | 2015-07-07 17:24:49 +0200 | [diff] [blame] | 988 | }; |
| 989 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 990 | struct amdgpu_ctx { |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 991 | struct kref refcount; |
Chunming Zhou | 9cb7e5a | 2015-07-21 13:17:19 +0800 | [diff] [blame] | 992 | struct amdgpu_device *adev; |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 993 | unsigned reset_counter; |
Christian König | 21c16bf | 2015-07-07 17:24:49 +0200 | [diff] [blame] | 994 | spinlock_t ring_lock; |
Chunming Zhou | 37cd0ca | 2015-12-10 15:45:11 +0800 | [diff] [blame] | 995 | struct fence **fences; |
Christian König | 21c16bf | 2015-07-07 17:24:49 +0200 | [diff] [blame] | 996 | struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 997 | }; |
| 998 | |
| 999 | struct amdgpu_ctx_mgr { |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 1000 | struct amdgpu_device *adev; |
| 1001 | struct mutex lock; |
| 1002 | /* protected by lock */ |
| 1003 | struct idr ctx_handles; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1004 | }; |
| 1005 | |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 1006 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); |
| 1007 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx); |
| 1008 | |
Christian König | 21c16bf | 2015-07-07 17:24:49 +0200 | [diff] [blame] | 1009 | uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, |
Christian König | ce882e6 | 2015-08-19 15:00:55 +0200 | [diff] [blame] | 1010 | struct fence *fence); |
Christian König | 21c16bf | 2015-07-07 17:24:49 +0200 | [diff] [blame] | 1011 | struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, |
| 1012 | struct amdgpu_ring *ring, uint64_t seq); |
| 1013 | |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 1014 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, |
| 1015 | struct drm_file *filp); |
| 1016 | |
Christian König | efd4ccb | 2015-08-04 16:20:31 +0200 | [diff] [blame] | 1017 | void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); |
| 1018 | void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 1019 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1020 | /* |
| 1021 | * file private structure |
| 1022 | */ |
| 1023 | |
| 1024 | struct amdgpu_fpriv { |
| 1025 | struct amdgpu_vm vm; |
| 1026 | struct mutex bo_list_lock; |
| 1027 | struct idr bo_list_handles; |
Alex Deucher | 0b492a4 | 2015-08-16 22:48:26 -0400 | [diff] [blame] | 1028 | struct amdgpu_ctx_mgr ctx_mgr; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1029 | }; |
| 1030 | |
| 1031 | /* |
| 1032 | * residency list |
| 1033 | */ |
| 1034 | |
| 1035 | struct amdgpu_bo_list { |
| 1036 | struct mutex lock; |
| 1037 | struct amdgpu_bo *gds_obj; |
| 1038 | struct amdgpu_bo *gws_obj; |
| 1039 | struct amdgpu_bo *oa_obj; |
Christian König | 211dff5 | 2016-02-22 15:40:59 +0100 | [diff] [blame] | 1040 | unsigned first_userptr; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1041 | unsigned num_entries; |
| 1042 | struct amdgpu_bo_list_entry *array; |
| 1043 | }; |
| 1044 | |
| 1045 | struct amdgpu_bo_list * |
| 1046 | amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); |
Christian König | 636ce25 | 2015-12-18 21:26:47 +0100 | [diff] [blame] | 1047 | void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, |
| 1048 | struct list_head *validated); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1049 | void amdgpu_bo_list_put(struct amdgpu_bo_list *list); |
| 1050 | void amdgpu_bo_list_free(struct amdgpu_bo_list *list); |
| 1051 | |
| 1052 | /* |
| 1053 | * GFX stuff |
| 1054 | */ |
| 1055 | #include "clearstate_defs.h" |
| 1056 | |
Alex Deucher | 79e5412 | 2016-04-08 15:45:13 -0400 | [diff] [blame] | 1057 | struct amdgpu_rlc_funcs { |
| 1058 | void (*enter_safe_mode)(struct amdgpu_device *adev); |
| 1059 | void (*exit_safe_mode)(struct amdgpu_device *adev); |
| 1060 | }; |
| 1061 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1062 | struct amdgpu_rlc { |
| 1063 | /* for power gating */ |
| 1064 | struct amdgpu_bo *save_restore_obj; |
| 1065 | uint64_t save_restore_gpu_addr; |
| 1066 | volatile uint32_t *sr_ptr; |
| 1067 | const u32 *reg_list; |
| 1068 | u32 reg_list_size; |
| 1069 | /* for clear state */ |
| 1070 | struct amdgpu_bo *clear_state_obj; |
| 1071 | uint64_t clear_state_gpu_addr; |
| 1072 | volatile uint32_t *cs_ptr; |
| 1073 | const struct cs_section_def *cs_data; |
| 1074 | u32 clear_state_size; |
| 1075 | /* for cp tables */ |
| 1076 | struct amdgpu_bo *cp_table_obj; |
| 1077 | uint64_t cp_table_gpu_addr; |
| 1078 | volatile uint32_t *cp_table_ptr; |
| 1079 | u32 cp_table_size; |
Alex Deucher | 79e5412 | 2016-04-08 15:45:13 -0400 | [diff] [blame] | 1080 | |
| 1081 | /* safe mode for updating CG/PG state */ |
| 1082 | bool in_safe_mode; |
| 1083 | const struct amdgpu_rlc_funcs *funcs; |
Eric Huang | 2b6cd97 | 2016-04-14 17:26:07 -0400 | [diff] [blame] | 1084 | |
| 1085 | /* for firmware data */ |
| 1086 | u32 save_and_restore_offset; |
| 1087 | u32 clear_state_descriptor_offset; |
| 1088 | u32 avail_scratch_ram_locations; |
| 1089 | u32 reg_restore_list_size; |
| 1090 | u32 reg_list_format_start; |
| 1091 | u32 reg_list_format_separate_start; |
| 1092 | u32 starting_offsets_start; |
| 1093 | u32 reg_list_format_size_bytes; |
| 1094 | u32 reg_list_size_bytes; |
| 1095 | |
| 1096 | u32 *register_list_format; |
| 1097 | u32 *register_restore; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1098 | }; |
| 1099 | |
| 1100 | struct amdgpu_mec { |
| 1101 | struct amdgpu_bo *hpd_eop_obj; |
| 1102 | u64 hpd_eop_gpu_addr; |
| 1103 | u32 num_pipe; |
| 1104 | u32 num_mec; |
| 1105 | u32 num_queue; |
| 1106 | }; |
| 1107 | |
| 1108 | /* |
| 1109 | * GPU scratch registers structures, functions & helpers |
| 1110 | */ |
| 1111 | struct amdgpu_scratch { |
| 1112 | unsigned num_reg; |
| 1113 | uint32_t reg_base; |
| 1114 | bool free[32]; |
| 1115 | uint32_t reg[32]; |
| 1116 | }; |
| 1117 | |
| 1118 | /* |
| 1119 | * GFX configurations |
| 1120 | */ |
| 1121 | struct amdgpu_gca_config { |
| 1122 | unsigned max_shader_engines; |
| 1123 | unsigned max_tile_pipes; |
| 1124 | unsigned max_cu_per_sh; |
| 1125 | unsigned max_sh_per_se; |
| 1126 | unsigned max_backends_per_se; |
| 1127 | unsigned max_texture_channel_caches; |
| 1128 | unsigned max_gprs; |
| 1129 | unsigned max_gs_threads; |
| 1130 | unsigned max_hw_contexts; |
| 1131 | unsigned sc_prim_fifo_size_frontend; |
| 1132 | unsigned sc_prim_fifo_size_backend; |
| 1133 | unsigned sc_hiz_tile_fifo_size; |
| 1134 | unsigned sc_earlyz_tile_fifo_size; |
| 1135 | |
| 1136 | unsigned num_tile_pipes; |
| 1137 | unsigned backend_enable_mask; |
| 1138 | unsigned mem_max_burst_length_bytes; |
| 1139 | unsigned mem_row_size_in_kb; |
| 1140 | unsigned shader_engine_tile_size; |
| 1141 | unsigned num_gpus; |
| 1142 | unsigned multi_gpu_tile_size; |
| 1143 | unsigned mc_arb_ramcfg; |
| 1144 | unsigned gb_addr_config; |
Alex Deucher | 8f8e00c | 2016-02-12 00:39:13 -0500 | [diff] [blame] | 1145 | unsigned num_rbs; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1146 | |
| 1147 | uint32_t tile_mode_array[32]; |
| 1148 | uint32_t macrotile_mode_array[16]; |
| 1149 | }; |
| 1150 | |
| 1151 | struct amdgpu_gfx { |
| 1152 | struct mutex gpu_clock_mutex; |
| 1153 | struct amdgpu_gca_config config; |
| 1154 | struct amdgpu_rlc rlc; |
| 1155 | struct amdgpu_mec mec; |
| 1156 | struct amdgpu_scratch scratch; |
| 1157 | const struct firmware *me_fw; /* ME firmware */ |
| 1158 | uint32_t me_fw_version; |
| 1159 | const struct firmware *pfp_fw; /* PFP firmware */ |
| 1160 | uint32_t pfp_fw_version; |
| 1161 | const struct firmware *ce_fw; /* CE firmware */ |
| 1162 | uint32_t ce_fw_version; |
| 1163 | const struct firmware *rlc_fw; /* RLC firmware */ |
| 1164 | uint32_t rlc_fw_version; |
| 1165 | const struct firmware *mec_fw; /* MEC firmware */ |
| 1166 | uint32_t mec_fw_version; |
| 1167 | const struct firmware *mec2_fw; /* MEC2 firmware */ |
| 1168 | uint32_t mec2_fw_version; |
Ken Wang | 02558a0 | 2015-06-03 19:52:06 +0800 | [diff] [blame] | 1169 | uint32_t me_feature_version; |
| 1170 | uint32_t ce_feature_version; |
| 1171 | uint32_t pfp_feature_version; |
Jammy Zhou | 351643d | 2015-08-04 10:43:50 +0800 | [diff] [blame] | 1172 | uint32_t rlc_feature_version; |
| 1173 | uint32_t mec_feature_version; |
| 1174 | uint32_t mec2_feature_version; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1175 | struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; |
| 1176 | unsigned num_gfx_rings; |
| 1177 | struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; |
| 1178 | unsigned num_compute_rings; |
| 1179 | struct amdgpu_irq_src eop_irq; |
| 1180 | struct amdgpu_irq_src priv_reg_irq; |
| 1181 | struct amdgpu_irq_src priv_inst_irq; |
| 1182 | /* gfx status */ |
| 1183 | uint32_t gfx_current_status; |
Ken Wang | a101a89 | 2015-06-03 17:47:54 +0800 | [diff] [blame] | 1184 | /* ce ram size*/ |
| 1185 | unsigned ce_ram_size; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1186 | }; |
| 1187 | |
Christian König | b07c60c | 2016-01-31 12:29:04 +0100 | [diff] [blame] | 1188 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1189 | unsigned size, struct amdgpu_ib *ib); |
Monk Liu | cc55c45 | 2016-03-17 10:47:07 +0800 | [diff] [blame] | 1190 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f); |
Christian König | b07c60c | 2016-01-31 12:29:04 +0100 | [diff] [blame] | 1191 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, |
Christian König | 336d1f5 | 2016-02-16 10:57:10 +0100 | [diff] [blame] | 1192 | struct amdgpu_ib *ib, struct fence *last_vm_update, |
Monk Liu | c563783 | 2016-04-19 20:11:32 +0800 | [diff] [blame^] | 1193 | struct amdgpu_job *job, struct fence **f); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1194 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
| 1195 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); |
| 1196 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1197 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); |
Jammy Zhou | edff0e2 | 2015-09-01 13:04:08 +0800 | [diff] [blame] | 1198 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); |
Christian König | 9e5d5309 | 2016-01-31 12:20:55 +0100 | [diff] [blame] | 1199 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1200 | void amdgpu_ring_commit(struct amdgpu_ring *ring); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1201 | void amdgpu_ring_undo(struct amdgpu_ring *ring); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1202 | unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, |
| 1203 | uint32_t **data); |
| 1204 | int amdgpu_ring_restore(struct amdgpu_ring *ring, |
| 1205 | unsigned size, uint32_t *data); |
| 1206 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, |
| 1207 | unsigned ring_size, u32 nop, u32 align_mask, |
| 1208 | struct amdgpu_irq_src *irq_src, unsigned irq_type, |
| 1209 | enum amdgpu_ring_type ring_type); |
| 1210 | void amdgpu_ring_fini(struct amdgpu_ring *ring); |
| 1211 | |
| 1212 | /* |
| 1213 | * CS. |
| 1214 | */ |
| 1215 | struct amdgpu_cs_chunk { |
| 1216 | uint32_t chunk_id; |
| 1217 | uint32_t length_dw; |
| 1218 | uint32_t *kdata; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1219 | }; |
| 1220 | |
| 1221 | struct amdgpu_cs_parser { |
| 1222 | struct amdgpu_device *adev; |
| 1223 | struct drm_file *filp; |
Christian König | 3cb485f | 2015-05-11 15:34:59 +0200 | [diff] [blame] | 1224 | struct amdgpu_ctx *ctx; |
Christian König | c3cca41 | 2015-12-15 14:41:33 +0100 | [diff] [blame] | 1225 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1226 | /* chunks */ |
| 1227 | unsigned nchunks; |
| 1228 | struct amdgpu_cs_chunk *chunks; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1229 | |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 1230 | /* scheduler job object */ |
| 1231 | struct amdgpu_job *job; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1232 | |
Christian König | c3cca41 | 2015-12-15 14:41:33 +0100 | [diff] [blame] | 1233 | /* buffer objects */ |
| 1234 | struct ww_acquire_ctx ticket; |
| 1235 | struct amdgpu_bo_list *bo_list; |
| 1236 | struct amdgpu_bo_list_entry vm_pd; |
| 1237 | struct list_head validated; |
| 1238 | struct fence *fence; |
| 1239 | uint64_t bytes_moved_threshold; |
| 1240 | uint64_t bytes_moved; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1241 | |
| 1242 | /* user fence */ |
Christian König | 91acbeb | 2015-12-14 16:42:31 +0100 | [diff] [blame] | 1243 | struct amdgpu_bo_list_entry uf_entry; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1244 | }; |
| 1245 | |
Chunming Zhou | bb977d3 | 2015-08-18 15:16:40 +0800 | [diff] [blame] | 1246 | struct amdgpu_job { |
| 1247 | struct amd_sched_job base; |
| 1248 | struct amdgpu_device *adev; |
Monk Liu | c563783 | 2016-04-19 20:11:32 +0800 | [diff] [blame^] | 1249 | struct amdgpu_vm *vm; |
Christian König | b07c60c | 2016-01-31 12:29:04 +0100 | [diff] [blame] | 1250 | struct amdgpu_ring *ring; |
Christian König | e86f9ce | 2016-02-08 12:13:05 +0100 | [diff] [blame] | 1251 | struct amdgpu_sync sync; |
Chunming Zhou | bb977d3 | 2015-08-18 15:16:40 +0800 | [diff] [blame] | 1252 | struct amdgpu_ib *ibs; |
Monk Liu | 73cfa5f | 2016-03-17 13:48:13 +0800 | [diff] [blame] | 1253 | struct fence *fence; /* the hw fence */ |
Chunming Zhou | bb977d3 | 2015-08-18 15:16:40 +0800 | [diff] [blame] | 1254 | uint32_t num_ibs; |
Christian König | e284022 | 2015-11-05 19:49:48 +0100 | [diff] [blame] | 1255 | void *owner; |
Chunming Zhou | bb977d3 | 2015-08-18 15:16:40 +0800 | [diff] [blame] | 1256 | struct amdgpu_user_fence uf; |
Chunming Zhou | bb977d3 | 2015-08-18 15:16:40 +0800 | [diff] [blame] | 1257 | }; |
Junwei Zhang | a6db8a3 | 2015-09-09 09:21:19 +0800 | [diff] [blame] | 1258 | #define to_amdgpu_job(sched_job) \ |
| 1259 | container_of((sched_job), struct amdgpu_job, base) |
Chunming Zhou | bb977d3 | 2015-08-18 15:16:40 +0800 | [diff] [blame] | 1260 | |
Christian König | 7270f83 | 2016-01-31 11:00:41 +0100 | [diff] [blame] | 1261 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, |
| 1262 | uint32_t ib_idx, int idx) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1263 | { |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 1264 | return p->job->ibs[ib_idx].ptr[idx]; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1265 | } |
| 1266 | |
Christian König | 7270f83 | 2016-01-31 11:00:41 +0100 | [diff] [blame] | 1267 | static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, |
| 1268 | uint32_t ib_idx, int idx, |
| 1269 | uint32_t value) |
| 1270 | { |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 1271 | p->job->ibs[ib_idx].ptr[idx] = value; |
Christian König | 7270f83 | 2016-01-31 11:00:41 +0100 | [diff] [blame] | 1272 | } |
| 1273 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1274 | /* |
| 1275 | * Writeback |
| 1276 | */ |
| 1277 | #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ |
| 1278 | |
| 1279 | struct amdgpu_wb { |
| 1280 | struct amdgpu_bo *wb_obj; |
| 1281 | volatile uint32_t *wb; |
| 1282 | uint64_t gpu_addr; |
| 1283 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ |
| 1284 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; |
| 1285 | }; |
| 1286 | |
| 1287 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); |
| 1288 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); |
| 1289 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1290 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1291 | |
| 1292 | enum amdgpu_int_thermal_type { |
| 1293 | THERMAL_TYPE_NONE, |
| 1294 | THERMAL_TYPE_EXTERNAL, |
| 1295 | THERMAL_TYPE_EXTERNAL_GPIO, |
| 1296 | THERMAL_TYPE_RV6XX, |
| 1297 | THERMAL_TYPE_RV770, |
| 1298 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
| 1299 | THERMAL_TYPE_EVERGREEN, |
| 1300 | THERMAL_TYPE_SUMO, |
| 1301 | THERMAL_TYPE_NI, |
| 1302 | THERMAL_TYPE_SI, |
| 1303 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
| 1304 | THERMAL_TYPE_CI, |
| 1305 | THERMAL_TYPE_KV, |
| 1306 | }; |
| 1307 | |
| 1308 | enum amdgpu_dpm_auto_throttle_src { |
| 1309 | AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, |
| 1310 | AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
| 1311 | }; |
| 1312 | |
| 1313 | enum amdgpu_dpm_event_src { |
| 1314 | AMDGPU_DPM_EVENT_SRC_ANALOG = 0, |
| 1315 | AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, |
| 1316 | AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, |
| 1317 | AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
| 1318 | AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
| 1319 | }; |
| 1320 | |
| 1321 | #define AMDGPU_MAX_VCE_LEVELS 6 |
| 1322 | |
| 1323 | enum amdgpu_vce_level { |
| 1324 | AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
| 1325 | AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
| 1326 | AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
| 1327 | AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
| 1328 | AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
| 1329 | AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
| 1330 | }; |
| 1331 | |
| 1332 | struct amdgpu_ps { |
| 1333 | u32 caps; /* vbios flags */ |
| 1334 | u32 class; /* vbios flags */ |
| 1335 | u32 class2; /* vbios flags */ |
| 1336 | /* UVD clocks */ |
| 1337 | u32 vclk; |
| 1338 | u32 dclk; |
| 1339 | /* VCE clocks */ |
| 1340 | u32 evclk; |
| 1341 | u32 ecclk; |
| 1342 | bool vce_active; |
| 1343 | enum amdgpu_vce_level vce_level; |
| 1344 | /* asic priv */ |
| 1345 | void *ps_priv; |
| 1346 | }; |
| 1347 | |
| 1348 | struct amdgpu_dpm_thermal { |
| 1349 | /* thermal interrupt work */ |
| 1350 | struct work_struct work; |
| 1351 | /* low temperature threshold */ |
| 1352 | int min_temp; |
| 1353 | /* high temperature threshold */ |
| 1354 | int max_temp; |
| 1355 | /* was last interrupt low to high or high to low */ |
| 1356 | bool high_to_low; |
| 1357 | /* interrupt source */ |
| 1358 | struct amdgpu_irq_src irq; |
| 1359 | }; |
| 1360 | |
| 1361 | enum amdgpu_clk_action |
| 1362 | { |
| 1363 | AMDGPU_SCLK_UP = 1, |
| 1364 | AMDGPU_SCLK_DOWN |
| 1365 | }; |
| 1366 | |
| 1367 | struct amdgpu_blacklist_clocks |
| 1368 | { |
| 1369 | u32 sclk; |
| 1370 | u32 mclk; |
| 1371 | enum amdgpu_clk_action action; |
| 1372 | }; |
| 1373 | |
| 1374 | struct amdgpu_clock_and_voltage_limits { |
| 1375 | u32 sclk; |
| 1376 | u32 mclk; |
| 1377 | u16 vddc; |
| 1378 | u16 vddci; |
| 1379 | }; |
| 1380 | |
| 1381 | struct amdgpu_clock_array { |
| 1382 | u32 count; |
| 1383 | u32 *values; |
| 1384 | }; |
| 1385 | |
| 1386 | struct amdgpu_clock_voltage_dependency_entry { |
| 1387 | u32 clk; |
| 1388 | u16 v; |
| 1389 | }; |
| 1390 | |
| 1391 | struct amdgpu_clock_voltage_dependency_table { |
| 1392 | u32 count; |
| 1393 | struct amdgpu_clock_voltage_dependency_entry *entries; |
| 1394 | }; |
| 1395 | |
| 1396 | union amdgpu_cac_leakage_entry { |
| 1397 | struct { |
| 1398 | u16 vddc; |
| 1399 | u32 leakage; |
| 1400 | }; |
| 1401 | struct { |
| 1402 | u16 vddc1; |
| 1403 | u16 vddc2; |
| 1404 | u16 vddc3; |
| 1405 | }; |
| 1406 | }; |
| 1407 | |
| 1408 | struct amdgpu_cac_leakage_table { |
| 1409 | u32 count; |
| 1410 | union amdgpu_cac_leakage_entry *entries; |
| 1411 | }; |
| 1412 | |
| 1413 | struct amdgpu_phase_shedding_limits_entry { |
| 1414 | u16 voltage; |
| 1415 | u32 sclk; |
| 1416 | u32 mclk; |
| 1417 | }; |
| 1418 | |
| 1419 | struct amdgpu_phase_shedding_limits_table { |
| 1420 | u32 count; |
| 1421 | struct amdgpu_phase_shedding_limits_entry *entries; |
| 1422 | }; |
| 1423 | |
| 1424 | struct amdgpu_uvd_clock_voltage_dependency_entry { |
| 1425 | u32 vclk; |
| 1426 | u32 dclk; |
| 1427 | u16 v; |
| 1428 | }; |
| 1429 | |
| 1430 | struct amdgpu_uvd_clock_voltage_dependency_table { |
| 1431 | u8 count; |
| 1432 | struct amdgpu_uvd_clock_voltage_dependency_entry *entries; |
| 1433 | }; |
| 1434 | |
| 1435 | struct amdgpu_vce_clock_voltage_dependency_entry { |
| 1436 | u32 ecclk; |
| 1437 | u32 evclk; |
| 1438 | u16 v; |
| 1439 | }; |
| 1440 | |
| 1441 | struct amdgpu_vce_clock_voltage_dependency_table { |
| 1442 | u8 count; |
| 1443 | struct amdgpu_vce_clock_voltage_dependency_entry *entries; |
| 1444 | }; |
| 1445 | |
| 1446 | struct amdgpu_ppm_table { |
| 1447 | u8 ppm_design; |
| 1448 | u16 cpu_core_number; |
| 1449 | u32 platform_tdp; |
| 1450 | u32 small_ac_platform_tdp; |
| 1451 | u32 platform_tdc; |
| 1452 | u32 small_ac_platform_tdc; |
| 1453 | u32 apu_tdp; |
| 1454 | u32 dgpu_tdp; |
| 1455 | u32 dgpu_ulv_power; |
| 1456 | u32 tj_max; |
| 1457 | }; |
| 1458 | |
| 1459 | struct amdgpu_cac_tdp_table { |
| 1460 | u16 tdp; |
| 1461 | u16 configurable_tdp; |
| 1462 | u16 tdc; |
| 1463 | u16 battery_power_limit; |
| 1464 | u16 small_power_limit; |
| 1465 | u16 low_cac_leakage; |
| 1466 | u16 high_cac_leakage; |
| 1467 | u16 maximum_power_delivery_limit; |
| 1468 | }; |
| 1469 | |
| 1470 | struct amdgpu_dpm_dynamic_state { |
| 1471 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; |
| 1472 | struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; |
| 1473 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; |
| 1474 | struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
| 1475 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
| 1476 | struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
| 1477 | struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
| 1478 | struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
| 1479 | struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
| 1480 | struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; |
| 1481 | struct amdgpu_clock_array valid_sclk_values; |
| 1482 | struct amdgpu_clock_array valid_mclk_values; |
| 1483 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; |
| 1484 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; |
| 1485 | u32 mclk_sclk_ratio; |
| 1486 | u32 sclk_mclk_delta; |
| 1487 | u16 vddc_vddci_delta; |
| 1488 | u16 min_vddc_for_pcie_gen2; |
| 1489 | struct amdgpu_cac_leakage_table cac_leakage_table; |
| 1490 | struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; |
| 1491 | struct amdgpu_ppm_table *ppm_table; |
| 1492 | struct amdgpu_cac_tdp_table *cac_tdp_table; |
| 1493 | }; |
| 1494 | |
| 1495 | struct amdgpu_dpm_fan { |
| 1496 | u16 t_min; |
| 1497 | u16 t_med; |
| 1498 | u16 t_high; |
| 1499 | u16 pwm_min; |
| 1500 | u16 pwm_med; |
| 1501 | u16 pwm_high; |
| 1502 | u8 t_hyst; |
| 1503 | u32 cycle_delay; |
| 1504 | u16 t_max; |
| 1505 | u8 control_mode; |
| 1506 | u16 default_max_fan_pwm; |
| 1507 | u16 default_fan_output_sensitivity; |
| 1508 | u16 fan_output_sensitivity; |
| 1509 | bool ucode_fan_control; |
| 1510 | }; |
| 1511 | |
| 1512 | enum amdgpu_pcie_gen { |
| 1513 | AMDGPU_PCIE_GEN1 = 0, |
| 1514 | AMDGPU_PCIE_GEN2 = 1, |
| 1515 | AMDGPU_PCIE_GEN3 = 2, |
| 1516 | AMDGPU_PCIE_GEN_INVALID = 0xffff |
| 1517 | }; |
| 1518 | |
| 1519 | enum amdgpu_dpm_forced_level { |
| 1520 | AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, |
| 1521 | AMDGPU_DPM_FORCED_LEVEL_LOW = 1, |
| 1522 | AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, |
Eric Huang | f3898ea | 2015-12-11 16:24:34 -0500 | [diff] [blame] | 1523 | AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1524 | }; |
| 1525 | |
| 1526 | struct amdgpu_vce_state { |
| 1527 | /* vce clocks */ |
| 1528 | u32 evclk; |
| 1529 | u32 ecclk; |
| 1530 | /* gpu clocks */ |
| 1531 | u32 sclk; |
| 1532 | u32 mclk; |
| 1533 | u8 clk_idx; |
| 1534 | u8 pstate; |
| 1535 | }; |
| 1536 | |
| 1537 | struct amdgpu_dpm_funcs { |
| 1538 | int (*get_temperature)(struct amdgpu_device *adev); |
| 1539 | int (*pre_set_power_state)(struct amdgpu_device *adev); |
| 1540 | int (*set_power_state)(struct amdgpu_device *adev); |
| 1541 | void (*post_set_power_state)(struct amdgpu_device *adev); |
| 1542 | void (*display_configuration_changed)(struct amdgpu_device *adev); |
| 1543 | u32 (*get_sclk)(struct amdgpu_device *adev, bool low); |
| 1544 | u32 (*get_mclk)(struct amdgpu_device *adev, bool low); |
| 1545 | void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); |
| 1546 | void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); |
| 1547 | int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); |
| 1548 | bool (*vblank_too_short)(struct amdgpu_device *adev); |
| 1549 | void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); |
Sonny Jiang | b7a0776 | 2015-05-28 15:47:53 -0400 | [diff] [blame] | 1550 | void (*powergate_vce)(struct amdgpu_device *adev, bool gate); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1551 | void (*enable_bapm)(struct amdgpu_device *adev, bool enable); |
| 1552 | void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); |
| 1553 | u32 (*get_fan_control_mode)(struct amdgpu_device *adev); |
| 1554 | int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); |
| 1555 | int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); |
| 1556 | }; |
| 1557 | |
| 1558 | struct amdgpu_dpm { |
| 1559 | struct amdgpu_ps *ps; |
| 1560 | /* number of valid power states */ |
| 1561 | int num_ps; |
| 1562 | /* current power state that is active */ |
| 1563 | struct amdgpu_ps *current_ps; |
| 1564 | /* requested power state */ |
| 1565 | struct amdgpu_ps *requested_ps; |
| 1566 | /* boot up power state */ |
| 1567 | struct amdgpu_ps *boot_ps; |
| 1568 | /* default uvd power state */ |
| 1569 | struct amdgpu_ps *uvd_ps; |
| 1570 | /* vce requirements */ |
| 1571 | struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; |
| 1572 | enum amdgpu_vce_level vce_level; |
Rex Zhu | 3a2c788 | 2015-08-25 15:57:43 +0800 | [diff] [blame] | 1573 | enum amd_pm_state_type state; |
| 1574 | enum amd_pm_state_type user_state; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1575 | u32 platform_caps; |
| 1576 | u32 voltage_response_time; |
| 1577 | u32 backbias_response_time; |
| 1578 | void *priv; |
| 1579 | u32 new_active_crtcs; |
| 1580 | int new_active_crtc_count; |
| 1581 | u32 current_active_crtcs; |
| 1582 | int current_active_crtc_count; |
| 1583 | struct amdgpu_dpm_dynamic_state dyn_state; |
| 1584 | struct amdgpu_dpm_fan fan; |
| 1585 | u32 tdp_limit; |
| 1586 | u32 near_tdp_limit; |
| 1587 | u32 near_tdp_limit_adjusted; |
| 1588 | u32 sq_ramping_threshold; |
| 1589 | u32 cac_leakage; |
| 1590 | u16 tdp_od_limit; |
| 1591 | u32 tdp_adjustment; |
| 1592 | u16 load_line_slope; |
| 1593 | bool power_control; |
| 1594 | bool ac_power; |
| 1595 | /* special states active */ |
| 1596 | bool thermal_active; |
| 1597 | bool uvd_active; |
| 1598 | bool vce_active; |
| 1599 | /* thermal handling */ |
| 1600 | struct amdgpu_dpm_thermal thermal; |
| 1601 | /* forced levels */ |
| 1602 | enum amdgpu_dpm_forced_level forced_level; |
| 1603 | }; |
| 1604 | |
| 1605 | struct amdgpu_pm { |
| 1606 | struct mutex mutex; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1607 | u32 current_sclk; |
| 1608 | u32 current_mclk; |
| 1609 | u32 default_sclk; |
| 1610 | u32 default_mclk; |
| 1611 | struct amdgpu_i2c_chan *i2c_bus; |
| 1612 | /* internal thermal controller on rv6xx+ */ |
| 1613 | enum amdgpu_int_thermal_type int_thermal_type; |
| 1614 | struct device *int_hwmon_dev; |
| 1615 | /* fan control parameters */ |
| 1616 | bool no_fan; |
| 1617 | u8 fan_pulses_per_revolution; |
| 1618 | u8 fan_min_rpm; |
| 1619 | u8 fan_max_rpm; |
| 1620 | /* dpm */ |
| 1621 | bool dpm_enabled; |
Alex Deucher | c86f5ebf | 2015-10-23 10:45:14 -0400 | [diff] [blame] | 1622 | bool sysfs_initialized; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1623 | struct amdgpu_dpm dpm; |
| 1624 | const struct firmware *fw; /* SMC firmware */ |
| 1625 | uint32_t fw_version; |
| 1626 | const struct amdgpu_dpm_funcs *funcs; |
Alex Deucher | d0dd7f0 | 2015-11-11 19:45:06 -0500 | [diff] [blame] | 1627 | uint32_t pcie_gen_mask; |
| 1628 | uint32_t pcie_mlw_mask; |
Rex Zhu | 7fb72a1 | 2015-11-19 13:35:30 +0800 | [diff] [blame] | 1629 | struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1630 | }; |
| 1631 | |
Alex Deucher | d0dd7f0 | 2015-11-11 19:45:06 -0500 | [diff] [blame] | 1632 | void amdgpu_get_pcie_info(struct amdgpu_device *adev); |
| 1633 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1634 | /* |
| 1635 | * UVD |
| 1636 | */ |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 1637 | #define AMDGPU_DEFAULT_UVD_HANDLES 10 |
| 1638 | #define AMDGPU_MAX_UVD_HANDLES 40 |
| 1639 | #define AMDGPU_UVD_STACK_SIZE (200*1024) |
| 1640 | #define AMDGPU_UVD_HEAP_SIZE (256*1024) |
| 1641 | #define AMDGPU_UVD_SESSION_SIZE (50*1024) |
| 1642 | #define AMDGPU_UVD_FIRMWARE_OFFSET 256 |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1643 | |
| 1644 | struct amdgpu_uvd { |
| 1645 | struct amdgpu_bo *vcpu_bo; |
| 1646 | void *cpu_addr; |
| 1647 | uint64_t gpu_addr; |
Sonny Jiang | 562e268 | 2016-04-18 16:05:04 -0400 | [diff] [blame] | 1648 | unsigned fw_version; |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 1649 | void *saved_bo; |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 1650 | unsigned max_handles; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1651 | atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; |
| 1652 | struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; |
| 1653 | struct delayed_work idle_work; |
| 1654 | const struct firmware *fw; /* UVD firmware */ |
| 1655 | struct amdgpu_ring ring; |
| 1656 | struct amdgpu_irq_src irq; |
| 1657 | bool address_64_bit; |
Christian König | ead833e | 2016-02-10 14:35:19 +0100 | [diff] [blame] | 1658 | struct amd_sched_entity entity; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1659 | }; |
| 1660 | |
| 1661 | /* |
| 1662 | * VCE |
| 1663 | */ |
| 1664 | #define AMDGPU_MAX_VCE_HANDLES 16 |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1665 | #define AMDGPU_VCE_FIRMWARE_OFFSET 256 |
| 1666 | |
Alex Deucher | 6a58577 | 2015-07-10 14:16:24 -0400 | [diff] [blame] | 1667 | #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) |
| 1668 | #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) |
| 1669 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1670 | struct amdgpu_vce { |
| 1671 | struct amdgpu_bo *vcpu_bo; |
| 1672 | uint64_t gpu_addr; |
| 1673 | unsigned fw_version; |
| 1674 | unsigned fb_version; |
| 1675 | atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; |
| 1676 | struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; |
Christian König | f1689ec | 2015-06-11 20:56:18 +0200 | [diff] [blame] | 1677 | uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1678 | struct delayed_work idle_work; |
| 1679 | const struct firmware *fw; /* VCE firmware */ |
| 1680 | struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; |
| 1681 | struct amdgpu_irq_src irq; |
Alex Deucher | 6a58577 | 2015-07-10 14:16:24 -0400 | [diff] [blame] | 1682 | unsigned harvest_config; |
Christian König | c594989 | 2016-02-10 17:43:00 +0100 | [diff] [blame] | 1683 | struct amd_sched_entity entity; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1684 | }; |
| 1685 | |
| 1686 | /* |
| 1687 | * SDMA |
| 1688 | */ |
Alex Deucher | c113ea1 | 2015-10-08 16:30:37 -0400 | [diff] [blame] | 1689 | struct amdgpu_sdma_instance { |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1690 | /* SDMA firmware */ |
| 1691 | const struct firmware *fw; |
| 1692 | uint32_t fw_version; |
Jammy Zhou | cfa2104 | 2015-08-04 10:50:47 +0800 | [diff] [blame] | 1693 | uint32_t feature_version; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1694 | |
| 1695 | struct amdgpu_ring ring; |
Jammy Zhou | 18111de | 2015-08-31 14:06:39 +0800 | [diff] [blame] | 1696 | bool burst_nop; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1697 | }; |
| 1698 | |
Alex Deucher | c113ea1 | 2015-10-08 16:30:37 -0400 | [diff] [blame] | 1699 | struct amdgpu_sdma { |
| 1700 | struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; |
| 1701 | struct amdgpu_irq_src trap_irq; |
| 1702 | struct amdgpu_irq_src illegal_inst_irq; |
| 1703 | int num_instances; |
| 1704 | }; |
| 1705 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1706 | /* |
| 1707 | * Firmware |
| 1708 | */ |
| 1709 | struct amdgpu_firmware { |
| 1710 | struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; |
| 1711 | bool smu_load; |
| 1712 | struct amdgpu_bo *fw_buf; |
| 1713 | unsigned int fw_size; |
| 1714 | }; |
| 1715 | |
| 1716 | /* |
| 1717 | * Benchmarking |
| 1718 | */ |
| 1719 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); |
| 1720 | |
| 1721 | |
| 1722 | /* |
| 1723 | * Testing |
| 1724 | */ |
| 1725 | void amdgpu_test_moves(struct amdgpu_device *adev); |
| 1726 | void amdgpu_test_ring_sync(struct amdgpu_device *adev, |
| 1727 | struct amdgpu_ring *cpA, |
| 1728 | struct amdgpu_ring *cpB); |
| 1729 | void amdgpu_test_syncing(struct amdgpu_device *adev); |
| 1730 | |
| 1731 | /* |
| 1732 | * MMU Notifier |
| 1733 | */ |
| 1734 | #if defined(CONFIG_MMU_NOTIFIER) |
| 1735 | int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); |
| 1736 | void amdgpu_mn_unregister(struct amdgpu_bo *bo); |
| 1737 | #else |
Harry Wentland | 1d1106b | 2015-07-15 07:10:41 -0400 | [diff] [blame] | 1738 | static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1739 | { |
| 1740 | return -ENODEV; |
| 1741 | } |
Harry Wentland | 1d1106b | 2015-07-15 07:10:41 -0400 | [diff] [blame] | 1742 | static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1743 | #endif |
| 1744 | |
| 1745 | /* |
| 1746 | * Debugfs |
| 1747 | */ |
| 1748 | struct amdgpu_debugfs { |
Nils Wallménius | 06ab683 | 2016-05-02 12:46:15 -0400 | [diff] [blame] | 1749 | const struct drm_info_list *files; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1750 | unsigned num_files; |
| 1751 | }; |
| 1752 | |
| 1753 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, |
Nils Wallménius | 06ab683 | 2016-05-02 12:46:15 -0400 | [diff] [blame] | 1754 | const struct drm_info_list *files, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1755 | unsigned nfiles); |
| 1756 | int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); |
| 1757 | |
| 1758 | #if defined(CONFIG_DEBUG_FS) |
| 1759 | int amdgpu_debugfs_init(struct drm_minor *minor); |
| 1760 | void amdgpu_debugfs_cleanup(struct drm_minor *minor); |
| 1761 | #endif |
| 1762 | |
| 1763 | /* |
| 1764 | * amdgpu smumgr functions |
| 1765 | */ |
| 1766 | struct amdgpu_smumgr_funcs { |
| 1767 | int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); |
| 1768 | int (*request_smu_load_fw)(struct amdgpu_device *adev); |
| 1769 | int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); |
| 1770 | }; |
| 1771 | |
| 1772 | /* |
| 1773 | * amdgpu smumgr |
| 1774 | */ |
| 1775 | struct amdgpu_smumgr { |
| 1776 | struct amdgpu_bo *toc_buf; |
| 1777 | struct amdgpu_bo *smu_buf; |
| 1778 | /* asic priv smu data */ |
| 1779 | void *priv; |
| 1780 | spinlock_t smu_lock; |
| 1781 | /* smumgr functions */ |
| 1782 | const struct amdgpu_smumgr_funcs *smumgr_funcs; |
| 1783 | /* ucode loading complete flag */ |
| 1784 | uint32_t fw_flags; |
| 1785 | }; |
| 1786 | |
| 1787 | /* |
| 1788 | * ASIC specific register table accessible by UMD |
| 1789 | */ |
| 1790 | struct amdgpu_allowed_register_entry { |
| 1791 | uint32_t reg_offset; |
| 1792 | bool untouched; |
| 1793 | bool grbm_indexed; |
| 1794 | }; |
| 1795 | |
| 1796 | struct amdgpu_cu_info { |
| 1797 | uint32_t number; /* total active CU number */ |
| 1798 | uint32_t ao_cu_mask; |
| 1799 | uint32_t bitmap[4][4]; |
| 1800 | }; |
| 1801 | |
| 1802 | |
| 1803 | /* |
| 1804 | * ASIC specific functions. |
| 1805 | */ |
| 1806 | struct amdgpu_asic_funcs { |
| 1807 | bool (*read_disabled_bios)(struct amdgpu_device *adev); |
Alex Deucher | 7946b87 | 2015-11-24 10:14:28 -0500 | [diff] [blame] | 1808 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
| 1809 | u8 *bios, u32 length_bytes); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1810 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
| 1811 | u32 sh_num, u32 reg_offset, u32 *value); |
| 1812 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); |
| 1813 | int (*reset)(struct amdgpu_device *adev); |
| 1814 | /* wait for mc_idle */ |
| 1815 | int (*wait_for_mc_idle)(struct amdgpu_device *adev); |
| 1816 | /* get the reference clock */ |
| 1817 | u32 (*get_xclk)(struct amdgpu_device *adev); |
| 1818 | /* get the gpu clock counter */ |
| 1819 | uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); |
| 1820 | int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); |
| 1821 | /* MM block clocks */ |
| 1822 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); |
| 1823 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); |
| 1824 | }; |
| 1825 | |
| 1826 | /* |
| 1827 | * IOCTL. |
| 1828 | */ |
| 1829 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1830 | struct drm_file *filp); |
| 1831 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, |
| 1832 | struct drm_file *filp); |
| 1833 | |
| 1834 | int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, |
| 1835 | struct drm_file *filp); |
| 1836 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, |
| 1837 | struct drm_file *filp); |
| 1838 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1839 | struct drm_file *filp); |
| 1840 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 1841 | struct drm_file *filp); |
| 1842 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, |
| 1843 | struct drm_file *filp); |
| 1844 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, |
| 1845 | struct drm_file *filp); |
| 1846 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
| 1847 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
| 1848 | |
| 1849 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, |
| 1850 | struct drm_file *filp); |
| 1851 | |
| 1852 | /* VRAM scratch page for HDP bug, default vram page */ |
| 1853 | struct amdgpu_vram_scratch { |
| 1854 | struct amdgpu_bo *robj; |
| 1855 | volatile uint32_t *ptr; |
| 1856 | u64 gpu_addr; |
| 1857 | }; |
| 1858 | |
| 1859 | /* |
| 1860 | * ACPI |
| 1861 | */ |
| 1862 | struct amdgpu_atif_notification_cfg { |
| 1863 | bool enabled; |
| 1864 | int command_code; |
| 1865 | }; |
| 1866 | |
| 1867 | struct amdgpu_atif_notifications { |
| 1868 | bool display_switch; |
| 1869 | bool expansion_mode_change; |
| 1870 | bool thermal_state; |
| 1871 | bool forced_power_state; |
| 1872 | bool system_power_state; |
| 1873 | bool display_conf_change; |
| 1874 | bool px_gfx_switch; |
| 1875 | bool brightness_change; |
| 1876 | bool dgpu_display_event; |
| 1877 | }; |
| 1878 | |
| 1879 | struct amdgpu_atif_functions { |
| 1880 | bool system_params; |
| 1881 | bool sbios_requests; |
| 1882 | bool select_active_disp; |
| 1883 | bool lid_state; |
| 1884 | bool get_tv_standard; |
| 1885 | bool set_tv_standard; |
| 1886 | bool get_panel_expansion_mode; |
| 1887 | bool set_panel_expansion_mode; |
| 1888 | bool temperature_change; |
| 1889 | bool graphics_device_types; |
| 1890 | }; |
| 1891 | |
| 1892 | struct amdgpu_atif { |
| 1893 | struct amdgpu_atif_notifications notifications; |
| 1894 | struct amdgpu_atif_functions functions; |
| 1895 | struct amdgpu_atif_notification_cfg notification_cfg; |
| 1896 | struct amdgpu_encoder *encoder_for_bl; |
| 1897 | }; |
| 1898 | |
| 1899 | struct amdgpu_atcs_functions { |
| 1900 | bool get_ext_state; |
| 1901 | bool pcie_perf_req; |
| 1902 | bool pcie_dev_rdy; |
| 1903 | bool pcie_bus_width; |
| 1904 | }; |
| 1905 | |
| 1906 | struct amdgpu_atcs { |
| 1907 | struct amdgpu_atcs_functions functions; |
| 1908 | }; |
| 1909 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1910 | /* |
Chunming Zhou | d03846a | 2015-07-28 14:20:03 -0400 | [diff] [blame] | 1911 | * CGS |
| 1912 | */ |
Dave Airlie | 110e6f2 | 2016-04-12 13:25:48 +1000 | [diff] [blame] | 1913 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); |
| 1914 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); |
Maruthi Bayyavarapu | a8fe58c | 2015-09-22 17:05:20 -0400 | [diff] [blame] | 1915 | |
| 1916 | |
Alex Deucher | 7e471e6 | 2016-02-01 11:13:04 -0500 | [diff] [blame] | 1917 | /* GPU virtualization */ |
| 1918 | struct amdgpu_virtualization { |
| 1919 | bool supports_sr_iov; |
| 1920 | }; |
| 1921 | |
Maruthi Bayyavarapu | a8fe58c | 2015-09-22 17:05:20 -0400 | [diff] [blame] | 1922 | /* |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1923 | * Core structure, functions and helpers. |
| 1924 | */ |
| 1925 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); |
| 1926 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); |
| 1927 | |
| 1928 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); |
| 1929 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); |
| 1930 | |
Alex Deucher | 8faf0e0 | 2015-07-28 11:50:31 -0400 | [diff] [blame] | 1931 | struct amdgpu_ip_block_status { |
| 1932 | bool valid; |
| 1933 | bool sw; |
| 1934 | bool hw; |
| 1935 | }; |
| 1936 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1937 | struct amdgpu_device { |
| 1938 | struct device *dev; |
| 1939 | struct drm_device *ddev; |
| 1940 | struct pci_dev *pdev; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1941 | |
Maruthi Bayyavarapu | a8fe58c | 2015-09-22 17:05:20 -0400 | [diff] [blame] | 1942 | #ifdef CONFIG_DRM_AMD_ACP |
| 1943 | struct amdgpu_acp acp; |
| 1944 | #endif |
| 1945 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1946 | /* ASIC */ |
Jammy Zhou | 2f7d10b | 2015-07-22 11:29:01 +0800 | [diff] [blame] | 1947 | enum amd_asic_type asic_type; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1948 | uint32_t family; |
| 1949 | uint32_t rev_id; |
| 1950 | uint32_t external_rev_id; |
| 1951 | unsigned long flags; |
| 1952 | int usec_timeout; |
| 1953 | const struct amdgpu_asic_funcs *asic_funcs; |
| 1954 | bool shutdown; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1955 | bool need_dma32; |
| 1956 | bool accel_working; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1957 | struct work_struct reset_work; |
| 1958 | struct notifier_block acpi_nb; |
| 1959 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; |
| 1960 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
| 1961 | unsigned debugfs_count; |
| 1962 | #if defined(CONFIG_DEBUG_FS) |
Tom St Denis | adcec28 | 2016-04-15 13:08:44 -0400 | [diff] [blame] | 1963 | struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1964 | #endif |
| 1965 | struct amdgpu_atif atif; |
| 1966 | struct amdgpu_atcs atcs; |
| 1967 | struct mutex srbm_mutex; |
| 1968 | /* GRBM index mutex. Protects concurrent access to GRBM index */ |
| 1969 | struct mutex grbm_idx_mutex; |
| 1970 | struct dev_pm_domain vga_pm_domain; |
| 1971 | bool have_disp_power_ref; |
| 1972 | |
| 1973 | /* BIOS */ |
| 1974 | uint8_t *bios; |
| 1975 | bool is_atom_bios; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 1976 | struct amdgpu_bo *stollen_vga_memory; |
| 1977 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; |
| 1978 | |
| 1979 | /* Register/doorbell mmio */ |
| 1980 | resource_size_t rmmio_base; |
| 1981 | resource_size_t rmmio_size; |
| 1982 | void __iomem *rmmio; |
| 1983 | /* protects concurrent MM_INDEX/DATA based register access */ |
| 1984 | spinlock_t mmio_idx_lock; |
| 1985 | /* protects concurrent SMC based register access */ |
| 1986 | spinlock_t smc_idx_lock; |
| 1987 | amdgpu_rreg_t smc_rreg; |
| 1988 | amdgpu_wreg_t smc_wreg; |
| 1989 | /* protects concurrent PCIE register access */ |
| 1990 | spinlock_t pcie_idx_lock; |
| 1991 | amdgpu_rreg_t pcie_rreg; |
| 1992 | amdgpu_wreg_t pcie_wreg; |
| 1993 | /* protects concurrent UVD register access */ |
| 1994 | spinlock_t uvd_ctx_idx_lock; |
| 1995 | amdgpu_rreg_t uvd_ctx_rreg; |
| 1996 | amdgpu_wreg_t uvd_ctx_wreg; |
| 1997 | /* protects concurrent DIDT register access */ |
| 1998 | spinlock_t didt_idx_lock; |
| 1999 | amdgpu_rreg_t didt_rreg; |
| 2000 | amdgpu_wreg_t didt_wreg; |
| 2001 | /* protects concurrent ENDPOINT (audio) register access */ |
| 2002 | spinlock_t audio_endpt_idx_lock; |
| 2003 | amdgpu_block_rreg_t audio_endpt_rreg; |
| 2004 | amdgpu_block_wreg_t audio_endpt_wreg; |
| 2005 | void __iomem *rio_mem; |
| 2006 | resource_size_t rio_mem_size; |
| 2007 | struct amdgpu_doorbell doorbell; |
| 2008 | |
| 2009 | /* clock/pll info */ |
| 2010 | struct amdgpu_clock clock; |
| 2011 | |
| 2012 | /* MC */ |
| 2013 | struct amdgpu_mc mc; |
| 2014 | struct amdgpu_gart gart; |
| 2015 | struct amdgpu_dummy_page dummy_page; |
| 2016 | struct amdgpu_vm_manager vm_manager; |
| 2017 | |
| 2018 | /* memory management */ |
| 2019 | struct amdgpu_mman mman; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2020 | struct amdgpu_vram_scratch vram_scratch; |
| 2021 | struct amdgpu_wb wb; |
| 2022 | atomic64_t vram_usage; |
| 2023 | atomic64_t vram_vis_usage; |
| 2024 | atomic64_t gtt_usage; |
| 2025 | atomic64_t num_bytes_moved; |
Marek Olšák | d94aed5 | 2015-05-05 21:13:49 +0200 | [diff] [blame] | 2026 | atomic_t gpu_reset_counter; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2027 | |
| 2028 | /* display */ |
| 2029 | struct amdgpu_mode_info mode_info; |
| 2030 | struct work_struct hotplug_work; |
| 2031 | struct amdgpu_irq_src crtc_irq; |
| 2032 | struct amdgpu_irq_src pageflip_irq; |
| 2033 | struct amdgpu_irq_src hpd_irq; |
| 2034 | |
| 2035 | /* rings */ |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2036 | unsigned fence_context; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2037 | unsigned num_rings; |
| 2038 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; |
| 2039 | bool ib_pool_ready; |
| 2040 | struct amdgpu_sa_manager ring_tmp_bo; |
| 2041 | |
| 2042 | /* interrupts */ |
| 2043 | struct amdgpu_irq irq; |
| 2044 | |
Alex Deucher | 1f7371b | 2015-12-02 17:46:21 -0500 | [diff] [blame] | 2045 | /* powerplay */ |
| 2046 | struct amd_powerplay powerplay; |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2047 | bool pp_enabled; |
Eric Huang | f3898ea | 2015-12-11 16:24:34 -0500 | [diff] [blame] | 2048 | bool pp_force_state_enabled; |
Alex Deucher | 1f7371b | 2015-12-02 17:46:21 -0500 | [diff] [blame] | 2049 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2050 | /* dpm */ |
| 2051 | struct amdgpu_pm pm; |
| 2052 | u32 cg_flags; |
| 2053 | u32 pg_flags; |
| 2054 | |
| 2055 | /* amdgpu smumgr */ |
| 2056 | struct amdgpu_smumgr smu; |
| 2057 | |
| 2058 | /* gfx */ |
| 2059 | struct amdgpu_gfx gfx; |
| 2060 | |
| 2061 | /* sdma */ |
Alex Deucher | c113ea1 | 2015-10-08 16:30:37 -0400 | [diff] [blame] | 2062 | struct amdgpu_sdma sdma; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2063 | |
| 2064 | /* uvd */ |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2065 | struct amdgpu_uvd uvd; |
| 2066 | |
| 2067 | /* vce */ |
| 2068 | struct amdgpu_vce vce; |
| 2069 | |
| 2070 | /* firmwares */ |
| 2071 | struct amdgpu_firmware firmware; |
| 2072 | |
| 2073 | /* GDS */ |
| 2074 | struct amdgpu_gds gds; |
| 2075 | |
| 2076 | const struct amdgpu_ip_block_version *ip_blocks; |
| 2077 | int num_ip_blocks; |
Alex Deucher | 8faf0e0 | 2015-07-28 11:50:31 -0400 | [diff] [blame] | 2078 | struct amdgpu_ip_block_status *ip_block_status; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2079 | struct mutex mn_lock; |
| 2080 | DECLARE_HASHTABLE(mn_hash, 7); |
| 2081 | |
| 2082 | /* tracking pinned memory */ |
| 2083 | u64 vram_pin_size; |
Chunming Zhou | e131b91 | 2016-04-05 10:48:48 +0800 | [diff] [blame] | 2084 | u64 invisible_pin_size; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2085 | u64 gart_pin_size; |
Oded Gabbay | 130e037 | 2015-06-12 21:35:14 +0300 | [diff] [blame] | 2086 | |
| 2087 | /* amdkfd interface */ |
| 2088 | struct kfd_dev *kfd; |
Chunming Zhou | 23ca0e4 | 2015-07-06 13:42:58 +0800 | [diff] [blame] | 2089 | |
Alex Deucher | 7e471e6 | 2016-02-01 11:13:04 -0500 | [diff] [blame] | 2090 | struct amdgpu_virtualization virtualization; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2091 | }; |
| 2092 | |
| 2093 | bool amdgpu_device_is_px(struct drm_device *dev); |
| 2094 | int amdgpu_device_init(struct amdgpu_device *adev, |
| 2095 | struct drm_device *ddev, |
| 2096 | struct pci_dev *pdev, |
| 2097 | uint32_t flags); |
| 2098 | void amdgpu_device_fini(struct amdgpu_device *adev); |
| 2099 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); |
| 2100 | |
| 2101 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
| 2102 | bool always_indirect); |
| 2103 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
| 2104 | bool always_indirect); |
| 2105 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); |
| 2106 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); |
| 2107 | |
| 2108 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); |
| 2109 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); |
| 2110 | |
| 2111 | /* |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2112 | * Registers read & write functions. |
| 2113 | */ |
| 2114 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) |
| 2115 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) |
| 2116 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) |
| 2117 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) |
| 2118 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) |
| 2119 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 2120 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 2121 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) |
| 2122 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) |
| 2123 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) |
| 2124 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) |
| 2125 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) |
| 2126 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) |
| 2127 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) |
| 2128 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) |
| 2129 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) |
| 2130 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) |
| 2131 | #define WREG32_P(reg, val, mask) \ |
| 2132 | do { \ |
| 2133 | uint32_t tmp_ = RREG32(reg); \ |
| 2134 | tmp_ &= (mask); \ |
| 2135 | tmp_ |= ((val) & ~(mask)); \ |
| 2136 | WREG32(reg, tmp_); \ |
| 2137 | } while (0) |
| 2138 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
| 2139 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
| 2140 | #define WREG32_PLL_P(reg, val, mask) \ |
| 2141 | do { \ |
| 2142 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 2143 | tmp_ &= (mask); \ |
| 2144 | tmp_ |= ((val) & ~(mask)); \ |
| 2145 | WREG32_PLL(reg, tmp_); \ |
| 2146 | } while (0) |
| 2147 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) |
| 2148 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) |
| 2149 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) |
| 2150 | |
| 2151 | #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) |
| 2152 | #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) |
| 2153 | |
| 2154 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT |
| 2155 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK |
| 2156 | |
| 2157 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ |
| 2158 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ |
| 2159 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) |
| 2160 | |
| 2161 | #define REG_GET_FIELD(value, reg, field) \ |
| 2162 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) |
| 2163 | |
| 2164 | /* |
| 2165 | * BIOS helpers. |
| 2166 | */ |
| 2167 | #define RBIOS8(i) (adev->bios[i]) |
| 2168 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 2169 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 2170 | |
| 2171 | /* |
| 2172 | * RING helpers. |
| 2173 | */ |
| 2174 | static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) |
| 2175 | { |
| 2176 | if (ring->count_dw <= 0) |
Jammy Zhou | 86c2b79 | 2015-05-13 22:52:42 +0800 | [diff] [blame] | 2177 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2178 | ring->ring[ring->wptr++] = v; |
| 2179 | ring->wptr &= ring->ptr_mask; |
| 2180 | ring->count_dw--; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2181 | } |
| 2182 | |
Alex Deucher | c113ea1 | 2015-10-08 16:30:37 -0400 | [diff] [blame] | 2183 | static inline struct amdgpu_sdma_instance * |
| 2184 | amdgpu_get_sdma_instance(struct amdgpu_ring *ring) |
Jammy Zhou | 4b2f7e2 | 2015-09-01 12:56:17 +0800 | [diff] [blame] | 2185 | { |
| 2186 | struct amdgpu_device *adev = ring->adev; |
| 2187 | int i; |
| 2188 | |
Alex Deucher | c113ea1 | 2015-10-08 16:30:37 -0400 | [diff] [blame] | 2189 | for (i = 0; i < adev->sdma.num_instances; i++) |
| 2190 | if (&adev->sdma.instance[i].ring == ring) |
Jammy Zhou | 4b2f7e2 | 2015-09-01 12:56:17 +0800 | [diff] [blame] | 2191 | break; |
| 2192 | |
| 2193 | if (i < AMDGPU_MAX_SDMA_INSTANCES) |
Alex Deucher | c113ea1 | 2015-10-08 16:30:37 -0400 | [diff] [blame] | 2194 | return &adev->sdma.instance[i]; |
Jammy Zhou | 4b2f7e2 | 2015-09-01 12:56:17 +0800 | [diff] [blame] | 2195 | else |
| 2196 | return NULL; |
| 2197 | } |
| 2198 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2199 | /* |
| 2200 | * ASICs macro. |
| 2201 | */ |
| 2202 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) |
| 2203 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) |
| 2204 | #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) |
| 2205 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) |
| 2206 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) |
| 2207 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) |
| 2208 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) |
| 2209 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) |
Alex Deucher | 7946b87 | 2015-11-24 10:14:28 -0500 | [diff] [blame] | 2210 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2211 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
| 2212 | #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) |
| 2213 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) |
| 2214 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) |
| 2215 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) |
Christian König | b07c9d2 | 2015-11-30 13:26:07 +0100 | [diff] [blame] | 2216 | #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2217 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2218 | #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) |
| 2219 | #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) |
| 2220 | #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2221 | #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) |
| 2222 | #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) |
| 2223 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) |
| 2224 | #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) |
Christian König | b8c7b39 | 2016-03-01 15:42:52 +0100 | [diff] [blame] | 2225 | #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2226 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 2227 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2228 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) |
Christian König | d2edb07 | 2015-05-11 14:10:34 +0200 | [diff] [blame] | 2229 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) |
Chunming Zhou | 11afbde | 2016-03-03 11:38:48 +0800 | [diff] [blame] | 2230 | #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) |
Christian König | 9e5d5309 | 2016-01-31 12:20:55 +0100 | [diff] [blame] | 2231 | #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) |
Monk Liu | 03ccf48 | 2016-01-14 19:07:38 +0800 | [diff] [blame] | 2232 | #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) |
| 2233 | #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2234 | #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) |
| 2235 | #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) |
| 2236 | #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) |
| 2237 | #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) |
| 2238 | #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) |
| 2239 | #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) |
| 2240 | #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) |
| 2241 | #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) |
| 2242 | #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) |
| 2243 | #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) |
| 2244 | #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) |
| 2245 | #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) |
| 2246 | #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) |
| 2247 | #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) |
| 2248 | #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) |
| 2249 | #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) |
| 2250 | #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) |
| 2251 | #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) |
| 2252 | #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) |
Chunming Zhou | c7ae72c | 2015-08-25 17:23:45 +0800 | [diff] [blame] | 2253 | #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) |
Chunming Zhou | 6e7a384 | 2015-08-27 13:46:09 +0800 | [diff] [blame] | 2254 | #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2255 | #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) |
| 2256 | #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) |
| 2257 | #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) |
| 2258 | #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2259 | #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2260 | #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2261 | #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) |
Rex Zhu | 3af76f2 | 2015-10-15 17:23:43 +0800 | [diff] [blame] | 2262 | |
| 2263 | #define amdgpu_dpm_get_temperature(adev) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2264 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2265 | (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2266 | (adev)->pm.funcs->get_temperature((adev))) |
Rex Zhu | 3af76f2 | 2015-10-15 17:23:43 +0800 | [diff] [blame] | 2267 | |
| 2268 | #define amdgpu_dpm_set_fan_control_mode(adev, m) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2269 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2270 | (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2271 | (adev)->pm.funcs->set_fan_control_mode((adev), (m))) |
Rex Zhu | 3af76f2 | 2015-10-15 17:23:43 +0800 | [diff] [blame] | 2272 | |
| 2273 | #define amdgpu_dpm_get_fan_control_mode(adev) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2274 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2275 | (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2276 | (adev)->pm.funcs->get_fan_control_mode((adev))) |
Rex Zhu | 3af76f2 | 2015-10-15 17:23:43 +0800 | [diff] [blame] | 2277 | |
| 2278 | #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2279 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2280 | (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2281 | (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) |
Rex Zhu | 3af76f2 | 2015-10-15 17:23:43 +0800 | [diff] [blame] | 2282 | |
| 2283 | #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2284 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2285 | (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2286 | (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2287 | |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2288 | #define amdgpu_dpm_get_sclk(adev, l) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2289 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2290 | (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2291 | (adev)->pm.funcs->get_sclk((adev), (l))) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2292 | |
| 2293 | #define amdgpu_dpm_get_mclk(adev, l) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2294 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2295 | (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2296 | (adev)->pm.funcs->get_mclk((adev), (l))) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2297 | |
| 2298 | |
| 2299 | #define amdgpu_dpm_force_performance_level(adev, l) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2300 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2301 | (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2302 | (adev)->pm.funcs->force_performance_level((adev), (l))) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2303 | |
| 2304 | #define amdgpu_dpm_powergate_uvd(adev, g) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2305 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2306 | (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2307 | (adev)->pm.funcs->powergate_uvd((adev), (g))) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2308 | |
| 2309 | #define amdgpu_dpm_powergate_vce(adev, g) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2310 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2311 | (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2312 | (adev)->pm.funcs->powergate_vce((adev), (g))) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2313 | |
| 2314 | #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2315 | ((adev)->pp_enabled ? \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2316 | (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ |
Eric Huang | 4b5ece2 | 2016-01-19 14:28:56 -0500 | [diff] [blame] | 2317 | (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2318 | |
| 2319 | #define amdgpu_dpm_get_current_power_state(adev) \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2320 | (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2321 | |
| 2322 | #define amdgpu_dpm_get_performance_level(adev) \ |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2323 | (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2324 | |
Eric Huang | f3898ea | 2015-12-11 16:24:34 -0500 | [diff] [blame] | 2325 | #define amdgpu_dpm_get_pp_num_states(adev, data) \ |
| 2326 | (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) |
| 2327 | |
| 2328 | #define amdgpu_dpm_get_pp_table(adev, table) \ |
| 2329 | (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) |
| 2330 | |
| 2331 | #define amdgpu_dpm_set_pp_table(adev, buf, size) \ |
| 2332 | (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) |
| 2333 | |
| 2334 | #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ |
| 2335 | (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) |
| 2336 | |
| 2337 | #define amdgpu_dpm_force_clock_level(adev, type, level) \ |
| 2338 | (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) |
| 2339 | |
Jammy Zhou | e61710c | 2015-11-10 18:31:08 -0500 | [diff] [blame] | 2340 | #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ |
Rex Zhu | 1b5708f | 2015-11-10 18:25:24 -0500 | [diff] [blame] | 2341 | (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2342 | |
| 2343 | #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) |
| 2344 | |
| 2345 | /* Common functions */ |
| 2346 | int amdgpu_gpu_reset(struct amdgpu_device *adev); |
| 2347 | void amdgpu_pci_config_reset(struct amdgpu_device *adev); |
| 2348 | bool amdgpu_card_posted(struct amdgpu_device *adev); |
| 2349 | void amdgpu_update_display_priority(struct amdgpu_device *adev); |
Chunming Zhou | d5fc5e8 | 2015-07-21 16:52:10 +0800 | [diff] [blame] | 2350 | |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2351 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); |
| 2352 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, |
| 2353 | u32 ip_instance, u32 ring, |
| 2354 | struct amdgpu_ring **out_ring); |
| 2355 | void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); |
| 2356 | bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); |
Christian König | 2f568db | 2016-02-23 12:36:59 +0100 | [diff] [blame] | 2357 | int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2358 | int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
| 2359 | uint32_t flags); |
| 2360 | bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); |
Christian König | cc325d1 | 2016-02-08 11:08:35 +0100 | [diff] [blame] | 2361 | struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); |
Christian König | d700696 | 2016-02-08 10:57:22 +0100 | [diff] [blame] | 2362 | bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, |
| 2363 | unsigned long end); |
Christian König | 2f568db | 2016-02-23 12:36:59 +0100 | [diff] [blame] | 2364 | bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, |
| 2365 | int *last_invalidated); |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2366 | bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); |
| 2367 | uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, |
| 2368 | struct ttm_mem_reg *mem); |
| 2369 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); |
| 2370 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); |
| 2371 | void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); |
| 2372 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, |
| 2373 | const u32 *registers, |
| 2374 | const u32 array_size); |
| 2375 | |
| 2376 | bool amdgpu_device_is_px(struct drm_device *dev); |
| 2377 | /* atpx handler */ |
| 2378 | #if defined(CONFIG_VGA_SWITCHEROO) |
| 2379 | void amdgpu_register_atpx_handler(void); |
| 2380 | void amdgpu_unregister_atpx_handler(void); |
| 2381 | #else |
| 2382 | static inline void amdgpu_register_atpx_handler(void) {} |
| 2383 | static inline void amdgpu_unregister_atpx_handler(void) {} |
| 2384 | #endif |
| 2385 | |
| 2386 | /* |
| 2387 | * KMS |
| 2388 | */ |
| 2389 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; |
Nils Wallménius | f498d9e | 2016-04-10 16:29:59 +0200 | [diff] [blame] | 2390 | extern const int amdgpu_max_kms_ioctl; |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2391 | |
| 2392 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); |
| 2393 | int amdgpu_driver_unload_kms(struct drm_device *dev); |
| 2394 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); |
| 2395 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); |
| 2396 | void amdgpu_driver_postclose_kms(struct drm_device *dev, |
| 2397 | struct drm_file *file_priv); |
| 2398 | void amdgpu_driver_preclose_kms(struct drm_device *dev, |
| 2399 | struct drm_file *file_priv); |
| 2400 | int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); |
| 2401 | int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 2402 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
| 2403 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); |
| 2404 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); |
| 2405 | int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2406 | int *max_error, |
| 2407 | struct timeval *vblank_time, |
| 2408 | unsigned flags); |
| 2409 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
| 2410 | unsigned long arg); |
| 2411 | |
| 2412 | /* |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2413 | * functions used by amdgpu_encoder.c |
| 2414 | */ |
| 2415 | struct amdgpu_afmt_acr { |
| 2416 | u32 clock; |
| 2417 | |
| 2418 | int n_32khz; |
| 2419 | int cts_32khz; |
| 2420 | |
| 2421 | int n_44_1khz; |
| 2422 | int cts_44_1khz; |
| 2423 | |
| 2424 | int n_48khz; |
| 2425 | int cts_48khz; |
| 2426 | |
| 2427 | }; |
| 2428 | |
| 2429 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); |
| 2430 | |
| 2431 | /* amdgpu_acpi.c */ |
| 2432 | #if defined(CONFIG_ACPI) |
| 2433 | int amdgpu_acpi_init(struct amdgpu_device *adev); |
| 2434 | void amdgpu_acpi_fini(struct amdgpu_device *adev); |
| 2435 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); |
| 2436 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, |
| 2437 | u8 perf_req, bool advertise); |
| 2438 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); |
| 2439 | #else |
| 2440 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } |
| 2441 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } |
| 2442 | #endif |
| 2443 | |
| 2444 | struct amdgpu_bo_va_mapping * |
| 2445 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, |
| 2446 | uint64_t addr, struct amdgpu_bo **bo); |
| 2447 | |
| 2448 | #include "amdgpu_object.h" |
Alex Deucher | 97b2e20 | 2015-04-20 16:51:00 -0400 | [diff] [blame] | 2449 | #endif |