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gerrit-public.fairphone.software / kernel / msm-4.9 / cac6f86ed8b30a1525384f62acfef215273e328c / . / arch / arm64 / boot / dts / qcom / sdm670.dtsi
blob: 401004a2b727217c078433fd4d55798bcb95898e [file] [log] [blame]
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]1/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "skeleton64.dtsi"
14#include <dt-bindings/interrupt-controller/arm-gic.h>
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]15#include <dt-bindings/clock/qcom,gcc-sdm845.h>
16#include <dt-bindings/clock/qcom,camcc-sdm845.h>
17#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
18#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
19#include <dt-bindings/clock/qcom,videocc-sdm845.h>
20#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
21#include <dt-bindings/clock/qcom,rpmh.h>
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]22#include <dt-bindings/soc/qcom,tcs-mbox.h>
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]23#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]24#include <dt-bindings/clock/qcom,aop-qmp.h>
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]25
Santosh Mardi903c95d2017-09-25 10:36:29 +0530[diff] [blame]26#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
27
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]28/ {
29 model = "Qualcomm Technologies, Inc. SDM670";
30 compatible = "qcom,sdm670";
31 qcom,msm-id = <336 0x0>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]32 interrupt-parent = <&pdc>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]33
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]34 aliases {
35 ufshc1 = &ufshc_mem; /* Embedded UFS slot */
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]36 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]37 sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
Mukesh Kumar Savaliya7b272542017-07-10 19:35:29 +0530[diff] [blame]38 serial0 = &qupv3_se12_2uart;
39 spi0 = &qupv3_se8_spi;
40 i2c0 = &qupv3_se10_i2c;
41 i2c1 = &qupv3_se3_i2c;
42 hsuart0 = &qupv3_se6_4uart;
43 };
44
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]45 chosen {
Pavankumar Kondeti2c218d72017-10-03 19:31:31 +0530[diff] [blame]46 bootargs = "rcupdate.rcu_expedited=1 core_ctl_disable_cpumask=6-7";
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]47 };
48
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
53 CPU0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,armv8";
56 reg = <0x0 0x0>;
57 enable-method = "psci";
58 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]59 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]60 cpu-release-addr = <0x0 0x90000000>;
61 next-level-cache = <&L2_0>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]62 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]63 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]64 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]65 L2_0: l2-cache {
66 compatible = "arm,arch-cache";
67 cache-size = <0x20000>;
68 cache-level = <2>;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "arm,arch-cache";
72 cache-size = <0x100000>;
73 cache-level = <3>;
74 };
75 };
76 L1_I_0: l1-icache {
77 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]78 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]79 };
80 L1_D_0: l1-dcache {
81 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]82 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]83 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]84 L1_TLB_0: l1-tlb {
85 qcom,dump-size = <0x3000>;
86 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]87 };
88
89 CPU1: cpu@100 {
90 device_type = "cpu";
91 compatible = "arm,armv8";
92 reg = <0x0 0x100>;
93 enable-method = "psci";
94 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]95 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]96 cpu-release-addr = <0x0 0x90000000>;
97 next-level-cache = <&L2_100>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]98 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]99 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]100 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]101 L2_100: l2-cache {
102 compatible = "arm,arch-cache";
103 cache-size = <0x20000>;
104 cache-level = <2>;
105 next-level-cache = <&L3_0>;
106 };
107 L1_I_100: l1-icache {
108 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]109 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]110 };
111 L1_D_100: l1-dcache {
112 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]113 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]114 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]115 L1_TLB_100: l1-tlb {
116 qcom,dump-size = <0x3000>;
117 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]118 };
119
120 CPU2: cpu@200 {
121 device_type = "cpu";
122 compatible = "arm,armv8";
123 reg = <0x0 0x200>;
124 enable-method = "psci";
125 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]126 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]127 cpu-release-addr = <0x0 0x90000000>;
128 next-level-cache = <&L2_200>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]129 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]130 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]131 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]132 L2_200: l2-cache {
133 compatible = "arm,arch-cache";
134 cache-size = <0x20000>;
135 cache-level = <2>;
136 next-level-cache = <&L3_0>;
137 };
138 L1_I_200: l1-icache {
139 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]140 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]141 };
142 L1_D_200: l1-dcache {
143 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]144 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]145 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]146 L1_TLB_200: l1-tlb {
147 qcom,dump-size = <0x3000>;
148 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]149 };
150
151 CPU3: cpu@300 {
152 device_type = "cpu";
153 compatible = "arm,armv8";
154 reg = <0x0 0x300>;
155 enable-method = "psci";
156 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]157 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]158 cpu-release-addr = <0x0 0x90000000>;
159 next-level-cache = <&L2_300>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]160 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]161 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]162 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]163 L2_300: l2-cache {
164 compatible = "arm,arch-cache";
165 cache-size = <0x20000>;
166 cache-level = <2>;
167 next-level-cache = <&L3_0>;
168 };
169 L1_I_300: l1-icache {
170 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]171 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]172 };
173 L1_D_300: l1-dcache {
174 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]175 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]176 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]177 L1_TLB_300: l1-tlb {
178 qcom,dump-size = <0x3000>;
179 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]180 };
181
182 CPU4: cpu@400 {
183 device_type = "cpu";
184 compatible = "arm,armv8";
185 reg = <0x0 0x400>;
186 enable-method = "psci";
187 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]188 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]189 cpu-release-addr = <0x0 0x90000000>;
190 next-level-cache = <&L2_400>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]191 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]192 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]193 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]194 L2_400: l2-cache {
195 compatible = "arm,arch-cache";
196 cache-size = <0x20000>;
197 cache-level = <2>;
198 next-level-cache = <&L3_0>;
199 };
200 L1_I_400: l1-icache {
201 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]202 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]203 };
204 L1_D_400: l1-dcache {
205 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]206 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]207 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]208 L1_TLB_400: l1-tlb {
209 qcom,dump-size = <0x3000>;
210 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]211 };
212
213 CPU5: cpu@500 {
214 device_type = "cpu";
215 compatible = "arm,armv8";
216 reg = <0x0 0x500>;
217 enable-method = "psci";
218 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]219 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]220 cpu-release-addr = <0x0 0x90000000>;
221 next-level-cache = <&L2_500>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]222 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]223 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]224 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]225 L2_500: l2-cache {
226 compatible = "arm,arch-cache";
227 cache-size = <0x20000>;
228 cache-level = <2>;
229 next-level-cache = <&L3_0>;
230 };
231 L1_I_500: l1-icache {
232 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]233 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]234 };
235 L1_D_500: l1-dcache {
236 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]237 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]238 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]239 L1_TLB_500: l1-tlb {
240 qcom,dump-size = <0x3000>;
241 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]242 };
243
244 CPU6: cpu@600 {
245 device_type = "cpu";
246 compatible = "arm,armv8";
247 reg = <0x0 0x600>;
248 enable-method = "psci";
249 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]250 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]251 cpu-release-addr = <0x0 0x90000000>;
252 next-level-cache = <&L2_600>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]253 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]254 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]255 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]256 L2_600: l2-cache {
257 compatible = "arm,arch-cache";
258 cache-size = <0x40000>;
259 cache-level = <2>;
260 next-level-cache = <&L3_0>;
261 };
262 L1_I_600: l1-icache {
263 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]264 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]265 };
266 L1_D_600: l1-dcache {
267 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]268 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]269 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]270 L1_TLB_600: l1-tlb {
271 qcom,dump-size = <0x3c000>;
272 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]273 };
274
275 CPU7: cpu@700 {
276 device_type = "cpu";
277 compatible = "arm,armv8";
278 reg = <0x0 0x700>;
279 enable-method = "psci";
280 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]281 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]282 cpu-release-addr = <0x0 0x90000000>;
283 next-level-cache = <&L2_700>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]284 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]285 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]286 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]287 L2_700: l2-cache {
288 compatible = "arm,arch-cache";
289 cache-size = <0x40000>;
290 cache-level = <2>;
291 next-level-cache = <&L3_0>;
292 };
293 L1_I_700: l1-icache {
294 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]295 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]296 };
297 L1_D_700: l1-dcache {
298 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]299 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]300 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]301 L1_TLB_700: l1-tlb {
302 qcom,dump-size = <0x3c000>;
303 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]304 };
305
306 cpu-map {
307 cluster0 {
308 core0 {
309 cpu = <&CPU0>;
310 };
311
312 core1 {
313 cpu = <&CPU1>;
314 };
315
316 core2 {
317 cpu = <&CPU2>;
318 };
319
320 core3 {
321 cpu = <&CPU3>;
322 };
323
324 core4 {
325 cpu = <&CPU4>;
326 };
327
328 core5 {
329 cpu = <&CPU5>;
330 };
331 };
332 cluster1 {
333 core0 {
334 cpu = <&CPU6>;
335 };
336
337 core1 {
338 cpu = <&CPU7>;
339 };
340 };
341 };
342 };
343
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]344 energy_costs: energy-costs {
345 compatible = "sched-energy";
346
347 CPU_COST_0: core-cost0 {
348 busy-cost-data = <
349 300000 14
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]350 576000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]351 748800 31
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]352 998400 46
353 1209600 57
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]354 1324800 84
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]355 1516800 96
356 1612800 114
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]357 1708800 139
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]358 >;
359 idle-cost-data = <
360 12 10 8 6
361 >;
362 };
363 CPU_COST_1: core-cost1 {
364 busy-cost-data = <
365 300000 256
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]366 652800 307
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]367 825600 332
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]368 979200 382
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]369 1132800 408
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]370 1363200 448
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]371 1536000 586
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]372 1747200 641
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]373 1843200 659
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]374 1996800 696
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]375 2054400 876
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]376 2169600 900
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]377 2208000 924
378 2361600 948
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]379 2400000 1170
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]380 2457600 1200
381 2515200 1300
382 2611200 1400
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]383 >;
384 idle-cost-data = <
385 100 80 60 40
386 >;
387 };
388 CLUSTER_COST_0: cluster-cost0 {
389 busy-cost-data = <
390 300000 5
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]391 576000 7
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]392 748800 8
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]393 998400 9
394 1209600 10
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]395 1324800 13
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]396 1516800 15
397 1612800 16
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]398 1708800 19
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]399 >;
400 idle-cost-data = <
401 4 3 2 1
402 >;
403 };
404 CLUSTER_COST_1: cluster-cost1 {
405 busy-cost-data = <
406 300000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]407 652800 30
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]408 825600 33
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]409 979200 38
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]410 1132800 40
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]411 1363200 44
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]412 1536000 58
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]413 1747200 64
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]414 1843200 65
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]415 1996800 69
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]416 2054400 87
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]417 2169600 90
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]418 2208000 92
419 2361600 94
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]420 2400000 117
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]421 2457600 120
422 2515200 130
423 2611200 140
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]424 >;
425 idle-cost-data = <
426 4 3 2 1
427 >;
428 };
429 };
430
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]431 psci {
432 compatible = "arm,psci-1.0";
433 method = "smc";
434 };
435
436 soc: soc { };
437
Imran Khanb1066fa2017-08-01 17:20:22 +0530[diff] [blame]438 vendor: vendor {
439 #address-cells = <1>;
440 #size-cells = <1>;
441 ranges = <0 0 0 0xffffffff>;
442 compatible = "simple-bus";
443 };
444
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]445 firmware: firmware {
446 android {
447 compatible = "android,firmware";
448
monisingfb2cb762017-12-19 14:40:49 +0530[diff] [blame]449 vbmeta {
450 compatible = "android,vbmeta";
451 parts = "vbmeta,boot,system,vendor,dtbo";
452 };
453
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]454 fstab {
455 compatible = "android,fstab";
456 vendor {
457 compatible = "android,vendor";
458 dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
459 type = "ext4";
460 mnt_flags = "ro,barrier=1,discard";
AnilKumar Chimata0d646ab2017-10-25 22:09:03 +0530[diff] [blame]461 fsmgr_flags = "wait,slotselect,avb";
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]462 };
463 };
464 };
465 };
466
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]467 reserved-memory {
468 #address-cells = <2>;
469 #size-cells = <2>;
470 ranges;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]471
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]472 hyp_region: hyp_region@85700000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]473 compatible = "removed-dma-pool";
474 no-map;
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]475 reg = <0 0x85700000 0 0x600000>;
476 };
477
478 xbl_region: xbl_region@85e00000 {
479 compatible = "removed-dma-pool";
480 no-map;
481 reg = <0 0x85e00000 0 0x100000>;
482 };
483
484 removed_region: removed_region@85fc0000 {
485 compatible = "removed-dma-pool";
486 no-map;
487 reg = <0 0x85fc0000 0 0x2f40000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]488 };
489
490 pil_camera_mem: camera_region@8ab00000 {
491 compatible = "removed-dma-pool";
492 no-map;
493 reg = <0 0x8ab00000 0 0x500000>;
494 };
495
496 pil_modem_mem: modem_region@8b000000 {
497 compatible = "removed-dma-pool";
498 no-map;
499 reg = <0 0x8b000000 0 0x7e00000>;
500 };
501
502 pil_video_mem: pil_video_region@92e00000 {
503 compatible = "removed-dma-pool";
504 no-map;
505 reg = <0 0x92e00000 0 0x500000>;
506 };
507
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]508 wlan_msa_mem: wlan_msa_region@93300000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]509 compatible = "removed-dma-pool";
510 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]511 reg = <0 0x93300000 0 0x100000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]512 };
513
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]514 pil_cdsp_mem: cdsp_regions@93400000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]515 compatible = "removed-dma-pool";
516 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]517 reg = <0 0x93400000 0 0x800000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]518 };
519
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]520 pil_mba_mem: pil_mba_region@0x93c00000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]521 compatible = "removed-dma-pool";
522 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]523 reg = <0 0x93c00000 0 0x200000>;
524 };
525
526 pil_adsp_mem: pil_adsp_region@93e00000 {
527 compatible = "removed-dma-pool";
528 no-map;
529 reg = <0 0x93e00000 0 0x1e00000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]530 };
531
Prakash Gupta7c571ef2018-01-19 17:57:47 +0530[diff] [blame]532 pil_ipa_fw_mem: ips_fw_region@0x95c00000 {
533 compatible = "removed-dma-pool";
534 no-map;
535 reg = <0 0x95c00000 0 0x10000>;
536 };
537
538 pil_ipa_gsi_mem: ipa_gsi_region@0x95c10000 {
539 compatible = "removed-dma-pool";
540 no-map;
541 reg = <0 0x95c10000 0 0x5000>;
542 };
543
544 pil_gpu_mem: gpu_region@0x95c15000 {
545 compatible = "removed-dma-pool";
546 no-map;
547 reg = <0 0x95c15000 0 0x2000>;
548 };
549
550 qseecom_mem: qseecom_region@0x9e400000 {
551 compatible = "shared-dma-pool";
552 no-map;
553 reg = <0 0x9e400000 0 0x1400000>;
554 };
555
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]556 adsp_mem: adsp_region {
557 compatible = "shared-dma-pool";
558 alloc-ranges = <0 0x00000000 0 0xffffffff>;
559 reusable;
560 alignment = <0 0x400000>;
561 size = <0 0xc00000>;
562 };
563
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]564 qseecom_ta_mem: qseecom_ta_region {
565 compatible = "shared-dma-pool";
566 alloc-ranges = <0 0x00000000 0 0xffffffff>;
567 reusable;
568 alignment = <0 0x400000>;
569 size = <0 0x1000000>;
570 };
571
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]572 sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
573 compatible = "shared-dma-pool";
574 alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
575 reusable;
576 alignment = <0 0x400000>;
577 size = <0 0x800000>;
578 };
579
580 secure_display_memory: secure_display_region {
581 compatible = "shared-dma-pool";
582 alloc-ranges = <0 0x00000000 0 0xffffffff>;
583 reusable;
584 alignment = <0 0x400000>;
585 size = <0 0x5c00000>;
586 };
587
Jayant Shekhare3191272018-01-30 16:49:08 +0530[diff] [blame]588 cont_splash_memory: cont_splash_region@9c000000 {
589 reg = <0x0 0x9c000000 0x0 0x02400000>;
Jayant Shekharb59d1692017-11-10 14:21:40 +0530[diff] [blame]590 label = "cont_splash_region";
591 };
592
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]593 dump_mem: mem_dump_region {
594 compatible = "shared-dma-pool";
595 reusable;
596 size = <0 0x2400000>;
597 };
598
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]599 /* global autoconfigured region for contiguous allocations */
600 linux,cma {
601 compatible = "shared-dma-pool";
602 alloc-ranges = <0 0x00000000 0 0xffffffff>;
603 reusable;
604 alignment = <0 0x400000>;
605 size = <0 0x2000000>;
606 linux,cma-default;
607 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]608 };
609};
610
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]611#include "sdm670-ion.dtsi"
612
Dhoat Harpal92d63dea2017-06-06 21:20:26 +0530[diff] [blame]613#include "sdm670-smp2p.dtsi"
614
c_mtharuce962e42017-12-05 22:41:17 +0530[diff] [blame]615#include "msm-rdbg.dtsi"
616
Mukesh Kumar Savaliya065ca482017-06-06 14:44:45 +0530[diff] [blame]617#include "sdm670-qupv3.dtsi"
618
Saranya Chiduraf49fee12017-06-19 10:52:37 +0530[diff] [blame]619#include "sdm670-coresight.dtsi"
Manikanta Kanamarlapudid4abc602017-08-28 19:23:41 +0530[diff] [blame]620
621#include "sdm670-vidc.dtsi"
622
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]623#include "sdm670-sde-pll.dtsi"
624
625#include "sdm670-sde.dtsi"
626
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]627&soc {
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges = <0 0 0 0xffffffff>;
631 compatible = "simple-bus";
632
Saranya Chidura0e8b4262017-10-04 13:06:26 +0530[diff] [blame]633 jtag_mm0: jtagmm@7040000 {
634 compatible = "qcom,jtagv8-mm";
635 reg = <0x7040000 0x1000>;
636 reg-names = "etm-base";
637
638 clocks = <&clock_aop QDSS_CLK>;
639 clock-names = "core_clk";
640
641 qcom,coresight-jtagmm-cpu = <&CPU0>;
642 };
643
644 jtag_mm1: jtagmm@7140000 {
645 compatible = "qcom,jtagv8-mm";
646 reg = <0x7140000 0x1000>;
647 reg-names = "etm-base";
648
649 clocks = <&clock_aop QDSS_CLK>;
650 clock-names = "core_clk";
651
652 qom,coresight-jtagmm-cpu = <&CPU1>;
653 };
654
655 jtag_mm2: jtagmm@7240000 {
656 compatible = "qcom,jtagv8-mm";
657 reg = <0x7240000 0x1000>;
658 reg-names = "etm-base";
659
660 clocks = <&clock_aop QDSS_CLK>;
661 clock-names = "core_clk";
662
663 qcom,coresight-jtagmm-cpu = <&CPU2>;
664 };
665
666 jtag_mm3: jtagmm@7340000 {
667 compatible = "qcom,jtagv8-mm";
668 reg = <0x7340000 0x1000>;
669 reg-names = "etm-base";
670
671 clocks = <&clock_aop QDSS_CLK>;
672 clock-names = "core_clk";
673
674 qcom,coresight-jtagmm-cpu = <&CPU3>;
675 };
676
677 jtag_mm4: jtagmm@7440000 {
678 compatible = "qcom,jtagv8-mm";
679 reg = <0x7440000 0x1000>;
680 reg-names = "etm-base";
681
682 clocks = <&clock_aop QDSS_CLK>;
683 clock-names = "core_clk";
684
685 qcom,coresight-jtagmm-cpu = <&CPU4>;
686 };
687
688 jtag_mm5: jtagmm@7540000 {
689 compatible = "qcom,jtagv8-mm";
690 reg = <0x7540000 0x1000>;
691 reg-names = "etm-base";
692
693 clocks = <&clock_aop QDSS_CLK>;
694 clock-names = "core_clk";
695
696 qcom,coresight-jtagmm-cpu = <&CPU5>;
697 };
698
699 jtag_mm6: jtagmm@7640000 {
700 compatible = "qcom,jtagv8-mm";
701 reg = <0x7640000 0x1000>;
702 reg-names = "etm-base";
703
704 clocks = <&clock_aop QDSS_CLK>;
705 clock-names = "core_clk";
706
707 qcom,coresight-jtagmm-cpu = <&CPU6>;
708 };
709
710 jtag_mm7: jtagmm@7740000 {
711 compatible = "qcom,jtagv8-mm";
712 reg = <0x7740000 0x1000>;
713 reg-names = "etm-base";
714
715 clocks = <&clock_aop QDSS_CLK>;
716 clock-names = "core_clk";
717
718 qcom,coresight-jtagmm-cpu = <&CPU7>;
719 };
720
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]721 intc: interrupt-controller@17a00000 {
722 compatible = "arm,gic-v3";
723 #interrupt-cells = <3>;
724 interrupt-controller;
725 #redistributor-regions = <1>;
726 redistributor-stride = <0x0 0x20000>;
727 reg = <0x17a00000 0x10000>, /* GICD */
728 <0x17a60000 0x100000>; /* GICR * 8 */
729 interrupts = <1 9 4>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]730 interrupt-parent = <&intc>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]731 };
732
Raghavendra Kakarla04f032162017-12-08 19:11:54 +0530[diff] [blame]733 pdc: interrupt-controller@b220000{
734 compatible = "qcom,pdc-sdm670";
735 reg = <0xb220000 0x400>;
736 #interrupt-cells = <3>;
737 interrupt-parent = <&intc>;
738 interrupt-controller;
739 };
740
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]741 timer {
742 compatible = "arm,armv8-timer";
743 interrupts = <1 1 0xf08>,
744 <1 2 0xf08>,
745 <1 3 0xf08>,
746 <1 0 0xf08>;
747 clock-frequency = <19200000>;
748 };
749
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]750 qcom,memshare {
751 compatible = "qcom,memshare";
752
753 qcom,client_1 {
754 compatible = "qcom,memshare-peripheral";
755 qcom,peripheral-size = <0x0>;
756 qcom,client-id = <0>;
757 qcom,allocate-boot-time;
758 label = "modem";
759 };
760
761 qcom,client_2 {
762 compatible = "qcom,memshare-peripheral";
763 qcom,peripheral-size = <0x0>;
764 qcom,client-id = <2>;
765 label = "modem";
766 };
767
768 mem_client_3_size: qcom,client_3 {
769 compatible = "qcom,memshare-peripheral";
770 qcom,peripheral-size = <0x500000>;
771 qcom,client-id = <1>;
Manoj Prabhu B991f9222018-01-03 19:13:56 +0530[diff] [blame]772 qcom,allocate-boot-time;
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]773 label = "modem";
774 };
775 };
776
Lakshmi Sunkarabbd69892017-06-09 13:17:10 +0530[diff] [blame]777 qcom,sps {
778 compatible = "qcom,msm_sps_4k";
779 qcom,pipe-attr-ee;
780 };
781
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]782 qcom_cedev: qcedev@1de0000 {
783 compatible = "qcom,qcedev";
784 reg = <0x1de0000 0x20000>,
785 <0x1dc4000 0x24000>;
786 reg-names = "crypto-base","crypto-bam-base";
787 interrupts = <0 272 0>;
788 qcom,bam-pipe-pair = <3>;
789 qcom,ce-hw-instance = <0>;
790 qcom,ce-device = <0>;
791 qcom,ce-hw-shared;
792 qcom,bam-ee = <0>;
793 qcom,msm-bus,name = "qcedev-noc";
794 qcom,msm-bus,num-cases = <2>;
795 qcom,msm-bus,num-paths = <1>;
796 qcom,msm-bus,vectors-KBps =
797 <125 512 0 0>,
798 <125 512 393600 393600>;
799 clock-names = "core_clk_src", "core_clk",
800 "iface_clk", "bus_clk";
801 clocks = <&clock_gcc GCC_CE1_CLK>,
802 <&clock_gcc GCC_CE1_CLK>,
803 <&clock_gcc GCC_CE1_AHB_CLK>,
804 <&clock_gcc GCC_CE1_AXI_CLK>;
805 qcom,ce-opp-freq = <171430000>;
806 qcom,request-bw-before-clk;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]807 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]808 iommus = <&apps_smmu 0x706 0x1>,
809 <&apps_smmu 0x716 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]810 };
811
Tatenda Chipeperekwa8a77c8a2018-01-30 14:50:11 -0800[diff] [blame]812 qcom_msmhdcp: qcom,msm_hdcp {
813 compatible = "qcom,msm-hdcp";
814 };
815
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]816 qcom_crypto: qcrypto@1de0000 {
817 compatible = "qcom,qcrypto";
818 reg = <0x1de0000 0x20000>,
819 <0x1dc4000 0x24000>;
820 reg-names = "crypto-base","crypto-bam-base";
821 interrupts = <0 272 0>;
822 qcom,bam-pipe-pair = <2>;
823 qcom,ce-hw-instance = <0>;
824 qcom,ce-device = <0>;
825 qcom,bam-ee = <0>;
826 qcom,ce-hw-shared;
827 qcom,clk-mgmt-sus-res;
828 qcom,msm-bus,name = "qcrypto-noc";
829 qcom,msm-bus,num-cases = <2>;
830 qcom,msm-bus,num-paths = <1>;
831 qcom,msm-bus,vectors-KBps =
832 <125 512 0 0>,
833 <125 512 393600 393600>;
834 clock-names = "core_clk_src", "core_clk",
835 "iface_clk", "bus_clk";
836 clocks = <&clock_gcc GCC_CE1_CLK>,
837 <&clock_gcc GCC_CE1_CLK>,
838 <&clock_gcc GCC_CE1_AHB_CLK>,
839 <&clock_gcc GCC_CE1_AXI_CLK>;
840 qcom,ce-opp-freq = <171430000>;
841 qcom,request-bw-before-clk;
842 qcom,use-sw-aes-cbc-ecb-ctr-algo;
843 qcom,use-sw-aes-xts-algo;
844 qcom,use-sw-aes-ccm-algo;
845 qcom,use-sw-aead-algo;
846 qcom,use-sw-ahash-algo;
847 qcom,use-sw-hmac-algo;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]848 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]849 iommus = <&apps_smmu 0x704 0x1>,
850 <&apps_smmu 0x714 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]851 };
852
Abir Ghoshb849ab22017-09-19 13:03:11 +0530[diff] [blame]853 qcom,qbt1000 {
854 compatible = "qcom,qbt1000";
855 clock-names = "core", "iface";
856 clock-frequency = <25000000>;
857 qcom,ipc-gpio = <&tlmm 121 0>;
858 qcom,finger-detect-gpio = <&tlmm 122 0>;
859 };
860
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]861 qcom_seecom: qseecom@86d00000 {
862 compatible = "qcom,qseecom";
863 reg = <0x86d00000 0x2200000>;
864 reg-names = "secapp-region";
865 qcom,hlos-num-ce-hw-instances = <1>;
866 qcom,hlos-ce-hw-instance = <0>;
867 qcom,qsee-ce-hw-instance = <0>;
868 qcom,disk-encrypt-pipe-pair = <2>;
869 qcom,support-fde;
870 qcom,no-clock-support;
Neeraj Soni7c4254c2017-11-15 11:13:14 +0530[diff] [blame]871 qcom,fde-key-size;
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]872 qcom,appsbl-qseecom-support;
873 qcom,msm-bus,name = "qseecom-noc";
874 qcom,msm-bus,num-cases = <4>;
875 qcom,msm-bus,num-paths = <1>;
876 qcom,msm-bus,vectors-KBps =
877 <125 512 0 0>,
878 <125 512 200000 400000>,
879 <125 512 300000 800000>,
880 <125 512 400000 1000000>;
881 clock-names = "core_clk_src", "core_clk",
882 "iface_clk", "bus_clk";
883 clocks = <&clock_gcc GCC_CE1_CLK>,
884 <&clock_gcc GCC_CE1_CLK>,
885 <&clock_gcc GCC_CE1_AHB_CLK>,
886 <&clock_gcc GCC_CE1_AXI_CLK>;
887 qcom,ce-opp-freq = <171430000>;
888 qcom,qsee-reentrancy-support = <2>;
889 };
890
mohamed sunfeer732f7572017-09-19 19:51:11 +0530[diff] [blame]891 qcom_tzlog: tz-log@146bf720 {
892 compatible = "qcom,tz-log";
893 reg = <0x146bf720 0x3000>;
894 qcom,hyplog-enabled;
895 hyplog-address-offset = <0x410>;
896 hyplog-size-offset = <0x414>;
897 };
898
mohamed sunfeer2228b242017-09-19 19:10:08 +0530[diff] [blame]899 qcom_rng: qrng@793000{
900 compatible = "qcom,msm-rng";
901 reg = <0x793000 0x1000>;
902 qcom,msm-rng-iface-clk;
903 qcom,no-qrng-config;
904 qcom,msm-bus,name = "msm-rng-noc";
905 qcom,msm-bus,num-cases = <2>;
906 qcom,msm-bus,num-paths = <1>;
907 qcom,msm-bus,vectors-KBps =
908 <1 618 0 0>, /* No vote */
909 <1 618 0 800>; /* 100 KHz */
910 clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
911 clock-names = "iface_clk";
912 };
913
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]914 thermal_zones: thermal-zones {};
Rama Krishna Phani Aa3c0e782017-07-17 20:09:15 +0530[diff] [blame]915
916 tsens0: tsens@c222000 {
917 compatible = "qcom,tsens24xx";
918 reg = <0xc222000 0x4>,
919 <0xc263000 0x1ff>;
920 reg-names = "tsens_srot_physical",
921 "tsens_tm_physical";
922 interrupts = <0 506 0>, <0 508 0>;
923 interrupt-names = "tsens-upper-lower", "tsens-critical";
924 #thermal-sensor-cells = <1>;
925 };
926
927 tsens1: tsens@c223000 {
928 compatible = "qcom,tsens24xx";
929 reg = <0xc223000 0x4>,
930 <0xc265000 0x1ff>;
931 reg-names = "tsens_srot_physical",
932 "tsens_tm_physical";
933 interrupts = <0 507 0>, <0 509 0>;
934 interrupt-names = "tsens-upper-lower", "tsens-critical";
935 #thermal-sensor-cells = <1>;
936 };
937
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]938 timer@0x17c90000{
939 #address-cells = <1>;
940 #size-cells = <1>;
941 ranges;
942 compatible = "arm,armv7-timer-mem";
943 reg = <0x17c90000 0x1000>;
944 clock-frequency = <19200000>;
945
946 frame@0x17ca0000 {
947 frame-number = <0>;
948 interrupts = <0 7 0x4>,
949 <0 6 0x4>;
950 reg = <0x17ca0000 0x1000>,
951 <0x17cb0000 0x1000>;
952 };
953
954 frame@17cc0000 {
955 frame-number = <1>;
956 interrupts = <0 8 0x4>;
957 reg = <0x17cc0000 0x1000>;
958 status = "disabled";
959 };
960
961 frame@17cd0000 {
962 frame-number = <2>;
963 interrupts = <0 9 0x4>;
964 reg = <0x17cd0000 0x1000>;
965 status = "disabled";
966 };
967
968 frame@17ce0000 {
969 frame-number = <3>;
970 interrupts = <0 10 0x4>;
971 reg = <0x17ce0000 0x1000>;
972 status = "disabled";
973 };
974
975 frame@17cf0000 {
976 frame-number = <4>;
977 interrupts = <0 11 0x4>;
978 reg = <0x17cf0000 0x1000>;
979 status = "disabled";
980 };
981
982 frame@17d00000 {
983 frame-number = <5>;
984 interrupts = <0 12 0x4>;
985 reg = <0x17d00000 0x1000>;
986 status = "disabled";
987 };
988
989 frame@17d10000 {
990 frame-number = <6>;
991 interrupts = <0 13 0x4>;
992 reg = <0x17d10000 0x1000>;
993 status = "disabled";
994 };
995 };
996
997 restart@10ac000 {
998 compatible = "qcom,pshold";
999 reg = <0xC264000 0x4>,
1000 <0x1fd3000 0x4>;
1001 reg-names = "pshold-base", "tcsr-boot-misc-detect";
1002 };
1003
Maulik Shah6bf7d5d2017-07-27 09:48:42 +0530[diff] [blame]1004 aop-msg-client {
1005 compatible = "qcom,debugfs-qmp-client";
1006 mboxes = <&qmp_aop 0>;
1007 mbox-names = "aop";
1008 };
1009
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1010 clock_rpmh: qcom,rpmhclk {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1011 compatible = "qcom,rpmh-clk-sdm670";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1012 #clock-cells = <1>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1013 mboxes = <&apps_rsc 0>;
1014 mbox-names = "apps";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1015 };
1016
1017 clock_gcc: qcom,gcc@100000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1018 compatible = "qcom,gcc-sdm670", "syscon";
1019 reg = <0x100000 0x1f0000>;
1020 reg-names = "cc_base";
1021 vdd_cx-supply = <&pm660l_s3_level>;
1022 vdd_cx_ao-supply = <&pm660l_s3_level_ao>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1023 #clock-cells = <1>;
1024 #reset-cells = <1>;
1025 };
1026
1027 clock_videocc: qcom,videocc@ab00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1028 compatible = "qcom,video_cc-sdm670", "syscon";
1029 reg = <0xab00000 0x10000>;
1030 reg-names = "cc_base";
1031 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1032 #clock-cells = <1>;
1033 #reset-cells = <1>;
1034 };
1035
1036 clock_camcc: qcom,camcc@ad00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1037 compatible = "qcom,cam_cc-sdm670", "syscon";
1038 reg = <0xad00000 0x10000>;
1039 reg-names = "cc_base";
1040 vdd_cx-supply = <&pm660l_s3_level>;
1041 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1042 #clock-cells = <1>;
1043 #reset-cells = <1>;
Alok Pandey499587b2018-02-08 22:14:59 +0530[diff] [blame]1044 qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>;
1045 qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>;
1046 qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>;
1047 qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>;
1048 qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>;
1049 qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>;
1050 qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>;
1051 qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>;
1052 qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>;
1053 qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>;
1054 qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>;
1055 qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>;
1056 qcom,cam_cc_ipe_1_clk_src-opp-handle = <&cam_ipe1>;
1057 qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1058 };
1059
1060 clock_dispcc: qcom,dispcc@af00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1061 compatible = "qcom,dispcc-sdm670", "syscon";
1062 reg = <0xaf00000 0x10000>;
1063 reg-names = "cc_base";
1064 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1065 #clock-cells = <1>;
1066 #reset-cells = <1>;
1067 };
1068
1069 clock_gpucc: qcom,gpucc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1070 compatible = "qcom,gpucc-sdm670", "syscon";
1071 reg = <0x5090000 0x9000>;
1072 reg-names = "cc_base";
1073 vdd_cx-supply = <&pm660l_s3_level>;
1074 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1075 qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1076 #clock-cells = <1>;
1077 #reset-cells = <1>;
1078 };
1079
1080 clock_gfx: qcom,gfxcc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1081 compatible = "qcom,gfxcc-sdm670";
1082 reg = <0x5090000 0x9000>;
1083 reg-names = "cc_base";
1084 vdd_gfx-supply = <&pm660l_s2_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1085 qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1086 #clock-cells = <1>;
1087 #reset-cells = <1>;
1088 };
1089
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1090 cpucc_debug: syscon@17970018 {
1091 compatible = "syscon";
1092 reg = <0x17970018 0x4>;
1093 };
1094
1095 clock_debug: qcom,cc-debug {
1096 compatible = "qcom,debugcc-sdm845";
1097 qcom,cc-count = <5>;
1098 qcom,gcc = <&clock_gcc>;
1099 qcom,videocc = <&clock_videocc>;
1100 qcom,camcc = <&clock_camcc>;
1101 qcom,dispcc = <&clock_dispcc>;
1102 qcom,gpucc = <&clock_gpucc>;
1103 qcom,cpucc = <&cpucc_debug>;
1104 clock-names = "xo_clk_src";
1105 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1106 #clock-cells = <1>;
1107 };
1108
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1109 clock_cpucc: qcom,cpucc@0x17d41000 {
1110 compatible = "qcom,clk-cpu-osm-sdm670";
1111 reg = <0x17d41000 0x1400>,
1112 <0x17d43000 0x1400>,
David Collins1e048402017-11-29 15:43:09 -0800[diff] [blame]1113 <0x17d45800 0x1400>;
1114 reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
Deepak Katragadda02617bd2017-11-10 16:03:43 -0800[diff] [blame]1115 vdd_l3_mx_ao-supply = <&pm660l_s1_level_ao>;
1116 vdd_pwrcl_mx_ao-supply = <&pm660l_s1_level_ao>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1117
Odelu Kukatla86c179e2017-12-12 19:10:23 +0530[diff] [blame]1118 qcom,mx-turbo-freq = <1440000000 1708000000 3300000001>;
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]1119 l3-devs = <&l3_cpu0 &l3_cpu6 &l3_cdsp>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1120
1121 clock-names = "xo_ao";
1122 clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1123 #clock-cells = <1>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1124 };
1125
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1126 clock_aop: qcom,aopclk {
Odelu Kukatla80f617f2017-09-15 19:30:25 +0530[diff] [blame]1127 compatible = "qcom,aop-qmp-clk-v1";
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1128 #clock-cells = <1>;
1129 mboxes = <&qmp_aop 0>;
1130 mbox-names = "qdss_clk";
1131 };
1132
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1133 slim_aud: slim@62dc0000 {
1134 cell-index = <1>;
1135 compatible = "qcom,slim-ngd";
1136 reg = <0x62dc0000 0x2c000>,
1137 <0x62d84000 0x2a000>;
1138 reg-names = "slimbus_physical", "slimbus_bam_physical";
1139 interrupts = <0 163 0>, <0 164 0>;
1140 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
1141 qcom,apps-ch-pipes = <0x780000>;
1142 qcom,ea-pc = <0x290>;
1143 status = "disabled";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1144 qcom,iommu-s1-bypass;
1145
1146 iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1147 compatible = "qcom,iommu-slim-ctrl-cb";
1148 iommus = <&apps_smmu 0x1826 0x0>,
1149 <&apps_smmu 0x182d 0x0>,
1150 <&apps_smmu 0x182e 0x1>,
1151 <&apps_smmu 0x1830 0x1>;
1152 };
1153
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1154 };
1155
1156 slim_qca: slim@62e40000 {
1157 cell-index = <3>;
1158 compatible = "qcom,slim-ngd";
1159 reg = <0x62e40000 0x2c000>,
1160 <0x62e04000 0x20000>;
1161 reg-names = "slimbus_physical", "slimbus_bam_physical";
1162 interrupts = <0 291 0>, <0 292 0>;
1163 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1164 status = "ok";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1165 qcom,iommu-s1-bypass;
1166
1167 iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1168 compatible = "qcom,iommu-slim-ctrl-cb";
1169 iommus = <&apps_smmu 0x1833 0x0>;
1170 };
1171
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1172 /* Slimbus Slave DT for WCN3990 */
1173 btfmslim_codec: wcn3990 {
1174 compatible = "qcom,btfmslim_slave";
1175 elemental-addr = [00 01 20 02 17 02];
1176 qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
1177 qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
1178 };
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1179 };
1180
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1181 wdog: qcom,wdt@17980000{
1182 compatible = "qcom,msm-watchdog";
1183 reg = <0x17980000 0x1000>;
1184 reg-names = "wdt-base";
Lingutla Chandrasekhar9fb9ba92017-10-08 21:59:19 +0530[diff] [blame]1185 interrupts = <0 0 0>, <0 1 0>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1186 qcom,bark-time = <11000>;
Neeraj Upadhyaydbc184d2017-12-07 16:05:39 +0530[diff] [blame]1187 qcom,pet-time = <9360>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1188 qcom,ipi-ping;
1189 qcom,wakeup-enable;
1190 };
1191
1192 qcom,msm-rtb {
1193 compatible = "qcom,msm-rtb";
1194 qcom,rtb-size = <0x100000>;
1195 };
1196
Lingutla Chandrasekhar4d78d722017-11-10 16:03:44 +0530[diff] [blame]1197 qcom,mpm2-sleep-counter@c221000 {
1198 compatible = "qcom,mpm2-sleep-counter";
1199 reg = <0x0c221000 0x1000>;
1200 clock-frequency = <32768>;
1201 };
1202
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1203 qcom,msm-imem@146bf000 {
1204 compatible = "qcom,msm-imem";
1205 reg = <0x146bf000 0x1000>;
1206 ranges = <0x0 0x146bf000 0x1000>;
1207 #address-cells = <1>;
1208 #size-cells = <1>;
1209
1210 mem_dump_table@10 {
1211 compatible = "qcom,msm-imem-mem_dump_table";
1212 reg = <0x10 8>;
1213 };
1214
Lingutla Chandrasekharfa5c13f2017-09-25 11:01:58 +0530[diff] [blame]1215 dload_type@1c {
1216 compatible = "qcom,msm-imem-dload-type";
1217 reg = <0x1c 0x4>;
1218 };
1219
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1220 restart_reason@65c {
1221 compatible = "qcom,msm-imem-restart_reason";
1222 reg = <0x65c 4>;
1223 };
1224
1225 pil@94c {
1226 compatible = "qcom,msm-imem-pil";
1227 reg = <0x94c 200>;
1228 };
1229
1230 kaslr_offset@6d0 {
1231 compatible = "qcom,msm-imem-kaslr_offset";
1232 reg = <0x6d0 12>;
1233 };
Lingutla Chandrasekhar3c51f0b2017-09-12 14:21:21 +0530[diff] [blame]1234
1235 boot_stats@6b0 {
1236 compatible = "qcom,msm-imem-boot_stats";
1237 reg = <0x6b0 0x20>;
1238 };
1239
1240 diag_dload@c8 {
1241 compatible = "qcom,msm-imem-diag-dload";
1242 reg = <0xc8 0xc8>;
1243 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1244 };
1245
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1246 gpi_dma0: qcom,gpi-dma@0x800000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1247 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1248 compatible = "qcom,gpi-dma";
1249 reg = <0x800000 0x60000>;
1250 reg-names = "gpi-top";
1251 interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
1252 <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
1253 <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
1254 <0 256 0>;
1255 qcom,max-num-gpii = <13>;
1256 qcom,gpii-mask = <0xfa>;
1257 qcom,ev-factor = <2>;
1258 iommus = <&apps_smmu 0x0016 0x0>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1259 qcom,smmu-cfg = <0x1>;
1260 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1261 status = "ok";
1262 };
1263
1264 gpi_dma1: qcom,gpi-dma@0xa00000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1265 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1266 compatible = "qcom,gpi-dma";
1267 reg = <0xa00000 0x60000>;
1268 reg-names = "gpi-top";
1269 interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>,
1270 <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>,
1271 <0 295 0>, <0 296 0>, <0 297 0>, <0 298 0>,
1272 <0 299 0>;
1273 qcom,max-num-gpii = <13>;
1274 qcom,gpii-mask = <0xfa>;
1275 qcom,ev-factor = <2>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1276 qcom,smmu-cfg = <0x1>;
1277 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1278 iommus = <&apps_smmu 0x06d6 0x0>;
1279 status = "ok";
1280 };
1281
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1282 cpuss_dump {
1283 compatible = "qcom,cpuss-dump";
1284 qcom,l1_i_cache0 {
1285 qcom,dump-node = <&L1_I_0>;
1286 qcom,dump-id = <0x60>;
1287 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1288 qcom,l1_i_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1289 qcom,dump-node = <&L1_I_100>;
1290 qcom,dump-id = <0x61>;
1291 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1292 qcom,l1_i_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1293 qcom,dump-node = <&L1_I_200>;
1294 qcom,dump-id = <0x62>;
1295 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1296 qcom,l1_i_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1297 qcom,dump-node = <&L1_I_300>;
1298 qcom,dump-id = <0x63>;
1299 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1300 qcom,l1_i_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1301 qcom,dump-node = <&L1_I_400>;
1302 qcom,dump-id = <0x64>;
1303 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1304 qcom,l1_i_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1305 qcom,dump-node = <&L1_I_500>;
1306 qcom,dump-id = <0x65>;
1307 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1308 qcom,l1_i_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1309 qcom,dump-node = <&L1_I_600>;
1310 qcom,dump-id = <0x66>;
1311 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1312 qcom,l1_i_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1313 qcom,dump-node = <&L1_I_700>;
1314 qcom,dump-id = <0x67>;
1315 };
1316 qcom,l1_d_cache0 {
1317 qcom,dump-node = <&L1_D_0>;
1318 qcom,dump-id = <0x80>;
1319 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1320 qcom,l1_d_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1321 qcom,dump-node = <&L1_D_100>;
1322 qcom,dump-id = <0x81>;
1323 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1324 qcom,l1_d_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1325 qcom,dump-node = <&L1_D_200>;
1326 qcom,dump-id = <0x82>;
1327 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1328 qcom,l1_d_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1329 qcom,dump-node = <&L1_D_300>;
1330 qcom,dump-id = <0x83>;
1331 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1332 qcom,l1_d_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1333 qcom,dump-node = <&L1_D_400>;
1334 qcom,dump-id = <0x84>;
1335 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1336 qcom,l1_d_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1337 qcom,dump-node = <&L1_D_500>;
1338 qcom,dump-id = <0x85>;
1339 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1340 qcom,l1_d_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1341 qcom,dump-node = <&L1_D_600>;
1342 qcom,dump-id = <0x86>;
1343 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1344 qcom,l1_d_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1345 qcom,dump-node = <&L1_D_700>;
1346 qcom,dump-id = <0x87>;
1347 };
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1348 qcom,llcc1_d_cache {
1349 qcom,dump-node = <&LLCC_1>;
1350 qcom,dump-id = <0x140>;
1351 };
1352 qcom,llcc2_d_cache {
1353 qcom,dump-node = <&LLCC_2>;
1354 qcom,dump-id = <0x141>;
1355 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1356 qcom,l1_tlb_dump0 {
1357 qcom,dump-node = <&L1_TLB_0>;
1358 qcom,dump-id = <0x20>;
1359 };
1360 qcom,l1_tlb_dump100 {
1361 qcom,dump-node = <&L1_TLB_100>;
1362 qcom,dump-id = <0x21>;
1363 };
1364 qcom,l1_tlb_dump200 {
1365 qcom,dump-node = <&L1_TLB_200>;
1366 qcom,dump-id = <0x22>;
1367 };
1368 qcom,l1_tlb_dump300 {
1369 qcom,dump-node = <&L1_TLB_300>;
1370 qcom,dump-id = <0x23>;
1371 };
1372 qcom,l1_tlb_dump400 {
1373 qcom,dump-node = <&L1_TLB_400>;
1374 qcom,dump-id = <0x24>;
1375 };
1376 qcom,l1_tlb_dump500 {
1377 qcom,dump-node = <&L1_TLB_500>;
1378 qcom,dump-id = <0x25>;
1379 };
1380 qcom,l1_tlb_dump600 {
1381 qcom,dump-node = <&L1_TLB_600>;
1382 qcom,dump-id = <0x26>;
1383 };
1384 qcom,l1_tlb_dump700 {
1385 qcom,dump-node = <&L1_TLB_700>;
1386 qcom,dump-id = <0x27>;
1387 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1388 };
1389
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1390 mem_dump {
1391 compatible = "qcom,mem-dump";
1392 memory-region = <&dump_mem>;
1393
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1394 rpmh {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1395 qcom,dump-size = <0x2000000>;
1396 qcom,dump-id = <0xec>;
1397 };
1398
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1399 rpm_sw {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1400 qcom,dump-size = <0x28000>;
1401 qcom,dump-id = <0xea>;
1402 };
1403
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1404 pmic {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1405 qcom,dump-size = <0x10000>;
1406 qcom,dump-id = <0xe4>;
1407 };
1408
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1409 tmc_etf {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1410 qcom,dump-size = <0x10000>;
1411 qcom,dump-id = <0xf0>;
1412 };
1413
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1414 tmc_etfswao {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1415 qcom,dump-size = <0x8400>;
1416 qcom,dump-id = <0xf1>;
1417 };
1418
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1419 tmc_etr_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1420 qcom,dump-size = <0x1000>;
1421 qcom,dump-id = <0x100>;
1422 };
1423
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1424 tmc_etf_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1425 qcom,dump-size = <0x1000>;
1426 qcom,dump-id = <0x101>;
1427 };
1428
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1429 etfswao_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1430 qcom,dump-size = <0x1000>;
1431 qcom,dump-id = <0x102>;
1432 };
1433
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1434 misc_data {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1435 qcom,dump-size = <0x1000>;
1436 qcom,dump-id = <0xe8>;
1437 };
1438
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1439 power_regs {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1440 qcom,dump-size = <0x100000>;
1441 qcom,dump-id = <0xed>;
1442 };
1443 };
1444
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1445 kryo3xx-erp {
1446 compatible = "arm,arm64-kryo3xx-cpu-erp";
1447 interrupts = <1 6 4>,
1448 <1 7 4>,
1449 <0 34 4>,
1450 <0 35 4>;
1451
1452 interrupt-names = "l1-l2-faultirq",
1453 "l1-l2-errirq",
1454 "l3-scu-errirq",
1455 "l3-scu-faultirq";
1456 };
1457
Dhoat Harpala24cb2c2017-06-06 20:39:54 +0530[diff] [blame]1458 qcom,ipc-spinlock@1f40000 {
1459 compatible = "qcom,ipc-spinlock-sfpb";
1460 reg = <0x1f40000 0x8000>;
1461 qcom,num-locks = <8>;
1462 };
1463
Dhoat Harpaldd9bfaf2017-06-06 20:43:16 +0530[diff] [blame]1464 qcom,smem@86000000 {
1465 compatible = "qcom,smem";
1466 reg = <0x86000000 0x200000>,
1467 <0x17911008 0x4>,
1468 <0x778000 0x7000>,
1469 <0x1fd4000 0x8>;
1470 reg-names = "smem", "irq-reg-base", "aux-mem1",
1471 "smem_targ_info_reg";
1472 qcom,mpu-enabled;
1473 };
1474
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1475 qmp_aop: qcom,qmp-aop@c300000 {
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1476 compatible = "qcom,qmp-mbox";
1477 label = "aop";
1478 reg = <0xc300000 0x100000>,
1479 <0x1799000c 0x4>;
1480 reg-names = "msgram", "irq-reg-base";
1481 qcom,irq-mask = <0x1>;
1482 interrupts = <0 389 1>;
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1483 priority = <0>;
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1484 mbox-desc-offset = <0x0>;
1485 #mbox-cells = <1>;
1486 };
1487
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1488 qcom,glink-smem-native-xprt-modem@86000000 {
1489 compatible = "qcom,glink-smem-native-xprt";
1490 reg = <0x86000000 0x200000>,
1491 <0x1799000c 0x4>;
1492 reg-names = "smem", "irq-reg-base";
1493 qcom,irq-mask = <0x1000>;
1494 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1495 label = "mpss";
1496 };
1497
1498 qcom,glink-smem-native-xprt-adsp@86000000 {
1499 compatible = "qcom,glink-smem-native-xprt";
1500 reg = <0x86000000 0x200000>,
1501 <0x1799000c 0x4>;
1502 reg-names = "smem", "irq-reg-base";
Dhoat Harpal3adebbe2017-07-06 15:59:13 +0530[diff] [blame]1503 qcom,irq-mask = <0x1000000>;
1504 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1505 label = "lpass";
1506 qcom,qos-config = <&glink_qos_adsp>;
1507 qcom,ramp-time = <0xaf>;
1508 };
1509
1510 glink_qos_adsp: qcom,glink-qos-config-adsp {
1511 compatible = "qcom,glink-qos-config";
1512 qcom,flow-info = <0x3c 0x0>,
1513 <0x3c 0x0>,
1514 <0x3c 0x0>,
1515 <0x3c 0x0>;
1516 qcom,mtu-size = <0x800>;
1517 qcom,tput-stats-cycle = <0xa>;
1518 };
1519
1520 glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
1521 compatible = "qcom,glink-spi-xprt";
1522 label = "wdsp";
1523 qcom,remote-fifo-config = <&glink_fifo_wdsp>;
1524 qcom,qos-config = <&glink_qos_wdsp>;
1525 qcom,ramp-time = <0x10>,
1526 <0x20>,
1527 <0x30>,
1528 <0x40>;
1529 };
1530
1531 glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
1532 compatible = "qcom,glink-fifo-config";
1533 qcom,out-read-idx-reg = <0x12000>;
1534 qcom,out-write-idx-reg = <0x12004>;
1535 qcom,in-read-idx-reg = <0x1200C>;
1536 qcom,in-write-idx-reg = <0x12010>;
1537 };
1538
1539 glink_qos_wdsp: qcom,glink-qos-config-wdsp {
1540 compatible = "qcom,glink-qos-config";
1541 qcom,flow-info = <0x80 0x0>,
1542 <0x70 0x1>,
1543 <0x60 0x2>,
1544 <0x50 0x3>;
1545 qcom,mtu-size = <0x800>;
1546 qcom,tput-stats-cycle = <0xa>;
1547 };
1548
1549 qcom,glink-smem-native-xprt-cdsp@86000000 {
1550 compatible = "qcom,glink-smem-native-xprt";
1551 reg = <0x86000000 0x200000>,
1552 <0x1799000c 0x4>;
1553 reg-names = "smem", "irq-reg-base";
1554 qcom,irq-mask = <0x10>;
1555 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1556 label = "cdsp";
1557 };
1558
Dhoat Harpal9cb73cc2017-06-06 20:58:14 +0530[diff] [blame]1559 glink_mpss: qcom,glink-ssr-modem {
1560 compatible = "qcom,glink_ssr";
1561 label = "modem";
1562 qcom,edge = "mpss";
1563 qcom,notify-edges = <&glink_lpass>, <&glink_cdsp>;
1564 qcom,xprt = "smem";
1565 };
1566
1567 glink_lpass: qcom,glink-ssr-adsp {
1568 compatible = "qcom,glink_ssr";
1569 label = "adsp";
1570 qcom,edge = "lpass";
1571 qcom,notify-edges = <&glink_mpss>, <&glink_cdsp>;
1572 qcom,xprt = "smem";
1573 };
1574
1575 glink_cdsp: qcom,glink-ssr-cdsp {
1576 compatible = "qcom,glink_ssr";
1577 label = "cdsp";
1578 qcom,edge = "cdsp";
1579 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>;
1580 qcom,xprt = "smem";
1581 };
1582
Dhoat Harpal22dafa92017-06-06 21:03:34 +0530[diff] [blame]1583 qcom,ipc_router {
1584 compatible = "qcom,ipc_router";
1585 qcom,node-id = <1>;
1586 };
1587
1588 qcom,ipc_router_modem_xprt {
1589 compatible = "qcom,ipc_router_glink_xprt";
1590 qcom,ch-name = "IPCRTR";
1591 qcom,xprt-remote = "mpss";
1592 qcom,glink-xprt = "smem";
1593 qcom,xprt-linkid = <1>;
1594 qcom,xprt-version = <1>;
1595 qcom,fragmented-data;
1596 };
1597
1598 qcom,ipc_router_q6_xprt {
1599 compatible = "qcom,ipc_router_glink_xprt";
1600 qcom,ch-name = "IPCRTR";
1601 qcom,xprt-remote = "lpass";
1602 qcom,glink-xprt = "smem";
1603 qcom,xprt-linkid = <1>;
1604 qcom,xprt-version = <1>;
1605 qcom,fragmented-data;
1606 };
1607
1608 qcom,ipc_router_cdsp_xprt {
1609 compatible = "qcom,ipc_router_glink_xprt";
1610 qcom,ch-name = "IPCRTR";
1611 qcom,xprt-remote = "cdsp";
1612 qcom,glink-xprt = "smem";
1613 qcom,xprt-linkid = <1>;
1614 qcom,xprt-version = <1>;
1615 qcom,fragmented-data;
1616 };
1617
Dhoat Harpal11d34482017-06-06 21:00:14 +0530[diff] [blame]1618 qcom,glink_pkt {
1619 compatible = "qcom,glinkpkt";
1620
1621 qcom,glinkpkt-at-mdm0 {
1622 qcom,glinkpkt-transport = "smem";
1623 qcom,glinkpkt-edge = "mpss";
1624 qcom,glinkpkt-ch-name = "DS";
1625 qcom,glinkpkt-dev-name = "at_mdm0";
1626 };
1627
1628 qcom,glinkpkt-loopback_cntl {
1629 qcom,glinkpkt-transport = "lloop";
1630 qcom,glinkpkt-edge = "local";
1631 qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
1632 qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
1633 };
1634
1635 qcom,glinkpkt-loopback_data {
1636 qcom,glinkpkt-transport = "lloop";
1637 qcom,glinkpkt-edge = "local";
1638 qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
1639 qcom,glinkpkt-dev-name = "glink_pkt_loopback";
1640 };
1641
1642 qcom,glinkpkt-apr-apps2 {
1643 qcom,glinkpkt-transport = "smem";
1644 qcom,glinkpkt-edge = "adsp";
1645 qcom,glinkpkt-ch-name = "apr_apps2";
1646 qcom,glinkpkt-dev-name = "apr_apps2";
1647 };
1648
1649 qcom,glinkpkt-data40-cntl {
1650 qcom,glinkpkt-transport = "smem";
1651 qcom,glinkpkt-edge = "mpss";
1652 qcom,glinkpkt-ch-name = "DATA40_CNTL";
1653 qcom,glinkpkt-dev-name = "smdcntl8";
1654 };
1655
1656 qcom,glinkpkt-data1 {
1657 qcom,glinkpkt-transport = "smem";
1658 qcom,glinkpkt-edge = "mpss";
1659 qcom,glinkpkt-ch-name = "DATA1";
1660 qcom,glinkpkt-dev-name = "smd7";
1661 };
1662
1663 qcom,glinkpkt-data4 {
1664 qcom,glinkpkt-transport = "smem";
1665 qcom,glinkpkt-edge = "mpss";
1666 qcom,glinkpkt-ch-name = "DATA4";
1667 qcom,glinkpkt-dev-name = "smd8";
1668 };
1669
1670 qcom,glinkpkt-data11 {
1671 qcom,glinkpkt-transport = "smem";
1672 qcom,glinkpkt-edge = "mpss";
1673 qcom,glinkpkt-ch-name = "DATA11";
1674 qcom,glinkpkt-dev-name = "smd11";
1675 };
1676 };
1677
Gaurav Kohlid1131902018-02-21 13:21:25 +0530[diff] [blame]1678 qcom,chd_silver {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1679 compatible = "qcom,core-hang-detect";
1680 label = "silver";
1681 qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058
1682 0x17e30058 0x17e40058 0x17e50058>;
1683 qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060
1684 0x17e30060 0x17e40060 0x17e50060>;
1685 };
1686
1687 qcom,chd_gold {
1688 compatible = "qcom,core-hang-detect";
1689 label = "gold";
1690 qcom,threshold-arr = <0x17e60058 0x17e70058>;
1691 qcom,config-arr = <0x17e60060 0x17e70060>;
1692 };
1693
1694 qcom,ghd {
1695 compatible = "qcom,gladiator-hang-detect-v2";
1696 qcom,threshold-arr = <0x1799041c 0x17990420>;
1697 qcom,config-reg = <0x17990434>;
1698 };
1699
1700 qcom,msm-gladiator-v3@17900000 {
1701 compatible = "qcom,msm-gladiator-v3";
1702 reg = <0x17900000 0xd080>;
1703 reg-names = "gladiator_base";
1704 interrupts = <0 17 0>;
1705 };
1706
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1707 eud: qcom,msm-eud@88e0000 {
1708 compatible = "qcom,msm-eud";
1709 interrupt-names = "eud_irq";
1710 interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
1711 reg = <0x88e0000 0x2000>;
1712 reg-names = "eud_base";
Lingutla Chandrasekhar5422daf2017-10-26 11:27:32 +0530[diff] [blame]1713 clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1714 clock-names = "cfg_ahb_clk";
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1715 };
1716
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1717 qcom,llcc@1100000 {
1718 compatible = "qcom,llcc-core", "syscon", "simple-mfd";
1719 reg = <0x1100000 0x250000>;
1720 reg-names = "llcc_base";
1721 qcom,llcc-banks-off = <0x0 0x80000 >;
1722 qcom,llcc-broadcast-off = <0x200000>;
1723
1724 llcc: qcom,sdm670-llcc {
1725 compatible = "qcom,sdm670-llcc";
1726 #cache-cells = <1>;
1727 max-slices = <32>;
1728 qcom,dump-size = <0x80000>;
1729 };
1730
Sankaran Nampoothiri0c5dac02017-11-06 11:53:52 +0530[diff] [blame]1731 qcom,llcc-perfmon {
1732 compatible = "qcom,llcc-perfmon";
1733 };
1734
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1735 qcom,llcc-erp {
1736 compatible = "qcom,llcc-erp";
1737 interrupt-names = "ecc_irq";
1738 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1739 };
1740
1741 qcom,llcc-amon {
1742 compatible = "qcom,llcc-amon";
1743 };
1744
1745 LLCC_1: llcc_1_dcache {
1746 qcom,dump-size = <0xd8000>;
1747 };
1748
1749 LLCC_2: llcc_2_dcache {
1750 qcom,dump-size = <0xd8000>;
1751 };
1752 };
1753
Maulik Shah210773d2017-06-15 09:49:12 +0530[diff] [blame]1754 cmd_db: qcom,cmd-db@c3f000c {
1755 compatible = "qcom,cmd-db";
1756 reg = <0xc3f000c 0x8>;
1757 };
1758
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]1759 apps_rsc: mailbox@179e0000 {
1760 compatible = "qcom,tcs-drv";
1761 label = "apps_rsc";
1762 reg = <0x179e0000 0x100>, <0x179e0d00 0x3000>;
1763 interrupts = <0 5 0>;
1764 #mbox-cells = <1>;
1765 qcom,drv-id = <2>;
1766 qcom,tcs-config = <ACTIVE_TCS 2>,
1767 <SLEEP_TCS 3>,
1768 <WAKE_TCS 3>,
1769 <CONTROL_TCS 1>;
1770 };
1771
Maulik Shahda3941f2017-06-15 09:41:38 +0530[diff] [blame]1772 disp_rsc: mailbox@af20000 {
1773 compatible = "qcom,tcs-drv";
1774 label = "display_rsc";
1775 reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
1776 interrupts = <0 129 0>;
1777 #mbox-cells = <1>;
1778 qcom,drv-id = <0>;
1779 qcom,tcs-config = <SLEEP_TCS 1>,
1780 <WAKE_TCS 1>,
1781 <ACTIVE_TCS 0>,
1782 <CONTROL_TCS 1>;
1783 };
1784
Maulik Shah0dd203f2017-06-15 09:44:59 +0530[diff] [blame]1785 system_pm {
1786 compatible = "qcom,system-pm";
1787 mboxes = <&apps_rsc 0>;
1788 };
1789
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1790 dcc: dcc_v2@10a2000 {
1791 compatible = "qcom,dcc_v2";
1792 reg = <0x10a2000 0x1000>,
1793 <0x10ae000 0x2000>;
1794 reg-names = "dcc-base", "dcc-ram-base";
Saranya Chidurac0a161c2017-08-28 13:06:10 +0530[diff] [blame]1795
1796 dcc-ram-offset = <0x6000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1797 };
1798
Tirupathi Reddy9ae4c892017-06-09 12:30:31 +0530[diff] [blame]1799 spmi_bus: qcom,spmi@c440000 {
1800 compatible = "qcom,spmi-pmic-arb";
1801 reg = <0xc440000 0x1100>,
1802 <0xc600000 0x2000000>,
1803 <0xe600000 0x100000>,
1804 <0xe700000 0xa0000>,
1805 <0xc40a000 0x26000>;
1806 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1807 interrupt-names = "periph_irq";
1808 interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
1809 qcom,ee = <0>;
1810 qcom,channel = <0>;
1811 #address-cells = <2>;
1812 #size-cells = <0>;
1813 interrupt-controller;
1814 #interrupt-cells = <4>;
1815 cell-index = <0>;
1816 };
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1817
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1818 ufs_ice: ufsice@1d90000 {
1819 compatible = "qcom,ice";
1820 reg = <0x1d90000 0x8000>;
1821 qcom,enable-ice-clk;
1822 clock-names = "ufs_core_clk", "bus_clk",
1823 "iface_clk", "ice_core_clk";
1824 clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
1825 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1826 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1827 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1828 qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
1829 vdd-hba-supply = <&ufs_phy_gdsc>;
1830 qcom,msm-bus,name = "ufs_ice_noc";
1831 qcom,msm-bus,num-cases = <2>;
1832 qcom,msm-bus,num-paths = <1>;
1833 qcom,msm-bus,vectors-KBps =
1834 <1 650 0 0>, /* No vote */
1835 <1 650 1000 0>; /* Max. bandwidth */
1836 qcom,bus-vector-names = "MIN",
1837 "MAX";
1838 qcom,instance-type = "ufs";
1839 };
1840
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1841 ufsphy_mem: ufsphy_mem@1d87000 {
1842 reg = <0x1d87000 0xe00>; /* PHY regs */
1843 reg-names = "phy_mem";
1844 #phy-cells = <0>;
1845
1846 lanes-per-direction = <1>;
1847
1848 clock-names = "ref_clk_src",
1849 "ref_clk",
1850 "ref_aux_clk";
1851 clocks = <&clock_rpmh RPMH_CXO_CLK>,
1852 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1853 <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;
1854
1855 status = "disabled";
1856 };
1857
1858 ufshc_mem: ufshc@1d84000 {
1859 compatible = "qcom,ufshc";
1860 reg = <0x1d84000 0x3000>;
1861 interrupts = <0 265 0>;
1862 phys = <&ufsphy_mem>;
1863 phy-names = "ufsphy";
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1864 ufs-qcom-crypto = <&ufs_ice>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1865
1866 lanes-per-direction = <1>;
1867 dev-ref-clk-freq = <0>; /* 19.2 MHz */
1868
1869 clock-names =
1870 "core_clk",
1871 "bus_aggr_clk",
1872 "iface_clk",
1873 "core_clk_unipro",
1874 "core_clk_ice",
1875 "ref_clk",
1876 "tx_lane0_sync_clk",
1877 "rx_lane0_sync_clk";
1878 clocks =
1879 <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
1880 <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>,
1881 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1882 <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
1883 <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
1884 <&clock_rpmh RPMH_CXO_CLK>,
1885 <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1886 <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
1887 freq-table-hz =
1888 <50000000 200000000>,
1889 <0 0>,
1890 <0 0>,
1891 <37500000 150000000>,
1892 <75000000 300000000>,
1893 <0 0>,
1894 <0 0>,
1895 <0 0>;
1896
Sayali Lokhandeaa3db742017-10-09 15:13:01 +0530[diff] [blame]1897 non-removable;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1898 qcom,msm-bus,name = "ufshc_mem";
1899 qcom,msm-bus,num-cases = <12>;
1900 qcom,msm-bus,num-paths = <2>;
1901 qcom,msm-bus,vectors-KBps =
1902 /*
1903 * During HS G3 UFS runs at nominal voltage corner, vote
1904 * higher bandwidth to push other buses in the data path
1905 * to run at nominal to achieve max throughput.
1906 * 4GBps pushes BIMC to run at nominal.
1907 * 200MBps pushes CNOC to run at nominal.
1908 * Vote for half of this bandwidth for HS G3 1-lane.
1909 * For max bandwidth, vote high enough to push the buses
1910 * to run in turbo voltage corner.
1911 */
1912 <123 512 0 0>, <1 757 0 0>, /* No vote */
1913 <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
1914 <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
1915 <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
1916 <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
1917 <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
1918 <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
1919 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
1920 <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
1921 <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
1922 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
1923 <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
1924
1925 qcom,bus-vector-names = "MIN",
1926 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
1927 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
1928 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
1929 "MAX";
1930
1931 /* PM QoS */
1932 qcom,pm-qos-cpu-groups = <0x3f 0xC0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]1933 qcom,pm-qos-cpu-group-latency-us = <67 67>;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1934 qcom,pm-qos-default-cpu = <0>;
1935
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1936 resets = <&clock_gcc GCC_UFS_PHY_BCR>;
1937 reset-names = "core_reset";
1938
1939 status = "disabled";
1940 };
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1941
1942 qcom,lpass@62400000 {
1943 compatible = "qcom,pil-tz-generic";
1944 reg = <0x62400000 0x00100>;
1945 interrupts = <0 162 1>;
1946
1947 vdd_cx-supply = <&pm660l_l9_level>;
1948 qcom,proxy-reg-names = "vdd_cx";
1949 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
1950
1951 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1952 clock-names = "xo";
1953 qcom,proxy-clock-names = "xo";
1954
1955 qcom,pas-id = <1>;
1956 qcom,proxy-timeout-ms = <10000>;
1957 qcom,smem-id = <423>;
1958 qcom,sysmon-id = <1>;
1959 qcom,ssctl-instance-id = <0x14>;
1960 qcom,firmware-name = "adsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1961 qcom,signal-aop;
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1962 memory-region = <&pil_adsp_mem>;
1963
1964 /* GPIO inputs from lpass */
1965 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
1966 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
1967 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
1968 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
1969
1970 /* GPIO output to lpass */
1971 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1972
1973 mboxes = <&qmp_aop 0>;
1974 mbox-names = "adsp-pil";
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1975 status = "ok";
1976 };
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]1977
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]1978 qcom,rmtfs_sharedmem@0 {
1979 compatible = "qcom,sharedmem-uio";
1980 reg = <0x0 0x200000>;
1981 reg-names = "rmtfs";
1982 qcom,client-id = <0x00000001>;
Sahitya Tummala57f7b572017-10-23 10:29:03 +0530[diff] [blame]1983 qcom,guard-memory;
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]1984 };
1985
Mohammed Javidf97a10e2017-10-08 13:11:26 +0530[diff] [blame]1986 qcom,msm_gsi {
1987 compatible = "qcom,msm_gsi";
1988 };
1989
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]1990 qcom,rmnet-ipa {
1991 compatible = "qcom,rmnet-ipa3";
1992 qcom,rmnet-ipa-ssr;
1993 qcom,ipa-loaduC;
1994 qcom,ipa-advertise-sg-support;
1995 qcom,ipa-napi-enable;
1996 };
1997
1998 ipa_hw: qcom,ipa@01e00000 {
1999 compatible = "qcom,ipa";
2000 reg = <0x1e00000 0x34000>,
2001 <0x1e04000 0x2c000>;
2002 reg-names = "ipa-base", "gsi-base";
2003 interrupts =
2004 <0 311 0>,
2005 <0 432 0>;
2006 interrupt-names = "ipa-irq", "gsi-irq";
2007 qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */
2008 qcom,ipa-hw-mode = <1>;
2009 qcom,ee = <0>;
2010 qcom,use-ipa-tethering-bridge;
2011 qcom,modem-cfg-emb-pipe-flt;
2012 qcom,ipa-wdi2;
2013 qcom,use-64-bit-dma-mask;
2014 qcom,arm-smmu;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2015 qcom,bandwidth-vote-for-ipa;
2016 qcom,msm-bus,name = "ipa";
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2017 qcom,msm-bus,num-cases = <5>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2018 qcom,msm-bus,num-paths = <4>;
2019 qcom,msm-bus,vectors-KBps =
2020 /* No vote */
2021 <90 512 0 0>,
2022 <90 585 0 0>,
2023 <1 676 0 0>,
2024 <143 777 0 0>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2025 /* SVS2 */
2026 <90 512 80000 600000>,
2027 <90 585 80000 350000>,
2028 <1 676 40000 40000>, /*gcc_config_noc_clk_src */
2029 <143 777 0 75>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2030 /* SVS */
2031 <90 512 80000 640000>,
2032 <90 585 80000 640000>,
2033 <1 676 80000 80000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2034 <143 777 0 150>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2035 /* NOMINAL */
2036 <90 512 206000 960000>,
2037 <90 585 206000 960000>,
2038 <1 676 206000 160000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2039 <143 777 0 300>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2040 /* TURBO */
2041 <90 512 206000 3600000>,
2042 <90 585 206000 3600000>,
2043 <1 676 206000 300000>,
Mohammed Javid6c065482017-09-19 19:19:27 +0530[diff] [blame]2044 <143 777 0 355>; /* IB defined for IPA clk in MHz*/
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2045 qcom,bus-vector-names =
2046 "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2047
2048 /* IPA RAM mmap */
2049 qcom,ipa-ram-mmap = <
2050 0x280 /* ofst_start; */
2051 0x0 /* nat_ofst; */
2052 0x0 /* nat_size; */
2053 0x288 /* v4_flt_hash_ofst; */
2054 0x78 /* v4_flt_hash_size; */
2055 0x4000 /* v4_flt_hash_size_ddr; */
2056 0x308 /* v4_flt_nhash_ofst; */
2057 0x78 /* v4_flt_nhash_size; */
2058 0x4000 /* v4_flt_nhash_size_ddr; */
2059 0x388 /* v6_flt_hash_ofst; */
2060 0x78 /* v6_flt_hash_size; */
2061 0x4000 /* v6_flt_hash_size_ddr; */
2062 0x408 /* v6_flt_nhash_ofst; */
2063 0x78 /* v6_flt_nhash_size; */
2064 0x4000 /* v6_flt_nhash_size_ddr; */
2065 0xf /* v4_rt_num_index; */
2066 0x0 /* v4_modem_rt_index_lo; */
2067 0x7 /* v4_modem_rt_index_hi; */
2068 0x8 /* v4_apps_rt_index_lo; */
2069 0xe /* v4_apps_rt_index_hi; */
2070 0x488 /* v4_rt_hash_ofst; */
2071 0x78 /* v4_rt_hash_size; */
2072 0x4000 /* v4_rt_hash_size_ddr; */
2073 0x508 /* v4_rt_nhash_ofst; */
2074 0x78 /* v4_rt_nhash_size; */
2075 0x4000 /* v4_rt_nhash_size_ddr; */
2076 0xf /* v6_rt_num_index; */
2077 0x0 /* v6_modem_rt_index_lo; */
2078 0x7 /* v6_modem_rt_index_hi; */
2079 0x8 /* v6_apps_rt_index_lo; */
2080 0xe /* v6_apps_rt_index_hi; */
2081 0x588 /* v6_rt_hash_ofst; */
2082 0x78 /* v6_rt_hash_size; */
2083 0x4000 /* v6_rt_hash_size_ddr; */
2084 0x608 /* v6_rt_nhash_ofst; */
2085 0x78 /* v6_rt_nhash_size; */
2086 0x4000 /* v6_rt_nhash_size_ddr; */
2087 0x688 /* modem_hdr_ofst; */
2088 0x140 /* modem_hdr_size; */
2089 0x7c8 /* apps_hdr_ofst; */
2090 0x0 /* apps_hdr_size; */
2091 0x800 /* apps_hdr_size_ddr; */
2092 0x7d0 /* modem_hdr_proc_ctx_ofst; */
2093 0x200 /* modem_hdr_proc_ctx_size; */
2094 0x9d0 /* apps_hdr_proc_ctx_ofst; */
2095 0x200 /* apps_hdr_proc_ctx_size; */
2096 0x0 /* apps_hdr_proc_ctx_size_ddr; */
2097 0x0 /* modem_comp_decomp_ofst; diff */
2098 0x0 /* modem_comp_decomp_size; diff */
2099 0xbd8 /* modem_ofst; */
2100 0x1024 /* modem_size; */
2101 0x2000 /* apps_v4_flt_hash_ofst; */
2102 0x0 /* apps_v4_flt_hash_size; */
2103 0x2000 /* apps_v4_flt_nhash_ofst; */
2104 0x0 /* apps_v4_flt_nhash_size; */
2105 0x2000 /* apps_v6_flt_hash_ofst; */
2106 0x0 /* apps_v6_flt_hash_size; */
2107 0x2000 /* apps_v6_flt_nhash_ofst; */
2108 0x0 /* apps_v6_flt_nhash_size; */
2109 0x80 /* uc_info_ofst; */
2110 0x200 /* uc_info_size; */
2111 0x2000 /* end_ofst; */
2112 0x2000 /* apps_v4_rt_hash_ofst; */
2113 0x0 /* apps_v4_rt_hash_size; */
2114 0x2000 /* apps_v4_rt_nhash_ofst; */
2115 0x0 /* apps_v4_rt_nhash_size; */
2116 0x2000 /* apps_v6_rt_hash_ofst; */
2117 0x0 /* apps_v6_rt_hash_size; */
2118 0x2000 /* apps_v6_rt_nhash_ofst; */
2119 0x0 /* apps_v6_rt_nhash_size; */
2120 0x1c00 /* uc_event_ring_ofst; */
2121 0x400 /* uc_event_ring_size; */
2122 >;
2123
2124 /* smp2p gpio information */
2125 qcom,smp2pgpio_map_ipa_1_out {
2126 compatible = "qcom,smp2pgpio-map-ipa-1-out";
2127 gpios = <&smp2pgpio_ipa_1_out 0 0>;
2128 };
2129
2130 qcom,smp2pgpio_map_ipa_1_in {
2131 compatible = "qcom,smp2pgpio-map-ipa-1-in";
2132 gpios = <&smp2pgpio_ipa_1_in 0 0>;
2133 };
2134
2135 ipa_smmu_ap: ipa_smmu_ap {
2136 compatible = "qcom,ipa-smmu-ap-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2137 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2138 iommus = <&apps_smmu 0x720 0x0>;
2139 qcom,iova-mapping = <0x20000000 0x40000000>;
2140 };
2141
2142 ipa_smmu_wlan: ipa_smmu_wlan {
2143 compatible = "qcom,ipa-smmu-wlan-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2144 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2145 iommus = <&apps_smmu 0x721 0x0>;
2146 };
2147
2148 ipa_smmu_uc: ipa_smmu_uc {
2149 compatible = "qcom,ipa-smmu-uc-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2150 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2151 iommus = <&apps_smmu 0x722 0x0>;
2152 qcom,iova-mapping = <0x40000000 0x20000000>;
2153 };
2154 };
2155
2156 qcom,ipa_fws {
2157 compatible = "qcom,pil-tz-generic";
2158 qcom,pas-id = <0xf>;
2159 qcom,firmware-name = "ipa_fws";
Mohammed Javid42445cb2018-02-01 18:22:17 +0530[diff] [blame]2160 qcom,pil-force-shutdown;
Mohammed Javide0dd2a32018-01-25 14:18:56 +0530[diff] [blame]2161 memory-region = <&pil_ipa_fw_mem>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2162 };
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2163
2164 pil_modem: qcom,mss@4080000 {
2165 compatible = "qcom,pil-q6v55-mss";
2166 reg = <0x4080000 0x100>,
2167 <0x1f63000 0x008>,
2168 <0x1f65000 0x008>,
2169 <0x1f64000 0x008>,
2170 <0x4180000 0x020>,
2171 <0xc2b0000 0x004>,
2172 <0xb2e0100 0x004>,
2173 <0x4180044 0x004>;
2174 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2175 "halt_nc", "rmb_base", "restart_reg",
2176 "pdc_sync", "alt_reset";
2177
2178 clocks = <&clock_rpmh RPMH_CXO_CLK>,
2179 <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
2180 <&clock_gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2181 <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
2182 <&clock_gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2183 <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
2184 <&clock_gcc GCC_MSS_MFAB_AXIS_CLK>,
2185 <&clock_gcc GCC_PRNG_AHB_CLK>;
2186 clock-names = "xo", "iface_clk", "bus_clk",
2187 "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2188 "mnoc_axi_clk", "prng_clk";
2189 qcom,proxy-clock-names = "xo", "prng_clk";
2190 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
2191 "gpll0_mss_clk", "snoc_axi_clk",
2192 "mnoc_axi_clk";
2193
2194 interrupts = <0 266 1>;
2195 vdd_cx-supply = <&pm660l_s3_level>;
2196 vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 vdd_mx-supply = <&pm660l_s1_level>;
2198 vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Jitendra Sharma2e981ef2017-10-30 12:16:23 +0530[diff] [blame]2199 vdd_mss-supply = <&pm660_s5_level>;
2200 vdd_mss-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2201 qcom,firmware-name = "modem";
2202 qcom,pil-self-auth;
2203 qcom,sysmon-id = <0>;
Avaneesh Kumar Dwivedi8d336612017-11-09 16:48:25 +0530[diff] [blame]2204 qcom,minidump-id = <3>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2205 qcom,ssctl-instance-id = <0x12>;
2206 qcom,override-acc;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2207 qcom,signal-aop;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2208 qcom,qdsp6v65-1-0;
Jitendra Sharma93dd7fc2017-10-14 17:38:55 +0530[diff] [blame]2209 qcom,mss_pdc_offset = <9>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2210 status = "ok";
2211 memory-region = <&pil_modem_mem>;
2212 qcom,mem-protect-id = <0xF>;
2213
2214 /* GPIO inputs from mss */
2215 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2216 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2217 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2218 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2219 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2220
2221 /* GPIO output to mss */
2222 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2223
2224 mboxes = <&qmp_aop 0>;
2225 mbox-names = "mss-pil";
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2226 qcom,mba-mem@0 {
2227 compatible = "qcom,pil-mba-mem";
2228 memory-region = <&pil_mba_mem>;
2229 };
2230 };
Gaurav Kohli985a99d2017-07-25 18:46:45 +0530[diff] [blame]2231
2232 qcom,venus@aae0000 {
2233 compatible = "qcom,pil-tz-generic";
2234 reg = <0xaae0000 0x4000>;
2235
2236 vdd-supply = <&venus_gdsc>;
2237 qcom,proxy-reg-names = "vdd";
2238
2239 clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2240 <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>,
2241 <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2242 clock-names = "core_clk", "iface_clk", "bus_clk";
2243 qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";
2244
2245 qcom,pas-id = <9>;
2246 qcom,msm-bus,name = "pil-venus";
2247 qcom,msm-bus,num-cases = <2>;
2248 qcom,msm-bus,num-paths = <1>;
2249 qcom,msm-bus,vectors-KBps =
2250 <63 512 0 0>,
2251 <63 512 0 304000>;
2252 qcom,proxy-timeout-ms = <100>;
2253 qcom,firmware-name = "venus";
2254 memory-region = <&pil_video_mem>;
2255 status = "ok";
2256 };
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2257
2258 qcom,turing@8300000 {
2259 compatible = "qcom,pil-tz-generic";
2260 reg = <0x8300000 0x100000>;
2261 interrupts = <0 578 1>;
2262
2263 vdd_cx-supply = <&pm660l_s3_level>;
2264 qcom,proxy-reg-names = "vdd_cx";
2265 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
2266
2267 clocks = <&clock_rpmh RPMH_CXO_CLK>;
2268 clock-names = "xo";
2269 qcom,proxy-clock-names = "xo";
2270
2271 qcom,pas-id = <18>;
2272 qcom,proxy-timeout-ms = <10000>;
2273 qcom,smem-id = <601>;
2274 qcom,sysmon-id = <7>;
2275 qcom,ssctl-instance-id = <0x17>;
2276 qcom,firmware-name = "cdsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2277 qcom,signal-aop;
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2278 memory-region = <&pil_cdsp_mem>;
2279
2280 /* GPIO inputs from turing */
2281 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
2282 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
2283 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
2284 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;
2285
2286 /* GPIO output to turing*/
2287 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2288
2289 mboxes = <&qmp_aop 0>;
2290 mbox-names = "cdsp-pil";
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2291 status = "ok";
2292 };
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2293
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2294 sdcc1_ice: sdcc1ice@7c8000 {
2295 compatible = "qcom,ice";
2296 reg = <0x7c8000 0x8000>;
2297 qcom,enable-ice-clk;
2298 clock-names = "ice_core_clk_src", "ice_core_clk",
2299 "bus_clk", "iface_clk";
2300 clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,
2301 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
2302 <&clock_gcc GCC_SDCC1_APPS_CLK>,
2303 <&clock_gcc GCC_SDCC1_AHB_CLK>;
2304 qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
2305 qcom,msm-bus,name = "sdcc_ice_noc";
2306 qcom,msm-bus,num-cases = <2>;
2307 qcom,msm-bus,num-paths = <1>;
2308 qcom,msm-bus,vectors-KBps =
2309 <150 512 0 0>, /* No vote */
2310 <150 512 1000 0>; /* Max. bandwidth */
2311 qcom,bus-vector-names = "MIN",
2312 "MAX";
2313 qcom,instance-type = "sdcc";
2314 };
2315
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2316 sdhc_1: sdhci@7c4000 {
2317 compatible = "qcom,sdhci-msm-v5";
2318 reg = <0x7C4000 0x1000>, <0x7C5000 0x1000>;
2319 reg-names = "hc_mem", "cmdq_mem";
2320
2321 interrupts = <0 641 0>, <0 644 0>;
2322 interrupt-names = "hc_irq", "pwr_irq";
2323
2324 qcom,bus-width = <8>;
2325 qcom,large-address-bus;
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2326 sdhc-msm-crypto = <&sdcc1_ice>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2327
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2328 qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
2329 192000000 384000000>;
Vijay Viswanath01db23a2017-11-09 15:46:22 +0530[diff] [blame]2330 qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000
2331 100000000 200000000 200000000>;
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2332 qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
2333
2334 qcom,devfreq,freq-table = <50000000 200000000>;
2335
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2336 qcom,msm-bus,name = "sdhc1";
2337 qcom,msm-bus,num-cases = <9>;
2338 qcom,msm-bus,num-paths = <2>;
2339 qcom,msm-bus,vectors-KBps =
2340 /* No vote */
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2341 <150 512 0 0>, <1 782 0 0>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2342 /* 400 KB/s*/
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2343 <150 512 1046 1600>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2344 <1 782 1600 1600>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2345 /* 20 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2346 <150 512 52286 80000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2347 <1 782 80000 80000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2348 /* 25 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2349 <150 512 65360 100000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2350 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2351 /* 50 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2352 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2353 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2354 /* 100 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2355 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2356 <1 782 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2357 /* 200 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2358 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2359 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2360 /* 400 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2361 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2362 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2363 /* Max. bandwidth */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2364 <150 512 1338562 4096000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2365 <1 782 1338562 4096000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2366 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2367 100000000 200000000 400000000 4294967295>;
2368
2369 /* PM QoS */
2370 qcom,pm-qos-irq-type = "affine_irq";
Vijay Viswanathcac6f862018-03-20 11:40:54 +0530[diff] [blame^]2371 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2372 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2373 qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;
2374 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2375
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2376 clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2377 <&clock_gcc GCC_SDCC1_APPS_CLK>,
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2378 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
2379 <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
2380 clock-names = "iface_clk", "core_clk", "ice_core_clk",
2381 "bus_aggr_clk";
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2382
2383 qcom,ice-clk-rates = <300000000 75000000>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2384
Vijay Viswanathd4dcf5f2017-10-17 15:42:00 +0530[diff] [blame]2385 qcom,ddr-config = <0xC3040873>;
2386
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2387 qcom,nonremovable;
Asutosh Das3d37f972018-01-12 15:48:25 +0530[diff] [blame]2388 nvmem-cells = <&minor_rev>;
2389 nvmem-cell-names = "minor_rev";
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2390
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2391 status = "disabled";
2392 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2393
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2394 sdhc_2: sdhci@8804000 {
2395 compatible = "qcom,sdhci-msm-v5";
2396 reg = <0x8804000 0x1000>;
2397 reg-names = "hc_mem";
2398
2399 interrupts = <0 204 0>, <0 222 0>;
2400 interrupt-names = "hc_irq", "pwr_irq";
2401
2402 qcom,bus-width = <4>;
2403 qcom,large-address-bus;
2404
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2405 qcom,clk-rates = <400000 20000000 25000000
2406 50000000 100000000 201500000>;
2407 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
2408 "SDR104";
2409
2410 qcom,devfreq,freq-table = <50000000 201500000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2411
2412 qcom,msm-bus,name = "sdhc2";
2413 qcom,msm-bus,num-cases = <8>;
2414 qcom,msm-bus,num-paths = <2>;
2415 qcom,msm-bus,vectors-KBps =
2416 /* No vote */
2417 <81 512 0 0>, <1 608 0 0>,
2418 /* 400 KB/s*/
2419 <81 512 1046 1600>,
2420 <1 608 1600 1600>,
2421 /* 20 MB/s */
2422 <81 512 52286 80000>,
2423 <1 608 80000 80000>,
2424 /* 25 MB/s */
2425 <81 512 65360 100000>,
2426 <1 608 100000 100000>,
2427 /* 50 MB/s */
2428 <81 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2429 <1 608 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2430 /* 100 MB/s */
2431 <81 512 261438 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2432 <1 608 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2433 /* 200 MB/s */
2434 <81 512 261438 400000>,
2435 <1 608 300000 300000>,
2436 /* Max. bandwidth */
2437 <81 512 1338562 4096000>,
2438 <1 608 1338562 4096000>;
2439 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2440 100000000 200000000 4294967295>;
2441
2442 /* PM QoS */
2443 qcom,pm-qos-irq-type = "affine_irq";
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2444 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2445 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2446 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2447
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2448 clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
2449 <&clock_gcc GCC_SDCC2_APPS_CLK>;
2450 clock-names = "iface_clk", "core_clk";
2451
2452 status = "disabled";
2453 };
2454
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2455 qcom,msm-cdsp-loader {
2456 compatible = "qcom,cdsp-loader";
2457 qcom,proc-img-to-load = "cdsp";
2458 };
2459
2460 qcom,msm-adsprpc-mem {
2461 compatible = "qcom,msm-adsprpc-mem-region";
2462 memory-region = <&adsp_mem>;
Tharun Kumar Merugu8bb71292018-01-17 15:55:05 +0530[diff] [blame]2463 restrict-access;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2464 };
2465
2466 qcom,msm_fastrpc {
2467 compatible = "qcom,msm-fastrpc-compute";
Tharun Kumar Merugubbebad12017-12-21 16:33:03 +0530[diff] [blame]2468 qcom,adsp-remoteheap-vmid = <22 37>;
Tharun Kumar Merugu1cb19c62018-01-18 12:20:16 +0530[diff] [blame]2469 qcom,fastrpc-adsp-audio-pdr;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2470
2471 qcom,msm_fastrpc_compute_cb1 {
2472 compatible = "qcom,msm-fastrpc-compute-cb";
2473 label = "cdsprpc-smd";
2474 iommus = <&apps_smmu 0x1421 0x30>;
2475 dma-coherent;
2476 };
2477 qcom,msm_fastrpc_compute_cb2 {
2478 compatible = "qcom,msm-fastrpc-compute-cb";
2479 label = "cdsprpc-smd";
2480 iommus = <&apps_smmu 0x1422 0x30>;
2481 dma-coherent;
2482 };
2483 qcom,msm_fastrpc_compute_cb3 {
2484 compatible = "qcom,msm-fastrpc-compute-cb";
2485 label = "cdsprpc-smd";
2486 iommus = <&apps_smmu 0x1423 0x30>;
2487 dma-coherent;
2488 };
2489 qcom,msm_fastrpc_compute_cb4 {
2490 compatible = "qcom,msm-fastrpc-compute-cb";
2491 label = "cdsprpc-smd";
2492 iommus = <&apps_smmu 0x1424 0x30>;
2493 dma-coherent;
2494 };
2495 qcom,msm_fastrpc_compute_cb5 {
2496 compatible = "qcom,msm-fastrpc-compute-cb";
2497 label = "cdsprpc-smd";
2498 iommus = <&apps_smmu 0x1425 0x30>;
2499 dma-coherent;
2500 };
2501 qcom,msm_fastrpc_compute_cb6 {
2502 compatible = "qcom,msm-fastrpc-compute-cb";
2503 label = "cdsprpc-smd";
2504 iommus = <&apps_smmu 0x1426 0x30>;
2505 dma-coherent;
2506 };
2507 qcom,msm_fastrpc_compute_cb7 {
2508 compatible = "qcom,msm-fastrpc-compute-cb";
2509 label = "cdsprpc-smd";
2510 qcom,secure-context-bank;
2511 iommus = <&apps_smmu 0x1429 0x30>;
2512 dma-coherent;
2513 };
2514 qcom,msm_fastrpc_compute_cb8 {
2515 compatible = "qcom,msm-fastrpc-compute-cb";
2516 label = "cdsprpc-smd";
2517 qcom,secure-context-bank;
2518 iommus = <&apps_smmu 0x142A 0x30>;
2519 dma-coherent;
2520 };
2521 qcom,msm_fastrpc_compute_cb9 {
2522 compatible = "qcom,msm-fastrpc-compute-cb";
2523 label = "adsprpc-smd";
2524 iommus = <&apps_smmu 0x1803 0x0>;
2525 dma-coherent;
2526 };
2527 qcom,msm_fastrpc_compute_cb10 {
2528 compatible = "qcom,msm-fastrpc-compute-cb";
2529 label = "adsprpc-smd";
2530 iommus = <&apps_smmu 0x1804 0x0>;
2531 dma-coherent;
2532 };
2533 qcom,msm_fastrpc_compute_cb11 {
2534 compatible = "qcom,msm-fastrpc-compute-cb";
2535 label = "adsprpc-smd";
2536 iommus = <&apps_smmu 0x1805 0x0>;
2537 dma-coherent;
2538 };
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2539 qcom,msm_fastrpc_compute_cb12 {
2540 compatible = "qcom,msm-fastrpc-compute-cb";
2541 label = "adsprpc-smd";
2542 iommus = <&apps_smmu 0x1806 0x0>;
2543 dma-coherent;
2544 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2545 };
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2546
Rupesh Tatiyaf2072952017-10-08 19:57:12 +0530[diff] [blame]2547 bluetooth: bt_wcn3990 {
2548 compatible = "qca,wcn3990";
2549 qca,bt-vdd-core-supply = <&pm660_l9>;
2550 qca,bt-vdd-pa-supply = <&pm660_l6>;
2551 qca,bt-vdd-ldo-supply = <&pm660_l19>;
2552
2553 qca,bt-vdd-core-voltage-level = <1800000 1900000>;
2554 qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
2555 qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
2556
2557 qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
2558 qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
2559 qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
2560 };
2561
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2562 qcom,icnss@18800000 {
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2563 compatible = "qcom,icnss";
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2564 reg = <0x18800000 0x800000>,
2565 <0xa0000000 0x10000000>,
2566 <0xb0000000 0x10000>;
2567 reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
2568 iommus = <&apps_smmu 0x0040 0x1>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2569 interrupts = <0 414 0 /* CE0 */ >,
2570 <0 415 0 /* CE1 */ >,
2571 <0 416 0 /* CE2 */ >,
2572 <0 417 0 /* CE3 */ >,
2573 <0 418 0 /* CE4 */ >,
2574 <0 419 0 /* CE5 */ >,
2575 <0 420 0 /* CE6 */ >,
2576 <0 421 0 /* CE7 */ >,
2577 <0 422 0 /* CE8 */ >,
2578 <0 423 0 /* CE9 */ >,
2579 <0 424 0 /* CE10 */ >,
2580 <0 425 0 /* CE11 */ >;
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2581 vdd-0.8-cx-mx-supply = <&pm660_l5>;
2582 vdd-1.8-xo-supply = <&pm660_l9>;
2583 vdd-1.3-rfa-supply = <&pm660_l6>;
2584 vdd-3.3-ch0-supply = <&pm660_l19>;
Hardik Kantilal Patel25c05b42017-12-08 11:10:27 +0530[diff] [blame]2585 qcom,vdd-3.3-ch0-config = <3000000 3312000>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2586 qcom,wlan-msa-memory = <0x100000>;
Anurag Chouhana4f55db2017-11-22 16:35:27 +0530[diff] [blame]2587 qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
Hardik Kantilal Patel1697bd12018-03-05 14:46:29 +0530[diff] [blame]2588 qcom,gpio-force-fatal-error = <&smp2pgpio_wlan_1_in 0 0>;
2589 qcom,gpio-early-crash-ind = <&smp2pgpio_wlan_1_in 1 0>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2590 qcom,smmu-s1-bypass;
2591 };
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2592
2593 cpubw: qcom,cpubw {
2594 compatible = "qcom,devbw";
2595 governor = "performance";
2596 qcom,src-dst-ports =
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2597 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2598 qcom,active-only;
2599 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2600 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2601 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2602 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2603 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2604 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2605 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2606 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2607 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2608 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2609 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2610 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2611 };
2612
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2613 bwmon: qcom,cpu-bwmon {
2614 compatible = "qcom,bimc-bwmon4";
2615 reg = <0x1436400 0x300>, <0x1436300 0x200>;
2616 reg-names = "base", "global_base";
2617 interrupts = <0 581 4>;
2618 qcom,mport = <0>;
Santosh Mardida0b0f82017-10-13 23:30:22 +0530[diff] [blame]2619 qcom,count-unit = <0x10000>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2620 qcom,hw-timer-hz = <19200000>;
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2621 qcom,target-dev = <&cpubw>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2622 };
2623
2624 memlat_cpu0: qcom,memlat-cpu0 {
2625 compatible = "qcom,devbw";
2626 governor = "powersave";
2627 qcom,src-dst-ports = <1 512>;
2628 qcom,active-only;
2629 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2630 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2631 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2632 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2633 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2634 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2635 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2636 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2637 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2638 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2639 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2640 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2641 };
2642
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2643 memlat_cpu6: qcom,memlat-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2644 compatible = "qcom,devbw";
2645 governor = "powersave";
2646 qcom,src-dst-ports = <1 512>;
2647 qcom,active-only;
2648 status = "ok";
2649 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2650 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2651 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2652 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2653 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2654 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2655 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2656 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2657 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2658 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2659 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2660 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2661 };
2662
Odelu Kukatlafe8d3302017-11-17 10:54:32 +0530[diff] [blame]2663 snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
2664 compatible = "qcom,devbw";
2665 governor = "powersave";
2666 qcom,src-dst-ports = <139 627>;
2667 qcom,active-only;
2668 status = "ok";
2669 qcom,bw-tbl =
2670 < 1 >;
2671 };
2672
Odelu Kukatla95e7aea2018-02-27 15:46:39 +0530[diff] [blame]2673 bus_proxy_client: qcom,bus_proxy_client {
2674 compatible = "qcom,bus-proxy-client";
2675 qcom,msm-bus,name = "bus-proxy-client";
2676 qcom,msm-bus,num-cases = <2>;
2677 qcom,msm-bus,num-paths = <2>;
2678 qcom,msm-bus,vectors-KBps =
2679 <22 512 0 0>, <23 512 0 0>,
2680 <22 512 0 5000000>, <23 512 0 5000000>;
2681 qcom,msm-bus,active-only;
2682 status = "ok";
2683 };
2684
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2685 devfreq_memlat_0: qcom,cpu0-memlat-mon {
2686 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2687 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2688 qcom,target-dev = <&memlat_cpu0>;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2689 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2690 qcom,core-dev-table =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2691 < 748800 MHZ_TO_MBPS( 300, 4) >,
2692 < 998400 MHZ_TO_MBPS( 451, 4) >,
2693 < 1209600 MHZ_TO_MBPS( 547, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2694 < 1516800 MHZ_TO_MBPS( 768, 4) >,
2695 < 1708000 MHZ_TO_MBPS(1017, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2696 };
2697
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2698 devfreq_memlat_6: qcom,cpu6-memlat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2699 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2700 qcom,cpulist = <&CPU6 &CPU7>;
2701 qcom,target-dev = <&memlat_cpu6>;
2702 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2703 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2704 < 825600 MHZ_TO_MBPS( 300, 4) >,
2705 < 1132800 MHZ_TO_MBPS( 547, 4) >,
2706 < 1363200 MHZ_TO_MBPS(1017, 4) >,
2707 < 1996800 MHZ_TO_MBPS(1555, 4) >,
2708 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2709 };
2710
2711 l3_cpu0: qcom,l3-cpu0 {
2712 compatible = "devfreq-simple-dev";
2713 clock-names = "devfreq_clk";
2714 clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;
2715 governor = "performance";
2716 };
2717
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2718 l3_cpu6: qcom,l3-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2719 compatible = "devfreq-simple-dev";
2720 clock-names = "devfreq_clk";
2721 clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
2722 governor = "performance";
2723 };
2724
2725 devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
2726 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2727 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2728 qcom,target-dev = <&l3_cpu0>;
2729 qcom,cachemiss-ev = <0x17>;
2730 qcom,core-dev-table =
Santosh Mardi10d45032017-11-02 17:25:54 +0530[diff] [blame]2731 < 576000 300000000 >,
Santosh Mardi831cc872018-01-11 14:52:32 +0530[diff] [blame]2732 < 998400 556800000 >,
2733 < 1209660 844800000 >,
2734 < 1516800 940800000 >,
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2735 < 1612800 1382400000 >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2736 < 1708000 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2737 };
2738
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2739 devfreq_l3lat_6: qcom,cpu6-l3lat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2740 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2741 qcom,cpulist = <&CPU6 &CPU7>;
2742 qcom,target-dev = <&l3_cpu6>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2743 qcom,cachemiss-ev = <0x17>;
2744 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2745 < 1132800 556800000 >,
2746 < 1363200 806400000 >,
2747 < 1747200 940800000 >,
2748 < 1996800 1190400000 >,
2749 < 2457600 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2750 };
2751
2752 mincpubw: qcom,mincpubw {
2753 compatible = "qcom,devbw";
2754 governor = "powersave";
2755 qcom,src-dst-ports = <1 512>;
2756 qcom,active-only;
2757 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2758 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2759 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2760 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2761 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2762 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2763 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2764 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2765 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2766 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2767 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2768 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2769 };
2770
2771 devfreq-cpufreq {
2772 mincpubw-cpufreq {
2773 target-dev = <&mincpubw>;
2774 cpu-to-dev-map-0 =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2775 < 748800 MHZ_TO_MBPS( 300, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2776 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2777 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2778 < 1708000 MHZ_TO_MBPS( 768, 4) >;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2779 cpu-to-dev-map-6 =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2780 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2781 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2782 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2783 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2784 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2785 };
2786 };
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2787
Jonathan Avilac7a6fd52017-10-12 15:24:05 -0700[diff] [blame]2788 mincpu0bw: qcom,mincpu0bw {
2789 compatible = "qcom,devbw";
2790 governor = "powersave";
2791 qcom,src-dst-ports = <1 512>;
2792 qcom,active-only;
2793 qcom,bw-tbl =
2794 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2795 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2796 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2797 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2798 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2799 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2800 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2801 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2802 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2803 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2804 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2805 };
2806
2807 mincpu6bw: qcom,mincpu6bw {
2808 compatible = "qcom,devbw";
2809 governor = "powersave";
2810 qcom,src-dst-ports = <1 512>;
2811 qcom,active-only;
2812 qcom,bw-tbl =
2813 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2814 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2815 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2816 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2817 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2818 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2819 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2820 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2821 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2822 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2823 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2824 };
2825
2826 devfreq_compute0: qcom,devfreq-compute0 {
2827 compatible = "qcom,arm-cpu-mon";
2828 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
2829 qcom,target-dev = <&mincpu0bw>;
2830 qcom,core-dev-table =
2831 < 748800 MHZ_TO_MBPS( 300, 4) >,
2832 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2833 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2834 < 1708000 MHZ_TO_MBPS( 768, 4) >;
2835 };
2836
2837 devfreq_compute6: qcom,devfreq-compute6 {
2838 compatible = "qcom,arm-cpu-mon";
2839 qcom,cpulist = <&CPU6 &CPU7>;
2840 qcom,target-dev = <&mincpu6bw>;
2841 qcom,core-dev-table =
2842 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2843 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2844 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2845 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2846 < 2457600 MHZ_TO_MBPS(1804, 4) >;
2847 };
2848
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]2849 l3_cdsp: qcom,l3-cdsp {
2850 compatible = "devfreq-simple-dev";
2851 clock-names = "devfreq_clk";
2852 clocks = <&clock_cpucc L3_MISC_VOTE_CLK>;
2853 governor = "powersave";
2854 };
2855
Raghavendra Rao Ananta28dd4502017-10-18 10:28:31 -0700[diff] [blame]2856 cpu_pmu: cpu-pmu {
2857 compatible = "arm,armv8-pmuv3";
2858 qcom,irq-is-percpu;
2859 interrupts = <1 5 4>;
2860 };
2861
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2862 gpu_gx_domain_addr: syscon@0x5091508 {
2863 compatible = "syscon";
2864 reg = <0x5091508 0x4>;
2865 };
2866
2867 gpu_gx_sw_reset: syscon@0x5091008 {
2868 compatible = "syscon";
2869 reg = <0x5091008 0x4>;
2870 };
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2871
2872 qfprom: qfprom@0x780000 {
2873 compatible = "qcom,qfprom";
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2874 reg = <0x00784000 0x1000>;
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2875 #address-cells = <1>;
2876 #size-cells = <1>;
2877 ranges;
2878
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2879 minor_rev: minor_rev@0x78414c {
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2880 reg = <0x14c 0x4>;
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2881 bits = <0 30>; /* Access 30 bits from bit offset 0 */
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2882 };
2883 };
2884
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2885};
2886
Ashay Jaiswal81940302017-09-20 15:17:58 +0530[diff] [blame]2887#include "pm660.dtsi"
2888#include "pm660l.dtsi"
2889#include "sdm670-regulator.dtsi"
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2890#include "sdm670-pinctrl.dtsi"
Vijayanand Jittad48c4082017-06-07 15:07:51 +0530[diff] [blame]2891#include "msm-arm-smmu-sdm670.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2892#include "msm-gdsc-sdm845.dtsi"
Maulik Shahd313ea82017-06-14 13:10:52 +0530[diff] [blame]2893#include "sdm670-pm.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2894
2895&usb30_prim_gdsc {
2896 status = "ok";
2897};
2898
2899&ufs_phy_gdsc {
2900 status = "ok";
2901};
2902
2903&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
2904 status = "ok";
2905};
2906
2907&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
2908 status = "ok";
2909};
2910
2911&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
2912 status = "ok";
2913};
2914
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2915&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
2916 status = "ok";
2917};
2918
2919&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
2920 status = "ok";
2921};
2922
2923&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
2924 status = "ok";
2925};
2926
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2927&bps_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2928 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2929 status = "ok";
2930};
2931
2932&ife_0_gdsc {
2933 status = "ok";
2934};
2935
2936&ife_1_gdsc {
2937 status = "ok";
2938};
2939
2940&ipe_0_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2941 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2942 status = "ok";
2943};
2944
2945&ipe_1_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2946 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2947 status = "ok";
2948};
2949
2950&titan_top_gdsc {
2951 status = "ok";
2952};
2953
2954&mdss_core_gdsc {
2955 status = "ok";
Sandeep Pandaae888352017-11-15 13:15:31 +0530[diff] [blame]2956 proxy-supply = <&mdss_core_gdsc>;
2957 qcom,proxy-consumer-enable;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2958};
2959
2960&gpu_cx_gdsc {
2961 status = "ok";
2962};
2963
2964&gpu_gx_gdsc {
2965 clock-names = "core_root_clk";
2966 clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>;
2967 qcom,force-enable-root-clk;
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2968 parent-supply = <&pm660l_s2_level>;
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2969 domain-addr = <&gpu_gx_domain_addr>;
2970 sw-reset = <&gpu_gx_sw_reset>;
2971 qcom,reset-aon-logic;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2972 status = "ok";
2973};
2974
2975&vcodec0_gdsc {
2976 qcom,support-hw-trigger;
2977 status = "ok";
2978};
2979
2980&vcodec1_gdsc {
2981 qcom,support-hw-trigger;
2982 status = "ok";
2983};
2984
2985&venus_gdsc {
2986 status = "ok";
2987};
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]2988
Sandeep Panda229db242017-10-03 11:32:29 +0530[diff] [blame]2989&mdss_dsi0 {
2990 qcom,core-supply-entries {
2991 #address-cells = <1>;
2992 #size-cells = <0>;
2993
2994 qcom,core-supply-entry@0 {
2995 reg = <0>;
2996 qcom,supply-name = "refgen";
2997 qcom,supply-min-voltage = <0>;
2998 qcom,supply-max-voltage = <0>;
2999 qcom,supply-enable-load = <0>;
3000 qcom,supply-disable-load = <0>;
3001 };
3002 };
3003};
3004
3005&mdss_dsi1 {
3006 qcom,core-supply-entries {
3007 #address-cells = <1>;
3008 #size-cells = <0>;
3009
3010 qcom,core-supply-entry@0 {
3011 reg = <0>;
3012 qcom,supply-name = "refgen";
3013 qcom,supply-min-voltage = <0>;
3014 qcom,supply-max-voltage = <0>;
3015 qcom,supply-enable-load = <0>;
3016 qcom,supply-disable-load = <0>;
3017 };
3018 };
3019};
3020
Padmanabhan Komanduru07137332017-10-20 12:53:23 +0530[diff] [blame]3021&sde_dp {
3022 qcom,core-supply-entries {
3023 #address-cells = <1>;
3024 #size-cells = <0>;
3025
3026 qcom,core-supply-entry@0 {
3027 reg = <0>;
3028 qcom,supply-name = "refgen";
3029 qcom,supply-min-voltage = <0>;
3030 qcom,supply-max-voltage = <0>;
3031 qcom,supply-enable-load = <0>;
3032 qcom,supply-disable-load = <0>;
3033 };
3034 };
3035};
3036
Rohit Kumar14051282017-07-12 11:18:48 +0530[diff] [blame]3037#include "sdm670-audio.dtsi"
Pratham Pratap9e420a32017-09-05 11:26:57 +0530[diff] [blame]3038#include "sdm670-usb.dtsi"
Rajesh Kemisettiba56c482017-08-31 18:12:35 +0530[diff] [blame]3039#include "sdm670-gpu.dtsi"
Suresh Vankadara402d0ca2017-10-26 22:54:54 +0530[diff] [blame]3040#include "sdm670-camera.dtsi"
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]3041#include "sdm670-thermal.dtsi"
Odelu Kukatlaf197e382017-07-04 19:47:35 +0530[diff] [blame]3042#include "sdm670-bus.dtsi"
Tirupathi Reddyf805ac72017-10-12 14:22:17 +0530[diff] [blame]3043
3044&pm660_div_clk {
3045 status = "ok";
3046};
Tirupathi Reddy53b92a62017-10-26 13:57:42 +0530[diff] [blame]3047
3048&qupv3_se10_i2c {
3049 nx30p6093: nx30p6093@36 {
3050 status = "disabled";
3051 compatible = "nxp,nx30p6093";
3052 reg = <0x36>;
3053 interrupt-parent = <&tlmm>;
3054 interrupts = <5 IRQ_TYPE_NONE>;
3055 nxp,long-wakeup-sec = <28800>; /* 8 hours */
3056 nxp,short-wakeup-ms = <180000>; /* 3 mins */
3057 pinctrl-names = "default";
3058 pinctrl-0 = <&nx30p6093_intr_default>;
3059 };
3060};