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gerrit-public.fairphone.software / kernel / msm-4.9 / d6f4899aaa32d2c70630ea2bd8223cd2737f9641 / . / arch / arm64 / boot / dts / qcom / sdm845-v2.dtsi
blob: d32e8f5763c74f202b6a44247d57267f8498b929 [file] [log] [blame]
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "sdm845.dtsi"
Soundrapandian Jeyaprakash3cc03bb2017-08-09 15:16:41 -0700[diff] [blame]14#include "sdm845-v2-camera.dtsi"
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]15
16/ {
17 model = "Qualcomm Technologies, Inc. SDM845 V2";
18 qcom,msm-id = <321 0x20000>;
19};
David Collins36050182017-04-26 11:41:22 -0700[diff] [blame]20
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]21&sdhc_2 {
Subhash Jadavani3497a962017-07-31 13:57:47 -0700[diff] [blame]22 /delete-property/ qcom,sdr104-wa;
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]23};
24
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]25/delete-node/ &apc0_cpr;
26/delete-node/ &apc1_cpr;
27
28&soc {
29 /* CPR controller regulators */
30 apc0_cpr: cprh-ctrl@17dc0000 {
31 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
32 reg = <0x17dc0000 0x4000>,
33 <0x00784000 0x1000>,
34 <0x17840000 0x1000>;
35 reg-names = "cpr_ctrl", "fuse_base", "saw";
36 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
37 clock-names = "core_clk";
38 qcom,cpr-ctrl-name = "apc0";
39 qcom,cpr-controller-id = <0>;
40
41 qcom,cpr-sensor-time = <1000>;
42 qcom,cpr-loop-time = <5000000>;
43 qcom,cpr-idle-cycles = <15>;
44 qcom,cpr-up-down-delay-time = <3000>;
45 qcom,cpr-step-quot-init-min = <11>;
46 qcom,cpr-step-quot-init-max = <12>;
47 qcom,cpr-count-mode = <0>; /* All at once */
48 qcom,cpr-count-repeat = <20>;
49 qcom,cpr-down-error-step-limit = <1>;
50 qcom,cpr-up-error-step-limit = <1>;
51 qcom,cpr-corner-switch-delay-time = <1042>;
52 qcom,cpr-voltage-settling-time = <1760>;
53 qcom,cpr-reset-step-quot-loop-en;
54
55 qcom,voltage-step = <4000>;
56 qcom,voltage-base = <352000>;
57 qcom,cpr-saw-use-unit-mV;
58
59 qcom,saw-avs-ctrl = <0x101C031>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]60 qcom,saw-avs-limit = <0x3E803E8>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]61
62 qcom,cpr-enable;
63 qcom,cpr-hw-closed-loop;
64
65 qcom,cpr-panic-reg-addr-list =
66 <0x17dc3a84 0x17dc3a88 0x17840c18>;
67 qcom,cpr-panic-reg-name-list =
68 "APSS_SILVER_CPRH_STATUS_0",
69 "APSS_SILVER_CPRH_STATUS_1",
70 "SILVER_SAW4_PMIC_STS";
71
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]72 qcom,cpr-aging-ref-voltage = <1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]73 vdd-supply = <&pm8998_s13>;
74
75 thread@0 {
76 qcom,cpr-thread-id = <0>;
77 qcom,cpr-consecutive-up = <0>;
78 qcom,cpr-consecutive-down = <0>;
79 qcom,cpr-up-threshold = <2>;
80 qcom,cpr-down-threshold = <2>;
81
82 apc0_pwrcl_vreg: regulator {
83 regulator-name = "apc0_pwrcl_corner";
84 regulator-min-microvolt = <1>;
85 regulator-max-microvolt = <18>;
86
87 qcom,cpr-fuse-corners = <4>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]88 qcom,cpr-fuse-combos = <24>;
89 qcom,cpr-speed-bins = <3>;
90 qcom,cpr-speed-bin-corners = <18 18 18>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]91 qcom,cpr-corners = <18>;
92
93 qcom,cpr-corner-fmax-map = <6 12 15 18>;
94
95 qcom,cpr-voltage-ceiling =
96 <828000 828000 828000 828000 828000
97 828000 828000 828000 828000 828000
98 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]99 932000 1000000 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]100
101 qcom,cpr-voltage-floor =
102 <568000 568000 568000 568000 568000
103 568000 568000 568000 568000 568000
104 568000 568000 568000 568000 568000
105 568000 568000 568000>;
106
107 qcom,cpr-floor-to-ceiling-max-range =
108 <32000 32000 32000 32000 32000
109 32000 32000 32000 32000 32000
110 32000 32000 32000 32000 32000
111 32000 40000 40000>;
112
113 qcom,corner-frequencies =
114 <300000000 403200000 480000000
115 576000000 652800000 748800000
116 825600000 902400000 979200000
117 1056000000 1132800000 1228800000
118 1324800000 1420800000 1516800000
119 1612800000 1689600000 1766400000>;
120
121 qcom,cpr-ro-scaling-factor =
122 <2594 2795 2576 2761 2469 2673 2198
123 2553 3188 3255 3191 2962 3055 2984
124 2043 2947>,
125 <2594 2795 2576 2761 2469 2673 2198
126 2553 3188 3255 3191 2962 3055 2984
127 2043 2947>,
128 <2259 2389 2387 2531 2294 2464 2218
129 2476 2525 2855 2817 2836 2740 2490
130 1950 2632>,
131 <2259 2389 2387 2531 2294 2464 2218
132 2476 2525 2855 2817 2836 2740 2490
133 1950 2632>;
134
135 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]136 /* Speed bin 0 */
137 < 0 0 12000 12000>,
138 <(-15000) (-15000) (-3000) (-3000)>,
139 <(-15000) (-15000) (-3000) (-3000)>,
140 <(-15000) (-15000) (-3000) (-3000)>,
141 <(-15000) (-15000) (-3000) (-3000)>,
142 <(-15000) (-15000) (-3000) (-3000)>,
143 <(-15000) (-15000) (-3000) (-3000)>,
144 <(-15000) (-15000) (-3000) (-3000)>,
145 /* Speed bin 1 */
146 < 0 0 12000 12000>,
147 <(-15000) (-15000) (-3000) (-3000)>,
148 <(-15000) (-15000) (-3000) (-3000)>,
149 <(-15000) (-15000) (-3000) (-3000)>,
150 <(-15000) (-15000) (-3000) (-3000)>,
151 <(-15000) (-15000) (-3000) (-3000)>,
152 <(-15000) (-15000) (-3000) (-3000)>,
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]153 <(-15000) (-15000) (-3000) (-3000)>,
154 /* Speed bin 2 */
155 < 0 0 12000 12000>,
156 <(-15000) (-15000) (-3000) (-3000)>,
157 <(-15000) (-15000) (-3000) (-3000)>,
158 <(-15000) (-15000) (-3000) (-3000)>,
159 <(-15000) (-15000) (-3000) (-3000)>,
160 <(-15000) (-15000) (-3000) (-3000)>,
161 <(-15000) (-15000) (-3000) (-3000)>,
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]162 <(-15000) (-15000) (-3000) (-3000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]163
164 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]165 /* Speed bin 0 */
166 < 0 0 12000 10000>,
167 <(-15000) (-15000) (-3000) (-5000)>,
168 <(-15000) (-15000) (-3000) (-5000)>,
169 <(-15000) (-15000) (-3000) (-5000)>,
170 <(-15000) (-15000) (-3000) (-5000)>,
171 <(-15000) (-15000) (-3000) (-5000)>,
172 <(-15000) (-15000) (-3000) (-5000)>,
173 <(-15000) (-15000) (-3000) (-5000)>,
174 /* Speed bin 1 */
175 < 0 0 12000 10000>,
176 <(-15000) (-15000) (-3000) (-5000)>,
177 <(-15000) (-15000) (-3000) (-5000)>,
178 <(-15000) (-15000) (-3000) (-5000)>,
179 <(-15000) (-15000) (-3000) (-5000)>,
180 <(-15000) (-15000) (-3000) (-5000)>,
181 <(-15000) (-15000) (-3000) (-5000)>,
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]182 <(-15000) (-15000) (-3000) (-5000)>,
183 /* Speed bin 2 */
184 < 0 0 12000 10000>,
185 <(-15000) (-15000) (-3000) (-5000)>,
186 <(-15000) (-15000) (-3000) (-5000)>,
187 <(-15000) (-15000) (-3000) (-5000)>,
188 <(-15000) (-15000) (-3000) (-5000)>,
189 <(-15000) (-15000) (-3000) (-5000)>,
190 <(-15000) (-15000) (-3000) (-5000)>,
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]191 <(-15000) (-15000) (-3000) (-5000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]192
193 qcom,allow-voltage-interpolation;
194 qcom,allow-quotient-interpolation;
195 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
196
197 qcom,cpr-aging-max-voltage-adjustment = <15000>;
198 qcom,cpr-aging-ref-corner = <18>;
199 qcom,cpr-aging-ro-scaling-factor = <1620>;
200 qcom,allow-aging-voltage-adjustment =
201 /* Speed bin 0 */
202 <0 1 1 1 1 1 1 1>,
203 /* Speed bin 1 */
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]204 <0 1 1 1 1 1 1 1>,
205 /* Speed bin 2 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]206 <0 1 1 1 1 1 1 1>;
207 qcom,allow-aging-open-loop-voltage-adjustment =
208 <1>;
209 };
210 };
211
212 thread@1 {
213 qcom,cpr-thread-id = <1>;
214 qcom,cpr-consecutive-up = <0>;
215 qcom,cpr-consecutive-down = <0>;
216 qcom,cpr-up-threshold = <2>;
217 qcom,cpr-down-threshold = <2>;
218
219 apc0_l3_vreg: regulator {
220 regulator-name = "apc0_l3_corner";
221 regulator-min-microvolt = <1>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]222 regulator-max-microvolt = <15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]223
224 qcom,cpr-fuse-corners = <4>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]225 qcom,cpr-fuse-combos = <24>;
226 qcom,cpr-speed-bins = <3>;
227 qcom,cpr-speed-bin-corners = <14 15 15>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]228 qcom,cpr-corners =
229 /* Speed bin 0 */
230 <14 14 14 14 14 14 14 14>,
231 /* Speed bin 1 */
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]232 <15 15 15 15 15 15 15 15>,
233 /* Speed bin 2 */
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]234 <15 15 15 15 15 15 15 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]235
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]236 qcom,cpr-corner-fmax-map =
237 /* Speed bin 0 */
238 <4 8 11 14>,
239 /* Speed bin 1 */
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]240 <4 8 11 15>,
241 /* Speed bin 2 */
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]242 <4 8 11 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]243
244 qcom,cpr-voltage-ceiling =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]245 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]246 <828000 828000 828000 828000 828000
247 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]248 828000 932000 932000 1000000>,
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]249 /* Speed bin 1 */
250 <828000 828000 828000 828000 828000
251 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]252 828000 932000 932000 1000000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]253 1000000>,
254 /* Speed bin 2 */
255 <828000 828000 828000 828000 828000
256 828000 828000 828000 828000 828000
257 828000 932000 932000 1000000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]258 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]259
260 qcom,cpr-voltage-floor =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]261 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]262 <568000 568000 568000 568000 568000
263 568000 568000 568000 568000 568000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]264 568000 568000 568000 568000>,
265 /* Speed bin 1 */
266 <568000 568000 568000 568000 568000
267 568000 568000 568000 568000 568000
268 568000 568000 568000 568000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]269 568000>,
270 /* Speed bin 2 */
271 <568000 568000 568000 568000 568000
272 568000 568000 568000 568000 568000
273 568000 568000 568000 568000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]274 568000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]275
276 qcom,cpr-floor-to-ceiling-max-range =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]277 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]278 <32000 32000 32000 32000 32000
279 32000 32000 32000 32000 32000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]280 32000 32000 32000 40000>,
281 /* Speed bin 1 */
282 <32000 32000 32000 32000 32000
283 32000 32000 32000 32000 32000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]284 32000 32000 32000 40000 40000>,
285 /* Speed bin 2 */
286 <32000 32000 32000 32000 32000
287 32000 32000 32000 32000 32000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]288 32000 32000 32000 40000 40000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]289
290 qcom,corner-frequencies =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]291 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]292 <300000000 403200000 480000000
293 576000000 652800000 748800000
294 844800000 940800000 1036800000
295 1132800000 1209600000 1305600000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]296 1401600000 1478400000>,
297 /* Speed bin 1 */
298 <300000000 403200000 480000000
299 576000000 652800000 748800000
300 844800000 940800000 1036800000
301 1132800000 1209600000 1305600000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]302 1401600000 1497600000 1593600000>,
303 /* Speed bin 2 */
304 <300000000 403200000 480000000
305 576000000 652800000 748800000
306 844800000 940800000 1036800000
307 1132800000 1209600000 1305600000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700[diff] [blame]308 1401600000 1497600000 1593600000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]309
310 qcom,cpr-ro-scaling-factor =
311 <2857 3056 2828 2952 2699 2796 2447
312 2631 2630 2579 2244 3343 3287 3137
313 3164 2656>,
314 <2857 3056 2828 2952 2699 2796 2447
315 2631 2630 2579 2244 3343 3287 3137
316 3164 2656>,
317 <2439 2577 2552 2667 2461 2577 2394
318 2536 2132 2307 2191 2903 2838 2912
319 2501 2095>,
320 <2439 2577 2552 2667 2461 2577 2394
321 2536 2132 2307 2191 2903 2838 2912
322 2501 2095>;
323
324 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]325 /* Speed bin 0 */
326 < 8000 16000 16000 12000>,
327 < (-7000) 1000 1000 (-3000)>,
328 < (-7000) 1000 1000 (-3000)>,
329 < (-7000) 1000 1000 (-3000)>,
330 < (-7000) 1000 1000 (-3000)>,
331 < (-7000) 1000 1000 (-3000)>,
332 < (-7000) 1000 1000 (-3000)>,
333 < (-7000) 1000 1000 (-3000)>,
334 /* Speed bin 1 */
335 < 8000 16000 16000 12000>,
336 < (-7000) 1000 1000 (-3000)>,
337 < (-7000) 1000 1000 (-3000)>,
338 < (-7000) 1000 1000 (-3000)>,
339 < (-7000) 1000 1000 (-3000)>,
340 < (-7000) 1000 1000 (-3000)>,
341 < (-7000) 1000 1000 (-3000)>,
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]342 < (-7000) 1000 1000 (-3000)>,
343 /* Speed bin 2 */
344 < 8000 16000 16000 12000>,
345 < (-7000) 1000 1000 (-3000)>,
346 < (-7000) 1000 1000 (-3000)>,
347 < (-7000) 1000 1000 (-3000)>,
348 < (-7000) 1000 1000 (-3000)>,
349 < (-7000) 1000 1000 (-3000)>,
350 < (-7000) 1000 1000 (-3000)>,
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]351 < (-7000) 1000 1000 (-3000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]352
353 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]354 /* Speed bin 0 */
355 < 6000 14000 16000 12000>,
356 < (-9000) (-1000) 1000 (-3000)>,
357 < (-9000) (-1000) 1000 (-3000)>,
358 < (-9000) (-1000) 1000 (-3000)>,
359 < (-9000) (-1000) 1000 (-3000)>,
360 < (-9000) (-1000) 1000 (-3000)>,
361 < (-9000) (-1000) 1000 (-3000)>,
362 < (-9000) (-1000) 1000 (-3000)>,
363 /* Speed bin 1 */
364 < 6000 14000 16000 12000>,
365 < (-9000) (-1000) 1000 (-3000)>,
366 < (-9000) (-1000) 1000 (-3000)>,
367 < (-9000) (-1000) 1000 (-3000)>,
368 < (-9000) (-1000) 1000 (-3000)>,
369 < (-9000) (-1000) 1000 (-3000)>,
370 < (-9000) (-1000) 1000 (-3000)>,
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]371 < (-9000) (-1000) 1000 (-3000)>,
372 /* Speed bin 2 */
373 < 6000 14000 16000 12000>,
374 < (-9000) (-1000) 1000 (-3000)>,
375 < (-9000) (-1000) 1000 (-3000)>,
376 < (-9000) (-1000) 1000 (-3000)>,
377 < (-9000) (-1000) 1000 (-3000)>,
378 < (-9000) (-1000) 1000 (-3000)>,
379 < (-9000) (-1000) 1000 (-3000)>,
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]380 < (-9000) (-1000) 1000 (-3000)>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]381
382 qcom,allow-voltage-interpolation;
383 qcom,allow-quotient-interpolation;
384 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
385
386 qcom,cpr-aging-max-voltage-adjustment = <15000>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]387 qcom,cpr-aging-ref-corner = <14 15 15>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]388 qcom,cpr-aging-ro-scaling-factor = <1620>;
389 qcom,allow-aging-voltage-adjustment =
390 /* Speed bin 0 */
391 <0 1 1 1 1 1 1 1>,
392 /* Speed bin 1 */
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]393 <0 1 1 1 1 1 1 1>,
394 /* Speed bin 2 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]395 <0 1 1 1 1 1 1 1>;
396 qcom,allow-aging-open-loop-voltage-adjustment =
397 <1>;
398 };
399 };
400 };
401
402 apc1_cpr: cprh-ctrl@17db0000 {
403 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
404 reg = <0x17db0000 0x4000>,
405 <0x00784000 0x1000>,
406 <0x17830000 0x1000>;
407 reg-names = "cpr_ctrl", "fuse_base", "saw";
408 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
409 clock-names = "core_clk";
410 qcom,cpr-ctrl-name = "apc1";
411 qcom,cpr-controller-id = <1>;
412
413 qcom,cpr-sensor-time = <1000>;
414 qcom,cpr-loop-time = <5000000>;
415 qcom,cpr-idle-cycles = <15>;
416 qcom,cpr-up-down-delay-time = <3000>;
417 qcom,cpr-step-quot-init-min = <9>;
418 qcom,cpr-step-quot-init-max = <14>;
419 qcom,cpr-count-mode = <0>; /* All at once */
420 qcom,cpr-count-repeat = <20>;
421 qcom,cpr-down-error-step-limit = <1>;
422 qcom,cpr-up-error-step-limit = <1>;
423 qcom,cpr-corner-switch-delay-time = <1042>;
424 qcom,cpr-voltage-settling-time = <1760>;
425 qcom,cpr-reset-step-quot-loop-en;
426
427 qcom,apm-threshold-voltage = <800000>;
428 qcom,apm-crossover-voltage = <880000>;
429 qcom,mem-acc-threshold-voltage = <852000>;
430 qcom,mem-acc-crossover-voltage = <852000>;
431
432 qcom,voltage-step = <4000>;
433 qcom,voltage-base = <352000>;
434 qcom,cpr-saw-use-unit-mV;
435
436 qcom,saw-avs-ctrl = <0x101C031>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]437 qcom,saw-avs-limit = <0x4880488>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]438
439 qcom,cpr-enable;
440 qcom,cpr-hw-closed-loop;
441
442 qcom,cpr-panic-reg-addr-list =
443 <0x17db3a84 0x17830c18>;
444 qcom,cpr-panic-reg-name-list =
445 "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
446
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]447 qcom,cpr-aging-ref-voltage = <1160000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]448 vdd-supply = <&pm8998_s12>;
449
450 thread@0 {
451 qcom,cpr-thread-id = <0>;
452 qcom,cpr-consecutive-up = <0>;
453 qcom,cpr-consecutive-down = <0>;
454 qcom,cpr-up-threshold = <2>;
455 qcom,cpr-down-threshold = <2>;
456
457 apc1_perfcl_vreg: regulator {
458 regulator-name = "apc1_perfcl_corner";
459 regulator-min-microvolt = <1>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]460 regulator-max-microvolt = <35>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]461
462 qcom,cpr-fuse-corners = <5>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]463 qcom,cpr-fuse-combos = <24>;
464 qcom,cpr-speed-bins = <3>;
465 qcom,cpr-speed-bin-corners = <28 31 33>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]466 qcom,cpr-corners =
467 /* Speed bin 0 */
468 <28 28 28 28 28 28 28 28>,
469 /* Speed bin 1 */
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]470 <31 31 31 31 31 31 31 31>,
471 /* Speed bin 2 */
472 <33 33 33 33 33 33 33 33>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]473
474 qcom,cpr-corner-fmax-map =
475 /* Speed bin 0 */
476 <7 14 22 27 28>,
477 /* Speed bin 1 */
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]478 <7 14 22 27 31>,
479 /* Speed bin 2 */
480 <7 14 22 30 33>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]481
482 qcom,cpr-voltage-ceiling =
483 /* Speed bin 0 */
484 <828000 828000 828000 828000 828000
485 828000 828000 828000 828000 828000
486 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]487 828000 828000 828000 932000 932000
488 932000 932000 1104000 1104000 1104000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]489 1104000 1160000 1160000>,
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]490 /* Speed bin 1 */
491 <828000 828000 828000 828000 828000
492 828000 828000 828000 828000 828000
493 828000 828000 828000 828000 828000
David Collins4d7ab0e2017-08-22 14:23:47 -0700[diff] [blame]494 828000 828000 828000 932000 932000
495 932000 932000 1104000 1104000 1104000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]496 1104000 1160000 1160000 1160000 1160000
497 1160000>,
498 /* Speed bin 2 */
499 <828000 828000 828000 828000 828000
500 828000 828000 828000 828000 828000
501 828000 828000 828000 828000 828000
502 828000 828000 828000 932000 932000
503 932000 932000 1104000 1104000 1104000
504 1104000 1160000 1160000 1160000 1160000
505 1160000 1160000 1160000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]506
507 qcom,cpr-voltage-floor =
508 /* Speed bin 0 */
509 <568000 568000 568000 568000 568000
510 568000 568000 568000 568000 568000
511 568000 568000 568000 568000 568000
512 568000 568000 568000 568000 568000
513 568000 568000 568000 568000 568000
514 568000 568000 568000>,
515 /* Speed bin 1 */
516 <568000 568000 568000 568000 568000
517 568000 568000 568000 568000 568000
518 568000 568000 568000 568000 568000
519 568000 568000 568000 568000 568000
520 568000 568000 568000 568000 568000
521 568000 568000 568000 568000 568000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]522 568000>,
523 /* Speed bin 2 */
524 <568000 568000 568000 568000 568000
525 568000 568000 568000 568000 568000
526 568000 568000 568000 568000 568000
527 568000 568000 568000 568000 568000
528 568000 568000 568000 568000 568000
529 568000 568000 568000 568000 568000
530 568000 568000 568000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]531
532 qcom,cpr-floor-to-ceiling-max-range =
533 /* Speed bin 0 */
534 <32000 32000 32000 32000 32000
535 32000 32000 32000 32000 32000
536 32000 32000 32000 32000 32000
537 32000 32000 32000 32000 32000
538 32000 32000 32000 32000 32000
539 32000 32000 32000>,
540 /* Speed bin 1 */
541 <32000 32000 32000 32000 32000
542 32000 32000 32000 32000 32000
543 32000 32000 32000 32000 32000
544 32000 32000 32000 32000 32000
545 32000 32000 32000 32000 32000
546 32000 32000 40000 40000 40000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]547 40000>,
548 /* Speed bin 2 */
549 <32000 32000 32000 32000 32000
550 32000 32000 32000 32000 32000
551 32000 32000 32000 32000 32000
552 32000 32000 32000 32000 32000
553 32000 32000 32000 32000 32000
554 32000 32000 40000 40000 40000
555 40000 40000 40000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]556
557 qcom,corner-frequencies =
558 /* Speed bin 0 */
559 <300000000 403200000 480000000
560 576000000 652800000 748800000
561 825600000 902400000 979200000
562 1056000000 1132800000 1209600000
563 1286400000 1363200000 1459200000
564 1536000000 1612800000 1689600000
565 1766400000 1843200000 1920000000
566 1996800000 2092800000 2169600000
567 2246400000 2323200000 2400000000
568 2400000000>,
569 /* Speed bin 1 */
570 <300000000 403200000 480000000
571 576000000 652800000 748800000
572 825600000 902400000 979200000
573 1056000000 1132800000 1209600000
574 1286400000 1363200000 1459200000
575 1536000000 1612800000 1689600000
576 1766400000 1843200000 1920000000
577 1996800000 2092800000 2169600000
578 2246400000 2323200000 2400000000
David Collinsae2591d2017-08-22 14:15:14 -0700[diff] [blame]579 2476800000 2553600000 2649600000
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]580 2707200000>,
581 /* Speed bin 2 */
582 <300000000 403200000 480000000
583 576000000 652800000 748800000
584 825600000 902400000 979200000
585 1056000000 1132800000 1209600000
586 1286400000 1363200000 1459200000
587 1536000000 1612800000 1689600000
588 1766400000 1843200000 1920000000
589 1996800000 2092800000 2169600000
590 2246400000 2323200000 2400000000
591 2476800000 2553600000 2649600000
592 2707200000 2726400000 2745600000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]593
594 qcom,cpr-ro-scaling-factor =
595 <2857 3056 2828 2952 2699 2796 2447
596 2631 2630 2579 2244 3343 3287 3137
597 3164 2656>,
598 <2857 3056 2828 2952 2699 2796 2447
599 2631 2630 2579 2244 3343 3287 3137
600 3164 2656>,
601 <2086 2208 2273 2408 2203 2327 2213
602 2340 1755 2039 2049 2474 2437 2618
603 2003 1675>,
604 <2086 2208 2273 2408 2203 2327 2213
605 2340 1755 2039 2049 2474 2437 2618
606 2003 1675>,
607 <2086 2208 2273 2408 2203 2327 2213
608 2340 1755 2039 2049 2474 2437 2618
609 2003 1675>;
610
611 qcom,cpr-open-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]612 /* Speed bin 0 */
613 < 8000 8000 8000 0 0>,
614 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
615 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
616 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
617 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
618 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
619 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
620 < (-7000) (-7000) (-7000) (-15000) (-15000)>,
621 /* Speed bin 1 */
622 < 8000 8000 8000 0 16000>,
623 < (-7000) (-7000) (-7000) (-15000) 1000>,
624 < (-7000) (-7000) (-7000) (-15000) 1000>,
625 < (-7000) (-7000) (-7000) (-15000) 1000>,
626 < (-7000) (-7000) (-7000) (-15000) 1000>,
627 < (-7000) (-7000) (-7000) (-15000) 1000>,
628 < (-7000) (-7000) (-7000) (-15000) 1000>,
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]629 < (-7000) (-7000) (-7000) (-15000) 1000>,
630 /* Speed bin 2 */
631 < 8000 8000 8000 0 16000>,
632 < (-7000) (-7000) (-7000) (-15000) 1000>,
633 < (-7000) (-7000) (-7000) (-15000) 1000>,
634 < (-7000) (-7000) (-7000) (-15000) 1000>,
635 < (-7000) (-7000) (-7000) (-15000) 1000>,
636 < (-7000) (-7000) (-7000) (-15000) 1000>,
637 < (-7000) (-7000) (-7000) (-15000) 1000>,
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]638 < (-7000) (-7000) (-7000) (-15000) 1000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]639
640 qcom,cpr-closed-loop-voltage-fuse-adjustment =
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]641 /* Speed bin 0 */
642 < 6000 6000 8000 0 0>,
643 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
644 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
645 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
646 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
647 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
648 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
649 < (-9000) (-9000) (-7000) (-15000) (-15000)>,
650 /* Speed bin 1 */
651 < 6000 6000 8000 0 16000>,
652 < (-9000) (-9000) (-7000) (-15000) 1000>,
653 < (-9000) (-9000) (-7000) (-15000) 1000>,
654 < (-9000) (-9000) (-7000) (-15000) 1000>,
655 < (-9000) (-9000) (-7000) (-15000) 1000>,
656 < (-9000) (-9000) (-7000) (-15000) 1000>,
657 < (-9000) (-9000) (-7000) (-15000) 1000>,
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]658 < (-9000) (-9000) (-7000) (-15000) 1000>,
659 /* Speed bin 2 */
660 < 6000 6000 8000 0 16000>,
661 < (-9000) (-9000) (-7000) (-15000) 1000>,
662 < (-9000) (-9000) (-7000) (-15000) 1000>,
663 < (-9000) (-9000) (-7000) (-15000) 1000>,
664 < (-9000) (-9000) (-7000) (-15000) 1000>,
665 < (-9000) (-9000) (-7000) (-15000) 1000>,
666 < (-9000) (-9000) (-7000) (-15000) 1000>,
David Collins85d44cb2017-09-11 17:45:16 -0700[diff] [blame]667 < (-9000) (-9000) (-7000) (-15000) 1000>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]668
669 qcom,allow-voltage-interpolation;
670 qcom,allow-quotient-interpolation;
671 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
672
673 qcom,cpr-aging-max-voltage-adjustment = <15000>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]674 qcom,cpr-aging-ref-corner = <27 31 33>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]675 qcom,cpr-aging-ro-scaling-factor = <1700>;
676 qcom,allow-aging-voltage-adjustment =
677 /* Speed bin 0 */
678 <0 1 1 1 1 1 1 1>,
679 /* Speed bin 1 */
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]680 <0 1 1 1 1 1 1 1>,
681 /* Speed bin 2 */
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]682 <0 1 1 1 1 1 1 1>;
683 qcom,allow-aging-open-loop-voltage-adjustment =
684 <1>;
685 };
686 };
687 };
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]688
689 gpu_gx_domain_addr: syscon@0x5091508 {
690 compatible = "syscon";
691 reg = <0x5091508 0x4>;
692 };
693
694 gpu_gx_sw_reset: syscon@0x5091008 {
695 compatible = "syscon";
696 reg = <0x5091008 0x4>;
697 };
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]698};
699
Kyle Yanf248e352017-09-14 11:15:58 -0700[diff] [blame]700&pil_modem {
701 qcom,mss_pdc_offset = <9>;
702};
703
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]704/* VDD_APC0 */
705&pm8998_s13 {
706 regulator-min-microvolt = <568000>;
707 regulator-max-microvolt = <1000000>;
708};
709
710/* VDD_APC1 */
711&pm8998_s12 {
712 regulator-min-microvolt = <568000>;
David Collinsd6f48992017-09-12 15:52:19 -0700[diff] [blame^]713 regulator-max-microvolt = <1160000>;
David Collinsfc666ff2017-08-31 10:46:18 -0700[diff] [blame]714};
715
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]716&clock_cpucc {
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]717 compatible = "qcom,clk-cpu-osm-v2";
718
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]719 vdd-l3-supply = <&apc0_l3_vreg>;
720 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]721 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
722
723 qcom,l3-speedbin0-v0 =
724 < 300000000 0x000c000f 0x00002020 0x1 1 >,
725 < 403200000 0x500c0115 0x00002020 0x1 2 >,
726 < 480000000 0x50140219 0x00002020 0x1 3 >,
727 < 576000000 0x5014031e 0x00002020 0x1 4 >,
728 < 652800000 0x401c0422 0x00002020 0x1 5 >,
729 < 748800000 0x401c0527 0x00002020 0x1 6 >,
730 < 844800000 0x4024062c 0x00002323 0x2 7 >,
731 < 940800000 0x40240731 0x00002727 0x2 8 >,
732 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
733 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
734 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
735 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
736 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
737 < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
738
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]739 qcom,l3-speedbin1-v0 =
740 < 300000000 0x000c000f 0x00002020 0x1 1 >,
741 < 403200000 0x500c0115 0x00002020 0x1 2 >,
742 < 480000000 0x50140219 0x00002020 0x1 3 >,
743 < 576000000 0x5014031e 0x00002020 0x1 4 >,
744 < 652800000 0x401c0422 0x00002020 0x1 5 >,
745 < 748800000 0x401c0527 0x00002020 0x1 6 >,
746 < 844800000 0x4024062c 0x00002323 0x2 7 >,
747 < 940800000 0x40240731 0x00002727 0x2 8 >,
748 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
749 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
750 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
751 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
752 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
753 < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
754 < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
755
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]756 qcom,pwrcl-speedbin0-v0 =
757 < 300000000 0x000c000f 0x00002020 0x1 1 >,
758 < 403200000 0x500c0115 0x00002020 0x1 2 >,
759 < 480000000 0x50140219 0x00002020 0x1 3 >,
760 < 576000000 0x5014031e 0x00002020 0x1 4 >,
761 < 652800000 0x401c0422 0x00002020 0x1 5 >,
762 < 748800000 0x401c0527 0x00002020 0x1 6 >,
763 < 825600000 0x401c062b 0x00002222 0x1 7 >,
764 < 902400000 0x4024072f 0x00002626 0x1 8 >,
765 < 979200000 0x40240833 0x00002929 0x1 9 >,
766 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
767 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
768 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
769 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
770 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
771 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
772 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
773 < 1689600000 0x40441058 0x00004646 0x2 17 >,
774 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
775
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]776 qcom,pwrcl-speedbin1-v0 =
777 < 300000000 0x000c000f 0x00002020 0x1 1 >,
778 < 403200000 0x500c0115 0x00002020 0x1 2 >,
779 < 480000000 0x50140219 0x00002020 0x1 3 >,
780 < 576000000 0x5014031e 0x00002020 0x1 4 >,
781 < 652800000 0x401c0422 0x00002020 0x1 5 >,
782 < 748800000 0x401c0527 0x00002020 0x1 6 >,
783 < 825600000 0x401c062b 0x00002222 0x1 7 >,
784 < 902400000 0x4024072f 0x00002626 0x1 8 >,
785 < 979200000 0x40240833 0x00002929 0x1 9 >,
786 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
787 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
788 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
789 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
790 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
791 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
792 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
793 < 1689600000 0x40441058 0x00004646 0x2 17 >,
794 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
795
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]796 qcom,perfcl-speedbin0-v0 =
797 < 300000000 0x000c000f 0x00002020 0x1 1 >,
798 < 403200000 0x500c0115 0x00002020 0x1 2 >,
799 < 480000000 0x50140219 0x00002020 0x1 3 >,
800 < 576000000 0x5014031e 0x00002020 0x1 4 >,
801 < 652800000 0x401c0422 0x00002020 0x1 5 >,
802 < 748800000 0x401c0527 0x00002020 0x1 6 >,
803 < 825600000 0x401c062b 0x00002222 0x1 7 >,
804 < 902400000 0x4024072f 0x00002626 0x1 8 >,
805 < 979200000 0x40240833 0x00002929 0x1 9 >,
806 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
807 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
808 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
809 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
810 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
811 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
812 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
813 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
814 < 1689600000 0x40441158 0x00004646 0x2 18 >,
815 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
816 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
817 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
818 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
819 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
820 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
821 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
822 < 2323200000 0x40541979 0x00006161 0x2 26 >,
823 < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
824
825 qcom,perfcl-speedbin1-v0 =
826 < 300000000 0x000c000f 0x00002020 0x1 1 >,
827 < 403200000 0x500c0115 0x00002020 0x1 2 >,
828 < 480000000 0x50140219 0x00002020 0x1 3 >,
829 < 576000000 0x5014031e 0x00002020 0x1 4 >,
830 < 652800000 0x401c0422 0x00002020 0x1 5 >,
831 < 748800000 0x401c0527 0x00002020 0x1 6 >,
832 < 825600000 0x401c062b 0x00002222 0x1 7 >,
833 < 902400000 0x4024072f 0x00002626 0x1 8 >,
834 < 979200000 0x40240833 0x00002929 0x1 9 >,
835 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
836 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
837 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
838 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
839 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
840 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
841 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
842 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
843 < 1689600000 0x40441158 0x00004646 0x2 18 >,
844 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
845 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
846 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
847 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
848 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
849 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
850 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
851 < 2323200000 0x40541979 0x00006161 0x2 26 >,
852 < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
853 < 2476800000 0x40541b81 0x00006767 0x2 28 >,
854 < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
Deepak Katragadda1a183252017-08-21 12:44:34 -0700[diff] [blame]855 < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
856 < 2745600000 0x40511e8f 0x00007272 0x2 31 >;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]857
858 qcom,l3-memacc-level-vc-bin0 = <8 13>;
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700[diff] [blame]859 qcom,l3-memacc-level-vc-bin1 = <8 13>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]860
861 qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
Deepak Katragadda401fcb92017-08-21 16:30:15 -0700[diff] [blame]862 qcom,pwrcl-memacc-level-vc-bin1 = <12 16>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]863
864 qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
865 qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]866};
867
Tony Truong80258d62017-08-16 11:41:33 -0700[diff] [blame]868&pcie1 {
869 qcom,phy-sequence = <0x1804 0x03 0x0
870 0x00dc 0x27 0x0
871 0x0014 0x01 0x0
872 0x0020 0x31 0x0
873 0x0024 0x01 0x0
874 0x0028 0xde 0x0
875 0x002c 0x07 0x0
876 0x0034 0x4c 0x0
877 0x0038 0x06 0x0
878 0x0054 0x18 0x0
879 0x0058 0xb0 0x0
880 0x006c 0x8c 0x0
881 0x0070 0x20 0x0
882 0x0078 0x14 0x0
883 0x007c 0x34 0x0
884 0x00b4 0x06 0x0
885 0x00b8 0x06 0x0
886 0x00c0 0x16 0x0
887 0x00c4 0x16 0x0
888 0x00cc 0x36 0x0
889 0x00d0 0x36 0x0
890 0x00f0 0x05 0x0
891 0x00f8 0x42 0x0
892 0x0100 0x82 0x0
893 0x0108 0x68 0x0
894 0x011c 0x55 0x0
895 0x0120 0x55 0x0
896 0x0124 0x03 0x0
897 0x0128 0xab 0x0
898 0x012c 0xaa 0x0
899 0x0130 0x02 0x0
900 0x0150 0x3f 0x0
901 0x0158 0x3f 0x0
902 0x0178 0x10 0x0
903 0x01cc 0x04 0x0
904 0x01d0 0x30 0x0
905 0x01e0 0x04 0x0
906 0x01e8 0x73 0x0
907 0x01f0 0x1c 0x0
908 0x01fc 0x15 0x0
909 0x021c 0x04 0x0
910 0x0224 0x01 0x0
911 0x0228 0x22 0x0
912 0x022c 0x00 0x0
913 0x0098 0x05 0x0
914 0x080c 0x00 0x0
915 0x0818 0x0d 0x0
916 0x0860 0x01 0x0
917 0x0864 0x3a 0x0
918 0x087c 0x2f 0x0
919 0x08c0 0x09 0x0
920 0x08c4 0x09 0x0
921 0x08c8 0x1a 0x0
922 0x08d0 0x01 0x0
923 0x08d4 0x07 0x0
924 0x08d8 0x31 0x0
925 0x08dc 0x31 0x0
926 0x08e0 0x03 0x0
927 0x08fc 0x02 0x0
928 0x0900 0x01 0x0
929 0x0908 0x12 0x0
930 0x0914 0x25 0x0
931 0x0918 0x00 0x0
932 0x091c 0x05 0x0
933 0x0920 0x01 0x0
934 0x0924 0x26 0x0
935 0x0928 0x12 0x0
936 0x0930 0x04 0x0
937 0x0934 0x04 0x0
938 0x0938 0x09 0x0
939 0x0954 0x15 0x0
940 0x0960 0x32 0x0
941 0x0968 0x7f 0x0
942 0x096c 0x07 0x0
943 0x0978 0x04 0x0
944 0x0980 0x70 0x0
945 0x0984 0x8b 0x0
946 0x0988 0x08 0x0
947 0x098c 0x09 0x0
948 0x0990 0x03 0x0
949 0x0994 0x04 0x0
950 0x0998 0x02 0x0
951 0x099c 0x0c 0x0
952 0x09a4 0x02 0x0
953 0x09c0 0x5c 0x0
954 0x09c4 0x3e 0x0
955 0x09c8 0x3f 0x0
956 0x0a30 0x01 0x0
957 0x0a34 0xa0 0x0
958 0x0a38 0x08 0x0
959 0x0aa4 0x01 0x0
960 0x0aac 0xc3 0x0
961 0x0ab0 0x00 0x0
962 0x0ab8 0x8c 0x0
963 0x0ac0 0x7f 0x0
964 0x0ac4 0x2a 0x0
965 0x0810 0x0c 0x0
966 0x0814 0x00 0x0
967 0x0acc 0x04 0x0
968 0x093c 0x20 0x0
969 0x100c 0x00 0x0
970 0x1018 0x0d 0x0
971 0x1060 0x01 0x0
972 0x1064 0x3a 0x0
973 0x107c 0x2f 0x0
974 0x10c0 0x09 0x0
975 0x10c4 0x09 0x0
976 0x10c8 0x1a 0x0
977 0x10d0 0x01 0x0
978 0x10d4 0x07 0x0
979 0x10d8 0x31 0x0
980 0x10dc 0x31 0x0
981 0x10e0 0x03 0x0
982 0x10fc 0x02 0x0
983 0x1100 0x01 0x0
984 0x1108 0x12 0x0
985 0x1114 0x25 0x0
986 0x1118 0x00 0x0
987 0x111c 0x05 0x0
988 0x1120 0x01 0x0
989 0x1124 0x26 0x0
990 0x1128 0x12 0x0
991 0x1130 0x04 0x0
992 0x1134 0x04 0x0
993 0x1138 0x09 0x0
994 0x1154 0x15 0x0
995 0x1160 0x32 0x0
996 0x1168 0x7f 0x0
997 0x116c 0x07 0x0
998 0x1178 0x04 0x0
999 0x1180 0x70 0x0
1000 0x1184 0x8b 0x0
1001 0x1188 0x08 0x0
1002 0x118c 0x09 0x0
1003 0x1190 0x03 0x0
1004 0x1194 0x04 0x0
1005 0x1198 0x02 0x0
1006 0x119c 0x0c 0x0
1007 0x11a4 0x02 0x0
1008 0x11c0 0x5c 0x0
1009 0x11c4 0x3e 0x0
1010 0x11c8 0x3f 0x0
1011 0x1230 0x01 0x0
1012 0x1234 0xa0 0x0
1013 0x1238 0x08 0x0
1014 0x12a4 0x01 0x0
1015 0x12ac 0xc3 0x0
1016 0x12b0 0x00 0x0
1017 0x12b8 0x8c 0x0
1018 0x12c0 0x7f 0x0
1019 0x12c4 0x2a 0x0
1020 0x1010 0x0c 0x0
1021 0x1014 0x0f 0x0
1022 0x12cc 0x04 0x0
1023 0x113c 0x20 0x0
1024 0x195c 0x3f 0x0
1025 0x1974 0x50 0x0
1026 0x196c 0x9f 0x0
1027 0x182c 0x19 0x0
1028 0x1840 0x07 0x0
1029 0x1854 0x17 0x0
1030 0x1868 0x09 0x0
1031 0x1800 0x00 0x0
1032 0x0aa8 0x01 0x0
1033 0x12a8 0x01 0x0
1034 0x1808 0x01 0x0>;
1035};
1036
Jonathan Avila29bc1972017-08-24 16:49:18 -0700[diff] [blame]1037&devfreq_l3lat_0 {
1038 qcom,core-dev-table =
1039 < 300000 300000000 >,
1040 < 480000 403200000 >,
1041 < 652800 480000000 >,
1042 < 748800 576000000 >,
1043 < 902400 652800000 >,
1044 < 979200 748800000 >,
1045 < 1132800 844800000 >,
1046 < 1228800 940800000 >,
1047 < 1324800 1036800000 >,
1048 < 1420800 1132800000 >,
1049 < 1516800 1209600000 >,
1050 < 1612800 1401600000 >,
1051 < 1689600 1497600000 >,
1052 < 1766400 1593600000 >;
1053};
1054
1055&devfreq_l3lat_4 {
1056 qcom,core-dev-table =
1057 < 300000 300000000 >,
1058 < 825600 576000000 >,
1059 < 1132800 748800000 >,
1060 < 1363200 940800000 >,
1061 < 1689600 1209600000 >,
1062 < 1996800 1401600000 >,
1063 < 2400000 1593600000 >;
1064};
1065
Stephen Boydcbe46a02017-08-02 13:59:31 -0700[diff] [blame]1066&bwmon {
1067 qcom,count-unit = <0x10000>;
1068};
1069
Stephen Boyd31aac5f2017-09-01 09:16:06 -0700[diff] [blame]1070&cpubw {
1071 qcom,bw-tbl =
1072 < MHZ_TO_MBPS(150, 16) >, /* 2288 MB/s */
1073 < MHZ_TO_MBPS(300, 16) >, /* 4577 MB/s */
1074 < MHZ_TO_MBPS(426, 16) >, /* 6500 MB/s */
1075 < MHZ_TO_MBPS(533, 16) >, /* 8132 MB/s */
1076 < MHZ_TO_MBPS(600, 16) >, /* 9155 MB/s */
1077 < MHZ_TO_MBPS(806, 16) >, /* 12298 MB/s */
1078 < MHZ_TO_MBPS(933, 16) >; /* 14236 MB/s */
1079};
1080
1081&devfreq_cpufreq {
1082 mincpubw-cpufreq {
1083 cpu-to-dev-map-4 =
1084 < 1881600 MHZ_TO_MBPS(200, 4) >,
1085 < 2400000 MHZ_TO_MBPS(681, 4) >;
1086 };
1087};
1088
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]1089&clock_gcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]1090 compatible = "qcom,gcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]1091};
1092
1093&clock_camcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]1094 compatible = "qcom,cam_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]1095};
1096
1097&clock_dispcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]1098 compatible = "qcom,dispcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]1099};
1100
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]1101&clock_gpucc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]1102 compatible = "qcom,gpucc-sdm845-v2", "syscon";
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]1103};
1104
1105&clock_gfx {
1106 compatible = "qcom,gfxcc-sdm845-v2";
1107};
1108
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]1109&clock_videocc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame]1110 compatible = "qcom,video_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]1111};
Praneeth Paladugu55381212017-07-05 15:02:44 -0700[diff] [blame]1112
1113&msm_vidc {
1114 qcom,allowed-clock-rates = <100000000 200000000 330000000
1115 404000000 444000000 533000000>;
1116};
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]1117
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]1118&refgen {
1119 status = "ok";
David Collinsd388dd82017-08-15 16:23:21 -0700[diff] [blame]1120 regulator-always-on;
David Collins113cc2772017-06-27 17:26:54 -0700[diff] [blame]1121};
1122
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]1123&spss_utils {
1124 qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
1125 qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
1126 qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
1127};
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]1128
1129&mdss_mdp {
1130 clock-max-rate = <0 0 0 0 430000000 19200000 0>;
Narendra Muppalla86a46a02017-08-17 11:14:37 -0700[diff] [blame]1131 qcom,sde-min-core-ib-kbps = <4800000>;
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]1132};
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1133
1134&energy_costs {
1135 CPU_COST_0: core-cost0 {
1136 busy-cost-data = <
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1137 300000 12
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1138 403200 17
1139 480000 21
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1140 576000 27
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1141 652800 31
1142 748800 37
1143 825600 42
1144 902400 47
1145 979200 52
1146 1056000 57
1147 1132800 62
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1148 1228800 70
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1149 1324800 78
1150 1420800 89
1151 1516800 103
1152 1612800 122
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1153 1689600 141
1154 1766400 160
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1155 >;
1156 idle-cost-data = <
1157 22 18 14 12
1158 >;
1159 };
1160 CPU_COST_1: core-cost1 {
1161 busy-cost-data = <
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1162 300000 189
1163 403200 523
1164 480000 763
1165 576000 1052
1166 652800 1273
1167 748800 1536
1168 825600 1736
1169 902400 1926
1170 979200 2108
1171 1056000 2284
1172 1132800 2456
1173 1209600 2628
1174 1286400 2804
1175 1363200 2992
1176 1459200 3255
1177 1536000 3499
1178 1612800 3786
1179 1689600 4128
1180 1766400 4535
1181 1843200 5019
1182 1920000 5583
1183 1996800 6226
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1184 2092800 7120
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1185 2169600 7876
1186 2246400 8628
1187 2323200 9344
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1188 2400000 10030
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1189 2476800 10806
1190 2553600 12045
1191 2649600 15686
1192 2745600 25586
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1193 >;
1194 idle-cost-data = <
1195 100 80 60 40
1196 >;
1197 };
1198 CLUSTER_COST_0: cluster-cost0 {
1199 busy-cost-data = <
1200 300000 3
1201 403200 4
1202 480000 4
1203 576000 4
1204 652800 5
1205 748800 5
1206 825600 6
1207 902400 7
1208 979200 7
1209 1056000 8
1210 1132800 9
1211 1228800 9
1212 1324800 10
1213 1420800 11
1214 1516800 12
1215 1612800 13
1216 1689600 15
1217 1766400 17
1218 >;
1219 idle-cost-data = <
1220 4 3 2 1
1221 >;
1222 };
1223 CLUSTER_COST_1: cluster-cost1 {
1224 busy-cost-data = <
1225 300000 24
1226 403200 24
1227 480000 25
1228 576000 25
1229 652800 26
1230 748800 27
1231 825600 28
1232 902400 29
1233 979200 30
1234 1056000 32
1235 1132800 34
1236 1209600 37
1237 1286400 40
1238 1363200 45
1239 1459200 50
1240 1536000 57
1241 1612800 64
1242 1689600 74
1243 1766400 84
1244 1843200 96
1245 1920000 106
1246 1996800 113
1247 2092800 120
1248 2169600 125
1249 2246400 127
1250 2323200 130
1251 2400000 135
1252 2476800 140
1253 2553600 145
Puja Gupta346e399c2017-09-06 14:32:42 -0700[diff] [blame]1254 2649600 150
1255 2745600 155
Joonwoo Parkf3f7dac2017-08-17 16:02:29 -0700[diff] [blame]1256 >;
1257 idle-cost-data = <
1258 4 3 2 1
1259 >;
1260 };
1261};
Vicky Wallaceddf4fad2017-08-03 20:15:55 -0700[diff] [blame]1262
1263&gpu_gx_gdsc {
1264 domain-addr = <&gpu_gx_domain_addr>;
1265 sw-reset = <&gpu_gx_sw_reset>;
1266 qcom,reset-aon-logic;
1267};
Lokesh Batra835f0162017-08-01 11:55:53 -0700[diff] [blame]1268
1269/* GPU overrides */
1270&msm_gpu {
1271 /* Updated chip ID */
1272 qcom,chipid = <0x06030001>;
1273 qcom,initial-pwrlevel = <5>;
1274
1275 qcom,gpu-pwrlevels {
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1278
1279 compatible = "qcom,gpu-pwrlevels";
1280
1281 qcom,gpu-pwrlevel@0 {
1282 reg = <0>;
1283 qcom,gpu-freq = <675000000>;
1284 qcom,bus-freq = <12>;
1285 qcom,bus-min = <10>;
1286 qcom,bus-max = <12>;
1287 };
1288
1289 qcom,gpu-pwrlevel@1 {
1290 reg = <1>;
1291 qcom,gpu-freq = <596000000>;
1292 qcom,bus-freq = <10>;
1293 qcom,bus-min = <9>;
1294 qcom,bus-max = <11>;
1295 };
1296
1297 qcom,gpu-pwrlevel@2 {
1298 reg = <2>;
1299 qcom,gpu-freq = <520000000>;
1300 qcom,bus-freq = <9>;
1301 qcom,bus-min = <8>;
1302 qcom,bus-max = <10>;
1303 };
1304
1305 qcom,gpu-pwrlevel@3 {
1306 reg = <3>;
1307 qcom,gpu-freq = <414000000>;
1308 qcom,bus-freq = <8>;
1309 qcom,bus-min = <7>;
1310 qcom,bus-max = <9>;
1311 };
1312
1313 qcom,gpu-pwrlevel@4 {
1314 reg = <4>;
1315 qcom,gpu-freq = <342000000>;
1316 qcom,bus-freq = <6>;
1317 qcom,bus-min = <5>;
1318 qcom,bus-max = <7>;
1319 };
1320
1321 qcom,gpu-pwrlevel@5 {
1322 reg = <5>;
1323 qcom,gpu-freq = <257000000>;
1324 qcom,bus-freq = <4>;
1325 qcom,bus-min = <3>;
1326 qcom,bus-max = <5>;
1327 };
1328
1329 qcom,gpu-pwrlevel@6 {
1330 reg = <6>;
1331 qcom,gpu-freq = <0>;
1332 qcom,bus-freq = <0>;
1333 qcom,bus-min = <0>;
1334 qcom,bus-max = <0>;
1335 };
1336 };
1337};
1338
1339&gmu {
1340 qcom,gmu-pwrlevels {
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1343
1344 compatible = "qcom,gmu-pwrlevels";
1345
1346 qcom,gmu-pwrlevel@0 {
1347 reg = <0>;
1348 qcom,gmu-freq = <500000000>;
1349 };
1350
1351 qcom,gmu-pwrlevel@1 {
1352 reg = <1>;
1353 qcom,gmu-freq = <200000000>;
1354 };
1355
1356 qcom,gmu-pwrlevel@2 {
1357 reg = <2>;
1358 qcom,gmu-freq = <0>;
1359 };
1360 };
1361};