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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Chris Wilson5eddb702010-09-11 13:48:45 +010028#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
Paulo Zanonia5c961d2012-10-24 15:59:34 -020029#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
Chris Wilson5eddb702010-09-11 13:48:45 +010030
Eugeni Dodonov2b139522012-03-29 12:32:22 -030031#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
Ville Syrjälä2d401b12014-04-09 13:29:08 +030032#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
Eugeni Dodonov2b139522012-03-29 12:32:22 -030034
Daniel Vetter6b26c862012-04-24 14:04:12 +020035#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
36#define _MASKED_BIT_DISABLE(a) ((a) << 16)
37
Jesse Barnes585fb112008-07-29 11:54:06 -070038/* PCI config space */
39
40#define HPLLCC 0xc0 /* 855 only */
Jesse Barnes652c3932009-08-17 13:31:43 -070041#define GC_CLOCK_CONTROL_MASK (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070042#define GC_CLOCK_133_200 (0 << 0)
43#define GC_CLOCK_100_200 (1 << 0)
44#define GC_CLOCK_100_133 (2 << 0)
45#define GC_CLOCK_166_250 (3 << 0)
Jesse Barnesf97108d2010-01-29 11:27:07 -080046#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -070047#define GCFGC 0xf0 /* 915+ only */
48#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
49#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
50#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
Daniel Vetter257a7ff2013-07-26 08:35:42 +020051#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
52#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
53#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
54#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
55#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
56#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -070057#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -070058#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
60#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
61#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
62#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
63#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
64#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
65#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
66#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
67#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
68#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
72#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
73#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
74#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
75#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
76#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Daniel Vetter7f1bdbc2014-01-16 16:42:54 +010077#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
78
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070079
80/* Graphics reset regs */
Kenneth Graunke0573ed42010-09-11 03:17:19 -070081#define I965_GDRST 0xc0 /* PCI config register */
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070082#define GRDOM_FULL (0<<2)
83#define GRDOM_RENDER (1<<2)
84#define GRDOM_MEDIA (3<<2)
Jesse Barnes8a5c2ae2013-03-28 13:57:19 -070085#define GRDOM_MASK (3<<2)
Daniel Vetter5ccce182012-04-27 15:17:45 +020086#define GRDOM_RESET_ENABLE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -070087
Ville Syrjäläb3a3f032014-05-19 19:23:24 +030088#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
89#define ILK_GRDOM_FULL (0<<1)
90#define ILK_GRDOM_RENDER (1<<1)
91#define ILK_GRDOM_MEDIA (3<<1)
92#define ILK_GRDOM_MASK (3<<1)
93#define ILK_GRDOM_RESET_ENABLE (1<<0)
94
Jesse Barnes07b7ddd2011-08-03 11:28:44 -070095#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
96#define GEN6_MBC_SNPCR_SHIFT 21
97#define GEN6_MBC_SNPCR_MASK (3<<21)
98#define GEN6_MBC_SNPCR_MAX (0<<21)
99#define GEN6_MBC_SNPCR_MED (1<<21)
100#define GEN6_MBC_SNPCR_LOW (2<<21)
101#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
102
Imre Deak9e72b462014-05-05 15:13:55 +0300103#define VLV_G3DCTL 0x9024
104#define VLV_GSCKGCTL 0x9028
105
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100106#define GEN6_MBCTL 0x0907c
107#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
108#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
109#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
110#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
111#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
112
Eric Anholtcff458c2010-11-18 09:31:14 +0800113#define GEN6_GDRST 0x941c
114#define GEN6_GRDOM_FULL (1 << 0)
115#define GEN6_GRDOM_RENDER (1 << 1)
116#define GEN6_GRDOM_MEDIA (1 << 2)
117#define GEN6_GRDOM_BLT (1 << 3)
118
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100119#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
120#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
121#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
122#define PP_DIR_DCLV_2G 0xffffffff
123
Ben Widawsky94e409c2013-11-04 22:29:36 -0800124#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
125#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
126
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100127#define GAM_ECOCHK 0x4090
128#define ECOCHK_SNB_BIT (1<<10)
Ben Widawskye3dff582013-03-20 14:49:14 -0700129#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100130#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
131#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300132#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
133#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
134#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
135#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
136#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100137
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200138#define GAC_ECO_BITS 0x14090
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300139#define ECOBITS_SNB_BIT (1<<13)
Daniel Vetter48ecfa12012-04-11 20:42:40 +0200140#define ECOBITS_PPGTT_CACHE64B (3<<8)
141#define ECOBITS_PPGTT_CACHE4B (0<<8)
142
Daniel Vetterbe901a52012-04-11 20:42:39 +0200143#define GAB_CTL 0x24000
144#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
145
Jesse Barnes585fb112008-07-29 11:54:06 -0700146/* VGA stuff */
147
148#define VGA_ST01_MDA 0x3ba
149#define VGA_ST01_CGA 0x3da
150
151#define VGA_MSR_WRITE 0x3c2
152#define VGA_MSR_READ 0x3cc
153#define VGA_MSR_MEM_EN (1<<1)
154#define VGA_MSR_CGA_MODE (1<<0)
155
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300156#define VGA_SR_INDEX 0x3c4
Daniel Vetterf930ddd2012-11-21 15:55:21 +0100157#define SR01 1
Ville Syrjälä5434fd92013-06-06 13:09:32 +0300158#define VGA_SR_DATA 0x3c5
Jesse Barnes585fb112008-07-29 11:54:06 -0700159
160#define VGA_AR_INDEX 0x3c0
161#define VGA_AR_VID_EN (1<<5)
162#define VGA_AR_DATA_WRITE 0x3c0
163#define VGA_AR_DATA_READ 0x3c1
164
165#define VGA_GR_INDEX 0x3ce
166#define VGA_GR_DATA 0x3cf
167/* GR05 */
168#define VGA_GR_MEM_READ_MODE_SHIFT 3
169#define VGA_GR_MEM_READ_MODE_PLANE 1
170/* GR06 */
171#define VGA_GR_MEM_MODE_MASK 0xc
172#define VGA_GR_MEM_MODE_SHIFT 2
173#define VGA_GR_MEM_A0000_AFFFF 0
174#define VGA_GR_MEM_A0000_BFFFF 1
175#define VGA_GR_MEM_B0000_B7FFF 2
176#define VGA_GR_MEM_B0000_BFFFF 3
177
178#define VGA_DACMASK 0x3c6
179#define VGA_DACRX 0x3c7
180#define VGA_DACWX 0x3c8
181#define VGA_DACDATA 0x3c9
182
183#define VGA_CR_INDEX_MDA 0x3b4
184#define VGA_CR_DATA_MDA 0x3b5
185#define VGA_CR_INDEX_CGA 0x3d4
186#define VGA_CR_DATA_CGA 0x3d5
187
188/*
Brad Volkin351e3db2014-02-18 10:15:46 -0800189 * Instruction field definitions used by the command parser
190 */
191#define INSTR_CLIENT_SHIFT 29
192#define INSTR_CLIENT_MASK 0xE0000000
193#define INSTR_MI_CLIENT 0x0
194#define INSTR_BC_CLIENT 0x2
195#define INSTR_RC_CLIENT 0x3
196#define INSTR_SUBCLIENT_SHIFT 27
197#define INSTR_SUBCLIENT_MASK 0x18000000
198#define INSTR_MEDIA_SUBCLIENT 0x2
199
200/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700201 * Memory interface instructions used by the kernel
202 */
203#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
Brad Volkind4d48032014-02-18 10:15:54 -0800204/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
205#define MI_GLOBAL_GTT (1<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -0700206
207#define MI_NOOP MI_INSTR(0, 0)
208#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
209#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200210#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700211#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
212#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
213#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
214#define MI_FLUSH MI_INSTR(0x04, 0)
215#define MI_READ_FLUSH (1 << 0)
216#define MI_EXE_FLUSH (1 << 1)
217#define MI_NO_WRITE_FLUSH (1 << 2)
218#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
219#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800220#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Ben Widawsky0e792842013-12-16 20:50:37 -0800221#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
222#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
223#define MI_ARB_ENABLE (1<<0)
224#define MI_ARB_DISABLE (0<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700225#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800226#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
227#define MI_SUSPEND_FLUSH_EN (1<<0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400228#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200229#define MI_OVERLAY_CONTINUE (0x0<<21)
230#define MI_OVERLAY_ON (0x1<<21)
231#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700232#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500233#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700234#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500235#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Daniel Vettercb05d8d2012-05-23 14:02:00 +0200236/* IVB has funny definitions for which plane to flip. */
237#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
238#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
239#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
240#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
241#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
242#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
Ben Widawsky3e789982014-06-30 09:53:37 -0700243#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
Ben Widawsky0e792842013-12-16 20:50:37 -0800244#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
245#define MI_SEMAPHORE_UPDATE (1<<21)
246#define MI_SEMAPHORE_COMPARE (1<<20)
247#define MI_SEMAPHORE_REGISTER (1<<18)
248#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
249#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
250#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
251#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
252#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
253#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
254#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
255#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
256#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
257#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
258#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
259#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
Daniel Vettera028c4b2014-03-15 00:08:56 +0100260#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
261#define MI_SEMAPHORE_SYNC_MASK (3<<16)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800262#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
263#define MI_MM_SPACE_GTT (1<<8)
264#define MI_MM_SPACE_PHYSICAL (0<<8)
265#define MI_SAVE_EXT_STATE_EN (1<<3)
266#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800267#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800268#define MI_RESTORE_INHIBIT (1<<0)
Ben Widawsky3e789982014-06-30 09:53:37 -0700269#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
270#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
Ben Widawsky5ee426c2014-06-30 09:53:38 -0700271#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
272#define MI_SEMAPHORE_POLL (1<<15)
273#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
Jesse Barnes585fb112008-07-29 11:54:06 -0700274#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
Oscar Mateo4da46e12014-07-24 17:04:27 +0100275#define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700276#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
277#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
278#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000279/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
280 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
281 * simply ignores the register load under certain conditions.
282 * - One can actually load arbitrary many arbitrary registers: Simply issue x
283 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
284 */
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100285#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100286#define MI_LRI_FORCE_POSTED (1<<12)
Damien Lespiau7ec55f42014-04-07 20:24:32 +0100287#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
Damien Lespiaub76bfeb2014-04-07 20:24:33 +0100288#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
Ben Widawsky0e792842013-12-16 20:50:37 -0800289#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
Chris Wilson71a77e02011-02-02 12:13:49 +0000290#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
Jesse Barnes9a289772012-10-26 09:42:42 -0700291#define MI_FLUSH_DW_STORE_INDEX (1<<21)
292#define MI_INVALIDATE_TLB (1<<18)
293#define MI_FLUSH_DW_OP_STOREDW (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800294#define MI_FLUSH_DW_OP_MASK (3<<14)
Brad Volkinb18b3962014-02-18 10:15:53 -0800295#define MI_FLUSH_DW_NOTIFY (1<<8)
Jesse Barnes9a289772012-10-26 09:42:42 -0700296#define MI_INVALIDATE_BSD (1<<7)
297#define MI_FLUSH_DW_USE_GTT (1<<2)
298#define MI_FLUSH_DW_USE_PPGTT (0<<2)
Jesse Barnes585fb112008-07-29 11:54:06 -0700299#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100300#define MI_BATCH_NON_SECURE (1)
301/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
Ben Widawsky0e792842013-12-16 20:50:37 -0800302#define MI_BATCH_NON_SECURE_I965 (1<<8)
Chris Wilsond7d4eed2012-10-17 12:09:54 +0100303#define MI_BATCH_PPGTT_HSW (1<<8)
Ben Widawsky0e792842013-12-16 20:50:37 -0800304#define MI_BATCH_NON_SECURE_HSW (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700305#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson65f56872012-04-17 16:38:12 +0100306#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
Ben Widawsky1c7a0622013-11-02 21:07:12 -0700307#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
Ben Widawsky0e792842013-12-16 20:50:37 -0800308
Rodrigo Vivi94353732013-08-28 16:45:46 -0300309
310#define MI_PREDICATE_RESULT_2 (0x2214)
311#define LOWER_SLICE_ENABLED (1<<0)
312#define LOWER_SLICE_DISABLED (0<<0)
313
Jesse Barnes585fb112008-07-29 11:54:06 -0700314/*
315 * 3D instructions used by the kernel
316 */
317#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
318
319#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
320#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
321#define SC_UPDATE_SCISSOR (0x1<<1)
322#define SC_ENABLE_MASK (0x1<<0)
323#define SC_ENABLE (0x1<<0)
324#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
325#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
326#define SCI_YMIN_MASK (0xffff<<16)
327#define SCI_XMIN_MASK (0xffff<<0)
328#define SCI_YMAX_MASK (0xffff<<16)
329#define SCI_XMAX_MASK (0xffff<<0)
330#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
331#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
332#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
333#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
334#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
335#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
336#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
337#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
338#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100339
340#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
341#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
Jesse Barnes585fb112008-07-29 11:54:06 -0700342#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
343#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100344#define BLT_WRITE_A (2<<20)
345#define BLT_WRITE_RGB (1<<20)
346#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
Jesse Barnes585fb112008-07-29 11:54:06 -0700347#define BLT_DEPTH_8 (0<<24)
348#define BLT_DEPTH_16_565 (1<<24)
349#define BLT_DEPTH_16_1555 (2<<24)
350#define BLT_DEPTH_32 (3<<24)
Chris Wilsonc4d69da2014-09-08 14:25:41 +0100351#define BLT_ROP_SRC_COPY (0xcc<<16)
352#define BLT_ROP_COLOR_COPY (0xf0<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700353#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
354#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
355#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
356#define ASYNC_FLIP (1<<22)
357#define DISPLAY_PLANE_A (0<<20)
358#define DISPLAY_PLANE_B (1<<20)
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200359#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200360#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
Brad Volkinf0a346b2014-02-18 10:15:52 -0800361#define PIPE_CONTROL_MMIO_WRITE (1<<23)
Brad Volkin114d4f72014-02-18 10:15:55 -0800362#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
Jesse Barnes8d315282011-10-16 10:23:31 +0200363#define PIPE_CONTROL_CS_STALL (1<<20)
Ben Widawskycc0f6392012-06-04 14:42:49 -0700364#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200365#define PIPE_CONTROL_QW_WRITE (1<<14)
Brad Volkind4d48032014-02-18 10:15:54 -0800366#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200367#define PIPE_CONTROL_DEPTH_STALL (1<<13)
368#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200369#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200370#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
371#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
372#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
373#define PIPE_CONTROL_NOTIFY (1<<8)
Ben Widawsky3e789982014-06-30 09:53:37 -0700374#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
Jesse Barnes8d315282011-10-16 10:23:31 +0200375#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
376#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
377#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200378#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200379#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700380#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700381
Brad Volkin3a6fa982014-02-18 10:15:47 -0800382/*
383 * Commands used only by the command parser
384 */
385#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
386#define MI_ARB_CHECK MI_INSTR(0x05, 0)
387#define MI_RS_CONTROL MI_INSTR(0x06, 0)
388#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
389#define MI_PREDICATE MI_INSTR(0x0C, 0)
390#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
391#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
Brad Volkin9c640d12014-02-18 10:15:48 -0800392#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800393#define MI_URB_CLEAR MI_INSTR(0x19, 0)
394#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
395#define MI_CLFLUSH MI_INSTR(0x27, 0)
Brad Volkind4d48032014-02-18 10:15:54 -0800396#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
397#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800398#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0)
399#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
400#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
401#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
402#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
403#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
404
405#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
406#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
Brad Volkinf0a346b2014-02-18 10:15:52 -0800407#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
408#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
Brad Volkin3a6fa982014-02-18 10:15:47 -0800409#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
410#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
411#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
412 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
413#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
414 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
415#define GFX_OP_3DSTATE_SO_DECL_LIST \
416 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
417
418#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
419 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
420#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
421 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
422#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
423 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
424#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
425 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
426#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
427 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
428
429#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
430
431#define COLOR_BLT ((0x2<<29)|(0x40<<22))
432#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100433
434/*
Brad Volkin5947de92014-02-18 10:15:50 -0800435 * Registers used only by the command parser
436 */
437#define BCS_SWCTRL 0x22200
438
439#define HS_INVOCATION_COUNT 0x2300
440#define DS_INVOCATION_COUNT 0x2308
441#define IA_VERTICES_COUNT 0x2310
442#define IA_PRIMITIVES_COUNT 0x2318
443#define VS_INVOCATION_COUNT 0x2320
444#define GS_INVOCATION_COUNT 0x2328
445#define GS_PRIMITIVES_COUNT 0x2330
446#define CL_INVOCATION_COUNT 0x2338
447#define CL_PRIMITIVES_COUNT 0x2340
448#define PS_INVOCATION_COUNT 0x2348
449#define PS_DEPTH_COUNT 0x2350
450
451/* There are the 4 64-bit counter registers, one for each stream output */
452#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
453
Brad Volkin113a0472014-04-08 14:18:58 -0700454#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
455
456#define GEN7_3DPRIM_END_OFFSET 0x2420
457#define GEN7_3DPRIM_START_VERTEX 0x2430
458#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
459#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
460#define GEN7_3DPRIM_START_INSTANCE 0x243C
461#define GEN7_3DPRIM_BASE_VERTEX 0x2440
462
Kenneth Graunke180b8132014-03-25 22:52:03 -0700463#define OACONTROL 0x2360
464
Brad Volkin220375a2014-02-18 10:15:51 -0800465#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
466#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
467#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
468 _GEN7_PIPEA_DE_LOAD_SL, \
469 _GEN7_PIPEB_DE_LOAD_SL)
470
Brad Volkin5947de92014-02-18 10:15:50 -0800471/*
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100472 * Reset registers
473 */
474#define DEBUG_RESET_I830 0x6070
475#define DEBUG_RESET_FULL (1<<7)
476#define DEBUG_RESET_RENDER (1<<8)
477#define DEBUG_RESET_DISPLAY (1<<9)
478
Jesse Barnes57f350b2012-03-28 13:39:25 -0700479/*
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300480 * IOSF sideband
481 */
482#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
483#define IOSF_DEVFN_SHIFT 24
484#define IOSF_OPCODE_SHIFT 16
485#define IOSF_PORT_SHIFT 8
486#define IOSF_BYTE_ENABLES_SHIFT 4
487#define IOSF_BAR_SHIFT 1
488#define IOSF_SB_BUSY (1<<0)
Jesse Barnesf3419152013-11-04 11:52:44 -0800489#define IOSF_PORT_BUNIT 0x3
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300490#define IOSF_PORT_PUNIT 0x4
491#define IOSF_PORT_NC 0x11
492#define IOSF_PORT_DPIO 0x12
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300493#define IOSF_PORT_DPIO_2 0x1a
Jani Nikulae9f882a2013-08-27 15:12:14 +0300494#define IOSF_PORT_GPIO_NC 0x13
495#define IOSF_PORT_CCK 0x14
496#define IOSF_PORT_CCU 0xA9
497#define IOSF_PORT_GPS_CORE 0x48
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530498#define IOSF_PORT_FLISDSI 0x1B
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300499#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
500#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
501
Jesse Barnes30a970c2013-11-04 13:48:12 -0800502/* See configdb bunit SB addr map */
503#define BUNIT_REG_BISOC 0x11
504
Jesse Barnes30a970c2013-11-04 13:48:12 -0800505#define PUNIT_REG_DSPFREQ 0x36
Ville Syrjälä383c5a62014-06-28 02:03:57 +0300506#define DSPFREQSTAT_SHIFT_CHV 24
507#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
508#define DSPFREQGUAR_SHIFT_CHV 8
509#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800510#define DSPFREQSTAT_SHIFT 30
511#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
512#define DSPFREQGUAR_SHIFT 14
513#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
Ville Syrjälä26972b02014-06-28 02:04:11 +0300514#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
515#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
516#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
517#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
518#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
519#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
520#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
521#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
522#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
523#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
524#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
525#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
Imre Deaka30180a2014-03-04 19:23:02 +0200526
527/* See the PUNIT HAS v0.8 for the below bits */
528enum punit_power_well {
529 PUNIT_POWER_WELL_RENDER = 0,
530 PUNIT_POWER_WELL_MEDIA = 1,
531 PUNIT_POWER_WELL_DISP2D = 3,
532 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
533 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
534 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
535 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
536 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
537 PUNIT_POWER_WELL_DPIO_RX0 = 10,
538 PUNIT_POWER_WELL_DPIO_RX1 = 11,
Ville Syrjälä5d6f7ea2014-06-28 02:04:08 +0300539 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
Ville Syrjälä2ce147f2014-06-28 02:04:13 +0300540 /* FIXME: guesswork below */
541 PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
542 PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
543 PUNIT_POWER_WELL_DPIO_RX2 = 15,
Imre Deaka30180a2014-03-04 19:23:02 +0200544
545 PUNIT_POWER_WELL_NUM,
546};
547
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800548#define PUNIT_REG_PWRGT_CTRL 0x60
549#define PUNIT_REG_PWRGT_STATUS 0x61
Imre Deaka30180a2014-03-04 19:23:02 +0200550#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
551#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
552#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
553#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
554#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
Chon Ming Lee02f4c9e2013-10-03 23:16:17 +0800555
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300556#define PUNIT_REG_GPU_LFM 0xd3
557#define PUNIT_REG_GPU_FREQ_REQ 0xd4
558#define PUNIT_REG_GPU_FREQ_STS 0xd8
Ville Syrjäläe8474402013-06-26 17:43:24 +0300559#define GENFREQSTATUS (1<<0)
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300560#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
Deepak S31685c22014-07-03 17:33:01 -0400561#define PUNIT_REG_CZ_TIMESTAMP 0xce
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300562
563#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
564#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
565
Deepak S2b6b3a02014-05-27 15:59:30 +0530566#define PUNIT_GPU_STATUS_REG 0xdb
567#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
568#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
569#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
570#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
571
572#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
573#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
574#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
575
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300576#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
577#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
578#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
579#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
580#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
581#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
582#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
583#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
584#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
585#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
586
Deepak S31685c22014-07-03 17:33:01 -0400587#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
588#define VLV_RP_UP_EI_THRESHOLD 90
589#define VLV_RP_DOWN_EI_THRESHOLD 70
590#define VLV_INT_COUNT_FOR_DOWN_EI 5
591
ymohanmabe4fc042013-08-27 23:40:56 +0300592/* vlv2 north clock has */
Chon Ming Lee24eb2d52013-09-27 15:31:00 +0800593#define CCK_FUSE_REG 0x8
594#define CCK_FUSE_HPLL_FREQ_MASK 0x3
ymohanmabe4fc042013-08-27 23:40:56 +0300595#define CCK_REG_DSI_PLL_FUSE 0x44
596#define CCK_REG_DSI_PLL_CONTROL 0x48
597#define DSI_PLL_VCO_EN (1 << 31)
598#define DSI_PLL_LDO_GATE (1 << 30)
599#define DSI_PLL_P1_POST_DIV_SHIFT 17
600#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
601#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
602#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
603#define DSI_PLL_MUX_MASK (3 << 9)
604#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
605#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
606#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
607#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
608#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
609#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
610#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
611#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
612#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
613#define DSI_PLL_LOCK (1 << 0)
614#define CCK_REG_DSI_PLL_DIVIDER 0x4c
615#define DSI_PLL_LFSR (1 << 31)
616#define DSI_PLL_FRACTION_EN (1 << 30)
617#define DSI_PLL_FRAC_COUNTER_SHIFT 27
618#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
619#define DSI_PLL_USYNC_CNT_SHIFT 18
620#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
621#define DSI_PLL_N1_DIV_SHIFT 16
622#define DSI_PLL_N1_DIV_MASK (3 << 16)
623#define DSI_PLL_M1_DIV_SHIFT 0
624#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
Jesse Barnes30a970c2013-11-04 13:48:12 -0800625#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
Ville Syrjälä9cf33db2014-06-13 13:37:48 +0300626#define DISPLAY_TRUNK_FORCE_ON (1 << 17)
627#define DISPLAY_TRUNK_FORCE_OFF (1 << 16)
628#define DISPLAY_FREQUENCY_STATUS (0x1f << 8)
629#define DISPLAY_FREQUENCY_STATUS_SHIFT 8
630#define DISPLAY_FREQUENCY_VALUES (0x1f << 0)
ymohanmabe4fc042013-08-27 23:40:56 +0300631
Ville Syrjälä0e767182014-04-25 20:14:31 +0300632/**
633 * DOC: DPIO
634 *
635 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
636 * ports. DPIO is the name given to such a display PHY. These PHYs
637 * don't follow the standard programming model using direct MMIO
638 * registers, and instead their registers must be accessed trough IOSF
639 * sideband. VLV has one such PHY for driving ports B and C, and CHV
640 * adds another PHY for driving port D. Each PHY responds to specific
641 * IOSF-SB port.
642 *
643 * Each display PHY is made up of one or two channels. Each channel
644 * houses a common lane part which contains the PLL and other common
645 * logic. CH0 common lane also contains the IOSF-SB logic for the
646 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
647 * must be running when any DPIO registers are accessed.
648 *
649 * In addition to having their own registers, the PHYs are also
650 * controlled through some dedicated signals from the display
651 * controller. These include PLL reference clock enable, PLL enable,
652 * and CRI clock selection, for example.
653 *
654 * Eeach channel also has two splines (also called data lanes), and
655 * each spline is made up of one Physical Access Coding Sub-Layer
656 * (PCS) block and two TX lanes. So each channel has two PCS blocks
657 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
658 * data/clock pairs depending on the output type.
659 *
660 * Additionally the PHY also contains an AUX lane with AUX blocks
661 * for each channel. This is used for DP AUX communication, but
662 * this fact isn't really relevant for the driver since AUX is
663 * controlled from the display controller side. No DPIO registers
664 * need to be accessed during AUX communication,
665 *
666 * Generally the common lane corresponds to the pipe and
667 * the spline (PCS/TX) correponds to the port.
668 *
669 * For dual channel PHY (VLV/CHV):
670 *
671 * pipe A == CMN/PLL/REF CH0
672 *
673 * pipe B == CMN/PLL/REF CH1
674 *
675 * port B == PCS/TX CH0
676 *
677 * port C == PCS/TX CH1
678 *
679 * This is especially important when we cross the streams
680 * ie. drive port B with pipe B, or port C with pipe A.
681 *
682 * For single channel PHY (CHV):
683 *
684 * pipe C == CMN/PLL/REF CH0
685 *
686 * port D == PCS/TX CH0
687 *
688 * Note: digital port B is DDI0, digital port C is DDI1,
689 * digital port D is DDI2
690 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300691/*
Ville Syrjälä0e767182014-04-25 20:14:31 +0300692 * Dual channel PHY (VLV/CHV)
693 * ---------------------------------
694 * | CH0 | CH1 |
695 * | CMN/PLL/REF | CMN/PLL/REF |
696 * |---------------|---------------| Display PHY
697 * | PCS01 | PCS23 | PCS01 | PCS23 |
698 * |-------|-------|-------|-------|
699 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
700 * ---------------------------------
701 * | DDI0 | DDI1 | DP/HDMI ports
702 * ---------------------------------
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200703 *
Ville Syrjälä0e767182014-04-25 20:14:31 +0300704 * Single channel PHY (CHV)
705 * -----------------
706 * | CH0 |
707 * | CMN/PLL/REF |
708 * |---------------| Display PHY
709 * | PCS01 | PCS23 |
710 * |-------|-------|
711 * |TX0|TX1|TX2|TX3|
712 * -----------------
713 * | DDI2 | DP/HDMI port
714 * -----------------
Jesse Barnes57f350b2012-03-28 13:39:25 -0700715 */
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300716#define DPIO_DEVFN 0
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300717
Ville Syrjälä54d9d492013-01-24 15:29:53 +0200718#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700719#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
720#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
721#define DPIO_SFR_BYPASS (1<<1)
Jesse Barnes40e9cf62013-10-03 11:35:46 -0700722#define DPIO_CMNRST (1<<0)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700723
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800724#define DPIO_PHY(pipe) ((pipe) >> 1)
725#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
726
Daniel Vetter598fac62013-04-18 22:01:46 +0200727/*
728 * Per pipe/PLL DPIO regs
729 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800730#define _VLV_PLL_DW3_CH0 0x800c
Jesse Barnes57f350b2012-03-28 13:39:25 -0700731#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
Daniel Vetter598fac62013-04-18 22:01:46 +0200732#define DPIO_POST_DIV_DAC 0
733#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
734#define DPIO_POST_DIV_LVDS1 2
735#define DPIO_POST_DIV_LVDS2 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700736#define DPIO_K_SHIFT (24) /* 4 bits */
737#define DPIO_P1_SHIFT (21) /* 3 bits */
738#define DPIO_P2_SHIFT (16) /* 5 bits */
739#define DPIO_N_SHIFT (12) /* 4 bits */
740#define DPIO_ENABLE_CALIBRATION (1<<11)
741#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
742#define DPIO_M2DIV_MASK 0xff
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800743#define _VLV_PLL_DW3_CH1 0x802c
744#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700745
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800746#define _VLV_PLL_DW5_CH0 0x8014
Jesse Barnes57f350b2012-03-28 13:39:25 -0700747#define DPIO_REFSEL_OVERRIDE 27
748#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
749#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
750#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530751#define DPIO_PLL_REFCLK_SEL_MASK 3
Jesse Barnes57f350b2012-03-28 13:39:25 -0700752#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
753#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800754#define _VLV_PLL_DW5_CH1 0x8034
755#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700756
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800757#define _VLV_PLL_DW7_CH0 0x801c
758#define _VLV_PLL_DW7_CH1 0x803c
759#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700760
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800761#define _VLV_PLL_DW8_CH0 0x8040
762#define _VLV_PLL_DW8_CH1 0x8060
763#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200764
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800765#define VLV_PLL_DW9_BCAST 0xc044
766#define _VLV_PLL_DW9_CH0 0x8044
767#define _VLV_PLL_DW9_CH1 0x8064
768#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200769
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800770#define _VLV_PLL_DW10_CH0 0x8048
771#define _VLV_PLL_DW10_CH1 0x8068
772#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200773
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800774#define _VLV_PLL_DW11_CH0 0x804c
775#define _VLV_PLL_DW11_CH1 0x806c
776#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
Jesse Barnes57f350b2012-03-28 13:39:25 -0700777
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800778/* Spec for ref block start counts at DW10 */
779#define VLV_REF_DW13 0x80ac
Daniel Vetter598fac62013-04-18 22:01:46 +0200780
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800781#define VLV_CMN_DW0 0x8100
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100782
Daniel Vetter598fac62013-04-18 22:01:46 +0200783/*
784 * Per DDI channel DPIO regs
785 */
786
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800787#define _VLV_PCS_DW0_CH0 0x8200
788#define _VLV_PCS_DW0_CH1 0x8400
Daniel Vetter598fac62013-04-18 22:01:46 +0200789#define DPIO_PCS_TX_LANE2_RESET (1<<16)
790#define DPIO_PCS_TX_LANE1_RESET (1<<7)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800791#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200792
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300793#define _VLV_PCS01_DW0_CH0 0x200
794#define _VLV_PCS23_DW0_CH0 0x400
795#define _VLV_PCS01_DW0_CH1 0x2600
796#define _VLV_PCS23_DW0_CH1 0x2800
797#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
798#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
799
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800800#define _VLV_PCS_DW1_CH0 0x8204
801#define _VLV_PCS_DW1_CH1 0x8404
Ville Syrjäläd2152b22014-04-28 14:15:24 +0300802#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
Daniel Vetter598fac62013-04-18 22:01:46 +0200803#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
804#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
805#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
806#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800807#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200808
Ville Syrjälä97fd4d52014-04-09 13:29:02 +0300809#define _VLV_PCS01_DW1_CH0 0x204
810#define _VLV_PCS23_DW1_CH0 0x404
811#define _VLV_PCS01_DW1_CH1 0x2604
812#define _VLV_PCS23_DW1_CH1 0x2804
813#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
814#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
815
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800816#define _VLV_PCS_DW8_CH0 0x8220
817#define _VLV_PCS_DW8_CH1 0x8420
Ville Syrjälä9197c882014-04-09 13:29:05 +0300818#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
819#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800820#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200821
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800822#define _VLV_PCS01_DW8_CH0 0x0220
823#define _VLV_PCS23_DW8_CH0 0x0420
824#define _VLV_PCS01_DW8_CH1 0x2620
825#define _VLV_PCS23_DW8_CH1 0x2820
826#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
827#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200828
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800829#define _VLV_PCS_DW9_CH0 0x8224
830#define _VLV_PCS_DW9_CH1 0x8424
831#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200832
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300833#define _CHV_PCS_DW10_CH0 0x8228
834#define _CHV_PCS_DW10_CH1 0x8428
835#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
836#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
837#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
838
Ville Syrjälä1966e592014-04-09 13:29:04 +0300839#define _VLV_PCS01_DW10_CH0 0x0228
840#define _VLV_PCS23_DW10_CH0 0x0428
841#define _VLV_PCS01_DW10_CH1 0x2628
842#define _VLV_PCS23_DW10_CH1 0x2828
843#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
844#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
845
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800846#define _VLV_PCS_DW11_CH0 0x822c
847#define _VLV_PCS_DW11_CH1 0x842c
848#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200849
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800850#define _VLV_PCS_DW12_CH0 0x8230
851#define _VLV_PCS_DW12_CH1 0x8430
852#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200853
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800854#define _VLV_PCS_DW14_CH0 0x8238
855#define _VLV_PCS_DW14_CH1 0x8438
856#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200857
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800858#define _VLV_PCS_DW23_CH0 0x825c
859#define _VLV_PCS_DW23_CH1 0x845c
860#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200861
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800862#define _VLV_TX_DW2_CH0 0x8288
863#define _VLV_TX_DW2_CH1 0x8488
Ville Syrjälä1fb44502014-06-28 02:04:03 +0300864#define DPIO_SWING_MARGIN000_SHIFT 16
865#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300866#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800867#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200868
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800869#define _VLV_TX_DW3_CH0 0x828c
870#define _VLV_TX_DW3_CH1 0x848c
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300871/* The following bit for CHV phy */
872#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
Ville Syrjälä1fb44502014-06-28 02:04:03 +0300873#define DPIO_SWING_MARGIN101_SHIFT 16
874#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800875#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
876
877#define _VLV_TX_DW4_CH0 0x8290
878#define _VLV_TX_DW4_CH1 0x8490
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300879#define DPIO_SWING_DEEMPH9P5_SHIFT 24
880#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
Ville Syrjälä1fb44502014-06-28 02:04:03 +0300881#define DPIO_SWING_DEEMPH6P0_SHIFT 16
882#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800883#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
884
885#define _VLV_TX3_DW4_CH0 0x690
886#define _VLV_TX3_DW4_CH1 0x2a90
887#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
888
889#define _VLV_TX_DW5_CH0 0x8294
890#define _VLV_TX_DW5_CH1 0x8494
Daniel Vetter598fac62013-04-18 22:01:46 +0200891#define DPIO_TX_OCALINIT_EN (1<<31)
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800892#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200893
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800894#define _VLV_TX_DW11_CH0 0x82ac
895#define _VLV_TX_DW11_CH1 0x84ac
896#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
Daniel Vetter598fac62013-04-18 22:01:46 +0200897
Chon Ming Leeab3c7592013-11-07 10:43:30 +0800898#define _VLV_TX_DW14_CH0 0x82b8
899#define _VLV_TX_DW14_CH1 0x84b8
900#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
Vijay Purushothamanb56747a2012-09-27 19:13:03 +0530901
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300902/* CHV dpPhy registers */
903#define _CHV_PLL_DW0_CH0 0x8000
904#define _CHV_PLL_DW0_CH1 0x8180
905#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
906
907#define _CHV_PLL_DW1_CH0 0x8004
908#define _CHV_PLL_DW1_CH1 0x8184
909#define DPIO_CHV_N_DIV_SHIFT 8
910#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
911#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
912
913#define _CHV_PLL_DW2_CH0 0x8008
914#define _CHV_PLL_DW2_CH1 0x8188
915#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
916
917#define _CHV_PLL_DW3_CH0 0x800c
918#define _CHV_PLL_DW3_CH1 0x818c
919#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
920#define DPIO_CHV_FIRST_MOD (0 << 8)
921#define DPIO_CHV_SECOND_MOD (1 << 8)
922#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
923#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
924
925#define _CHV_PLL_DW6_CH0 0x8018
926#define _CHV_PLL_DW6_CH1 0x8198
927#define DPIO_CHV_GAIN_CTRL_SHIFT 16
928#define DPIO_CHV_INT_COEFF_SHIFT 8
929#define DPIO_CHV_PROP_COEFF_SHIFT 0
930#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
931
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +0300932#define _CHV_CMN_DW5_CH0 0x8114
933#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
934#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
935#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
936#define CHV_BUFRIGHTENA1_MASK (3 << 20)
937#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
938#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
939#define CHV_BUFLEFTENA1_FORCE (3 << 22)
940#define CHV_BUFLEFTENA1_MASK (3 << 22)
941
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300942#define _CHV_CMN_DW13_CH0 0x8134
943#define _CHV_CMN_DW0_CH1 0x8080
944#define DPIO_CHV_S1_DIV_SHIFT 21
945#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
946#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
947#define DPIO_CHV_K_DIV_SHIFT 4
948#define DPIO_PLL_FREQLOCK (1 << 1)
949#define DPIO_PLL_LOCK (1 << 0)
950#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
951
952#define _CHV_CMN_DW14_CH0 0x8138
953#define _CHV_CMN_DW1_CH1 0x8084
954#define DPIO_AFC_RECAL (1 << 14)
955#define DPIO_DCLKP_EN (1 << 13)
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +0300956#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
957#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
958#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
959#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
960#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
961#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
962#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
963#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300964#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
965
Ville Syrjälä9197c882014-04-09 13:29:05 +0300966#define _CHV_CMN_DW19_CH0 0x814c
967#define _CHV_CMN_DW6_CH1 0x8098
968#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
969#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
970
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300971#define CHV_CMN_DW30 0x8178
972#define DPIO_LRC_BYPASS (1 << 3)
973
974#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
975 (lane) * 0x200 + (offset))
976
Ville Syrjäläf72df8d2014-04-09 13:29:03 +0300977#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
978#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
979#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
980#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
981#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
982#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
983#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
984#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
985#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
986#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
987#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
Chon Ming Lee9d556c92014-05-02 14:27:47 +0300988#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
989#define DPIO_FRC_LATENCY_SHFIT 8
990#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
991#define DPIO_UPAR_SHIFT 30
Jesse Barnes585fb112008-07-29 11:54:06 -0700992/*
Jesse Barnesde151cf2008-11-12 10:03:55 -0800993 * Fence registers
994 */
995#define FENCE_REG_830_0 0x2000
Eric Anholtdc529a42009-03-10 22:34:49 -0700996#define FENCE_REG_945_8 0x3000
Jesse Barnesde151cf2008-11-12 10:03:55 -0800997#define I830_FENCE_START_MASK 0x07f80000
998#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -0800999#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001000#define I830_FENCE_PITCH_SHIFT 4
1001#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +02001002#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -07001003#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001004#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001005
1006#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -08001007#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001008
1009#define FENCE_REG_965_0 0x03000
1010#define I965_FENCE_PITCH_SHIFT 2
1011#define I965_FENCE_TILING_Y_SHIFT 1
1012#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +02001013#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -08001014
Eric Anholt4e901fd2009-10-26 16:44:17 -07001015#define FENCE_REG_SANDYBRIDGE_0 0x100000
1016#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
Ville Syrjälä3a062472013-04-09 11:45:05 +03001017#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
Eric Anholt4e901fd2009-10-26 16:44:17 -07001018
Deepak S2b6b3a02014-05-27 15:59:30 +05301019
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001020/* control register for cpu gtt access */
1021#define TILECTL 0x101000
1022#define TILECTL_SWZCTL (1 << 0)
1023#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1024#define TILECTL_BACKSNOOP_DIS (1 << 3)
1025
Jesse Barnesde151cf2008-11-12 10:03:55 -08001026/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001027 * Instruction and interrupt control regs
1028 */
Ville Syrjäläf1e1c212014-06-05 20:02:59 +03001029#define PGTBL_CTL 0x02020
1030#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1031#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001032#define PGTBL_ER 0x02024
Ville Syrjälä81e7f202014-08-15 01:21:55 +03001033#define PRB0_BASE (0x2030-0x30)
1034#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1035#define PRB2_BASE (0x2050-0x30) /* gen3 */
1036#define SRB0_BASE (0x2100-0x30) /* gen2 */
1037#define SRB1_BASE (0x2110-0x30) /* gen2 */
1038#define SRB2_BASE (0x2120-0x30) /* 830 */
1039#define SRB3_BASE (0x2130-0x30) /* 830 */
Daniel Vetter333e9fe2010-08-02 16:24:01 +02001040#define RENDER_RING_BASE 0x02000
1041#define BSD_RING_BASE 0x04000
1042#define GEN6_BSD_RING_BASE 0x12000
Zhao Yakui845f74a2014-04-17 10:37:37 +08001043#define GEN8_BSD2_RING_BASE 0x1c000
Ben Widawsky1950de12013-05-28 19:22:20 -07001044#define VEBOX_RING_BASE 0x1a000
Chris Wilson549f7362010-10-19 11:19:32 +01001045#define BLT_RING_BASE 0x22000
Daniel Vetter3d281d82010-09-24 21:14:22 +02001046#define RING_TAIL(base) ((base)+0x30)
1047#define RING_HEAD(base) ((base)+0x34)
1048#define RING_START(base) ((base)+0x38)
1049#define RING_CTL(base) ((base)+0x3c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001050#define RING_SYNC_0(base) ((base)+0x40)
1051#define RING_SYNC_1(base) ((base)+0x44)
Ben Widawsky1950de12013-05-28 19:22:20 -07001052#define RING_SYNC_2(base) ((base)+0x48)
1053#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1054#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1055#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1056#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1057#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1058#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1059#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1060#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1061#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1062#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1063#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1064#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
Ben Widawskyad776f82013-05-28 19:22:18 -07001065#define GEN6_NOSYNC 0
Chris Wilson8fd26852010-12-08 18:40:43 +00001066#define RING_MAX_IDLE(base) ((base)+0x54)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001067#define RING_HWS_PGA(base) ((base)+0x80)
1068#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
Imre Deak9e72b462014-05-05 15:13:55 +03001069
1070#define GEN7_WR_WATERMARK 0x4028
1071#define GEN7_GFX_PRIO_CTRL 0x402C
1072#define ARB_MODE 0x4030
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001073#define ARB_MODE_SWIZZLE_SNB (1<<4)
1074#define ARB_MODE_SWIZZLE_IVB (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03001075#define GEN7_GFX_PEND_TLB0 0x4034
1076#define GEN7_GFX_PEND_TLB1 0x4038
1077/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1078#define GEN7_LRA_LIMITS_BASE 0x403C
1079#define GEN7_LRA_LIMITS_REG_NUM 13
1080#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1081#define GEN7_GFX_MAX_REQ_COUNT 0x4074
1082
Ben Widawsky31a53362013-11-02 21:07:04 -07001083#define GAMTARBMODE 0x04a08
Ben Widawsky4afe8d32013-11-02 21:07:55 -07001084#define ARB_MODE_BWGTLB_DISABLE (1<<9)
Ben Widawsky31a53362013-11-02 21:07:04 -07001085#define ARB_MODE_SWIZZLE_BDW (1<<1)
Eric Anholt45930102011-05-06 17:12:35 -07001086#define RENDER_HWS_PGA_GEN7 (0x04080)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001087#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
Ben Widawsky828c7902013-10-16 09:21:30 -07001088#define RING_FAULT_GTTSEL_MASK (1<<11)
1089#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
1090#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
1091#define RING_FAULT_VALID (1<<0)
Daniel Vetter33f3f512011-12-14 13:57:39 +01001092#define DONE_REG 0x40b0
Ben Widawskyfbe5d362013-11-04 19:56:49 -08001093#define GEN8_PRIVATE_PAT 0x40e0
Eric Anholt45930102011-05-06 17:12:35 -07001094#define BSD_HWS_PGA_GEN7 (0x04180)
1095#define BLT_HWS_PGA_GEN7 (0x04280)
Ben Widawsky9a8a2212013-05-28 19:22:23 -07001096#define VEBOX_HWS_PGA_GEN7 (0x04380)
Daniel Vetter3d281d82010-09-24 21:14:22 +02001097#define RING_ACTHD(base) ((base)+0x74)
Chris Wilson50877442014-03-21 12:41:53 +00001098#define RING_ACTHD_UDW(base) ((base)+0x5c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001099#define RING_NOPID(base) ((base)+0x94)
Chris Wilson0f468322011-01-04 17:35:21 +00001100#define RING_IMR(base) ((base)+0xa8)
Oscar Mateo73d477f2014-07-24 17:04:31 +01001101#define RING_HWSTAM(base) ((base)+0x98)
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001102#define RING_TIMESTAMP(base) ((base)+0x358)
Jesse Barnes585fb112008-07-29 11:54:06 -07001103#define TAIL_ADDR 0x001FFFF8
1104#define HEAD_WRAP_COUNT 0xFFE00000
1105#define HEAD_WRAP_ONE 0x00200000
1106#define HEAD_ADDR 0x001FFFFC
1107#define RING_NR_PAGES 0x001FF000
1108#define RING_REPORT_MASK 0x00000006
1109#define RING_REPORT_64K 0x00000002
1110#define RING_REPORT_128K 0x00000004
1111#define RING_NO_REPORT 0x00000000
1112#define RING_VALID_MASK 0x00000001
1113#define RING_VALID 0x00000001
1114#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +01001115#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1116#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001117#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Imre Deak9e72b462014-05-05 15:13:55 +03001118
1119#define GEN7_TLB_RD_ADDR 0x4700
1120
Chris Wilson8168bd42010-11-11 17:54:52 +00001121#if 0
1122#define PRB0_TAIL 0x02030
1123#define PRB0_HEAD 0x02034
1124#define PRB0_START 0x02038
1125#define PRB0_CTL 0x0203c
Jesse Barnes585fb112008-07-29 11:54:06 -07001126#define PRB1_TAIL 0x02040 /* 915+ only */
1127#define PRB1_HEAD 0x02044 /* 915+ only */
1128#define PRB1_START 0x02048 /* 915+ only */
1129#define PRB1_CTL 0x0204c /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +00001130#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001131#define IPEIR_I965 0x02064
1132#define IPEHR_I965 0x02068
1133#define INSTDONE_I965 0x0206c
Ben Widawskyd53bd482012-08-22 11:32:14 -07001134#define GEN7_INSTDONE_1 0x0206c
1135#define GEN7_SC_INSTDONE 0x07100
1136#define GEN7_SAMPLER_INSTDONE 0x0e160
1137#define GEN7_ROW_INSTDONE 0x0e164
1138#define I915_NUM_INSTDONE_REG 4
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001139#define RING_IPEIR(base) ((base)+0x64)
1140#define RING_IPEHR(base) ((base)+0x68)
1141#define RING_INSTDONE(base) ((base)+0x6c)
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001142#define RING_INSTPS(base) ((base)+0x70)
1143#define RING_DMA_FADD(base) ((base)+0x78)
Ben Widawsky13ffadd2014-04-01 16:31:07 -07001144#define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001145#define RING_INSTPM(base) ((base)+0xc0)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301146#define RING_MI_MODE(base) ((base)+0x9c)
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001147#define INSTPS 0x02070 /* 965+ only */
1148#define INSTDONE1 0x0207c /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001149#define ACTHD_I965 0x02074
1150#define HWS_PGA 0x02080
1151#define HWS_ADDRESS_MASK 0xfffff000
1152#define HWS_START_ADDRESS_SHIFT 4
Jesse Barnes97f5ab62009-10-08 10:16:48 -07001153#define PWRCTXA 0x2088 /* 965GM+ only */
1154#define PWRCTX_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001155#define IPEIR 0x02088
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001156#define IPEHR 0x0208c
1157#define INSTDONE 0x02090
Jesse Barnes585fb112008-07-29 11:54:06 -07001158#define NOPID 0x02094
1159#define HWSTAM 0x02098
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001160#define DMA_FADD_I8XX 0x020d0
Chris Wilson94e39e22013-10-30 09:28:22 +00001161#define RING_BBSTATE(base) ((base)+0x110)
Ville Syrjälä3dda20a2013-12-10 21:44:43 +02001162#define RING_BBADDR(base) ((base)+0x140)
1163#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
Eric Anholt71cf39b2010-03-08 23:41:55 -08001164
Chris Wilsonf4068392010-10-27 20:36:41 +01001165#define ERROR_GEN6 0x040a0
Ben Widawsky71e172e2012-08-20 16:15:13 -07001166#define GEN7_ERR_INT 0x44040
Paulo Zanonide032bf2013-04-12 17:57:58 -03001167#define ERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03001168#define ERR_INT_MMIO_UNCLAIMED (1<<13)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001169#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
Paulo Zanoni86642812013-04-12 17:57:57 -03001170#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001171#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
Paulo Zanoni86642812013-04-12 17:57:57 -03001172#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001173#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001174#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03001175#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
Daniel Vetter7336df62013-07-09 22:59:16 +02001176#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Chris Wilsonf4068392010-10-27 20:36:41 +01001177
Paulo Zanoni3f1e1092013-02-18 19:00:21 -03001178#define FPGA_DBG 0x42300
1179#define FPGA_DBG_RM_NOCLAIM (1<<31)
1180
Chris Wilson0f3b6842013-01-15 12:05:55 +00001181#define DERRMR 0x44050
Ben Widawsky4e0bbc32013-11-02 21:07:07 -07001182/* Note that HBLANK events are reserved on bdw+ */
Chris Wilsonffe74d72013-08-26 20:58:12 +01001183#define DERRMR_PIPEA_SCANLINE (1<<0)
1184#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1185#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1186#define DERRMR_PIPEA_VBLANK (1<<3)
1187#define DERRMR_PIPEA_HBLANK (1<<5)
1188#define DERRMR_PIPEB_SCANLINE (1<<8)
1189#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1190#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1191#define DERRMR_PIPEB_VBLANK (1<<11)
1192#define DERRMR_PIPEB_HBLANK (1<<13)
1193/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1194#define DERRMR_PIPEC_SCANLINE (1<<14)
1195#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1196#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1197#define DERRMR_PIPEC_VBLANK (1<<21)
1198#define DERRMR_PIPEC_HBLANK (1<<22)
1199
Chris Wilson0f3b6842013-01-15 12:05:55 +00001200
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001201/* GM45+ chicken bits -- debug workaround bits that may be required
1202 * for various sorts of correct behavior. The top 16 bits of each are
1203 * the enables for writing to the corresponding low bit.
1204 */
1205#define _3D_CHICKEN 0x02084
Daniel Vetter42839082012-12-14 23:38:28 +01001206#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001207#define _3D_CHICKEN2 0x0208c
1208/* Disables pipelining of read flushes past the SF-WIZ interface.
1209 * Required on all Ironlake steppings according to the B-Spec, but the
1210 * particular danger of not doing so is not specified.
1211 */
1212# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1213#define _3D_CHICKEN3 0x02090
Jesse Barnes87f80202012-10-02 17:43:41 -05001214#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
Kenneth Graunke26b6e442012-10-07 08:51:07 -07001215#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
Ville Syrjäläe927ecd2014-02-04 21:59:18 +02001216#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1217#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
Eric Anholtde6e2ea2010-11-06 14:53:32 -07001218
Eric Anholt71cf39b2010-03-08 23:41:55 -08001219#define MI_MODE 0x0209c
1220# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -08001221# define MI_FLUSH_ENABLE (1 << 12)
Chris Wilson1c8c38c2013-01-20 16:11:20 +00001222# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +05301223# define MODE_IDLE (1 << 9)
Chris Wilson9991ae72014-04-02 16:36:07 +01001224# define STOP_RING (1 << 8)
Eric Anholt71cf39b2010-03-08 23:41:55 -08001225
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001226#define GEN6_GT_MODE 0x20d0
Ville Syrjäläa607c1a2014-02-04 21:59:19 +02001227#define GEN7_GT_MODE 0x7008
Ville Syrjälä8d85d272014-02-04 21:59:15 +02001228#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1229#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1230#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1231#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1232#define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16)
Daniel Vetter6547fbd2012-12-14 23:38:29 +01001233#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
Ben Widawskyf8f2ac92012-10-03 19:34:24 -07001234
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001235#define GFX_MODE 0x02520
Jesse Barnesb095cd02011-08-12 15:28:32 -07001236#define GFX_MODE_GEN7 0x0229c
Daniel Vetter5eb719c2012-02-09 17:15:48 +01001237#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001238#define GFX_RUN_LIST_ENABLE (1<<15)
Chris Wilsonaa83e302014-03-21 17:18:54 +00001239#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001240#define GFX_SURFACE_FAULT_ENABLE (1<<12)
1241#define GFX_REPLAY_MODE (1<<11)
1242#define GFX_PSMI_GRANULARITY (1<<10)
1243#define GFX_PPGTT_ENABLE (1<<9)
1244
Daniel Vettera7e806d2012-07-11 16:27:55 +02001245#define VLV_DISPLAY_BASE 0x180000
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301246#define VLV_MIPI_BASE VLV_DISPLAY_BASE
Daniel Vettera7e806d2012-07-11 16:27:55 +02001247
Imre Deak9e72b462014-05-05 15:13:55 +03001248#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1249#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
Jesse Barnes585fb112008-07-29 11:54:06 -07001250#define SCPD0 0x0209c /* 915+ only */
1251#define IER 0x020a0
1252#define IIR 0x020a4
1253#define IMR 0x020a8
1254#define ISR 0x020ac
Ville Syrjälä07ec7ec2013-01-24 15:29:51 +02001255#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001256#define GINT_DIS (1<<22)
Jesse Barnes2d809572012-10-25 12:15:44 -07001257#define GCFG_DIS (1<<8)
Imre Deak9e72b462014-05-05 15:13:55 +03001258#define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
Ville Syrjäläff763012013-01-24 15:29:52 +02001259#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1260#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1261#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1262#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1263#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001264#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
Deepak S38807742014-05-23 21:00:15 +05301265#define VLV_PCBR_ADDR_SHIFT 12
1266
Ville Syrjälä90a72f82013-02-19 23:16:44 +02001267#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001268#define EIR 0x020b0
1269#define EMR 0x020b4
1270#define ESR 0x020b8
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001271#define GM45_ERROR_PAGE_TABLE (1<<5)
1272#define GM45_ERROR_MEM_PRIV (1<<4)
1273#define I915_ERROR_PAGE_TABLE (1<<4)
1274#define GM45_ERROR_CP_PRIV (1<<3)
1275#define I915_ERROR_MEMORY_REFRESH (1<<1)
1276#define I915_ERROR_INSTRUCTION (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001277#define INSTPM 0x020c0
Li Pengee980b82010-01-27 19:01:11 +08001278#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Ville Syrjälä32992542014-02-25 15:13:39 +02001279#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
Chris Wilson8692d00e2011-02-05 10:08:21 +00001280 will not assert AGPBUSY# and will only
1281 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -08001282#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Chris Wilson884020b2013-08-06 19:01:14 +01001283#define INSTPM_TLB_INVALIDATE (1<<9)
1284#define INSTPM_SYNC_FLUSH (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001285#define ACTHD 0x020c8
Ville Syrjälä10383922014-08-15 01:21:54 +03001286#define MEM_MODE 0x020cc
1287#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1288#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1289#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001290#define FW_BLC 0x020d8
Chris Wilson8692d00e2011-02-05 10:08:21 +00001291#define FW_BLC2 0x020dc
Jesse Barnes585fb112008-07-29 11:54:06 -07001292#define FW_BLC_SELF 0x020e0 /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +08001293#define FW_BLC_SELF_EN_MASK (1<<31)
1294#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1295#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001296#define MM_BURST_LENGTH 0x00700000
1297#define MM_FIFO_WATERMARK 0x0001F000
1298#define LM_BURST_LENGTH 0x00000700
1299#define LM_FIFO_WATERMARK 0x0000001F
Jesse Barnes585fb112008-07-29 11:54:06 -07001300#define MI_ARB_STATE 0x020e4 /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -07001301
1302/* Make render/texture TLB fetches lower priorty than associated data
1303 * fetches. This is not turned on by default
1304 */
1305#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1306
1307/* Isoch request wait on GTT enable (Display A/B/C streams).
1308 * Make isoch requests stall on the TLB update. May cause
1309 * display underruns (test mode only)
1310 */
1311#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1312
1313/* Block grant count for isoch requests when block count is
1314 * set to a finite value.
1315 */
1316#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1317#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1318#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1319#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1320#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1321
1322/* Enable render writes to complete in C2/C3/C4 power states.
1323 * If this isn't enabled, render writes are prevented in low
1324 * power states. That seems bad to me.
1325 */
1326#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1327
1328/* This acknowledges an async flip immediately instead
1329 * of waiting for 2TLB fetches.
1330 */
1331#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1332
1333/* Enables non-sequential data reads through arbiter
1334 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001335#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -07001336
1337/* Disable FSB snooping of cacheable write cycles from binner/render
1338 * command stream
1339 */
1340#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1341
1342/* Arbiter time slice for non-isoch streams */
1343#define MI_ARB_TIME_SLICE_MASK (7 << 5)
1344#define MI_ARB_TIME_SLICE_1 (0 << 5)
1345#define MI_ARB_TIME_SLICE_2 (1 << 5)
1346#define MI_ARB_TIME_SLICE_4 (2 << 5)
1347#define MI_ARB_TIME_SLICE_6 (3 << 5)
1348#define MI_ARB_TIME_SLICE_8 (4 << 5)
1349#define MI_ARB_TIME_SLICE_10 (5 << 5)
1350#define MI_ARB_TIME_SLICE_14 (6 << 5)
1351#define MI_ARB_TIME_SLICE_16 (7 << 5)
1352
1353/* Low priority grace period page size */
1354#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1355#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1356
1357/* Disable display A/B trickle feed */
1358#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1359
1360/* Set display plane priority */
1361#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1362#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1363
Ville Syrjälä54e472a2014-02-25 15:13:40 +02001364#define MI_STATE 0x020e4 /* gen2 only */
1365#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1366#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1367
Jesse Barnes585fb112008-07-29 11:54:06 -07001368#define CACHE_MODE_0 0x02120 /* 915+ only */
Daniel Vetter4358a372012-10-18 11:49:51 +02001369#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001370#define CM0_IZ_OPT_DISABLE (1<<6)
1371#define CM0_ZR_OPT_DISABLE (1<<5)
Daniel Vetter009be662012-04-11 20:42:42 +02001372#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
Jesse Barnes585fb112008-07-29 11:54:06 -07001373#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1374#define CM0_COLOR_EVICT_DISABLE (1<<3)
1375#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1376#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1377#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001378#define GFX_FLSH_CNTL_GEN6 0x101008
1379#define GFX_FLSH_CNTL_EN (1<<0)
Jesse Barnes1afe3e92010-03-26 10:35:20 -07001380#define ECOSKPD 0x021d0
1381#define ECO_GATING_CX_ONLY (1<<3)
1382#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001383
Chia-I Wufe27c602014-01-28 13:29:33 +08001384#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
Akash Goel4e046322014-04-04 17:14:38 +05301385#define RC_OP_FLUSH_ENABLE (1<<0)
Chia-I Wufe27c602014-01-28 13:29:33 +08001386#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
Jesse Barnesfb046852012-03-28 13:39:26 -07001387#define CACHE_MODE_1 0x7004 /* IVB+ */
Damien Lespiau5d708682014-03-26 18:41:51 +00001388#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1389#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
Jesse Barnesfb046852012-03-28 13:39:26 -07001390
Jesse Barnes4efe0702011-01-18 11:25:41 -08001391#define GEN6_BLITTER_ECOSKPD 0x221d0
1392#define GEN6_BLITTER_LOCK_SHIFT 16
1393#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1394
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001395#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
1396#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
Ville Syrjäläe4443e42014-04-09 13:28:41 +03001397#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
Ville Syrjälä295e8bb2014-02-27 21:59:01 +02001398
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001399#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
Chris Wilson12f55812012-07-05 17:14:01 +01001400#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1401#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1402#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1403#define GEN6_BSD_GO_INDICATOR (1 << 4)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001404
Ben Widawskycc609d52013-05-28 19:22:29 -07001405/* On modern GEN architectures interrupt control consists of two sets
1406 * of registers. The first set pertains to the ring generating the
1407 * interrupt. The second control is for the functional block generating the
1408 * interrupt. These are PM, GT, DE, etc.
1409 *
1410 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1411 * GT interrupt bits, so we don't need to duplicate the defines.
1412 *
1413 * These defines should cover us well from SNB->HSW with minor exceptions
1414 * it can also work on ILK.
1415 */
1416#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1417#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1418#define GT_BLT_USER_INTERRUPT (1 << 22)
1419#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1420#define GT_BSD_USER_INTERRUPT (1 << 12)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001421#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
Oscar Mateo73d477f2014-07-24 17:04:31 +01001422#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
Ben Widawskycc609d52013-05-28 19:22:29 -07001423#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1424#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1425#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1426#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1427#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1428#define GT_RENDER_USER_INTERRUPT (1 << 0)
1429
Ben Widawsky12638c52013-05-28 19:22:31 -07001430#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1431#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1432
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001433#define GT_PARITY_ERROR(dev) \
1434 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
Dan Carpenter45f80d52013-09-24 10:57:35 +03001435 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001436
Ben Widawskycc609d52013-05-28 19:22:29 -07001437/* These are all the "old" interrupts */
1438#define ILK_BSD_USER_INTERRUPT (1<<5)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001439
1440#define I915_PM_INTERRUPT (1<<31)
1441#define I915_ISP_INTERRUPT (1<<22)
1442#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1443#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
1444#define I915_MIPIB_INTERRUPT (1<<19)
1445#define I915_MIPIA_INTERRUPT (1<<18)
Ben Widawskycc609d52013-05-28 19:22:29 -07001446#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1447#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001448#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1449#define I915_MASTER_ERROR_INTERRUPT (1<<15)
Ben Widawskycc609d52013-05-28 19:22:29 -07001450#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001451#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
Ben Widawskycc609d52013-05-28 19:22:29 -07001452#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001453#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
Ben Widawskycc609d52013-05-28 19:22:29 -07001454#define I915_HWB_OOM_INTERRUPT (1<<13)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001455#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
Ben Widawskycc609d52013-05-28 19:22:29 -07001456#define I915_SYNC_STATUS_INTERRUPT (1<<12)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001457#define I915_MISC_INTERRUPT (1<<11)
Ben Widawskycc609d52013-05-28 19:22:29 -07001458#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001459#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
Ben Widawskycc609d52013-05-28 19:22:29 -07001460#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001461#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
Ben Widawskycc609d52013-05-28 19:22:29 -07001462#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001463#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
Ben Widawskycc609d52013-05-28 19:22:29 -07001464#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1465#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1466#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1467#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1468#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001469#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1470#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
Ben Widawskycc609d52013-05-28 19:22:29 -07001471#define I915_DEBUG_INTERRUPT (1<<2)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001472#define I915_WINVALID_INTERRUPT (1<<1)
Ben Widawskycc609d52013-05-28 19:22:29 -07001473#define I915_USER_INTERRUPT (1<<1)
1474#define I915_ASLE_INTERRUPT (1<<0)
Ville Syrjäläfac12f62014-04-09 13:28:06 +03001475#define I915_BSD_USER_INTERRUPT (1<<25)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001476
1477#define GEN6_BSD_RNCID 0x12198
1478
Ben Widawskya1e969e2012-04-14 18:41:32 -07001479#define GEN7_FF_THREAD_MODE 0x20a0
1480#define GEN7_FF_SCHED_MASK 0x0077070
Ben Widawskyab57fff2013-12-12 15:28:04 -08001481#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001482#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1483#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1484#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1485#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
Ben Widawsky41c0b3a2013-01-26 11:52:00 -08001486#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
Ben Widawskya1e969e2012-04-14 18:41:32 -07001487#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1488#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1489#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1490#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1491#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1492#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1493#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1494#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1495
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001496/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001497 * Framebuffer compression (915+ only)
1498 */
1499
1500#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1501#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1502#define FBC_CONTROL 0x03208
1503#define FBC_CTL_EN (1<<31)
1504#define FBC_CTL_PERIODIC (1<<30)
1505#define FBC_CTL_INTERVAL_SHIFT (16)
1506#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +02001507#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -07001508#define FBC_CTL_STRIDE_SHIFT (5)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001509#define FBC_CTL_FENCENO_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001510#define FBC_COMMAND 0x0320c
1511#define FBC_CMD_COMPRESS (1<<0)
1512#define FBC_STATUS 0x03210
1513#define FBC_STAT_COMPRESSING (1<<31)
1514#define FBC_STAT_COMPRESSED (1<<30)
1515#define FBC_STAT_MODIFIED (1<<29)
Ville Syrjälä82f34492013-11-28 17:29:55 +02001516#define FBC_STAT_CURRENT_LINE_SHIFT (0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001517#define FBC_CONTROL2 0x03214
1518#define FBC_CTL_FENCE_DBL (0<<4)
1519#define FBC_CTL_IDLE_IMM (0<<2)
1520#define FBC_CTL_IDLE_FULL (1<<2)
1521#define FBC_CTL_IDLE_LINE (2<<2)
1522#define FBC_CTL_IDLE_DEBUG (3<<2)
1523#define FBC_CTL_CPU_FENCE (1<<1)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001524#define FBC_CTL_PLANE(plane) ((plane)<<0)
Ville Syrjäläf64f1722014-01-23 16:49:17 +02001525#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
Jesse Barnes80824002009-09-10 15:28:06 -07001526#define FBC_TAG 0x03300
Jesse Barnes585fb112008-07-29 11:54:06 -07001527
1528#define FBC_LL_SIZE (1536)
1529
Jesse Barnes74dff282009-09-14 15:39:40 -07001530/* Framebuffer compression for GM45+ */
1531#define DPFC_CB_BASE 0x3200
1532#define DPFC_CONTROL 0x3208
1533#define DPFC_CTL_EN (1<<31)
Ville Syrjälä7f2cf222014-01-23 16:49:11 +02001534#define DPFC_CTL_PLANE(plane) ((plane)<<30)
1535#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
Jesse Barnes74dff282009-09-14 15:39:40 -07001536#define DPFC_CTL_FENCE_EN (1<<29)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001537#define IVB_DPFC_CTL_FENCE_EN (1<<28)
Chris Wilson9ce9d062011-07-08 12:22:40 +01001538#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -07001539#define DPFC_SR_EN (1<<10)
1540#define DPFC_CTL_LIMIT_1X (0<<6)
1541#define DPFC_CTL_LIMIT_2X (1<<6)
1542#define DPFC_CTL_LIMIT_4X (2<<6)
1543#define DPFC_RECOMP_CTL 0x320c
1544#define DPFC_RECOMP_STALL_EN (1<<27)
1545#define DPFC_RECOMP_STALL_WM_SHIFT (16)
1546#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1547#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1548#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1549#define DPFC_STATUS 0x3210
1550#define DPFC_INVAL_SEG_SHIFT (16)
1551#define DPFC_INVAL_SEG_MASK (0x07ff0000)
1552#define DPFC_COMP_SEG_SHIFT (0)
1553#define DPFC_COMP_SEG_MASK (0x000003ff)
1554#define DPFC_STATUS2 0x3214
1555#define DPFC_FENCE_YOFF 0x3218
1556#define DPFC_CHICKEN 0x3224
1557#define DPFC_HT_MODIFY (1<<31)
1558
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001559/* Framebuffer compression for Ironlake */
1560#define ILK_DPFC_CB_BASE 0x43200
1561#define ILK_DPFC_CONTROL 0x43208
Rodrigo Vivida46f932014-08-01 02:04:45 -07001562#define FBC_CTL_FALSE_COLOR (1<<10)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001563/* The bit 28-8 is reserved */
1564#define DPFC_RESERVED (0x1FFFFF00)
1565#define ILK_DPFC_RECOMP_CTL 0x4320c
1566#define ILK_DPFC_STATUS 0x43210
1567#define ILK_DPFC_FENCE_YOFF 0x43218
1568#define ILK_DPFC_CHICKEN 0x43224
1569#define ILK_FBC_RT_BASE 0x2128
1570#define ILK_FBC_RT_VALID (1<<0)
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001571#define SNB_FBC_FRONT_BUFFER (1<<1)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001572
1573#define ILK_DISPLAY_CHICKEN1 0x42000
1574#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -04001575#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +08001576
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001577
Jesse Barnes585fb112008-07-29 11:54:06 -07001578/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001579 * Framebuffer compression for Sandybridge
1580 *
1581 * The following two registers are of type GTTMMADR
1582 */
1583#define SNB_DPFC_CTL_SA 0x100100
1584#define SNB_CPU_FENCE_ENABLE (1<<29)
1585#define DPFC_CPU_FENCE_OFFSET 0x100104
1586
Rodrigo Viviabe959c2013-05-06 19:37:33 -03001587/* Framebuffer compression for Ivybridge */
1588#define IVB_FBC_RT_BASE 0x7020
1589
Paulo Zanoni42db64e2013-05-31 16:33:22 -03001590#define IPS_CTL 0x43408
1591#define IPS_ENABLE (1 << 31)
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001592
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03001593#define MSG_FBC_REND_STATE 0x50380
1594#define FBC_REND_NUKE (1<<2)
1595#define FBC_REND_CACHE_CLEAN (1<<1)
1596
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001597/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001598 * GPIO regs
1599 */
1600#define GPIOA 0x5010
1601#define GPIOB 0x5014
1602#define GPIOC 0x5018
1603#define GPIOD 0x501c
1604#define GPIOE 0x5020
1605#define GPIOF 0x5024
1606#define GPIOG 0x5028
1607#define GPIOH 0x502c
1608# define GPIO_CLOCK_DIR_MASK (1 << 0)
1609# define GPIO_CLOCK_DIR_IN (0 << 1)
1610# define GPIO_CLOCK_DIR_OUT (1 << 1)
1611# define GPIO_CLOCK_VAL_MASK (1 << 2)
1612# define GPIO_CLOCK_VAL_OUT (1 << 3)
1613# define GPIO_CLOCK_VAL_IN (1 << 4)
1614# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1615# define GPIO_DATA_DIR_MASK (1 << 8)
1616# define GPIO_DATA_DIR_IN (0 << 9)
1617# define GPIO_DATA_DIR_OUT (1 << 9)
1618# define GPIO_DATA_VAL_MASK (1 << 10)
1619# define GPIO_DATA_VAL_OUT (1 << 11)
1620# define GPIO_DATA_VAL_IN (1 << 12)
1621# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1622
Chris Wilsonf899fc62010-07-20 15:44:45 -07001623#define GMBUS0 0x5100 /* clock/port select */
1624#define GMBUS_RATE_100KHZ (0<<8)
1625#define GMBUS_RATE_50KHZ (1<<8)
1626#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1627#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1628#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1629#define GMBUS_PORT_DISABLED 0
1630#define GMBUS_PORT_SSC 1
1631#define GMBUS_PORT_VGADDC 2
1632#define GMBUS_PORT_PANEL 3
Ville Syrjäläc0c35322014-04-09 13:28:52 +03001633#define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */
Chris Wilsonf899fc62010-07-20 15:44:45 -07001634#define GMBUS_PORT_DPC 4 /* HDMIC */
1635#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
Daniel Kurtze4fd17a2012-03-28 02:36:12 +08001636#define GMBUS_PORT_DPD 6 /* HDMID */
1637#define GMBUS_PORT_RESERVED 7 /* 7 reserved */
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08001638#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
Chris Wilsonf899fc62010-07-20 15:44:45 -07001639#define GMBUS1 0x5104 /* command/status */
1640#define GMBUS_SW_CLR_INT (1<<31)
1641#define GMBUS_SW_RDY (1<<30)
1642#define GMBUS_ENT (1<<29) /* enable timeout */
1643#define GMBUS_CYCLE_NONE (0<<25)
1644#define GMBUS_CYCLE_WAIT (1<<25)
1645#define GMBUS_CYCLE_INDEX (2<<25)
1646#define GMBUS_CYCLE_STOP (4<<25)
1647#define GMBUS_BYTE_COUNT_SHIFT 16
1648#define GMBUS_SLAVE_INDEX_SHIFT 8
1649#define GMBUS_SLAVE_ADDR_SHIFT 1
1650#define GMBUS_SLAVE_READ (1<<0)
1651#define GMBUS_SLAVE_WRITE (0<<0)
1652#define GMBUS2 0x5108 /* status */
1653#define GMBUS_INUSE (1<<15)
1654#define GMBUS_HW_WAIT_PHASE (1<<14)
1655#define GMBUS_STALL_TIMEOUT (1<<13)
1656#define GMBUS_INT (1<<12)
1657#define GMBUS_HW_RDY (1<<11)
1658#define GMBUS_SATOER (1<<10)
1659#define GMBUS_ACTIVE (1<<9)
1660#define GMBUS3 0x510c /* data buffer bytes 3-0 */
1661#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1662#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1663#define GMBUS_NAK_EN (1<<3)
1664#define GMBUS_IDLE_EN (1<<2)
1665#define GMBUS_HW_WAIT_EN (1<<1)
1666#define GMBUS_HW_RDY_EN (1<<0)
1667#define GMBUS5 0x5120 /* byte index */
1668#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -08001669
Jesse Barnes585fb112008-07-29 11:54:06 -07001670/*
1671 * Clock control & power management
1672 */
Ville Syrjälä2d401b12014-04-09 13:29:08 +03001673#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
1674#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
1675#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
1676#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
Jesse Barnes585fb112008-07-29 11:54:06 -07001677
1678#define VGA0 0x6000
1679#define VGA1 0x6004
1680#define VGA_PD 0x6010
1681#define VGA0_PD_P2_DIV_4 (1 << 7)
1682#define VGA0_PD_P1_DIV_2 (1 << 5)
1683#define VGA0_PD_P1_SHIFT 0
1684#define VGA0_PD_P1_MASK (0x1f << 0)
1685#define VGA1_PD_P2_DIV_4 (1 << 15)
1686#define VGA1_PD_P1_DIV_2 (1 << 13)
1687#define VGA1_PD_P1_SHIFT 8
1688#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001689#define DPLL_VCO_ENABLE (1 << 31)
Daniel Vetter4a33e482013-07-06 12:52:05 +02001690#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1691#define DPLL_DVO_2X_MODE (1 << 30)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001692#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07001693#define DPLL_SYNCLOCK_ENABLE (1 << 29)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001694#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
Jesse Barnes585fb112008-07-29 11:54:06 -07001695#define DPLL_VGA_MODE_DIS (1 << 28)
1696#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1697#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1698#define DPLL_MODE_MASK (3 << 26)
1699#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1700#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1701#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1702#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1703#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1704#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001705#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07001706#define DPLL_LOCK_VLV (1<<15)
Daniel Vetter598fac62013-04-18 22:01:46 +02001707#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001708#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001709#define DPLL_SSC_REF_CLOCK_CHV (1<<13)
Daniel Vetter598fac62013-04-18 22:01:46 +02001710#define DPLL_PORTC_READY_MASK (0xf << 4)
1711#define DPLL_PORTB_READY_MASK (0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07001712
Jesse Barnes585fb112008-07-29 11:54:06 -07001713#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001714
1715/* Additional CHV pll/phy registers */
1716#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
1717#define DPLL_PORTD_READY_MASK (0xf)
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001718#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
Ville Syrjäläefd814b2014-06-27 19:52:13 +03001719#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001720#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
Ville Syrjäläefd814b2014-06-27 19:52:13 +03001721#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001722
Jesse Barnes585fb112008-07-29 11:54:06 -07001723/*
1724 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1725 * this field (only one bit may be set).
1726 */
1727#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1728#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001729#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -07001730/* i830, required in DVO non-gang */
1731#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1732#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1733#define PLL_REF_INPUT_DREFCLK (0 << 13)
1734#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1735#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1736#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1737#define PLL_REF_INPUT_MASK (3 << 13)
1738#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001739/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08001740# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1741# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1742# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1743# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1744# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1745
Jesse Barnes585fb112008-07-29 11:54:06 -07001746/*
1747 * Parallel to Serial Load Pulse phase selection.
1748 * Selects the phase for the 10X DPLL clock for the PCIe
1749 * digital display port. The range is 4 to 13; 10 or more
1750 * is just a flip delay. The default is 6
1751 */
1752#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1753#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1754/*
1755 * SDVO multiplier for 945G/GM. Not used on 965.
1756 */
1757#define SDVO_MULTIPLIER_MASK 0x000000ff
1758#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1759#define SDVO_MULTIPLIER_SHIFT_VGA 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001760
Ville Syrjälä2d401b12014-04-09 13:29:08 +03001761#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
1762#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
1763#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
1764#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001765
Jesse Barnes585fb112008-07-29 11:54:06 -07001766/*
1767 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1768 *
1769 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1770 */
1771#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1772#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1773/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1774#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1775#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1776/*
1777 * SDVO/UDI pixel multiplier.
1778 *
1779 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1780 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1781 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1782 * dummy bytes in the datastream at an increased clock rate, with both sides of
1783 * the link knowing how many bytes are fill.
1784 *
1785 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1786 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1787 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1788 * through an SDVO command.
1789 *
1790 * This register field has values of multiplication factor minus 1, with
1791 * a maximum multiplier of 5 for SDVO.
1792 */
1793#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1794#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1795/*
1796 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1797 * This best be set to the default value (3) or the CRT won't work. No,
1798 * I don't entirely understand what this does...
1799 */
1800#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1801#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07001802
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001803#define _FPA0 0x06040
1804#define _FPA1 0x06044
1805#define _FPB0 0x06048
1806#define _FPB1 0x0604c
1807#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1808#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -07001809#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001810#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -07001811#define FP_N_DIV_SHIFT 16
1812#define FP_M1_DIV_MASK 0x00003f00
1813#define FP_M1_DIV_SHIFT 8
1814#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001815#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -07001816#define FP_M2_DIV_SHIFT 0
1817#define DPLL_TEST 0x606c
1818#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1819#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1820#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1821#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1822#define DPLLB_TEST_N_BYPASS (1 << 19)
1823#define DPLLB_TEST_M_BYPASS (1 << 18)
1824#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1825#define DPLLA_TEST_N_BYPASS (1 << 3)
1826#define DPLLA_TEST_M_BYPASS (1 << 2)
1827#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1828#define D_STATE 0x6104
Chris Wilsondc96e9b2010-10-01 12:05:06 +01001829#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -07001830#define DSTATE_PLL_D3_OFF (1<<3)
1831#define DSTATE_GFX_CLOCK_GATING (1<<1)
1832#define DSTATE_DOT_CLOCK_GATING (1<<0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001833#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
Jesse Barnes652c3932009-08-17 13:31:43 -07001834# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1835# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1836# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1837# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1838# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1839# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1840# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1841# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1842# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1843# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1844# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1845# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1846# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1847# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1848# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1849# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1850# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1851# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1852# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1853# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1854# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1855# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1856# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1857# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1858# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1859# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1860# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1861# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001862/*
Jesse Barnes652c3932009-08-17 13:31:43 -07001863 * This bit must be set on the 830 to prevent hangs when turning off the
1864 * overlay scaler.
1865 */
1866# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1867# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1868# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1869# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1870# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1871
1872#define RENCLK_GATE_D1 0x6204
1873# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1874# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1875# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1876# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1877# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1878# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1879# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1880# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1881# define MAG_CLOCK_GATE_DISABLE (1 << 5)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001882/* This bit must be unset on 855,865 */
Jesse Barnes652c3932009-08-17 13:31:43 -07001883# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1884# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1885# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1886# define MECO_CLOCK_GATE_DISABLE (1 << 1)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001887/* This bit must be set on 855,865. */
Jesse Barnes652c3932009-08-17 13:31:43 -07001888# define SV_CLOCK_GATE_DISABLE (1 << 0)
1889# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1890# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1891# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1892# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1893# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1894# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1895# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1896# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1897# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1898# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1899# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1900# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1901# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1902# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1903# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1904# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1905# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1906
1907# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001908/* This bit must always be set on 965G/965GM */
Jesse Barnes652c3932009-08-17 13:31:43 -07001909# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1910# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1911# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1912# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1913# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1914# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03001915/* This bit must always be set on 965G */
Jesse Barnes652c3932009-08-17 13:31:43 -07001916# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1917# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1918# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1919# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1920# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1921# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1922# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1923# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1924# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1925# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1926# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1927# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1928# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1929# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1930# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1931# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1932# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1933# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1934# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1935
1936#define RENCLK_GATE_D2 0x6208
1937#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1938#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1939#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
Ville Syrjäläfa4f53c2014-05-19 19:23:27 +03001940
1941#define VDECCLK_GATE_D 0x620C /* g4x only */
1942#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
1943
Jesse Barnes652c3932009-08-17 13:31:43 -07001944#define RAMCLK_GATE_D 0x6210 /* CRL only */
1945#define DEUC 0x6214 /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001946
Ville Syrjäläd88b2272013-01-24 15:29:48 +02001947#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
Jesse Barnesceb04242012-03-28 13:39:22 -07001948#define FW_CSPWRDWNEN (1<<15)
1949
Ville Syrjäläe0d8d592013-06-12 22:11:18 +03001950#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1951
Chon Ming Lee24eb2d52013-09-27 15:31:00 +08001952#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
1953#define CDCLK_FREQ_SHIFT 4
1954#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1955#define CZCLK_FREQ_MASK 0xf
1956#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
1957
Jesse Barnes585fb112008-07-29 11:54:06 -07001958/*
1959 * Palette regs
1960 */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02001961#define PALETTE_A_OFFSET 0xa000
1962#define PALETTE_B_OFFSET 0xa800
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03001963#define CHV_PALETTE_C_OFFSET 0xc000
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001964#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
1965 dev_priv->info.display_mmio_offset)
Jesse Barnes585fb112008-07-29 11:54:06 -07001966
Eric Anholt673a3942008-07-30 12:06:12 -07001967/* MCH MMIO space */
1968
1969/*
1970 * MCHBAR mirror.
1971 *
1972 * This mirrors the MCHBAR MMIO space whose location is determined by
1973 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1974 * every way. It is not accessible from the CP register read instructions.
1975 *
Paulo Zanoni515b2392013-09-10 19:36:37 -03001976 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
1977 * just read.
Eric Anholt673a3942008-07-30 12:06:12 -07001978 */
1979#define MCHBAR_MIRROR_BASE 0x10000
1980
Yuanhan Liu13982612010-12-15 15:42:31 +08001981#define MCHBAR_MIRROR_BASE_SNB 0x140000
1982
Chris Wilson3ebecd02013-04-12 19:10:13 +01001983/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
Ben Widawsky153b4b952013-10-22 22:05:09 -07001984#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
Chris Wilson3ebecd02013-04-12 19:10:13 +01001985
Ville Syrjälä646b4262014-04-25 20:14:30 +03001986/* 915-945 and GM965 MCH register controlling DRAM channel access */
Eric Anholt673a3942008-07-30 12:06:12 -07001987#define DCC 0x10200
1988#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1989#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1990#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1991#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1992#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08001993#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Eric Anholt673a3942008-07-30 12:06:12 -07001994
Ville Syrjälä646b4262014-04-25 20:14:30 +03001995/* Pineview MCH register contains DDR3 setting */
Li Peng95534262010-05-18 18:58:44 +08001996#define CSHRDDR3CTL 0x101a8
1997#define CSHRDDR3CTL_DDR3 (1 << 2)
1998
Ville Syrjälä646b4262014-04-25 20:14:30 +03001999/* 965 MCH register controlling DRAM channel configuration */
Eric Anholt673a3942008-07-30 12:06:12 -07002000#define C0DRB3 0x10206
2001#define C1DRB3 0x10606
2002
Ville Syrjälä646b4262014-04-25 20:14:30 +03002003/* snb MCH registers for reading the DRAM channel configuration */
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002004#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
2005#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
2006#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
2007#define MAD_DIMM_ECC_MASK (0x3 << 24)
2008#define MAD_DIMM_ECC_OFF (0x0 << 24)
2009#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2010#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2011#define MAD_DIMM_ECC_ON (0x3 << 24)
2012#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2013#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2014#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2015#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2016#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2017#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2018#define MAD_DIMM_A_SELECT (0x1 << 16)
2019/* DIMM sizes are in multiples of 256mb. */
2020#define MAD_DIMM_B_SIZE_SHIFT 8
2021#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2022#define MAD_DIMM_A_SIZE_SHIFT 0
2023#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2024
Ville Syrjälä646b4262014-04-25 20:14:30 +03002025/* snb MCH registers for priority tuning */
Daniel Vetter1d7aaa02013-02-09 21:03:42 +01002026#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2027#define MCH_SSKPD_WM0_MASK 0x3f
2028#define MCH_SSKPD_WM0_VAL 0xc
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002029
Jesse Barnesec013e72013-08-20 10:29:23 +01002030#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
2031
Keith Packardb11248d2009-06-11 22:28:56 -07002032/* Clocking configuration register */
2033#define CLKCFG 0x10c00
Shaohua Li7662c8b2009-06-26 11:23:55 +08002034#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07002035#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2036#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2037#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2038#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2039#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002040/* Note, below two are guess */
Keith Packardb11248d2009-06-11 22:28:56 -07002041#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002042#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07002043#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002044#define CLKCFG_MEM_533 (1 << 4)
2045#define CLKCFG_MEM_667 (2 << 4)
2046#define CLKCFG_MEM_800 (3 << 4)
2047#define CLKCFG_MEM_MASK (7 << 4)
2048
Jesse Barnesea056c12010-09-10 10:02:13 -07002049#define TSC1 0x11001
2050#define TSE (1<<0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07002051#define TR1 0x11006
2052#define TSFS 0x11020
2053#define TSFS_SLOPE_MASK 0x0000ff00
2054#define TSFS_SLOPE_SHIFT 8
2055#define TSFS_INTR_MASK 0x000000ff
2056
Jesse Barnesf97108d2010-01-29 11:27:07 -08002057#define CRSTANDVID 0x11100
2058#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2059#define PXVFREQ_PX_MASK 0x7f000000
2060#define PXVFREQ_PX_SHIFT 24
2061#define VIDFREQ_BASE 0x11110
2062#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2063#define VIDFREQ2 0x11114
2064#define VIDFREQ3 0x11118
2065#define VIDFREQ4 0x1111c
2066#define VIDFREQ_P0_MASK 0x1f000000
2067#define VIDFREQ_P0_SHIFT 24
2068#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2069#define VIDFREQ_P0_CSCLK_SHIFT 20
2070#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2071#define VIDFREQ_P0_CRCLK_SHIFT 16
2072#define VIDFREQ_P1_MASK 0x00001f00
2073#define VIDFREQ_P1_SHIFT 8
2074#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2075#define VIDFREQ_P1_CSCLK_SHIFT 4
2076#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2077#define INTTOEXT_BASE_ILK 0x11300
2078#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2079#define INTTOEXT_MAP3_SHIFT 24
2080#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2081#define INTTOEXT_MAP2_SHIFT 16
2082#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2083#define INTTOEXT_MAP1_SHIFT 8
2084#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2085#define INTTOEXT_MAP0_SHIFT 0
2086#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2087#define MEMSWCTL 0x11170 /* Ironlake only */
2088#define MEMCTL_CMD_MASK 0xe000
2089#define MEMCTL_CMD_SHIFT 13
2090#define MEMCTL_CMD_RCLK_OFF 0
2091#define MEMCTL_CMD_RCLK_ON 1
2092#define MEMCTL_CMD_CHFREQ 2
2093#define MEMCTL_CMD_CHVID 3
2094#define MEMCTL_CMD_VMMOFF 4
2095#define MEMCTL_CMD_VMMON 5
2096#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2097 when command complete */
2098#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2099#define MEMCTL_FREQ_SHIFT 8
2100#define MEMCTL_SFCAVM (1<<7)
2101#define MEMCTL_TGT_VID_MASK 0x007f
2102#define MEMIHYST 0x1117c
2103#define MEMINTREN 0x11180 /* 16 bits */
2104#define MEMINT_RSEXIT_EN (1<<8)
2105#define MEMINT_CX_SUPR_EN (1<<7)
2106#define MEMINT_CONT_BUSY_EN (1<<6)
2107#define MEMINT_AVG_BUSY_EN (1<<5)
2108#define MEMINT_EVAL_CHG_EN (1<<4)
2109#define MEMINT_MON_IDLE_EN (1<<3)
2110#define MEMINT_UP_EVAL_EN (1<<2)
2111#define MEMINT_DOWN_EVAL_EN (1<<1)
2112#define MEMINT_SW_CMD_EN (1<<0)
2113#define MEMINTRSTR 0x11182 /* 16 bits */
2114#define MEM_RSEXIT_MASK 0xc000
2115#define MEM_RSEXIT_SHIFT 14
2116#define MEM_CONT_BUSY_MASK 0x3000
2117#define MEM_CONT_BUSY_SHIFT 12
2118#define MEM_AVG_BUSY_MASK 0x0c00
2119#define MEM_AVG_BUSY_SHIFT 10
2120#define MEM_EVAL_CHG_MASK 0x0300
2121#define MEM_EVAL_BUSY_SHIFT 8
2122#define MEM_MON_IDLE_MASK 0x00c0
2123#define MEM_MON_IDLE_SHIFT 6
2124#define MEM_UP_EVAL_MASK 0x0030
2125#define MEM_UP_EVAL_SHIFT 4
2126#define MEM_DOWN_EVAL_MASK 0x000c
2127#define MEM_DOWN_EVAL_SHIFT 2
2128#define MEM_SW_CMD_MASK 0x0003
2129#define MEM_INT_STEER_GFX 0
2130#define MEM_INT_STEER_CMR 1
2131#define MEM_INT_STEER_SMI 2
2132#define MEM_INT_STEER_SCI 3
2133#define MEMINTRSTS 0x11184
2134#define MEMINT_RSEXIT (1<<7)
2135#define MEMINT_CONT_BUSY (1<<6)
2136#define MEMINT_AVG_BUSY (1<<5)
2137#define MEMINT_EVAL_CHG (1<<4)
2138#define MEMINT_MON_IDLE (1<<3)
2139#define MEMINT_UP_EVAL (1<<2)
2140#define MEMINT_DOWN_EVAL (1<<1)
2141#define MEMINT_SW_CMD (1<<0)
2142#define MEMMODECTL 0x11190
2143#define MEMMODE_BOOST_EN (1<<31)
2144#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2145#define MEMMODE_BOOST_FREQ_SHIFT 24
2146#define MEMMODE_IDLE_MODE_MASK 0x00030000
2147#define MEMMODE_IDLE_MODE_SHIFT 16
2148#define MEMMODE_IDLE_MODE_EVAL 0
2149#define MEMMODE_IDLE_MODE_CONT 1
2150#define MEMMODE_HWIDLE_EN (1<<15)
2151#define MEMMODE_SWMODE_EN (1<<14)
2152#define MEMMODE_RCLK_GATE (1<<13)
2153#define MEMMODE_HW_UPDATE (1<<12)
2154#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2155#define MEMMODE_FSTART_SHIFT 8
2156#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2157#define MEMMODE_FMAX_SHIFT 4
2158#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2159#define RCBMAXAVG 0x1119c
2160#define MEMSWCTL2 0x1119e /* Cantiga only */
2161#define SWMEMCMD_RENDER_OFF (0 << 13)
2162#define SWMEMCMD_RENDER_ON (1 << 13)
2163#define SWMEMCMD_SWFREQ (2 << 13)
2164#define SWMEMCMD_TARVID (3 << 13)
2165#define SWMEMCMD_VRM_OFF (4 << 13)
2166#define SWMEMCMD_VRM_ON (5 << 13)
2167#define CMDSTS (1<<12)
2168#define SFCAVM (1<<11)
2169#define SWFREQ_MASK 0x0380 /* P0-7 */
2170#define SWFREQ_SHIFT 7
2171#define TARVID_MASK 0x001f
2172#define MEMSTAT_CTG 0x111a0
2173#define RCBMINAVG 0x111a0
2174#define RCUPEI 0x111b0
2175#define RCDNEI 0x111b4
Jesse Barnes88271da2011-01-05 12:01:24 -08002176#define RSTDBYCTL 0x111b8
2177#define RS1EN (1<<31)
2178#define RS2EN (1<<30)
2179#define RS3EN (1<<29)
2180#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2181#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2182#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2183#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2184#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2185#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2186#define RSX_STATUS_MASK (7<<20)
2187#define RSX_STATUS_ON (0<<20)
2188#define RSX_STATUS_RC1 (1<<20)
2189#define RSX_STATUS_RC1E (2<<20)
2190#define RSX_STATUS_RS1 (3<<20)
2191#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2192#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2193#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2194#define RSX_STATUS_RSVD2 (7<<20)
2195#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2196#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2197#define JRSC (1<<17) /* rsx coupled to cpu c-state */
2198#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2199#define RS1CONTSAV_MASK (3<<14)
2200#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2201#define RS1CONTSAV_RSVD (1<<14)
2202#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2203#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2204#define NORMSLEXLAT_MASK (3<<12)
2205#define SLOW_RS123 (0<<12)
2206#define SLOW_RS23 (1<<12)
2207#define SLOW_RS3 (2<<12)
2208#define NORMAL_RS123 (3<<12)
2209#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2210#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2211#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2212#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2213#define RS_CSTATE_MASK (3<<4)
2214#define RS_CSTATE_C367_RS1 (0<<4)
2215#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2216#define RS_CSTATE_RSVD (2<<4)
2217#define RS_CSTATE_C367_RS2 (3<<4)
2218#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2219#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Jesse Barnesf97108d2010-01-29 11:27:07 -08002220#define VIDCTL 0x111c0
2221#define VIDSTS 0x111c8
2222#define VIDSTART 0x111cc /* 8 bits */
2223#define MEMSTAT_ILK 0x111f8
2224#define MEMSTAT_VID_MASK 0x7f00
2225#define MEMSTAT_VID_SHIFT 8
2226#define MEMSTAT_PSTATE_MASK 0x00f8
2227#define MEMSTAT_PSTATE_SHIFT 3
2228#define MEMSTAT_MON_ACTV (1<<2)
2229#define MEMSTAT_SRC_CTL_MASK 0x0003
2230#define MEMSTAT_SRC_CTL_CORE 0
2231#define MEMSTAT_SRC_CTL_TRB 1
2232#define MEMSTAT_SRC_CTL_THM 2
2233#define MEMSTAT_SRC_CTL_STDBY 3
2234#define RCPREVBSYTUPAVG 0x113b8
2235#define RCPREVBSYTDNAVG 0x113bc
Jesse Barnesea056c12010-09-10 10:02:13 -07002236#define PMMISC 0x11214
2237#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Jesse Barnes7648fa92010-05-20 14:28:11 -07002238#define SDEW 0x1124c
2239#define CSIEW0 0x11250
2240#define CSIEW1 0x11254
2241#define CSIEW2 0x11258
2242#define PEW 0x1125c
2243#define DEW 0x11270
2244#define MCHAFE 0x112c0
2245#define CSIEC 0x112e0
2246#define DMIEC 0x112e4
2247#define DDREC 0x112e8
2248#define PEG0EC 0x112ec
2249#define PEG1EC 0x112f0
2250#define GFXEC 0x112f4
2251#define RPPREVBSYTUPAVG 0x113b8
2252#define RPPREVBSYTDNAVG 0x113bc
2253#define ECR 0x11600
2254#define ECR_GPFE (1<<31)
2255#define ECR_IMONE (1<<30)
2256#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2257#define OGW0 0x11608
2258#define OGW1 0x1160c
2259#define EG0 0x11610
2260#define EG1 0x11614
2261#define EG2 0x11618
2262#define EG3 0x1161c
2263#define EG4 0x11620
2264#define EG5 0x11624
2265#define EG6 0x11628
2266#define EG7 0x1162c
2267#define PXW 0x11664
2268#define PXWL 0x11680
2269#define LCFUSE02 0x116c0
2270#define LCFUSE_HIV_MASK 0x000000ff
2271#define CSIPLL0 0x12c10
2272#define DDRMPLL1 0X12c20
Eric Anholt7d573822009-01-02 13:33:00 -08002273#define PEG_BAND_GAP_DATA 0x14d68
2274
Chris Wilsonc4de7b02012-07-02 11:51:03 -03002275#define GEN6_GT_THREAD_STATUS_REG 0x13805c
2276#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2277#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
2278
Ben Widawsky153b4b952013-10-22 22:05:09 -07002279#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
2280#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2281#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002282
Jesse Barnes585fb112008-07-29 11:54:06 -07002283/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002284 * Logical Context regs
2285 */
2286#define CCID 0x2180
2287#define CCID_EN (1<<0)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002288/*
2289 * Notes on SNB/IVB/VLV context size:
2290 * - Power context is saved elsewhere (LLC or stolen)
2291 * - Ring/execlist context is saved on SNB, not on IVB
2292 * - Extended context size already includes render context size
2293 * - We always need to follow the extended context size.
2294 * SNB BSpec has comments indicating that we should use the
2295 * render context size instead if execlists are disabled, but
2296 * based on empirical testing that's just nonsense.
2297 * - Pipelined/VF state is saved on SNB/IVB respectively
2298 * - GT1 size just indicates how much of render context
2299 * doesn't need saving on GT1
2300 */
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002301#define CXT_SIZE 0x21a0
2302#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
2303#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
2304#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
2305#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
2306#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002307#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
Ben Widawskyfe1cc682012-06-04 14:42:41 -07002308 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2309 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002310#define GEN7_CXT_SIZE 0x21a8
Ben Widawsky6a4ea122012-07-18 10:10:10 -07002311#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
2312#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002313#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
2314#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
2315#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
2316#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
Ville Syrjäläe8016052013-08-22 19:23:13 +03002317#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
Ben Widawsky4f91dd62012-07-18 10:10:09 -07002318 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
Ben Widawskya0de80a2013-06-25 21:53:40 -07002319/* Haswell does have the CXT_SIZE register however it does not appear to be
2320 * valid. Now, docs explain in dwords what is in the context object. The full
2321 * size is 70720 bytes, however, the power context and execlist context will
2322 * never be saved (power context is stored elsewhere, and execlists don't work
2323 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
2324 */
2325#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
Ben Widawsky88976442013-11-02 21:07:05 -07002326/* Same as Haswell, but 72064 bytes now. */
2327#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2328
Mika Kuoppala542a6b22014-07-09 14:55:56 +03002329#define CHV_CLK_CTL1 0x101100
Jesse Barnese454a052013-09-26 17:55:58 -07002330#define VLV_CLK_CTL2 0x101104
2331#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2332
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08002333/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002334 * Overlay regs
2335 */
2336
2337#define OVADD 0x30000
2338#define DOVSTA 0x30008
2339#define OC_BUF (0x3<<20)
2340#define OGAMC5 0x30010
2341#define OGAMC4 0x30014
2342#define OGAMC3 0x30018
2343#define OGAMC2 0x3001c
2344#define OGAMC1 0x30020
2345#define OGAMC0 0x30024
2346
2347/*
2348 * Display engine regs
2349 */
2350
Shuang He8bf1e9f2013-10-15 18:55:27 +01002351/* Pipe A CRC regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002352#define _PIPE_CRC_CTL_A 0x60050
Shuang He8bf1e9f2013-10-15 18:55:27 +01002353#define PIPE_CRC_ENABLE (1 << 31)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002354/* ivb+ source selection */
Shuang He8bf1e9f2013-10-15 18:55:27 +01002355#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2356#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2357#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002358/* ilk+ source selection */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002359#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2360#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2361#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2362/* embedded DP port on the north display block, reserved on ivb */
2363#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2364#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
Daniel Vetterb4437a42013-10-16 22:55:54 +02002365/* vlv source selection */
2366#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2367#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2368#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2369/* with DP port the pipe source is invalid */
2370#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2371#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2372#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2373/* gen3+ source selection */
2374#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2375#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2376#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2377/* with DP/TV port the pipe source is invalid */
2378#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2379#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2380#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2381#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2382#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2383/* gen2 doesn't have source selection bits */
Daniel Vetter52f843f2013-10-21 17:26:38 +02002384#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
Daniel Vetterb4437a42013-10-16 22:55:54 +02002385
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002386#define _PIPE_CRC_RES_1_A_IVB 0x60064
2387#define _PIPE_CRC_RES_2_A_IVB 0x60068
2388#define _PIPE_CRC_RES_3_A_IVB 0x6006c
2389#define _PIPE_CRC_RES_4_A_IVB 0x60070
2390#define _PIPE_CRC_RES_5_A_IVB 0x60074
2391
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002392#define _PIPE_CRC_RES_RED_A 0x60060
2393#define _PIPE_CRC_RES_GREEN_A 0x60064
2394#define _PIPE_CRC_RES_BLUE_A 0x60068
2395#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2396#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
Shuang He8bf1e9f2013-10-15 18:55:27 +01002397
2398/* Pipe B CRC regs */
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002399#define _PIPE_CRC_RES_1_B_IVB 0x61064
2400#define _PIPE_CRC_RES_2_B_IVB 0x61068
2401#define _PIPE_CRC_RES_3_B_IVB 0x6106c
2402#define _PIPE_CRC_RES_4_B_IVB 0x61070
2403#define _PIPE_CRC_RES_5_B_IVB 0x61074
Shuang He8bf1e9f2013-10-15 18:55:27 +01002404
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002405#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002406#define PIPE_CRC_RES_1_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002407 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002408#define PIPE_CRC_RES_2_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002409 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002410#define PIPE_CRC_RES_3_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002411 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002412#define PIPE_CRC_RES_4_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002413 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002414#define PIPE_CRC_RES_5_IVB(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002415 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002416
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002417#define PIPE_CRC_RES_RED(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002418 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002419#define PIPE_CRC_RES_GREEN(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002420 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002421#define PIPE_CRC_RES_BLUE(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002422 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002423#define PIPE_CRC_RES_RES1_I915(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002424 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02002425#define PIPE_CRC_RES_RES2_G4X(pipe) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002426 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
Daniel Vetter5a6b5c82013-10-16 22:55:47 +02002427
Jesse Barnes585fb112008-07-29 11:54:06 -07002428/* Pipe A timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002429#define _HTOTAL_A 0x60000
2430#define _HBLANK_A 0x60004
2431#define _HSYNC_A 0x60008
2432#define _VTOTAL_A 0x6000c
2433#define _VBLANK_A 0x60010
2434#define _VSYNC_A 0x60014
2435#define _PIPEASRC 0x6001c
2436#define _BCLRPAT_A 0x60020
2437#define _VSYNCSHIFT_A 0x60028
Jesse Barnes585fb112008-07-29 11:54:06 -07002438
2439/* Pipe B timing regs */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002440#define _HTOTAL_B 0x61000
2441#define _HBLANK_B 0x61004
2442#define _HSYNC_B 0x61008
2443#define _VTOTAL_B 0x6100c
2444#define _VBLANK_B 0x61010
2445#define _VSYNC_B 0x61014
2446#define _PIPEBSRC 0x6101c
2447#define _BCLRPAT_B 0x61020
2448#define _VSYNCSHIFT_B 0x61028
Daniel Vetter0529a0d2012-01-28 14:49:24 +01002449
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002450#define TRANSCODER_A_OFFSET 0x60000
2451#define TRANSCODER_B_OFFSET 0x61000
2452#define TRANSCODER_C_OFFSET 0x62000
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03002453#define CHV_TRANSCODER_C_OFFSET 0x63000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002454#define TRANSCODER_EDP_OFFSET 0x6f000
2455
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002456#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2457 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2458 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02002459
2460#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2461#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2462#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2463#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2464#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2465#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2466#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2467#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2468#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002469
Ben Widawskyed8546a2013-11-04 22:45:05 -08002470/* HSW+ eDP PSR registers */
2471#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
Ben Widawsky18b59922013-09-20 09:35:30 -07002472#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002473#define EDP_PSR_ENABLE (1<<31)
Rodrigo Vivi82c56252014-06-12 10:16:42 -07002474#define BDW_PSR_SINGLE_FRAME (1<<30)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002475#define EDP_PSR_LINK_DISABLE (0<<27)
2476#define EDP_PSR_LINK_STANDBY (1<<27)
2477#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
2478#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
2479#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
2480#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
2481#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
2482#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2483#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2484#define EDP_PSR_TP1_TP2_SEL (0<<11)
2485#define EDP_PSR_TP1_TP3_SEL (1<<11)
2486#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2487#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2488#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2489#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2490#define EDP_PSR_TP1_TIME_500us (0<<4)
2491#define EDP_PSR_TP1_TIME_100us (1<<4)
2492#define EDP_PSR_TP1_TIME_2500us (2<<4)
2493#define EDP_PSR_TP1_TIME_0us (3<<4)
2494#define EDP_PSR_IDLE_FRAME_SHIFT 0
2495
Ben Widawsky18b59922013-09-20 09:35:30 -07002496#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2497#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002498#define EDP_PSR_DPCD_COMMAND 0x80060000
Ben Widawsky18b59922013-09-20 09:35:30 -07002499#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002500#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
Ben Widawsky18b59922013-09-20 09:35:30 -07002501#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2502#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2503#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002504
Ben Widawsky18b59922013-09-20 09:35:30 -07002505#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002506#define EDP_PSR_STATUS_STATE_MASK (7<<29)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002507#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2508#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2509#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2510#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2511#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2512#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2513#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2514#define EDP_PSR_STATUS_LINK_MASK (3<<26)
2515#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2516#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2517#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2518#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2519#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2520#define EDP_PSR_STATUS_COUNT_SHIFT 16
2521#define EDP_PSR_STATUS_COUNT_MASK 0xf
2522#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2523#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2524#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2525#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2526#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2527#define EDP_PSR_STATUS_IDLE_MASK 0xf
2528
Ben Widawsky18b59922013-09-20 09:35:30 -07002529#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002530#define EDP_PSR_PERF_CNT_MASK 0xffffff
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002531
Ben Widawsky18b59922013-09-20 09:35:30 -07002532#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002533#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2534#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2535#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2536
Jesse Barnes585fb112008-07-29 11:54:06 -07002537/* VGA port control */
2538#define ADPA 0x61100
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002539#define PCH_ADPA 0xe1100
Daniel Vetter540a8952012-07-11 16:27:57 +02002540#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002541
Jesse Barnes585fb112008-07-29 11:54:06 -07002542#define ADPA_DAC_ENABLE (1<<31)
2543#define ADPA_DAC_DISABLE 0
2544#define ADPA_PIPE_SELECT_MASK (1<<30)
2545#define ADPA_PIPE_A_SELECT 0
2546#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07002547#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Daniel Vetterebc0fd82012-07-11 16:27:56 +02002548/* CPT uses bits 29:30 for pch transcoder select */
2549#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2550#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2551#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2552#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2553#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2554#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2555#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2556#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2557#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2558#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2559#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2560#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2561#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2562#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2563#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2564#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2565#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2566#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2567#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07002568#define ADPA_USE_VGA_HVPOLARITY (1<<15)
2569#define ADPA_SETS_HVPOLARITY 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002570#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07002571#define ADPA_VSYNC_CNTL_ENABLE 0
Patrik Jakobsson60222c02013-03-05 19:09:37 +01002572#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07002573#define ADPA_HSYNC_CNTL_ENABLE 0
2574#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2575#define ADPA_VSYNC_ACTIVE_LOW 0
2576#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2577#define ADPA_HSYNC_ACTIVE_LOW 0
2578#define ADPA_DPMS_MASK (~(3<<10))
2579#define ADPA_DPMS_ON (0<<10)
2580#define ADPA_DPMS_SUSPEND (1<<10)
2581#define ADPA_DPMS_STANDBY (2<<10)
2582#define ADPA_DPMS_OFF (3<<10)
2583
Chris Wilson939fe4d2010-10-09 10:33:26 +01002584
Jesse Barnes585fb112008-07-29 11:54:06 -07002585/* Hotplug control (945+ only) */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002586#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
Daniel Vetter26739f12013-02-07 12:42:32 +01002587#define PORTB_HOTPLUG_INT_EN (1 << 29)
2588#define PORTC_HOTPLUG_INT_EN (1 << 28)
2589#define PORTD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07002590#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2591#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2592#define TV_HOTPLUG_INT_EN (1 << 18)
2593#define CRT_HOTPLUG_INT_EN (1 << 9)
Egbert Eiche5868a32013-02-28 04:17:12 -05002594#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2595 PORTC_HOTPLUG_INT_EN | \
2596 PORTD_HOTPLUG_INT_EN | \
2597 SDVOC_HOTPLUG_INT_EN | \
2598 SDVOB_HOTPLUG_INT_EN | \
2599 CRT_HOTPLUG_INT_EN)
Jesse Barnes585fb112008-07-29 11:54:06 -07002600#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08002601#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2602/* must use period 64 on GM45 according to docs */
2603#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2604#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2605#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2606#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2607#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2608#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2609#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2610#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2611#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2612#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2613#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2614#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002615
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002616#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
Daniel Vetter0ce99f72013-07-26 11:27:49 +02002617/*
2618 * HDMI/DP bits are gen4+
2619 *
2620 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2621 * Please check the detailed lore in the commit message for for experimental
2622 * evidence.
2623 */
Todd Previte232a6ee2014-01-23 00:13:41 -07002624#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2625#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2626#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2627/* VLV DP/HDMI bits again match Bspec */
2628#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2629#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2630#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
Daniel Vetter26739f12013-02-07 12:42:32 +01002631#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
Daniel Vettera211b492014-06-05 09:36:23 +02002632#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2633#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
Daniel Vetter26739f12013-02-07 12:42:32 +01002634#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
Daniel Vettera211b492014-06-05 09:36:23 +02002635#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2636#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
Daniel Vetter26739f12013-02-07 12:42:32 +01002637#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
Daniel Vettera211b492014-06-05 09:36:23 +02002638#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2639#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
Chris Wilson084b6122012-05-11 18:01:33 +01002640/* CRT/TV common between gen3+ */
Jesse Barnes585fb112008-07-29 11:54:06 -07002641#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2642#define TV_HOTPLUG_INT_STATUS (1 << 10)
2643#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2644#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2645#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2646#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
Daniel Vetter4aeebd72013-10-31 09:53:36 +01002647#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2648#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2649#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
Imre Deakbfbdb422014-01-16 19:56:53 +02002650#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2651
Chris Wilson084b6122012-05-11 18:01:33 +01002652/* SDVO is different across gen3/4 */
2653#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2654#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
Daniel Vetter4f7fd702013-06-24 21:33:28 +02002655/*
2656 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2657 * since reality corrobates that they're the same as on gen3. But keep these
2658 * bits here (and the comment!) to help any other lost wanderers back onto the
2659 * right tracks.
2660 */
Chris Wilson084b6122012-05-11 18:01:33 +01002661#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2662#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2663#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2664#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05002665#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2666 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2667 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2668 PORTB_HOTPLUG_INT_STATUS | \
2669 PORTC_HOTPLUG_INT_STATUS | \
2670 PORTD_HOTPLUG_INT_STATUS)
2671
Egbert Eiche5868a32013-02-28 04:17:12 -05002672#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2673 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2674 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2675 PORTB_HOTPLUG_INT_STATUS | \
2676 PORTC_HOTPLUG_INT_STATUS | \
2677 PORTD_HOTPLUG_INT_STATUS)
Jesse Barnes585fb112008-07-29 11:54:06 -07002678
Paulo Zanonic20cd312013-02-19 16:21:45 -03002679/* SDVO and HDMI port control.
2680 * The same register may be used for SDVO or HDMI */
2681#define GEN3_SDVOB 0x61140
2682#define GEN3_SDVOC 0x61160
2683#define GEN4_HDMIB GEN3_SDVOB
2684#define GEN4_HDMIC GEN3_SDVOC
Ville Syrjälä9418c1f2014-04-09 13:28:56 +03002685#define CHV_HDMID 0x6116C
Paulo Zanonic20cd312013-02-19 16:21:45 -03002686#define PCH_SDVOB 0xe1140
2687#define PCH_HDMIB PCH_SDVOB
2688#define PCH_HDMIC 0xe1150
2689#define PCH_HDMID 0xe1160
2690
Daniel Vetter84093602013-11-01 10:50:21 +01002691#define PORT_DFT_I9XX 0x61150
2692#define DC_BALANCE_RESET (1 << 25)
Rodrigo Vivia8aab8b2014-06-05 14:28:17 -07002693#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
Daniel Vetter84093602013-11-01 10:50:21 +01002694#define DC_BALANCE_RESET_VLV (1 << 31)
2695#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2696#define PIPE_B_SCRAMBLE_RESET (1 << 1)
2697#define PIPE_A_SCRAMBLE_RESET (1 << 0)
2698
Paulo Zanonic20cd312013-02-19 16:21:45 -03002699/* Gen 3 SDVO bits: */
2700#define SDVO_ENABLE (1 << 31)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002701#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2702#define SDVO_PIPE_SEL_MASK (1 << 30)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002703#define SDVO_PIPE_B_SELECT (1 << 30)
2704#define SDVO_STALL_SELECT (1 << 29)
2705#define SDVO_INTERRUPT_ENABLE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03002706/*
Jesse Barnes585fb112008-07-29 11:54:06 -07002707 * 915G/GM SDVO pixel multiplier.
Jesse Barnes585fb112008-07-29 11:54:06 -07002708 * Programmed value is multiplier - 1, up to 5x.
Jesse Barnes585fb112008-07-29 11:54:06 -07002709 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2710 */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002711#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
Jesse Barnes585fb112008-07-29 11:54:06 -07002712#define SDVO_PORT_MULTIPLY_SHIFT 23
Paulo Zanonic20cd312013-02-19 16:21:45 -03002713#define SDVO_PHASE_SELECT_MASK (15 << 19)
2714#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2715#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2716#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2717#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2718#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2719#define SDVO_DETECTED (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07002720/* Bits to be preserved when writing */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002721#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2722 SDVO_INTERRUPT_ENABLE)
2723#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2724
2725/* Gen 4 SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002726#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
Ville Syrjälä18442d02013-09-13 16:00:08 +03002727#define SDVO_COLOR_FORMAT_MASK (7 << 26)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002728#define SDVO_ENCODING_SDVO (0 << 10)
2729#define SDVO_ENCODING_HDMI (2 << 10)
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002730#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2731#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002732#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002733#define SDVO_AUDIO_ENABLE (1 << 6)
2734/* VSYNC/HSYNC bits new with 965, default is to be set */
2735#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2736#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2737
2738/* Gen 5 (IBX) SDVO/HDMI bits: */
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03002739#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
Paulo Zanonic20cd312013-02-19 16:21:45 -03002740#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2741
2742/* Gen 6 (CPT) SDVO/HDMI bits: */
Paulo Zanonidc0fa712013-02-19 16:21:46 -03002743#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2744#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
Paulo Zanonic20cd312013-02-19 16:21:45 -03002745
Chon Ming Lee44f37d12014-04-09 13:28:21 +03002746/* CHV SDVO/HDMI bits: */
2747#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2748#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2749
Jesse Barnes585fb112008-07-29 11:54:06 -07002750
2751/* DVO port control */
2752#define DVOA 0x61120
2753#define DVOB 0x61140
2754#define DVOC 0x61160
2755#define DVO_ENABLE (1 << 31)
2756#define DVO_PIPE_B_SELECT (1 << 30)
2757#define DVO_PIPE_STALL_UNUSED (0 << 28)
2758#define DVO_PIPE_STALL (1 << 28)
2759#define DVO_PIPE_STALL_TV (2 << 28)
2760#define DVO_PIPE_STALL_MASK (3 << 28)
2761#define DVO_USE_VGA_SYNC (1 << 15)
2762#define DVO_DATA_ORDER_I740 (0 << 14)
2763#define DVO_DATA_ORDER_FP (1 << 14)
2764#define DVO_VSYNC_DISABLE (1 << 11)
2765#define DVO_HSYNC_DISABLE (1 << 10)
2766#define DVO_VSYNC_TRISTATE (1 << 9)
2767#define DVO_HSYNC_TRISTATE (1 << 8)
2768#define DVO_BORDER_ENABLE (1 << 7)
2769#define DVO_DATA_ORDER_GBRG (1 << 6)
2770#define DVO_DATA_ORDER_RGGB (0 << 6)
2771#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2772#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2773#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2774#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2775#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2776#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2777#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2778#define DVO_PRESERVE_MASK (0x7<<24)
2779#define DVOA_SRCDIM 0x61124
2780#define DVOB_SRCDIM 0x61144
2781#define DVOC_SRCDIM 0x61164
2782#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2783#define DVO_SRCDIM_VERTICAL_SHIFT 0
2784
2785/* LVDS port control */
2786#define LVDS 0x61180
2787/*
2788 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2789 * the DPLL semantics change when the LVDS is assigned to that pipe.
2790 */
2791#define LVDS_PORT_EN (1 << 31)
2792/* Selects pipe B for LVDS data. Must be set on pre-965. */
2793#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08002794#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07002795#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08002796/* LVDS dithering flag on 965/g4x platform */
2797#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08002798/* LVDS sync polarity flags. Set to invert (i.e. negative) */
2799#define LVDS_VSYNC_POLARITY (1 << 21)
2800#define LVDS_HSYNC_POLARITY (1 << 20)
2801
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08002802/* Enable border for unscaled (or aspect-scaled) display */
2803#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07002804/*
2805 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2806 * pixel.
2807 */
2808#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2809#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2810#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2811/*
2812 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2813 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2814 * on.
2815 */
2816#define LVDS_A3_POWER_MASK (3 << 6)
2817#define LVDS_A3_POWER_DOWN (0 << 6)
2818#define LVDS_A3_POWER_UP (3 << 6)
2819/*
2820 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2821 * is set.
2822 */
2823#define LVDS_CLKB_POWER_MASK (3 << 4)
2824#define LVDS_CLKB_POWER_DOWN (0 << 4)
2825#define LVDS_CLKB_POWER_UP (3 << 4)
2826/*
2827 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2828 * setting for whether we are in dual-channel mode. The B3 pair will
2829 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2830 */
2831#define LVDS_B0B3_POWER_MASK (3 << 2)
2832#define LVDS_B0B3_POWER_DOWN (0 << 2)
2833#define LVDS_B0B3_POWER_UP (3 << 2)
2834
David Härdeman3c17fe42010-09-24 21:44:32 +02002835/* Video Data Island Packet control */
2836#define VIDEO_DIP_DATA 0x61178
Paulo Zanoniadf00b22012-09-25 13:23:34 -03002837/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2838 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2839 * of the infoframe structure specified by CEA-861. */
2840#define VIDEO_DIP_DATA_SIZE 32
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002841#define VIDEO_DIP_VSC_DATA_SIZE 36
David Härdeman3c17fe42010-09-24 21:44:32 +02002842#define VIDEO_DIP_CTL 0x61170
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002843/* Pre HSW: */
David Härdeman3c17fe42010-09-24 21:44:32 +02002844#define VIDEO_DIP_ENABLE (1 << 31)
Ville Syrjälä822cdc52014-01-23 23:15:34 +02002845#define VIDEO_DIP_PORT(port) ((port) << 29)
Paulo Zanoni3e6e6392012-05-04 17:18:19 -03002846#define VIDEO_DIP_PORT_MASK (3 << 29)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002847#define VIDEO_DIP_ENABLE_GCP (1 << 25)
David Härdeman3c17fe42010-09-24 21:44:32 +02002848#define VIDEO_DIP_ENABLE_AVI (1 << 21)
2849#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002850#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
David Härdeman3c17fe42010-09-24 21:44:32 +02002851#define VIDEO_DIP_ENABLE_SPD (8 << 21)
2852#define VIDEO_DIP_SELECT_AVI (0 << 19)
2853#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2854#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07002855#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02002856#define VIDEO_DIP_FREQ_ONCE (0 << 16)
2857#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2858#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
Paulo Zanoni60c5ea22012-05-04 17:18:22 -03002859#define VIDEO_DIP_FREQ_MASK (3 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002860/* HSW and later: */
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002861#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2862#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002863#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
Paulo Zanoni0dd87d22012-05-28 16:42:53 -03002864#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2865#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
Paulo Zanoni2da8af52012-05-14 17:12:51 -03002866#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
David Härdeman3c17fe42010-09-24 21:44:32 +02002867
Jesse Barnes585fb112008-07-29 11:54:06 -07002868/* Panel power sequencing */
2869#define PP_STATUS 0x61200
2870#define PP_ON (1 << 31)
2871/*
2872 * Indicates that all dependencies of the panel are on:
2873 *
2874 * - PLL enabled
2875 * - pipe enabled
2876 * - LVDS/DVOB/DVOC on
2877 */
2878#define PP_READY (1 << 30)
2879#define PP_SEQUENCE_NONE (0 << 28)
Keith Packard99ea7122011-11-01 19:57:50 -07002880#define PP_SEQUENCE_POWER_UP (1 << 28)
2881#define PP_SEQUENCE_POWER_DOWN (2 << 28)
2882#define PP_SEQUENCE_MASK (3 << 28)
2883#define PP_SEQUENCE_SHIFT 28
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002884#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002885#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07002886#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2887#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2888#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2889#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2890#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2891#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2892#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2893#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2894#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07002895#define PP_CONTROL 0x61204
2896#define POWER_TARGET_ON (1 << 0)
2897#define PP_ON_DELAYS 0x61208
2898#define PP_OFF_DELAYS 0x6120c
2899#define PP_DIVISOR 0x61210
2900
2901/* Panel fitting */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002902#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
Jesse Barnes585fb112008-07-29 11:54:06 -07002903#define PFIT_ENABLE (1 << 31)
2904#define PFIT_PIPE_MASK (3 << 29)
2905#define PFIT_PIPE_SHIFT 29
2906#define VERT_INTERP_DISABLE (0 << 10)
2907#define VERT_INTERP_BILINEAR (1 << 10)
2908#define VERT_INTERP_MASK (3 << 10)
2909#define VERT_AUTO_SCALE (1 << 9)
2910#define HORIZ_INTERP_DISABLE (0 << 6)
2911#define HORIZ_INTERP_BILINEAR (1 << 6)
2912#define HORIZ_INTERP_MASK (3 << 6)
2913#define HORIZ_AUTO_SCALE (1 << 5)
2914#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08002915#define PFIT_FILTER_FUZZY (0 << 24)
2916#define PFIT_SCALING_AUTO (0 << 26)
2917#define PFIT_SCALING_PROGRAMMED (1 << 26)
2918#define PFIT_SCALING_PILLAR (2 << 26)
2919#define PFIT_SCALING_LETTER (3 << 26)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002920#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08002921/* Pre-965 */
2922#define PFIT_VERT_SCALE_SHIFT 20
2923#define PFIT_VERT_SCALE_MASK 0xfff00000
2924#define PFIT_HORIZ_SCALE_SHIFT 4
2925#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2926/* 965+ */
2927#define PFIT_VERT_SCALE_SHIFT_965 16
2928#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2929#define PFIT_HORIZ_SCALE_SHIFT_965 0
2930#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2931
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002932#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
Jesse Barnes585fb112008-07-29 11:54:06 -07002933
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002934#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
2935#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
Jesse Barnes07bf1392013-10-31 18:55:50 +02002936#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2937 _VLV_BLC_PWM_CTL2_B)
2938
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002939#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
2940#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
Jesse Barnes07bf1392013-10-31 18:55:50 +02002941#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2942 _VLV_BLC_PWM_CTL_B)
2943
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002944#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
2945#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
Jesse Barnes07bf1392013-10-31 18:55:50 +02002946#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2947 _VLV_BLC_HIST_CTL_B)
2948
Jesse Barnes585fb112008-07-29 11:54:06 -07002949/* Backlight control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002950#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
Daniel Vetter7cf41602012-06-05 10:07:09 +02002951#define BLM_PWM_ENABLE (1 << 31)
2952#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2953#define BLM_PIPE_SELECT (1 << 29)
2954#define BLM_PIPE_SELECT_IVB (3 << 29)
2955#define BLM_PIPE_A (0 << 29)
2956#define BLM_PIPE_B (1 << 29)
2957#define BLM_PIPE_C (2 << 29) /* ivb + */
Jani Nikula35ffda42013-04-25 16:49:25 +03002958#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
2959#define BLM_TRANSCODER_B BLM_PIPE_B
2960#define BLM_TRANSCODER_C BLM_PIPE_C
2961#define BLM_TRANSCODER_EDP (3 << 29)
Daniel Vetter7cf41602012-06-05 10:07:09 +02002962#define BLM_PIPE(pipe) ((pipe) << 29)
2963#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
2964#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2965#define BLM_PHASE_IN_ENABLE (1 << 25)
2966#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2967#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2968#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2969#define BLM_PHASE_IN_COUNT_SHIFT (8)
2970#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2971#define BLM_PHASE_IN_INCR_SHIFT (0)
2972#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002973#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
Takashi Iwaiba3820a2011-03-10 14:02:12 +01002974/*
2975 * This is the most significant 15 bits of the number of backlight cycles in a
2976 * complete cycle of the modulated backlight control.
2977 *
2978 * The actual value is this field multiplied by two.
2979 */
Daniel Vetter7cf41602012-06-05 10:07:09 +02002980#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2981#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2982#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002983/*
2984 * This is the number of cycles out of the backlight modulation cycle for which
2985 * the backlight is on.
2986 *
2987 * This field must be no greater than the number of cycles in the complete
2988 * backlight modulation cycle.
2989 */
2990#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2991#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
Daniel Vetter534b5a52012-06-05 10:07:08 +02002992#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2993#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002994
Damien Lespiau5c969aa2014-02-07 19:12:48 +00002995#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
Jesse Barnes0eb96d62009-10-14 12:33:41 -07002996
Daniel Vetter7cf41602012-06-05 10:07:09 +02002997/* New registers for PCH-split platforms. Safe where new bits show up, the
2998 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2999#define BLC_PWM_CPU_CTL2 0x48250
3000#define BLC_PWM_CPU_CTL 0x48254
3001
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003002#define HSW_BLC_PWM2_CTL 0x48350
3003
Daniel Vetter7cf41602012-06-05 10:07:09 +02003004/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3005 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3006#define BLC_PWM_PCH_CTL1 0xc8250
Daniel Vetter4b4147c2012-07-11 00:31:06 +02003007#define BLM_PCH_PWM_ENABLE (1 << 31)
Daniel Vetter7cf41602012-06-05 10:07:09 +02003008#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3009#define BLM_PCH_POLARITY (1 << 29)
3010#define BLC_PWM_PCH_CTL2 0xc8254
3011
Paulo Zanonibe256dc2013-07-23 11:19:26 -03003012#define UTIL_PIN_CTL 0x48400
3013#define UTIL_PIN_ENABLE (1 << 31)
3014
3015#define PCH_GTC_CTL 0xe7000
3016#define PCH_GTC_ENABLE (1 << 31)
3017
Jesse Barnes585fb112008-07-29 11:54:06 -07003018/* TV port control */
3019#define TV_CTL 0x68000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003020/* Enables the TV encoder */
Jesse Barnes585fb112008-07-29 11:54:06 -07003021# define TV_ENC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003022/* Sources the TV encoder input from pipe B instead of A. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003023# define TV_ENC_PIPEB_SELECT (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003024/* Outputs composite video (DAC A only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003025# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003026/* Outputs SVideo video (DAC B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003027# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003028/* Outputs Component video (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003029# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003030/* Outputs Composite and SVideo (DAC A/B/C) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003031# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3032# define TV_TRILEVEL_SYNC (1 << 21)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003033/* Enables slow sync generation (945GM only) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003034# define TV_SLOW_SYNC (1 << 20)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003035/* Selects 4x oversampling for 480i and 576p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003036# define TV_OVERSAMPLE_4X (0 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003037/* Selects 2x oversampling for 720p and 1080i */
Jesse Barnes585fb112008-07-29 11:54:06 -07003038# define TV_OVERSAMPLE_2X (1 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003039/* Selects no oversampling for 1080p */
Jesse Barnes585fb112008-07-29 11:54:06 -07003040# define TV_OVERSAMPLE_NONE (2 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003041/* Selects 8x oversampling */
Jesse Barnes585fb112008-07-29 11:54:06 -07003042# define TV_OVERSAMPLE_8X (3 << 18)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003043/* Selects progressive mode rather than interlaced */
Jesse Barnes585fb112008-07-29 11:54:06 -07003044# define TV_PROGRESSIVE (1 << 17)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003045/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003046# define TV_PAL_BURST (1 << 16)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003047/* Field for setting delay of Y compared to C */
Jesse Barnes585fb112008-07-29 11:54:06 -07003048# define TV_YC_SKEW_MASK (7 << 12)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003049/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
Jesse Barnes585fb112008-07-29 11:54:06 -07003050# define TV_ENC_SDP_FIX (1 << 11)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003051/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003052 * Enables a fix for the 915GM only.
3053 *
3054 * Not sure what it does.
3055 */
3056# define TV_ENC_C0_FIX (1 << 10)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003057/* Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08003058# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07003059# define TV_FUSE_STATE_MASK (3 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003060/* Read-only state that reports all features enabled */
Jesse Barnes585fb112008-07-29 11:54:06 -07003061# define TV_FUSE_STATE_ENABLED (0 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003062/* Read-only state that reports that Macrovision is disabled in hardware*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003063# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003064/* Read-only state that reports that TV-out is disabled in hardware. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003065# define TV_FUSE_STATE_DISABLED (2 << 4)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003066/* Normal operation */
Jesse Barnes585fb112008-07-29 11:54:06 -07003067# define TV_TEST_MODE_NORMAL (0 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003068/* Encoder test pattern 1 - combo pattern */
Jesse Barnes585fb112008-07-29 11:54:06 -07003069# define TV_TEST_MODE_PATTERN_1 (1 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003070/* Encoder test pattern 2 - full screen vertical 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003071# define TV_TEST_MODE_PATTERN_2 (2 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003072/* Encoder test pattern 3 - full screen horizontal 75% color bars */
Jesse Barnes585fb112008-07-29 11:54:06 -07003073# define TV_TEST_MODE_PATTERN_3 (3 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003074/* Encoder test pattern 4 - random noise */
Jesse Barnes585fb112008-07-29 11:54:06 -07003075# define TV_TEST_MODE_PATTERN_4 (4 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003076/* Encoder test pattern 5 - linear color ramps */
Jesse Barnes585fb112008-07-29 11:54:06 -07003077# define TV_TEST_MODE_PATTERN_5 (5 << 0)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003078/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003079 * This test mode forces the DACs to 50% of full output.
3080 *
3081 * This is used for load detection in combination with TVDAC_SENSE_MASK
3082 */
3083# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3084# define TV_TEST_MODE_MASK (7 << 0)
3085
3086#define TV_DAC 0x68004
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01003087# define TV_DAC_SAVE 0x00ffff00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003088/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003089 * Reports that DAC state change logic has reported change (RO).
3090 *
3091 * This gets cleared when TV_DAC_STATE_EN is cleared
3092*/
3093# define TVDAC_STATE_CHG (1 << 31)
3094# define TVDAC_SENSE_MASK (7 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003095/* Reports that DAC A voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003096# define TVDAC_A_SENSE (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003097/* Reports that DAC B voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003098# define TVDAC_B_SENSE (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003099/* Reports that DAC C voltage is above the detect threshold */
Jesse Barnes585fb112008-07-29 11:54:06 -07003100# define TVDAC_C_SENSE (1 << 28)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003101/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003102 * Enables DAC state detection logic, for load-based TV detection.
3103 *
3104 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3105 * to off, for load detection to work.
3106 */
3107# define TVDAC_STATE_CHG_EN (1 << 27)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003108/* Sets the DAC A sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003109# define TVDAC_A_SENSE_CTL (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003110/* Sets the DAC B sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003111# define TVDAC_B_SENSE_CTL (1 << 25)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003112/* Sets the DAC C sense value to high */
Jesse Barnes585fb112008-07-29 11:54:06 -07003113# define TVDAC_C_SENSE_CTL (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003114/* Overrides the ENC_ENABLE and DAC voltage levels */
Jesse Barnes585fb112008-07-29 11:54:06 -07003115# define DAC_CTL_OVERRIDE (1 << 7)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003116/* Sets the slew rate. Must be preserved in software */
Jesse Barnes585fb112008-07-29 11:54:06 -07003117# define ENC_TVDAC_SLEW_FAST (1 << 6)
3118# define DAC_A_1_3_V (0 << 4)
3119# define DAC_A_1_1_V (1 << 4)
3120# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08003121# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07003122# define DAC_B_1_3_V (0 << 2)
3123# define DAC_B_1_1_V (1 << 2)
3124# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08003125# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07003126# define DAC_C_1_3_V (0 << 0)
3127# define DAC_C_1_1_V (1 << 0)
3128# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08003129# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003130
Ville Syrjälä646b4262014-04-25 20:14:30 +03003131/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003132 * CSC coefficients are stored in a floating point format with 9 bits of
3133 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3134 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3135 * -1 (0x3) being the only legal negative value.
3136 */
3137#define TV_CSC_Y 0x68010
3138# define TV_RY_MASK 0x07ff0000
3139# define TV_RY_SHIFT 16
3140# define TV_GY_MASK 0x00000fff
3141# define TV_GY_SHIFT 0
3142
3143#define TV_CSC_Y2 0x68014
3144# define TV_BY_MASK 0x07ff0000
3145# define TV_BY_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003146/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003147 * Y attenuation for component video.
3148 *
3149 * Stored in 1.9 fixed point.
3150 */
3151# define TV_AY_MASK 0x000003ff
3152# define TV_AY_SHIFT 0
3153
3154#define TV_CSC_U 0x68018
3155# define TV_RU_MASK 0x07ff0000
3156# define TV_RU_SHIFT 16
3157# define TV_GU_MASK 0x000007ff
3158# define TV_GU_SHIFT 0
3159
3160#define TV_CSC_U2 0x6801c
3161# define TV_BU_MASK 0x07ff0000
3162# define TV_BU_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003163/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003164 * U attenuation for component video.
3165 *
3166 * Stored in 1.9 fixed point.
3167 */
3168# define TV_AU_MASK 0x000003ff
3169# define TV_AU_SHIFT 0
3170
3171#define TV_CSC_V 0x68020
3172# define TV_RV_MASK 0x0fff0000
3173# define TV_RV_SHIFT 16
3174# define TV_GV_MASK 0x000007ff
3175# define TV_GV_SHIFT 0
3176
3177#define TV_CSC_V2 0x68024
3178# define TV_BV_MASK 0x07ff0000
3179# define TV_BV_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003180/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003181 * V attenuation for component video.
3182 *
3183 * Stored in 1.9 fixed point.
3184 */
3185# define TV_AV_MASK 0x000007ff
3186# define TV_AV_SHIFT 0
3187
3188#define TV_CLR_KNOBS 0x68028
Ville Syrjälä646b4262014-04-25 20:14:30 +03003189/* 2s-complement brightness adjustment */
Jesse Barnes585fb112008-07-29 11:54:06 -07003190# define TV_BRIGHTNESS_MASK 0xff000000
3191# define TV_BRIGHTNESS_SHIFT 24
Ville Syrjälä646b4262014-04-25 20:14:30 +03003192/* Contrast adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003193# define TV_CONTRAST_MASK 0x00ff0000
3194# define TV_CONTRAST_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003195/* Saturation adjustment, as a 2.6 unsigned floating point number */
Jesse Barnes585fb112008-07-29 11:54:06 -07003196# define TV_SATURATION_MASK 0x0000ff00
3197# define TV_SATURATION_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003198/* Hue adjustment, as an integer phase angle in degrees */
Jesse Barnes585fb112008-07-29 11:54:06 -07003199# define TV_HUE_MASK 0x000000ff
3200# define TV_HUE_SHIFT 0
3201
3202#define TV_CLR_LEVEL 0x6802c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003203/* Controls the DAC level for black */
Jesse Barnes585fb112008-07-29 11:54:06 -07003204# define TV_BLACK_LEVEL_MASK 0x01ff0000
3205# define TV_BLACK_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003206/* Controls the DAC level for blanking */
Jesse Barnes585fb112008-07-29 11:54:06 -07003207# define TV_BLANK_LEVEL_MASK 0x000001ff
3208# define TV_BLANK_LEVEL_SHIFT 0
3209
3210#define TV_H_CTL_1 0x68030
Ville Syrjälä646b4262014-04-25 20:14:30 +03003211/* Number of pixels in the hsync. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003212# define TV_HSYNC_END_MASK 0x1fff0000
3213# define TV_HSYNC_END_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003214/* Total number of pixels minus one in the line (display and blanking). */
Jesse Barnes585fb112008-07-29 11:54:06 -07003215# define TV_HTOTAL_MASK 0x00001fff
3216# define TV_HTOTAL_SHIFT 0
3217
3218#define TV_H_CTL_2 0x68034
Ville Syrjälä646b4262014-04-25 20:14:30 +03003219/* Enables the colorburst (needed for non-component color) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003220# define TV_BURST_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003221/* Offset of the colorburst from the start of hsync, in pixels minus one. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003222# define TV_HBURST_START_SHIFT 16
3223# define TV_HBURST_START_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003224/* Length of the colorburst */
Jesse Barnes585fb112008-07-29 11:54:06 -07003225# define TV_HBURST_LEN_SHIFT 0
3226# define TV_HBURST_LEN_MASK 0x0001fff
3227
3228#define TV_H_CTL_3 0x68038
Ville Syrjälä646b4262014-04-25 20:14:30 +03003229/* End of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003230# define TV_HBLANK_END_SHIFT 16
3231# define TV_HBLANK_END_MASK 0x1fff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003232/* Start of hblank, measured in pixels minus one from start of hsync */
Jesse Barnes585fb112008-07-29 11:54:06 -07003233# define TV_HBLANK_START_SHIFT 0
3234# define TV_HBLANK_START_MASK 0x0001fff
3235
3236#define TV_V_CTL_1 0x6803c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003237/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003238# define TV_NBR_END_SHIFT 16
3239# define TV_NBR_END_MASK 0x07ff0000
Ville Syrjälä646b4262014-04-25 20:14:30 +03003240/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003241# define TV_VI_END_F1_SHIFT 8
3242# define TV_VI_END_F1_MASK 0x00003f00
Ville Syrjälä646b4262014-04-25 20:14:30 +03003243/* XXX */
Jesse Barnes585fb112008-07-29 11:54:06 -07003244# define TV_VI_END_F2_SHIFT 0
3245# define TV_VI_END_F2_MASK 0x0000003f
3246
3247#define TV_V_CTL_2 0x68040
Ville Syrjälä646b4262014-04-25 20:14:30 +03003248/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003249# define TV_VSYNC_LEN_MASK 0x07ff0000
3250# define TV_VSYNC_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003251/* Offset of the start of vsync in field 1, measured in one less than the
Jesse Barnes585fb112008-07-29 11:54:06 -07003252 * number of half lines.
3253 */
3254# define TV_VSYNC_START_F1_MASK 0x00007f00
3255# define TV_VSYNC_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003256/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003257 * Offset of the start of vsync in field 2, measured in one less than the
3258 * number of half lines.
3259 */
3260# define TV_VSYNC_START_F2_MASK 0x0000007f
3261# define TV_VSYNC_START_F2_SHIFT 0
3262
3263#define TV_V_CTL_3 0x68044
Ville Syrjälä646b4262014-04-25 20:14:30 +03003264/* Enables generation of the equalization signal */
Jesse Barnes585fb112008-07-29 11:54:06 -07003265# define TV_EQUAL_ENA (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003266/* Length of vsync, in half lines */
Jesse Barnes585fb112008-07-29 11:54:06 -07003267# define TV_VEQ_LEN_MASK 0x007f0000
3268# define TV_VEQ_LEN_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003269/* Offset of the start of equalization in field 1, measured in one less than
Jesse Barnes585fb112008-07-29 11:54:06 -07003270 * the number of half lines.
3271 */
3272# define TV_VEQ_START_F1_MASK 0x0007f00
3273# define TV_VEQ_START_F1_SHIFT 8
Ville Syrjälä646b4262014-04-25 20:14:30 +03003274/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003275 * Offset of the start of equalization in field 2, measured in one less than
3276 * the number of half lines.
3277 */
3278# define TV_VEQ_START_F2_MASK 0x000007f
3279# define TV_VEQ_START_F2_SHIFT 0
3280
3281#define TV_V_CTL_4 0x68048
Ville Syrjälä646b4262014-04-25 20:14:30 +03003282/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003283 * Offset to start of vertical colorburst, measured in one less than the
3284 * number of lines from vertical start.
3285 */
3286# define TV_VBURST_START_F1_MASK 0x003f0000
3287# define TV_VBURST_START_F1_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003288/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003289 * Offset to the end of vertical colorburst, measured in one less than the
3290 * number of lines from the start of NBR.
3291 */
3292# define TV_VBURST_END_F1_MASK 0x000000ff
3293# define TV_VBURST_END_F1_SHIFT 0
3294
3295#define TV_V_CTL_5 0x6804c
Ville Syrjälä646b4262014-04-25 20:14:30 +03003296/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003297 * Offset to start of vertical colorburst, measured in one less than the
3298 * number of lines from vertical start.
3299 */
3300# define TV_VBURST_START_F2_MASK 0x003f0000
3301# define TV_VBURST_START_F2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003302/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003303 * Offset to the end of vertical colorburst, measured in one less than the
3304 * number of lines from the start of NBR.
3305 */
3306# define TV_VBURST_END_F2_MASK 0x000000ff
3307# define TV_VBURST_END_F2_SHIFT 0
3308
3309#define TV_V_CTL_6 0x68050
Ville Syrjälä646b4262014-04-25 20:14:30 +03003310/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003311 * Offset to start of vertical colorburst, measured in one less than the
3312 * number of lines from vertical start.
3313 */
3314# define TV_VBURST_START_F3_MASK 0x003f0000
3315# define TV_VBURST_START_F3_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003316/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003317 * Offset to the end of vertical colorburst, measured in one less than the
3318 * number of lines from the start of NBR.
3319 */
3320# define TV_VBURST_END_F3_MASK 0x000000ff
3321# define TV_VBURST_END_F3_SHIFT 0
3322
3323#define TV_V_CTL_7 0x68054
Ville Syrjälä646b4262014-04-25 20:14:30 +03003324/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003325 * Offset to start of vertical colorburst, measured in one less than the
3326 * number of lines from vertical start.
3327 */
3328# define TV_VBURST_START_F4_MASK 0x003f0000
3329# define TV_VBURST_START_F4_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003330/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003331 * Offset to the end of vertical colorburst, measured in one less than the
3332 * number of lines from the start of NBR.
3333 */
3334# define TV_VBURST_END_F4_MASK 0x000000ff
3335# define TV_VBURST_END_F4_SHIFT 0
3336
3337#define TV_SC_CTL_1 0x68060
Ville Syrjälä646b4262014-04-25 20:14:30 +03003338/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003339# define TV_SC_DDA1_EN (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003340/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003341# define TV_SC_DDA2_EN (1 << 30)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003342/* Turns on the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003343# define TV_SC_DDA3_EN (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003344/* Sets the subcarrier DDA to reset frequency every other field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003345# define TV_SC_RESET_EVERY_2 (0 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003346/* Sets the subcarrier DDA to reset frequency every fourth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003347# define TV_SC_RESET_EVERY_4 (1 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003348/* Sets the subcarrier DDA to reset frequency every eighth field */
Jesse Barnes585fb112008-07-29 11:54:06 -07003349# define TV_SC_RESET_EVERY_8 (2 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003350/* Sets the subcarrier DDA to never reset the frequency */
Jesse Barnes585fb112008-07-29 11:54:06 -07003351# define TV_SC_RESET_NEVER (3 << 24)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003352/* Sets the peak amplitude of the colorburst.*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003353# define TV_BURST_LEVEL_MASK 0x00ff0000
3354# define TV_BURST_LEVEL_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003355/* Sets the increment of the first subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003356# define TV_SCDDA1_INC_MASK 0x00000fff
3357# define TV_SCDDA1_INC_SHIFT 0
3358
3359#define TV_SC_CTL_2 0x68064
Ville Syrjälä646b4262014-04-25 20:14:30 +03003360/* Sets the rollover for the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003361# define TV_SCDDA2_SIZE_MASK 0x7fff0000
3362# define TV_SCDDA2_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003363/* Sets the increent of the second subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003364# define TV_SCDDA2_INC_MASK 0x00007fff
3365# define TV_SCDDA2_INC_SHIFT 0
3366
3367#define TV_SC_CTL_3 0x68068
Ville Syrjälä646b4262014-04-25 20:14:30 +03003368/* Sets the rollover for the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003369# define TV_SCDDA3_SIZE_MASK 0x7fff0000
3370# define TV_SCDDA3_SIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003371/* Sets the increent of the third subcarrier phase generation DDA */
Jesse Barnes585fb112008-07-29 11:54:06 -07003372# define TV_SCDDA3_INC_MASK 0x00007fff
3373# define TV_SCDDA3_INC_SHIFT 0
3374
3375#define TV_WIN_POS 0x68070
Ville Syrjälä646b4262014-04-25 20:14:30 +03003376/* X coordinate of the display from the start of horizontal active */
Jesse Barnes585fb112008-07-29 11:54:06 -07003377# define TV_XPOS_MASK 0x1fff0000
3378# define TV_XPOS_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003379/* Y coordinate of the display from the start of vertical active (NBR) */
Jesse Barnes585fb112008-07-29 11:54:06 -07003380# define TV_YPOS_MASK 0x00000fff
3381# define TV_YPOS_SHIFT 0
3382
3383#define TV_WIN_SIZE 0x68074
Ville Syrjälä646b4262014-04-25 20:14:30 +03003384/* Horizontal size of the display window, measured in pixels*/
Jesse Barnes585fb112008-07-29 11:54:06 -07003385# define TV_XSIZE_MASK 0x1fff0000
3386# define TV_XSIZE_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003387/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003388 * Vertical size of the display window, measured in pixels.
3389 *
3390 * Must be even for interlaced modes.
3391 */
3392# define TV_YSIZE_MASK 0x00000fff
3393# define TV_YSIZE_SHIFT 0
3394
3395#define TV_FILTER_CTL_1 0x68080
Ville Syrjälä646b4262014-04-25 20:14:30 +03003396/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003397 * Enables automatic scaling calculation.
3398 *
3399 * If set, the rest of the registers are ignored, and the calculated values can
3400 * be read back from the register.
3401 */
3402# define TV_AUTO_SCALE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003403/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003404 * Disables the vertical filter.
3405 *
3406 * This is required on modes more than 1024 pixels wide */
3407# define TV_V_FILTER_BYPASS (1 << 29)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003408/* Enables adaptive vertical filtering */
Jesse Barnes585fb112008-07-29 11:54:06 -07003409# define TV_VADAPT (1 << 28)
3410# define TV_VADAPT_MODE_MASK (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003411/* Selects the least adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003412# define TV_VADAPT_MODE_LEAST (0 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003413/* Selects the moderately adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003414# define TV_VADAPT_MODE_MODERATE (1 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003415/* Selects the most adaptive vertical filtering mode */
Jesse Barnes585fb112008-07-29 11:54:06 -07003416# define TV_VADAPT_MODE_MOST (3 << 26)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003417/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003418 * Sets the horizontal scaling factor.
3419 *
3420 * This should be the fractional part of the horizontal scaling factor divided
3421 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3422 *
3423 * (src width - 1) / ((oversample * dest width) - 1)
3424 */
3425# define TV_HSCALE_FRAC_MASK 0x00003fff
3426# define TV_HSCALE_FRAC_SHIFT 0
3427
3428#define TV_FILTER_CTL_2 0x68084
Ville Syrjälä646b4262014-04-25 20:14:30 +03003429/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003430 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3431 *
3432 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3433 */
3434# define TV_VSCALE_INT_MASK 0x00038000
3435# define TV_VSCALE_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03003436/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003437 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3438 *
3439 * \sa TV_VSCALE_INT_MASK
3440 */
3441# define TV_VSCALE_FRAC_MASK 0x00007fff
3442# define TV_VSCALE_FRAC_SHIFT 0
3443
3444#define TV_FILTER_CTL_3 0x68088
Ville Syrjälä646b4262014-04-25 20:14:30 +03003445/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003446 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3447 *
3448 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3449 *
3450 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3451 */
3452# define TV_VSCALE_IP_INT_MASK 0x00038000
3453# define TV_VSCALE_IP_INT_SHIFT 15
Ville Syrjälä646b4262014-04-25 20:14:30 +03003454/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003455 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3456 *
3457 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3458 *
3459 * \sa TV_VSCALE_IP_INT_MASK
3460 */
3461# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3462# define TV_VSCALE_IP_FRAC_SHIFT 0
3463
3464#define TV_CC_CONTROL 0x68090
3465# define TV_CC_ENABLE (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003466/*
Jesse Barnes585fb112008-07-29 11:54:06 -07003467 * Specifies which field to send the CC data in.
3468 *
3469 * CC data is usually sent in field 0.
3470 */
3471# define TV_CC_FID_MASK (1 << 27)
3472# define TV_CC_FID_SHIFT 27
Ville Syrjälä646b4262014-04-25 20:14:30 +03003473/* Sets the horizontal position of the CC data. Usually 135. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003474# define TV_CC_HOFF_MASK 0x03ff0000
3475# define TV_CC_HOFF_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003476/* Sets the vertical position of the CC data. Usually 21 */
Jesse Barnes585fb112008-07-29 11:54:06 -07003477# define TV_CC_LINE_MASK 0x0000003f
3478# define TV_CC_LINE_SHIFT 0
3479
3480#define TV_CC_DATA 0x68094
3481# define TV_CC_RDY (1 << 31)
Ville Syrjälä646b4262014-04-25 20:14:30 +03003482/* Second word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003483# define TV_CC_DATA_2_MASK 0x007f0000
3484# define TV_CC_DATA_2_SHIFT 16
Ville Syrjälä646b4262014-04-25 20:14:30 +03003485/* First word of CC data to be transmitted. */
Jesse Barnes585fb112008-07-29 11:54:06 -07003486# define TV_CC_DATA_1_MASK 0x0000007f
3487# define TV_CC_DATA_1_SHIFT 0
3488
3489#define TV_H_LUMA_0 0x68100
3490#define TV_H_LUMA_59 0x681ec
3491#define TV_H_CHROMA_0 0x68200
3492#define TV_H_CHROMA_59 0x682ec
3493#define TV_V_LUMA_0 0x68300
3494#define TV_V_LUMA_42 0x683a8
3495#define TV_V_CHROMA_0 0x68400
3496#define TV_V_CHROMA_42 0x684a8
3497
Keith Packard040d87f2009-05-30 20:42:33 -07003498/* Display Port */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003499#define DP_A 0x64000 /* eDP */
Keith Packard040d87f2009-05-30 20:42:33 -07003500#define DP_B 0x64100
3501#define DP_C 0x64200
3502#define DP_D 0x64300
3503
3504#define DP_PORT_EN (1 << 31)
3505#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003506#define DP_PIPE_MASK (1 << 30)
Chon Ming Lee44f37d12014-04-09 13:28:21 +03003507#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
3508#define DP_PIPE_MASK_CHV (3 << 16)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003509
Keith Packard040d87f2009-05-30 20:42:33 -07003510/* Link training mode - select a suitable mode for each stage */
3511#define DP_LINK_TRAIN_PAT_1 (0 << 28)
3512#define DP_LINK_TRAIN_PAT_2 (1 << 28)
3513#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3514#define DP_LINK_TRAIN_OFF (3 << 28)
3515#define DP_LINK_TRAIN_MASK (3 << 28)
3516#define DP_LINK_TRAIN_SHIFT 28
Ville Syrjäläaad3d142014-06-28 02:04:25 +03003517#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
3518#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
Keith Packard040d87f2009-05-30 20:42:33 -07003519
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003520/* CPT Link training mode */
3521#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3522#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3523#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3524#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3525#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3526#define DP_LINK_TRAIN_SHIFT_CPT 8
3527
Keith Packard040d87f2009-05-30 20:42:33 -07003528/* Signal voltages. These are mostly controlled by the other end */
3529#define DP_VOLTAGE_0_4 (0 << 25)
3530#define DP_VOLTAGE_0_6 (1 << 25)
3531#define DP_VOLTAGE_0_8 (2 << 25)
3532#define DP_VOLTAGE_1_2 (3 << 25)
3533#define DP_VOLTAGE_MASK (7 << 25)
3534#define DP_VOLTAGE_SHIFT 25
3535
3536/* Signal pre-emphasis levels, like voltages, the other end tells us what
3537 * they want
3538 */
3539#define DP_PRE_EMPHASIS_0 (0 << 22)
3540#define DP_PRE_EMPHASIS_3_5 (1 << 22)
3541#define DP_PRE_EMPHASIS_6 (2 << 22)
3542#define DP_PRE_EMPHASIS_9_5 (3 << 22)
3543#define DP_PRE_EMPHASIS_MASK (7 << 22)
3544#define DP_PRE_EMPHASIS_SHIFT 22
3545
3546/* How many wires to use. I guess 3 was too hard */
Daniel Vetter17aa6be2013-04-30 14:01:40 +02003547#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
Keith Packard040d87f2009-05-30 20:42:33 -07003548#define DP_PORT_WIDTH_MASK (7 << 19)
3549
3550/* Mystic DPCD version 1.1 special mode */
3551#define DP_ENHANCED_FRAMING (1 << 18)
3552
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003553/* eDP */
3554#define DP_PLL_FREQ_270MHZ (0 << 16)
3555#define DP_PLL_FREQ_160MHZ (1 << 16)
3556#define DP_PLL_FREQ_MASK (3 << 16)
3557
Ville Syrjälä646b4262014-04-25 20:14:30 +03003558/* locked once port is enabled */
Keith Packard040d87f2009-05-30 20:42:33 -07003559#define DP_PORT_REVERSAL (1 << 15)
3560
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003561/* eDP */
3562#define DP_PLL_ENABLE (1 << 14)
3563
Ville Syrjälä646b4262014-04-25 20:14:30 +03003564/* sends the clock on lane 15 of the PEG for debug */
Keith Packard040d87f2009-05-30 20:42:33 -07003565#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3566
3567#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003568#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07003569
Ville Syrjälä646b4262014-04-25 20:14:30 +03003570/* limit RGB values to avoid confusing TVs */
Keith Packard040d87f2009-05-30 20:42:33 -07003571#define DP_COLOR_RANGE_16_235 (1 << 8)
3572
Ville Syrjälä646b4262014-04-25 20:14:30 +03003573/* Turn on the audio link */
Keith Packard040d87f2009-05-30 20:42:33 -07003574#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3575
Ville Syrjälä646b4262014-04-25 20:14:30 +03003576/* vs and hs sync polarity */
Keith Packard040d87f2009-05-30 20:42:33 -07003577#define DP_SYNC_VS_HIGH (1 << 4)
3578#define DP_SYNC_HS_HIGH (1 << 3)
3579
Ville Syrjälä646b4262014-04-25 20:14:30 +03003580/* A fantasy */
Keith Packard040d87f2009-05-30 20:42:33 -07003581#define DP_DETECTED (1 << 2)
3582
Ville Syrjälä646b4262014-04-25 20:14:30 +03003583/* The aux channel provides a way to talk to the
Keith Packard040d87f2009-05-30 20:42:33 -07003584 * signal sink for DDC etc. Max packet size supported
3585 * is 20 bytes in each direction, hence the 5 fixed
3586 * data registers
3587 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003588#define DPA_AUX_CH_CTL 0x64010
3589#define DPA_AUX_CH_DATA1 0x64014
3590#define DPA_AUX_CH_DATA2 0x64018
3591#define DPA_AUX_CH_DATA3 0x6401c
3592#define DPA_AUX_CH_DATA4 0x64020
3593#define DPA_AUX_CH_DATA5 0x64024
3594
Keith Packard040d87f2009-05-30 20:42:33 -07003595#define DPB_AUX_CH_CTL 0x64110
3596#define DPB_AUX_CH_DATA1 0x64114
3597#define DPB_AUX_CH_DATA2 0x64118
3598#define DPB_AUX_CH_DATA3 0x6411c
3599#define DPB_AUX_CH_DATA4 0x64120
3600#define DPB_AUX_CH_DATA5 0x64124
3601
3602#define DPC_AUX_CH_CTL 0x64210
3603#define DPC_AUX_CH_DATA1 0x64214
3604#define DPC_AUX_CH_DATA2 0x64218
3605#define DPC_AUX_CH_DATA3 0x6421c
3606#define DPC_AUX_CH_DATA4 0x64220
3607#define DPC_AUX_CH_DATA5 0x64224
3608
3609#define DPD_AUX_CH_CTL 0x64310
3610#define DPD_AUX_CH_DATA1 0x64314
3611#define DPD_AUX_CH_DATA2 0x64318
3612#define DPD_AUX_CH_DATA3 0x6431c
3613#define DPD_AUX_CH_DATA4 0x64320
3614#define DPD_AUX_CH_DATA5 0x64324
3615
3616#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3617#define DP_AUX_CH_CTL_DONE (1 << 30)
3618#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3619#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3620#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3621#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3622#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3623#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3624#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3625#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3626#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3627#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3628#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3629#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3630#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3631#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3632#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3633#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3634#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3635#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3636#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3637
3638/*
3639 * Computing GMCH M and N values for the Display Port link
3640 *
3641 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3642 *
3643 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3644 *
3645 * The GMCH value is used internally
3646 *
3647 * bytes_per_pixel is the number of bytes coming out of the plane,
3648 * which is after the LUTs, so we want the bytes for our color format.
3649 * For our current usage, this is always 3, one byte for R, G and B.
3650 */
Daniel Vettere3b95f12013-05-03 11:49:49 +02003651#define _PIPEA_DATA_M_G4X 0x70050
3652#define _PIPEB_DATA_M_G4X 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07003653
3654/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003655#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
Daniel Vetter72419202013-04-04 13:28:53 +02003656#define TU_SIZE_SHIFT 25
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003657#define TU_SIZE_MASK (0x3f << 25)
Keith Packard040d87f2009-05-30 20:42:33 -07003658
Ville Syrjäläa65851a2013-04-23 15:03:34 +03003659#define DATA_LINK_M_N_MASK (0xffffff)
3660#define DATA_LINK_N_MAX (0x800000)
Keith Packard040d87f2009-05-30 20:42:33 -07003661
Daniel Vettere3b95f12013-05-03 11:49:49 +02003662#define _PIPEA_DATA_N_G4X 0x70054
3663#define _PIPEB_DATA_N_G4X 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07003664#define PIPE_GMCH_DATA_N_MASK (0xffffff)
3665
3666/*
3667 * Computing Link M and N values for the Display Port link
3668 *
3669 * Link M / N = pixel_clock / ls_clk
3670 *
3671 * (the DP spec calls pixel_clock the 'strm_clk')
3672 *
3673 * The Link value is transmitted in the Main Stream
3674 * Attributes and VB-ID.
3675 */
3676
Daniel Vettere3b95f12013-05-03 11:49:49 +02003677#define _PIPEA_LINK_M_G4X 0x70060
3678#define _PIPEB_LINK_M_G4X 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07003679#define PIPEA_DP_LINK_M_MASK (0xffffff)
3680
Daniel Vettere3b95f12013-05-03 11:49:49 +02003681#define _PIPEA_LINK_N_G4X 0x70064
3682#define _PIPEB_LINK_N_G4X 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07003683#define PIPEA_DP_LINK_N_MASK (0xffffff)
3684
Daniel Vettere3b95f12013-05-03 11:49:49 +02003685#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3686#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3687#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3688#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003689
Jesse Barnes585fb112008-07-29 11:54:06 -07003690/* Display & cursor control */
3691
3692/* Pipe A */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003693#define _PIPEADSL 0x70000
Paulo Zanoni837ba002012-05-04 17:18:14 -03003694#define DSL_LINEMASK_GEN2 0x00000fff
3695#define DSL_LINEMASK_GEN3 0x00001fff
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003696#define _PIPEACONF 0x70008
Chris Wilson5eddb702010-09-11 13:48:45 +01003697#define PIPECONF_ENABLE (1<<31)
3698#define PIPECONF_DISABLE 0
3699#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003700#define I965_PIPECONF_ACTIVE (1<<30)
Jani Nikulab6ec10b2013-08-27 15:12:15 +03003701#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
Chris Wilsonf47166d2012-03-22 15:00:50 +00003702#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01003703#define PIPECONF_SINGLE_WIDE 0
3704#define PIPECONF_PIPE_UNLOCKED 0
3705#define PIPECONF_PIPE_LOCKED (1<<25)
3706#define PIPECONF_PALETTE 0
3707#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07003708#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01003709#define PIPECONF_INTERLACE_MASK (7 << 21)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03003710#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01003711/* Note that pre-gen3 does not support interlaced display directly. Panel
3712 * fitting must be disabled on pre-ilk for interlaced. */
3713#define PIPECONF_PROGRESSIVE (0 << 21)
3714#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3715#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3716#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3717#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3718/* Ironlake and later have a complete new set of values for interlaced. PFIT
3719 * means panel fitter required, PF means progressive fetch, DBL means power
3720 * saving pixel doubling. */
3721#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3722#define PIPECONF_INTERLACED_ILK (3 << 21)
3723#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3724#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02003725#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05303726#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
Jesse Barnes652c3932009-08-17 13:31:43 -07003727#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02003728#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003729#define PIPECONF_BPC_MASK (0x7 << 5)
3730#define PIPECONF_8BPC (0<<5)
3731#define PIPECONF_10BPC (1<<5)
3732#define PIPECONF_6BPC (2<<5)
3733#define PIPECONF_12BPC (3<<5)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07003734#define PIPECONF_DITHER_EN (1<<4)
3735#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3736#define PIPECONF_DITHER_TYPE_SP (0<<2)
3737#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3738#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3739#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003740#define _PIPEASTAT 0x70024
Jesse Barnes585fb112008-07-29 11:54:06 -07003741#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
Imre Deak579a9b02014-02-04 21:35:48 +02003742#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07003743#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3744#define PIPE_CRC_DONE_ENABLE (1UL<<28)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003745#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
Jesse Barnes585fb112008-07-29 11:54:06 -07003746#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003747#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07003748#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3749#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3750#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3751#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
Ville Syrjäläc70af1e2013-01-16 19:59:03 +02003752#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
Jesse Barnes585fb112008-07-29 11:54:06 -07003753#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3754#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3755#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
Imre Deak10c59c52014-02-10 18:42:48 +02003756#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003757#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
Jesse Barnes585fb112008-07-29 11:54:06 -07003758#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3759#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003760#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnes585fb112008-07-29 11:54:06 -07003761#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003762#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -07003763#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
Imre Deak579a9b02014-02-04 21:35:48 +02003764#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3765#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
Jesse Barnes585fb112008-07-29 11:54:06 -07003766#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3767#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003768#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
Jesse Barnes585fb112008-07-29 11:54:06 -07003769#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
Imre Deak579a9b02014-02-04 21:35:48 +02003770#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
Jesse Barnes585fb112008-07-29 11:54:06 -07003771#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3772#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3773#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3774#define PIPE_DPST_EVENT_STATUS (1UL<<7)
Imre Deak10c59c52014-02-10 18:42:48 +02003775#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003776#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
Jesse Barnes585fb112008-07-29 11:54:06 -07003777#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3778#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
Imre Deak10c59c52014-02-10 18:42:48 +02003779#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003780#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
Jesse Barnes585fb112008-07-29 11:54:06 -07003781#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3782#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003783#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
Jesse Barnes585fb112008-07-29 11:54:06 -07003784#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
Ville Syrjälä8cc96e72014-04-09 13:28:04 +03003785#define PIPE_HBLANK_INT_STATUS (1UL<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -07003786#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3787
Imre Deak755e9012014-02-10 18:42:47 +02003788#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3789#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3790
Rafael Barbalho84fd4f42014-04-28 14:00:42 +03003791#define PIPE_A_OFFSET 0x70000
3792#define PIPE_B_OFFSET 0x71000
3793#define PIPE_C_OFFSET 0x72000
3794#define CHV_PIPE_C_OFFSET 0x74000
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003795/*
3796 * There's actually no pipe EDP. Some pipe registers have
3797 * simply shifted from the pipe to the transcoder, while
3798 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3799 * to access such registers in transcoder EDP.
3800 */
3801#define PIPE_EDP_OFFSET 0x7f000
3802
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003803#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3804 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3805 dev_priv->info.display_mmio_offset)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003806
3807#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3808#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3809#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3810#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3811#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01003812
Paulo Zanoni756f85c2013-11-02 21:07:38 -07003813#define _PIPE_MISC_A 0x70030
3814#define _PIPE_MISC_B 0x71030
3815#define PIPEMISC_DITHER_BPC_MASK (7<<5)
3816#define PIPEMISC_DITHER_8_BPC (0<<5)
3817#define PIPEMISC_DITHER_10_BPC (1<<5)
3818#define PIPEMISC_DITHER_6_BPC (2<<5)
3819#define PIPEMISC_DITHER_12_BPC (3<<5)
3820#define PIPEMISC_DITHER_ENABLE (1<<4)
3821#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3822#define PIPEMISC_DITHER_TYPE_SP (0<<2)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02003823#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07003824
Ville Syrjäläb41fbda2013-01-24 15:29:41 +02003825#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
Jesse Barnes79831172012-06-20 10:53:12 -07003826#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003827#define PIPEB_HLINE_INT_EN (1<<28)
3828#define PIPEB_VBLANK_INT_EN (1<<27)
Imre Deak579a9b02014-02-04 21:35:48 +02003829#define SPRITED_FLIP_DONE_INT_EN (1<<26)
3830#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
3831#define PLANEB_FLIP_DONE_INT_EN (1<<24)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03003832#define PIPE_PSR_INT_EN (1<<22)
Jesse Barnes79831172012-06-20 10:53:12 -07003833#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003834#define PIPEA_HLINE_INT_EN (1<<20)
3835#define PIPEA_VBLANK_INT_EN (1<<19)
Imre Deak579a9b02014-02-04 21:35:48 +02003836#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
3837#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003838#define PLANEA_FLIPDONE_INT_EN (1<<16)
Ville Syrjäläf3c67fd2014-04-09 13:28:05 +03003839#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
3840#define PIPEC_HLINE_INT_EN (1<<12)
3841#define PIPEC_VBLANK_INT_EN (1<<11)
3842#define SPRITEF_FLIPDONE_INT_EN (1<<10)
3843#define SPRITEE_FLIPDONE_INT_EN (1<<9)
3844#define PLANEC_FLIPDONE_INT_EN (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003845
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03003846#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3847#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
3848#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
3849#define PLANEC_INVALID_GTT_INT_EN (1<<25)
3850#define CURSORC_INVALID_GTT_INT_EN (1<<24)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003851#define CURSORB_INVALID_GTT_INT_EN (1<<23)
3852#define CURSORA_INVALID_GTT_INT_EN (1<<22)
3853#define SPRITED_INVALID_GTT_INT_EN (1<<21)
3854#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3855#define PLANEB_INVALID_GTT_INT_EN (1<<19)
3856#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3857#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3858#define PLANEA_INVALID_GTT_INT_EN (1<<16)
3859#define DPINVGTT_EN_MASK 0xff0000
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03003860#define DPINVGTT_EN_MASK_CHV 0xfff0000
3861#define SPRITEF_INVALID_GTT_STATUS (1<<11)
3862#define SPRITEE_INVALID_GTT_STATUS (1<<10)
3863#define PLANEC_INVALID_GTT_STATUS (1<<9)
3864#define CURSORC_INVALID_GTT_STATUS (1<<8)
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003865#define CURSORB_INVALID_GTT_STATUS (1<<7)
3866#define CURSORA_INVALID_GTT_STATUS (1<<6)
3867#define SPRITED_INVALID_GTT_STATUS (1<<5)
3868#define SPRITEC_INVALID_GTT_STATUS (1<<4)
3869#define PLANEB_INVALID_GTT_STATUS (1<<3)
3870#define SPRITEB_INVALID_GTT_STATUS (1<<2)
3871#define SPRITEA_INVALID_GTT_STATUS (1<<1)
3872#define PLANEA_INVALID_GTT_STATUS (1<<0)
3873#define DPINVGTT_STATUS_MASK 0xff
Ville Syrjäläbf67a6f2014-05-02 11:35:51 +03003874#define DPINVGTT_STATUS_MASK_CHV 0xfff
Jesse Barnesc46ce4d2012-03-28 13:39:24 -07003875
Jesse Barnes585fb112008-07-29 11:54:06 -07003876#define DSPARB 0x70030
3877#define DSPARB_CSTART_MASK (0x7f << 7)
3878#define DSPARB_CSTART_SHIFT 7
3879#define DSPARB_BSTART_MASK (0x7f)
3880#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08003881#define DSPARB_BEND_SHIFT 9 /* on 855 */
3882#define DSPARB_AEND_SHIFT 0
3883
Ville Syrjälä0a560672014-06-11 16:51:18 +03003884/* pnv/gen4/g4x/vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003885#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
Ville Syrjälä0a560672014-06-11 16:51:18 +03003886#define DSPFW_SR_SHIFT 23
3887#define DSPFW_SR_MASK (0x1ff<<23)
3888#define DSPFW_CURSORB_SHIFT 16
3889#define DSPFW_CURSORB_MASK (0x3f<<16)
3890#define DSPFW_PLANEB_SHIFT 8
3891#define DSPFW_PLANEB_MASK (0x7f<<8)
3892#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
3893#define DSPFW_PLANEA_SHIFT 0
3894#define DSPFW_PLANEA_MASK (0x7f<<0)
3895#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003896#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
Ville Syrjälä0a560672014-06-11 16:51:18 +03003897#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
3898#define DSPFW_FBC_SR_SHIFT 28
3899#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
3900#define DSPFW_FBC_HPLL_SR_SHIFT 24
3901#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
3902#define DSPFW_SPRITEB_SHIFT (16)
3903#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
3904#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
3905#define DSPFW_CURSORA_SHIFT 8
3906#define DSPFW_CURSORA_MASK (0x3f<<8)
3907#define DSPFW_PLANEC_SHIFT_OLD 0
3908#define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */
3909#define DSPFW_SPRITEA_SHIFT 0
3910#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
3911#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00003912#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
Ville Syrjälä0a560672014-06-11 16:51:18 +03003913#define DSPFW_HPLL_SR_EN (1<<31)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003914#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Ville Syrjälä0a560672014-06-11 16:51:18 +03003915#define DSPFW_CURSOR_SR_SHIFT 24
Zhao Yakuid4294342010-03-22 22:45:36 +08003916#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3917#define DSPFW_HPLL_CURSOR_SHIFT 16
3918#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
Ville Syrjälä0a560672014-06-11 16:51:18 +03003919#define DSPFW_HPLL_SR_SHIFT 0
3920#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
3921
3922/* vlv/chv */
3923#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
3924#define DSPFW_SPRITEB_WM1_SHIFT 16
3925#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
3926#define DSPFW_CURSORA_WM1_SHIFT 8
3927#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
3928#define DSPFW_SPRITEA_WM1_SHIFT 0
3929#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
3930#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
3931#define DSPFW_PLANEB_WM1_SHIFT 24
3932#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
3933#define DSPFW_PLANEA_WM1_SHIFT 16
3934#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
3935#define DSPFW_CURSORB_WM1_SHIFT 8
3936#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
3937#define DSPFW_CURSOR_SR_WM1_SHIFT 0
3938#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
3939#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
3940#define DSPFW_SR_WM1_SHIFT 0
3941#define DSPFW_SR_WM1_MASK (0x1ff<<0)
3942#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
3943#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
3944#define DSPFW_SPRITED_WM1_SHIFT 24
3945#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
3946#define DSPFW_SPRITED_SHIFT 16
3947#define DSPFW_SPRITED_MASK (0xff<<16)
3948#define DSPFW_SPRITEC_WM1_SHIFT 8
3949#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
3950#define DSPFW_SPRITEC_SHIFT 0
3951#define DSPFW_SPRITEC_MASK (0xff<<0)
3952#define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
3953#define DSPFW_SPRITEF_WM1_SHIFT 24
3954#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
3955#define DSPFW_SPRITEF_SHIFT 16
3956#define DSPFW_SPRITEF_MASK (0xff<<16)
3957#define DSPFW_SPRITEE_WM1_SHIFT 8
3958#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
3959#define DSPFW_SPRITEE_SHIFT 0
3960#define DSPFW_SPRITEE_MASK (0xff<<0)
3961#define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
3962#define DSPFW_PLANEC_WM1_SHIFT 24
3963#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
3964#define DSPFW_PLANEC_SHIFT 16
3965#define DSPFW_PLANEC_MASK (0xff<<16)
3966#define DSPFW_CURSORC_WM1_SHIFT 8
3967#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
3968#define DSPFW_CURSORC_SHIFT 0
3969#define DSPFW_CURSORC_MASK (0x3f<<0)
3970
3971/* vlv/chv high order bits */
3972#define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
3973#define DSPFW_SR_HI_SHIFT 24
3974#define DSPFW_SR_HI_MASK (1<<24)
3975#define DSPFW_SPRITEF_HI_SHIFT 23
3976#define DSPFW_SPRITEF_HI_MASK (1<<23)
3977#define DSPFW_SPRITEE_HI_SHIFT 22
3978#define DSPFW_SPRITEE_HI_MASK (1<<22)
3979#define DSPFW_PLANEC_HI_SHIFT 21
3980#define DSPFW_PLANEC_HI_MASK (1<<21)
3981#define DSPFW_SPRITED_HI_SHIFT 20
3982#define DSPFW_SPRITED_HI_MASK (1<<20)
3983#define DSPFW_SPRITEC_HI_SHIFT 16
3984#define DSPFW_SPRITEC_HI_MASK (1<<16)
3985#define DSPFW_PLANEB_HI_SHIFT 12
3986#define DSPFW_PLANEB_HI_MASK (1<<12)
3987#define DSPFW_SPRITEB_HI_SHIFT 8
3988#define DSPFW_SPRITEB_HI_MASK (1<<8)
3989#define DSPFW_SPRITEA_HI_SHIFT 4
3990#define DSPFW_SPRITEA_HI_MASK (1<<4)
3991#define DSPFW_PLANEA_HI_SHIFT 0
3992#define DSPFW_PLANEA_HI_MASK (1<<0)
3993#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
3994#define DSPFW_SR_WM1_HI_SHIFT 24
3995#define DSPFW_SR_WM1_HI_MASK (1<<24)
3996#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
3997#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
3998#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
3999#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4000#define DSPFW_PLANEC_WM1_HI_SHIFT 21
4001#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4002#define DSPFW_SPRITED_WM1_HI_SHIFT 20
4003#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4004#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4005#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4006#define DSPFW_PLANEB_WM1_HI_SHIFT 12
4007#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4008#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4009#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4010#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4011#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4012#define DSPFW_PLANEA_WM1_HI_SHIFT 0
4013#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004014
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004015/* drain latency register values*/
4016#define DRAIN_LATENCY_PRECISION_32 32
Zhenyu Wang22c5aee2014-02-28 06:50:06 +08004017#define DRAIN_LATENCY_PRECISION_64 64
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004018#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4019#define DDL_CURSOR_PRECISION_64 (1<<31)
4020#define DDL_CURSOR_PRECISION_32 (0<<31)
4021#define DDL_CURSOR_SHIFT 24
Gajanan Bhat01e184c2014-08-07 17:03:30 +05304022#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite)))
4023#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite)))
4024#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
Ville Syrjälä1abc4dc2014-06-26 17:02:37 +03004025#define DDL_PLANE_PRECISION_64 (1<<7)
4026#define DDL_PLANE_PRECISION_32 (0<<7)
4027#define DDL_PLANE_SHIFT 0
Gajanan Bhat0948c262014-08-07 01:58:24 +05304028#define DRAIN_LATENCY_MASK 0x7f
Gajanan Bhat12a3c052012-03-28 13:39:30 -07004029
Shaohua Li7662c8b2009-06-26 11:23:55 +08004030/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09004031#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08004032#define I915_FIFO_LINE_SIZE 64
4033#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09004034
Jesse Barnesceb04242012-03-28 13:39:22 -07004035#define VALLEYVIEW_FIFO_SIZE 255
Jesse Barnes0e442c62009-10-19 10:09:33 +09004036#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08004037#define I965_FIFO_SIZE 512
4038#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08004039#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004040#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004041#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09004042
Jesse Barnesceb04242012-03-28 13:39:22 -07004043#define VALLEYVIEW_MAX_WM 0xff
Jesse Barnes0e442c62009-10-19 10:09:33 +09004044#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08004045#define I915_MAX_WM 0x3f
4046
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004047#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4048#define PINEVIEW_FIFO_LINE_SIZE 64
4049#define PINEVIEW_MAX_WM 0x1ff
4050#define PINEVIEW_DFT_WM 0x3f
4051#define PINEVIEW_DFT_HPLLOFF_WM 0
4052#define PINEVIEW_GUARD_WM 10
4053#define PINEVIEW_CURSOR_FIFO 64
4054#define PINEVIEW_CURSOR_MAX_WM 0x3f
4055#define PINEVIEW_CURSOR_DFT_WM 0
4056#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08004057
Jesse Barnesceb04242012-03-28 13:39:22 -07004058#define VALLEYVIEW_CURSOR_MAX_WM 64
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004059#define I965_CURSOR_FIFO 64
4060#define I965_CURSOR_MAX_WM 32
4061#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004062
4063/* define the Watermark register on Ironlake */
4064#define WM0_PIPEA_ILK 0x45100
Ville Syrjälä1996d622013-10-09 19:18:07 +03004065#define WM0_PIPE_PLANE_MASK (0xffff<<16)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004066#define WM0_PIPE_PLANE_SHIFT 16
Ville Syrjälä1996d622013-10-09 19:18:07 +03004067#define WM0_PIPE_SPRITE_MASK (0xff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004068#define WM0_PIPE_SPRITE_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004069#define WM0_PIPE_CURSOR_MASK (0xff)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004070
4071#define WM0_PIPEB_ILK 0x45104
Jesse Barnesd6c892d2011-10-12 15:36:42 -07004072#define WM0_PIPEC_IVB 0x45200
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004073#define WM1_LP_ILK 0x45108
4074#define WM1_LP_SR_EN (1<<31)
4075#define WM1_LP_LATENCY_SHIFT 24
4076#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01004077#define WM1_LP_FBC_MASK (0xf<<20)
4078#define WM1_LP_FBC_SHIFT 20
Ville Syrjälä416f4722013-11-02 21:07:46 -07004079#define WM1_LP_FBC_SHIFT_BDW 19
Ville Syrjälä1996d622013-10-09 19:18:07 +03004080#define WM1_LP_SR_MASK (0x7ff<<8)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004081#define WM1_LP_SR_SHIFT 8
Ville Syrjälä1996d622013-10-09 19:18:07 +03004082#define WM1_LP_CURSOR_MASK (0xff)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004083#define WM2_LP_ILK 0x4510c
4084#define WM2_LP_EN (1<<31)
4085#define WM3_LP_ILK 0x45110
4086#define WM3_LP_EN (1<<31)
4087#define WM1S_LP_ILK 0x45120
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004088#define WM2S_LP_IVB 0x45124
4089#define WM3S_LP_IVB 0x45128
Jesse Barnesdd8849c2010-09-09 11:58:02 -07004090#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004091
Paulo Zanonicca32e92013-05-31 11:45:06 -03004092#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4093 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4094 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4095
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004096/* Memory latency timer register */
4097#define MLTR_ILK 0x11222
Jesse Barnesb79d4992010-12-21 13:10:23 -08004098#define MLTR_WM1_SHIFT 0
4099#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004100/* the unit of memory self-refresh latency time is 0.5us */
4101#define ILK_SRLT_MASK 0x3f
4102
Yuanhan Liu13982612010-12-15 15:42:31 +08004103
4104/* the address where we get all kinds of latency value */
4105#define SSKPD 0x5d10
4106#define SSKPD_WM_MASK 0x3f
4107#define SSKPD_WM0_SHIFT 0
4108#define SSKPD_WM1_SHIFT 8
4109#define SSKPD_WM2_SHIFT 16
4110#define SSKPD_WM3_SHIFT 24
4111
Jesse Barnes585fb112008-07-29 11:54:06 -07004112/*
4113 * The two pipe frame counter registers are not synchronized, so
4114 * reading a stable value is somewhat tricky. The following code
4115 * should work:
4116 *
4117 * do {
4118 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4119 * PIPE_FRAME_HIGH_SHIFT;
4120 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4121 * PIPE_FRAME_LOW_SHIFT);
4122 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4123 * PIPE_FRAME_HIGH_SHIFT);
4124 * } while (high1 != high2);
4125 * frame = (high1 << 8) | low1;
4126 */
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004127#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07004128#define PIPE_FRAME_HIGH_MASK 0x0000ffff
4129#define PIPE_FRAME_HIGH_SHIFT 0
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004130#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07004131#define PIPE_FRAME_LOW_MASK 0xff000000
4132#define PIPE_FRAME_LOW_SHIFT 24
4133#define PIPE_PIXEL_MASK 0x00ffffff
4134#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08004135/* GM45+ just has to be different */
Rafael Barbalhoeb6008a2014-03-31 18:21:29 +03004136#define _PIPEA_FRMCOUNT_GM45 0x70040
4137#define _PIPEA_FLIPCOUNT_GM45 0x70044
4138#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03004139#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -07004140
4141/* Cursor A & B regs */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004142#define _CURACNTR 0x70080
Jesse Barnes14b60392009-05-20 16:47:08 -04004143/* Old style CUR*CNTR flags (desktop 8xx) */
4144#define CURSOR_ENABLE 0x80000000
4145#define CURSOR_GAMMA_ENABLE 0x40000000
Ville Syrjälädc41c152014-08-13 11:57:05 +03004146#define CURSOR_STRIDE_SHIFT 28
4147#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004148#define CURSOR_PIPE_CSC_ENABLE (1<<24)
Jesse Barnes14b60392009-05-20 16:47:08 -04004149#define CURSOR_FORMAT_SHIFT 24
4150#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4151#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4152#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4153#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4154#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4155#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4156/* New style CUR*CNTR flags */
4157#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07004158#define CURSOR_MODE_DISABLE 0x00
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304159#define CURSOR_MODE_128_32B_AX 0x02
4160#define CURSOR_MODE_256_32B_AX 0x03
Jesse Barnes585fb112008-07-29 11:54:06 -07004161#define CURSOR_MODE_64_32B_AX 0x07
Sagar Kamble4726e0b2014-03-10 17:06:23 +05304162#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4163#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
Jesse Barnes585fb112008-07-29 11:54:06 -07004164#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Jesse Barnes14b60392009-05-20 16:47:08 -04004165#define MCURSOR_PIPE_SELECT (1 << 28)
4166#define MCURSOR_PIPE_A 0x00
4167#define MCURSOR_PIPE_B (1 << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07004168#define MCURSOR_GAMMA_ENABLE (1 << 26)
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03004169#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004170#define _CURABASE 0x70084
4171#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07004172#define CURSOR_POS_MASK 0x007FF
4173#define CURSOR_POS_SIGN 0x8000
4174#define CURSOR_X_SHIFT 0
4175#define CURSOR_Y_SHIFT 16
Jesse Barnes14b60392009-05-20 16:47:08 -04004176#define CURSIZE 0x700a0
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004177#define _CURBCNTR 0x700c0
4178#define _CURBBASE 0x700c4
4179#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07004180
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004181#define _CURBCNTR_IVB 0x71080
4182#define _CURBBASE_IVB 0x71084
4183#define _CURBPOS_IVB 0x71088
4184
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004185#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4186 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4187 dev_priv->info.display_mmio_offset)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00004188
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03004189#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4190#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4191#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4192
4193#define CURSOR_A_OFFSET 0x70080
4194#define CURSOR_B_OFFSET 0x700c0
4195#define CHV_CURSOR_C_OFFSET 0x700e0
4196#define IVB_CURSOR_B_OFFSET 0x71080
4197#define IVB_CURSOR_C_OFFSET 0x72080
Jesse Barnes65a21cd2011-10-12 11:10:21 -07004198
Jesse Barnes585fb112008-07-29 11:54:06 -07004199/* Display A control */
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004200#define _DSPACNTR 0x70180
Jesse Barnes585fb112008-07-29 11:54:06 -07004201#define DISPLAY_PLANE_ENABLE (1<<31)
4202#define DISPLAY_PLANE_DISABLE 0
4203#define DISPPLANE_GAMMA_ENABLE (1<<30)
4204#define DISPPLANE_GAMMA_DISABLE 0
4205#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004206#define DISPPLANE_YUV422 (0x0<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004207#define DISPPLANE_8BPP (0x2<<26)
Ville Syrjälä57779d02012-10-31 17:50:14 +02004208#define DISPPLANE_BGRA555 (0x3<<26)
4209#define DISPPLANE_BGRX555 (0x4<<26)
4210#define DISPPLANE_BGRX565 (0x5<<26)
4211#define DISPPLANE_BGRX888 (0x6<<26)
4212#define DISPPLANE_BGRA888 (0x7<<26)
4213#define DISPPLANE_RGBX101010 (0x8<<26)
4214#define DISPPLANE_RGBA101010 (0x9<<26)
4215#define DISPPLANE_BGRX101010 (0xa<<26)
4216#define DISPPLANE_RGBX161616 (0xc<<26)
4217#define DISPPLANE_RGBX888 (0xe<<26)
4218#define DISPPLANE_RGBA888 (0xf<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07004219#define DISPPLANE_STEREO_ENABLE (1<<25)
4220#define DISPPLANE_STEREO_DISABLE 0
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004221#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb24e7172011-01-04 15:09:30 -08004222#define DISPPLANE_SEL_PIPE_SHIFT 24
4223#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004224#define DISPPLANE_SEL_PIPE_A 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08004225#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07004226#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4227#define DISPPLANE_SRC_KEY_DISABLE 0
4228#define DISPPLANE_LINE_DOUBLE (1<<20)
4229#define DISPPLANE_NO_LINE_DOUBLE 0
4230#define DISPPLANE_STEREO_POLARITY_FIRST 0
4231#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Sonika Jindal48404c12014-08-22 14:06:04 +05304232#define DISPPLANE_ROTATE_180 (1<<15)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004233#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07004234#define DISPPLANE_TILED (1<<10)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004235#define _DSPAADDR 0x70184
4236#define _DSPASTRIDE 0x70188
4237#define _DSPAPOS 0x7018C /* reserved */
4238#define _DSPASIZE 0x70190
4239#define _DSPASURF 0x7019C /* 965+ only */
4240#define _DSPATILEOFF 0x701A4 /* 965+ only */
4241#define _DSPAOFFSET 0x701A4 /* HSW */
4242#define _DSPASURFLIVE 0x701AC
Jesse Barnes585fb112008-07-29 11:54:06 -07004243
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004244#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4245#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4246#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4247#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4248#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4249#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4250#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
Daniel Vettere506a0c2012-07-05 12:17:29 +02004251#define DSPLINOFF(plane) DSPADDR(plane)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004252#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4253#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
Chris Wilson5eddb702010-09-11 13:48:45 +01004254
Armin Reese446f2542012-03-30 16:20:16 -07004255/* Display/Sprite base address macros */
4256#define DISP_BASEADDR_MASK (0xfffff000)
4257#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
4258#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
Armin Reese446f2542012-03-30 16:20:16 -07004259
Jesse Barnes585fb112008-07-29 11:54:06 -07004260/* VBIOS flags */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004261#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4262#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4263#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4264#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4265#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4266#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4267#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4268#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4269#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4270#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4271#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4272#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4273#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
Jesse Barnes585fb112008-07-29 11:54:06 -07004274
4275/* Pipe B */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004276#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4277#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4278#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
Ville Syrjälä25a2e2d2013-10-11 22:24:41 +03004279#define _PIPEBFRAMEHIGH 0x71040
4280#define _PIPEBFRAMEPIXEL 0x71044
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004281#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4282#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
Jesse Barnes9880b7a2009-02-06 10:22:41 -08004283
Jesse Barnes585fb112008-07-29 11:54:06 -07004284
4285/* Display B control */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004286#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
Jesse Barnes585fb112008-07-29 11:54:06 -07004287#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
4288#define DISPPLANE_ALPHA_TRANS_DISABLE 0
4289#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
4290#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Damien Lespiau5c969aa2014-02-07 19:12:48 +00004291#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4292#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4293#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4294#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4295#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4296#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4297#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4298#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
Jesse Barnes585fb112008-07-29 11:54:06 -07004299
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004300/* Sprite A control */
4301#define _DVSACNTR 0x72180
4302#define DVS_ENABLE (1<<31)
4303#define DVS_GAMMA_ENABLE (1<<30)
4304#define DVS_PIXFORMAT_MASK (3<<25)
4305#define DVS_FORMAT_YUV422 (0<<25)
4306#define DVS_FORMAT_RGBX101010 (1<<25)
4307#define DVS_FORMAT_RGBX888 (2<<25)
4308#define DVS_FORMAT_RGBX161616 (3<<25)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004309#define DVS_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004310#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08004311#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004312#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
4313#define DVS_YUV_ORDER_YUYV (0<<16)
4314#define DVS_YUV_ORDER_UYVY (1<<16)
4315#define DVS_YUV_ORDER_YVYU (2<<16)
4316#define DVS_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05304317#define DVS_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004318#define DVS_DEST_KEY (1<<2)
4319#define DVS_TRICKLE_FEED_DISABLE (1<<14)
4320#define DVS_TILED (1<<10)
4321#define _DVSALINOFF 0x72184
4322#define _DVSASTRIDE 0x72188
4323#define _DVSAPOS 0x7218c
4324#define _DVSASIZE 0x72190
4325#define _DVSAKEYVAL 0x72194
4326#define _DVSAKEYMSK 0x72198
4327#define _DVSASURF 0x7219c
4328#define _DVSAKEYMAXVAL 0x721a0
4329#define _DVSATILEOFF 0x721a4
4330#define _DVSASURFLIVE 0x721ac
4331#define _DVSASCALE 0x72204
4332#define DVS_SCALE_ENABLE (1<<31)
4333#define DVS_FILTER_MASK (3<<29)
4334#define DVS_FILTER_MEDIUM (0<<29)
4335#define DVS_FILTER_ENHANCING (1<<29)
4336#define DVS_FILTER_SOFTENING (2<<29)
4337#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4338#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
4339#define _DVSAGAMC 0x72300
4340
4341#define _DVSBCNTR 0x73180
4342#define _DVSBLINOFF 0x73184
4343#define _DVSBSTRIDE 0x73188
4344#define _DVSBPOS 0x7318c
4345#define _DVSBSIZE 0x73190
4346#define _DVSBKEYVAL 0x73194
4347#define _DVSBKEYMSK 0x73198
4348#define _DVSBSURF 0x7319c
4349#define _DVSBKEYMAXVAL 0x731a0
4350#define _DVSBTILEOFF 0x731a4
4351#define _DVSBSURFLIVE 0x731ac
4352#define _DVSBSCALE 0x73204
4353#define _DVSBGAMC 0x73300
4354
4355#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4356#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4357#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4358#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4359#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08004360#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004361#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4362#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4363#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08004364#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4365#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004366#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004367
4368#define _SPRA_CTL 0x70280
4369#define SPRITE_ENABLE (1<<31)
4370#define SPRITE_GAMMA_ENABLE (1<<30)
4371#define SPRITE_PIXFORMAT_MASK (7<<25)
4372#define SPRITE_FORMAT_YUV422 (0<<25)
4373#define SPRITE_FORMAT_RGBX101010 (1<<25)
4374#define SPRITE_FORMAT_RGBX888 (2<<25)
4375#define SPRITE_FORMAT_RGBX161616 (3<<25)
4376#define SPRITE_FORMAT_YUV444 (4<<25)
4377#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02004378#define SPRITE_PIPE_CSC_ENABLE (1<<24)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004379#define SPRITE_SOURCE_KEY (1<<22)
4380#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
4381#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
4382#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
4383#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
4384#define SPRITE_YUV_ORDER_YUYV (0<<16)
4385#define SPRITE_YUV_ORDER_UYVY (1<<16)
4386#define SPRITE_YUV_ORDER_YVYU (2<<16)
4387#define SPRITE_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05304388#define SPRITE_ROTATE_180 (1<<15)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004389#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
4390#define SPRITE_INT_GAMMA_ENABLE (1<<13)
4391#define SPRITE_TILED (1<<10)
4392#define SPRITE_DEST_KEY (1<<2)
4393#define _SPRA_LINOFF 0x70284
4394#define _SPRA_STRIDE 0x70288
4395#define _SPRA_POS 0x7028c
4396#define _SPRA_SIZE 0x70290
4397#define _SPRA_KEYVAL 0x70294
4398#define _SPRA_KEYMSK 0x70298
4399#define _SPRA_SURF 0x7029c
4400#define _SPRA_KEYMAX 0x702a0
4401#define _SPRA_TILEOFF 0x702a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01004402#define _SPRA_OFFSET 0x702a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004403#define _SPRA_SURFLIVE 0x702ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004404#define _SPRA_SCALE 0x70304
4405#define SPRITE_SCALE_ENABLE (1<<31)
4406#define SPRITE_FILTER_MASK (3<<29)
4407#define SPRITE_FILTER_MEDIUM (0<<29)
4408#define SPRITE_FILTER_ENHANCING (1<<29)
4409#define SPRITE_FILTER_SOFTENING (2<<29)
4410#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4411#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
4412#define _SPRA_GAMC 0x70400
4413
4414#define _SPRB_CTL 0x71280
4415#define _SPRB_LINOFF 0x71284
4416#define _SPRB_STRIDE 0x71288
4417#define _SPRB_POS 0x7128c
4418#define _SPRB_SIZE 0x71290
4419#define _SPRB_KEYVAL 0x71294
4420#define _SPRB_KEYMSK 0x71298
4421#define _SPRB_SURF 0x7129c
4422#define _SPRB_KEYMAX 0x712a0
4423#define _SPRB_TILEOFF 0x712a4
Damien Lespiauc54173a2012-10-26 18:20:11 +01004424#define _SPRB_OFFSET 0x712a4
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004425#define _SPRB_SURFLIVE 0x712ac
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004426#define _SPRB_SCALE 0x71304
4427#define _SPRB_GAMC 0x71400
4428
4429#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4430#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4431#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4432#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
4433#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4434#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4435#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4436#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4437#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4438#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
Damien Lespiauc54173a2012-10-26 18:20:11 +01004439#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004440#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4441#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
Ville Syrjälä32ae46bf2012-11-01 19:26:45 +02004442#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004443
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004444#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004445#define SP_ENABLE (1<<31)
Ville Syrjälä4ea67bc2013-11-18 18:32:38 -08004446#define SP_GAMMA_ENABLE (1<<30)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004447#define SP_PIXFORMAT_MASK (0xf<<26)
4448#define SP_FORMAT_YUV422 (0<<26)
4449#define SP_FORMAT_BGR565 (5<<26)
4450#define SP_FORMAT_BGRX8888 (6<<26)
4451#define SP_FORMAT_BGRA8888 (7<<26)
4452#define SP_FORMAT_RGBX1010102 (8<<26)
4453#define SP_FORMAT_RGBA1010102 (9<<26)
4454#define SP_FORMAT_RGBX8888 (0xe<<26)
4455#define SP_FORMAT_RGBA8888 (0xf<<26)
4456#define SP_SOURCE_KEY (1<<22)
4457#define SP_YUV_BYTE_ORDER_MASK (3<<16)
4458#define SP_YUV_ORDER_YUYV (0<<16)
4459#define SP_YUV_ORDER_UYVY (1<<16)
4460#define SP_YUV_ORDER_YVYU (2<<16)
4461#define SP_YUV_ORDER_VYUY (3<<16)
Ville Syrjälä76eebda2014-08-05 11:26:52 +05304462#define SP_ROTATE_180 (1<<15)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004463#define SP_TILED (1<<10)
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004464#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4465#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4466#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4467#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4468#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4469#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4470#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4471#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4472#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4473#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
4474#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004475
Ville Syrjälä921c3b62013-06-25 14:16:35 +03004476#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4477#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4478#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4479#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4480#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4481#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4482#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4483#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4484#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4485#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4486#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4487#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
Jesse Barnes7f1f3852013-04-02 11:22:20 -07004488
4489#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
4490#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
4491#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
4492#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
4493#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
4494#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
4495#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
4496#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
4497#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4498#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
4499#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
4500#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
4501
Jesse Barnes585fb112008-07-29 11:54:06 -07004502/* VBIOS regs */
4503#define VGACNTRL 0x71400
4504# define VGA_DISP_DISABLE (1 << 31)
4505# define VGA_2X_MODE (1 << 30)
4506# define VGA_PIPE_B_SELECT (1 << 29)
4507
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02004508#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
4509
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004510/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004511
4512#define CPU_VGACNTRL 0x41000
4513
4514#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
4515#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
4516#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
4517#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
4518#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
4519#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
4520#define DIGITAL_PORTA_NO_DETECT (0 << 0)
4521#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
4522#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
4523
4524/* refresh rate hardware control */
4525#define RR_HW_CTL 0x45300
4526#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
4527#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
4528
4529#define FDI_PLL_BIOS_0 0x46000
Chris Wilson021357a2010-09-07 20:54:59 +01004530#define FDI_PLL_FB_CLOCK_MASK 0xff
Zhenyu Wangb9055052009-06-05 15:38:38 +08004531#define FDI_PLL_BIOS_1 0x46004
4532#define FDI_PLL_BIOS_2 0x46008
4533#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
4534#define DISPLAY_PORT_PLL_BIOS_1 0x46010
4535#define DISPLAY_PORT_PLL_BIOS_2 0x46014
4536
Eric Anholt8956c8b2010-03-18 13:21:14 -07004537#define PCH_3DCGDIS0 0x46020
4538# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
4539# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
4540
Eric Anholt06f37752010-12-14 10:06:46 -08004541#define PCH_3DCGDIS1 0x46024
4542# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
4543
Zhenyu Wangb9055052009-06-05 15:38:38 +08004544#define FDI_PLL_FREQ_CTL 0x46030
4545#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
4546#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
4547#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
4548
4549
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004550#define _PIPEA_DATA_M1 0x60030
Chris Wilson5eddb702010-09-11 13:48:45 +01004551#define PIPE_DATA_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004552#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01004553#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004554
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004555#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01004556#define PIPE_DATA_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004557#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01004558#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004559
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004560#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01004561#define PIPE_LINK_M1_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004562#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01004563#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004564
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004565#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01004566#define PIPE_LINK_M2_OFFSET 0
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004567#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01004568#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08004569
4570/* PIPEB timing regs are same start from 0x61000 */
4571
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004572#define _PIPEB_DATA_M1 0x61030
4573#define _PIPEB_DATA_N1 0x61034
4574#define _PIPEB_DATA_M2 0x61038
4575#define _PIPEB_DATA_N2 0x6103c
4576#define _PIPEB_LINK_M1 0x61040
4577#define _PIPEB_LINK_N1 0x61044
4578#define _PIPEB_LINK_M2 0x61048
4579#define _PIPEB_LINK_N2 0x6104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08004580
Antti Koskipaaa57c7742014-02-04 14:22:24 +02004581#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
4582#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
4583#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
4584#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
4585#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
4586#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
4587#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
4588#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004589
4590/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004591/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
4592#define _PFA_CTL_1 0x68080
4593#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08004594#define PF_ENABLE (1<<31)
Paulo Zanoni13888d72012-11-20 13:27:41 -02004595#define PF_PIPE_SEL_MASK_IVB (3<<29)
4596#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08004597#define PF_FILTER_MASK (3<<23)
4598#define PF_FILTER_PROGRAMMED (0<<23)
4599#define PF_FILTER_MED_3x3 (1<<23)
4600#define PF_FILTER_EDGE_ENHANCE (2<<23)
4601#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004602#define _PFA_WIN_SZ 0x68074
4603#define _PFB_WIN_SZ 0x68874
4604#define _PFA_WIN_POS 0x68070
4605#define _PFB_WIN_POS 0x68870
4606#define _PFA_VSCALE 0x68084
4607#define _PFB_VSCALE 0x68884
4608#define _PFA_HSCALE 0x68090
4609#define _PFB_HSCALE 0x68890
4610
4611#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4612#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4613#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4614#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4615#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004616
4617/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004618#define _LGC_PALETTE_A 0x4a000
4619#define _LGC_PALETTE_B 0x4a800
4620#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004621
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004622#define _GAMMA_MODE_A 0x4a480
4623#define _GAMMA_MODE_B 0x4ac80
4624#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4625#define GAMMA_MODE_MODE_MASK (3 << 0)
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02004626#define GAMMA_MODE_MODE_8BIT (0 << 0)
4627#define GAMMA_MODE_MODE_10BIT (1 << 0)
4628#define GAMMA_MODE_MODE_12BIT (2 << 0)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004629#define GAMMA_MODE_MODE_SPLIT (3 << 0)
4630
Zhenyu Wangb9055052009-06-05 15:38:38 +08004631/* interrupts */
4632#define DE_MASTER_IRQ_CONTROL (1 << 31)
4633#define DE_SPRITEB_FLIP_DONE (1 << 29)
4634#define DE_SPRITEA_FLIP_DONE (1 << 28)
4635#define DE_PLANEB_FLIP_DONE (1 << 27)
4636#define DE_PLANEA_FLIP_DONE (1 << 26)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004637#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004638#define DE_PCU_EVENT (1 << 25)
4639#define DE_GTT_FAULT (1 << 24)
4640#define DE_POISON (1 << 23)
4641#define DE_PERFORM_COUNTER (1 << 22)
4642#define DE_PCH_EVENT (1 << 21)
4643#define DE_AUX_CHANNEL_A (1 << 20)
4644#define DE_DP_A_HOTPLUG (1 << 19)
4645#define DE_GSE (1 << 18)
4646#define DE_PIPEB_VBLANK (1 << 15)
4647#define DE_PIPEB_EVEN_FIELD (1 << 14)
4648#define DE_PIPEB_ODD_FIELD (1 << 13)
4649#define DE_PIPEB_LINE_COMPARE (1 << 12)
4650#define DE_PIPEB_VSYNC (1 << 11)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02004651#define DE_PIPEB_CRC_DONE (1 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004652#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4653#define DE_PIPEA_VBLANK (1 << 7)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004654#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004655#define DE_PIPEA_EVEN_FIELD (1 << 6)
4656#define DE_PIPEA_ODD_FIELD (1 << 5)
4657#define DE_PIPEA_LINE_COMPARE (1 << 4)
4658#define DE_PIPEA_VSYNC (1 << 3)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02004659#define DE_PIPEA_CRC_DONE (1 << 2)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004660#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004661#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004662#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
Zhenyu Wangb9055052009-06-05 15:38:38 +08004663
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004664/* More Ivybridge lolz */
Paulo Zanoni86642812013-04-12 17:57:57 -03004665#define DE_ERR_INT_IVB (1<<30)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004666#define DE_GSE_IVB (1<<29)
4667#define DE_PCH_EVENT_IVB (1<<28)
4668#define DE_DP_A_HOTPLUG_IVB (1<<27)
4669#define DE_AUX_CHANNEL_A_IVB (1<<26)
Chris Wilsonb615b572012-05-02 09:52:12 +01004670#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
4671#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
4672#define DE_PIPEC_VBLANK_IVB (1<<10)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004673#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004674#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004675#define DE_PIPEB_VBLANK_IVB (1<<5)
Chris Wilsonb615b572012-05-02 09:52:12 +01004676#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
4677#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
Daniel Vetter40da17c2013-10-21 18:04:36 +02004678#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07004679#define DE_PIPEA_VBLANK_IVB (1<<0)
Paulo Zanonib5184212013-07-12 20:00:08 -03004680#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4681
Jesse Barnes7eea1dd2012-03-22 14:38:44 -07004682#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
4683#define MASTER_INTERRUPT_ENABLE (1<<31)
4684
Zhenyu Wangb9055052009-06-05 15:38:38 +08004685#define DEISR 0x44000
4686#define DEIMR 0x44004
4687#define DEIIR 0x44008
4688#define DEIER 0x4400c
4689
Zhenyu Wangb9055052009-06-05 15:38:38 +08004690#define GTISR 0x44010
4691#define GTIMR 0x44014
4692#define GTIIR 0x44018
4693#define GTIER 0x4401c
4694
Ben Widawskyabd58f02013-11-02 21:07:09 -07004695#define GEN8_MASTER_IRQ 0x44200
4696#define GEN8_MASTER_IRQ_CONTROL (1<<31)
4697#define GEN8_PCU_IRQ (1<<30)
4698#define GEN8_DE_PCH_IRQ (1<<23)
4699#define GEN8_DE_MISC_IRQ (1<<22)
4700#define GEN8_DE_PORT_IRQ (1<<20)
4701#define GEN8_DE_PIPE_C_IRQ (1<<18)
4702#define GEN8_DE_PIPE_B_IRQ (1<<17)
4703#define GEN8_DE_PIPE_A_IRQ (1<<16)
Daniel Vetterc42664c2013-11-07 11:05:40 +01004704#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
Ben Widawskyabd58f02013-11-02 21:07:09 -07004705#define GEN8_GT_VECS_IRQ (1<<6)
Ben Widawsky09610212014-05-15 20:58:08 +03004706#define GEN8_GT_PM_IRQ (1<<4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004707#define GEN8_GT_VCS2_IRQ (1<<3)
4708#define GEN8_GT_VCS1_IRQ (1<<2)
4709#define GEN8_GT_BCS_IRQ (1<<1)
4710#define GEN8_GT_RCS_IRQ (1<<0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004711
4712#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
4713#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
4714#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
4715#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
4716
4717#define GEN8_BCS_IRQ_SHIFT 16
4718#define GEN8_RCS_IRQ_SHIFT 0
4719#define GEN8_VCS2_IRQ_SHIFT 16
4720#define GEN8_VCS1_IRQ_SHIFT 0
4721#define GEN8_VECS_IRQ_SHIFT 0
4722
4723#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
4724#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
4725#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
4726#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
Daniel Vetter38d83c962013-11-07 11:05:46 +01004727#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004728#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4729#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4730#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4731#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4732#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4733#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
Damien Lespiaud0e1f1c2014-04-08 01:22:44 +01004734#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004735#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4736#define GEN8_PIPE_VSYNC (1 << 1)
4737#define GEN8_PIPE_VBLANK (1 << 0)
Daniel Vetter30100f22013-11-07 14:49:24 +01004738#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4739 (GEN8_PIPE_CURSOR_FAULT | \
4740 GEN8_PIPE_SPRITE_FAULT | \
4741 GEN8_PIPE_PRIMARY_FAULT)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004742
4743#define GEN8_DE_PORT_ISR 0x44440
4744#define GEN8_DE_PORT_IMR 0x44444
4745#define GEN8_DE_PORT_IIR 0x44448
4746#define GEN8_DE_PORT_IER 0x4444c
Daniel Vetter6d766f02013-11-07 14:49:55 +01004747#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
4748#define GEN8_AUX_CHANNEL_A (1 << 0)
Ben Widawskyabd58f02013-11-02 21:07:09 -07004749
4750#define GEN8_DE_MISC_ISR 0x44460
4751#define GEN8_DE_MISC_IMR 0x44464
4752#define GEN8_DE_MISC_IIR 0x44468
4753#define GEN8_DE_MISC_IER 0x4446c
4754#define GEN8_DE_MISC_GSE (1 << 27)
4755
4756#define GEN8_PCU_ISR 0x444e0
4757#define GEN8_PCU_IMR 0x444e4
4758#define GEN8_PCU_IIR 0x444e8
4759#define GEN8_PCU_IER 0x444ec
4760
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004761#define ILK_DISPLAY_CHICKEN2 0x42004
Eric Anholt67e92af2010-11-06 14:53:33 -07004762/* Required on all Ironlake and Sandybridge according to the B-Spec. */
4763#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004764#define ILK_DPARB_GATE (1<<22)
4765#define ILK_VSDPFD_FULL (1<<21)
Damien Lespiaue3589902014-02-07 19:12:50 +00004766#define FUSE_STRAP 0x42014
4767#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
4768#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
4769#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
4770#define ILK_HDCP_DISABLE (1 << 25)
4771#define ILK_eDP_A_DISABLE (1 << 24)
4772#define HSW_CDCLK_LIMIT (1 << 24)
4773#define ILK_DESKTOP (1 << 23)
Yuanhan Liu13982612010-12-15 15:42:31 +08004774
Damien Lespiau231e54f2012-10-19 17:55:41 +01004775#define ILK_DSPCLK_GATE_D 0x42020
4776#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
4777#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
4778#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
4779#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
4780#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004781
Eric Anholt116ac8d2011-12-21 10:31:09 -08004782#define IVB_CHICKEN3 0x4200c
4783# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
4784# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
4785
Paulo Zanoni90a88642013-05-03 17:23:45 -03004786#define CHICKEN_PAR1_1 0x42080
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07004787#define DPA_MASK_VBLANK_SRD (1 << 15)
Paulo Zanoni90a88642013-05-03 17:23:45 -03004788#define FORCE_ARB_IDLE_PLANES (1 << 14)
4789
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07004790#define _CHICKEN_PIPESL_1_A 0x420b0
4791#define _CHICKEN_PIPESL_1_B 0x420b4
Ville Syrjälä8f670bb2014-03-05 13:05:47 +02004792#define HSW_FBCQ_DIS (1 << 22)
4793#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
Ben Widawskyfe4ab3c2013-11-02 21:07:54 -07004794#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4795
Zhenyu Wang553bd142009-09-02 10:57:52 +08004796#define DISP_ARB_CTL 0x45000
4797#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004798#define DISP_FBC_WM_DIS (1<<15)
Ville Syrjäläac9545f2013-12-05 15:51:28 +02004799#define DISP_ARB_CTL2 0x45004
4800#define DISP_DATA_PARTITION_5_6 (1<<6)
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07004801#define GEN7_MSG_CTL 0x45010
4802#define WAIT_FOR_PCH_RESET_ACK (1<<1)
4803#define WAIT_FOR_PCH_FLR_ACK (1<<0)
Daniel Vetter6ba844b2014-01-22 23:39:30 +01004804#define HSW_NDE_RSTWRN_OPT 0x46408
4805#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
Zhenyu Wang553bd142009-09-02 10:57:52 +08004806
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004807/* GEN7 chicken */
Kenneth Graunked71de142012-02-08 12:53:52 -08004808#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
4809# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
Ben Widawskya75f3622013-11-02 21:07:59 -07004810#define COMMON_SLICE_CHICKEN2 0x7014
4811# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
Kenneth Graunked71de142012-02-08 12:53:52 -08004812
Ville Syrjälä031994e2014-01-22 21:32:46 +02004813#define GEN7_L3SQCREG1 0xB010
4814#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
4815
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004816#define GEN7_L3CNTLREG1 0xB01C
Chris Wilson1af84522014-02-14 22:34:43 +00004817#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
Jesse Barnesd0cf5ea2012-10-25 12:15:41 -07004818#define GEN7_L3AGDIS (1<<19)
Brad Volkinc9224fa2014-06-17 14:10:34 -07004819#define GEN7_L3CNTLREG2 0xB020
4820#define GEN7_L3CNTLREG3 0xB024
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08004821
4822#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
4823#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
4824
Jesse Barnes61939d92012-10-02 17:43:38 -05004825#define GEN7_L3SQCREG4 0xb034
4826#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
4827
Ben Widawsky63801f22013-12-12 17:26:03 -08004828/* GEN8 chicken */
4829#define HDC_CHICKEN0 0x7300
4830#define HDC_FORCE_NON_COHERENT (1<<4)
4831
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08004832/* WaCatErrorRejectionIssue */
4833#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
4834#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
4835
Francisco Jerezf3fc4882013-10-02 15:53:16 -07004836#define HSW_SCRATCH1 0xb038
4837#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4838
Zhenyu Wangb9055052009-06-05 15:38:38 +08004839/* PCH */
4840
Adam Jackson23e81d62012-06-06 15:45:44 -04004841/* south display engine interrupt: IBX */
Jesse Barnes776ad802011-01-04 15:09:39 -08004842#define SDE_AUDIO_POWER_D (1 << 27)
4843#define SDE_AUDIO_POWER_C (1 << 26)
4844#define SDE_AUDIO_POWER_B (1 << 25)
4845#define SDE_AUDIO_POWER_SHIFT (25)
4846#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4847#define SDE_GMBUS (1 << 24)
4848#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4849#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4850#define SDE_AUDIO_HDCP_MASK (3 << 22)
4851#define SDE_AUDIO_TRANSB (1 << 21)
4852#define SDE_AUDIO_TRANSA (1 << 20)
4853#define SDE_AUDIO_TRANS_MASK (3 << 20)
4854#define SDE_POISON (1 << 19)
4855/* 18 reserved */
4856#define SDE_FDI_RXB (1 << 17)
4857#define SDE_FDI_RXA (1 << 16)
4858#define SDE_FDI_MASK (3 << 16)
4859#define SDE_AUXD (1 << 15)
4860#define SDE_AUXC (1 << 14)
4861#define SDE_AUXB (1 << 13)
4862#define SDE_AUX_MASK (7 << 13)
4863/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004864#define SDE_CRT_HOTPLUG (1 << 11)
4865#define SDE_PORTD_HOTPLUG (1 << 10)
4866#define SDE_PORTC_HOTPLUG (1 << 9)
4867#define SDE_PORTB_HOTPLUG (1 << 8)
4868#define SDE_SDVOB_HOTPLUG (1 << 6)
Egbert Eiche5868a32013-02-28 04:17:12 -05004869#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4870 SDE_SDVOB_HOTPLUG | \
4871 SDE_PORTB_HOTPLUG | \
4872 SDE_PORTC_HOTPLUG | \
4873 SDE_PORTD_HOTPLUG)
Jesse Barnes776ad802011-01-04 15:09:39 -08004874#define SDE_TRANSB_CRC_DONE (1 << 5)
4875#define SDE_TRANSB_CRC_ERR (1 << 4)
4876#define SDE_TRANSB_FIFO_UNDER (1 << 3)
4877#define SDE_TRANSA_CRC_DONE (1 << 2)
4878#define SDE_TRANSA_CRC_ERR (1 << 1)
4879#define SDE_TRANSA_FIFO_UNDER (1 << 0)
4880#define SDE_TRANS_MASK (0x3f)
Adam Jackson23e81d62012-06-06 15:45:44 -04004881
4882/* south display engine interrupt: CPT/PPT */
4883#define SDE_AUDIO_POWER_D_CPT (1 << 31)
4884#define SDE_AUDIO_POWER_C_CPT (1 << 30)
4885#define SDE_AUDIO_POWER_B_CPT (1 << 29)
4886#define SDE_AUDIO_POWER_SHIFT_CPT 29
4887#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4888#define SDE_AUXD_CPT (1 << 27)
4889#define SDE_AUXC_CPT (1 << 26)
4890#define SDE_AUXB_CPT (1 << 25)
4891#define SDE_AUX_MASK_CPT (7 << 25)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004892#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4893#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4894#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Adam Jackson23e81d62012-06-06 15:45:44 -04004895#define SDE_CRT_HOTPLUG_CPT (1 << 19)
Daniel Vetter73c352a2013-03-26 22:38:43 +01004896#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01004897#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
Daniel Vetter73c352a2013-03-26 22:38:43 +01004898 SDE_SDVOB_HOTPLUG_CPT | \
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01004899 SDE_PORTD_HOTPLUG_CPT | \
4900 SDE_PORTC_HOTPLUG_CPT | \
4901 SDE_PORTB_HOTPLUG_CPT)
Adam Jackson23e81d62012-06-06 15:45:44 -04004902#define SDE_GMBUS_CPT (1 << 17)
Paulo Zanoni86642812013-04-12 17:57:57 -03004903#define SDE_ERROR_CPT (1 << 16)
Adam Jackson23e81d62012-06-06 15:45:44 -04004904#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4905#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4906#define SDE_FDI_RXC_CPT (1 << 8)
4907#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4908#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4909#define SDE_FDI_RXB_CPT (1 << 4)
4910#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4911#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4912#define SDE_FDI_RXA_CPT (1 << 0)
4913#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4914 SDE_AUDIO_CP_REQ_B_CPT | \
4915 SDE_AUDIO_CP_REQ_A_CPT)
4916#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4917 SDE_AUDIO_CP_CHG_B_CPT | \
4918 SDE_AUDIO_CP_CHG_A_CPT)
4919#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4920 SDE_FDI_RXB_CPT | \
4921 SDE_FDI_RXA_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004922
4923#define SDEISR 0xc4000
4924#define SDEIMR 0xc4004
4925#define SDEIIR 0xc4008
4926#define SDEIER 0xc400c
4927
Paulo Zanoni86642812013-04-12 17:57:57 -03004928#define SERR_INT 0xc4040
Paulo Zanonide032bf2013-04-12 17:57:58 -03004929#define SERR_INT_POISON (1<<31)
Paulo Zanoni86642812013-04-12 17:57:57 -03004930#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
4931#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
4932#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
Daniel Vetter1dd246f2013-07-10 08:30:23 +02004933#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
Paulo Zanoni86642812013-04-12 17:57:57 -03004934
Zhenyu Wangb9055052009-06-05 15:38:38 +08004935/* digital port hotplug */
Keith Packard7fe0b972011-09-19 13:31:02 -07004936#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
Zhenyu Wangb9055052009-06-05 15:38:38 +08004937#define PORTD_HOTPLUG_ENABLE (1 << 20)
4938#define PORTD_PULSE_DURATION_2ms (0)
4939#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
4940#define PORTD_PULSE_DURATION_6ms (2 << 18)
4941#define PORTD_PULSE_DURATION_100ms (3 << 18)
Keith Packard7fe0b972011-09-19 13:31:02 -07004942#define PORTD_PULSE_DURATION_MASK (3 << 18)
Damien Lespiaub6965192012-12-13 16:08:59 +00004943#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
4944#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4945#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4946#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004947#define PORTC_HOTPLUG_ENABLE (1 << 12)
4948#define PORTC_PULSE_DURATION_2ms (0)
4949#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
4950#define PORTC_PULSE_DURATION_6ms (2 << 10)
4951#define PORTC_PULSE_DURATION_100ms (3 << 10)
Keith Packard7fe0b972011-09-19 13:31:02 -07004952#define PORTC_PULSE_DURATION_MASK (3 << 10)
Damien Lespiaub6965192012-12-13 16:08:59 +00004953#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
4954#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4955#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4956#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004957#define PORTB_HOTPLUG_ENABLE (1 << 4)
4958#define PORTB_PULSE_DURATION_2ms (0)
4959#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
4960#define PORTB_PULSE_DURATION_6ms (2 << 2)
4961#define PORTB_PULSE_DURATION_100ms (3 << 2)
Keith Packard7fe0b972011-09-19 13:31:02 -07004962#define PORTB_PULSE_DURATION_MASK (3 << 2)
Damien Lespiaub6965192012-12-13 16:08:59 +00004963#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
4964#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4965#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4966#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004967
4968#define PCH_GPIOA 0xc5010
4969#define PCH_GPIOB 0xc5014
4970#define PCH_GPIOC 0xc5018
4971#define PCH_GPIOD 0xc501c
4972#define PCH_GPIOE 0xc5020
4973#define PCH_GPIOF 0xc5024
4974
Eric Anholtf0217c42009-12-01 11:56:30 -08004975#define PCH_GMBUS0 0xc5100
4976#define PCH_GMBUS1 0xc5104
4977#define PCH_GMBUS2 0xc5108
4978#define PCH_GMBUS3 0xc510c
4979#define PCH_GMBUS4 0xc5110
4980#define PCH_GMBUS5 0xc5120
4981
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004982#define _PCH_DPLL_A 0xc6014
4983#define _PCH_DPLL_B 0xc6018
Daniel Vettere9a632a2013-06-05 13:34:13 +02004984#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004985
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004986#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00004987#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004988#define _PCH_FPA1 0xc6044
4989#define _PCH_FPB0 0xc6048
4990#define _PCH_FPB1 0xc604c
Daniel Vettere9a632a2013-06-05 13:34:13 +02004991#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4992#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08004993
4994#define PCH_DPLL_TEST 0xc606c
4995
4996#define PCH_DREF_CONTROL 0xC6200
4997#define DREF_CONTROL_MASK 0x7fc3
4998#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4999#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
5000#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
5001#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
5002#define DREF_SSC_SOURCE_DISABLE (0<<11)
5003#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08005004#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005005#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
5006#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
5007#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08005008#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005009#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
5010#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08005011#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005012#define DREF_SSC4_DOWNSPREAD (0<<6)
5013#define DREF_SSC4_CENTERSPREAD (1<<6)
5014#define DREF_SSC1_DISABLE (0<<1)
5015#define DREF_SSC1_ENABLE (1<<1)
5016#define DREF_SSC4_DISABLE (0)
5017#define DREF_SSC4_ENABLE (1)
5018
5019#define PCH_RAWCLK_FREQ 0xc6204
5020#define FDL_TP1_TIMER_SHIFT 12
5021#define FDL_TP1_TIMER_MASK (3<<12)
5022#define FDL_TP2_TIMER_SHIFT 10
5023#define FDL_TP2_TIMER_MASK (3<<10)
5024#define RAWCLK_FREQ_MASK 0x3ff
5025
5026#define PCH_DPLL_TMR_CFG 0xc6208
5027
5028#define PCH_SSC4_PARMS 0xc6210
5029#define PCH_SSC4_AUX_PARMS 0xc6214
5030
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005031#define PCH_DPLL_SEL 0xc7000
Daniel Vetter11887392013-06-05 13:34:09 +02005032#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
5033#define TRANS_DPLLA_SEL(pipe) 0
5034#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005035
Zhenyu Wangb9055052009-06-05 15:38:38 +08005036/* transcoder */
5037
Daniel Vetter275f01b22013-05-03 11:49:47 +02005038#define _PCH_TRANS_HTOTAL_A 0xe0000
5039#define TRANS_HTOTAL_SHIFT 16
5040#define TRANS_HACTIVE_SHIFT 0
5041#define _PCH_TRANS_HBLANK_A 0xe0004
5042#define TRANS_HBLANK_END_SHIFT 16
5043#define TRANS_HBLANK_START_SHIFT 0
5044#define _PCH_TRANS_HSYNC_A 0xe0008
5045#define TRANS_HSYNC_END_SHIFT 16
5046#define TRANS_HSYNC_START_SHIFT 0
5047#define _PCH_TRANS_VTOTAL_A 0xe000c
5048#define TRANS_VTOTAL_SHIFT 16
5049#define TRANS_VACTIVE_SHIFT 0
5050#define _PCH_TRANS_VBLANK_A 0xe0010
5051#define TRANS_VBLANK_END_SHIFT 16
5052#define TRANS_VBLANK_START_SHIFT 0
5053#define _PCH_TRANS_VSYNC_A 0xe0014
5054#define TRANS_VSYNC_END_SHIFT 16
5055#define TRANS_VSYNC_START_SHIFT 0
5056#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08005057
Daniel Vettere3b95f12013-05-03 11:49:49 +02005058#define _PCH_TRANSA_DATA_M1 0xe0030
5059#define _PCH_TRANSA_DATA_N1 0xe0034
5060#define _PCH_TRANSA_DATA_M2 0xe0038
5061#define _PCH_TRANSA_DATA_N2 0xe003c
5062#define _PCH_TRANSA_LINK_M1 0xe0040
5063#define _PCH_TRANSA_LINK_N1 0xe0044
5064#define _PCH_TRANSA_LINK_M2 0xe0048
5065#define _PCH_TRANSA_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005066
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005067/* Per-transcoder DIP controls (PCH) */
Jesse Barnesb055c8f2011-07-08 11:31:57 -07005068#define _VIDEO_DIP_CTL_A 0xe0200
5069#define _VIDEO_DIP_DATA_A 0xe0208
5070#define _VIDEO_DIP_GCP_A 0xe0210
5071
5072#define _VIDEO_DIP_CTL_B 0xe1200
5073#define _VIDEO_DIP_DATA_B 0xe1208
5074#define _VIDEO_DIP_GCP_B 0xe1210
5075
5076#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
5077#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
5078#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
5079
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005080/* Per-transcoder DIP controls (VLV) */
Ville Syrjäläb9064872013-01-24 15:29:31 +02005081#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
5082#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
5083#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005084
Ville Syrjäläb9064872013-01-24 15:29:31 +02005085#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
5086#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
5087#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005088
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005089#define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
5090#define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
5091#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
5092
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005093#define VLV_TVIDEO_DIP_CTL(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005094 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
5095 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005096#define VLV_TVIDEO_DIP_DATA(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005097 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
5098 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005099#define VLV_TVIDEO_DIP_GCP(pipe) \
Ville Syrjälä2dcbc342014-04-09 13:29:09 +03005100 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
5101 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
Shobhit Kumar90b107c2012-03-28 13:39:32 -07005102
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03005103/* Haswell DIP controls */
5104#define HSW_VIDEO_DIP_CTL_A 0x60200
5105#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
5106#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
5107#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
5108#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
5109#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
5110#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
5111#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
5112#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
5113#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
5114#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
5115#define HSW_VIDEO_DIP_GCP_A 0x60210
5116
5117#define HSW_VIDEO_DIP_CTL_B 0x61200
5118#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
5119#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
5120#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
5121#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
5122#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
5123#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
5124#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
5125#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
5126#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
5127#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
5128#define HSW_VIDEO_DIP_GCP_B 0x61210
5129
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005130#define HSW_TVIDEO_DIP_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005131 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005132#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005133 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +01005134#define HSW_TVIDEO_DIP_VS_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005135 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005136#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005137 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005138#define HSW_TVIDEO_DIP_GCP(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005139 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -03005140#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005141 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03005142
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03005143#define HSW_STEREO_3D_CTL_A 0x70020
5144#define S3D_ENABLE (1<<31)
5145#define HSW_STEREO_3D_CTL_B 0x71020
5146
5147#define HSW_STEREO_3D_CTL(trans) \
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005148 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03005149
Daniel Vetter275f01b22013-05-03 11:49:47 +02005150#define _PCH_TRANS_HTOTAL_B 0xe1000
5151#define _PCH_TRANS_HBLANK_B 0xe1004
5152#define _PCH_TRANS_HSYNC_B 0xe1008
5153#define _PCH_TRANS_VTOTAL_B 0xe100c
5154#define _PCH_TRANS_VBLANK_B 0xe1010
5155#define _PCH_TRANS_VSYNC_B 0xe1014
5156#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08005157
Daniel Vetter275f01b22013-05-03 11:49:47 +02005158#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
5159#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5160#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5161#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5162#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5163#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5164#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
5165 _PCH_TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01005166
Daniel Vettere3b95f12013-05-03 11:49:49 +02005167#define _PCH_TRANSB_DATA_M1 0xe1030
5168#define _PCH_TRANSB_DATA_N1 0xe1034
5169#define _PCH_TRANSB_DATA_M2 0xe1038
5170#define _PCH_TRANSB_DATA_N2 0xe103c
5171#define _PCH_TRANSB_LINK_M1 0xe1040
5172#define _PCH_TRANSB_LINK_N1 0xe1044
5173#define _PCH_TRANSB_LINK_M2 0xe1048
5174#define _PCH_TRANSB_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08005175
Daniel Vettere3b95f12013-05-03 11:49:49 +02005176#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5177#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5178#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5179#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5180#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5181#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5182#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5183#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005184
Daniel Vetterab9412b2013-05-03 11:49:46 +02005185#define _PCH_TRANSACONF 0xf0008
5186#define _PCH_TRANSBCONF 0xf1008
5187#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5188#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005189#define TRANS_DISABLE (0<<31)
5190#define TRANS_ENABLE (1<<31)
5191#define TRANS_STATE_MASK (1<<30)
5192#define TRANS_STATE_DISABLE (0<<30)
5193#define TRANS_STATE_ENABLE (1<<30)
5194#define TRANS_FSYNC_DELAY_HB1 (0<<27)
5195#define TRANS_FSYNC_DELAY_HB2 (1<<27)
5196#define TRANS_FSYNC_DELAY_HB3 (2<<27)
5197#define TRANS_FSYNC_DELAY_HB4 (3<<27)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02005198#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005199#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02005200#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02005201#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005202#define TRANS_8BPC (0<<5)
5203#define TRANS_10BPC (1<<5)
5204#define TRANS_6BPC (2<<5)
5205#define TRANS_12BPC (3<<5)
5206
Daniel Vetterce401412012-10-31 22:52:30 +01005207#define _TRANSA_CHICKEN1 0xf0060
5208#define _TRANSB_CHICKEN1 0xf1060
5209#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5210#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07005211#define _TRANSA_CHICKEN2 0xf0064
5212#define _TRANSB_CHICKEN2 0xf1064
5213#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
Paulo Zanonidc4bd2d2013-04-08 15:48:08 -03005214#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
5215#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
5216#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
5217#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
5218#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
Jesse Barnes3bcf6032011-07-27 11:51:40 -07005219
Jesse Barnes291427f2011-07-29 12:42:37 -07005220#define SOUTH_CHICKEN1 0xc2000
5221#define FDIA_PHASE_SYNC_SHIFT_OVR 19
5222#define FDIA_PHASE_SYNC_SHIFT_EN 18
Daniel Vetter01a415f2012-10-27 15:58:40 +02005223#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5224#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5225#define FDI_BC_BIFURCATION_SELECT (1 << 12)
Jesse Barnes645c62a2011-05-11 09:49:31 -07005226#define SOUTH_CHICKEN2 0xc2004
Paulo Zanonidde86e22012-12-01 12:04:25 -02005227#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
5228#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
5229#define DPLS_EDP_PPS_FIX_DIS (1<<0)
Jesse Barnes645c62a2011-05-11 09:49:31 -07005230
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005231#define _FDI_RXA_CHICKEN 0xc200c
5232#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08005233#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
5234#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005235#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005236
Jesse Barnes382b0932010-10-07 16:01:25 -07005237#define SOUTH_DSPCLK_GATE_D 0xc2020
Jesse Barnescd664072013-10-02 10:34:19 -07005238#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
Jesse Barnes382b0932010-10-07 16:01:25 -07005239#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
Jesse Barnescd664072013-10-02 10:34:19 -07005240#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
Paulo Zanoni17a303e2012-11-20 15:12:07 -02005241#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
Jesse Barnes382b0932010-10-07 16:01:25 -07005242
Zhenyu Wangb9055052009-06-05 15:38:38 +08005243/* CPU: FDI_TX */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005244#define _FDI_TXA_CTL 0x60100
5245#define _FDI_TXB_CTL 0x61100
5246#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005247#define FDI_TX_DISABLE (0<<31)
5248#define FDI_TX_ENABLE (1<<31)
5249#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
5250#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
5251#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
5252#define FDI_LINK_TRAIN_NONE (3<<28)
5253#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
5254#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
5255#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
5256#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
5257#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
5258#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
5259#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
5260#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005261/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
5262 SNB has different settings. */
5263/* SNB A-stepping */
5264#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5265#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5266#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5267#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5268/* SNB B-stepping */
5269#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
5270#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
5271#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
5272#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
5273#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005274#define FDI_DP_PORT_WIDTH_SHIFT 19
5275#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
5276#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005277#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005278/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08005279#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07005280
5281/* Ivybridge has different bits for lolz */
5282#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
5283#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
5284#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
5285#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
5286
Zhenyu Wangb9055052009-06-05 15:38:38 +08005287/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07005288#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07005289#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005290#define FDI_SCRAMBLING_ENABLE (0<<7)
5291#define FDI_SCRAMBLING_DISABLE (1<<7)
5292
5293/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005294#define _FDI_RXA_CTL 0xf000c
5295#define _FDI_RXB_CTL 0xf100c
5296#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005297#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005298/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07005299#define FDI_FS_ERRC_ENABLE (1<<27)
5300#define FDI_FE_ERRC_ENABLE (1<<26)
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02005301#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005302#define FDI_8BPC (0<<16)
5303#define FDI_10BPC (1<<16)
5304#define FDI_6BPC (2<<16)
5305#define FDI_12BPC (3<<16)
Damien Lespiau3e683202012-12-11 18:48:29 +00005306#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005307#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
5308#define FDI_RX_PLL_ENABLE (1<<13)
5309#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
5310#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
5311#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
5312#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
5313#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01005314#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005315/* CPT */
5316#define FDI_AUTO_TRAINING (1<<10)
5317#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
5318#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
5319#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
5320#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
5321#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005322
Paulo Zanoni04945642012-11-01 21:00:59 -02005323#define _FDI_RXA_MISC 0xf0010
5324#define _FDI_RXB_MISC 0xf1010
5325#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
5326#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
5327#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
5328#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
5329#define FDI_RX_TP1_TO_TP2_48 (2<<20)
5330#define FDI_RX_TP1_TO_TP2_64 (3<<20)
5331#define FDI_RX_FDI_DELAY_90 (0x90<<0)
5332#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
5333
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005334#define _FDI_RXA_TUSIZE1 0xf0030
5335#define _FDI_RXA_TUSIZE2 0xf0038
5336#define _FDI_RXB_TUSIZE1 0xf1030
5337#define _FDI_RXB_TUSIZE2 0xf1038
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005338#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
5339#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005340
5341/* FDI_RX interrupt register format */
5342#define FDI_RX_INTER_LANE_ALIGN (1<<10)
5343#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
5344#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
5345#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
5346#define FDI_RX_FS_CODE_ERR (1<<6)
5347#define FDI_RX_FE_CODE_ERR (1<<5)
5348#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
5349#define FDI_RX_HDCP_LINK_FAIL (1<<3)
5350#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
5351#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
5352#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
5353
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005354#define _FDI_RXA_IIR 0xf0014
5355#define _FDI_RXA_IMR 0xf0018
5356#define _FDI_RXB_IIR 0xf1014
5357#define _FDI_RXB_IMR 0xf1018
5358#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
5359#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005360
5361#define FDI_PLL_CTL_1 0xfe000
5362#define FDI_PLL_CTL_2 0xfe004
5363
Zhenyu Wangb9055052009-06-05 15:38:38 +08005364#define PCH_LVDS 0xe1180
5365#define LVDS_DETECTED (1 << 1)
5366
Shobhit Kumar98364372012-06-15 11:55:14 -07005367/* vlv has 2 sets of panel control regs. */
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005368#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
5369#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
5370#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
Ville Syrjäläad933b52014-08-18 22:15:56 +03005371#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005372#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
5373#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
Shobhit Kumar98364372012-06-15 11:55:14 -07005374
Ville Syrjäläf12c47b2013-01-24 15:29:30 +02005375#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
5376#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
5377#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
5378#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
5379#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
Shobhit Kumar98364372012-06-15 11:55:14 -07005380
Jesse Barnes453c5422013-03-28 09:55:41 -07005381#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
5382#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
5383#define VLV_PIPE_PP_ON_DELAYS(pipe) \
5384 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
5385#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
5386 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
5387#define VLV_PIPE_PP_DIVISOR(pipe) \
5388 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
5389
Zhenyu Wangb9055052009-06-05 15:38:38 +08005390#define PCH_PP_STATUS 0xc7200
5391#define PCH_PP_CONTROL 0xc7204
Jesse Barnes4a655f02010-07-22 13:18:18 -07005392#define PANEL_UNLOCK_REGS (0xabcd << 16)
Keith Packard1c0ae802011-09-19 13:59:29 -07005393#define PANEL_UNLOCK_MASK (0xffff << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08005394#define EDP_FORCE_VDD (1 << 3)
5395#define EDP_BLC_ENABLE (1 << 2)
5396#define PANEL_POWER_RESET (1 << 1)
5397#define PANEL_POWER_OFF (0 << 0)
5398#define PANEL_POWER_ON (1 << 0)
5399#define PCH_PP_ON_DELAYS 0xc7208
Keith Packardf01eca22011-09-28 16:48:10 -07005400#define PANEL_PORT_SELECT_MASK (3 << 30)
5401#define PANEL_PORT_SELECT_LVDS (0 << 30)
5402#define PANEL_PORT_SELECT_DPA (1 << 30)
Keith Packardf01eca22011-09-28 16:48:10 -07005403#define PANEL_PORT_SELECT_DPC (2 << 30)
5404#define PANEL_PORT_SELECT_DPD (3 << 30)
5405#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
5406#define PANEL_POWER_UP_DELAY_SHIFT 16
5407#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
5408#define PANEL_LIGHT_ON_DELAY_SHIFT 0
5409
Zhenyu Wangb9055052009-06-05 15:38:38 +08005410#define PCH_PP_OFF_DELAYS 0xc720c
Keith Packardf01eca22011-09-28 16:48:10 -07005411#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
5412#define PANEL_POWER_DOWN_DELAY_SHIFT 16
5413#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
5414#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
5415
Zhenyu Wangb9055052009-06-05 15:38:38 +08005416#define PCH_PP_DIVISOR 0xc7210
Keith Packardf01eca22011-09-28 16:48:10 -07005417#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
5418#define PP_REFERENCE_DIVIDER_SHIFT 8
5419#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
5420#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08005421
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005422#define PCH_DP_B 0xe4100
5423#define PCH_DPB_AUX_CH_CTL 0xe4110
5424#define PCH_DPB_AUX_CH_DATA1 0xe4114
5425#define PCH_DPB_AUX_CH_DATA2 0xe4118
5426#define PCH_DPB_AUX_CH_DATA3 0xe411c
5427#define PCH_DPB_AUX_CH_DATA4 0xe4120
5428#define PCH_DPB_AUX_CH_DATA5 0xe4124
5429
5430#define PCH_DP_C 0xe4200
5431#define PCH_DPC_AUX_CH_CTL 0xe4210
5432#define PCH_DPC_AUX_CH_DATA1 0xe4214
5433#define PCH_DPC_AUX_CH_DATA2 0xe4218
5434#define PCH_DPC_AUX_CH_DATA3 0xe421c
5435#define PCH_DPC_AUX_CH_DATA4 0xe4220
5436#define PCH_DPC_AUX_CH_DATA5 0xe4224
5437
5438#define PCH_DP_D 0xe4300
5439#define PCH_DPD_AUX_CH_CTL 0xe4310
5440#define PCH_DPD_AUX_CH_DATA1 0xe4314
5441#define PCH_DPD_AUX_CH_DATA2 0xe4318
5442#define PCH_DPD_AUX_CH_DATA3 0xe431c
5443#define PCH_DPD_AUX_CH_DATA4 0xe4320
5444#define PCH_DPD_AUX_CH_DATA5 0xe4324
5445
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005446/* CPT */
5447#define PORT_TRANS_A_SEL_CPT 0
5448#define PORT_TRANS_B_SEL_CPT (1<<29)
5449#define PORT_TRANS_C_SEL_CPT (2<<29)
5450#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07005451#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Daniel Vetter19d8fe12012-07-02 13:26:27 +02005452#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
5453#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
Ville Syrjälä71485e02014-04-09 13:28:55 +03005454#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
5455#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005456
5457#define TRANS_DP_CTL_A 0xe0300
5458#define TRANS_DP_CTL_B 0xe1300
5459#define TRANS_DP_CTL_C 0xe2300
Daniel Vetter23670b322012-11-01 09:15:30 +01005460#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005461#define TRANS_DP_OUTPUT_ENABLE (1<<31)
5462#define TRANS_DP_PORT_SEL_B (0<<29)
5463#define TRANS_DP_PORT_SEL_C (1<<29)
5464#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08005465#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005466#define TRANS_DP_PORT_SEL_MASK (3<<29)
5467#define TRANS_DP_AUDIO_ONLY (1<<26)
5468#define TRANS_DP_ENH_FRAMING (1<<18)
5469#define TRANS_DP_8BPC (0<<9)
5470#define TRANS_DP_10BPC (1<<9)
5471#define TRANS_DP_6BPC (2<<9)
5472#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08005473#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005474#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
5475#define TRANS_DP_VSYNC_ACTIVE_LOW 0
5476#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
5477#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01005478#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005479
5480/* SNB eDP training params */
5481/* SNB A-stepping */
5482#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
5483#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
5484#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
5485#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
5486/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08005487#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
5488#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
5489#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
5490#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
5491#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005492#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
5493
Keith Packard1a2eb462011-11-16 16:26:07 -08005494/* IVB */
5495#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
5496#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
5497#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
5498#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
5499#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
5500#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
Imre Deak77fa4cb2013-08-23 23:50:23 +03005501#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
Keith Packard1a2eb462011-11-16 16:26:07 -08005502
5503/* legacy values */
5504#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
5505#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
5506#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
5507#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
5508#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
5509
5510#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
5511
Imre Deak9e72b462014-05-05 15:13:55 +03005512#define VLV_PMWGICZ 0x1300a4
5513
Zou Nan haicae58522010-11-09 17:17:32 +08005514#define FORCEWAKE 0xA18C
Jesse Barnes575155a2012-03-28 13:39:37 -07005515#define FORCEWAKE_VLV 0x1300b0
5516#define FORCEWAKE_ACK_VLV 0x1300b4
Jesse Barnesed5de392013-03-08 10:45:57 -08005517#define FORCEWAKE_MEDIA_VLV 0x1300b8
5518#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
Eugeni Dodonove7911c42012-07-02 11:51:04 -03005519#define FORCEWAKE_ACK_HSW 0x130044
Chris Wilsoneb43f4a2010-12-08 17:32:24 +00005520#define FORCEWAKE_ACK 0x130090
Jesse Barnesd62b4892013-03-08 10:45:53 -08005521#define VLV_GTLC_WAKE_CTRL 0x130090
Imre Deak981a5ae2014-04-14 20:24:22 +03005522#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
5523#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
5524#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
5525
Jesse Barnesd62b4892013-03-08 10:45:53 -08005526#define VLV_GTLC_PW_STATUS 0x130094
Imre Deak981a5ae2014-04-14 20:24:22 +03005527#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
5528#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
5529#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
5530#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
Keith Packard8d715f02011-11-18 20:39:01 -08005531#define FORCEWAKE_MT 0xa188 /* multi-threaded */
Chris Wilsonc5836c22012-10-17 12:09:55 +01005532#define FORCEWAKE_KERNEL 0x1
5533#define FORCEWAKE_USER 0x2
Keith Packard8d715f02011-11-18 20:39:01 -08005534#define FORCEWAKE_MT_ACK 0x130040
5535#define ECOBUS 0xa180
5536#define FORCEWAKE_MT_ENABLE (1<<5)
Imre Deak9e72b462014-05-05 15:13:55 +03005537#define VLV_SPAREG2H 0xA194
Chris Wilson8fd26852010-12-08 18:40:43 +00005538
Ben Widawskydd202c62012-02-09 10:15:18 +01005539#define GTFIFODBG 0x120000
Ville Syrjälä90f256b2013-11-14 01:59:59 +02005540#define GT_FIFO_SBDROPERR (1<<6)
5541#define GT_FIFO_BLOBDROPERR (1<<5)
5542#define GT_FIFO_SB_READ_ABORTERR (1<<4)
5543#define GT_FIFO_DROPERR (1<<3)
Ben Widawskydd202c62012-02-09 10:15:18 +01005544#define GT_FIFO_OVFERR (1<<2)
5545#define GT_FIFO_IAWRERR (1<<1)
5546#define GT_FIFO_IARDERR (1<<0)
5547
Ville Syrjälä46520e22013-11-14 02:00:00 +02005548#define GTFIFOCTL 0x120008
5549#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
Chris Wilson957367202011-05-12 22:17:09 +01005550#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Chris Wilson91355832011-03-04 19:22:40 +00005551
Ben Widawsky05e21cc2013-07-04 11:02:04 -07005552#define HSW_IDICR 0x9008
5553#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
5554#define HSW_EDRAM_PRESENT 0x120010
5555
Daniel Vetter80e829f2012-03-31 11:21:57 +02005556#define GEN6_UCGCTL1 0x9400
Ville Syrjäläe4443e42014-04-09 13:28:41 +03005557# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
Daniel Vetter80e829f2012-03-31 11:21:57 +02005558# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Daniel Vetterde4a8bd2012-04-11 20:42:38 +02005559# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
Daniel Vetter80e829f2012-03-31 11:21:57 +02005560
Eric Anholt406478d2011-11-07 16:07:04 -08005561#define GEN6_UCGCTL2 0x9404
Jesse Barnes0f846f82012-06-14 11:04:47 -07005562# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
Jesse Barnes6edaa7f2012-06-14 11:04:49 -07005563# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08005564# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08005565# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08005566# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08005567
Imre Deak9e72b462014-05-05 15:13:55 +03005568#define GEN6_UCGCTL3 0x9408
5569
Jesse Barnese3f33d42012-06-14 11:04:50 -07005570#define GEN7_UCGCTL4 0x940c
5571#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
5572
Imre Deak9e72b462014-05-05 15:13:55 +03005573#define GEN6_RCGCTL1 0x9410
5574#define GEN6_RCGCTL2 0x9414
5575#define GEN6_RSTCTL 0x9420
5576
Ville Syrjälä4f1ca9e2014-02-27 21:59:02 +02005577#define GEN8_UCGCTL6 0x9430
5578#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
5579
Daisy Sunc76bb612014-08-11 11:08:38 -07005580#define TIMESTAMP_CTR 0x44070
5581#define FREQ_1_28_US(us) (((us) * 100) >> 7)
5582#define MCHBAR_PCU_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5960)
5583
Imre Deak9e72b462014-05-05 15:13:55 +03005584#define GEN6_GFXPAUSE 0xA000
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08005585#define GEN6_RPNSWREQ 0xA008
Chris Wilson8fd26852010-12-08 18:40:43 +00005586#define GEN6_TURBO_DISABLE (1<<31)
5587#define GEN6_FREQUENCY(x) ((x)<<25)
Rodrigo Vivi92bd1bf2013-03-25 17:55:49 -03005588#define HSW_FREQUENCY(x) ((x)<<24)
Chris Wilson8fd26852010-12-08 18:40:43 +00005589#define GEN6_OFFSET(x) ((x)<<19)
5590#define GEN6_AGGRESSIVE_TURBO (0<<15)
5591#define GEN6_RC_VIDEO_FREQ 0xA00C
5592#define GEN6_RC_CONTROL 0xA090
5593#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
5594#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
5595#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
5596#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
5597#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
Jesse Barnes6b88f292013-11-15 09:32:12 -08005598#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
Jesse Barnes0a073b82013-04-17 15:54:58 -07005599#define GEN7_RC_CTL_TO_MODE (1<<28)
Chris Wilson8fd26852010-12-08 18:40:43 +00005600#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
5601#define GEN6_RC_CTL_HW_ENABLE (1<<31)
5602#define GEN6_RP_DOWN_TIMEOUT 0xA010
5603#define GEN6_RP_INTERRUPT_LIMITS 0xA014
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08005604#define GEN6_RPSTAT1 0xA01C
Jesse Barnesccab5c82011-01-18 15:49:25 -08005605#define GEN6_CAGF_SHIFT 8
Ben Widawskyf82855d2013-01-29 12:00:15 -08005606#define HSW_CAGF_SHIFT 7
Jesse Barnesccab5c82011-01-18 15:49:25 -08005607#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Ben Widawskyf82855d2013-01-29 12:00:15 -08005608#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
Chris Wilson8fd26852010-12-08 18:40:43 +00005609#define GEN6_RP_CONTROL 0xA024
5610#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08005611#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
5612#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
5613#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
5614#define GEN6_RP_MEDIA_HW_MODE (1<<9)
5615#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00005616#define GEN6_RP_MEDIA_IS_GFX (1<<8)
5617#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08005618#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
5619#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
5620#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
Chris Wilsondd75fdc2013-09-25 17:34:57 +01005621#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
Jesse Barnesccab5c82011-01-18 15:49:25 -08005622#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Chris Wilson8fd26852010-12-08 18:40:43 +00005623#define GEN6_RP_UP_THRESHOLD 0xA02C
5624#define GEN6_RP_DOWN_THRESHOLD 0xA030
Jesse Barnesccab5c82011-01-18 15:49:25 -08005625#define GEN6_RP_CUR_UP_EI 0xA050
5626#define GEN6_CURICONT_MASK 0xffffff
5627#define GEN6_RP_CUR_UP 0xA054
5628#define GEN6_CURBSYTAVG_MASK 0xffffff
5629#define GEN6_RP_PREV_UP 0xA058
5630#define GEN6_RP_CUR_DOWN_EI 0xA05C
5631#define GEN6_CURIAVG_MASK 0xffffff
5632#define GEN6_RP_CUR_DOWN 0xA060
5633#define GEN6_RP_PREV_DOWN 0xA064
Chris Wilson8fd26852010-12-08 18:40:43 +00005634#define GEN6_RP_UP_EI 0xA068
5635#define GEN6_RP_DOWN_EI 0xA06C
5636#define GEN6_RP_IDLE_HYSTERSIS 0xA070
Imre Deak9e72b462014-05-05 15:13:55 +03005637#define GEN6_RPDEUHWTC 0xA080
5638#define GEN6_RPDEUC 0xA084
5639#define GEN6_RPDEUCSW 0xA088
Chris Wilson8fd26852010-12-08 18:40:43 +00005640#define GEN6_RC_STATE 0xA094
5641#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
5642#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
5643#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
5644#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
5645#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
5646#define GEN6_RC_SLEEP 0xA0B0
Imre Deak9e72b462014-05-05 15:13:55 +03005647#define GEN6_RCUBMABDTMR 0xA0B0
Chris Wilson8fd26852010-12-08 18:40:43 +00005648#define GEN6_RC1e_THRESHOLD 0xA0B4
5649#define GEN6_RC6_THRESHOLD 0xA0B8
5650#define GEN6_RC6p_THRESHOLD 0xA0BC
Imre Deak9e72b462014-05-05 15:13:55 +03005651#define VLV_RCEDATA 0xA0BC
Chris Wilson8fd26852010-12-08 18:40:43 +00005652#define GEN6_RC6pp_THRESHOLD 0xA0C0
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08005653#define GEN6_PMINTRMSK 0xA168
Deepak Sbaccd452014-05-15 20:58:09 +03005654#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
Imre Deak9e72b462014-05-05 15:13:55 +03005655#define VLV_PWRDWNUPCTL 0xA294
Chris Wilson8fd26852010-12-08 18:40:43 +00005656
5657#define GEN6_PMISR 0x44020
Ben Widawsky4912d042011-04-25 11:25:20 -07005658#define GEN6_PMIMR 0x44024 /* rps_lock */
Chris Wilson8fd26852010-12-08 18:40:43 +00005659#define GEN6_PMIIR 0x44028
5660#define GEN6_PMIER 0x4402C
5661#define GEN6_PM_MBOX_EVENT (1<<25)
5662#define GEN6_PM_THERMAL_EVENT (1<<24)
5663#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
5664#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
5665#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
5666#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
5667#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky48484052013-05-28 19:22:27 -07005668#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
Ben Widawsky4912d042011-04-25 11:25:20 -07005669 GEN6_PM_RP_DOWN_THRESHOLD | \
5670 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00005671
Imre Deak9e72b462014-05-05 15:13:55 +03005672#define GEN7_GT_SCRATCH_BASE 0x4F100
5673#define GEN7_GT_SCRATCH_REG_NUM 8
5674
Deepak S76c3552f2014-01-30 23:08:16 +05305675#define VLV_GTLC_SURVIVABILITY_REG 0x130098
5676#define VLV_GFX_CLK_STATUS_BIT (1<<3)
5677#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
5678
Ben Widawskycce66a22012-03-27 18:59:38 -07005679#define GEN6_GT_GFX_RC6_LOCKED 0x138104
Jesse Barnes49798eb2013-09-26 17:55:57 -07005680#define VLV_COUNTER_CONTROL 0x138104
5681#define VLV_COUNT_RANGE_HIGH (1<<15)
Deepak S31685c22014-07-03 17:33:01 -04005682#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
5683#define VLV_RENDER_RC0_COUNT_EN (1<<4)
Jesse Barnes49798eb2013-09-26 17:55:57 -07005684#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
5685#define VLV_RENDER_RC6_COUNT_EN (1<<0)
Ben Widawskycce66a22012-03-27 18:59:38 -07005686#define GEN6_GT_GFX_RC6 0x138108
Imre Deak9cc19be2014-04-14 20:24:24 +03005687#define VLV_GT_RENDER_RC6 0x138108
5688#define VLV_GT_MEDIA_RC6 0x13810C
5689
Ben Widawskycce66a22012-03-27 18:59:38 -07005690#define GEN6_GT_GFX_RC6p 0x13810C
5691#define GEN6_GT_GFX_RC6pp 0x138110
Deepak S31685c22014-07-03 17:33:01 -04005692#define VLV_RENDER_C0_COUNT_REG 0x138118
5693#define VLV_MEDIA_C0_COUNT_REG 0x13811C
Ben Widawskycce66a22012-03-27 18:59:38 -07005694
Chris Wilson8fd26852010-12-08 18:40:43 +00005695#define GEN6_PCODE_MAILBOX 0x138124
5696#define GEN6_PCODE_READY (1<<31)
Jesse Barnesa6044e22010-12-20 11:34:20 -08005697#define GEN6_READ_OC_PARAMS 0xc
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07005698#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
5699#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
Ben Widawsky31643d52012-09-26 10:34:01 -07005700#define GEN6_PCODE_WRITE_RC6VIDS 0x4
5701#define GEN6_PCODE_READ_RC6VIDS 0x5
Paulo Zanoni515b2392013-09-10 19:36:37 -03005702#define GEN6_PCODE_READ_D_COMP 0x10
5703#define GEN6_PCODE_WRITE_D_COMP 0x11
Ben Widawsky7083e052013-02-01 16:41:14 -08005704#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5705#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
Ben Widawsky2a114cc2013-11-02 21:07:47 -07005706#define DISPLAY_IPS_CONTROL 0x19
Chris Wilson8fd26852010-12-08 18:40:43 +00005707#define GEN6_PCODE_DATA 0x138128
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07005708#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson3ebecd02013-04-12 19:10:13 +01005709#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
Chris Wilson8fd26852010-12-08 18:40:43 +00005710
Ben Widawsky4d855292011-12-12 19:34:16 -08005711#define GEN6_GT_CORE_STATUS 0x138060
5712#define GEN6_CORE_CPD_STATE_MASK (7<<4)
5713#define GEN6_RCn_MASK 7
5714#define GEN6_RC0 0
5715#define GEN6_RC3 2
5716#define GEN6_RC6 3
5717#define GEN6_RC7 4
5718
Ben Widawskye3689192012-05-25 16:56:22 -07005719#define GEN7_MISCCPCTL (0x9424)
5720#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
5721
5722/* IVYBRIDGE DPF */
5723#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07005724#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
Ben Widawskye3689192012-05-25 16:56:22 -07005725#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
5726#define GEN7_PARITY_ERROR_VALID (1<<13)
5727#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
5728#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
5729#define GEN7_PARITY_ERROR_ROW(reg) \
5730 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
5731#define GEN7_PARITY_ERROR_BANK(reg) \
5732 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
5733#define GEN7_PARITY_ERROR_SUBBANK(reg) \
5734 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
5735#define GEN7_L3CDERRST1_ENABLE (1<<7)
5736
Ben Widawskyb9524a12012-05-25 16:56:24 -07005737#define GEN7_L3LOG_BASE 0xB070
Ben Widawsky35a85ac2013-09-19 11:13:41 -07005738#define HSW_L3LOG_BASE_SLICE1 0xB270
Ben Widawskyb9524a12012-05-25 16:56:24 -07005739#define GEN7_L3LOG_SIZE 0x80
5740
Jesse Barnes12f33822012-10-25 12:15:45 -07005741#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
5742#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
5743#define GEN7_MAX_PS_THREAD_DEP (8<<12)
Ben Widawsky4c2e7a52013-11-02 21:08:00 -07005744#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
Jesse Barnes12f33822012-10-25 12:15:45 -07005745#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
5746
Kenneth Graunkec8966e12014-02-26 23:59:30 -08005747#define GEN8_ROW_CHICKEN 0xe4f0
5748#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
Kenneth Graunke1411e6a2014-02-26 23:59:31 -08005749#define STALL_DOP_GATING_DISABLE (1<<5)
Kenneth Graunkec8966e12014-02-26 23:59:30 -08005750
Jesse Barnes8ab43972012-10-25 12:15:42 -07005751#define GEN7_ROW_CHICKEN2 0xe4f4
5752#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
5753#define DOP_CLOCK_GATING_DISABLE (1<<0)
5754
Francisco Jerezf3fc4882013-10-02 15:53:16 -07005755#define HSW_ROW_CHICKEN3 0xe49c
5756#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
5757
Ben Widawskyfd392b62013-11-04 22:52:39 -08005758#define HALF_SLICE_CHICKEN3 0xe184
5759#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
Ben Widawskybf663472013-11-02 21:07:57 -07005760#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
Ben Widawskyfd392b62013-11-04 22:52:39 -08005761
Damien Lespiau5c969aa2014-02-07 19:12:48 +00005762#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
Wu Fengguange0dac652011-09-05 14:25:34 +08005763#define INTEL_AUDIO_DEVCL 0x808629FB
5764#define INTEL_AUDIO_DEVBLC 0x80862801
5765#define INTEL_AUDIO_DEVCTG 0x80862802
5766
5767#define G4X_AUD_CNTL_ST 0x620B4
5768#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
5769#define G4X_ELDV_DEVCTG (1 << 14)
5770#define G4X_ELD_ADDR (0xf << 5)
5771#define G4X_ELD_ACK (1 << 4)
5772#define G4X_HDMIW_HDMIEDID 0x6210C
5773
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005774#define IBX_HDMIW_HDMIEDID_A 0xE2050
Wang Xingchao9b138a82012-08-09 16:52:18 +08005775#define IBX_HDMIW_HDMIEDID_B 0xE2150
5776#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5777 IBX_HDMIW_HDMIEDID_A, \
5778 IBX_HDMIW_HDMIEDID_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005779#define IBX_AUD_CNTL_ST_A 0xE20B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08005780#define IBX_AUD_CNTL_ST_B 0xE21B4
5781#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5782 IBX_AUD_CNTL_ST_A, \
5783 IBX_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005784#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
5785#define IBX_ELD_ADDRESS (0x1f << 5)
5786#define IBX_ELD_ACK (1 << 4)
5787#define IBX_AUD_CNTL_ST2 0xE20C0
5788#define IBX_ELD_VALIDB (1 << 0)
5789#define IBX_CP_READYB (1 << 1)
Wu Fengguange0dac652011-09-05 14:25:34 +08005790
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005791#define CPT_HDMIW_HDMIEDID_A 0xE5050
Wang Xingchao9b138a82012-08-09 16:52:18 +08005792#define CPT_HDMIW_HDMIEDID_B 0xE5150
5793#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5794 CPT_HDMIW_HDMIEDID_A, \
5795 CPT_HDMIW_HDMIEDID_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005796#define CPT_AUD_CNTL_ST_A 0xE50B4
Wang Xingchao9b138a82012-08-09 16:52:18 +08005797#define CPT_AUD_CNTL_ST_B 0xE51B4
5798#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5799 CPT_AUD_CNTL_ST_A, \
5800 CPT_AUD_CNTL_ST_B)
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005801#define CPT_AUD_CNTRL_ST2 0xE50C0
Wu Fengguange0dac652011-09-05 14:25:34 +08005802
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04005803#define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
5804#define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
5805#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5806 VLV_HDMIW_HDMIEDID_A, \
5807 VLV_HDMIW_HDMIEDID_B)
5808#define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
5809#define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
5810#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5811 VLV_AUD_CNTL_ST_A, \
5812 VLV_AUD_CNTL_ST_B)
5813#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
5814
Eric Anholtae662d32012-01-03 09:23:29 -08005815/* These are the 4 32-bit write offset registers for each stream
5816 * output buffer. It determines the offset from the
5817 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5818 */
5819#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
5820
Wu Fengguangb6daa022012-01-06 14:41:31 -06005821#define IBX_AUD_CONFIG_A 0xe2000
Wang Xingchao9b138a82012-08-09 16:52:18 +08005822#define IBX_AUD_CONFIG_B 0xe2100
5823#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5824 IBX_AUD_CONFIG_A, \
5825 IBX_AUD_CONFIG_B)
Wu Fengguangb6daa022012-01-06 14:41:31 -06005826#define CPT_AUD_CONFIG_A 0xe5000
Wang Xingchao9b138a82012-08-09 16:52:18 +08005827#define CPT_AUD_CONFIG_B 0xe5100
5828#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5829 CPT_AUD_CONFIG_A, \
5830 CPT_AUD_CONFIG_B)
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04005831#define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
5832#define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
5833#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5834 VLV_AUD_CONFIG_A, \
5835 VLV_AUD_CONFIG_B)
5836
Wu Fengguangb6daa022012-01-06 14:41:31 -06005837#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
5838#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
5839#define AUD_CONFIG_UPPER_N_SHIFT 20
5840#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
5841#define AUD_CONFIG_LOWER_N_SHIFT 4
5842#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
5843#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
Jani Nikula1a915102013-10-16 12:34:48 +03005844#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
5845#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
5846#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
5847#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
5848#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
5849#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
5850#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
5851#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
5852#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
5853#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
5854#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
Wu Fengguangb6daa022012-01-06 14:41:31 -06005855#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
5856
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08005857/* HSW Audio */
5858#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
5859#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
5860#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5861 HSW_AUD_CONFIG_A, \
5862 HSW_AUD_CONFIG_B)
5863
5864#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
5865#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
5866#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5867 HSW_AUD_MISC_CTRL_A, \
5868 HSW_AUD_MISC_CTRL_B)
5869
5870#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
5871#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
5872#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5873 HSW_AUD_DIP_ELD_CTRL_ST_A, \
5874 HSW_AUD_DIP_ELD_CTRL_ST_B)
5875
5876/* Audio Digital Converter */
5877#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
5878#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
5879#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5880 HSW_AUD_DIG_CNVT_1, \
5881 HSW_AUD_DIG_CNVT_2)
Wang Xingchao9b138a82012-08-09 16:52:18 +08005882#define DIP_PORT_SEL_MASK 0x3
Wang Xingchao9a78b6c2012-08-09 16:52:15 +08005883
5884#define HSW_AUD_EDID_DATA_A 0x65050
5885#define HSW_AUD_EDID_DATA_B 0x65150
5886#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5887 HSW_AUD_EDID_DATA_A, \
5888 HSW_AUD_EDID_DATA_B)
5889
5890#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
5891#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
5892#define AUDIO_INACTIVE_C (1<<11)
5893#define AUDIO_INACTIVE_B (1<<7)
5894#define AUDIO_INACTIVE_A (1<<3)
5895#define AUDIO_OUTPUT_ENABLE_A (1<<2)
5896#define AUDIO_OUTPUT_ENABLE_B (1<<6)
5897#define AUDIO_OUTPUT_ENABLE_C (1<<10)
5898#define AUDIO_ELD_VALID_A (1<<0)
5899#define AUDIO_ELD_VALID_B (1<<4)
5900#define AUDIO_ELD_VALID_C (1<<8)
5901#define AUDIO_CP_READY_A (1<<1)
5902#define AUDIO_CP_READY_B (1<<5)
5903#define AUDIO_CP_READY_C (1<<9)
5904
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005905/* HSW Power Wells */
Paulo Zanonifa42e232013-01-25 16:59:11 -02005906#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
5907#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
5908#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
5909#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -03005910#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
5911#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005912#define HSW_PWR_WELL_CTL5 0x45410
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005913#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
5914#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005915#define HSW_PWR_WELL_FORCE_ON (1<<19)
5916#define HSW_PWR_WELL_CTL6 0x45414
Eugeni Dodonov9eb3a752012-03-29 12:32:21 -03005917
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005918/* Per-pipe DDI Function Control */
Paulo Zanoniad80a812012-10-24 16:06:19 -02005919#define TRANS_DDI_FUNC_CTL_A 0x60400
5920#define TRANS_DDI_FUNC_CTL_B 0x61400
5921#define TRANS_DDI_FUNC_CTL_C 0x62400
5922#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
Antti Koskipaaa57c7742014-02-04 14:22:24 +02005923#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
5924
Paulo Zanoniad80a812012-10-24 16:06:19 -02005925#define TRANS_DDI_FUNC_ENABLE (1<<31)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005926/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
Paulo Zanoniad80a812012-10-24 16:06:19 -02005927#define TRANS_DDI_PORT_MASK (7<<28)
Daniel Vetter26804af2014-06-25 22:01:55 +03005928#define TRANS_DDI_PORT_SHIFT 28
Paulo Zanoniad80a812012-10-24 16:06:19 -02005929#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
5930#define TRANS_DDI_PORT_NONE (0<<28)
5931#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
5932#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
5933#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
5934#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
5935#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
5936#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
5937#define TRANS_DDI_BPC_MASK (7<<20)
5938#define TRANS_DDI_BPC_8 (0<<20)
5939#define TRANS_DDI_BPC_10 (1<<20)
5940#define TRANS_DDI_BPC_6 (2<<20)
5941#define TRANS_DDI_BPC_12 (3<<20)
5942#define TRANS_DDI_PVSYNC (1<<17)
5943#define TRANS_DDI_PHSYNC (1<<16)
5944#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
5945#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
5946#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5947#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5948#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
Dave Airlie01b887c2014-05-02 11:17:41 +10005949#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
Paulo Zanoniad80a812012-10-24 16:06:19 -02005950#define TRANS_DDI_BFI_ENABLE (1<<4)
Eugeni Dodonove7e104c2012-03-29 12:32:23 -03005951
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005952/* DisplayPort Transport Control */
5953#define DP_TP_CTL_A 0x64040
5954#define DP_TP_CTL_B 0x64140
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005955#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
5956#define DP_TP_CTL_ENABLE (1<<31)
5957#define DP_TP_CTL_MODE_SST (0<<27)
5958#define DP_TP_CTL_MODE_MST (1<<27)
Dave Airlie01b887c2014-05-02 11:17:41 +10005959#define DP_TP_CTL_FORCE_ACT (1<<25)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005960#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005961#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005962#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
5963#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
5964#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005965#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
5966#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005967#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Paulo Zanonid6c0d722012-10-15 15:51:34 -03005968#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
Eugeni Dodonov0e87f662012-03-29 12:32:24 -03005969
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03005970/* DisplayPort Transport Status */
5971#define DP_TP_STATUS_A 0x64044
5972#define DP_TP_STATUS_B 0x64144
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005973#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
Dave Airlie01b887c2014-05-02 11:17:41 +10005974#define DP_TP_STATUS_IDLE_DONE (1<<25)
5975#define DP_TP_STATUS_ACT_SENT (1<<24)
5976#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
5977#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5978#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
5979#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
5980#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
Eugeni Dodonove411b2c2012-03-29 12:32:25 -03005981
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005982/* DDI Buffer Control */
5983#define DDI_BUF_CTL_A 0x64000
5984#define DDI_BUF_CTL_B 0x64100
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005985#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5986#define DDI_BUF_CTL_ENABLE (1<<31)
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05305987#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005988#define DDI_BUF_EMP_MASK (0xf<<24)
Damien Lespiau876a8cd2012-12-11 18:48:30 +00005989#define DDI_BUF_PORT_REVERSAL (1<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005990#define DDI_BUF_IS_IDLE (1<<7)
Paulo Zanoni79935fc2012-11-20 13:27:40 -02005991#define DDI_A_4_LANES (1<<4)
Daniel Vetter17aa6be2013-04-30 14:01:40 +02005992#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
Eugeni Dodonov03f896a2012-03-29 12:32:26 -03005993#define DDI_INIT_DISPLAY_DETECTED (1<<0)
5994
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03005995/* DDI Buffer Translations */
5996#define DDI_BUF_TRANS_A 0x64E00
5997#define DDI_BUF_TRANS_B 0x64E60
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03005998#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
Eugeni Dodonovbb879a42012-03-29 12:32:27 -03005999
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03006000/* Sideband Interface (SBI) is programmed indirectly, via
6001 * SBI_ADDR, which contains the register offset; and SBI_DATA,
6002 * which contains the payload */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006003#define SBI_ADDR 0xC6000
6004#define SBI_DATA 0xC6004
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03006005#define SBI_CTL_STAT 0xC6008
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02006006#define SBI_CTL_DEST_ICLK (0x0<<16)
6007#define SBI_CTL_DEST_MPHY (0x1<<16)
6008#define SBI_CTL_OP_IORD (0x2<<8)
6009#define SBI_CTL_OP_IOWR (0x3<<8)
Eugeni Dodonov7501a4d2012-03-29 12:32:29 -03006010#define SBI_CTL_OP_CRRD (0x6<<8)
6011#define SBI_CTL_OP_CRWR (0x7<<8)
6012#define SBI_RESPONSE_FAIL (0x1<<1)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006013#define SBI_RESPONSE_SUCCESS (0x0<<1)
6014#define SBI_BUSY (0x1<<0)
6015#define SBI_READY (0x0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03006016
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006017/* SBI offsets */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006018#define SBI_SSCDIVINTPHASE6 0x0600
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006019#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
6020#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
6021#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
6022#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006023#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006024#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006025#define SBI_SSCCTL 0x020c
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006026#define SBI_SSCCTL6 0x060C
Paulo Zanonidde86e22012-12-01 12:04:25 -02006027#define SBI_SSCCTL_PATHALT (1<<3)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006028#define SBI_SSCCTL_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006029#define SBI_SSCAUXDIV6 0x0610
6030#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006031#define SBI_DBUFF0 0x2a00
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006032#define SBI_GEN0 0x1f00
6033#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
Eugeni Dodonovccf1c862012-03-29 12:32:34 -03006034
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03006035/* LPT PIXCLK_GATE */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006036#define PIXCLK_GATE 0xC6020
Paulo Zanoni745ca3b2012-08-08 14:15:32 -03006037#define PIXCLK_GATE_UNGATE (1<<0)
6038#define PIXCLK_GATE_GATE (0<<0)
Eugeni Dodonov52f025e2012-03-29 12:32:31 -03006039
Eugeni Dodonove93ea062012-03-29 12:32:32 -03006040/* SPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006041#define SPLL_CTL 0x46020
Eugeni Dodonove93ea062012-03-29 12:32:32 -03006042#define SPLL_PLL_ENABLE (1<<31)
Damien Lespiau39bc66c2012-10-11 15:24:04 +01006043#define SPLL_PLL_SSC (1<<28)
6044#define SPLL_PLL_NON_SSC (2<<28)
Jesse Barnes11578552014-01-21 12:42:10 -08006045#define SPLL_PLL_LCPLL (3<<28)
6046#define SPLL_PLL_REF_MASK (3<<28)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006047#define SPLL_PLL_FREQ_810MHz (0<<26)
6048#define SPLL_PLL_FREQ_1350MHz (1<<26)
Jesse Barnes11578552014-01-21 12:42:10 -08006049#define SPLL_PLL_FREQ_2700MHz (2<<26)
6050#define SPLL_PLL_FREQ_MASK (3<<26)
Eugeni Dodonove93ea062012-03-29 12:32:32 -03006051
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03006052/* WRPLL */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006053#define WRPLL_CTL1 0x46040
6054#define WRPLL_CTL2 0x46060
Daniel Vetterd452c5b2014-07-04 11:27:39 -03006055#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006056#define WRPLL_PLL_ENABLE (1<<31)
Daniel Vetter114fe482014-06-25 22:01:48 +03006057#define WRPLL_PLL_SSC (1<<28)
6058#define WRPLL_PLL_NON_SSC (2<<28)
6059#define WRPLL_PLL_LCPLL (3<<28)
6060#define WRPLL_PLL_REF_MASK (3<<28)
Eugeni Dodonovef4d0842012-04-13 17:08:38 -03006061/* WRPLL divider programming */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006062#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
Jesse Barnes11578552014-01-21 12:42:10 -08006063#define WRPLL_DIVIDER_REF_MASK (0xff)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006064#define WRPLL_DIVIDER_POST(x) ((x)<<8)
Jesse Barnes11578552014-01-21 12:42:10 -08006065#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
6066#define WRPLL_DIVIDER_POST_SHIFT 8
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006067#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
Jesse Barnes11578552014-01-21 12:42:10 -08006068#define WRPLL_DIVIDER_FB_SHIFT 16
6069#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
Eugeni Dodonov4dffc402012-03-29 12:32:36 -03006070
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006071/* Port clock selection */
6072#define PORT_CLK_SEL_A 0x46100
6073#define PORT_CLK_SEL_B 0x46104
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006074#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006075#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
6076#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
6077#define PORT_CLK_SEL_LCPLL_810 (2<<29)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006078#define PORT_CLK_SEL_SPLL (3<<29)
Daniel Vetter716c2e52014-06-25 22:02:02 +03006079#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006080#define PORT_CLK_SEL_WRPLL1 (4<<29)
6081#define PORT_CLK_SEL_WRPLL2 (5<<29)
Paulo Zanoni6441ab52012-10-05 12:05:58 -03006082#define PORT_CLK_SEL_NONE (7<<29)
Jesse Barnes11578552014-01-21 12:42:10 -08006083#define PORT_CLK_SEL_MASK (7<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006084
Paulo Zanonibb523fc2012-10-23 18:29:56 -02006085/* Transcoder clock selection */
6086#define TRANS_CLK_SEL_A 0x46140
6087#define TRANS_CLK_SEL_B 0x46144
6088#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
6089/* For each transcoder, we need to select the corresponding port clock */
6090#define TRANS_CLK_SEL_DISABLED (0x0<<29)
6091#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
Eugeni Dodonovfec91812012-03-29 12:32:33 -03006092
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006093#define TRANSA_MSA_MISC 0x60410
6094#define TRANSB_MSA_MISC 0x61410
6095#define TRANSC_MSA_MISC 0x62410
6096#define TRANS_EDP_MSA_MISC 0x6f410
6097#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
6098
Paulo Zanonic9809792012-10-23 18:30:00 -02006099#define TRANS_MSA_SYNC_CLK (1<<0)
6100#define TRANS_MSA_6_BPC (0<<5)
6101#define TRANS_MSA_8_BPC (1<<5)
6102#define TRANS_MSA_10_BPC (2<<5)
6103#define TRANS_MSA_12_BPC (3<<5)
6104#define TRANS_MSA_16_BPC (4<<5)
Paulo Zanonidae84792012-10-15 15:51:30 -03006105
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006106/* LCPLL Control */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006107#define LCPLL_CTL 0x130040
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006108#define LCPLL_PLL_DISABLE (1<<31)
6109#define LCPLL_PLL_LOCK (1<<30)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03006110#define LCPLL_CLK_FREQ_MASK (3<<26)
6111#define LCPLL_CLK_FREQ_450 (0<<26)
Paulo Zanonie39bf982013-11-02 21:07:36 -07006112#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
6113#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
6114#define LCPLL_CLK_FREQ_675_BDW (3<<26)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006115#define LCPLL_CD_CLOCK_DISABLE (1<<25)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006116#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006117#define LCPLL_POWER_DOWN_ALLOW (1<<22)
Paulo Zanoni79f689a2012-10-05 12:05:52 -03006118#define LCPLL_CD_SOURCE_FCLK (1<<21)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006119#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
6120
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03006121/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
6122 * since on HSW we can't write to it using I915_WRITE. */
6123#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
6124#define D_COMP_BDW 0x138144
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006125#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
6126#define D_COMP_COMP_FORCE (1<<8)
6127#define D_COMP_COMP_DISABLE (1<<0)
Eugeni Dodonov90e8d312012-03-29 12:32:35 -03006128
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03006129/* Pipe WM_LINETIME - watermark line time */
6130#define PIPE_WM_LINETIME_A 0x45270
6131#define PIPE_WM_LINETIME_B 0x45274
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006132#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
6133 PIPE_WM_LINETIME_B)
6134#define PIPE_WM_LINETIME_MASK (0x1ff)
6135#define PIPE_WM_LINETIME_TIME(x) ((x))
Eugeni Dodonov69e94b72012-03-29 12:32:37 -03006136#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006137#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03006138
6139/* SFUSE_STRAP */
Paulo Zanoni5e49cea2012-08-08 14:15:31 -03006140#define SFUSE_STRAP 0xc2014
Damien Lespiau658ac4c2014-02-10 17:19:45 +00006141#define SFUSE_STRAP_FUSE_LOCK (1<<13)
6142#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
Eugeni Dodonov96d6e352012-03-29 12:32:38 -03006143#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
6144#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
6145#define SFUSE_STRAP_DDID_DETECTED (1<<0)
6146
Paulo Zanoni801bcff2013-05-31 10:08:35 -03006147#define WM_MISC 0x45260
6148#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
6149
Eugeni Dodonov1544d9d2012-07-02 11:51:10 -03006150#define WM_DBG 0x45280
6151#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
6152#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
6153#define WM_DBG_DISALLOW_SPRITE (1<<2)
6154
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006155/* pipe CSC */
6156#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
6157#define _PIPE_A_CSC_COEFF_BY 0x49014
6158#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
6159#define _PIPE_A_CSC_COEFF_BU 0x4901c
6160#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
6161#define _PIPE_A_CSC_COEFF_BV 0x49024
6162#define _PIPE_A_CSC_MODE 0x49028
Ville Syrjälä29a397b2013-04-19 12:23:02 +03006163#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
6164#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
6165#define CSC_MODE_YUV_TO_RGB (1 << 0)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006166#define _PIPE_A_CSC_PREOFF_HI 0x49030
6167#define _PIPE_A_CSC_PREOFF_ME 0x49034
6168#define _PIPE_A_CSC_PREOFF_LO 0x49038
6169#define _PIPE_A_CSC_POSTOFF_HI 0x49040
6170#define _PIPE_A_CSC_POSTOFF_ME 0x49044
6171#define _PIPE_A_CSC_POSTOFF_LO 0x49048
6172
6173#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
6174#define _PIPE_B_CSC_COEFF_BY 0x49114
6175#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
6176#define _PIPE_B_CSC_COEFF_BU 0x4911c
6177#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
6178#define _PIPE_B_CSC_COEFF_BV 0x49124
6179#define _PIPE_B_CSC_MODE 0x49128
6180#define _PIPE_B_CSC_PREOFF_HI 0x49130
6181#define _PIPE_B_CSC_PREOFF_ME 0x49134
6182#define _PIPE_B_CSC_PREOFF_LO 0x49138
6183#define _PIPE_B_CSC_POSTOFF_HI 0x49140
6184#define _PIPE_B_CSC_POSTOFF_ME 0x49144
6185#define _PIPE_B_CSC_POSTOFF_LO 0x49148
6186
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006187#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6188#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6189#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6190#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6191#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6192#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6193#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6194#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6195#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6196#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6197#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6198#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6199#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6200
Jani Nikula3230bf12013-08-27 15:12:16 +03006201/* VLV MIPI registers */
6202
6203#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
6204#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306205#define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \
6206 _MIPIB_PORT_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006207#define DPI_ENABLE (1 << 31) /* A + B */
6208#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
6209#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
6210#define DUAL_LINK_MODE_MASK (1 << 26)
6211#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
6212#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
6213#define DITHERING_ENABLE (1 << 25) /* A + B */
6214#define FLOPPED_HSTX (1 << 23)
6215#define DE_INVERT (1 << 19) /* XXX */
6216#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
6217#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
6218#define AFE_LATCHOUT (1 << 17)
6219#define LP_OUTPUT_HOLD (1 << 16)
6220#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
6221#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
6222#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
6223#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
6224#define CSB_SHIFT 9
6225#define CSB_MASK (3 << 9)
6226#define CSB_20MHZ (0 << 9)
6227#define CSB_10MHZ (1 << 9)
6228#define CSB_40MHZ (2 << 9)
6229#define BANDGAP_MASK (1 << 8)
6230#define BANDGAP_PNW_CIRCUIT (0 << 8)
6231#define BANDGAP_LNC_CIRCUIT (1 << 8)
6232#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
6233#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
6234#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
6235#define TEARING_EFFECT_SHIFT 2 /* A + B */
6236#define TEARING_EFFECT_MASK (3 << 2)
6237#define TEARING_EFFECT_OFF (0 << 2)
6238#define TEARING_EFFECT_DSI (1 << 2)
6239#define TEARING_EFFECT_GPIO (2 << 2)
6240#define LANE_CONFIGURATION_SHIFT 0
6241#define LANE_CONFIGURATION_MASK (3 << 0)
6242#define LANE_CONFIGURATION_4LANE (0 << 0)
6243#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
6244#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
6245
6246#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
6247#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306248#define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \
6249 _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006250#define TEARING_EFFECT_DELAY_SHIFT 0
6251#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
6252
6253/* XXX: all bits reserved */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306254#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
Jani Nikula3230bf12013-08-27 15:12:16 +03006255
6256/* MIPI DSI Controller and D-PHY registers */
6257
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306258#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
6259#define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306260#define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \
6261 _MIPIB_DEVICE_READY)
Jani Nikula3230bf12013-08-27 15:12:16 +03006262#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
6263#define ULPS_STATE_MASK (3 << 1)
6264#define ULPS_STATE_ENTER (2 << 1)
6265#define ULPS_STATE_EXIT (1 << 1)
6266#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
6267#define DEVICE_READY (1 << 0)
6268
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306269#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
6270#define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306271#define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \
6272 _MIPIB_INTR_STAT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306273#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
6274#define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306275#define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \
6276 _MIPIB_INTR_EN)
Jani Nikula3230bf12013-08-27 15:12:16 +03006277#define TEARING_EFFECT (1 << 31)
6278#define SPL_PKT_SENT_INTERRUPT (1 << 30)
6279#define GEN_READ_DATA_AVAIL (1 << 29)
6280#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
6281#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
6282#define RX_PROT_VIOLATION (1 << 26)
6283#define RX_INVALID_TX_LENGTH (1 << 25)
6284#define ACK_WITH_NO_ERROR (1 << 24)
6285#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
6286#define LP_RX_TIMEOUT (1 << 22)
6287#define HS_TX_TIMEOUT (1 << 21)
6288#define DPI_FIFO_UNDERRUN (1 << 20)
6289#define LOW_CONTENTION (1 << 19)
6290#define HIGH_CONTENTION (1 << 18)
6291#define TXDSI_VC_ID_INVALID (1 << 17)
6292#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
6293#define TXCHECKSUM_ERROR (1 << 15)
6294#define TXECC_MULTIBIT_ERROR (1 << 14)
6295#define TXECC_SINGLE_BIT_ERROR (1 << 13)
6296#define TXFALSE_CONTROL_ERROR (1 << 12)
6297#define RXDSI_VC_ID_INVALID (1 << 11)
6298#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
6299#define RXCHECKSUM_ERROR (1 << 9)
6300#define RXECC_MULTIBIT_ERROR (1 << 8)
6301#define RXECC_SINGLE_BIT_ERROR (1 << 7)
6302#define RXFALSE_CONTROL_ERROR (1 << 6)
6303#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
6304#define RX_LP_TX_SYNC_ERROR (1 << 4)
6305#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
6306#define RXEOT_SYNC_ERROR (1 << 2)
6307#define RXSOT_SYNC_ERROR (1 << 1)
6308#define RXSOT_ERROR (1 << 0)
6309
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306310#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
6311#define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306312#define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \
6313 _MIPIB_DSI_FUNC_PRG)
Jani Nikula3230bf12013-08-27 15:12:16 +03006314#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
6315#define CMD_MODE_NOT_SUPPORTED (0 << 13)
6316#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
6317#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
6318#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
6319#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
6320#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
6321#define VID_MODE_FORMAT_MASK (0xf << 7)
6322#define VID_MODE_NOT_SUPPORTED (0 << 7)
6323#define VID_MODE_FORMAT_RGB565 (1 << 7)
6324#define VID_MODE_FORMAT_RGB666 (2 << 7)
6325#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
6326#define VID_MODE_FORMAT_RGB888 (4 << 7)
6327#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
6328#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
6329#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
6330#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
6331#define DATA_LANES_PRG_REG_SHIFT 0
6332#define DATA_LANES_PRG_REG_MASK (7 << 0)
6333
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306334#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
6335#define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306336#define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \
6337 _MIPIB_HS_TX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006338#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
6339
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306340#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
6341#define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306342#define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \
6343 _MIPIB_LP_RX_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006344#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
6345
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306346#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
6347#define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306348#define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \
6349 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006350#define TURN_AROUND_TIMEOUT_MASK 0x3f
6351
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306352#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
6353#define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306354#define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \
6355 _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
Jani Nikula3230bf12013-08-27 15:12:16 +03006356#define DEVICE_RESET_TIMER_MASK 0xffff
6357
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306358#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
6359#define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306360#define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \
6361 _MIPIB_DPI_RESOLUTION)
Jani Nikula3230bf12013-08-27 15:12:16 +03006362#define VERTICAL_ADDRESS_SHIFT 16
6363#define VERTICAL_ADDRESS_MASK (0xffff << 16)
6364#define HORIZONTAL_ADDRESS_SHIFT 0
6365#define HORIZONTAL_ADDRESS_MASK 0xffff
6366
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306367#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
6368#define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306369#define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \
6370 _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03006371#define DBI_FIFO_EMPTY_HALF (0 << 0)
6372#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
6373#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
6374
6375/* regs below are bits 15:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306376#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
6377#define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306378#define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \
6379 _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006380
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306381#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
6382#define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306383#define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \
6384 _MIPIB_HBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006385
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306386#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
6387#define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306388#define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \
6389 _MIPIB_HFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006390
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306391#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
6392#define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306393#define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \
6394 _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006395
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306396#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
6397#define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306398#define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \
6399 _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006400
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306401#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
6402#define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306403#define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \
6404 _MIPIB_VBP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006405
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306406#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
6407#define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306408#define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \
6409 _MIPIB_VFP_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006410
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306411#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
6412#define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306413#define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \
6414 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306415
Jani Nikula3230bf12013-08-27 15:12:16 +03006416/* regs above are bits 15:0 */
6417
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306418#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
6419#define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306420#define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \
6421 _MIPIB_DPI_CONTROL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006422#define DPI_LP_MODE (1 << 6)
6423#define BACKLIGHT_OFF (1 << 5)
6424#define BACKLIGHT_ON (1 << 4)
6425#define COLOR_MODE_OFF (1 << 3)
6426#define COLOR_MODE_ON (1 << 2)
6427#define TURN_ON (1 << 1)
6428#define SHUTDOWN (1 << 0)
6429
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306430#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
6431#define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306432#define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \
6433 _MIPIB_DPI_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03006434#define COMMAND_BYTE_SHIFT 0
6435#define COMMAND_BYTE_MASK (0x3f << 0)
6436
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306437#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
6438#define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306439#define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \
6440 _MIPIB_INIT_COUNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006441#define MASTER_INIT_TIMER_SHIFT 0
6442#define MASTER_INIT_TIMER_MASK (0xffff << 0)
6443
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306444#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
6445#define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306446#define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \
6447 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
Jani Nikula3230bf12013-08-27 15:12:16 +03006448#define MAX_RETURN_PKT_SIZE_SHIFT 0
6449#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
6450
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306451#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
6452#define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306453#define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \
6454 _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006455#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
6456#define DISABLE_VIDEO_BTA (1 << 3)
6457#define IP_TG_CONFIG (1 << 2)
6458#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
6459#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
6460#define VIDEO_MODE_BURST (3 << 0)
6461
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306462#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
6463#define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306464#define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \
6465 _MIPIB_EOT_DISABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03006466#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
6467#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
6468#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
6469#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
6470#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
6471#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
6472#define CLOCKSTOP (1 << 1)
6473#define EOT_DISABLE (1 << 0)
6474
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306475#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
6476#define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306477#define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \
6478 _MIPIB_LP_BYTECLK)
Jani Nikula3230bf12013-08-27 15:12:16 +03006479#define LP_BYTECLK_SHIFT 0
6480#define LP_BYTECLK_MASK (0xffff << 0)
6481
6482/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306483#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
6484#define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306485#define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \
6486 _MIPIB_LP_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03006487
6488/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306489#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
6490#define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306491#define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \
6492 _MIPIB_HS_GEN_DATA)
Jani Nikula3230bf12013-08-27 15:12:16 +03006493
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306494#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
6495#define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306496#define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \
6497 _MIPIB_LP_GEN_CTRL)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306498#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
6499#define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306500#define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \
6501 _MIPIB_HS_GEN_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006502#define LONG_PACKET_WORD_COUNT_SHIFT 8
6503#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
6504#define SHORT_PACKET_PARAM_SHIFT 8
6505#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
6506#define VIRTUAL_CHANNEL_SHIFT 6
6507#define VIRTUAL_CHANNEL_MASK (3 << 6)
6508#define DATA_TYPE_SHIFT 0
6509#define DATA_TYPE_MASK (3f << 0)
6510/* data type values, see include/video/mipi_display.h */
6511
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306512#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
6513#define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306514#define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \
6515 _MIPIB_GEN_FIFO_STAT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006516#define DPI_FIFO_EMPTY (1 << 28)
6517#define DBI_FIFO_EMPTY (1 << 27)
6518#define LP_CTRL_FIFO_EMPTY (1 << 26)
6519#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
6520#define LP_CTRL_FIFO_FULL (1 << 24)
6521#define HS_CTRL_FIFO_EMPTY (1 << 18)
6522#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
6523#define HS_CTRL_FIFO_FULL (1 << 16)
6524#define LP_DATA_FIFO_EMPTY (1 << 10)
6525#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
6526#define LP_DATA_FIFO_FULL (1 << 8)
6527#define HS_DATA_FIFO_EMPTY (1 << 2)
6528#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
6529#define HS_DATA_FIFO_FULL (1 << 0)
6530
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306531#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
6532#define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306533#define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \
6534 _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
Jani Nikula3230bf12013-08-27 15:12:16 +03006535#define DBI_HS_LP_MODE_MASK (1 << 0)
6536#define DBI_LP_MODE (1 << 0)
6537#define DBI_HS_MODE (0 << 0)
6538
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306539#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
6540#define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306541#define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \
6542 _MIPIB_DPHY_PARAM)
Jani Nikula3230bf12013-08-27 15:12:16 +03006543#define EXIT_ZERO_COUNT_SHIFT 24
6544#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
6545#define TRAIL_COUNT_SHIFT 16
6546#define TRAIL_COUNT_MASK (0x1f << 16)
6547#define CLK_ZERO_COUNT_SHIFT 8
6548#define CLK_ZERO_COUNT_MASK (0xff << 8)
6549#define PREPARE_COUNT_SHIFT 0
6550#define PREPARE_COUNT_MASK (0x3f << 0)
6551
6552/* bits 31:0 */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306553#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
6554#define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306555#define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \
6556 _MIPIB_DBI_BW_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006557
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306558#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
6559 + 0xb088)
6560#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
6561 + 0xb888)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306562#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \
6563 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
Jani Nikula3230bf12013-08-27 15:12:16 +03006564#define LP_HS_SSW_CNT_SHIFT 16
6565#define LP_HS_SSW_CNT_MASK (0xffff << 16)
6566#define HS_LP_PWR_SW_CNT_SHIFT 0
6567#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
6568
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306569#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
6570#define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306571#define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \
6572 _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006573#define STOP_STATE_STALL_COUNTER_SHIFT 0
6574#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
6575
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306576#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
6577#define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306578#define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \
6579 _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306580#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
6581#define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306582#define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \
6583 _MIPIB_INTR_EN_REG_1)
Jani Nikula3230bf12013-08-27 15:12:16 +03006584#define RX_CONTENTION_DETECTED (1 << 0)
6585
6586/* XXX: only pipe A ?!? */
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306587#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
Jani Nikula3230bf12013-08-27 15:12:16 +03006588#define DBI_TYPEC_ENABLE (1 << 31)
6589#define DBI_TYPEC_WIP (1 << 30)
6590#define DBI_TYPEC_OPTION_SHIFT 28
6591#define DBI_TYPEC_OPTION_MASK (3 << 28)
6592#define DBI_TYPEC_FREQ_SHIFT 24
6593#define DBI_TYPEC_FREQ_MASK (0xf << 24)
6594#define DBI_TYPEC_OVERRIDE (1 << 8)
6595#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
6596#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
6597
6598
6599/* MIPI adapter registers */
6600
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306601#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
6602#define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306603#define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \
6604 _MIPIB_CTRL)
Jani Nikula3230bf12013-08-27 15:12:16 +03006605#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
6606#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
6607#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
6608#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
6609#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
6610#define READ_REQUEST_PRIORITY_SHIFT 3
6611#define READ_REQUEST_PRIORITY_MASK (3 << 3)
6612#define READ_REQUEST_PRIORITY_LOW (0 << 3)
6613#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
6614#define RGB_FLIP_TO_BGR (1 << 2)
6615
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306616#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
6617#define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306618#define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \
6619 _MIPIB_DATA_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03006620#define DATA_MEM_ADDRESS_SHIFT 5
6621#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
6622#define DATA_VALID (1 << 0)
6623
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306624#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
6625#define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306626#define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \
6627 _MIPIB_DATA_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03006628#define DATA_LENGTH_SHIFT 0
6629#define DATA_LENGTH_MASK (0xfffff << 0)
6630
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306631#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
6632#define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306633#define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \
6634 _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
Jani Nikula3230bf12013-08-27 15:12:16 +03006635#define COMMAND_MEM_ADDRESS_SHIFT 5
6636#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
6637#define AUTO_PWG_ENABLE (1 << 2)
6638#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
6639#define COMMAND_VALID (1 << 0)
6640
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306641#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
6642#define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306643#define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \
6644 _MIPIB_COMMAND_LENGTH)
Jani Nikula3230bf12013-08-27 15:12:16 +03006645#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
6646#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
6647
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306648#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
6649#define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306650#define MIPI_READ_DATA_RETURN(tc, n) \
6651 (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \
6652 + 4 * (n)) /* n: 0...7 */
Jani Nikula3230bf12013-08-27 15:12:16 +03006653
Shashank Sharma4ad83e92014-06-02 18:07:47 +05306654#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
6655#define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
Shashank Sharmaa2560a62014-06-02 18:07:48 +05306656#define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \
6657 _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
Jani Nikula3230bf12013-08-27 15:12:16 +03006658#define READ_DATA_VALID(n) (1 << (n))
6659
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006660/* For UMS only (deprecated): */
Damien Lespiau5c969aa2014-02-07 19:12:48 +00006661#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
6662#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
Antti Koskipaaa57c7742014-02-04 14:22:24 +02006663
Jesse Barnes585fb112008-07-29 11:54:06 -07006664#endif /* _I915_REG_H_ */