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Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Jesse Barnes63eeaf32009-06-18 16:56:52 -070029#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010035#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#define MAX_NOPID ((u32)~0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Keith Packard7c463582008-11-04 02:03:27 -080040/**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050047#define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Keith Packard7c463582008-11-04 02:03:27 -080054
55/** Interrupts that we mask and unmask at runtime. */
56#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
57
Jesse Barnes79e53942008-11-07 14:24:08 -080058#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +010067void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050068ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080069{
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
74 }
75}
76
77static inline void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050078ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080079{
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
84 }
85}
86
87/* For display hotplug interrupt */
88void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050089ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080090{
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
95 }
96}
97
98static inline void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050099ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800100{
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
105 }
106}
107
108void
Eric Anholted4cb412008-07-29 12:10:39 -0700109i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110{
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
115 }
116}
117
118static inline void
119i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120{
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
125 }
126}
127
Keith Packard7c463582008-11-04 02:03:27 -0800128static inline u32
129i915_pipestat(int pipe)
130{
131 if (pipe == 0)
132 return PIPEASTAT;
133 if (pipe == 1)
134 return PIPEBSTAT;
Andrew Morton9c84ba42008-12-01 13:14:08 -0800135 BUG();
Keith Packard7c463582008-11-04 02:03:27 -0800136}
137
138void
139i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140{
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
143
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
148 }
149}
150
151void
152i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153{
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
156
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
160 }
161}
162
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000163/**
Zhao Yakui01c66882009-10-28 05:10:00 +0000164 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 */
166void intel_enable_asle (struct drm_device *dev)
167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
Eric Anholtc619eed2010-01-28 16:45:52 -0800170 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500171 ironlake_enable_display_irq(dev_priv, DE_GSE);
Zhao Yakui01c66882009-10-28 05:10:00 +0000172 else
173 i915_enable_pipestat(dev_priv, 1,
174 I915_LEGACY_BLC_EVENT_ENABLE);
175}
176
177/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700178 * i915_pipe_enabled - check if a pipe is enabled
179 * @dev: DRM device
180 * @pipe: pipe to check
181 *
182 * Reading certain registers when the pipe is disabled can hang the chip.
183 * Use this routine to make sure the PLL is running and the pipe is active
184 * before reading such registers if unsure.
185 */
186static int
187i915_pipe_enabled(struct drm_device *dev, int pipe)
188{
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
190 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
191
192 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
193 return 1;
194
195 return 0;
196}
197
Keith Packard42f52ef2008-10-18 19:39:29 -0700198/* Called from drm generic code, passed a 'crtc', which
199 * we use as a pipe index
200 */
201u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700202{
203 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
204 unsigned long high_frame;
205 unsigned long low_frame;
206 u32 high1, high2, low, count;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700207
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700208 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
209 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
210
211 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800212 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
213 "pipe %d\n", pipe);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700214 return 0;
215 }
216
217 /*
218 * High & low register fields aren't synchronized, so make sure
219 * we get a low value that's stable across two reads of the high
220 * register.
221 */
222 do {
223 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
224 PIPE_FRAME_HIGH_SHIFT);
225 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
226 PIPE_FRAME_LOW_SHIFT);
227 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
228 PIPE_FRAME_HIGH_SHIFT);
229 } while (high1 != high2);
230
231 count = (high1 << 8) | low;
232
233 return count;
234}
235
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800236u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
237{
238 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
239 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
240
241 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800242 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
243 "pipe %d\n", pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800244 return 0;
245 }
246
247 return I915_READ(reg);
248}
249
Jesse Barnes5ca58282009-03-31 14:11:15 -0700250/*
251 * Handle hotplug events outside the interrupt handler proper.
252 */
253static void i915_hotplug_work_func(struct work_struct *work)
254{
255 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
256 hotplug_work);
257 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700258 struct drm_mode_config *mode_config = &dev->mode_config;
259 struct drm_connector *connector;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700260
Keith Packardc31c4ba2009-05-06 11:48:58 -0700261 if (mode_config->num_connector) {
262 list_for_each_entry(connector, &mode_config->connector_list, head) {
Eric Anholt21d40d32010-03-25 11:11:14 -0700263 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
Keith Packardc31c4ba2009-05-06 11:48:58 -0700264
Eric Anholt21d40d32010-03-25 11:11:14 -0700265 if (intel_encoder->hot_plug)
266 (*intel_encoder->hot_plug) (intel_encoder);
Keith Packardc31c4ba2009-05-06 11:48:58 -0700267 }
268 }
Jesse Barnes5ca58282009-03-31 14:11:15 -0700269 /* Just fire off a uevent and let userspace tell us what to do */
270 drm_sysfs_hotplug_event(dev);
271}
272
Jesse Barnesf97108d2010-01-29 11:27:07 -0800273static void i915_handle_rps_change(struct drm_device *dev)
274{
275 drm_i915_private_t *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000276 u32 busy_up, busy_down, max_avg, min_avg;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800277 u16 rgvswctl;
278 u8 new_delay = dev_priv->cur_delay;
279
280 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000281 busy_up = I915_READ(RCPREVBSYTUPAVG);
282 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800283 max_avg = I915_READ(RCBMAXAVG);
284 min_avg = I915_READ(RCBMINAVG);
285
286 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000287 if (busy_up > max_avg) {
Jesse Barnesf97108d2010-01-29 11:27:07 -0800288 if (dev_priv->cur_delay != dev_priv->max_delay)
289 new_delay = dev_priv->cur_delay - 1;
290 if (new_delay < dev_priv->max_delay)
291 new_delay = dev_priv->max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000292 } else if (busy_down < min_avg) {
Jesse Barnesf97108d2010-01-29 11:27:07 -0800293 if (dev_priv->cur_delay != dev_priv->min_delay)
294 new_delay = dev_priv->cur_delay + 1;
295 if (new_delay > dev_priv->min_delay)
296 new_delay = dev_priv->min_delay;
297 }
298
299 DRM_DEBUG("rps change requested: %d -> %d\n",
300 dev_priv->cur_delay, new_delay);
301
302 rgvswctl = I915_READ(MEMSWCTL);
303 if (rgvswctl & MEMCTL_CMD_STS) {
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000304 DRM_ERROR("gpu busy, RCS change rejected\n");
305 return; /* still busy with another command */
Jesse Barnesf97108d2010-01-29 11:27:07 -0800306 }
307
308 /* Program the new state */
309 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
310 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
311 I915_WRITE(MEMSWCTL, rgvswctl);
312 POSTING_READ(MEMSWCTL);
313
314 rgvswctl |= MEMCTL_CMD_STS;
315 I915_WRITE(MEMSWCTL, rgvswctl);
316
317 dev_priv->cur_delay = new_delay;
318
319 DRM_DEBUG("rps changed\n");
320
321 return;
322}
323
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500324irqreturn_t ironlake_irq_handler(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800325{
326 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
327 int ret = IRQ_NONE;
Dave Airlie3ff99162009-12-08 14:03:47 +1000328 u32 de_iir, gt_iir, de_ier, pch_iir;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800329 struct drm_i915_master_private *master_priv;
330
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000331 /* disable master interrupt before clearing iir */
332 de_ier = I915_READ(DEIER);
333 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
334 (void)I915_READ(DEIER);
335
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800336 de_iir = I915_READ(DEIIR);
337 gt_iir = I915_READ(GTIIR);
Zhenyu Wangc6501562009-11-03 18:57:21 +0000338 pch_iir = I915_READ(SDEIIR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800339
Zou Nan haic7c85102010-01-15 10:29:06 +0800340 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
341 goto done;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800342
Zou Nan haic7c85102010-01-15 10:29:06 +0800343 ret = IRQ_HANDLED;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800344
Zou Nan haic7c85102010-01-15 10:29:06 +0800345 if (dev->primary->master) {
346 master_priv = dev->primary->master->driver_priv;
347 if (master_priv->sarea_priv)
348 master_priv->sarea_priv->last_dispatch =
349 READ_BREADCRUMB(dev_priv);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800350 }
351
Jesse Barnese552eb72010-04-21 11:39:23 -0700352 if (gt_iir & GT_PIPE_NOTIFY) {
Zou Nan haic7c85102010-01-15 10:29:06 +0800353 u32 seqno = i915_get_gem_seqno(dev);
354 dev_priv->mm.irq_gem_seqno = seqno;
355 trace_i915_gem_request_complete(dev, seqno);
356 DRM_WAKEUP(&dev_priv->irq_queue);
357 dev_priv->hangcheck_count = 0;
358 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
359 }
360
361 if (de_iir & DE_GSE)
362 ironlake_opregion_gse_intr(dev);
363
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800364 if (de_iir & DE_PLANEA_FLIP_DONE) {
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800365 intel_prepare_page_flip(dev, 0);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800366 intel_finish_page_flip(dev, 0);
367 }
368
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800369 if (de_iir & DE_PLANEB_FLIP_DONE) {
370 intel_prepare_page_flip(dev, 1);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800371 intel_finish_page_flip(dev, 1);
372 }
Li Pengc062df62010-01-23 00:12:58 +0800373
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800374 if (de_iir & DE_PIPEA_VBLANK)
375 drm_handle_vblank(dev, 0);
376
377 if (de_iir & DE_PIPEB_VBLANK)
378 drm_handle_vblank(dev, 1);
379
Zou Nan haic7c85102010-01-15 10:29:06 +0800380 /* check event from PCH */
381 if ((de_iir & DE_PCH_EVENT) &&
382 (pch_iir & SDE_HOTPLUG_MASK)) {
383 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
384 }
385
Jesse Barnesf97108d2010-01-29 11:27:07 -0800386 if (de_iir & DE_PCU_EVENT) {
387 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
388 i915_handle_rps_change(dev);
389 }
390
Zou Nan haic7c85102010-01-15 10:29:06 +0800391 /* should clear PCH hotplug event before clear CPU irq */
392 I915_WRITE(SDEIIR, pch_iir);
393 I915_WRITE(GTIIR, gt_iir);
394 I915_WRITE(DEIIR, de_iir);
395
396done:
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000397 I915_WRITE(DEIER, de_ier);
398 (void)I915_READ(DEIER);
399
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800400 return ret;
401}
402
Jesse Barnes8a905232009-07-11 16:48:03 -0400403/**
404 * i915_error_work_func - do process context error handling work
405 * @work: work struct
406 *
407 * Fire an error uevent so userspace can see that a hang or error
408 * was detected.
409 */
410static void i915_error_work_func(struct work_struct *work)
411{
412 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
413 error_work);
414 struct drm_device *dev = dev_priv->dev;
Ben Gamarif316a422009-09-14 17:48:46 -0400415 char *error_event[] = { "ERROR=1", NULL };
416 char *reset_event[] = { "RESET=1", NULL };
417 char *reset_done_event[] = { "ERROR=0", NULL };
Jesse Barnes8a905232009-07-11 16:48:03 -0400418
Zhao Yakui44d98a62009-10-09 11:39:40 +0800419 DRM_DEBUG_DRIVER("generating error event\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400420 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -0400421
Ben Gamariba1234d2009-09-14 17:48:47 -0400422 if (atomic_read(&dev_priv->mm.wedged)) {
Ben Gamarif316a422009-09-14 17:48:46 -0400423 if (IS_I965G(dev)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800424 DRM_DEBUG_DRIVER("resetting chip\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400425 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
426 if (!i965_reset(dev, GDRST_RENDER)) {
Ben Gamariba1234d2009-09-14 17:48:47 -0400427 atomic_set(&dev_priv->mm.wedged, 0);
Ben Gamarif316a422009-09-14 17:48:46 -0400428 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
429 }
430 } else {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800431 DRM_DEBUG_DRIVER("reboot required\n");
Ben Gamarif316a422009-09-14 17:48:46 -0400432 }
433 }
Jesse Barnes8a905232009-07-11 16:48:03 -0400434}
435
Chris Wilson9df30792010-02-18 10:24:56 +0000436static struct drm_i915_error_object *
437i915_error_object_create(struct drm_device *dev,
438 struct drm_gem_object *src)
439{
440 struct drm_i915_error_object *dst;
441 struct drm_i915_gem_object *src_priv;
442 int page, page_count;
443
444 if (src == NULL)
445 return NULL;
446
Daniel Vetter23010e42010-03-08 13:35:02 +0100447 src_priv = to_intel_bo(src);
Chris Wilson9df30792010-02-18 10:24:56 +0000448 if (src_priv->pages == NULL)
449 return NULL;
450
451 page_count = src->size / PAGE_SIZE;
452
453 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
454 if (dst == NULL)
455 return NULL;
456
457 for (page = 0; page < page_count; page++) {
458 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
459 if (d == NULL)
460 goto unwind;
461 s = kmap_atomic(src_priv->pages[page], KM_USER0);
462 memcpy(d, s, PAGE_SIZE);
463 kunmap_atomic(s, KM_USER0);
464 dst->pages[page] = d;
465 }
466 dst->page_count = page_count;
467 dst->gtt_offset = src_priv->gtt_offset;
468
469 return dst;
470
471unwind:
472 while (page--)
473 kfree(dst->pages[page]);
474 kfree(dst);
475 return NULL;
476}
477
478static void
479i915_error_object_free(struct drm_i915_error_object *obj)
480{
481 int page;
482
483 if (obj == NULL)
484 return;
485
486 for (page = 0; page < obj->page_count; page++)
487 kfree(obj->pages[page]);
488
489 kfree(obj);
490}
491
492static void
493i915_error_state_free(struct drm_device *dev,
494 struct drm_i915_error_state *error)
495{
496 i915_error_object_free(error->batchbuffer[0]);
497 i915_error_object_free(error->batchbuffer[1]);
498 i915_error_object_free(error->ringbuffer);
499 kfree(error->active_bo);
500 kfree(error);
501}
502
503static u32
504i915_get_bbaddr(struct drm_device *dev, u32 *ring)
505{
506 u32 cmd;
507
508 if (IS_I830(dev) || IS_845G(dev))
509 cmd = MI_BATCH_BUFFER;
510 else if (IS_I965G(dev))
511 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
512 MI_BATCH_NON_SECURE_I965);
513 else
514 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
515
516 return ring[0] == cmd ? ring[1] : 0;
517}
518
519static u32
520i915_ringbuffer_last_batch(struct drm_device *dev)
521{
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 u32 head, bbaddr;
524 u32 *ring;
525
526 /* Locate the current position in the ringbuffer and walk back
527 * to find the most recently dispatched batch buffer.
528 */
529 bbaddr = 0;
530 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
531 ring = (u32 *)(dev_priv->ring.virtual_start + head);
532
533 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
534 bbaddr = i915_get_bbaddr(dev, ring);
535 if (bbaddr)
536 break;
537 }
538
539 if (bbaddr == 0) {
540 ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
541 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
542 bbaddr = i915_get_bbaddr(dev, ring);
543 if (bbaddr)
544 break;
545 }
546 }
547
548 return bbaddr;
549}
550
Jesse Barnes8a905232009-07-11 16:48:03 -0400551/**
552 * i915_capture_error_state - capture an error record for later analysis
553 * @dev: drm device
554 *
555 * Should be called when an error is detected (either a hang or an error
556 * interrupt) to capture error state from the time of the error. Fills
557 * out a structure which becomes available in debugfs for user level tools
558 * to pick up.
559 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700560static void i915_capture_error_state(struct drm_device *dev)
561{
562 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9df30792010-02-18 10:24:56 +0000563 struct drm_i915_gem_object *obj_priv;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700564 struct drm_i915_error_state *error;
Chris Wilson9df30792010-02-18 10:24:56 +0000565 struct drm_gem_object *batchbuffer[2];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700566 unsigned long flags;
Chris Wilson9df30792010-02-18 10:24:56 +0000567 u32 bbaddr;
568 int count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700569
570 spin_lock_irqsave(&dev_priv->error_lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000571 error = dev_priv->first_error;
572 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
573 if (error)
574 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700575
576 error = kmalloc(sizeof(*error), GFP_ATOMIC);
577 if (!error) {
Chris Wilson9df30792010-02-18 10:24:56 +0000578 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
579 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700580 }
581
Chris Wilson9df30792010-02-18 10:24:56 +0000582 error->seqno = i915_get_gem_seqno(dev);
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700583 error->eir = I915_READ(EIR);
584 error->pgtbl_er = I915_READ(PGTBL_ER);
585 error->pipeastat = I915_READ(PIPEASTAT);
586 error->pipebstat = I915_READ(PIPEBSTAT);
587 error->instpm = I915_READ(INSTPM);
588 if (!IS_I965G(dev)) {
589 error->ipeir = I915_READ(IPEIR);
590 error->ipehr = I915_READ(IPEHR);
591 error->instdone = I915_READ(INSTDONE);
592 error->acthd = I915_READ(ACTHD);
Chris Wilson9df30792010-02-18 10:24:56 +0000593 error->bbaddr = 0;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700594 } else {
595 error->ipeir = I915_READ(IPEIR_I965);
596 error->ipehr = I915_READ(IPEHR_I965);
597 error->instdone = I915_READ(INSTDONE_I965);
598 error->instps = I915_READ(INSTPS);
599 error->instdone1 = I915_READ(INSTDONE1);
600 error->acthd = I915_READ(ACTHD_I965);
Chris Wilson9df30792010-02-18 10:24:56 +0000601 error->bbaddr = I915_READ64(BB_ADDR);
602 }
603
604 bbaddr = i915_ringbuffer_last_batch(dev);
605
606 /* Grab the current batchbuffer, most likely to have crashed. */
607 batchbuffer[0] = NULL;
608 batchbuffer[1] = NULL;
609 count = 0;
610 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
611 struct drm_gem_object *obj = obj_priv->obj;
612
613 if (batchbuffer[0] == NULL &&
614 bbaddr >= obj_priv->gtt_offset &&
615 bbaddr < obj_priv->gtt_offset + obj->size)
616 batchbuffer[0] = obj;
617
618 if (batchbuffer[1] == NULL &&
619 error->acthd >= obj_priv->gtt_offset &&
620 error->acthd < obj_priv->gtt_offset + obj->size &&
621 batchbuffer[0] != obj)
622 batchbuffer[1] = obj;
623
624 count++;
625 }
626
627 /* We need to copy these to an anonymous buffer as the simplest
628 * method to avoid being overwritten by userpace.
629 */
630 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
631 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
632
633 /* Record the ringbuffer */
634 error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
635
636 /* Record buffers on the active list. */
637 error->active_bo = NULL;
638 error->active_bo_count = 0;
639
640 if (count)
641 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
642 GFP_ATOMIC);
643
644 if (error->active_bo) {
645 int i = 0;
646 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
647 struct drm_gem_object *obj = obj_priv->obj;
648
649 error->active_bo[i].size = obj->size;
650 error->active_bo[i].name = obj->name;
651 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
652 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
653 error->active_bo[i].read_domains = obj->read_domains;
654 error->active_bo[i].write_domain = obj->write_domain;
655 error->active_bo[i].fence_reg = obj_priv->fence_reg;
656 error->active_bo[i].pinned = 0;
657 if (obj_priv->pin_count > 0)
658 error->active_bo[i].pinned = 1;
659 if (obj_priv->user_pin_count > 0)
660 error->active_bo[i].pinned = -1;
661 error->active_bo[i].tiling = obj_priv->tiling_mode;
662 error->active_bo[i].dirty = obj_priv->dirty;
663 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
664
665 if (++i == count)
666 break;
667 }
668 error->active_bo_count = i;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700669 }
670
Jesse Barnes8a905232009-07-11 16:48:03 -0400671 do_gettimeofday(&error->time);
672
Chris Wilson9df30792010-02-18 10:24:56 +0000673 spin_lock_irqsave(&dev_priv->error_lock, flags);
674 if (dev_priv->first_error == NULL) {
675 dev_priv->first_error = error;
676 error = NULL;
677 }
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700678 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +0000679
680 if (error)
681 i915_error_state_free(dev, error);
682}
683
684void i915_destroy_error_state(struct drm_device *dev)
685{
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct drm_i915_error_state *error;
688
689 spin_lock(&dev_priv->error_lock);
690 error = dev_priv->first_error;
691 dev_priv->first_error = NULL;
692 spin_unlock(&dev_priv->error_lock);
693
694 if (error)
695 i915_error_state_free(dev, error);
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700696}
697
Jesse Barnes8a905232009-07-11 16:48:03 -0400698/**
699 * i915_handle_error - handle an error interrupt
700 * @dev: drm device
701 *
702 * Do some basic checking of regsiter state at error interrupt time and
703 * dump it to the syslog. Also call i915_capture_error_state() to make
704 * sure we get a record and make it available in debugfs. Fire a uevent
705 * so userspace knows something bad happened (should trigger collection
706 * of a ring dump etc.).
707 */
Ben Gamariba1234d2009-09-14 17:48:47 -0400708static void i915_handle_error(struct drm_device *dev, bool wedged)
Jesse Barnes8a905232009-07-11 16:48:03 -0400709{
710 struct drm_i915_private *dev_priv = dev->dev_private;
711 u32 eir = I915_READ(EIR);
712 u32 pipea_stats = I915_READ(PIPEASTAT);
713 u32 pipeb_stats = I915_READ(PIPEBSTAT);
714
715 i915_capture_error_state(dev);
716
717 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
718 eir);
719
720 if (IS_G4X(dev)) {
721 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
722 u32 ipeir = I915_READ(IPEIR_I965);
723
724 printk(KERN_ERR " IPEIR: 0x%08x\n",
725 I915_READ(IPEIR_I965));
726 printk(KERN_ERR " IPEHR: 0x%08x\n",
727 I915_READ(IPEHR_I965));
728 printk(KERN_ERR " INSTDONE: 0x%08x\n",
729 I915_READ(INSTDONE_I965));
730 printk(KERN_ERR " INSTPS: 0x%08x\n",
731 I915_READ(INSTPS));
732 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
733 I915_READ(INSTDONE1));
734 printk(KERN_ERR " ACTHD: 0x%08x\n",
735 I915_READ(ACTHD_I965));
736 I915_WRITE(IPEIR_I965, ipeir);
737 (void)I915_READ(IPEIR_I965);
738 }
739 if (eir & GM45_ERROR_PAGE_TABLE) {
740 u32 pgtbl_err = I915_READ(PGTBL_ER);
741 printk(KERN_ERR "page table error\n");
742 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
743 pgtbl_err);
744 I915_WRITE(PGTBL_ER, pgtbl_err);
745 (void)I915_READ(PGTBL_ER);
746 }
747 }
748
749 if (IS_I9XX(dev)) {
750 if (eir & I915_ERROR_PAGE_TABLE) {
751 u32 pgtbl_err = I915_READ(PGTBL_ER);
752 printk(KERN_ERR "page table error\n");
753 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
754 pgtbl_err);
755 I915_WRITE(PGTBL_ER, pgtbl_err);
756 (void)I915_READ(PGTBL_ER);
757 }
758 }
759
760 if (eir & I915_ERROR_MEMORY_REFRESH) {
761 printk(KERN_ERR "memory refresh error\n");
762 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
763 pipea_stats);
764 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
765 pipeb_stats);
766 /* pipestat has already been acked */
767 }
768 if (eir & I915_ERROR_INSTRUCTION) {
769 printk(KERN_ERR "instruction error\n");
770 printk(KERN_ERR " INSTPM: 0x%08x\n",
771 I915_READ(INSTPM));
772 if (!IS_I965G(dev)) {
773 u32 ipeir = I915_READ(IPEIR);
774
775 printk(KERN_ERR " IPEIR: 0x%08x\n",
776 I915_READ(IPEIR));
777 printk(KERN_ERR " IPEHR: 0x%08x\n",
778 I915_READ(IPEHR));
779 printk(KERN_ERR " INSTDONE: 0x%08x\n",
780 I915_READ(INSTDONE));
781 printk(KERN_ERR " ACTHD: 0x%08x\n",
782 I915_READ(ACTHD));
783 I915_WRITE(IPEIR, ipeir);
784 (void)I915_READ(IPEIR);
785 } else {
786 u32 ipeir = I915_READ(IPEIR_I965);
787
788 printk(KERN_ERR " IPEIR: 0x%08x\n",
789 I915_READ(IPEIR_I965));
790 printk(KERN_ERR " IPEHR: 0x%08x\n",
791 I915_READ(IPEHR_I965));
792 printk(KERN_ERR " INSTDONE: 0x%08x\n",
793 I915_READ(INSTDONE_I965));
794 printk(KERN_ERR " INSTPS: 0x%08x\n",
795 I915_READ(INSTPS));
796 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
797 I915_READ(INSTDONE1));
798 printk(KERN_ERR " ACTHD: 0x%08x\n",
799 I915_READ(ACTHD_I965));
800 I915_WRITE(IPEIR_I965, ipeir);
801 (void)I915_READ(IPEIR_I965);
802 }
803 }
804
805 I915_WRITE(EIR, eir);
806 (void)I915_READ(EIR);
807 eir = I915_READ(EIR);
808 if (eir) {
809 /*
810 * some errors might have become stuck,
811 * mask them.
812 */
813 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
814 I915_WRITE(EMR, I915_READ(EMR) | eir);
815 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
816 }
817
Ben Gamariba1234d2009-09-14 17:48:47 -0400818 if (wedged) {
819 atomic_set(&dev_priv->mm.wedged, 1);
820
Ben Gamari11ed50e2009-09-14 17:48:45 -0400821 /*
822 * Wakeup waiting processes so they don't hang
823 */
Ben Gamari11ed50e2009-09-14 17:48:45 -0400824 DRM_WAKEUP(&dev_priv->irq_queue);
825 }
826
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700827 queue_work(dev_priv->wq, &dev_priv->error_work);
Jesse Barnes8a905232009-07-11 16:48:03 -0400828}
829
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
831{
Dave Airlie84b1fd12007-07-11 15:53:27 +1000832 struct drm_device *dev = (struct drm_device *) arg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000834 struct drm_i915_master_private *master_priv;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800835 u32 iir, new_iir;
836 u32 pipea_stats, pipeb_stats;
Keith Packard05eff842008-11-19 14:03:05 -0800837 u32 vblank_status;
838 u32 vblank_enable;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700839 int vblank = 0;
Keith Packard7c463582008-11-04 02:03:27 -0800840 unsigned long irqflags;
Keith Packard05eff842008-11-19 14:03:05 -0800841 int irq_received;
842 int ret = IRQ_NONE;
Dave Airlieaf6061a2008-05-07 12:15:39 +1000843
Eric Anholt630681d2008-10-06 15:14:12 -0700844 atomic_inc(&dev_priv->irq_received);
845
Eric Anholtbad720f2009-10-22 16:11:14 -0700846 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500847 return ironlake_irq_handler(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800848
Eric Anholted4cb412008-07-29 12:10:39 -0700849 iir = I915_READ(IIR);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000850
Keith Packard05eff842008-11-19 14:03:05 -0800851 if (IS_I965G(dev)) {
852 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
853 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
854 } else {
855 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
856 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
857 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858
Keith Packard05eff842008-11-19 14:03:05 -0800859 for (;;) {
860 irq_received = iir != 0;
861
862 /* Can't rely on pipestat interrupt bit in iir as it might
863 * have been cleared after the pipestat interrupt was received.
864 * It doesn't set the bit in iir again, but it still produces
865 * interrupts (for non-MSI).
866 */
867 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
868 pipea_stats = I915_READ(PIPEASTAT);
869 pipeb_stats = I915_READ(PIPEBSTAT);
Jesse Barnes79e53942008-11-07 14:24:08 -0800870
Jesse Barnes8a905232009-07-11 16:48:03 -0400871 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Ben Gamariba1234d2009-09-14 17:48:47 -0400872 i915_handle_error(dev, false);
Jesse Barnes8a905232009-07-11 16:48:03 -0400873
Eric Anholtcdfbc412008-11-04 15:50:30 -0800874 /*
875 * Clear the PIPE(A|B)STAT regs before the IIR
876 */
Keith Packard05eff842008-11-19 14:03:05 -0800877 if (pipea_stats & 0x8000ffff) {
Shaohua Li7662c8b2009-06-26 11:23:55 +0800878 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
Zhao Yakui44d98a62009-10-09 11:39:40 +0800879 DRM_DEBUG_DRIVER("pipe a underrun\n");
Eric Anholtcdfbc412008-11-04 15:50:30 -0800880 I915_WRITE(PIPEASTAT, pipea_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800881 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800882 }
Keith Packard7c463582008-11-04 02:03:27 -0800883
Keith Packard05eff842008-11-19 14:03:05 -0800884 if (pipeb_stats & 0x8000ffff) {
Shaohua Li7662c8b2009-06-26 11:23:55 +0800885 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
Zhao Yakui44d98a62009-10-09 11:39:40 +0800886 DRM_DEBUG_DRIVER("pipe b underrun\n");
Eric Anholtcdfbc412008-11-04 15:50:30 -0800887 I915_WRITE(PIPEBSTAT, pipeb_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800888 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800889 }
Keith Packard05eff842008-11-19 14:03:05 -0800890 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
891
892 if (!irq_received)
893 break;
894
895 ret = IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896
Jesse Barnes5ca58282009-03-31 14:11:15 -0700897 /* Consume port. Then clear IIR or we'll miss events */
898 if ((I915_HAS_HOTPLUG(dev)) &&
899 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
900 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
901
Zhao Yakui44d98a62009-10-09 11:39:40 +0800902 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
Jesse Barnes5ca58282009-03-31 14:11:15 -0700903 hotplug_status);
904 if (hotplug_status & dev_priv->hotplug_supported_mask)
Eric Anholt9c9fe1f2009-08-03 16:09:16 -0700905 queue_work(dev_priv->wq,
906 &dev_priv->hotplug_work);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700907
908 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
909 I915_READ(PORT_HOTPLUG_STAT);
910 }
911
Eric Anholtcdfbc412008-11-04 15:50:30 -0800912 I915_WRITE(IIR, iir);
913 new_iir = I915_READ(IIR); /* Flush posted writes */
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100914
Dave Airlie7c1c2872008-11-28 14:22:24 +1000915 if (dev->primary->master) {
916 master_priv = dev->primary->master->driver_priv;
917 if (master_priv->sarea_priv)
918 master_priv->sarea_priv->last_dispatch =
919 READ_BREADCRUMB(dev_priv);
920 }
Keith Packard7c463582008-11-04 02:03:27 -0800921
Eric Anholtcdfbc412008-11-04 15:50:30 -0800922 if (iir & I915_USER_INTERRUPT) {
Chris Wilson1c5d22f2009-08-25 11:15:50 +0100923 u32 seqno = i915_get_gem_seqno(dev);
924 dev_priv->mm.irq_gem_seqno = seqno;
925 trace_i915_gem_request_complete(dev, seqno);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800926 DRM_WAKEUP(&dev_priv->irq_queue);
Ben Gamarif65d9422009-09-14 17:48:44 -0400927 dev_priv->hangcheck_count = 0;
928 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800929 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700930
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500931 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
932 intel_prepare_page_flip(dev, 0);
933
934 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
935 intel_prepare_page_flip(dev, 1);
936
Keith Packard05eff842008-11-19 14:03:05 -0800937 if (pipea_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800938 vblank++;
939 drm_handle_vblank(dev, 0);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500940 intel_finish_page_flip(dev, 0);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800941 }
Eric Anholt673a3942008-07-30 12:06:12 -0700942
Keith Packard05eff842008-11-19 14:03:05 -0800943 if (pipeb_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800944 vblank++;
945 drm_handle_vblank(dev, 1);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500946 intel_finish_page_flip(dev, 1);
Eric Anholtcdfbc412008-11-04 15:50:30 -0800947 }
Keith Packard7c463582008-11-04 02:03:27 -0800948
Eric Anholtcdfbc412008-11-04 15:50:30 -0800949 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
950 (iir & I915_ASLE_INTERRUPT))
951 opregion_asle_intr(dev);
Keith Packard7c463582008-11-04 02:03:27 -0800952
Eric Anholtcdfbc412008-11-04 15:50:30 -0800953 /* With MSI, interrupts are only generated when iir
954 * transitions from zero to nonzero. If another bit got
955 * set while we were handling the existing iir bits, then
956 * we would never get another interrupt.
957 *
958 * This is fine on non-MSI as well, as if we hit this path
959 * we avoid exiting the interrupt handler only to generate
960 * another one.
961 *
962 * Note that for MSI this could cause a stray interrupt report
963 * if an interrupt landed in the time between writing IIR and
964 * the posting read. This should be rare enough to never
965 * trigger the 99% of 100,000 interrupts test for disabling
966 * stray interrupts.
967 */
968 iir = new_iir;
Keith Packard05eff842008-11-19 14:03:05 -0800969 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700970
Keith Packard05eff842008-11-19 14:03:05 -0800971 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972}
973
Dave Airlieaf6061a2008-05-07 12:15:39 +1000974static int i915_emit_irq(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975{
976 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000977 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978 RING_LOCALS;
979
980 i915_kernel_lost_context(dev);
981
Zhao Yakui44d98a62009-10-09 11:39:40 +0800982 DRM_DEBUG_DRIVER("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700983
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400984 dev_priv->counter++;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000985 if (dev_priv->counter > 0x7FFFFFFFUL)
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400986 dev_priv->counter = 1;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000987 if (master_priv->sarea_priv)
988 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000989
Keith Packard0baf8232008-11-08 11:44:14 +1000990 BEGIN_LP_RING(4);
Jesse Barnes585fb112008-07-29 11:54:06 -0700991 OUT_RING(MI_STORE_DWORD_INDEX);
Keith Packard0baf8232008-11-08 11:44:14 +1000992 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Alan Hourihanec29b6692006-08-12 16:29:24 +1000993 OUT_RING(dev_priv->counter);
Jesse Barnes585fb112008-07-29 11:54:06 -0700994 OUT_RING(MI_USER_INTERRUPT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995 ADVANCE_LP_RING();
Dave Airliebc5f4522007-11-05 12:50:58 +1000996
Alan Hourihanec29b6692006-08-12 16:29:24 +1000997 return dev_priv->counter;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998}
999
Eric Anholt673a3942008-07-30 12:06:12 -07001000void i915_user_irq_get(struct drm_device *dev)
Eric Anholted4cb412008-07-29 12:10:39 -07001001{
1002 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001003 unsigned long irqflags;
Eric Anholted4cb412008-07-29 12:10:39 -07001004
Keith Packarde9d21d72008-10-16 11:31:38 -07001005 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001006 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001007 if (HAS_PCH_SPLIT(dev))
Jesse Barnese552eb72010-04-21 11:39:23 -07001008 ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001009 else
1010 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1011 }
Keith Packarde9d21d72008-10-16 11:31:38 -07001012 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -07001013}
1014
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001015void i915_user_irq_put(struct drm_device *dev)
Eric Anholted4cb412008-07-29 12:10:39 -07001016{
1017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001018 unsigned long irqflags;
Eric Anholted4cb412008-07-29 12:10:39 -07001019
Keith Packarde9d21d72008-10-16 11:31:38 -07001020 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -07001021 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001022 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001023 if (HAS_PCH_SPLIT(dev))
Jesse Barnese552eb72010-04-21 11:39:23 -07001024 ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001025 else
1026 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1027 }
Keith Packarde9d21d72008-10-16 11:31:38 -07001028 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -07001029}
1030
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001031void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1032{
1033 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1034
1035 if (dev_priv->trace_irq_seqno == 0)
1036 i915_user_irq_get(dev);
1037
1038 dev_priv->trace_irq_seqno = seqno;
1039}
1040
Dave Airlie84b1fd12007-07-11 15:53:27 +10001041static int i915_wait_irq(struct drm_device * dev, int irq_nr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042{
1043 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001044 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045 int ret = 0;
1046
Zhao Yakui44d98a62009-10-09 11:39:40 +08001047 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 READ_BREADCRUMB(dev_priv));
1049
Eric Anholted4cb412008-07-29 12:10:39 -07001050 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
Dave Airlie7c1c2872008-11-28 14:22:24 +10001051 if (master_priv->sarea_priv)
1052 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053 return 0;
Eric Anholted4cb412008-07-29 12:10:39 -07001054 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055
Dave Airlie7c1c2872008-11-28 14:22:24 +10001056 if (master_priv->sarea_priv)
1057 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058
Eric Anholted4cb412008-07-29 12:10:39 -07001059 i915_user_irq_get(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1061 READ_BREADCRUMB(dev_priv) >= irq_nr);
Eric Anholted4cb412008-07-29 12:10:39 -07001062 i915_user_irq_put(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063
Eric Anholt20caafa2007-08-25 19:22:43 +10001064 if (ret == -EBUSY) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001065 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1067 }
1068
Dave Airlieaf6061a2008-05-07 12:15:39 +10001069 return ret;
1070}
1071
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072/* Needs the lock as it touches the ring.
1073 */
Eric Anholtc153f452007-09-03 12:06:45 +10001074int i915_irq_emit(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001078 drm_i915_irq_emit_t *emit = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079 int result;
1080
Eric Anholt07f4f8b2009-04-16 13:46:12 -07001081 if (!dev_priv || !dev_priv->ring.virtual_start) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001082 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001083 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084 }
Eric Anholt299eb932009-02-24 22:14:12 -08001085
1086 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1087
Eric Anholt546b0972008-09-01 16:45:29 -07001088 mutex_lock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 result = i915_emit_irq(dev);
Eric Anholt546b0972008-09-01 16:45:29 -07001090 mutex_unlock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091
Eric Anholtc153f452007-09-03 12:06:45 +10001092 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 DRM_ERROR("copy_to_user\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001094 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 }
1096
1097 return 0;
1098}
1099
1100/* Doesn't need the hardware lock.
1101 */
Eric Anholtc153f452007-09-03 12:06:45 +10001102int i915_irq_wait(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001106 drm_i915_irq_wait_t *irqwait = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107
1108 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001109 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001110 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 }
1112
Eric Anholtc153f452007-09-03 12:06:45 +10001113 return i915_wait_irq(dev, irqwait->irq_seq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114}
1115
Keith Packard42f52ef2008-10-18 19:39:29 -07001116/* Called from drm generic code, passed 'crtc' which
1117 * we use as a pipe index
1118 */
1119int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001120{
1121 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001122 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08001123 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1124 u32 pipeconf;
1125
1126 pipeconf = I915_READ(pipeconf_reg);
1127 if (!(pipeconf & PIPEACONF_ENABLE))
1128 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001129
Keith Packarde9d21d72008-10-16 11:31:38 -07001130 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholtbad720f2009-10-22 16:11:14 -07001131 if (HAS_PCH_SPLIT(dev))
Li Pengc062df62010-01-23 00:12:58 +08001132 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1133 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1134 else if (IS_I965G(dev))
Keith Packard7c463582008-11-04 02:03:27 -08001135 i915_enable_pipestat(dev_priv, pipe,
1136 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001137 else
Keith Packard7c463582008-11-04 02:03:27 -08001138 i915_enable_pipestat(dev_priv, pipe,
1139 PIPE_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001140 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001141 return 0;
1142}
1143
Keith Packard42f52ef2008-10-18 19:39:29 -07001144/* Called from drm generic code, passed 'crtc' which
1145 * we use as a pipe index
1146 */
1147void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001148{
1149 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001150 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001151
Keith Packarde9d21d72008-10-16 11:31:38 -07001152 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholtbad720f2009-10-22 16:11:14 -07001153 if (HAS_PCH_SPLIT(dev))
Li Pengc062df62010-01-23 00:12:58 +08001154 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1155 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1156 else
1157 i915_disable_pipestat(dev_priv, pipe,
1158 PIPE_VBLANK_INTERRUPT_ENABLE |
1159 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001160 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001161}
1162
Jesse Barnes79e53942008-11-07 14:24:08 -08001163void i915_enable_interrupt (struct drm_device *dev)
1164{
1165 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wange170b032009-06-05 15:38:40 +08001166
Eric Anholtbad720f2009-10-22 16:11:14 -07001167 if (!HAS_PCH_SPLIT(dev))
Zhenyu Wange170b032009-06-05 15:38:40 +08001168 opregion_enable_asle(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001169 dev_priv->irq_enabled = 1;
1170}
1171
1172
Dave Airlie702880f2006-06-24 17:07:34 +10001173/* Set the vblank monitor pipe
1174 */
Eric Anholtc153f452007-09-03 12:06:45 +10001175int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1176 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +10001177{
Dave Airlie702880f2006-06-24 17:07:34 +10001178 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie702880f2006-06-24 17:07:34 +10001179
1180 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001181 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001182 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +10001183 }
1184
=?utf-8?q?Michel_D=C3=A4nzer?=5b516942006-10-25 00:08:23 +10001185 return 0;
Dave Airlie702880f2006-06-24 17:07:34 +10001186}
1187
Eric Anholtc153f452007-09-03 12:06:45 +10001188int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1189 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +10001190{
Dave Airlie702880f2006-06-24 17:07:34 +10001191 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001192 drm_i915_vblank_pipe_t *pipe = data;
Dave Airlie702880f2006-06-24 17:07:34 +10001193
1194 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001195 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001196 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +10001197 }
1198
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001199 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Eric Anholtc153f452007-09-03 12:06:45 +10001200
Dave Airlie702880f2006-06-24 17:07:34 +10001201 return 0;
1202}
1203
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001204/**
1205 * Schedule buffer swap at given vertical blank.
1206 */
Eric Anholtc153f452007-09-03 12:06:45 +10001207int i915_vblank_swap(struct drm_device *dev, void *data,
1208 struct drm_file *file_priv)
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001209{
Eric Anholtbd95e0a2008-11-04 12:01:24 -08001210 /* The delayed swap mechanism was fundamentally racy, and has been
1211 * removed. The model was that the client requested a delayed flip/swap
1212 * from the kernel, then waited for vblank before continuing to perform
1213 * rendering. The problem was that the kernel might wake the client
1214 * up before it dispatched the vblank swap (since the lock has to be
1215 * held while touching the ringbuffer), in which case the client would
1216 * clear and start the next frame before the swap occurred, and
1217 * flicker would occur in addition to likely missing the vblank.
1218 *
1219 * In the absence of this ioctl, userland falls back to a correct path
1220 * of waiting for a vblank, then dispatching the swap on its own.
1221 * Context switching to userland and back is plenty fast enough for
1222 * meeting the requirements of vblank swapping.
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001223 */
Eric Anholtbd95e0a2008-11-04 12:01:24 -08001224 return -EINVAL;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +10001225}
1226
Ben Gamarif65d9422009-09-14 17:48:44 -04001227struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1228 drm_i915_private_t *dev_priv = dev->dev_private;
1229 return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1230}
1231
1232/**
1233 * This is called when the chip hasn't reported back with completed
1234 * batchbuffers in a long time. The first time this is called we simply record
1235 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1236 * again, we assume the chip is wedged and try to fix it.
1237 */
1238void i915_hangcheck_elapsed(unsigned long data)
1239{
1240 struct drm_device *dev = (struct drm_device *)data;
1241 drm_i915_private_t *dev_priv = dev->dev_private;
1242 uint32_t acthd;
Eric Anholtb9201c12010-01-08 14:25:16 -08001243
1244 /* No reset support on this chip yet. */
1245 if (IS_GEN6(dev))
1246 return;
1247
Ben Gamarif65d9422009-09-14 17:48:44 -04001248 if (!IS_I965G(dev))
1249 acthd = I915_READ(ACTHD);
1250 else
1251 acthd = I915_READ(ACTHD_I965);
1252
1253 /* If all work is done then ACTHD clearly hasn't advanced. */
1254 if (list_empty(&dev_priv->mm.request_list) ||
1255 i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1256 dev_priv->hangcheck_count = 0;
1257 return;
1258 }
1259
1260 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1261 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04001262 i915_handle_error(dev, true);
Ben Gamarif65d9422009-09-14 17:48:44 -04001263 return;
1264 }
1265
1266 /* Reset timer case chip hangs without another request being added */
1267 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1268
1269 if (acthd != dev_priv->last_acthd)
1270 dev_priv->hangcheck_count = 0;
1271 else
1272 dev_priv->hangcheck_count++;
1273
1274 dev_priv->last_acthd = acthd;
1275}
1276
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277/* drm_dma.h hooks
1278*/
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001279static void ironlake_irq_preinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001280{
1281 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1282
1283 I915_WRITE(HWSTAM, 0xeffe);
1284
1285 /* XXX hotplug from PCH */
1286
1287 I915_WRITE(DEIMR, 0xffffffff);
1288 I915_WRITE(DEIER, 0x0);
1289 (void) I915_READ(DEIER);
1290
1291 /* and GT */
1292 I915_WRITE(GTIMR, 0xffffffff);
1293 I915_WRITE(GTIER, 0x0);
1294 (void) I915_READ(GTIER);
Zhenyu Wangc6501562009-11-03 18:57:21 +00001295
1296 /* south display irq */
1297 I915_WRITE(SDEIMR, 0xffffffff);
1298 I915_WRITE(SDEIER, 0x0);
1299 (void) I915_READ(SDEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001300}
1301
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001302static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001303{
1304 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1305 /* enable kind of interrupts always enabled */
Jesse Barnes013d5aa2010-01-29 11:18:31 -08001306 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1307 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
Jesse Barnese552eb72010-04-21 11:39:23 -07001308 u32 render_mask = GT_PIPE_NOTIFY;
Zhenyu Wangc6501562009-11-03 18:57:21 +00001309 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1310 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001311
1312 dev_priv->irq_mask_reg = ~display_mask;
Li Peng643ced92010-01-28 01:05:09 +08001313 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001314
1315 /* should always can generate irq */
1316 I915_WRITE(DEIIR, I915_READ(DEIIR));
1317 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1318 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1319 (void) I915_READ(DEIER);
1320
1321 /* user interrupt should be enabled, but masked initial */
1322 dev_priv->gt_irq_mask_reg = 0xffffffff;
1323 dev_priv->gt_irq_enable_reg = render_mask;
1324
1325 I915_WRITE(GTIIR, I915_READ(GTIIR));
1326 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1327 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1328 (void) I915_READ(GTIER);
1329
Zhenyu Wangc6501562009-11-03 18:57:21 +00001330 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1331 dev_priv->pch_irq_enable_reg = hotplug_mask;
1332
1333 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1334 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1335 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1336 (void) I915_READ(SDEIER);
1337
Jesse Barnesf97108d2010-01-29 11:27:07 -08001338 if (IS_IRONLAKE_M(dev)) {
1339 /* Clear & enable PCU event interrupts */
1340 I915_WRITE(DEIIR, DE_PCU_EVENT);
1341 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1342 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1343 }
1344
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001345 return 0;
1346}
1347
Dave Airlie84b1fd12007-07-11 15:53:27 +10001348void i915_driver_irq_preinstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349{
1350 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1351
Jesse Barnes79e53942008-11-07 14:24:08 -08001352 atomic_set(&dev_priv->irq_received, 0);
1353
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001354 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Jesse Barnes8a905232009-07-11 16:48:03 -04001355 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001356
Eric Anholtbad720f2009-10-22 16:11:14 -07001357 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001358 ironlake_irq_preinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001359 return;
1360 }
1361
Jesse Barnes5ca58282009-03-31 14:11:15 -07001362 if (I915_HAS_HOTPLUG(dev)) {
1363 I915_WRITE(PORT_HOTPLUG_EN, 0);
1364 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1365 }
1366
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001367 I915_WRITE(HWSTAM, 0xeffe);
Keith Packard7c463582008-11-04 02:03:27 -08001368 I915_WRITE(PIPEASTAT, 0);
1369 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001370 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -07001371 I915_WRITE(IER, 0x0);
Keith Packard7c463582008-11-04 02:03:27 -08001372 (void) I915_READ(IER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373}
1374
Jesse Barnesb01f2c32009-12-11 11:07:17 -08001375/*
1376 * Must be called after intel_modeset_init or hotplug interrupts won't be
1377 * enabled correctly.
1378 */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001379int i915_driver_irq_postinstall(struct drm_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380{
1381 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes5ca58282009-03-31 14:11:15 -07001382 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001383 u32 error_mask;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001384
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001385 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1386
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001387 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001388
Eric Anholtbad720f2009-10-22 16:11:14 -07001389 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001390 return ironlake_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001391
Keith Packard7c463582008-11-04 02:03:27 -08001392 /* Unmask the interrupts that we always want on. */
1393 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001394
Keith Packard7c463582008-11-04 02:03:27 -08001395 dev_priv->pipestat[0] = 0;
1396 dev_priv->pipestat[1] = 0;
1397
Jesse Barnes5ca58282009-03-31 14:11:15 -07001398 if (I915_HAS_HOTPLUG(dev)) {
1399 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1400
Jesse Barnesb01f2c32009-12-11 11:07:17 -08001401 /* Note HDMI and DP share bits */
1402 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1403 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1404 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1405 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1406 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1407 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1408 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1409 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1410 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1411 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1412 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1413 hotplug_en |= CRT_HOTPLUG_INT_EN;
1414 /* Ignore TV since it's buggy */
1415
Jesse Barnes5ca58282009-03-31 14:11:15 -07001416 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1417
Jesse Barnes5ca58282009-03-31 14:11:15 -07001418 /* Enable in IER... */
1419 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1420 /* and unmask in IMR */
1421 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1422 }
1423
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001424 /*
1425 * Enable some error detection, note the instruction error mask
1426 * bit is reserved, so we leave it masked.
1427 */
1428 if (IS_G4X(dev)) {
1429 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1430 GM45_ERROR_MEM_PRIV |
1431 GM45_ERROR_CP_PRIV |
1432 I915_ERROR_MEMORY_REFRESH);
1433 } else {
1434 error_mask = ~(I915_ERROR_PAGE_TABLE |
1435 I915_ERROR_MEMORY_REFRESH);
1436 }
1437 I915_WRITE(EMR, error_mask);
1438
Keith Packard7c463582008-11-04 02:03:27 -08001439 /* Disable pipe interrupt enables, clear pending pipe status */
1440 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1441 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1442 /* Clear pending interrupt status */
1443 I915_WRITE(IIR, I915_READ(IIR));
1444
Jesse Barnes5ca58282009-03-31 14:11:15 -07001445 I915_WRITE(IER, enable_mask);
Keith Packard7c463582008-11-04 02:03:27 -08001446 I915_WRITE(IMR, dev_priv->irq_mask_reg);
Eric Anholted4cb412008-07-29 12:10:39 -07001447 (void) I915_READ(IER);
1448
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001449 opregion_enable_asle(dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001450
1451 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452}
1453
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001454static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001455{
1456 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1457 I915_WRITE(HWSTAM, 0xffffffff);
1458
1459 I915_WRITE(DEIMR, 0xffffffff);
1460 I915_WRITE(DEIER, 0x0);
1461 I915_WRITE(DEIIR, I915_READ(DEIIR));
1462
1463 I915_WRITE(GTIMR, 0xffffffff);
1464 I915_WRITE(GTIER, 0x0);
1465 I915_WRITE(GTIIR, I915_READ(GTIIR));
1466}
1467
Dave Airlie84b1fd12007-07-11 15:53:27 +10001468void i915_driver_irq_uninstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469{
1470 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie91e37382006-02-18 15:17:04 +11001471
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472 if (!dev_priv)
1473 return;
1474
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001475 dev_priv->vblank_pipe = 0;
1476
Eric Anholtbad720f2009-10-22 16:11:14 -07001477 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001478 ironlake_irq_uninstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001479 return;
1480 }
1481
Jesse Barnes5ca58282009-03-31 14:11:15 -07001482 if (I915_HAS_HOTPLUG(dev)) {
1483 I915_WRITE(PORT_HOTPLUG_EN, 0);
1484 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1485 }
1486
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001487 I915_WRITE(HWSTAM, 0xffffffff);
Keith Packard7c463582008-11-04 02:03:27 -08001488 I915_WRITE(PIPEASTAT, 0);
1489 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001490 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -07001491 I915_WRITE(IER, 0x0);
Dave Airlie91e37382006-02-18 15:17:04 +11001492
Keith Packard7c463582008-11-04 02:03:27 -08001493 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1494 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1495 I915_WRITE(IIR, I915_READ(IIR));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496}