Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 30 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 31 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 32 | #include <linux/export.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 35 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 37 | #include "i915_drv.h" |
| 38 | |
| 39 | #define DRM_I915_RING_DEBUG 1 |
| 40 | |
| 41 | |
| 42 | #if defined(CONFIG_DEBUG_FS) |
| 43 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 44 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 45 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 46 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 47 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 48 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 49 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 50 | static const char *yesno(int v) |
| 51 | { |
| 52 | return v ? "yes" : "no"; |
| 53 | } |
| 54 | |
| 55 | static int i915_capabilities(struct seq_file *m, void *data) |
| 56 | { |
| 57 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 58 | struct drm_device *dev = node->minor->dev; |
| 59 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 60 | |
| 61 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 63 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 64 | #define SEP_SEMICOLON ; |
| 65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 66 | #undef PRINT_FLAG |
| 67 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 68 | |
| 69 | return 0; |
| 70 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 71 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 72 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 73 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 74 | if (obj->user_pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 75 | return "P"; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 76 | else if (obj->pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 77 | return "p"; |
| 78 | else |
| 79 | return " "; |
| 80 | } |
| 81 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 82 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 83 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 84 | switch (obj->tiling_mode) { |
| 85 | default: |
| 86 | case I915_TILING_NONE: return " "; |
| 87 | case I915_TILING_X: return "X"; |
| 88 | case I915_TILING_Y: return "Y"; |
| 89 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 90 | } |
| 91 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 92 | static void |
| 93 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 94 | { |
Kees Cook | 2563a45 | 2013-03-11 12:25:19 -0700 | [diff] [blame] | 95 | seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 96 | &obj->base, |
| 97 | get_pin_flag(obj), |
| 98 | get_tiling_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 99 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 100 | obj->base.read_domains, |
| 101 | obj->base.write_domain, |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 102 | obj->last_read_seqno, |
| 103 | obj->last_write_seqno, |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 104 | obj->last_fenced_seqno, |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 105 | i915_cache_level_str(obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 106 | obj->dirty ? " dirty" : "", |
| 107 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 108 | if (obj->base.name) |
| 109 | seq_printf(m, " (name: %d)", obj->base.name); |
Chris Wilson | c110a6d | 2012-08-11 15:41:02 +0100 | [diff] [blame] | 110 | if (obj->pin_count) |
| 111 | seq_printf(m, " (pinned x %d)", obj->pin_count); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 112 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 113 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 114 | if (i915_gem_obj_ggtt_bound(obj)) |
| 115 | seq_printf(m, " (gtt offset: %08lx, size: %08x)", |
| 116 | i915_gem_obj_ggtt_offset(obj), (unsigned int)i915_gem_obj_ggtt_size(obj)); |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 117 | if (obj->stolen) |
| 118 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 119 | if (obj->pin_mappable || obj->fault_mappable) { |
| 120 | char s[3], *t = s; |
| 121 | if (obj->pin_mappable) |
| 122 | *t++ = 'p'; |
| 123 | if (obj->fault_mappable) |
| 124 | *t++ = 'f'; |
| 125 | *t = '\0'; |
| 126 | seq_printf(m, " (%s mappable)", s); |
| 127 | } |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 128 | if (obj->ring != NULL) |
| 129 | seq_printf(m, " (%s)", obj->ring->name); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 130 | } |
| 131 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 132 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 133 | { |
| 134 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 135 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 136 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 137 | struct drm_device *dev = node->minor->dev; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 138 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 139 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 140 | struct drm_i915_gem_object *obj; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 141 | size_t total_obj_size, total_gtt_size; |
| 142 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 143 | |
| 144 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 145 | if (ret) |
| 146 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 147 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 148 | switch (list) { |
| 149 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 150 | seq_puts(m, "Active:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 151 | head = &vm->active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 152 | break; |
| 153 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 154 | seq_puts(m, "Inactive:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 155 | head = &vm->inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 156 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 157 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 158 | mutex_unlock(&dev->struct_mutex); |
| 159 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 160 | } |
| 161 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 162 | total_obj_size = total_gtt_size = count = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 163 | list_for_each_entry(obj, head, mm_list) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 164 | seq_puts(m, " "); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 165 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 166 | seq_putc(m, '\n'); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 167 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 168 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 169 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 170 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 171 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 172 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 173 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 174 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 175 | return 0; |
| 176 | } |
| 177 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 178 | #define count_objects(list, member) do { \ |
| 179 | list_for_each_entry(obj, list, member) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 180 | size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 181 | ++count; \ |
| 182 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 183 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 184 | ++mappable_count; \ |
| 185 | } \ |
| 186 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 187 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 188 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 189 | struct file_stats { |
| 190 | int count; |
| 191 | size_t total, active, inactive, unbound; |
| 192 | }; |
| 193 | |
| 194 | static int per_file_stats(int id, void *ptr, void *data) |
| 195 | { |
| 196 | struct drm_i915_gem_object *obj = ptr; |
| 197 | struct file_stats *stats = data; |
| 198 | |
| 199 | stats->count++; |
| 200 | stats->total += obj->base.size; |
| 201 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 202 | if (i915_gem_obj_ggtt_bound(obj)) { |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 203 | if (!list_empty(&obj->ring_list)) |
| 204 | stats->active += obj->base.size; |
| 205 | else |
| 206 | stats->inactive += obj->base.size; |
| 207 | } else { |
| 208 | if (!list_empty(&obj->global_list)) |
| 209 | stats->unbound += obj->base.size; |
| 210 | } |
| 211 | |
| 212 | return 0; |
| 213 | } |
| 214 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 215 | static int i915_gem_object_info(struct seq_file *m, void *data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 216 | { |
| 217 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 218 | struct drm_device *dev = node->minor->dev; |
| 219 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 220 | u32 count, mappable_count, purgeable_count; |
| 221 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 222 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 223 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 224 | struct drm_file *file; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 225 | int ret; |
| 226 | |
| 227 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 228 | if (ret) |
| 229 | return ret; |
| 230 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 231 | seq_printf(m, "%u objects, %zu bytes\n", |
| 232 | dev_priv->mm.object_count, |
| 233 | dev_priv->mm.object_memory); |
| 234 | |
| 235 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 236 | count_objects(&dev_priv->mm.bound_list, global_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 237 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 238 | count, mappable_count, size, mappable_size); |
| 239 | |
| 240 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 241 | count_objects(&vm->active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 242 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 243 | count, mappable_count, size, mappable_size); |
| 244 | |
| 245 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 246 | count_objects(&vm->inactive_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 247 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 248 | count, mappable_count, size, mappable_size); |
| 249 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 250 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 251 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 252 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 253 | if (obj->madv == I915_MADV_DONTNEED) |
| 254 | purgeable_size += obj->base.size, ++purgeable_count; |
| 255 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 256 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 257 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 258 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 259 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 260 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 261 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 262 | ++count; |
| 263 | } |
| 264 | if (obj->pin_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 265 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 266 | ++mappable_count; |
| 267 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 268 | if (obj->madv == I915_MADV_DONTNEED) { |
| 269 | purgeable_size += obj->base.size; |
| 270 | ++purgeable_count; |
| 271 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 272 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 273 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 274 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 275 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 276 | mappable_count, mappable_size); |
| 277 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 278 | count, size); |
| 279 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 280 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 281 | dev_priv->gtt.base.total, |
| 282 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 283 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 284 | seq_putc(m, '\n'); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 285 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 286 | struct file_stats stats; |
| 287 | |
| 288 | memset(&stats, 0, sizeof(stats)); |
| 289 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
| 290 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", |
| 291 | get_pid_task(file->pid, PIDTYPE_PID)->comm, |
| 292 | stats.count, |
| 293 | stats.total, |
| 294 | stats.active, |
| 295 | stats.inactive, |
| 296 | stats.unbound); |
| 297 | } |
| 298 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 299 | mutex_unlock(&dev->struct_mutex); |
| 300 | |
| 301 | return 0; |
| 302 | } |
| 303 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 304 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 305 | { |
| 306 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 307 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 308 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 309 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 310 | struct drm_i915_gem_object *obj; |
| 311 | size_t total_obj_size, total_gtt_size; |
| 312 | int count, ret; |
| 313 | |
| 314 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 315 | if (ret) |
| 316 | return ret; |
| 317 | |
| 318 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 319 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 320 | if (list == PINNED_LIST && obj->pin_count == 0) |
| 321 | continue; |
| 322 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 323 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 324 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 325 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 326 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 327 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 328 | count++; |
| 329 | } |
| 330 | |
| 331 | mutex_unlock(&dev->struct_mutex); |
| 332 | |
| 333 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 334 | count, total_obj_size, total_gtt_size); |
| 335 | |
| 336 | return 0; |
| 337 | } |
| 338 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 339 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 340 | { |
| 341 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 342 | struct drm_device *dev = node->minor->dev; |
| 343 | unsigned long flags; |
| 344 | struct intel_crtc *crtc; |
| 345 | |
| 346 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 347 | const char pipe = pipe_name(crtc->pipe); |
| 348 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 349 | struct intel_unpin_work *work; |
| 350 | |
| 351 | spin_lock_irqsave(&dev->event_lock, flags); |
| 352 | work = crtc->unpin_work; |
| 353 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 354 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 355 | pipe, plane); |
| 356 | } else { |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 357 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 358 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 359 | pipe, plane); |
| 360 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 361 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 362 | pipe, plane); |
| 363 | } |
| 364 | if (work->enable_stall_check) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 365 | seq_puts(m, "Stall check enabled, "); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 366 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 367 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 368 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 369 | |
| 370 | if (work->old_fb_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 371 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
| 372 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 373 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
| 374 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 375 | } |
| 376 | if (work->pending_flip_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 377 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
| 378 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 379 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
| 380 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 381 | } |
| 382 | } |
| 383 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 384 | } |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 389 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 390 | { |
| 391 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 392 | struct drm_device *dev = node->minor->dev; |
| 393 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 394 | struct intel_ring_buffer *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 395 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 396 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 397 | |
| 398 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 399 | if (ret) |
| 400 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 401 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 402 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 403 | for_each_ring(ring, dev_priv, i) { |
| 404 | if (list_empty(&ring->request_list)) |
| 405 | continue; |
| 406 | |
| 407 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 408 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 409 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 410 | list) { |
| 411 | seq_printf(m, " %d @ %d\n", |
| 412 | gem_request->seqno, |
| 413 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 414 | } |
| 415 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 416 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 417 | mutex_unlock(&dev->struct_mutex); |
| 418 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 419 | if (count == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 420 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 421 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 422 | return 0; |
| 423 | } |
| 424 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 425 | static void i915_ring_seqno_info(struct seq_file *m, |
| 426 | struct intel_ring_buffer *ring) |
| 427 | { |
| 428 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 429 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 430 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 431 | } |
| 432 | } |
| 433 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 434 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 435 | { |
| 436 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 437 | struct drm_device *dev = node->minor->dev; |
| 438 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 439 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 440 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 441 | |
| 442 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 443 | if (ret) |
| 444 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 445 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 446 | for_each_ring(ring, dev_priv, i) |
| 447 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 448 | |
| 449 | mutex_unlock(&dev->struct_mutex); |
| 450 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | |
| 455 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 456 | { |
| 457 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 458 | struct drm_device *dev = node->minor->dev; |
| 459 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 460 | struct intel_ring_buffer *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 461 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 462 | |
| 463 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 464 | if (ret) |
| 465 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 466 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 467 | if (IS_VALLEYVIEW(dev)) { |
| 468 | seq_printf(m, "Display IER:\t%08x\n", |
| 469 | I915_READ(VLV_IER)); |
| 470 | seq_printf(m, "Display IIR:\t%08x\n", |
| 471 | I915_READ(VLV_IIR)); |
| 472 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 473 | I915_READ(VLV_IIR_RW)); |
| 474 | seq_printf(m, "Display IMR:\t%08x\n", |
| 475 | I915_READ(VLV_IMR)); |
| 476 | for_each_pipe(pipe) |
| 477 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 478 | pipe_name(pipe), |
| 479 | I915_READ(PIPESTAT(pipe))); |
| 480 | |
| 481 | seq_printf(m, "Master IER:\t%08x\n", |
| 482 | I915_READ(VLV_MASTER_IER)); |
| 483 | |
| 484 | seq_printf(m, "Render IER:\t%08x\n", |
| 485 | I915_READ(GTIER)); |
| 486 | seq_printf(m, "Render IIR:\t%08x\n", |
| 487 | I915_READ(GTIIR)); |
| 488 | seq_printf(m, "Render IMR:\t%08x\n", |
| 489 | I915_READ(GTIMR)); |
| 490 | |
| 491 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 492 | I915_READ(GEN6_PMIER)); |
| 493 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 494 | I915_READ(GEN6_PMIIR)); |
| 495 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 496 | I915_READ(GEN6_PMIMR)); |
| 497 | |
| 498 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 499 | I915_READ(PORT_HOTPLUG_EN)); |
| 500 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 501 | I915_READ(VLV_DPFLIPSTAT)); |
| 502 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 503 | I915_READ(DPINVGTT)); |
| 504 | |
| 505 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 506 | seq_printf(m, "Interrupt enable: %08x\n", |
| 507 | I915_READ(IER)); |
| 508 | seq_printf(m, "Interrupt identity: %08x\n", |
| 509 | I915_READ(IIR)); |
| 510 | seq_printf(m, "Interrupt mask: %08x\n", |
| 511 | I915_READ(IMR)); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 512 | for_each_pipe(pipe) |
| 513 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 514 | pipe_name(pipe), |
| 515 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 516 | } else { |
| 517 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 518 | I915_READ(DEIER)); |
| 519 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 520 | I915_READ(DEIIR)); |
| 521 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 522 | I915_READ(DEIMR)); |
| 523 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 524 | I915_READ(SDEIER)); |
| 525 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 526 | I915_READ(SDEIIR)); |
| 527 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 528 | I915_READ(SDEIMR)); |
| 529 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 530 | I915_READ(GTIER)); |
| 531 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 532 | I915_READ(GTIIR)); |
| 533 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 534 | I915_READ(GTIMR)); |
| 535 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 536 | seq_printf(m, "Interrupts received: %d\n", |
| 537 | atomic_read(&dev_priv->irq_received)); |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 538 | for_each_ring(ring, dev_priv, i) { |
Jesse Barnes | da64c6f | 2011-08-09 09:17:46 -0700 | [diff] [blame] | 539 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 540 | seq_printf(m, |
| 541 | "Graphics Interrupt mask (%s): %08x\n", |
| 542 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 543 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 544 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 545 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 546 | mutex_unlock(&dev->struct_mutex); |
| 547 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 548 | return 0; |
| 549 | } |
| 550 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 551 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 552 | { |
| 553 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 554 | struct drm_device *dev = node->minor->dev; |
| 555 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 556 | int i, ret; |
| 557 | |
| 558 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 559 | if (ret) |
| 560 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 561 | |
| 562 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 563 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 564 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 565 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 566 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 567 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 568 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 569 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 570 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 571 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 572 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 573 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 574 | } |
| 575 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 576 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 577 | return 0; |
| 578 | } |
| 579 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 580 | static int i915_hws_info(struct seq_file *m, void *data) |
| 581 | { |
| 582 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 583 | struct drm_device *dev = node->minor->dev; |
| 584 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 585 | struct intel_ring_buffer *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 586 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 587 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 588 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 589 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 590 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 591 | if (hws == NULL) |
| 592 | return 0; |
| 593 | |
| 594 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 595 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 596 | i * 4, |
| 597 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 598 | } |
| 599 | return 0; |
| 600 | } |
| 601 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 602 | static ssize_t |
| 603 | i915_error_state_write(struct file *filp, |
| 604 | const char __user *ubuf, |
| 605 | size_t cnt, |
| 606 | loff_t *ppos) |
| 607 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 608 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 609 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 610 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 611 | |
| 612 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 613 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 614 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 615 | if (ret) |
| 616 | return ret; |
| 617 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 618 | i915_destroy_error_state(dev); |
| 619 | mutex_unlock(&dev->struct_mutex); |
| 620 | |
| 621 | return cnt; |
| 622 | } |
| 623 | |
| 624 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 625 | { |
| 626 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 627 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 628 | |
| 629 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 630 | if (!error_priv) |
| 631 | return -ENOMEM; |
| 632 | |
| 633 | error_priv->dev = dev; |
| 634 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 635 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 636 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 637 | file->private_data = error_priv; |
| 638 | |
| 639 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 640 | } |
| 641 | |
| 642 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 643 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 644 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 645 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 646 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 647 | kfree(error_priv); |
| 648 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 653 | size_t count, loff_t *pos) |
| 654 | { |
| 655 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 656 | struct drm_i915_error_state_buf error_str; |
| 657 | loff_t tmp_pos = 0; |
| 658 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 659 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 660 | |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 661 | ret = i915_error_state_buf_init(&error_str, count, *pos); |
| 662 | if (ret) |
| 663 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 664 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 665 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 666 | if (ret) |
| 667 | goto out; |
| 668 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 669 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 670 | error_str.buf, |
| 671 | error_str.bytes); |
| 672 | |
| 673 | if (ret_count < 0) |
| 674 | ret = ret_count; |
| 675 | else |
| 676 | *pos = error_str.start + ret_count; |
| 677 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 678 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 679 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 680 | } |
| 681 | |
| 682 | static const struct file_operations i915_error_state_fops = { |
| 683 | .owner = THIS_MODULE, |
| 684 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 685 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 686 | .write = i915_error_state_write, |
| 687 | .llseek = default_llseek, |
| 688 | .release = i915_error_state_release, |
| 689 | }; |
| 690 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 691 | static int |
| 692 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 693 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 694 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 695 | drm_i915_private_t *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 696 | int ret; |
| 697 | |
| 698 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 699 | if (ret) |
| 700 | return ret; |
| 701 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 702 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 703 | mutex_unlock(&dev->struct_mutex); |
| 704 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 705 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 706 | } |
| 707 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 708 | static int |
| 709 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 710 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 711 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 712 | int ret; |
| 713 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 714 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 715 | if (ret) |
| 716 | return ret; |
| 717 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 718 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 719 | mutex_unlock(&dev->struct_mutex); |
| 720 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 721 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 722 | } |
| 723 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 724 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 725 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 726 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 727 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 728 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
| 729 | { |
| 730 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 731 | struct drm_device *dev = node->minor->dev; |
| 732 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 733 | u16 crstanddelay; |
| 734 | int ret; |
| 735 | |
| 736 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 737 | if (ret) |
| 738 | return ret; |
| 739 | |
| 740 | crstanddelay = I915_READ16(CRSTANDVID); |
| 741 | |
| 742 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 743 | |
| 744 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); |
| 745 | |
| 746 | return 0; |
| 747 | } |
| 748 | |
| 749 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) |
| 750 | { |
| 751 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 752 | struct drm_device *dev = node->minor->dev; |
| 753 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 754 | int ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 755 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 756 | if (IS_GEN5(dev)) { |
| 757 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 758 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 759 | |
| 760 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 761 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 762 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 763 | MEMSTAT_VID_SHIFT); |
| 764 | seq_printf(m, "Current P-state: %d\n", |
| 765 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 766 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 767 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 768 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 769 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 770 | u32 rpstat, cagf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 771 | u32 rpupei, rpcurup, rpprevup; |
| 772 | u32 rpdownei, rpcurdown, rpprevdown; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 773 | int max_freq; |
| 774 | |
| 775 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 776 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 777 | if (ret) |
| 778 | return ret; |
| 779 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 780 | gen6_gt_force_wake_get(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 781 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 782 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 783 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 784 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 785 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 786 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 787 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 788 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 789 | if (IS_HASWELL(dev)) |
| 790 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 791 | else |
| 792 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 793 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 794 | |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 795 | gen6_gt_force_wake_put(dev_priv); |
| 796 | mutex_unlock(&dev->struct_mutex); |
| 797 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 798 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 799 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 800 | seq_printf(m, "Render p-state ratio: %d\n", |
| 801 | (gt_perf_status & 0xff00) >> 8); |
| 802 | seq_printf(m, "Render p-state VID: %d\n", |
| 803 | gt_perf_status & 0xff); |
| 804 | seq_printf(m, "Render p-state limit: %d\n", |
| 805 | rp_state_limits & 0xff); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 806 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 807 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 808 | GEN6_CURICONT_MASK); |
| 809 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 810 | GEN6_CURBSYTAVG_MASK); |
| 811 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 812 | GEN6_CURBSYTAVG_MASK); |
| 813 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 814 | GEN6_CURIAVG_MASK); |
| 815 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 816 | GEN6_CURBSYTAVG_MASK); |
| 817 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 818 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 819 | |
| 820 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 821 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 822 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 823 | |
| 824 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 825 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 826 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 827 | |
| 828 | max_freq = rp_state_cap & 0xff; |
| 829 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 830 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 831 | |
| 832 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
| 833 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 834 | } else if (IS_VALLEYVIEW(dev)) { |
| 835 | u32 freq_sts, val; |
| 836 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 837 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 838 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 839 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 840 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 841 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 842 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 843 | seq_printf(m, "max GPU freq: %d MHz\n", |
| 844 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 845 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 846 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 847 | seq_printf(m, "min GPU freq: %d MHz\n", |
| 848 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 849 | |
| 850 | seq_printf(m, "current GPU freq: %d MHz\n", |
| 851 | vlv_gpu_freq(dev_priv->mem_freq, |
| 852 | (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 853 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 854 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 855 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 856 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 857 | |
| 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | static int i915_delayfreq_table(struct seq_file *m, void *unused) |
| 862 | { |
| 863 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 864 | struct drm_device *dev = node->minor->dev; |
| 865 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 866 | u32 delayfreq; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 867 | int ret, i; |
| 868 | |
| 869 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 870 | if (ret) |
| 871 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 872 | |
| 873 | for (i = 0; i < 16; i++) { |
| 874 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 875 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
| 876 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 877 | } |
| 878 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 879 | mutex_unlock(&dev->struct_mutex); |
| 880 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 881 | return 0; |
| 882 | } |
| 883 | |
| 884 | static inline int MAP_TO_MV(int map) |
| 885 | { |
| 886 | return 1250 - (map * 25); |
| 887 | } |
| 888 | |
| 889 | static int i915_inttoext_table(struct seq_file *m, void *unused) |
| 890 | { |
| 891 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 892 | struct drm_device *dev = node->minor->dev; |
| 893 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 894 | u32 inttoext; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 895 | int ret, i; |
| 896 | |
| 897 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 898 | if (ret) |
| 899 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 900 | |
| 901 | for (i = 1; i <= 32; i++) { |
| 902 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); |
| 903 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); |
| 904 | } |
| 905 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 906 | mutex_unlock(&dev->struct_mutex); |
| 907 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 908 | return 0; |
| 909 | } |
| 910 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 911 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 912 | { |
| 913 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 914 | struct drm_device *dev = node->minor->dev; |
| 915 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 916 | u32 rgvmodectl, rstdbyctl; |
| 917 | u16 crstandvid; |
| 918 | int ret; |
| 919 | |
| 920 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 921 | if (ret) |
| 922 | return ret; |
| 923 | |
| 924 | rgvmodectl = I915_READ(MEMMODECTL); |
| 925 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 926 | crstandvid = I915_READ16(CRSTANDVID); |
| 927 | |
| 928 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 929 | |
| 930 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 931 | "yes" : "no"); |
| 932 | seq_printf(m, "Boost freq: %d\n", |
| 933 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 934 | MEMMODE_BOOST_FREQ_SHIFT); |
| 935 | seq_printf(m, "HW control enabled: %s\n", |
| 936 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 937 | seq_printf(m, "SW control enabled: %s\n", |
| 938 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 939 | seq_printf(m, "Gated voltage change: %s\n", |
| 940 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 941 | seq_printf(m, "Starting frequency: P%d\n", |
| 942 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 943 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 944 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 945 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 946 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 947 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 948 | seq_printf(m, "Render standby enabled: %s\n", |
| 949 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 950 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 951 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 952 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 953 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 954 | break; |
| 955 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 956 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 957 | break; |
| 958 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 959 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 960 | break; |
| 961 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 962 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 963 | break; |
| 964 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 965 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 966 | break; |
| 967 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 968 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 969 | break; |
| 970 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 971 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 972 | break; |
| 973 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 974 | |
| 975 | return 0; |
| 976 | } |
| 977 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 978 | static int gen6_drpc_info(struct seq_file *m) |
| 979 | { |
| 980 | |
| 981 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 982 | struct drm_device *dev = node->minor->dev; |
| 983 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 984 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 985 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 986 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 987 | |
| 988 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 989 | if (ret) |
| 990 | return ret; |
| 991 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 992 | spin_lock_irq(&dev_priv->uncore.lock); |
| 993 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 994 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 995 | |
| 996 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 997 | seq_puts(m, "RC information inaccurate because somebody " |
| 998 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 999 | } else { |
| 1000 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1001 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1002 | udelay(10); |
| 1003 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1004 | } |
| 1005 | |
| 1006 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame^] | 1007 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1008 | |
| 1009 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1010 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1011 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1012 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1013 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1014 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1015 | |
| 1016 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1017 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1018 | seq_printf(m, "HW control enabled: %s\n", |
| 1019 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1020 | seq_printf(m, "SW control enabled: %s\n", |
| 1021 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1022 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1023 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1024 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1025 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1026 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1027 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1028 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1029 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1030 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1031 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1032 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1033 | case GEN6_RC0: |
| 1034 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1035 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1036 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1037 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1038 | break; |
| 1039 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1040 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1041 | break; |
| 1042 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1043 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1044 | break; |
| 1045 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1046 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1047 | break; |
| 1048 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1049 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1050 | break; |
| 1051 | } |
| 1052 | |
| 1053 | seq_printf(m, "Core Power Down: %s\n", |
| 1054 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1055 | |
| 1056 | /* Not exactly sure what this is */ |
| 1057 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1058 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1059 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1060 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1061 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1062 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1063 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1064 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1065 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1066 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1067 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1068 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1069 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1070 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1071 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1072 | return 0; |
| 1073 | } |
| 1074 | |
| 1075 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1076 | { |
| 1077 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1078 | struct drm_device *dev = node->minor->dev; |
| 1079 | |
| 1080 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 1081 | return gen6_drpc_info(m); |
| 1082 | else |
| 1083 | return ironlake_drpc_info(m); |
| 1084 | } |
| 1085 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1086 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1087 | { |
| 1088 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1089 | struct drm_device *dev = node->minor->dev; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1090 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1091 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1092 | if (!I915_HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1093 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1094 | return 0; |
| 1095 | } |
| 1096 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1097 | if (intel_fbc_enabled(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1098 | seq_puts(m, "FBC enabled\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1099 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1100 | seq_puts(m, "FBC disabled: "); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1101 | switch (dev_priv->fbc.no_fbc_reason) { |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1102 | case FBC_NO_OUTPUT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1103 | seq_puts(m, "no outputs"); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1104 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1105 | case FBC_STOLEN_TOO_SMALL: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1106 | seq_puts(m, "not enough stolen memory"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1107 | break; |
| 1108 | case FBC_UNSUPPORTED_MODE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1109 | seq_puts(m, "mode not supported"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1110 | break; |
| 1111 | case FBC_MODE_TOO_LARGE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1112 | seq_puts(m, "mode too large"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1113 | break; |
| 1114 | case FBC_BAD_PLANE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1115 | seq_puts(m, "FBC unsupported on plane"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1116 | break; |
| 1117 | case FBC_NOT_TILED: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1118 | seq_puts(m, "scanout buffer not tiled"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1119 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1120 | case FBC_MULTIPLE_PIPES: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1121 | seq_puts(m, "multiple pipes are enabled"); |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1122 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1123 | case FBC_MODULE_PARAM: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1124 | seq_puts(m, "disabled per module param (default off)"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1125 | break; |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1126 | case FBC_CHIP_DEFAULT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1127 | seq_puts(m, "disabled per chip default"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1128 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1129 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1130 | seq_puts(m, "unknown reason"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1131 | } |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1132 | seq_putc(m, '\n'); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1133 | } |
| 1134 | return 0; |
| 1135 | } |
| 1136 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1137 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1138 | { |
| 1139 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1140 | struct drm_device *dev = node->minor->dev; |
| 1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1142 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1143 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1144 | seq_puts(m, "not supported\n"); |
| 1145 | return 0; |
| 1146 | } |
| 1147 | |
| 1148 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1149 | seq_puts(m, "enabled\n"); |
| 1150 | else |
| 1151 | seq_puts(m, "disabled\n"); |
| 1152 | |
| 1153 | return 0; |
| 1154 | } |
| 1155 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1156 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1157 | { |
| 1158 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1159 | struct drm_device *dev = node->minor->dev; |
| 1160 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1161 | bool sr_enabled = false; |
| 1162 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1163 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1164 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1165 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1166 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1167 | else if (IS_I915GM(dev)) |
| 1168 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1169 | else if (IS_PINEVIEW(dev)) |
| 1170 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1171 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1172 | seq_printf(m, "self-refresh: %s\n", |
| 1173 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1174 | |
| 1175 | return 0; |
| 1176 | } |
| 1177 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1178 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1179 | { |
| 1180 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1181 | struct drm_device *dev = node->minor->dev; |
| 1182 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1183 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1184 | int ret; |
| 1185 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1186 | if (!IS_GEN5(dev)) |
| 1187 | return -ENODEV; |
| 1188 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1189 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1190 | if (ret) |
| 1191 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1192 | |
| 1193 | temp = i915_mch_val(dev_priv); |
| 1194 | chipset = i915_chipset_val(dev_priv); |
| 1195 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1196 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1197 | |
| 1198 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1199 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1200 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1201 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1202 | |
| 1203 | return 0; |
| 1204 | } |
| 1205 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1206 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1207 | { |
| 1208 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1209 | struct drm_device *dev = node->minor->dev; |
| 1210 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1211 | int ret; |
| 1212 | int gpu_freq, ia_freq; |
| 1213 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1214 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1215 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1216 | return 0; |
| 1217 | } |
| 1218 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1219 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1220 | if (ret) |
| 1221 | return ret; |
| 1222 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1223 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1224 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1225 | for (gpu_freq = dev_priv->rps.min_delay; |
| 1226 | gpu_freq <= dev_priv->rps.max_delay; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1227 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1228 | ia_freq = gpu_freq; |
| 1229 | sandybridge_pcode_read(dev_priv, |
| 1230 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1231 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1232 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1233 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1234 | ((ia_freq >> 0) & 0xff) * 100, |
| 1235 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1236 | } |
| 1237 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1238 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1239 | |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1243 | static int i915_gfxec(struct seq_file *m, void *unused) |
| 1244 | { |
| 1245 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1246 | struct drm_device *dev = node->minor->dev; |
| 1247 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1248 | int ret; |
| 1249 | |
| 1250 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1251 | if (ret) |
| 1252 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1253 | |
| 1254 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); |
| 1255 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1256 | mutex_unlock(&dev->struct_mutex); |
| 1257 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1258 | return 0; |
| 1259 | } |
| 1260 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1261 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1262 | { |
| 1263 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1264 | struct drm_device *dev = node->minor->dev; |
| 1265 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1266 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1267 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1268 | int ret; |
| 1269 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1270 | if (data == NULL) |
| 1271 | return -ENOMEM; |
| 1272 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1273 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1274 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1275 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1276 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1277 | if (opregion->header) { |
| 1278 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1279 | seq_write(m, data, OPREGION_SIZE); |
| 1280 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1281 | |
| 1282 | mutex_unlock(&dev->struct_mutex); |
| 1283 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1284 | out: |
| 1285 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1286 | return 0; |
| 1287 | } |
| 1288 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1289 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1290 | { |
| 1291 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1292 | struct drm_device *dev = node->minor->dev; |
| 1293 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1294 | struct intel_fbdev *ifbdev; |
| 1295 | struct intel_framebuffer *fb; |
| 1296 | int ret; |
| 1297 | |
| 1298 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
| 1299 | if (ret) |
| 1300 | return ret; |
| 1301 | |
| 1302 | ifbdev = dev_priv->fbdev; |
| 1303 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1304 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1305 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1306 | fb->base.width, |
| 1307 | fb->base.height, |
| 1308 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1309 | fb->base.bits_per_pixel, |
| 1310 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1311 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1312 | seq_putc(m, '\n'); |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1313 | mutex_unlock(&dev->mode_config.mutex); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1314 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1315 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1316 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
| 1317 | if (&fb->base == ifbdev->helper.fb) |
| 1318 | continue; |
| 1319 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1320 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1321 | fb->base.width, |
| 1322 | fb->base.height, |
| 1323 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1324 | fb->base.bits_per_pixel, |
| 1325 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1326 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1327 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1328 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1329 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1330 | |
| 1331 | return 0; |
| 1332 | } |
| 1333 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1334 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1335 | { |
| 1336 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1337 | struct drm_device *dev = node->minor->dev; |
| 1338 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1339 | struct intel_ring_buffer *ring; |
| 1340 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1341 | |
| 1342 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
| 1343 | if (ret) |
| 1344 | return ret; |
| 1345 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1346 | if (dev_priv->ips.pwrctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1347 | seq_puts(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1348 | describe_obj(m, dev_priv->ips.pwrctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1349 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1350 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1351 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1352 | if (dev_priv->ips.renderctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1353 | seq_puts(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1354 | describe_obj(m, dev_priv->ips.renderctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1355 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1356 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1357 | |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1358 | for_each_ring(ring, dev_priv, i) { |
| 1359 | if (ring->default_context) { |
| 1360 | seq_printf(m, "HW default context %s ring ", ring->name); |
| 1361 | describe_obj(m, ring->default_context->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1362 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1363 | } |
| 1364 | } |
| 1365 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1366 | mutex_unlock(&dev->mode_config.mutex); |
| 1367 | |
| 1368 | return 0; |
| 1369 | } |
| 1370 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1371 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
| 1372 | { |
| 1373 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1374 | struct drm_device *dev = node->minor->dev; |
| 1375 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1376 | unsigned forcewake_count; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1377 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1378 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1379 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1380 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1381 | |
| 1382 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1383 | |
| 1384 | return 0; |
| 1385 | } |
| 1386 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1387 | static const char *swizzle_string(unsigned swizzle) |
| 1388 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1389 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1390 | case I915_BIT_6_SWIZZLE_NONE: |
| 1391 | return "none"; |
| 1392 | case I915_BIT_6_SWIZZLE_9: |
| 1393 | return "bit9"; |
| 1394 | case I915_BIT_6_SWIZZLE_9_10: |
| 1395 | return "bit9/bit10"; |
| 1396 | case I915_BIT_6_SWIZZLE_9_11: |
| 1397 | return "bit9/bit11"; |
| 1398 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 1399 | return "bit9/bit10/bit11"; |
| 1400 | case I915_BIT_6_SWIZZLE_9_17: |
| 1401 | return "bit9/bit17"; |
| 1402 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 1403 | return "bit9/bit10/bit17"; |
| 1404 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 1405 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1406 | } |
| 1407 | |
| 1408 | return "bug"; |
| 1409 | } |
| 1410 | |
| 1411 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 1412 | { |
| 1413 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1414 | struct drm_device *dev = node->minor->dev; |
| 1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1416 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1417 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1418 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1419 | if (ret) |
| 1420 | return ret; |
| 1421 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1422 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 1423 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 1424 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 1425 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 1426 | |
| 1427 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 1428 | seq_printf(m, "DDC = 0x%08x\n", |
| 1429 | I915_READ(DCC)); |
| 1430 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 1431 | I915_READ16(C0DRB3)); |
| 1432 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 1433 | I915_READ16(C1DRB3)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1434 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1435 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 1436 | I915_READ(MAD_DIMM_C0)); |
| 1437 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 1438 | I915_READ(MAD_DIMM_C1)); |
| 1439 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 1440 | I915_READ(MAD_DIMM_C2)); |
| 1441 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 1442 | I915_READ(TILECTL)); |
| 1443 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 1444 | I915_READ(ARB_MODE)); |
| 1445 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 1446 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1447 | } |
| 1448 | mutex_unlock(&dev->struct_mutex); |
| 1449 | |
| 1450 | return 0; |
| 1451 | } |
| 1452 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1453 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 1454 | { |
| 1455 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1456 | struct drm_device *dev = node->minor->dev; |
| 1457 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1458 | struct intel_ring_buffer *ring; |
| 1459 | int i, ret; |
| 1460 | |
| 1461 | |
| 1462 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1463 | if (ret) |
| 1464 | return ret; |
| 1465 | if (INTEL_INFO(dev)->gen == 6) |
| 1466 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 1467 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 1468 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1469 | seq_printf(m, "%s\n", ring->name); |
| 1470 | if (INTEL_INFO(dev)->gen == 7) |
| 1471 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 1472 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 1473 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 1474 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 1475 | } |
| 1476 | if (dev_priv->mm.aliasing_ppgtt) { |
| 1477 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1478 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1479 | seq_puts(m, "aliasing PPGTT:\n"); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1480 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
| 1481 | } |
| 1482 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
| 1483 | mutex_unlock(&dev->struct_mutex); |
| 1484 | |
| 1485 | return 0; |
| 1486 | } |
| 1487 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1488 | static int i915_dpio_info(struct seq_file *m, void *data) |
| 1489 | { |
| 1490 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1491 | struct drm_device *dev = node->minor->dev; |
| 1492 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1493 | int ret; |
| 1494 | |
| 1495 | |
| 1496 | if (!IS_VALLEYVIEW(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1497 | seq_puts(m, "unsupported\n"); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1498 | return 0; |
| 1499 | } |
| 1500 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1501 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1502 | if (ret) |
| 1503 | return ret; |
| 1504 | |
| 1505 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); |
| 1506 | |
| 1507 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1508 | vlv_dpio_read(dev_priv, _DPIO_DIV_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1509 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1510 | vlv_dpio_read(dev_priv, _DPIO_DIV_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1511 | |
| 1512 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1513 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1514 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1515 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1516 | |
| 1517 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1518 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1519 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1520 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1521 | |
Ville Syrjälä | 4abb2c3 | 2013-06-14 14:02:53 +0300 | [diff] [blame] | 1522 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
| 1523 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); |
| 1524 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
| 1525 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1526 | |
| 1527 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1528 | vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1529 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1530 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1531 | |
| 1532 | return 0; |
| 1533 | } |
| 1534 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 1535 | static int i915_llc(struct seq_file *m, void *data) |
| 1536 | { |
| 1537 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1538 | struct drm_device *dev = node->minor->dev; |
| 1539 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1540 | |
| 1541 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ |
| 1542 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
| 1543 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); |
| 1544 | |
| 1545 | return 0; |
| 1546 | } |
| 1547 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1548 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 1549 | { |
| 1550 | struct drm_info_node *node = m->private; |
| 1551 | struct drm_device *dev = node->minor->dev; |
| 1552 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1553 | u32 psrstat, psrperf; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1554 | |
| 1555 | if (!IS_HASWELL(dev)) { |
| 1556 | seq_puts(m, "PSR not supported on this platform\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1557 | } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) { |
| 1558 | seq_puts(m, "PSR enabled\n"); |
| 1559 | } else { |
| 1560 | seq_puts(m, "PSR disabled: "); |
| 1561 | switch (dev_priv->no_psr_reason) { |
| 1562 | case PSR_NO_SOURCE: |
| 1563 | seq_puts(m, "not supported on this platform"); |
| 1564 | break; |
| 1565 | case PSR_NO_SINK: |
| 1566 | seq_puts(m, "not supported by panel"); |
| 1567 | break; |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1568 | case PSR_MODULE_PARAM: |
| 1569 | seq_puts(m, "disabled by flag"); |
| 1570 | break; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1571 | case PSR_CRTC_NOT_ACTIVE: |
| 1572 | seq_puts(m, "crtc not active"); |
| 1573 | break; |
| 1574 | case PSR_PWR_WELL_ENABLED: |
| 1575 | seq_puts(m, "power well enabled"); |
| 1576 | break; |
| 1577 | case PSR_NOT_TILED: |
| 1578 | seq_puts(m, "not tiled"); |
| 1579 | break; |
| 1580 | case PSR_SPRITE_ENABLED: |
| 1581 | seq_puts(m, "sprite enabled"); |
| 1582 | break; |
| 1583 | case PSR_S3D_ENABLED: |
| 1584 | seq_puts(m, "stereo 3d enabled"); |
| 1585 | break; |
| 1586 | case PSR_INTERLACED_ENABLED: |
| 1587 | seq_puts(m, "interlaced enabled"); |
| 1588 | break; |
| 1589 | case PSR_HSW_NOT_DDIA: |
| 1590 | seq_puts(m, "HSW ties PSR to DDI A (eDP)"); |
| 1591 | break; |
| 1592 | default: |
| 1593 | seq_puts(m, "unknown reason"); |
| 1594 | } |
| 1595 | seq_puts(m, "\n"); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1596 | return 0; |
| 1597 | } |
| 1598 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1599 | psrstat = I915_READ(EDP_PSR_STATUS_CTL); |
| 1600 | |
| 1601 | seq_puts(m, "PSR Current State: "); |
| 1602 | switch (psrstat & EDP_PSR_STATUS_STATE_MASK) { |
| 1603 | case EDP_PSR_STATUS_STATE_IDLE: |
| 1604 | seq_puts(m, "Reset state\n"); |
| 1605 | break; |
| 1606 | case EDP_PSR_STATUS_STATE_SRDONACK: |
| 1607 | seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n"); |
| 1608 | break; |
| 1609 | case EDP_PSR_STATUS_STATE_SRDENT: |
| 1610 | seq_puts(m, "SRD entry\n"); |
| 1611 | break; |
| 1612 | case EDP_PSR_STATUS_STATE_BUFOFF: |
| 1613 | seq_puts(m, "Wait for buffer turn off\n"); |
| 1614 | break; |
| 1615 | case EDP_PSR_STATUS_STATE_BUFON: |
| 1616 | seq_puts(m, "Wait for buffer turn on\n"); |
| 1617 | break; |
| 1618 | case EDP_PSR_STATUS_STATE_AUXACK: |
| 1619 | seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n"); |
| 1620 | break; |
| 1621 | case EDP_PSR_STATUS_STATE_SRDOFFACK: |
| 1622 | seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n"); |
| 1623 | break; |
| 1624 | default: |
| 1625 | seq_puts(m, "Unknown\n"); |
| 1626 | break; |
| 1627 | } |
| 1628 | |
| 1629 | seq_puts(m, "Link Status: "); |
| 1630 | switch (psrstat & EDP_PSR_STATUS_LINK_MASK) { |
| 1631 | case EDP_PSR_STATUS_LINK_FULL_OFF: |
| 1632 | seq_puts(m, "Link is fully off\n"); |
| 1633 | break; |
| 1634 | case EDP_PSR_STATUS_LINK_FULL_ON: |
| 1635 | seq_puts(m, "Link is fully on\n"); |
| 1636 | break; |
| 1637 | case EDP_PSR_STATUS_LINK_STANDBY: |
| 1638 | seq_puts(m, "Link is in standby\n"); |
| 1639 | break; |
| 1640 | default: |
| 1641 | seq_puts(m, "Unknown\n"); |
| 1642 | break; |
| 1643 | } |
| 1644 | |
| 1645 | seq_printf(m, "PSR Entry Count: %u\n", |
| 1646 | psrstat >> EDP_PSR_STATUS_COUNT_SHIFT & |
| 1647 | EDP_PSR_STATUS_COUNT_MASK); |
| 1648 | |
| 1649 | seq_printf(m, "Max Sleep Timer Counter: %u\n", |
| 1650 | psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT & |
| 1651 | EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK); |
| 1652 | |
| 1653 | seq_printf(m, "Had AUX error: %s\n", |
| 1654 | yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR)); |
| 1655 | |
| 1656 | seq_printf(m, "Sending AUX: %s\n", |
| 1657 | yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING)); |
| 1658 | |
| 1659 | seq_printf(m, "Sending Idle: %s\n", |
| 1660 | yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE)); |
| 1661 | |
| 1662 | seq_printf(m, "Sending TP2 TP3: %s\n", |
| 1663 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3)); |
| 1664 | |
| 1665 | seq_printf(m, "Sending TP1: %s\n", |
| 1666 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1)); |
| 1667 | |
| 1668 | seq_printf(m, "Idle Count: %u\n", |
| 1669 | psrstat & EDP_PSR_STATUS_IDLE_MASK); |
| 1670 | |
| 1671 | psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK; |
| 1672 | seq_printf(m, "Performance Counter: %u\n", psrperf); |
| 1673 | |
| 1674 | return 0; |
| 1675 | } |
| 1676 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1677 | static int |
| 1678 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1679 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1680 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1681 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1682 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1683 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1684 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1685 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1686 | } |
| 1687 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1688 | static int |
| 1689 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1690 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1691 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1692 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1693 | DRM_INFO("Manually setting wedged to %llu\n", val); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1694 | i915_handle_error(dev, val); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1695 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1696 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1697 | } |
| 1698 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1699 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 1700 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1701 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1702 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1703 | static int |
| 1704 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1705 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1706 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1707 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1708 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1709 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1710 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1711 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1712 | } |
| 1713 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1714 | static int |
| 1715 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1716 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1717 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1718 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1719 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1720 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1721 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1722 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1723 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1724 | if (ret) |
| 1725 | return ret; |
| 1726 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1727 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1728 | mutex_unlock(&dev->struct_mutex); |
| 1729 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1730 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1731 | } |
| 1732 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1733 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 1734 | i915_ring_stop_get, i915_ring_stop_set, |
| 1735 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1736 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1737 | #define DROP_UNBOUND 0x1 |
| 1738 | #define DROP_BOUND 0x2 |
| 1739 | #define DROP_RETIRE 0x4 |
| 1740 | #define DROP_ACTIVE 0x8 |
| 1741 | #define DROP_ALL (DROP_UNBOUND | \ |
| 1742 | DROP_BOUND | \ |
| 1743 | DROP_RETIRE | \ |
| 1744 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1745 | static int |
| 1746 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1747 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1748 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1749 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1750 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1751 | } |
| 1752 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1753 | static int |
| 1754 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1755 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1756 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1757 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1758 | struct drm_i915_gem_object *obj, *next; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 1759 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1760 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1761 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1762 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1763 | |
| 1764 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 1765 | * on ioctls on -EAGAIN. */ |
| 1766 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1767 | if (ret) |
| 1768 | return ret; |
| 1769 | |
| 1770 | if (val & DROP_ACTIVE) { |
| 1771 | ret = i915_gpu_idle(dev); |
| 1772 | if (ret) |
| 1773 | goto unlock; |
| 1774 | } |
| 1775 | |
| 1776 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 1777 | i915_gem_retire_requests(dev); |
| 1778 | |
| 1779 | if (val & DROP_BOUND) { |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 1780 | list_for_each_entry_safe(obj, next, &vm->inactive_list, |
| 1781 | mm_list) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1782 | if (obj->pin_count == 0) { |
| 1783 | ret = i915_gem_object_unbind(obj); |
| 1784 | if (ret) |
| 1785 | goto unlock; |
| 1786 | } |
| 1787 | } |
| 1788 | |
| 1789 | if (val & DROP_UNBOUND) { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1790 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
| 1791 | global_list) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1792 | if (obj->pages_pin_count == 0) { |
| 1793 | ret = i915_gem_object_put_pages(obj); |
| 1794 | if (ret) |
| 1795 | goto unlock; |
| 1796 | } |
| 1797 | } |
| 1798 | |
| 1799 | unlock: |
| 1800 | mutex_unlock(&dev->struct_mutex); |
| 1801 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1802 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1803 | } |
| 1804 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1805 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 1806 | i915_drop_caches_get, i915_drop_caches_set, |
| 1807 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1808 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1809 | static int |
| 1810 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1811 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1812 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1813 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1814 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1815 | |
| 1816 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1817 | return -ENODEV; |
| 1818 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1819 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1820 | if (ret) |
| 1821 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1822 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1823 | if (IS_VALLEYVIEW(dev)) |
| 1824 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 1825 | dev_priv->rps.max_delay); |
| 1826 | else |
| 1827 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1828 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1829 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1830 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1831 | } |
| 1832 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1833 | static int |
| 1834 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1835 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1836 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1837 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1838 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1839 | |
| 1840 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1841 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1842 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1843 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1844 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1845 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1846 | if (ret) |
| 1847 | return ret; |
| 1848 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1849 | /* |
| 1850 | * Turbo will still be enabled, but won't go above the set value. |
| 1851 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1852 | if (IS_VALLEYVIEW(dev)) { |
| 1853 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 1854 | dev_priv->rps.max_delay = val; |
| 1855 | gen6_set_rps(dev, val); |
| 1856 | } else { |
| 1857 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 1858 | dev_priv->rps.max_delay = val; |
| 1859 | gen6_set_rps(dev, val); |
| 1860 | } |
| 1861 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1862 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1863 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1864 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1865 | } |
| 1866 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1867 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 1868 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1869 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1870 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1871 | static int |
| 1872 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1873 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1874 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1875 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1876 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1877 | |
| 1878 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1879 | return -ENODEV; |
| 1880 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1881 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1882 | if (ret) |
| 1883 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1884 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1885 | if (IS_VALLEYVIEW(dev)) |
| 1886 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 1887 | dev_priv->rps.min_delay); |
| 1888 | else |
| 1889 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1890 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1891 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1892 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1893 | } |
| 1894 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1895 | static int |
| 1896 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1897 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1898 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1899 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1900 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1901 | |
| 1902 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1903 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1904 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1905 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1906 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1907 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1908 | if (ret) |
| 1909 | return ret; |
| 1910 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1911 | /* |
| 1912 | * Turbo will still be enabled, but won't go below the set value. |
| 1913 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1914 | if (IS_VALLEYVIEW(dev)) { |
| 1915 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 1916 | dev_priv->rps.min_delay = val; |
| 1917 | valleyview_set_rps(dev, val); |
| 1918 | } else { |
| 1919 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 1920 | dev_priv->rps.min_delay = val; |
| 1921 | gen6_set_rps(dev, val); |
| 1922 | } |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1923 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1924 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1925 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1926 | } |
| 1927 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1928 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 1929 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1930 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 1931 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1932 | static int |
| 1933 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1934 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1935 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1936 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1937 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1938 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1939 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1940 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1941 | return -ENODEV; |
| 1942 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1943 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1944 | if (ret) |
| 1945 | return ret; |
| 1946 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1947 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 1948 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 1949 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1950 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1951 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1952 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1953 | } |
| 1954 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1955 | static int |
| 1956 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1957 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1958 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1959 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1960 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1961 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1962 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1963 | return -ENODEV; |
| 1964 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1965 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1966 | return -EINVAL; |
| 1967 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1968 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1969 | |
| 1970 | /* Update the cache sharing policy here as well */ |
| 1971 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 1972 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 1973 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 1974 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 1975 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1976 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1977 | } |
| 1978 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1979 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 1980 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 1981 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 1982 | |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1983 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 1984 | * allocated we need to hook into the minor for release. */ |
| 1985 | static int |
| 1986 | drm_add_fake_info_node(struct drm_minor *minor, |
| 1987 | struct dentry *ent, |
| 1988 | const void *key) |
| 1989 | { |
| 1990 | struct drm_info_node *node; |
| 1991 | |
| 1992 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); |
| 1993 | if (node == NULL) { |
| 1994 | debugfs_remove(ent); |
| 1995 | return -ENOMEM; |
| 1996 | } |
| 1997 | |
| 1998 | node->minor = minor; |
| 1999 | node->dent = ent; |
| 2000 | node->info_ent = (void *) key; |
Marcin Slusarz | b3e067c | 2011-11-09 22:20:35 +0100 | [diff] [blame] | 2001 | |
| 2002 | mutex_lock(&minor->debugfs_lock); |
| 2003 | list_add(&node->list, &minor->debugfs_list); |
| 2004 | mutex_unlock(&minor->debugfs_lock); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2005 | |
| 2006 | return 0; |
| 2007 | } |
| 2008 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2009 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 2010 | { |
| 2011 | struct drm_device *dev = inode->i_private; |
| 2012 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2013 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2014 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2015 | return 0; |
| 2016 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2017 | gen6_gt_force_wake_get(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2018 | |
| 2019 | return 0; |
| 2020 | } |
| 2021 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2022 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2023 | { |
| 2024 | struct drm_device *dev = inode->i_private; |
| 2025 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2026 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2027 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2028 | return 0; |
| 2029 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2030 | gen6_gt_force_wake_put(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2031 | |
| 2032 | return 0; |
| 2033 | } |
| 2034 | |
| 2035 | static const struct file_operations i915_forcewake_fops = { |
| 2036 | .owner = THIS_MODULE, |
| 2037 | .open = i915_forcewake_open, |
| 2038 | .release = i915_forcewake_release, |
| 2039 | }; |
| 2040 | |
| 2041 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 2042 | { |
| 2043 | struct drm_device *dev = minor->dev; |
| 2044 | struct dentry *ent; |
| 2045 | |
| 2046 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2047 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2048 | root, dev, |
| 2049 | &i915_forcewake_fops); |
| 2050 | if (IS_ERR(ent)) |
| 2051 | return PTR_ERR(ent); |
| 2052 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2053 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2054 | } |
| 2055 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2056 | static int i915_debugfs_create(struct dentry *root, |
| 2057 | struct drm_minor *minor, |
| 2058 | const char *name, |
| 2059 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2060 | { |
| 2061 | struct drm_device *dev = minor->dev; |
| 2062 | struct dentry *ent; |
| 2063 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2064 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2065 | S_IRUGO | S_IWUSR, |
| 2066 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2067 | fops); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2068 | if (IS_ERR(ent)) |
| 2069 | return PTR_ERR(ent); |
| 2070 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2071 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2072 | } |
| 2073 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2074 | static struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 2075 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2076 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 2077 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 2078 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 2079 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 2080 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2081 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2082 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 2083 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 2084 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2085 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2086 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 2087 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 2088 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 2089 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2090 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
| 2091 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, |
| 2092 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, |
| 2093 | {"i915_inttoext_table", i915_inttoext_table, 0}, |
| 2094 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2095 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 2096 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2097 | {"i915_gfxec", i915_gfxec, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 2098 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 2099 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 2100 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2101 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 2102 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 2103 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2104 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2105 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2106 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 2107 | {"i915_dpio", i915_dpio_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2108 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2109 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2110 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2111 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2112 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2113 | struct i915_debugfs_files { |
| 2114 | const char *name; |
| 2115 | const struct file_operations *fops; |
| 2116 | } i915_debugfs_files[] = { |
| 2117 | {"i915_wedged", &i915_wedged_fops}, |
| 2118 | {"i915_max_freq", &i915_max_freq_fops}, |
| 2119 | {"i915_min_freq", &i915_min_freq_fops}, |
| 2120 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 2121 | {"i915_ring_stop", &i915_ring_stop_fops}, |
| 2122 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 2123 | {"i915_error_state", &i915_error_state_fops}, |
| 2124 | {"i915_next_seqno", &i915_next_seqno_fops}, |
| 2125 | }; |
| 2126 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2127 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2128 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2129 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2130 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2131 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 2132 | if (ret) |
| 2133 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2134 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2135 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 2136 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 2137 | i915_debugfs_files[i].name, |
| 2138 | i915_debugfs_files[i].fops); |
| 2139 | if (ret) |
| 2140 | return ret; |
| 2141 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 2142 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2143 | return drm_debugfs_create_files(i915_debugfs_list, |
| 2144 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2145 | minor->debugfs_root, minor); |
| 2146 | } |
| 2147 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2148 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2149 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2150 | int i; |
| 2151 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2152 | drm_debugfs_remove_files(i915_debugfs_list, |
| 2153 | I915_DEBUGFS_ENTRIES, minor); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2154 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 2155 | 1, minor); |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 2156 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 2157 | struct drm_info_list *info_list = |
| 2158 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 2159 | |
| 2160 | drm_debugfs_remove_files(info_list, 1, minor); |
| 2161 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2162 | } |
| 2163 | |
| 2164 | #endif /* CONFIG_DEBUG_FS */ |