blob: ed72fe08217c7ce62ae0f7d7642c7d6661dfb5f7 [file] [log] [blame]
Ben Gamari20172632009-02-17 20:08:50 -05001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
Chris Wilsonf3cd4742009-10-13 22:20:20 +010030#include <linux/debugfs.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040032#include <linux/export.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
Simon Farnsworth4e5359c2010-09-01 17:47:52 +010034#include "intel_drv.h"
Chris Wilsone5c65262010-11-01 11:35:28 +000035#include "intel_ringbuffer.h"
David Howells760285e2012-10-02 18:01:07 +010036#include <drm/i915_drm.h>
Ben Gamari20172632009-02-17 20:08:50 -050037#include "i915_drv.h"
38
39#define DRM_I915_RING_DEBUG 1
40
41
42#if defined(CONFIG_DEBUG_FS)
43
Chris Wilsonf13d3f72010-09-20 17:36:15 +010044enum {
Chris Wilson69dc4982010-10-19 10:36:51 +010045 ACTIVE_LIST,
Chris Wilsonf13d3f72010-09-20 17:36:15 +010046 INACTIVE_LIST,
Chris Wilsond21d5972010-09-26 11:19:33 +010047 PINNED_LIST,
Chris Wilsonf13d3f72010-09-20 17:36:15 +010048};
Ben Gamari433e12f2009-02-17 20:08:51 -050049
Chris Wilson70d39fe2010-08-25 16:03:34 +010050static const char *yesno(int v)
51{
52 return v ? "yes" : "no";
53}
54
55static int i915_capabilities(struct seq_file *m, void *data)
56{
57 struct drm_info_node *node = (struct drm_info_node *) m->private;
58 struct drm_device *dev = node->minor->dev;
59 const struct intel_device_info *info = INTEL_INFO(dev);
60
61 seq_printf(m, "gen: %d\n", info->gen);
Paulo Zanoni03d00ac2011-10-14 18:17:41 -030062 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
Damien Lespiau79fc46d2013-04-23 16:37:17 +010063#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
64#define SEP_SEMICOLON ;
65 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
66#undef PRINT_FLAG
67#undef SEP_SEMICOLON
Chris Wilson70d39fe2010-08-25 16:03:34 +010068
69 return 0;
70}
Ben Gamari433e12f2009-02-17 20:08:51 -050071
Chris Wilson05394f32010-11-08 19:18:58 +000072static const char *get_pin_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +000073{
Chris Wilson05394f32010-11-08 19:18:58 +000074 if (obj->user_pin_count > 0)
Chris Wilsona6172a82009-02-11 14:26:38 +000075 return "P";
Chris Wilson05394f32010-11-08 19:18:58 +000076 else if (obj->pin_count > 0)
Chris Wilsona6172a82009-02-11 14:26:38 +000077 return "p";
78 else
79 return " ";
80}
81
Chris Wilson05394f32010-11-08 19:18:58 +000082static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +000083{
Akshay Joshi0206e352011-08-16 15:34:10 -040084 switch (obj->tiling_mode) {
85 default:
86 case I915_TILING_NONE: return " ";
87 case I915_TILING_X: return "X";
88 case I915_TILING_Y: return "Y";
89 }
Chris Wilsona6172a82009-02-11 14:26:38 +000090}
91
Chris Wilson37811fc2010-08-25 22:45:57 +010092static void
93describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
94{
Kees Cook2563a452013-03-11 12:25:19 -070095 seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
Chris Wilson37811fc2010-08-25 22:45:57 +010096 &obj->base,
97 get_pin_flag(obj),
98 get_tiling_flag(obj),
Eric Anholta05a5862011-12-20 08:54:15 -080099 obj->base.size / 1024,
Chris Wilson37811fc2010-08-25 22:45:57 +0100100 obj->base.read_domains,
101 obj->base.write_domain,
Chris Wilson0201f1e2012-07-20 12:41:01 +0100102 obj->last_read_seqno,
103 obj->last_write_seqno,
Chris Wilsoncaea7472010-11-12 13:53:37 +0000104 obj->last_fenced_seqno,
Mika Kuoppala84734a02013-07-12 16:50:57 +0300105 i915_cache_level_str(obj->cache_level),
Chris Wilson37811fc2010-08-25 22:45:57 +0100106 obj->dirty ? " dirty" : "",
107 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
108 if (obj->base.name)
109 seq_printf(m, " (name: %d)", obj->base.name);
Chris Wilsonc110a6d2012-08-11 15:41:02 +0100110 if (obj->pin_count)
111 seq_printf(m, " (pinned x %d)", obj->pin_count);
Chris Wilson37811fc2010-08-25 22:45:57 +0100112 if (obj->fence_reg != I915_FENCE_REG_NONE)
113 seq_printf(m, " (fence: %d)", obj->fence_reg);
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700114 if (i915_gem_obj_ggtt_bound(obj))
115 seq_printf(m, " (gtt offset: %08lx, size: %08x)",
116 i915_gem_obj_ggtt_offset(obj), (unsigned int)i915_gem_obj_ggtt_size(obj));
Chris Wilsonc1ad11f2012-11-15 11:32:21 +0000117 if (obj->stolen)
118 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
Chris Wilson6299f992010-11-24 12:23:44 +0000119 if (obj->pin_mappable || obj->fault_mappable) {
120 char s[3], *t = s;
121 if (obj->pin_mappable)
122 *t++ = 'p';
123 if (obj->fault_mappable)
124 *t++ = 'f';
125 *t = '\0';
126 seq_printf(m, " (%s mappable)", s);
127 }
Chris Wilson69dc4982010-10-19 10:36:51 +0100128 if (obj->ring != NULL)
129 seq_printf(m, " (%s)", obj->ring->name);
Chris Wilson37811fc2010-08-25 22:45:57 +0100130}
131
Ben Gamari433e12f2009-02-17 20:08:51 -0500132static int i915_gem_object_list_info(struct seq_file *m, void *data)
Ben Gamari20172632009-02-17 20:08:50 -0500133{
134 struct drm_info_node *node = (struct drm_info_node *) m->private;
Ben Gamari433e12f2009-02-17 20:08:51 -0500135 uintptr_t list = (uintptr_t) node->info_ent->data;
136 struct list_head *head;
Ben Gamari20172632009-02-17 20:08:50 -0500137 struct drm_device *dev = node->minor->dev;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700138 struct drm_i915_private *dev_priv = dev->dev_private;
139 struct i915_address_space *vm = &dev_priv->gtt.base;
Chris Wilson05394f32010-11-08 19:18:58 +0000140 struct drm_i915_gem_object *obj;
Chris Wilson8f2480f2010-09-26 11:44:19 +0100141 size_t total_obj_size, total_gtt_size;
142 int count, ret;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100143
144 ret = mutex_lock_interruptible(&dev->struct_mutex);
145 if (ret)
146 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500147
Ben Gamari433e12f2009-02-17 20:08:51 -0500148 switch (list) {
149 case ACTIVE_LIST:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100150 seq_puts(m, "Active:\n");
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700151 head = &vm->active_list;
Ben Gamari433e12f2009-02-17 20:08:51 -0500152 break;
153 case INACTIVE_LIST:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100154 seq_puts(m, "Inactive:\n");
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700155 head = &vm->inactive_list;
Ben Gamari433e12f2009-02-17 20:08:51 -0500156 break;
Ben Gamari433e12f2009-02-17 20:08:51 -0500157 default:
Chris Wilsonde227ef2010-07-03 07:58:38 +0100158 mutex_unlock(&dev->struct_mutex);
159 return -EINVAL;
Ben Gamari433e12f2009-02-17 20:08:51 -0500160 }
161
Chris Wilson8f2480f2010-09-26 11:44:19 +0100162 total_obj_size = total_gtt_size = count = 0;
Chris Wilson05394f32010-11-08 19:18:58 +0000163 list_for_each_entry(obj, head, mm_list) {
Damien Lespiau267f0c92013-06-24 22:59:48 +0100164 seq_puts(m, " ");
Chris Wilson05394f32010-11-08 19:18:58 +0000165 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100166 seq_putc(m, '\n');
Chris Wilson05394f32010-11-08 19:18:58 +0000167 total_obj_size += obj->base.size;
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700168 total_gtt_size += i915_gem_obj_ggtt_size(obj);
Chris Wilson8f2480f2010-09-26 11:44:19 +0100169 count++;
Ben Gamari20172632009-02-17 20:08:50 -0500170 }
Chris Wilsonde227ef2010-07-03 07:58:38 +0100171 mutex_unlock(&dev->struct_mutex);
Carl Worth5e118f42009-03-20 11:54:25 -0700172
Chris Wilson8f2480f2010-09-26 11:44:19 +0100173 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
174 count, total_obj_size, total_gtt_size);
Ben Gamari20172632009-02-17 20:08:50 -0500175 return 0;
176}
177
Chris Wilson6299f992010-11-24 12:23:44 +0000178#define count_objects(list, member) do { \
179 list_for_each_entry(obj, list, member) { \
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700180 size += i915_gem_obj_ggtt_size(obj); \
Chris Wilson6299f992010-11-24 12:23:44 +0000181 ++count; \
182 if (obj->map_and_fenceable) { \
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700183 mappable_size += i915_gem_obj_ggtt_size(obj); \
Chris Wilson6299f992010-11-24 12:23:44 +0000184 ++mappable_count; \
185 } \
186 } \
Akshay Joshi0206e352011-08-16 15:34:10 -0400187} while (0)
Chris Wilson6299f992010-11-24 12:23:44 +0000188
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100189struct file_stats {
190 int count;
191 size_t total, active, inactive, unbound;
192};
193
194static int per_file_stats(int id, void *ptr, void *data)
195{
196 struct drm_i915_gem_object *obj = ptr;
197 struct file_stats *stats = data;
198
199 stats->count++;
200 stats->total += obj->base.size;
201
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700202 if (i915_gem_obj_ggtt_bound(obj)) {
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100203 if (!list_empty(&obj->ring_list))
204 stats->active += obj->base.size;
205 else
206 stats->inactive += obj->base.size;
207 } else {
208 if (!list_empty(&obj->global_list))
209 stats->unbound += obj->base.size;
210 }
211
212 return 0;
213}
214
Damien Lespiauaee56cf2013-06-24 22:59:49 +0100215static int i915_gem_object_info(struct seq_file *m, void *data)
Chris Wilson73aa8082010-09-30 11:46:12 +0100216{
217 struct drm_info_node *node = (struct drm_info_node *) m->private;
218 struct drm_device *dev = node->minor->dev;
219 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonb7abb712012-08-20 11:33:30 +0200220 u32 count, mappable_count, purgeable_count;
221 size_t size, mappable_size, purgeable_size;
Chris Wilson6299f992010-11-24 12:23:44 +0000222 struct drm_i915_gem_object *obj;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700223 struct i915_address_space *vm = &dev_priv->gtt.base;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100224 struct drm_file *file;
Chris Wilson73aa8082010-09-30 11:46:12 +0100225 int ret;
226
227 ret = mutex_lock_interruptible(&dev->struct_mutex);
228 if (ret)
229 return ret;
230
Chris Wilson6299f992010-11-24 12:23:44 +0000231 seq_printf(m, "%u objects, %zu bytes\n",
232 dev_priv->mm.object_count,
233 dev_priv->mm.object_memory);
234
235 size = count = mappable_size = mappable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700236 count_objects(&dev_priv->mm.bound_list, global_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000237 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
238 count, mappable_count, size, mappable_size);
239
240 size = count = mappable_size = mappable_count = 0;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700241 count_objects(&vm->active_list, mm_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000242 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
243 count, mappable_count, size, mappable_size);
244
245 size = count = mappable_size = mappable_count = 0;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700246 count_objects(&vm->inactive_list, mm_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000247 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
248 count, mappable_count, size, mappable_size);
249
Chris Wilsonb7abb712012-08-20 11:33:30 +0200250 size = count = purgeable_size = purgeable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700251 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
Chris Wilson6c085a72012-08-20 11:40:46 +0200252 size += obj->base.size, ++count;
Chris Wilsonb7abb712012-08-20 11:33:30 +0200253 if (obj->madv == I915_MADV_DONTNEED)
254 purgeable_size += obj->base.size, ++purgeable_count;
255 }
Chris Wilson6c085a72012-08-20 11:40:46 +0200256 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
257
Chris Wilson6299f992010-11-24 12:23:44 +0000258 size = count = mappable_size = mappable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700259 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Chris Wilson6299f992010-11-24 12:23:44 +0000260 if (obj->fault_mappable) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700261 size += i915_gem_obj_ggtt_size(obj);
Chris Wilson6299f992010-11-24 12:23:44 +0000262 ++count;
263 }
264 if (obj->pin_mappable) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700265 mappable_size += i915_gem_obj_ggtt_size(obj);
Chris Wilson6299f992010-11-24 12:23:44 +0000266 ++mappable_count;
267 }
Chris Wilsonb7abb712012-08-20 11:33:30 +0200268 if (obj->madv == I915_MADV_DONTNEED) {
269 purgeable_size += obj->base.size;
270 ++purgeable_count;
271 }
Chris Wilson6299f992010-11-24 12:23:44 +0000272 }
Chris Wilsonb7abb712012-08-20 11:33:30 +0200273 seq_printf(m, "%u purgeable objects, %zu bytes\n",
274 purgeable_count, purgeable_size);
Chris Wilson6299f992010-11-24 12:23:44 +0000275 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
276 mappable_count, mappable_size);
277 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
278 count, size);
279
Ben Widawsky93d18792013-01-17 12:45:17 -0800280 seq_printf(m, "%zu [%lu] gtt total\n",
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700281 dev_priv->gtt.base.total,
282 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
Chris Wilson73aa8082010-09-30 11:46:12 +0100283
Damien Lespiau267f0c92013-06-24 22:59:48 +0100284 seq_putc(m, '\n');
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100285 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
286 struct file_stats stats;
287
288 memset(&stats, 0, sizeof(stats));
289 idr_for_each(&file->object_idr, per_file_stats, &stats);
290 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
291 get_pid_task(file->pid, PIDTYPE_PID)->comm,
292 stats.count,
293 stats.total,
294 stats.active,
295 stats.inactive,
296 stats.unbound);
297 }
298
Chris Wilson73aa8082010-09-30 11:46:12 +0100299 mutex_unlock(&dev->struct_mutex);
300
301 return 0;
302}
303
Damien Lespiauaee56cf2013-06-24 22:59:49 +0100304static int i915_gem_gtt_info(struct seq_file *m, void *data)
Chris Wilson08c18322011-01-10 00:00:24 +0000305{
306 struct drm_info_node *node = (struct drm_info_node *) m->private;
307 struct drm_device *dev = node->minor->dev;
Chris Wilson1b502472012-04-24 15:47:30 +0100308 uintptr_t list = (uintptr_t) node->info_ent->data;
Chris Wilson08c18322011-01-10 00:00:24 +0000309 struct drm_i915_private *dev_priv = dev->dev_private;
310 struct drm_i915_gem_object *obj;
311 size_t total_obj_size, total_gtt_size;
312 int count, ret;
313
314 ret = mutex_lock_interruptible(&dev->struct_mutex);
315 if (ret)
316 return ret;
317
318 total_obj_size = total_gtt_size = count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700319 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Chris Wilson1b502472012-04-24 15:47:30 +0100320 if (list == PINNED_LIST && obj->pin_count == 0)
321 continue;
322
Damien Lespiau267f0c92013-06-24 22:59:48 +0100323 seq_puts(m, " ");
Chris Wilson08c18322011-01-10 00:00:24 +0000324 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100325 seq_putc(m, '\n');
Chris Wilson08c18322011-01-10 00:00:24 +0000326 total_obj_size += obj->base.size;
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700327 total_gtt_size += i915_gem_obj_ggtt_size(obj);
Chris Wilson08c18322011-01-10 00:00:24 +0000328 count++;
329 }
330
331 mutex_unlock(&dev->struct_mutex);
332
333 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
334 count, total_obj_size, total_gtt_size);
335
336 return 0;
337}
338
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100339static int i915_gem_pageflip_info(struct seq_file *m, void *data)
340{
341 struct drm_info_node *node = (struct drm_info_node *) m->private;
342 struct drm_device *dev = node->minor->dev;
343 unsigned long flags;
344 struct intel_crtc *crtc;
345
346 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800347 const char pipe = pipe_name(crtc->pipe);
348 const char plane = plane_name(crtc->plane);
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100349 struct intel_unpin_work *work;
350
351 spin_lock_irqsave(&dev->event_lock, flags);
352 work = crtc->unpin_work;
353 if (work == NULL) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800354 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100355 pipe, plane);
356 } else {
Chris Wilsone7d841c2012-12-03 11:36:30 +0000357 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800358 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100359 pipe, plane);
360 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800361 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100362 pipe, plane);
363 }
364 if (work->enable_stall_check)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100365 seq_puts(m, "Stall check enabled, ");
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100366 else
Damien Lespiau267f0c92013-06-24 22:59:48 +0100367 seq_puts(m, "Stall check waiting for page flip ioctl, ");
Chris Wilsone7d841c2012-12-03 11:36:30 +0000368 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100369
370 if (work->old_fb_obj) {
Chris Wilson05394f32010-11-08 19:18:58 +0000371 struct drm_i915_gem_object *obj = work->old_fb_obj;
372 if (obj)
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700373 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
374 i915_gem_obj_ggtt_offset(obj));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100375 }
376 if (work->pending_flip_obj) {
Chris Wilson05394f32010-11-08 19:18:58 +0000377 struct drm_i915_gem_object *obj = work->pending_flip_obj;
378 if (obj)
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700379 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
380 i915_gem_obj_ggtt_offset(obj));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100381 }
382 }
383 spin_unlock_irqrestore(&dev->event_lock, flags);
384 }
385
386 return 0;
387}
388
Ben Gamari20172632009-02-17 20:08:50 -0500389static int i915_gem_request_info(struct seq_file *m, void *data)
390{
391 struct drm_info_node *node = (struct drm_info_node *) m->private;
392 struct drm_device *dev = node->minor->dev;
393 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100394 struct intel_ring_buffer *ring;
Ben Gamari20172632009-02-17 20:08:50 -0500395 struct drm_i915_gem_request *gem_request;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100396 int ret, count, i;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100397
398 ret = mutex_lock_interruptible(&dev->struct_mutex);
399 if (ret)
400 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500401
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100402 count = 0;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100403 for_each_ring(ring, dev_priv, i) {
404 if (list_empty(&ring->request_list))
405 continue;
406
407 seq_printf(m, "%s requests:\n", ring->name);
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100408 list_for_each_entry(gem_request,
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100409 &ring->request_list,
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100410 list) {
411 seq_printf(m, " %d @ %d\n",
412 gem_request->seqno,
413 (int) (jiffies - gem_request->emitted_jiffies));
414 }
415 count++;
Ben Gamari20172632009-02-17 20:08:50 -0500416 }
Chris Wilsonde227ef2010-07-03 07:58:38 +0100417 mutex_unlock(&dev->struct_mutex);
418
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100419 if (count == 0)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100420 seq_puts(m, "No requests\n");
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100421
Ben Gamari20172632009-02-17 20:08:50 -0500422 return 0;
423}
424
Chris Wilsonb2223492010-10-27 15:27:33 +0100425static void i915_ring_seqno_info(struct seq_file *m,
426 struct intel_ring_buffer *ring)
427{
428 if (ring->get_seqno) {
Mika Kuoppala43a7b922012-12-04 15:12:01 +0200429 seq_printf(m, "Current sequence (%s): %u\n",
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100430 ring->name, ring->get_seqno(ring, false));
Chris Wilsonb2223492010-10-27 15:27:33 +0100431 }
432}
433
Ben Gamari20172632009-02-17 20:08:50 -0500434static int i915_gem_seqno_info(struct seq_file *m, void *data)
435{
436 struct drm_info_node *node = (struct drm_info_node *) m->private;
437 struct drm_device *dev = node->minor->dev;
438 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100439 struct intel_ring_buffer *ring;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000440 int ret, i;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100441
442 ret = mutex_lock_interruptible(&dev->struct_mutex);
443 if (ret)
444 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500445
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100446 for_each_ring(ring, dev_priv, i)
447 i915_ring_seqno_info(m, ring);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100448
449 mutex_unlock(&dev->struct_mutex);
450
Ben Gamari20172632009-02-17 20:08:50 -0500451 return 0;
452}
453
454
455static int i915_interrupt_info(struct seq_file *m, void *data)
456{
457 struct drm_info_node *node = (struct drm_info_node *) m->private;
458 struct drm_device *dev = node->minor->dev;
459 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100460 struct intel_ring_buffer *ring;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800461 int ret, i, pipe;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100462
463 ret = mutex_lock_interruptible(&dev->struct_mutex);
464 if (ret)
465 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500466
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700467 if (IS_VALLEYVIEW(dev)) {
468 seq_printf(m, "Display IER:\t%08x\n",
469 I915_READ(VLV_IER));
470 seq_printf(m, "Display IIR:\t%08x\n",
471 I915_READ(VLV_IIR));
472 seq_printf(m, "Display IIR_RW:\t%08x\n",
473 I915_READ(VLV_IIR_RW));
474 seq_printf(m, "Display IMR:\t%08x\n",
475 I915_READ(VLV_IMR));
476 for_each_pipe(pipe)
477 seq_printf(m, "Pipe %c stat:\t%08x\n",
478 pipe_name(pipe),
479 I915_READ(PIPESTAT(pipe)));
480
481 seq_printf(m, "Master IER:\t%08x\n",
482 I915_READ(VLV_MASTER_IER));
483
484 seq_printf(m, "Render IER:\t%08x\n",
485 I915_READ(GTIER));
486 seq_printf(m, "Render IIR:\t%08x\n",
487 I915_READ(GTIIR));
488 seq_printf(m, "Render IMR:\t%08x\n",
489 I915_READ(GTIMR));
490
491 seq_printf(m, "PM IER:\t\t%08x\n",
492 I915_READ(GEN6_PMIER));
493 seq_printf(m, "PM IIR:\t\t%08x\n",
494 I915_READ(GEN6_PMIIR));
495 seq_printf(m, "PM IMR:\t\t%08x\n",
496 I915_READ(GEN6_PMIMR));
497
498 seq_printf(m, "Port hotplug:\t%08x\n",
499 I915_READ(PORT_HOTPLUG_EN));
500 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
501 I915_READ(VLV_DPFLIPSTAT));
502 seq_printf(m, "DPINVGTT:\t%08x\n",
503 I915_READ(DPINVGTT));
504
505 } else if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800506 seq_printf(m, "Interrupt enable: %08x\n",
507 I915_READ(IER));
508 seq_printf(m, "Interrupt identity: %08x\n",
509 I915_READ(IIR));
510 seq_printf(m, "Interrupt mask: %08x\n",
511 I915_READ(IMR));
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800512 for_each_pipe(pipe)
513 seq_printf(m, "Pipe %c stat: %08x\n",
514 pipe_name(pipe),
515 I915_READ(PIPESTAT(pipe)));
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800516 } else {
517 seq_printf(m, "North Display Interrupt enable: %08x\n",
518 I915_READ(DEIER));
519 seq_printf(m, "North Display Interrupt identity: %08x\n",
520 I915_READ(DEIIR));
521 seq_printf(m, "North Display Interrupt mask: %08x\n",
522 I915_READ(DEIMR));
523 seq_printf(m, "South Display Interrupt enable: %08x\n",
524 I915_READ(SDEIER));
525 seq_printf(m, "South Display Interrupt identity: %08x\n",
526 I915_READ(SDEIIR));
527 seq_printf(m, "South Display Interrupt mask: %08x\n",
528 I915_READ(SDEIMR));
529 seq_printf(m, "Graphics Interrupt enable: %08x\n",
530 I915_READ(GTIER));
531 seq_printf(m, "Graphics Interrupt identity: %08x\n",
532 I915_READ(GTIIR));
533 seq_printf(m, "Graphics Interrupt mask: %08x\n",
534 I915_READ(GTIMR));
535 }
Ben Gamari20172632009-02-17 20:08:50 -0500536 seq_printf(m, "Interrupts received: %d\n",
537 atomic_read(&dev_priv->irq_received));
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100538 for_each_ring(ring, dev_priv, i) {
Jesse Barnesda64c6f2011-08-09 09:17:46 -0700539 if (IS_GEN6(dev) || IS_GEN7(dev)) {
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100540 seq_printf(m,
541 "Graphics Interrupt mask (%s): %08x\n",
542 ring->name, I915_READ_IMR(ring));
Chris Wilson9862e602011-01-04 22:22:17 +0000543 }
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100544 i915_ring_seqno_info(m, ring);
Chris Wilson9862e602011-01-04 22:22:17 +0000545 }
Chris Wilsonde227ef2010-07-03 07:58:38 +0100546 mutex_unlock(&dev->struct_mutex);
547
Ben Gamari20172632009-02-17 20:08:50 -0500548 return 0;
549}
550
Chris Wilsona6172a82009-02-11 14:26:38 +0000551static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
552{
553 struct drm_info_node *node = (struct drm_info_node *) m->private;
554 struct drm_device *dev = node->minor->dev;
555 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100556 int i, ret;
557
558 ret = mutex_lock_interruptible(&dev->struct_mutex);
559 if (ret)
560 return ret;
Chris Wilsona6172a82009-02-11 14:26:38 +0000561
562 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
563 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
564 for (i = 0; i < dev_priv->num_fence_regs; i++) {
Chris Wilson05394f32010-11-08 19:18:58 +0000565 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
Chris Wilsona6172a82009-02-11 14:26:38 +0000566
Chris Wilson6c085a72012-08-20 11:40:46 +0200567 seq_printf(m, "Fence %d, pin count = %d, object = ",
568 i, dev_priv->fence_regs[i].pin_count);
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100569 if (obj == NULL)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100570 seq_puts(m, "unused");
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100571 else
Chris Wilson05394f32010-11-08 19:18:58 +0000572 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100573 seq_putc(m, '\n');
Chris Wilsona6172a82009-02-11 14:26:38 +0000574 }
575
Chris Wilson05394f32010-11-08 19:18:58 +0000576 mutex_unlock(&dev->struct_mutex);
Chris Wilsona6172a82009-02-11 14:26:38 +0000577 return 0;
578}
579
Ben Gamari20172632009-02-17 20:08:50 -0500580static int i915_hws_info(struct seq_file *m, void *data)
581{
582 struct drm_info_node *node = (struct drm_info_node *) m->private;
583 struct drm_device *dev = node->minor->dev;
584 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson4066c0a2010-10-29 21:00:54 +0100585 struct intel_ring_buffer *ring;
Daniel Vetter1a240d42012-11-29 22:18:51 +0100586 const u32 *hws;
Chris Wilson4066c0a2010-10-29 21:00:54 +0100587 int i;
Ben Gamari20172632009-02-17 20:08:50 -0500588
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000589 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
Daniel Vetter1a240d42012-11-29 22:18:51 +0100590 hws = ring->status_page.page_addr;
Ben Gamari20172632009-02-17 20:08:50 -0500591 if (hws == NULL)
592 return 0;
593
594 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
595 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
596 i * 4,
597 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
598 }
599 return 0;
600}
601
Daniel Vetterd5442302012-04-27 15:17:40 +0200602static ssize_t
603i915_error_state_write(struct file *filp,
604 const char __user *ubuf,
605 size_t cnt,
606 loff_t *ppos)
607{
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300608 struct i915_error_state_file_priv *error_priv = filp->private_data;
Daniel Vetterd5442302012-04-27 15:17:40 +0200609 struct drm_device *dev = error_priv->dev;
Daniel Vetter22bcfc62012-08-09 15:07:02 +0200610 int ret;
Daniel Vetterd5442302012-04-27 15:17:40 +0200611
612 DRM_DEBUG_DRIVER("Resetting error state\n");
613
Daniel Vetter22bcfc62012-08-09 15:07:02 +0200614 ret = mutex_lock_interruptible(&dev->struct_mutex);
615 if (ret)
616 return ret;
617
Daniel Vetterd5442302012-04-27 15:17:40 +0200618 i915_destroy_error_state(dev);
619 mutex_unlock(&dev->struct_mutex);
620
621 return cnt;
622}
623
624static int i915_error_state_open(struct inode *inode, struct file *file)
625{
626 struct drm_device *dev = inode->i_private;
Daniel Vetterd5442302012-04-27 15:17:40 +0200627 struct i915_error_state_file_priv *error_priv;
Daniel Vetterd5442302012-04-27 15:17:40 +0200628
629 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
630 if (!error_priv)
631 return -ENOMEM;
632
633 error_priv->dev = dev;
634
Mika Kuoppala95d5bfb2013-06-06 15:18:40 +0300635 i915_error_state_get(dev, error_priv);
Daniel Vetterd5442302012-04-27 15:17:40 +0200636
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300637 file->private_data = error_priv;
638
639 return 0;
Daniel Vetterd5442302012-04-27 15:17:40 +0200640}
641
642static int i915_error_state_release(struct inode *inode, struct file *file)
643{
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300644 struct i915_error_state_file_priv *error_priv = file->private_data;
Daniel Vetterd5442302012-04-27 15:17:40 +0200645
Mika Kuoppala95d5bfb2013-06-06 15:18:40 +0300646 i915_error_state_put(error_priv);
Daniel Vetterd5442302012-04-27 15:17:40 +0200647 kfree(error_priv);
648
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300649 return 0;
650}
651
652static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
653 size_t count, loff_t *pos)
654{
655 struct i915_error_state_file_priv *error_priv = file->private_data;
656 struct drm_i915_error_state_buf error_str;
657 loff_t tmp_pos = 0;
658 ssize_t ret_count = 0;
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300659 int ret;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300660
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300661 ret = i915_error_state_buf_init(&error_str, count, *pos);
662 if (ret)
663 return ret;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300664
Mika Kuoppalafc16b482013-06-06 15:18:39 +0300665 ret = i915_error_state_to_str(&error_str, error_priv);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300666 if (ret)
667 goto out;
668
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300669 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
670 error_str.buf,
671 error_str.bytes);
672
673 if (ret_count < 0)
674 ret = ret_count;
675 else
676 *pos = error_str.start + ret_count;
677out:
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300678 i915_error_state_buf_release(&error_str);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300679 return ret ?: ret_count;
Daniel Vetterd5442302012-04-27 15:17:40 +0200680}
681
682static const struct file_operations i915_error_state_fops = {
683 .owner = THIS_MODULE,
684 .open = i915_error_state_open,
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300685 .read = i915_error_state_read,
Daniel Vetterd5442302012-04-27 15:17:40 +0200686 .write = i915_error_state_write,
687 .llseek = default_llseek,
688 .release = i915_error_state_release,
689};
690
Kees Cook647416f2013-03-10 14:10:06 -0700691static int
692i915_next_seqno_get(void *data, u64 *val)
Mika Kuoppala40633212012-12-04 15:12:00 +0200693{
Kees Cook647416f2013-03-10 14:10:06 -0700694 struct drm_device *dev = data;
Mika Kuoppala40633212012-12-04 15:12:00 +0200695 drm_i915_private_t *dev_priv = dev->dev_private;
Mika Kuoppala40633212012-12-04 15:12:00 +0200696 int ret;
697
698 ret = mutex_lock_interruptible(&dev->struct_mutex);
699 if (ret)
700 return ret;
701
Kees Cook647416f2013-03-10 14:10:06 -0700702 *val = dev_priv->next_seqno;
Mika Kuoppala40633212012-12-04 15:12:00 +0200703 mutex_unlock(&dev->struct_mutex);
704
Kees Cook647416f2013-03-10 14:10:06 -0700705 return 0;
Mika Kuoppala40633212012-12-04 15:12:00 +0200706}
707
Kees Cook647416f2013-03-10 14:10:06 -0700708static int
709i915_next_seqno_set(void *data, u64 val)
Mika Kuoppala40633212012-12-04 15:12:00 +0200710{
Kees Cook647416f2013-03-10 14:10:06 -0700711 struct drm_device *dev = data;
Mika Kuoppala40633212012-12-04 15:12:00 +0200712 int ret;
713
Mika Kuoppala40633212012-12-04 15:12:00 +0200714 ret = mutex_lock_interruptible(&dev->struct_mutex);
715 if (ret)
716 return ret;
717
Mika Kuoppalae94fbaa2012-12-19 11:13:09 +0200718 ret = i915_gem_set_seqno(dev, val);
Mika Kuoppala40633212012-12-04 15:12:00 +0200719 mutex_unlock(&dev->struct_mutex);
720
Kees Cook647416f2013-03-10 14:10:06 -0700721 return ret;
Mika Kuoppala40633212012-12-04 15:12:00 +0200722}
723
Kees Cook647416f2013-03-10 14:10:06 -0700724DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
725 i915_next_seqno_get, i915_next_seqno_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +0300726 "0x%llx\n");
Mika Kuoppala40633212012-12-04 15:12:00 +0200727
Jesse Barnesf97108d2010-01-29 11:27:07 -0800728static int i915_rstdby_delays(struct seq_file *m, void *unused)
729{
730 struct drm_info_node *node = (struct drm_info_node *) m->private;
731 struct drm_device *dev = node->minor->dev;
732 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawsky616fdb52011-10-05 11:44:54 -0700733 u16 crstanddelay;
734 int ret;
735
736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
739
740 crstanddelay = I915_READ16(CRSTANDVID);
741
742 mutex_unlock(&dev->struct_mutex);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800743
744 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
745
746 return 0;
747}
748
749static int i915_cur_delayinfo(struct seq_file *m, void *unused)
750{
751 struct drm_info_node *node = (struct drm_info_node *) m->private;
752 struct drm_device *dev = node->minor->dev;
753 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawskyd1ebd8162011-04-25 20:11:50 +0100754 int ret;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800755
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800756 if (IS_GEN5(dev)) {
757 u16 rgvswctl = I915_READ16(MEMSWCTL);
758 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
759
760 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
761 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
762 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
763 MEMSTAT_VID_SHIFT);
764 seq_printf(m, "Current P-state: %d\n",
765 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
Jesse Barnes0a073b82013-04-17 15:54:58 -0700766 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800767 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
768 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
769 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
Ben Widawskyf82855d2013-01-29 12:00:15 -0800770 u32 rpstat, cagf;
Jesse Barnesccab5c82011-01-18 15:49:25 -0800771 u32 rpupei, rpcurup, rpprevup;
772 u32 rpdownei, rpcurdown, rpprevdown;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800773 int max_freq;
774
775 /* RPSTAT1 is in the GT power well */
Ben Widawskyd1ebd8162011-04-25 20:11:50 +0100776 ret = mutex_lock_interruptible(&dev->struct_mutex);
777 if (ret)
778 return ret;
779
Ben Widawskyfcca7922011-04-25 11:23:07 -0700780 gen6_gt_force_wake_get(dev_priv);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800781
Jesse Barnesccab5c82011-01-18 15:49:25 -0800782 rpstat = I915_READ(GEN6_RPSTAT1);
783 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
784 rpcurup = I915_READ(GEN6_RP_CUR_UP);
785 rpprevup = I915_READ(GEN6_RP_PREV_UP);
786 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
787 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
788 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
Ben Widawskyf82855d2013-01-29 12:00:15 -0800789 if (IS_HASWELL(dev))
790 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
791 else
792 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
793 cagf *= GT_FREQUENCY_MULTIPLIER;
Jesse Barnesccab5c82011-01-18 15:49:25 -0800794
Ben Widawskyd1ebd8162011-04-25 20:11:50 +0100795 gen6_gt_force_wake_put(dev_priv);
796 mutex_unlock(&dev->struct_mutex);
797
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800798 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
Jesse Barnesccab5c82011-01-18 15:49:25 -0800799 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800800 seq_printf(m, "Render p-state ratio: %d\n",
801 (gt_perf_status & 0xff00) >> 8);
802 seq_printf(m, "Render p-state VID: %d\n",
803 gt_perf_status & 0xff);
804 seq_printf(m, "Render p-state limit: %d\n",
805 rp_state_limits & 0xff);
Ben Widawskyf82855d2013-01-29 12:00:15 -0800806 seq_printf(m, "CAGF: %dMHz\n", cagf);
Jesse Barnesccab5c82011-01-18 15:49:25 -0800807 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
808 GEN6_CURICONT_MASK);
809 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
810 GEN6_CURBSYTAVG_MASK);
811 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
812 GEN6_CURBSYTAVG_MASK);
813 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
814 GEN6_CURIAVG_MASK);
815 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
816 GEN6_CURBSYTAVG_MASK);
817 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
818 GEN6_CURBSYTAVG_MASK);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800819
820 max_freq = (rp_state_cap & 0xff0000) >> 16;
821 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -0700822 max_freq * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800823
824 max_freq = (rp_state_cap & 0xff00) >> 8;
825 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -0700826 max_freq * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800827
828 max_freq = rp_state_cap & 0xff;
829 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -0700830 max_freq * GT_FREQUENCY_MULTIPLIER);
Ben Widawsky31c77382013-04-05 14:29:22 -0700831
832 seq_printf(m, "Max overclocked frequency: %dMHz\n",
833 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes0a073b82013-04-17 15:54:58 -0700834 } else if (IS_VALLEYVIEW(dev)) {
835 u32 freq_sts, val;
836
Jesse Barnes259bd5d2013-04-22 15:59:30 -0700837 mutex_lock(&dev_priv->rps.hw_lock);
Jani Nikula64936252013-05-22 15:36:20 +0300838 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
Jesse Barnes0a073b82013-04-17 15:54:58 -0700839 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
840 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
841
Jani Nikula64936252013-05-22 15:36:20 +0300842 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
Jesse Barnes0a073b82013-04-17 15:54:58 -0700843 seq_printf(m, "max GPU freq: %d MHz\n",
844 vlv_gpu_freq(dev_priv->mem_freq, val));
845
Jani Nikula64936252013-05-22 15:36:20 +0300846 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
Jesse Barnes0a073b82013-04-17 15:54:58 -0700847 seq_printf(m, "min GPU freq: %d MHz\n",
848 vlv_gpu_freq(dev_priv->mem_freq, val));
849
850 seq_printf(m, "current GPU freq: %d MHz\n",
851 vlv_gpu_freq(dev_priv->mem_freq,
852 (freq_sts >> 8) & 0xff));
Jesse Barnes259bd5d2013-04-22 15:59:30 -0700853 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800854 } else {
Damien Lespiau267f0c92013-06-24 22:59:48 +0100855 seq_puts(m, "no P-state info available\n");
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800856 }
Jesse Barnesf97108d2010-01-29 11:27:07 -0800857
858 return 0;
859}
860
861static int i915_delayfreq_table(struct seq_file *m, void *unused)
862{
863 struct drm_info_node *node = (struct drm_info_node *) m->private;
864 struct drm_device *dev = node->minor->dev;
865 drm_i915_private_t *dev_priv = dev->dev_private;
866 u32 delayfreq;
Ben Widawsky616fdb52011-10-05 11:44:54 -0700867 int ret, i;
868
869 ret = mutex_lock_interruptible(&dev->struct_mutex);
870 if (ret)
871 return ret;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800872
873 for (i = 0; i < 16; i++) {
874 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
Jesse Barnes7648fa92010-05-20 14:28:11 -0700875 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
876 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800877 }
878
Ben Widawsky616fdb52011-10-05 11:44:54 -0700879 mutex_unlock(&dev->struct_mutex);
880
Jesse Barnesf97108d2010-01-29 11:27:07 -0800881 return 0;
882}
883
884static inline int MAP_TO_MV(int map)
885{
886 return 1250 - (map * 25);
887}
888
889static int i915_inttoext_table(struct seq_file *m, void *unused)
890{
891 struct drm_info_node *node = (struct drm_info_node *) m->private;
892 struct drm_device *dev = node->minor->dev;
893 drm_i915_private_t *dev_priv = dev->dev_private;
894 u32 inttoext;
Ben Widawsky616fdb52011-10-05 11:44:54 -0700895 int ret, i;
896
897 ret = mutex_lock_interruptible(&dev->struct_mutex);
898 if (ret)
899 return ret;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800900
901 for (i = 1; i <= 32; i++) {
902 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
903 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
904 }
905
Ben Widawsky616fdb52011-10-05 11:44:54 -0700906 mutex_unlock(&dev->struct_mutex);
907
Jesse Barnesf97108d2010-01-29 11:27:07 -0800908 return 0;
909}
910
Ben Widawsky4d855292011-12-12 19:34:16 -0800911static int ironlake_drpc_info(struct seq_file *m)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800912{
913 struct drm_info_node *node = (struct drm_info_node *) m->private;
914 struct drm_device *dev = node->minor->dev;
915 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawsky616fdb52011-10-05 11:44:54 -0700916 u32 rgvmodectl, rstdbyctl;
917 u16 crstandvid;
918 int ret;
919
920 ret = mutex_lock_interruptible(&dev->struct_mutex);
921 if (ret)
922 return ret;
923
924 rgvmodectl = I915_READ(MEMMODECTL);
925 rstdbyctl = I915_READ(RSTDBYCTL);
926 crstandvid = I915_READ16(CRSTANDVID);
927
928 mutex_unlock(&dev->struct_mutex);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800929
930 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
931 "yes" : "no");
932 seq_printf(m, "Boost freq: %d\n",
933 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
934 MEMMODE_BOOST_FREQ_SHIFT);
935 seq_printf(m, "HW control enabled: %s\n",
936 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
937 seq_printf(m, "SW control enabled: %s\n",
938 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
939 seq_printf(m, "Gated voltage change: %s\n",
940 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
941 seq_printf(m, "Starting frequency: P%d\n",
942 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -0700943 seq_printf(m, "Max P-state: P%d\n",
Jesse Barnesf97108d2010-01-29 11:27:07 -0800944 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -0700945 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
946 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
947 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
948 seq_printf(m, "Render standby enabled: %s\n",
949 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
Damien Lespiau267f0c92013-06-24 22:59:48 +0100950 seq_puts(m, "Current RS state: ");
Jesse Barnes88271da2011-01-05 12:01:24 -0800951 switch (rstdbyctl & RSX_STATUS_MASK) {
952 case RSX_STATUS_ON:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100953 seq_puts(m, "on\n");
Jesse Barnes88271da2011-01-05 12:01:24 -0800954 break;
955 case RSX_STATUS_RC1:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100956 seq_puts(m, "RC1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -0800957 break;
958 case RSX_STATUS_RC1E:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100959 seq_puts(m, "RC1E\n");
Jesse Barnes88271da2011-01-05 12:01:24 -0800960 break;
961 case RSX_STATUS_RS1:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100962 seq_puts(m, "RS1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -0800963 break;
964 case RSX_STATUS_RS2:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100965 seq_puts(m, "RS2 (RC6)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -0800966 break;
967 case RSX_STATUS_RS3:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100968 seq_puts(m, "RC3 (RC6+)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -0800969 break;
970 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100971 seq_puts(m, "unknown\n");
Jesse Barnes88271da2011-01-05 12:01:24 -0800972 break;
973 }
Jesse Barnesf97108d2010-01-29 11:27:07 -0800974
975 return 0;
976}
977
Ben Widawsky4d855292011-12-12 19:34:16 -0800978static int gen6_drpc_info(struct seq_file *m)
979{
980
981 struct drm_info_node *node = (struct drm_info_node *) m->private;
982 struct drm_device *dev = node->minor->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyecd8fae2012-09-26 10:34:02 -0700984 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
Daniel Vetter93b525d2012-01-25 13:52:43 +0100985 unsigned forcewake_count;
Damien Lespiauaee56cf2013-06-24 22:59:49 +0100986 int count = 0, ret;
Ben Widawsky4d855292011-12-12 19:34:16 -0800987
988 ret = mutex_lock_interruptible(&dev->struct_mutex);
989 if (ret)
990 return ret;
991
Chris Wilson907b28c2013-07-19 20:36:52 +0100992 spin_lock_irq(&dev_priv->uncore.lock);
993 forcewake_count = dev_priv->uncore.forcewake_count;
994 spin_unlock_irq(&dev_priv->uncore.lock);
Daniel Vetter93b525d2012-01-25 13:52:43 +0100995
996 if (forcewake_count) {
Damien Lespiau267f0c92013-06-24 22:59:48 +0100997 seq_puts(m, "RC information inaccurate because somebody "
998 "holds a forcewake reference \n");
Ben Widawsky4d855292011-12-12 19:34:16 -0800999 } else {
1000 /* NB: we cannot use forcewake, else we read the wrong values */
1001 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1002 udelay(10);
1003 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1004 }
1005
1006 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
Chris Wilsoned71f1b2013-07-19 20:36:56 +01001007 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
Ben Widawsky4d855292011-12-12 19:34:16 -08001008
1009 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1010 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1011 mutex_unlock(&dev->struct_mutex);
Ben Widawsky44cbd332012-11-06 14:36:36 +00001012 mutex_lock(&dev_priv->rps.hw_lock);
1013 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1014 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky4d855292011-12-12 19:34:16 -08001015
1016 seq_printf(m, "Video Turbo Mode: %s\n",
1017 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1018 seq_printf(m, "HW control enabled: %s\n",
1019 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1020 seq_printf(m, "SW control enabled: %s\n",
1021 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1022 GEN6_RP_MEDIA_SW_MODE));
Eric Anholtfff24e22012-01-23 16:14:05 -08001023 seq_printf(m, "RC1e Enabled: %s\n",
Ben Widawsky4d855292011-12-12 19:34:16 -08001024 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1025 seq_printf(m, "RC6 Enabled: %s\n",
1026 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1027 seq_printf(m, "Deep RC6 Enabled: %s\n",
1028 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1029 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1030 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
Damien Lespiau267f0c92013-06-24 22:59:48 +01001031 seq_puts(m, "Current RC state: ");
Ben Widawsky4d855292011-12-12 19:34:16 -08001032 switch (gt_core_status & GEN6_RCn_MASK) {
1033 case GEN6_RC0:
1034 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
Damien Lespiau267f0c92013-06-24 22:59:48 +01001035 seq_puts(m, "Core Power Down\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001036 else
Damien Lespiau267f0c92013-06-24 22:59:48 +01001037 seq_puts(m, "on\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001038 break;
1039 case GEN6_RC3:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001040 seq_puts(m, "RC3\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001041 break;
1042 case GEN6_RC6:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001043 seq_puts(m, "RC6\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001044 break;
1045 case GEN6_RC7:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001046 seq_puts(m, "RC7\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001047 break;
1048 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001049 seq_puts(m, "Unknown\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001050 break;
1051 }
1052
1053 seq_printf(m, "Core Power Down: %s\n",
1054 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
Ben Widawskycce66a22012-03-27 18:59:38 -07001055
1056 /* Not exactly sure what this is */
1057 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1058 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1059 seq_printf(m, "RC6 residency since boot: %u\n",
1060 I915_READ(GEN6_GT_GFX_RC6));
1061 seq_printf(m, "RC6+ residency since boot: %u\n",
1062 I915_READ(GEN6_GT_GFX_RC6p));
1063 seq_printf(m, "RC6++ residency since boot: %u\n",
1064 I915_READ(GEN6_GT_GFX_RC6pp));
1065
Ben Widawskyecd8fae2012-09-26 10:34:02 -07001066 seq_printf(m, "RC6 voltage: %dmV\n",
1067 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1068 seq_printf(m, "RC6+ voltage: %dmV\n",
1069 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1070 seq_printf(m, "RC6++ voltage: %dmV\n",
1071 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
Ben Widawsky4d855292011-12-12 19:34:16 -08001072 return 0;
1073}
1074
1075static int i915_drpc_info(struct seq_file *m, void *unused)
1076{
1077 struct drm_info_node *node = (struct drm_info_node *) m->private;
1078 struct drm_device *dev = node->minor->dev;
1079
1080 if (IS_GEN6(dev) || IS_GEN7(dev))
1081 return gen6_drpc_info(m);
1082 else
1083 return ironlake_drpc_info(m);
1084}
1085
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001086static int i915_fbc_status(struct seq_file *m, void *unused)
1087{
1088 struct drm_info_node *node = (struct drm_info_node *) m->private;
1089 struct drm_device *dev = node->minor->dev;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001090 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001091
Adam Jacksonee5382a2010-04-23 11:17:39 -04001092 if (!I915_HAS_FBC(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001093 seq_puts(m, "FBC unsupported on this chipset\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001094 return 0;
1095 }
1096
Adam Jacksonee5382a2010-04-23 11:17:39 -04001097 if (intel_fbc_enabled(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001098 seq_puts(m, "FBC enabled\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001099 } else {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001100 seq_puts(m, "FBC disabled: ");
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001101 switch (dev_priv->fbc.no_fbc_reason) {
Chris Wilsonbed4a672010-09-11 10:47:47 +01001102 case FBC_NO_OUTPUT:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001103 seq_puts(m, "no outputs");
Chris Wilsonbed4a672010-09-11 10:47:47 +01001104 break;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001105 case FBC_STOLEN_TOO_SMALL:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001106 seq_puts(m, "not enough stolen memory");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001107 break;
1108 case FBC_UNSUPPORTED_MODE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001109 seq_puts(m, "mode not supported");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001110 break;
1111 case FBC_MODE_TOO_LARGE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001112 seq_puts(m, "mode too large");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001113 break;
1114 case FBC_BAD_PLANE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001115 seq_puts(m, "FBC unsupported on plane");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001116 break;
1117 case FBC_NOT_TILED:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001118 seq_puts(m, "scanout buffer not tiled");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001119 break;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001120 case FBC_MULTIPLE_PIPES:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001121 seq_puts(m, "multiple pipes are enabled");
Jesse Barnes9c928d12010-07-23 15:20:00 -07001122 break;
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001123 case FBC_MODULE_PARAM:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001124 seq_puts(m, "disabled per module param (default off)");
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001125 break;
Damien Lespiau8a5729a2013-06-24 16:22:02 +01001126 case FBC_CHIP_DEFAULT:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001127 seq_puts(m, "disabled per chip default");
Damien Lespiau8a5729a2013-06-24 16:22:02 +01001128 break;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001129 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001130 seq_puts(m, "unknown reason");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001131 }
Damien Lespiau267f0c92013-06-24 22:59:48 +01001132 seq_putc(m, '\n');
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001133 }
1134 return 0;
1135}
1136
Paulo Zanoni92d44622013-05-31 16:33:24 -03001137static int i915_ips_status(struct seq_file *m, void *unused)
1138{
1139 struct drm_info_node *node = (struct drm_info_node *) m->private;
1140 struct drm_device *dev = node->minor->dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142
Damien Lespiauf5adf942013-06-24 18:29:34 +01001143 if (!HAS_IPS(dev)) {
Paulo Zanoni92d44622013-05-31 16:33:24 -03001144 seq_puts(m, "not supported\n");
1145 return 0;
1146 }
1147
1148 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1149 seq_puts(m, "enabled\n");
1150 else
1151 seq_puts(m, "disabled\n");
1152
1153 return 0;
1154}
1155
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001156static int i915_sr_status(struct seq_file *m, void *unused)
1157{
1158 struct drm_info_node *node = (struct drm_info_node *) m->private;
1159 struct drm_device *dev = node->minor->dev;
1160 drm_i915_private_t *dev_priv = dev->dev_private;
1161 bool sr_enabled = false;
1162
Yuanhan Liu13982612010-12-15 15:42:31 +08001163 if (HAS_PCH_SPLIT(dev))
Chris Wilson5ba2aaa2010-08-19 18:04:08 +01001164 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001165 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001166 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1167 else if (IS_I915GM(dev))
1168 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1169 else if (IS_PINEVIEW(dev))
1170 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1171
Chris Wilson5ba2aaa2010-08-19 18:04:08 +01001172 seq_printf(m, "self-refresh: %s\n",
1173 sr_enabled ? "enabled" : "disabled");
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001174
1175 return 0;
1176}
1177
Jesse Barnes7648fa92010-05-20 14:28:11 -07001178static int i915_emon_status(struct seq_file *m, void *unused)
1179{
1180 struct drm_info_node *node = (struct drm_info_node *) m->private;
1181 struct drm_device *dev = node->minor->dev;
1182 drm_i915_private_t *dev_priv = dev->dev_private;
1183 unsigned long temp, chipset, gfx;
Chris Wilsonde227ef2010-07-03 07:58:38 +01001184 int ret;
1185
Chris Wilson582be6b2012-04-30 19:35:02 +01001186 if (!IS_GEN5(dev))
1187 return -ENODEV;
1188
Chris Wilsonde227ef2010-07-03 07:58:38 +01001189 ret = mutex_lock_interruptible(&dev->struct_mutex);
1190 if (ret)
1191 return ret;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001192
1193 temp = i915_mch_val(dev_priv);
1194 chipset = i915_chipset_val(dev_priv);
1195 gfx = i915_gfx_val(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +01001196 mutex_unlock(&dev->struct_mutex);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001197
1198 seq_printf(m, "GMCH temp: %ld\n", temp);
1199 seq_printf(m, "Chipset power: %ld\n", chipset);
1200 seq_printf(m, "GFX power: %ld\n", gfx);
1201 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1202
1203 return 0;
1204}
1205
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001206static int i915_ring_freq_table(struct seq_file *m, void *unused)
1207{
1208 struct drm_info_node *node = (struct drm_info_node *) m->private;
1209 struct drm_device *dev = node->minor->dev;
1210 drm_i915_private_t *dev_priv = dev->dev_private;
1211 int ret;
1212 int gpu_freq, ia_freq;
1213
Jesse Barnes1c70c0c2011-06-29 13:34:36 -07001214 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001215 seq_puts(m, "unsupported on this chipset\n");
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001216 return 0;
1217 }
1218
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001219 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001220 if (ret)
1221 return ret;
1222
Damien Lespiau267f0c92013-06-24 22:59:48 +01001223 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001224
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001225 for (gpu_freq = dev_priv->rps.min_delay;
1226 gpu_freq <= dev_priv->rps.max_delay;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001227 gpu_freq++) {
Ben Widawsky42c05262012-09-26 10:34:00 -07001228 ia_freq = gpu_freq;
1229 sandybridge_pcode_read(dev_priv,
1230 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1231 &ia_freq);
Chris Wilson3ebecd02013-04-12 19:10:13 +01001232 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1233 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1234 ((ia_freq >> 0) & 0xff) * 100,
1235 ((ia_freq >> 8) & 0xff) * 100);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001236 }
1237
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001238 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001239
1240 return 0;
1241}
1242
Jesse Barnes7648fa92010-05-20 14:28:11 -07001243static int i915_gfxec(struct seq_file *m, void *unused)
1244{
1245 struct drm_info_node *node = (struct drm_info_node *) m->private;
1246 struct drm_device *dev = node->minor->dev;
1247 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawsky616fdb52011-10-05 11:44:54 -07001248 int ret;
1249
1250 ret = mutex_lock_interruptible(&dev->struct_mutex);
1251 if (ret)
1252 return ret;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001253
1254 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1255
Ben Widawsky616fdb52011-10-05 11:44:54 -07001256 mutex_unlock(&dev->struct_mutex);
1257
Jesse Barnes7648fa92010-05-20 14:28:11 -07001258 return 0;
1259}
1260
Chris Wilson44834a62010-08-19 16:09:23 +01001261static int i915_opregion(struct seq_file *m, void *unused)
1262{
1263 struct drm_info_node *node = (struct drm_info_node *) m->private;
1264 struct drm_device *dev = node->minor->dev;
1265 drm_i915_private_t *dev_priv = dev->dev_private;
1266 struct intel_opregion *opregion = &dev_priv->opregion;
Daniel Vetter0d38f002012-04-21 22:49:10 +02001267 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
Chris Wilson44834a62010-08-19 16:09:23 +01001268 int ret;
1269
Daniel Vetter0d38f002012-04-21 22:49:10 +02001270 if (data == NULL)
1271 return -ENOMEM;
1272
Chris Wilson44834a62010-08-19 16:09:23 +01001273 ret = mutex_lock_interruptible(&dev->struct_mutex);
1274 if (ret)
Daniel Vetter0d38f002012-04-21 22:49:10 +02001275 goto out;
Chris Wilson44834a62010-08-19 16:09:23 +01001276
Daniel Vetter0d38f002012-04-21 22:49:10 +02001277 if (opregion->header) {
1278 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1279 seq_write(m, data, OPREGION_SIZE);
1280 }
Chris Wilson44834a62010-08-19 16:09:23 +01001281
1282 mutex_unlock(&dev->struct_mutex);
1283
Daniel Vetter0d38f002012-04-21 22:49:10 +02001284out:
1285 kfree(data);
Chris Wilson44834a62010-08-19 16:09:23 +01001286 return 0;
1287}
1288
Chris Wilson37811fc2010-08-25 22:45:57 +01001289static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1290{
1291 struct drm_info_node *node = (struct drm_info_node *) m->private;
1292 struct drm_device *dev = node->minor->dev;
1293 drm_i915_private_t *dev_priv = dev->dev_private;
1294 struct intel_fbdev *ifbdev;
1295 struct intel_framebuffer *fb;
1296 int ret;
1297
1298 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1299 if (ret)
1300 return ret;
1301
1302 ifbdev = dev_priv->fbdev;
1303 fb = to_intel_framebuffer(ifbdev->helper.fb);
1304
Daniel Vetter623f9782012-12-11 16:21:38 +01001305 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
Chris Wilson37811fc2010-08-25 22:45:57 +01001306 fb->base.width,
1307 fb->base.height,
1308 fb->base.depth,
Daniel Vetter623f9782012-12-11 16:21:38 +01001309 fb->base.bits_per_pixel,
1310 atomic_read(&fb->base.refcount.refcount));
Chris Wilson05394f32010-11-08 19:18:58 +00001311 describe_obj(m, fb->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001312 seq_putc(m, '\n');
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001313 mutex_unlock(&dev->mode_config.mutex);
Chris Wilson37811fc2010-08-25 22:45:57 +01001314
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001315 mutex_lock(&dev->mode_config.fb_lock);
Chris Wilson37811fc2010-08-25 22:45:57 +01001316 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1317 if (&fb->base == ifbdev->helper.fb)
1318 continue;
1319
Daniel Vetter623f9782012-12-11 16:21:38 +01001320 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
Chris Wilson37811fc2010-08-25 22:45:57 +01001321 fb->base.width,
1322 fb->base.height,
1323 fb->base.depth,
Daniel Vetter623f9782012-12-11 16:21:38 +01001324 fb->base.bits_per_pixel,
1325 atomic_read(&fb->base.refcount.refcount));
Chris Wilson05394f32010-11-08 19:18:58 +00001326 describe_obj(m, fb->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001327 seq_putc(m, '\n');
Chris Wilson37811fc2010-08-25 22:45:57 +01001328 }
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001329 mutex_unlock(&dev->mode_config.fb_lock);
Chris Wilson37811fc2010-08-25 22:45:57 +01001330
1331 return 0;
1332}
1333
Ben Widawskye76d3632011-03-19 18:14:29 -07001334static int i915_context_status(struct seq_file *m, void *unused)
1335{
1336 struct drm_info_node *node = (struct drm_info_node *) m->private;
1337 struct drm_device *dev = node->minor->dev;
1338 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawskya168c292013-02-14 15:05:12 -08001339 struct intel_ring_buffer *ring;
1340 int ret, i;
Ben Widawskye76d3632011-03-19 18:14:29 -07001341
1342 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1343 if (ret)
1344 return ret;
1345
Daniel Vetter3e373942012-11-02 19:55:04 +01001346 if (dev_priv->ips.pwrctx) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001347 seq_puts(m, "power context ");
Daniel Vetter3e373942012-11-02 19:55:04 +01001348 describe_obj(m, dev_priv->ips.pwrctx);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001349 seq_putc(m, '\n');
Ben Widawskydc501fb2011-06-29 11:41:51 -07001350 }
Ben Widawskye76d3632011-03-19 18:14:29 -07001351
Daniel Vetter3e373942012-11-02 19:55:04 +01001352 if (dev_priv->ips.renderctx) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001353 seq_puts(m, "render context ");
Daniel Vetter3e373942012-11-02 19:55:04 +01001354 describe_obj(m, dev_priv->ips.renderctx);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001355 seq_putc(m, '\n');
Ben Widawskydc501fb2011-06-29 11:41:51 -07001356 }
Ben Widawskye76d3632011-03-19 18:14:29 -07001357
Ben Widawskya168c292013-02-14 15:05:12 -08001358 for_each_ring(ring, dev_priv, i) {
1359 if (ring->default_context) {
1360 seq_printf(m, "HW default context %s ring ", ring->name);
1361 describe_obj(m, ring->default_context->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001362 seq_putc(m, '\n');
Ben Widawskya168c292013-02-14 15:05:12 -08001363 }
1364 }
1365
Ben Widawskye76d3632011-03-19 18:14:29 -07001366 mutex_unlock(&dev->mode_config.mutex);
1367
1368 return 0;
1369}
1370
Ben Widawsky6d794d42011-04-25 11:25:56 -07001371static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1372{
1373 struct drm_info_node *node = (struct drm_info_node *) m->private;
1374 struct drm_device *dev = node->minor->dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9f1f46a2011-12-14 13:57:03 +01001376 unsigned forcewake_count;
Ben Widawsky6d794d42011-04-25 11:25:56 -07001377
Chris Wilson907b28c2013-07-19 20:36:52 +01001378 spin_lock_irq(&dev_priv->uncore.lock);
1379 forcewake_count = dev_priv->uncore.forcewake_count;
1380 spin_unlock_irq(&dev_priv->uncore.lock);
Daniel Vetter9f1f46a2011-12-14 13:57:03 +01001381
1382 seq_printf(m, "forcewake count = %u\n", forcewake_count);
Ben Widawsky6d794d42011-04-25 11:25:56 -07001383
1384 return 0;
1385}
1386
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001387static const char *swizzle_string(unsigned swizzle)
1388{
Damien Lespiauaee56cf2013-06-24 22:59:49 +01001389 switch (swizzle) {
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001390 case I915_BIT_6_SWIZZLE_NONE:
1391 return "none";
1392 case I915_BIT_6_SWIZZLE_9:
1393 return "bit9";
1394 case I915_BIT_6_SWIZZLE_9_10:
1395 return "bit9/bit10";
1396 case I915_BIT_6_SWIZZLE_9_11:
1397 return "bit9/bit11";
1398 case I915_BIT_6_SWIZZLE_9_10_11:
1399 return "bit9/bit10/bit11";
1400 case I915_BIT_6_SWIZZLE_9_17:
1401 return "bit9/bit17";
1402 case I915_BIT_6_SWIZZLE_9_10_17:
1403 return "bit9/bit10/bit17";
1404 case I915_BIT_6_SWIZZLE_UNKNOWN:
Masanari Iida8a168ca2012-12-29 02:00:09 +09001405 return "unknown";
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001406 }
1407
1408 return "bug";
1409}
1410
1411static int i915_swizzle_info(struct seq_file *m, void *data)
1412{
1413 struct drm_info_node *node = (struct drm_info_node *) m->private;
1414 struct drm_device *dev = node->minor->dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001416 int ret;
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001417
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001418 ret = mutex_lock_interruptible(&dev->struct_mutex);
1419 if (ret)
1420 return ret;
1421
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001422 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1423 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1424 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1425 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1426
1427 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1428 seq_printf(m, "DDC = 0x%08x\n",
1429 I915_READ(DCC));
1430 seq_printf(m, "C0DRB3 = 0x%04x\n",
1431 I915_READ16(C0DRB3));
1432 seq_printf(m, "C1DRB3 = 0x%04x\n",
1433 I915_READ16(C1DRB3));
Daniel Vetter3fa7d232012-01-31 16:47:56 +01001434 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1435 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1436 I915_READ(MAD_DIMM_C0));
1437 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1438 I915_READ(MAD_DIMM_C1));
1439 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1440 I915_READ(MAD_DIMM_C2));
1441 seq_printf(m, "TILECTL = 0x%08x\n",
1442 I915_READ(TILECTL));
1443 seq_printf(m, "ARB_MODE = 0x%08x\n",
1444 I915_READ(ARB_MODE));
1445 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1446 I915_READ(DISP_ARB_CTL));
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001447 }
1448 mutex_unlock(&dev->struct_mutex);
1449
1450 return 0;
1451}
1452
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001453static int i915_ppgtt_info(struct seq_file *m, void *data)
1454{
1455 struct drm_info_node *node = (struct drm_info_node *) m->private;
1456 struct drm_device *dev = node->minor->dev;
1457 struct drm_i915_private *dev_priv = dev->dev_private;
1458 struct intel_ring_buffer *ring;
1459 int i, ret;
1460
1461
1462 ret = mutex_lock_interruptible(&dev->struct_mutex);
1463 if (ret)
1464 return ret;
1465 if (INTEL_INFO(dev)->gen == 6)
1466 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1467
Chris Wilsona2c7f6f2012-09-01 20:51:22 +01001468 for_each_ring(ring, dev_priv, i) {
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001469 seq_printf(m, "%s\n", ring->name);
1470 if (INTEL_INFO(dev)->gen == 7)
1471 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1472 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1473 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1474 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1475 }
1476 if (dev_priv->mm.aliasing_ppgtt) {
1477 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1478
Damien Lespiau267f0c92013-06-24 22:59:48 +01001479 seq_puts(m, "aliasing PPGTT:\n");
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001480 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1481 }
1482 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1483 mutex_unlock(&dev->struct_mutex);
1484
1485 return 0;
1486}
1487
Jesse Barnes57f350b2012-03-28 13:39:25 -07001488static int i915_dpio_info(struct seq_file *m, void *data)
1489{
1490 struct drm_info_node *node = (struct drm_info_node *) m->private;
1491 struct drm_device *dev = node->minor->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 int ret;
1494
1495
1496 if (!IS_VALLEYVIEW(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001497 seq_puts(m, "unsupported\n");
Jesse Barnes57f350b2012-03-28 13:39:25 -07001498 return 0;
1499 }
1500
Daniel Vetter09153002012-12-12 14:06:44 +01001501 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
Jesse Barnes57f350b2012-03-28 13:39:25 -07001502 if (ret)
1503 return ret;
1504
1505 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1506
1507 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
Jani Nikulaae992582013-05-22 15:36:19 +03001508 vlv_dpio_read(dev_priv, _DPIO_DIV_A));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001509 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
Jani Nikulaae992582013-05-22 15:36:19 +03001510 vlv_dpio_read(dev_priv, _DPIO_DIV_B));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001511
1512 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
Jani Nikulaae992582013-05-22 15:36:19 +03001513 vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001514 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
Jani Nikulaae992582013-05-22 15:36:19 +03001515 vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001516
1517 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
Jani Nikulaae992582013-05-22 15:36:19 +03001518 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001519 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
Jani Nikulaae992582013-05-22 15:36:19 +03001520 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001521
Ville Syrjälä4abb2c32013-06-14 14:02:53 +03001522 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1523 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
1524 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1525 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001526
1527 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
Jani Nikulaae992582013-05-22 15:36:19 +03001528 vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001529
Daniel Vetter09153002012-12-12 14:06:44 +01001530 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes57f350b2012-03-28 13:39:25 -07001531
1532 return 0;
1533}
1534
Ben Widawsky63573eb2013-07-04 11:02:07 -07001535static int i915_llc(struct seq_file *m, void *data)
1536{
1537 struct drm_info_node *node = (struct drm_info_node *) m->private;
1538 struct drm_device *dev = node->minor->dev;
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540
1541 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1542 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1543 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1544
1545 return 0;
1546}
1547
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001548static int i915_edp_psr_status(struct seq_file *m, void *data)
1549{
1550 struct drm_info_node *node = m->private;
1551 struct drm_device *dev = node->minor->dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001553 u32 psrstat, psrperf;
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001554
1555 if (!IS_HASWELL(dev)) {
1556 seq_puts(m, "PSR not supported on this platform\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001557 } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) {
1558 seq_puts(m, "PSR enabled\n");
1559 } else {
1560 seq_puts(m, "PSR disabled: ");
1561 switch (dev_priv->no_psr_reason) {
1562 case PSR_NO_SOURCE:
1563 seq_puts(m, "not supported on this platform");
1564 break;
1565 case PSR_NO_SINK:
1566 seq_puts(m, "not supported by panel");
1567 break;
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001568 case PSR_MODULE_PARAM:
1569 seq_puts(m, "disabled by flag");
1570 break;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001571 case PSR_CRTC_NOT_ACTIVE:
1572 seq_puts(m, "crtc not active");
1573 break;
1574 case PSR_PWR_WELL_ENABLED:
1575 seq_puts(m, "power well enabled");
1576 break;
1577 case PSR_NOT_TILED:
1578 seq_puts(m, "not tiled");
1579 break;
1580 case PSR_SPRITE_ENABLED:
1581 seq_puts(m, "sprite enabled");
1582 break;
1583 case PSR_S3D_ENABLED:
1584 seq_puts(m, "stereo 3d enabled");
1585 break;
1586 case PSR_INTERLACED_ENABLED:
1587 seq_puts(m, "interlaced enabled");
1588 break;
1589 case PSR_HSW_NOT_DDIA:
1590 seq_puts(m, "HSW ties PSR to DDI A (eDP)");
1591 break;
1592 default:
1593 seq_puts(m, "unknown reason");
1594 }
1595 seq_puts(m, "\n");
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001596 return 0;
1597 }
1598
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001599 psrstat = I915_READ(EDP_PSR_STATUS_CTL);
1600
1601 seq_puts(m, "PSR Current State: ");
1602 switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
1603 case EDP_PSR_STATUS_STATE_IDLE:
1604 seq_puts(m, "Reset state\n");
1605 break;
1606 case EDP_PSR_STATUS_STATE_SRDONACK:
1607 seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
1608 break;
1609 case EDP_PSR_STATUS_STATE_SRDENT:
1610 seq_puts(m, "SRD entry\n");
1611 break;
1612 case EDP_PSR_STATUS_STATE_BUFOFF:
1613 seq_puts(m, "Wait for buffer turn off\n");
1614 break;
1615 case EDP_PSR_STATUS_STATE_BUFON:
1616 seq_puts(m, "Wait for buffer turn on\n");
1617 break;
1618 case EDP_PSR_STATUS_STATE_AUXACK:
1619 seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n");
1620 break;
1621 case EDP_PSR_STATUS_STATE_SRDOFFACK:
1622 seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
1623 break;
1624 default:
1625 seq_puts(m, "Unknown\n");
1626 break;
1627 }
1628
1629 seq_puts(m, "Link Status: ");
1630 switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
1631 case EDP_PSR_STATUS_LINK_FULL_OFF:
1632 seq_puts(m, "Link is fully off\n");
1633 break;
1634 case EDP_PSR_STATUS_LINK_FULL_ON:
1635 seq_puts(m, "Link is fully on\n");
1636 break;
1637 case EDP_PSR_STATUS_LINK_STANDBY:
1638 seq_puts(m, "Link is in standby\n");
1639 break;
1640 default:
1641 seq_puts(m, "Unknown\n");
1642 break;
1643 }
1644
1645 seq_printf(m, "PSR Entry Count: %u\n",
1646 psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
1647 EDP_PSR_STATUS_COUNT_MASK);
1648
1649 seq_printf(m, "Max Sleep Timer Counter: %u\n",
1650 psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
1651 EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
1652
1653 seq_printf(m, "Had AUX error: %s\n",
1654 yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
1655
1656 seq_printf(m, "Sending AUX: %s\n",
1657 yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
1658
1659 seq_printf(m, "Sending Idle: %s\n",
1660 yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
1661
1662 seq_printf(m, "Sending TP2 TP3: %s\n",
1663 yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
1664
1665 seq_printf(m, "Sending TP1: %s\n",
1666 yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
1667
1668 seq_printf(m, "Idle Count: %u\n",
1669 psrstat & EDP_PSR_STATUS_IDLE_MASK);
1670
1671 psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
1672 seq_printf(m, "Performance Counter: %u\n", psrperf);
1673
1674 return 0;
1675}
1676
Kees Cook647416f2013-03-10 14:10:06 -07001677static int
1678i915_wedged_get(void *data, u64 *val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001679{
Kees Cook647416f2013-03-10 14:10:06 -07001680 struct drm_device *dev = data;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001681 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001682
Kees Cook647416f2013-03-10 14:10:06 -07001683 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001684
Kees Cook647416f2013-03-10 14:10:06 -07001685 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001686}
1687
Kees Cook647416f2013-03-10 14:10:06 -07001688static int
1689i915_wedged_set(void *data, u64 val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001690{
Kees Cook647416f2013-03-10 14:10:06 -07001691 struct drm_device *dev = data;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001692
Kees Cook647416f2013-03-10 14:10:06 -07001693 DRM_INFO("Manually setting wedged to %llu\n", val);
Chris Wilson527f9e92010-11-11 01:16:58 +00001694 i915_handle_error(dev, val);
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001695
Kees Cook647416f2013-03-10 14:10:06 -07001696 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001697}
1698
Kees Cook647416f2013-03-10 14:10:06 -07001699DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1700 i915_wedged_get, i915_wedged_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03001701 "%llu\n");
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001702
Kees Cook647416f2013-03-10 14:10:06 -07001703static int
1704i915_ring_stop_get(void *data, u64 *val)
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001705{
Kees Cook647416f2013-03-10 14:10:06 -07001706 struct drm_device *dev = data;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001707 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001708
Kees Cook647416f2013-03-10 14:10:06 -07001709 *val = dev_priv->gpu_error.stop_rings;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001710
Kees Cook647416f2013-03-10 14:10:06 -07001711 return 0;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001712}
1713
Kees Cook647416f2013-03-10 14:10:06 -07001714static int
1715i915_ring_stop_set(void *data, u64 val)
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001716{
Kees Cook647416f2013-03-10 14:10:06 -07001717 struct drm_device *dev = data;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001718 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07001719 int ret;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001720
Kees Cook647416f2013-03-10 14:10:06 -07001721 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001722
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001723 ret = mutex_lock_interruptible(&dev->struct_mutex);
1724 if (ret)
1725 return ret;
1726
Daniel Vetter99584db2012-11-14 17:14:04 +01001727 dev_priv->gpu_error.stop_rings = val;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001728 mutex_unlock(&dev->struct_mutex);
1729
Kees Cook647416f2013-03-10 14:10:06 -07001730 return 0;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02001731}
1732
Kees Cook647416f2013-03-10 14:10:06 -07001733DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1734 i915_ring_stop_get, i915_ring_stop_set,
1735 "0x%08llx\n");
Daniel Vetterd5442302012-04-27 15:17:40 +02001736
Chris Wilsondd624af2013-01-15 12:39:35 +00001737#define DROP_UNBOUND 0x1
1738#define DROP_BOUND 0x2
1739#define DROP_RETIRE 0x4
1740#define DROP_ACTIVE 0x8
1741#define DROP_ALL (DROP_UNBOUND | \
1742 DROP_BOUND | \
1743 DROP_RETIRE | \
1744 DROP_ACTIVE)
Kees Cook647416f2013-03-10 14:10:06 -07001745static int
1746i915_drop_caches_get(void *data, u64 *val)
Chris Wilsondd624af2013-01-15 12:39:35 +00001747{
Kees Cook647416f2013-03-10 14:10:06 -07001748 *val = DROP_ALL;
Chris Wilsondd624af2013-01-15 12:39:35 +00001749
Kees Cook647416f2013-03-10 14:10:06 -07001750 return 0;
Chris Wilsondd624af2013-01-15 12:39:35 +00001751}
1752
Kees Cook647416f2013-03-10 14:10:06 -07001753static int
1754i915_drop_caches_set(void *data, u64 val)
Chris Wilsondd624af2013-01-15 12:39:35 +00001755{
Kees Cook647416f2013-03-10 14:10:06 -07001756 struct drm_device *dev = data;
Chris Wilsondd624af2013-01-15 12:39:35 +00001757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 struct drm_i915_gem_object *obj, *next;
Ben Widawsky5cef07e2013-07-16 16:50:08 -07001759 struct i915_address_space *vm = &dev_priv->gtt.base;
Kees Cook647416f2013-03-10 14:10:06 -07001760 int ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00001761
Kees Cook647416f2013-03-10 14:10:06 -07001762 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
Chris Wilsondd624af2013-01-15 12:39:35 +00001763
1764 /* No need to check and wait for gpu resets, only libdrm auto-restarts
1765 * on ioctls on -EAGAIN. */
1766 ret = mutex_lock_interruptible(&dev->struct_mutex);
1767 if (ret)
1768 return ret;
1769
1770 if (val & DROP_ACTIVE) {
1771 ret = i915_gpu_idle(dev);
1772 if (ret)
1773 goto unlock;
1774 }
1775
1776 if (val & (DROP_RETIRE | DROP_ACTIVE))
1777 i915_gem_retire_requests(dev);
1778
1779 if (val & DROP_BOUND) {
Ben Widawsky5cef07e2013-07-16 16:50:08 -07001780 list_for_each_entry_safe(obj, next, &vm->inactive_list,
1781 mm_list)
Chris Wilsondd624af2013-01-15 12:39:35 +00001782 if (obj->pin_count == 0) {
1783 ret = i915_gem_object_unbind(obj);
1784 if (ret)
1785 goto unlock;
1786 }
1787 }
1788
1789 if (val & DROP_UNBOUND) {
Ben Widawsky35c20a62013-05-31 11:28:48 -07001790 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1791 global_list)
Chris Wilsondd624af2013-01-15 12:39:35 +00001792 if (obj->pages_pin_count == 0) {
1793 ret = i915_gem_object_put_pages(obj);
1794 if (ret)
1795 goto unlock;
1796 }
1797 }
1798
1799unlock:
1800 mutex_unlock(&dev->struct_mutex);
1801
Kees Cook647416f2013-03-10 14:10:06 -07001802 return ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00001803}
1804
Kees Cook647416f2013-03-10 14:10:06 -07001805DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1806 i915_drop_caches_get, i915_drop_caches_set,
1807 "0x%08llx\n");
Chris Wilsondd624af2013-01-15 12:39:35 +00001808
Kees Cook647416f2013-03-10 14:10:06 -07001809static int
1810i915_max_freq_get(void *data, u64 *val)
Jesse Barnes358733e2011-07-27 11:53:01 -07001811{
Kees Cook647416f2013-03-10 14:10:06 -07001812 struct drm_device *dev = data;
Jesse Barnes358733e2011-07-27 11:53:01 -07001813 drm_i915_private_t *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07001814 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02001815
1816 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1817 return -ENODEV;
1818
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001819 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02001820 if (ret)
1821 return ret;
Jesse Barnes358733e2011-07-27 11:53:01 -07001822
Jesse Barnes0a073b82013-04-17 15:54:58 -07001823 if (IS_VALLEYVIEW(dev))
1824 *val = vlv_gpu_freq(dev_priv->mem_freq,
1825 dev_priv->rps.max_delay);
1826 else
1827 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001828 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes358733e2011-07-27 11:53:01 -07001829
Kees Cook647416f2013-03-10 14:10:06 -07001830 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07001831}
1832
Kees Cook647416f2013-03-10 14:10:06 -07001833static int
1834i915_max_freq_set(void *data, u64 val)
Jesse Barnes358733e2011-07-27 11:53:01 -07001835{
Kees Cook647416f2013-03-10 14:10:06 -07001836 struct drm_device *dev = data;
Jesse Barnes358733e2011-07-27 11:53:01 -07001837 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07001838 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02001839
1840 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1841 return -ENODEV;
Jesse Barnes358733e2011-07-27 11:53:01 -07001842
Kees Cook647416f2013-03-10 14:10:06 -07001843 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
Jesse Barnes358733e2011-07-27 11:53:01 -07001844
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001845 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02001846 if (ret)
1847 return ret;
1848
Jesse Barnes358733e2011-07-27 11:53:01 -07001849 /*
1850 * Turbo will still be enabled, but won't go above the set value.
1851 */
Jesse Barnes0a073b82013-04-17 15:54:58 -07001852 if (IS_VALLEYVIEW(dev)) {
1853 val = vlv_freq_opcode(dev_priv->mem_freq, val);
1854 dev_priv->rps.max_delay = val;
1855 gen6_set_rps(dev, val);
1856 } else {
1857 do_div(val, GT_FREQUENCY_MULTIPLIER);
1858 dev_priv->rps.max_delay = val;
1859 gen6_set_rps(dev, val);
1860 }
1861
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001862 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes358733e2011-07-27 11:53:01 -07001863
Kees Cook647416f2013-03-10 14:10:06 -07001864 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07001865}
1866
Kees Cook647416f2013-03-10 14:10:06 -07001867DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
1868 i915_max_freq_get, i915_max_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03001869 "%llu\n");
Jesse Barnes358733e2011-07-27 11:53:01 -07001870
Kees Cook647416f2013-03-10 14:10:06 -07001871static int
1872i915_min_freq_get(void *data, u64 *val)
Jesse Barnes1523c312012-05-25 12:34:54 -07001873{
Kees Cook647416f2013-03-10 14:10:06 -07001874 struct drm_device *dev = data;
Jesse Barnes1523c312012-05-25 12:34:54 -07001875 drm_i915_private_t *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07001876 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02001877
1878 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1879 return -ENODEV;
1880
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001881 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02001882 if (ret)
1883 return ret;
Jesse Barnes1523c312012-05-25 12:34:54 -07001884
Jesse Barnes0a073b82013-04-17 15:54:58 -07001885 if (IS_VALLEYVIEW(dev))
1886 *val = vlv_gpu_freq(dev_priv->mem_freq,
1887 dev_priv->rps.min_delay);
1888 else
1889 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001890 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes1523c312012-05-25 12:34:54 -07001891
Kees Cook647416f2013-03-10 14:10:06 -07001892 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07001893}
1894
Kees Cook647416f2013-03-10 14:10:06 -07001895static int
1896i915_min_freq_set(void *data, u64 val)
Jesse Barnes1523c312012-05-25 12:34:54 -07001897{
Kees Cook647416f2013-03-10 14:10:06 -07001898 struct drm_device *dev = data;
Jesse Barnes1523c312012-05-25 12:34:54 -07001899 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07001900 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02001901
1902 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1903 return -ENODEV;
Jesse Barnes1523c312012-05-25 12:34:54 -07001904
Kees Cook647416f2013-03-10 14:10:06 -07001905 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
Jesse Barnes1523c312012-05-25 12:34:54 -07001906
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001907 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02001908 if (ret)
1909 return ret;
1910
Jesse Barnes1523c312012-05-25 12:34:54 -07001911 /*
1912 * Turbo will still be enabled, but won't go below the set value.
1913 */
Jesse Barnes0a073b82013-04-17 15:54:58 -07001914 if (IS_VALLEYVIEW(dev)) {
1915 val = vlv_freq_opcode(dev_priv->mem_freq, val);
1916 dev_priv->rps.min_delay = val;
1917 valleyview_set_rps(dev, val);
1918 } else {
1919 do_div(val, GT_FREQUENCY_MULTIPLIER);
1920 dev_priv->rps.min_delay = val;
1921 gen6_set_rps(dev, val);
1922 }
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001923 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes1523c312012-05-25 12:34:54 -07001924
Kees Cook647416f2013-03-10 14:10:06 -07001925 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07001926}
1927
Kees Cook647416f2013-03-10 14:10:06 -07001928DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
1929 i915_min_freq_get, i915_min_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03001930 "%llu\n");
Jesse Barnes1523c312012-05-25 12:34:54 -07001931
Kees Cook647416f2013-03-10 14:10:06 -07001932static int
1933i915_cache_sharing_get(void *data, u64 *val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001934{
Kees Cook647416f2013-03-10 14:10:06 -07001935 struct drm_device *dev = data;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001936 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001937 u32 snpcr;
Kees Cook647416f2013-03-10 14:10:06 -07001938 int ret;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001939
Daniel Vetter004777c2012-08-09 15:07:01 +02001940 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1941 return -ENODEV;
1942
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001943 ret = mutex_lock_interruptible(&dev->struct_mutex);
1944 if (ret)
1945 return ret;
1946
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001947 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1948 mutex_unlock(&dev_priv->dev->struct_mutex);
1949
Kees Cook647416f2013-03-10 14:10:06 -07001950 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001951
Kees Cook647416f2013-03-10 14:10:06 -07001952 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001953}
1954
Kees Cook647416f2013-03-10 14:10:06 -07001955static int
1956i915_cache_sharing_set(void *data, u64 val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001957{
Kees Cook647416f2013-03-10 14:10:06 -07001958 struct drm_device *dev = data;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001959 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001960 u32 snpcr;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001961
Daniel Vetter004777c2012-08-09 15:07:01 +02001962 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1963 return -ENODEV;
1964
Kees Cook647416f2013-03-10 14:10:06 -07001965 if (val > 3)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001966 return -EINVAL;
1967
Kees Cook647416f2013-03-10 14:10:06 -07001968 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001969
1970 /* Update the cache sharing policy here as well */
1971 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1972 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1973 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1974 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1975
Kees Cook647416f2013-03-10 14:10:06 -07001976 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001977}
1978
Kees Cook647416f2013-03-10 14:10:06 -07001979DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
1980 i915_cache_sharing_get, i915_cache_sharing_set,
1981 "%llu\n");
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07001982
Chris Wilsonf3cd4742009-10-13 22:20:20 +01001983/* As the drm_debugfs_init() routines are called before dev->dev_private is
1984 * allocated we need to hook into the minor for release. */
1985static int
1986drm_add_fake_info_node(struct drm_minor *minor,
1987 struct dentry *ent,
1988 const void *key)
1989{
1990 struct drm_info_node *node;
1991
1992 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1993 if (node == NULL) {
1994 debugfs_remove(ent);
1995 return -ENOMEM;
1996 }
1997
1998 node->minor = minor;
1999 node->dent = ent;
2000 node->info_ent = (void *) key;
Marcin Slusarzb3e067c2011-11-09 22:20:35 +01002001
2002 mutex_lock(&minor->debugfs_lock);
2003 list_add(&node->list, &minor->debugfs_list);
2004 mutex_unlock(&minor->debugfs_lock);
Chris Wilsonf3cd4742009-10-13 22:20:20 +01002005
2006 return 0;
2007}
2008
Ben Widawsky6d794d42011-04-25 11:25:56 -07002009static int i915_forcewake_open(struct inode *inode, struct file *file)
2010{
2011 struct drm_device *dev = inode->i_private;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky6d794d42011-04-25 11:25:56 -07002013
Daniel Vetter075edca2012-01-24 09:44:28 +01002014 if (INTEL_INFO(dev)->gen < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07002015 return 0;
2016
Ben Widawsky6d794d42011-04-25 11:25:56 -07002017 gen6_gt_force_wake_get(dev_priv);
Ben Widawsky6d794d42011-04-25 11:25:56 -07002018
2019 return 0;
2020}
2021
Ben Widawskyc43b5632012-04-16 14:07:40 -07002022static int i915_forcewake_release(struct inode *inode, struct file *file)
Ben Widawsky6d794d42011-04-25 11:25:56 -07002023{
2024 struct drm_device *dev = inode->i_private;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026
Daniel Vetter075edca2012-01-24 09:44:28 +01002027 if (INTEL_INFO(dev)->gen < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07002028 return 0;
2029
Ben Widawsky6d794d42011-04-25 11:25:56 -07002030 gen6_gt_force_wake_put(dev_priv);
Ben Widawsky6d794d42011-04-25 11:25:56 -07002031
2032 return 0;
2033}
2034
2035static const struct file_operations i915_forcewake_fops = {
2036 .owner = THIS_MODULE,
2037 .open = i915_forcewake_open,
2038 .release = i915_forcewake_release,
2039};
2040
2041static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2042{
2043 struct drm_device *dev = minor->dev;
2044 struct dentry *ent;
2045
2046 ent = debugfs_create_file("i915_forcewake_user",
Ben Widawsky8eb57292011-05-11 15:10:58 -07002047 S_IRUSR,
Ben Widawsky6d794d42011-04-25 11:25:56 -07002048 root, dev,
2049 &i915_forcewake_fops);
2050 if (IS_ERR(ent))
2051 return PTR_ERR(ent);
2052
Ben Widawsky8eb57292011-05-11 15:10:58 -07002053 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
Ben Widawsky6d794d42011-04-25 11:25:56 -07002054}
2055
Daniel Vetter6a9c3082011-12-14 13:57:11 +01002056static int i915_debugfs_create(struct dentry *root,
2057 struct drm_minor *minor,
2058 const char *name,
2059 const struct file_operations *fops)
Jesse Barnes358733e2011-07-27 11:53:01 -07002060{
2061 struct drm_device *dev = minor->dev;
2062 struct dentry *ent;
2063
Daniel Vetter6a9c3082011-12-14 13:57:11 +01002064 ent = debugfs_create_file(name,
Jesse Barnes358733e2011-07-27 11:53:01 -07002065 S_IRUGO | S_IWUSR,
2066 root, dev,
Daniel Vetter6a9c3082011-12-14 13:57:11 +01002067 fops);
Jesse Barnes358733e2011-07-27 11:53:01 -07002068 if (IS_ERR(ent))
2069 return PTR_ERR(ent);
2070
Daniel Vetter6a9c3082011-12-14 13:57:11 +01002071 return drm_add_fake_info_node(minor, ent, fops);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07002072}
2073
Ben Gamari27c202a2009-07-01 22:26:52 -04002074static struct drm_info_list i915_debugfs_list[] = {
Chris Wilson311bd682011-01-13 19:06:50 +00002075 {"i915_capabilities", i915_capabilities, 0},
Chris Wilson73aa8082010-09-30 11:46:12 +01002076 {"i915_gem_objects", i915_gem_object_info, 0},
Chris Wilson08c18322011-01-10 00:00:24 +00002077 {"i915_gem_gtt", i915_gem_gtt_info, 0},
Chris Wilson1b502472012-04-24 15:47:30 +01002078 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
Ben Gamari433e12f2009-02-17 20:08:51 -05002079 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
Ben Gamari433e12f2009-02-17 20:08:51 -05002080 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01002081 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05002082 {"i915_gem_request", i915_gem_request_info, 0},
2083 {"i915_gem_seqno", i915_gem_seqno_info, 0},
Chris Wilsona6172a82009-02-11 14:26:38 +00002084 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05002085 {"i915_gem_interrupt", i915_interrupt_info, 0},
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002086 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2087 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2088 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
Xiang, Haihao9010ebf2013-05-29 09:22:36 -07002089 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
Jesse Barnesf97108d2010-01-29 11:27:07 -08002090 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2091 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2092 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2093 {"i915_inttoext_table", i915_inttoext_table, 0},
2094 {"i915_drpc_info", i915_drpc_info, 0},
Jesse Barnes7648fa92010-05-20 14:28:11 -07002095 {"i915_emon_status", i915_emon_status, 0},
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07002096 {"i915_ring_freq_table", i915_ring_freq_table, 0},
Jesse Barnes7648fa92010-05-20 14:28:11 -07002097 {"i915_gfxec", i915_gfxec, 0},
Jesse Barnesb5e50c32010-02-05 12:42:41 -08002098 {"i915_fbc_status", i915_fbc_status, 0},
Paulo Zanoni92d44622013-05-31 16:33:24 -03002099 {"i915_ips_status", i915_ips_status, 0},
Jesse Barnes4a9bef32010-02-05 12:47:35 -08002100 {"i915_sr_status", i915_sr_status, 0},
Chris Wilson44834a62010-08-19 16:09:23 +01002101 {"i915_opregion", i915_opregion, 0},
Chris Wilson37811fc2010-08-25 22:45:57 +01002102 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
Ben Widawskye76d3632011-03-19 18:14:29 -07002103 {"i915_context_status", i915_context_status, 0},
Ben Widawsky6d794d42011-04-25 11:25:56 -07002104 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
Daniel Vetterea16a3c2011-12-14 13:57:16 +01002105 {"i915_swizzle_info", i915_swizzle_info, 0},
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002106 {"i915_ppgtt_info", i915_ppgtt_info, 0},
Jesse Barnes57f350b2012-03-28 13:39:25 -07002107 {"i915_dpio", i915_dpio_info, 0},
Ben Widawsky63573eb2013-07-04 11:02:07 -07002108 {"i915_llc", i915_llc, 0},
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002109 {"i915_edp_psr_status", i915_edp_psr_status, 0},
Ben Gamari20172632009-02-17 20:08:50 -05002110};
Ben Gamari27c202a2009-07-01 22:26:52 -04002111#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
Ben Gamari20172632009-02-17 20:08:50 -05002112
Daniel Vetter34b96742013-07-04 20:49:44 +02002113struct i915_debugfs_files {
2114 const char *name;
2115 const struct file_operations *fops;
2116} i915_debugfs_files[] = {
2117 {"i915_wedged", &i915_wedged_fops},
2118 {"i915_max_freq", &i915_max_freq_fops},
2119 {"i915_min_freq", &i915_min_freq_fops},
2120 {"i915_cache_sharing", &i915_cache_sharing_fops},
2121 {"i915_ring_stop", &i915_ring_stop_fops},
2122 {"i915_gem_drop_caches", &i915_drop_caches_fops},
2123 {"i915_error_state", &i915_error_state_fops},
2124 {"i915_next_seqno", &i915_next_seqno_fops},
2125};
2126
Ben Gamari27c202a2009-07-01 22:26:52 -04002127int i915_debugfs_init(struct drm_minor *minor)
Ben Gamari20172632009-02-17 20:08:50 -05002128{
Daniel Vetter34b96742013-07-04 20:49:44 +02002129 int ret, i;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01002130
Ben Widawsky6d794d42011-04-25 11:25:56 -07002131 ret = i915_forcewake_create(minor->debugfs_root, minor);
2132 if (ret)
2133 return ret;
Daniel Vetter6a9c3082011-12-14 13:57:11 +01002134
Daniel Vetter34b96742013-07-04 20:49:44 +02002135 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2136 ret = i915_debugfs_create(minor->debugfs_root, minor,
2137 i915_debugfs_files[i].name,
2138 i915_debugfs_files[i].fops);
2139 if (ret)
2140 return ret;
2141 }
Mika Kuoppala40633212012-12-04 15:12:00 +02002142
Ben Gamari27c202a2009-07-01 22:26:52 -04002143 return drm_debugfs_create_files(i915_debugfs_list,
2144 I915_DEBUGFS_ENTRIES,
Ben Gamari20172632009-02-17 20:08:50 -05002145 minor->debugfs_root, minor);
2146}
2147
Ben Gamari27c202a2009-07-01 22:26:52 -04002148void i915_debugfs_cleanup(struct drm_minor *minor)
Ben Gamari20172632009-02-17 20:08:50 -05002149{
Daniel Vetter34b96742013-07-04 20:49:44 +02002150 int i;
2151
Ben Gamari27c202a2009-07-01 22:26:52 -04002152 drm_debugfs_remove_files(i915_debugfs_list,
2153 I915_DEBUGFS_ENTRIES, minor);
Ben Widawsky6d794d42011-04-25 11:25:56 -07002154 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2155 1, minor);
Daniel Vetter34b96742013-07-04 20:49:44 +02002156 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2157 struct drm_info_list *info_list =
2158 (struct drm_info_list *) i915_debugfs_files[i].fops;
2159
2160 drm_debugfs_remove_files(info_list, 1, minor);
2161 }
Ben Gamari20172632009-02-17 20:08:50 -05002162}
2163
2164#endif /* CONFIG_DEBUG_FS */