Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Synthesize TLB refill handlers at runtime. |
| 7 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
| 9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
Steven J. Hill | 113c62d | 2012-07-06 23:56:00 +0200 | [diff] [blame] | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 13 | * |
| 14 | * ... and the days got worse and worse and now you see |
Adam Buchbinder | 92a76f6 | 2016-02-25 00:44:58 -0800 | [diff] [blame] | 15 | * I've gone completely out of my mind. |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 16 | * |
| 17 | * They're coming to take me a away haha |
| 18 | * they're coming to take me a away hoho hihi haha |
| 19 | * to the funny farm where code is beautiful all the time ... |
| 20 | * |
| 21 | * (Condolences to Napoleon XIV) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | */ |
| 23 | |
David Daney | 95affdd | 2009-05-20 11:40:59 -0700 | [diff] [blame] | 24 | #include <linux/bug.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <linux/kernel.h> |
| 26 | #include <linux/types.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 27 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | #include <linux/string.h> |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 29 | #include <linux/cache.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 31 | #include <asm/cacheflush.h> |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 32 | #include <asm/cpu-type.h> |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 33 | #include <asm/pgtable.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include <asm/war.h> |
Florian Fainelli | 3482d71 | 2010-01-28 15:21:24 +0100 | [diff] [blame] | 35 | #include <asm/uasm.h> |
David Howells | b81947c | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 36 | #include <asm/setup.h> |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 37 | |
Paul Gortmaker | a2d25e6 | 2015-04-27 18:47:59 -0400 | [diff] [blame] | 38 | static int mips_xpa_disabled; |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 39 | |
| 40 | static int __init xpa_disable(char *s) |
| 41 | { |
| 42 | mips_xpa_disabled = 1; |
| 43 | |
| 44 | return 1; |
| 45 | } |
| 46 | |
| 47 | __setup("noxpa", xpa_disable); |
| 48 | |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 49 | /* |
| 50 | * TLB load/store/modify handlers. |
| 51 | * |
| 52 | * Only the fastpath gets synthesized at runtime, the slowpath for |
| 53 | * do_page_fault remains normal asm. |
| 54 | */ |
| 55 | extern void tlb_do_page_fault_0(void); |
| 56 | extern void tlb_do_page_fault_1(void); |
| 57 | |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 58 | struct work_registers { |
| 59 | int r1; |
| 60 | int r2; |
| 61 | int r3; |
| 62 | }; |
| 63 | |
| 64 | struct tlb_reg_save { |
| 65 | unsigned long a; |
| 66 | unsigned long b; |
| 67 | } ____cacheline_aligned_in_smp; |
| 68 | |
| 69 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 70 | |
Ralf Baechle | aeffdbb | 2007-10-11 23:46:14 +0100 | [diff] [blame] | 71 | static inline int r45k_bvahwbug(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | { |
| 73 | /* XXX: We should probe for the presence of this bug, but we don't. */ |
| 74 | return 0; |
| 75 | } |
| 76 | |
Ralf Baechle | aeffdbb | 2007-10-11 23:46:14 +0100 | [diff] [blame] | 77 | static inline int r4k_250MHZhwbug(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | { |
| 79 | /* XXX: We should probe for the presence of this bug, but we don't. */ |
| 80 | return 0; |
| 81 | } |
| 82 | |
Ralf Baechle | aeffdbb | 2007-10-11 23:46:14 +0100 | [diff] [blame] | 83 | static inline int __maybe_unused bcm1250_m3_war(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | { |
| 85 | return BCM1250_M3_WAR; |
| 86 | } |
| 87 | |
Ralf Baechle | aeffdbb | 2007-10-11 23:46:14 +0100 | [diff] [blame] | 88 | static inline int __maybe_unused r10000_llsc_war(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | { |
| 90 | return R10000_LLSC_WAR; |
| 91 | } |
| 92 | |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 93 | static int use_bbit_insns(void) |
| 94 | { |
| 95 | switch (current_cpu_type()) { |
| 96 | case CPU_CAVIUM_OCTEON: |
| 97 | case CPU_CAVIUM_OCTEON_PLUS: |
| 98 | case CPU_CAVIUM_OCTEON2: |
David Daney | 4723b20 | 2013-07-29 15:07:03 -0700 | [diff] [blame] | 99 | case CPU_CAVIUM_OCTEON3: |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 100 | return 1; |
| 101 | default: |
| 102 | return 0; |
| 103 | } |
| 104 | } |
| 105 | |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 106 | static int use_lwx_insns(void) |
| 107 | { |
| 108 | switch (current_cpu_type()) { |
| 109 | case CPU_CAVIUM_OCTEON2: |
David Daney | 4723b20 | 2013-07-29 15:07:03 -0700 | [diff] [blame] | 110 | case CPU_CAVIUM_OCTEON3: |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 111 | return 1; |
| 112 | default: |
| 113 | return 0; |
| 114 | } |
| 115 | } |
| 116 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ |
| 117 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 |
| 118 | static bool scratchpad_available(void) |
| 119 | { |
| 120 | return true; |
| 121 | } |
| 122 | static int scratchpad_offset(int i) |
| 123 | { |
| 124 | /* |
| 125 | * CVMSEG starts at address -32768 and extends for |
| 126 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. |
| 127 | */ |
| 128 | i += 1; /* Kernel use starts at the top and works down. */ |
| 129 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; |
| 130 | } |
| 131 | #else |
| 132 | static bool scratchpad_available(void) |
| 133 | { |
| 134 | return false; |
| 135 | } |
| 136 | static int scratchpad_offset(int i) |
| 137 | { |
| 138 | BUG(); |
David Daney | e1c87d2 | 2011-01-19 15:24:42 -0800 | [diff] [blame] | 139 | /* Really unreachable, but evidently some GCC want this. */ |
| 140 | return 0; |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 141 | } |
| 142 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | /* |
Maciej W. Rozycki | 8df5bea | 2006-08-23 14:26:50 +0100 | [diff] [blame] | 144 | * Found by experiment: At least some revisions of the 4kc throw under |
| 145 | * some circumstances a machine check exception, triggered by invalid |
| 146 | * values in the index register. Delaying the tlbp instruction until |
| 147 | * after the next branch, plus adding an additional nop in front of |
| 148 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows |
| 149 | * why; it's not an issue caused by the core RTL. |
| 150 | * |
| 151 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 152 | static int m4kc_tlbp_war(void) |
Maciej W. Rozycki | 8df5bea | 2006-08-23 14:26:50 +0100 | [diff] [blame] | 153 | { |
| 154 | return (current_cpu_data.processor_id & 0xffff00) == |
| 155 | (PRID_COMP_MIPS | PRID_IMP_4KC); |
| 156 | } |
| 157 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 158 | /* Handle labels (which must be positive integers). */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | enum label_id { |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 160 | label_second_part = 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | label_leave, |
| 162 | label_vmalloc, |
| 163 | label_vmalloc_done, |
Ralf Baechle | 02a5417 | 2012-10-13 22:46:26 +0200 | [diff] [blame] | 164 | label_tlbw_hazard_0, |
| 165 | label_split = label_tlbw_hazard_0 + 8, |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 166 | label_tlbl_goaround1, |
| 167 | label_tlbl_goaround2, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | label_nopage_tlbl, |
| 169 | label_nopage_tlbs, |
| 170 | label_nopage_tlbm, |
| 171 | label_smp_pgtable_change, |
| 172 | label_r3000_write_probe_fail, |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 173 | label_large_segbits_fault, |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 174 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 175 | label_tlb_huge_update, |
| 176 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | }; |
| 178 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 179 | UASM_L_LA(_second_part) |
| 180 | UASM_L_LA(_leave) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 181 | UASM_L_LA(_vmalloc) |
| 182 | UASM_L_LA(_vmalloc_done) |
Ralf Baechle | 02a5417 | 2012-10-13 22:46:26 +0200 | [diff] [blame] | 183 | /* _tlbw_hazard_x is handled differently. */ |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 184 | UASM_L_LA(_split) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 185 | UASM_L_LA(_tlbl_goaround1) |
| 186 | UASM_L_LA(_tlbl_goaround2) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 187 | UASM_L_LA(_nopage_tlbl) |
| 188 | UASM_L_LA(_nopage_tlbs) |
| 189 | UASM_L_LA(_nopage_tlbm) |
| 190 | UASM_L_LA(_smp_pgtable_change) |
| 191 | UASM_L_LA(_r3000_write_probe_fail) |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 192 | UASM_L_LA(_large_segbits_fault) |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 193 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 194 | UASM_L_LA(_tlb_huge_update) |
| 195 | #endif |
Atsushi Nemoto | 656be92 | 2006-10-26 00:08:31 +0900 | [diff] [blame] | 196 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 197 | static int hazard_instance; |
Ralf Baechle | 02a5417 | 2012-10-13 22:46:26 +0200 | [diff] [blame] | 198 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 199 | static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) |
Ralf Baechle | 02a5417 | 2012-10-13 22:46:26 +0200 | [diff] [blame] | 200 | { |
| 201 | switch (instance) { |
| 202 | case 0 ... 7: |
| 203 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); |
| 204 | return; |
| 205 | default: |
| 206 | BUG(); |
| 207 | } |
| 208 | } |
| 209 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 210 | static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) |
Ralf Baechle | 02a5417 | 2012-10-13 22:46:26 +0200 | [diff] [blame] | 211 | { |
| 212 | switch (instance) { |
| 213 | case 0 ... 7: |
| 214 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); |
| 215 | break; |
| 216 | default: |
| 217 | BUG(); |
| 218 | } |
| 219 | } |
| 220 | |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 221 | /* |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 222 | * pgtable bits are assigned dynamically depending on processor feature |
| 223 | * and statically based on kernel configuration. This spits out the actual |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 224 | * values the kernel is using. Required to make sense from disassembled |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 225 | * TLB exception handlers. |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 226 | */ |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 227 | static void output_pgtable_bits_defines(void) |
| 228 | { |
| 229 | #define pr_define(fmt, ...) \ |
| 230 | pr_debug("#define " fmt, ##__VA_ARGS__) |
| 231 | |
| 232 | pr_debug("#include <asm/asm.h>\n"); |
| 233 | pr_debug("#include <asm/regdef.h>\n"); |
| 234 | pr_debug("\n"); |
| 235 | |
| 236 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); |
Paul Burton | 780602d | 2016-04-19 09:25:03 +0100 | [diff] [blame] | 237 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 238 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); |
| 239 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); |
| 240 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); |
Ralf Baechle | 970d032 | 2012-10-18 13:54:15 +0200 | [diff] [blame] | 241 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 242 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
| 243 | #endif |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 244 | #ifdef _PAGE_NO_EXEC_SHIFT |
Paul Burton | 780602d | 2016-04-19 09:25:03 +0100 | [diff] [blame] | 245 | if (cpu_has_rixi) |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 246 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); |
Steven J. Hill | be0c37c | 2015-02-26 18:16:37 -0600 | [diff] [blame] | 247 | #endif |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 248 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); |
| 249 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); |
| 250 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); |
| 251 | pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); |
| 252 | pr_debug("\n"); |
| 253 | } |
| 254 | |
| 255 | static inline void dump_handler(const char *symbol, const u32 *handler, int count) |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 256 | { |
| 257 | int i; |
| 258 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 259 | pr_debug("LEAF(%s)\n", symbol); |
| 260 | |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 261 | pr_debug("\t.set push\n"); |
| 262 | pr_debug("\t.set noreorder\n"); |
| 263 | |
| 264 | for (i = 0; i < count; i++) |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 265 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 266 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 267 | pr_debug("\t.set\tpop\n"); |
| 268 | |
| 269 | pr_debug("\tEND(%s)\n", symbol); |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 270 | } |
| 271 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | /* The only general purpose registers allowed in TLB handlers. */ |
| 273 | #define K0 26 |
| 274 | #define K1 27 |
| 275 | |
| 276 | /* Some CP0 registers */ |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 277 | #define C0_INDEX 0, 0 |
| 278 | #define C0_ENTRYLO0 2, 0 |
| 279 | #define C0_TCBIND 2, 2 |
| 280 | #define C0_ENTRYLO1 3, 0 |
| 281 | #define C0_CONTEXT 4, 0 |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 282 | #define C0_PAGEMASK 5, 0 |
Huacai Chen | 380cd58 | 2016-03-03 09:45:12 +0800 | [diff] [blame] | 283 | #define C0_PWBASE 5, 5 |
| 284 | #define C0_PWFIELD 5, 6 |
| 285 | #define C0_PWSIZE 5, 7 |
| 286 | #define C0_PWCTL 6, 6 |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 287 | #define C0_BADVADDR 8, 0 |
Huacai Chen | 380cd58 | 2016-03-03 09:45:12 +0800 | [diff] [blame] | 288 | #define C0_PGD 9, 7 |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 289 | #define C0_ENTRYHI 10, 0 |
| 290 | #define C0_EPC 14, 0 |
| 291 | #define C0_XCONTEXT 20, 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 293 | #ifdef CONFIG_64BIT |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 294 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | #else |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 296 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | #endif |
| 298 | |
| 299 | /* The worst case length of the handler is around 18 instructions for |
| 300 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. |
| 301 | * Maximum space available is 32 instructions for R3000 and 64 |
| 302 | * instructions for R4000. |
| 303 | * |
| 304 | * We deliberately chose a buffer size of 128, so we won't scribble |
| 305 | * over anything important on overflow before we panic. |
| 306 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 307 | static u32 tlb_handler[128]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | |
| 309 | /* simply assume worst case size for labels and relocs */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 310 | static struct uasm_label labels[128]; |
| 311 | static struct uasm_reloc relocs[128]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 313 | static int check_for_high_segbits; |
Paul Burton | 00bf1c6 | 2015-09-22 11:42:52 -0700 | [diff] [blame] | 314 | static bool fill_includes_sw_bits; |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 315 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 316 | static unsigned int kscratch_used_mask; |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 317 | |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 318 | static inline int __maybe_unused c0_kscratch(void) |
| 319 | { |
| 320 | switch (current_cpu_type()) { |
| 321 | case CPU_XLP: |
| 322 | case CPU_XLR: |
| 323 | return 22; |
| 324 | default: |
| 325 | return 31; |
| 326 | } |
| 327 | } |
| 328 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 329 | static int allocate_kscratch(void) |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 330 | { |
| 331 | int r; |
| 332 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; |
| 333 | |
| 334 | r = ffs(a); |
| 335 | |
| 336 | if (r == 0) |
| 337 | return -1; |
| 338 | |
| 339 | r--; /* make it zero based */ |
| 340 | |
| 341 | kscratch_used_mask |= (1 << r); |
| 342 | |
| 343 | return r; |
| 344 | } |
| 345 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 346 | static int scratch_reg; |
| 347 | static int pgd_reg; |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 348 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 349 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 350 | static struct work_registers build_get_work_registers(u32 **p) |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 351 | { |
| 352 | struct work_registers r; |
| 353 | |
Jayachandran C | 0e6ecc1 | 2013-06-11 14:41:36 +0000 | [diff] [blame] | 354 | if (scratch_reg >= 0) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 355 | /* Save in CPU local C0_KScratch? */ |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 356 | UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 357 | r.r1 = K0; |
| 358 | r.r2 = K1; |
| 359 | r.r3 = 1; |
| 360 | return r; |
| 361 | } |
| 362 | |
| 363 | if (num_possible_cpus() > 1) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 364 | /* Get smp_processor_id */ |
Jayachandran C | c2377a4 | 2013-08-11 17:10:16 +0530 | [diff] [blame] | 365 | UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); |
| 366 | UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 367 | |
| 368 | /* handler_reg_save index in K0 */ |
| 369 | UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); |
| 370 | |
| 371 | UASM_i_LA(p, K1, (long)&handler_reg_save); |
| 372 | UASM_i_ADDU(p, K0, K0, K1); |
| 373 | } else { |
| 374 | UASM_i_LA(p, K0, (long)&handler_reg_save); |
| 375 | } |
| 376 | /* K0 now points to save area, save $1 and $2 */ |
| 377 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); |
| 378 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); |
| 379 | |
| 380 | r.r1 = K1; |
| 381 | r.r2 = 1; |
| 382 | r.r3 = 2; |
| 383 | return r; |
| 384 | } |
| 385 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 386 | static void build_restore_work_registers(u32 **p) |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 387 | { |
Jayachandran C | 0e6ecc1 | 2013-06-11 14:41:36 +0000 | [diff] [blame] | 388 | if (scratch_reg >= 0) { |
Dmitry Korotin | dd8f65a | 2019-06-24 19:05:27 +0000 | [diff] [blame] | 389 | uasm_i_ehb(p); |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 390 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 391 | return; |
| 392 | } |
| 393 | /* K0 already points to save area, restore $1 and $2 */ |
| 394 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); |
| 395 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); |
| 396 | } |
| 397 | |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 398 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
| 399 | |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 400 | /* |
| 401 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, |
| 402 | * we cannot do r3000 under these circumstances. |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 403 | * |
| 404 | * Declare pgd_current here instead of including mmu_context.h to avoid type |
| 405 | * conflicts for tlbmiss_handler_setup_pgd |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 406 | */ |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 407 | extern unsigned long pgd_current[]; |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 408 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 409 | /* |
| 410 | * The R3000 TLB handler is simple. |
| 411 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 412 | static void build_r3000_tlb_refill_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | { |
| 414 | long pgdc = (long)pgd_current; |
| 415 | u32 *p; |
| 416 | |
| 417 | memset(tlb_handler, 0, sizeof(tlb_handler)); |
| 418 | p = tlb_handler; |
| 419 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 420 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
| 421 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ |
| 422 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); |
| 423 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ |
| 424 | uasm_i_sll(&p, K0, K0, 2); |
| 425 | uasm_i_addu(&p, K1, K1, K0); |
| 426 | uasm_i_mfc0(&p, K0, C0_CONTEXT); |
| 427 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ |
| 428 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ |
| 429 | uasm_i_addu(&p, K1, K1, K0); |
| 430 | uasm_i_lw(&p, K0, 0, K1); |
| 431 | uasm_i_nop(&p); /* load delay */ |
| 432 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); |
| 433 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ |
| 434 | uasm_i_tlbwr(&p); /* cp0 delay */ |
| 435 | uasm_i_jr(&p, K1); |
| 436 | uasm_i_rfe(&p); /* branch delay */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | |
| 438 | if (p > tlb_handler + 32) |
| 439 | panic("TLB refill handler space exceeded"); |
| 440 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 441 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
| 442 | (unsigned int)(p - tlb_handler)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | |
Ralf Baechle | 91b05e6 | 2006-03-29 18:53:00 +0100 | [diff] [blame] | 444 | memcpy((void *)ebase, tlb_handler, 0x80); |
Leonid Yegoshin | 1062080 | 2014-07-11 15:18:05 -0700 | [diff] [blame] | 445 | local_flush_icache_range(ebase, ebase + 0x80); |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 446 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 447 | dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | } |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 449 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | |
| 451 | /* |
| 452 | * The R4000 TLB handler is much more complicated. We have two |
| 453 | * consecutive handler areas with 32 instructions space each. |
| 454 | * Since they aren't used at the same time, we can overflow in the |
| 455 | * other one.To keep things simple, we first assume linear space, |
| 456 | * then we relocate it to the final handler layout as needed. |
| 457 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 458 | static u32 final_handler[64]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | |
| 460 | /* |
| 461 | * Hazards |
| 462 | * |
| 463 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: |
| 464 | * 2. A timing hazard exists for the TLBP instruction. |
| 465 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 466 | * stalling_instruction |
| 467 | * TLBP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | * |
| 469 | * The JTLB is being read for the TLBP throughout the stall generated by the |
| 470 | * previous instruction. This is not really correct as the stalling instruction |
| 471 | * can modify the address used to access the JTLB. The failure symptom is that |
| 472 | * the TLBP instruction will use an address created for the stalling instruction |
| 473 | * and not the address held in C0_ENHI and thus report the wrong results. |
| 474 | * |
| 475 | * The software work-around is to not allow the instruction preceding the TLBP |
| 476 | * to stall - make it an NOP or some other instruction guaranteed not to stall. |
| 477 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 478 | * Errata 2 will not be fixed. This errata is also on the R5000. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | * |
| 480 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... |
| 481 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 482 | static void __maybe_unused build_tlb_probe_entry(u32 **p) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | { |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 484 | switch (current_cpu_type()) { |
Thomas Bogendoerfer | 326e2e1 | 2008-05-12 13:55:42 +0200 | [diff] [blame] | 485 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
Thiemo Seufer | f5b4d95 | 2005-09-09 17:11:50 +0000 | [diff] [blame] | 486 | case CPU_R4600: |
Thomas Bogendoerfer | 326e2e1 | 2008-05-12 13:55:42 +0200 | [diff] [blame] | 487 | case CPU_R4700: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | case CPU_R5000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | case CPU_NEVADA: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 490 | uasm_i_nop(p); |
| 491 | uasm_i_tlbp(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 492 | break; |
| 493 | |
| 494 | default: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 495 | uasm_i_tlbp(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 496 | break; |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | /* |
| 501 | * Write random or indexed TLB entry, and care about the hazards from |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 502 | * the preceding mtc0 and for the following eret. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | */ |
| 504 | enum tlb_write_entry { tlb_random, tlb_indexed }; |
| 505 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 506 | static void build_tlb_write_entry(u32 **p, struct uasm_label **l, |
| 507 | struct uasm_reloc **r, |
| 508 | enum tlb_write_entry wmode) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | { |
| 510 | void(*tlbw)(u32 **) = NULL; |
| 511 | |
| 512 | switch (wmode) { |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 513 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
| 514 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | } |
| 516 | |
Ralf Baechle | 9eaffa8 | 2015-03-25 13:18:27 +0100 | [diff] [blame] | 517 | if (cpu_has_mips_r2_r6) { |
| 518 | if (cpu_has_mips_r2_exec_hazard) |
David Daney | 41f0e4d | 2009-05-12 12:41:53 -0700 | [diff] [blame] | 519 | uasm_i_ehb(p); |
Ralf Baechle | 161548b | 2008-01-29 10:14:54 +0000 | [diff] [blame] | 520 | tlbw(p); |
| 521 | return; |
| 522 | } |
| 523 | |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 524 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | case CPU_R4000PC: |
| 526 | case CPU_R4000SC: |
| 527 | case CPU_R4000MC: |
| 528 | case CPU_R4400PC: |
| 529 | case CPU_R4400SC: |
| 530 | case CPU_R4400MC: |
| 531 | /* |
| 532 | * This branch uses up a mtc0 hazard nop slot and saves |
| 533 | * two nops after the tlbw instruction. |
| 534 | */ |
Ralf Baechle | 02a5417 | 2012-10-13 22:46:26 +0200 | [diff] [blame] | 535 | uasm_bgezl_hazard(p, r, hazard_instance); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | tlbw(p); |
Ralf Baechle | 02a5417 | 2012-10-13 22:46:26 +0200 | [diff] [blame] | 537 | uasm_bgezl_label(l, p, hazard_instance); |
| 538 | hazard_instance++; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 539 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | break; |
| 541 | |
| 542 | case CPU_R4600: |
| 543 | case CPU_R4700: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 544 | uasm_i_nop(p); |
Maciej W. Rozycki | 2c93e12 | 2005-06-30 10:51:01 +0000 | [diff] [blame] | 545 | tlbw(p); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 546 | uasm_i_nop(p); |
Maciej W. Rozycki | 2c93e12 | 2005-06-30 10:51:01 +0000 | [diff] [blame] | 547 | break; |
| 548 | |
Ralf Baechle | 359187d | 2012-10-16 22:13:06 +0200 | [diff] [blame] | 549 | case CPU_R5000: |
Ralf Baechle | 359187d | 2012-10-16 22:13:06 +0200 | [diff] [blame] | 550 | case CPU_NEVADA: |
| 551 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
| 552 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
| 553 | tlbw(p); |
| 554 | break; |
| 555 | |
Maciej W. Rozycki | 2c93e12 | 2005-06-30 10:51:01 +0000 | [diff] [blame] | 556 | case CPU_R4300: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | case CPU_5KC: |
| 558 | case CPU_TX49XX: |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 559 | case CPU_PR4450: |
Jayachandran C | efa0f81 | 2011-05-07 01:36:21 +0530 | [diff] [blame] | 560 | case CPU_XLR: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 561 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 562 | tlbw(p); |
| 563 | break; |
| 564 | |
| 565 | case CPU_R10000: |
| 566 | case CPU_R12000: |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 567 | case CPU_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 568 | case CPU_R16000: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 569 | case CPU_4KC: |
Thomas Bogendoerfer | b1ec4c8 | 2008-03-26 16:42:54 +0100 | [diff] [blame] | 570 | case CPU_4KEC: |
Steven J. Hill | 113c62d | 2012-07-06 23:56:00 +0200 | [diff] [blame] | 571 | case CPU_M14KC: |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 572 | case CPU_M14KEC: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | case CPU_SB1: |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 574 | case CPU_SB1A: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | case CPU_4KSC: |
| 576 | case CPU_20KC: |
| 577 | case CPU_25KF: |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 578 | case CPU_BMIPS32: |
| 579 | case CPU_BMIPS3300: |
| 580 | case CPU_BMIPS4350: |
| 581 | case CPU_BMIPS4380: |
| 582 | case CPU_BMIPS5000: |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 583 | case CPU_LOONGSON2: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 584 | case CPU_LOONGSON3: |
Shinya Kuribayashi | a644b27 | 2009-03-03 18:05:51 +0900 | [diff] [blame] | 585 | case CPU_R5500: |
Maciej W. Rozycki | 8df5bea | 2006-08-23 14:26:50 +0100 | [diff] [blame] | 586 | if (m4kc_tlbp_war()) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 587 | uasm_i_nop(p); |
Manuel Lauss | 2f794d0 | 2009-03-25 17:49:30 +0100 | [diff] [blame] | 588 | case CPU_ALCHEMY: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 589 | tlbw(p); |
| 590 | break; |
| 591 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | case CPU_RM7000: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 593 | uasm_i_nop(p); |
| 594 | uasm_i_nop(p); |
| 595 | uasm_i_nop(p); |
| 596 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | tlbw(p); |
| 598 | break; |
| 599 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | case CPU_VR4111: |
| 601 | case CPU_VR4121: |
| 602 | case CPU_VR4122: |
| 603 | case CPU_VR4181: |
| 604 | case CPU_VR4181A: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 605 | uasm_i_nop(p); |
| 606 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | tlbw(p); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 608 | uasm_i_nop(p); |
| 609 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | break; |
| 611 | |
| 612 | case CPU_VR4131: |
| 613 | case CPU_VR4133: |
Ralf Baechle | 7623deb | 2005-08-29 16:49:55 +0000 | [diff] [blame] | 614 | case CPU_R5432: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 615 | uasm_i_nop(p); |
| 616 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | tlbw(p); |
| 618 | break; |
| 619 | |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 620 | case CPU_JZRISC: |
| 621 | tlbw(p); |
| 622 | uasm_i_nop(p); |
| 623 | break; |
| 624 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | default: |
| 626 | panic("No TLB refill handler yet (CPU type: %d)", |
Wu Zhangjin | d7b1205 | 2010-12-26 04:42:37 +0800 | [diff] [blame] | 627 | current_cpu_type()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | break; |
| 629 | } |
| 630 | } |
| 631 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 632 | static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
| 633 | unsigned int reg) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 634 | { |
Paul Burton | 2caa89b | 2016-04-19 09:25:09 +0100 | [diff] [blame] | 635 | if (_PAGE_GLOBAL_SHIFT == 0) { |
| 636 | /* pte_t is already in EntryLo format */ |
| 637 | return; |
| 638 | } |
| 639 | |
Nathan Chancellor | cbc4467 | 2019-08-11 20:31:20 -0700 | [diff] [blame] | 640 | if (cpu_has_rixi && !!_PAGE_NO_EXEC) { |
Paul Burton | 00bf1c6 | 2015-09-22 11:42:52 -0700 | [diff] [blame] | 641 | if (fill_includes_sw_bits) { |
| 642 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
| 643 | } else { |
| 644 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); |
| 645 | UASM_i_ROTR(p, reg, reg, |
| 646 | ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); |
| 647 | } |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 648 | } else { |
Ralf Baechle | 34adb28 | 2014-11-22 00:16:48 +0100 | [diff] [blame] | 649 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
David Daney | 3be6022 | 2010-04-28 12:16:17 -0700 | [diff] [blame] | 650 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 651 | #else |
| 652 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
| 653 | #endif |
| 654 | } |
| 655 | } |
| 656 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 657 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 658 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 659 | static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, |
| 660 | unsigned int tmp, enum label_id lid, |
| 661 | int restore_scratch) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 662 | { |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 663 | if (restore_scratch) { |
Paul Burton | bfdf982 | 2019-10-18 15:38:48 -0700 | [diff] [blame] | 664 | /* |
| 665 | * Ensure the MFC0 below observes the value written to the |
| 666 | * KScratch register by the prior MTC0. |
| 667 | */ |
| 668 | if (scratch_reg >= 0) |
| 669 | uasm_i_ehb(p); |
| 670 | |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 671 | /* Reset default page size */ |
| 672 | if (PM_DEFAULT_MASK >> 16) { |
| 673 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); |
| 674 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); |
| 675 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
| 676 | uasm_il_b(p, r, lid); |
| 677 | } else if (PM_DEFAULT_MASK) { |
| 678 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); |
| 679 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
| 680 | uasm_il_b(p, r, lid); |
| 681 | } else { |
| 682 | uasm_i_mtc0(p, 0, C0_PAGEMASK); |
| 683 | uasm_il_b(p, r, lid); |
| 684 | } |
Paul Burton | bfdf982 | 2019-10-18 15:38:48 -0700 | [diff] [blame] | 685 | if (scratch_reg >= 0) |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 686 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
Paul Burton | bfdf982 | 2019-10-18 15:38:48 -0700 | [diff] [blame] | 687 | else |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 688 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 689 | } else { |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 690 | /* Reset default page size */ |
| 691 | if (PM_DEFAULT_MASK >> 16) { |
| 692 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); |
| 693 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); |
| 694 | uasm_il_b(p, r, lid); |
| 695 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
| 696 | } else if (PM_DEFAULT_MASK) { |
| 697 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); |
| 698 | uasm_il_b(p, r, lid); |
| 699 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
| 700 | } else { |
| 701 | uasm_il_b(p, r, lid); |
| 702 | uasm_i_mtc0(p, 0, C0_PAGEMASK); |
| 703 | } |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 704 | } |
| 705 | } |
| 706 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 707 | static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, |
| 708 | struct uasm_reloc **r, |
| 709 | unsigned int tmp, |
| 710 | enum tlb_write_entry wmode, |
| 711 | int restore_scratch) |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 712 | { |
| 713 | /* Set huge page tlb entry size */ |
| 714 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); |
| 715 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); |
| 716 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
| 717 | |
| 718 | build_tlb_write_entry(p, l, r, wmode); |
| 719 | |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 720 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | /* |
| 724 | * Check if Huge PTE is present, if so then jump to LABEL. |
| 725 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 726 | static void |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 727 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 728 | unsigned int pmd, int lid) |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 729 | { |
| 730 | UASM_i_LW(p, tmp, 0, pmd); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 731 | if (use_bbit_insns()) { |
| 732 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); |
| 733 | } else { |
| 734 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); |
| 735 | uasm_il_bnez(p, r, tmp, lid); |
| 736 | } |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 737 | } |
| 738 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 739 | static void build_huge_update_entries(u32 **p, unsigned int pte, |
| 740 | unsigned int tmp) |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 741 | { |
| 742 | int small_sequence; |
| 743 | |
| 744 | /* |
| 745 | * A huge PTE describes an area the size of the |
| 746 | * configured huge page size. This is twice the |
| 747 | * of the large TLB entry size we intend to use. |
| 748 | * A TLB entry half the size of the configured |
| 749 | * huge page size is configured into entrylo0 |
| 750 | * and entrylo1 to cover the contiguous huge PTE |
| 751 | * address space. |
| 752 | */ |
| 753 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; |
| 754 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 755 | /* We can clobber tmp. It isn't used after this.*/ |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 756 | if (!small_sequence) |
| 757 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); |
| 758 | |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 759 | build_convert_pte_to_entrylo(p, pte); |
David Daney | 9b8c389 | 2010-02-10 15:12:44 -0800 | [diff] [blame] | 760 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 761 | /* convert to entrylo1 */ |
| 762 | if (small_sequence) |
| 763 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); |
| 764 | else |
| 765 | UASM_i_ADDU(p, pte, pte, tmp); |
| 766 | |
David Daney | 9b8c389 | 2010-02-10 15:12:44 -0800 | [diff] [blame] | 767 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 768 | } |
| 769 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 770 | static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, |
| 771 | struct uasm_label **l, |
| 772 | unsigned int pte, |
Huacai Chen | 59b8725 | 2017-03-16 21:00:27 +0800 | [diff] [blame] | 773 | unsigned int ptr, |
| 774 | unsigned int flush) |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 775 | { |
| 776 | #ifdef CONFIG_SMP |
| 777 | UASM_i_SC(p, pte, 0, ptr); |
| 778 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); |
| 779 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ |
| 780 | #else |
| 781 | UASM_i_SW(p, pte, 0, ptr); |
| 782 | #endif |
Huacai Chen | 59b8725 | 2017-03-16 21:00:27 +0800 | [diff] [blame] | 783 | if (cpu_has_ftlb && flush) { |
| 784 | BUG_ON(!cpu_has_tlbinv); |
| 785 | |
| 786 | UASM_i_MFC0(p, ptr, C0_ENTRYHI); |
| 787 | uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); |
| 788 | UASM_i_MTC0(p, ptr, C0_ENTRYHI); |
| 789 | build_tlb_write_entry(p, l, r, tlb_indexed); |
| 790 | |
| 791 | uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); |
| 792 | UASM_i_MTC0(p, ptr, C0_ENTRYHI); |
| 793 | build_huge_update_entries(p, pte, ptr); |
| 794 | build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); |
| 795 | |
| 796 | return; |
| 797 | } |
| 798 | |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 799 | build_huge_update_entries(p, pte, ptr); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 800 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 801 | } |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 802 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 803 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 804 | #ifdef CONFIG_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 805 | /* |
| 806 | * TMP and PTR are scratch. |
| 807 | * TMP will be clobbered, PTR will hold the pmd entry. |
| 808 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 809 | static void |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 810 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | unsigned int tmp, unsigned int ptr) |
| 812 | { |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 813 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | long pgdc = (long)pgd_current; |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 815 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | /* |
| 817 | * The vmalloc handling is not in the hotpath. |
| 818 | */ |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 819 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 820 | |
| 821 | if (check_for_high_segbits) { |
| 822 | /* |
| 823 | * The kernel currently implicitely assumes that the |
| 824 | * MIPS SEGBITS parameter for the processor is |
| 825 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never |
| 826 | * allocate virtual addresses outside the maximum |
| 827 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But |
| 828 | * that doesn't prevent user code from accessing the |
| 829 | * higher xuseg addresses. Here, we make sure that |
| 830 | * everything but the lower xuseg addresses goes down |
| 831 | * the module_alloc/vmalloc path. |
| 832 | */ |
| 833 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); |
| 834 | uasm_il_bnez(p, r, ptr, label_vmalloc); |
| 835 | } else { |
| 836 | uasm_il_bltz(p, r, tmp, label_vmalloc); |
| 837 | } |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 838 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 840 | if (pgd_reg != -1) { |
| 841 | /* pgd is in pgd_reg */ |
Huacai Chen | 380cd58 | 2016-03-03 09:45:12 +0800 | [diff] [blame] | 842 | if (cpu_has_ldpte) |
| 843 | UASM_i_MFC0(p, ptr, C0_PWBASE); |
| 844 | else |
| 845 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 846 | } else { |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 847 | #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 848 | /* |
| 849 | * &pgd << 11 stored in CONTEXT [23..63]. |
| 850 | */ |
| 851 | UASM_i_MFC0(p, ptr, C0_CONTEXT); |
| 852 | |
| 853 | /* Clear lower 23 bits of context. */ |
| 854 | uasm_i_dins(p, ptr, 0, 0, 23); |
| 855 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 856 | /* 1 0 1 0 1 << 6 xkphys cached */ |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 857 | uasm_i_ori(p, ptr, ptr, 0x540); |
| 858 | uasm_i_drotr(p, ptr, ptr, 11); |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 859 | #elif defined(CONFIG_SMP) |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 860 | UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); |
| 861 | uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); |
| 862 | UASM_i_LA_mostly(p, tmp, pgdc); |
| 863 | uasm_i_daddu(p, ptr, ptr, tmp); |
| 864 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
| 865 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 866 | #else |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 867 | UASM_i_LA_mostly(p, ptr, pgdc); |
| 868 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 869 | #endif |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 870 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 872 | uasm_l_vmalloc_done(l, *p); |
Ralf Baechle | 242954b | 2006-10-24 02:29:01 +0100 | [diff] [blame] | 873 | |
David Daney | 3be6022 | 2010-04-28 12:16:17 -0700 | [diff] [blame] | 874 | /* get pgd offset in bytes */ |
| 875 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); |
Ralf Baechle | 242954b | 2006-10-24 02:29:01 +0100 | [diff] [blame] | 876 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 877 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); |
| 878 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ |
David Daney | 325f8a0 | 2009-12-04 13:52:36 -0800 | [diff] [blame] | 879 | #ifndef __PAGETABLE_PMD_FOLDED |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 880 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
| 881 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ |
David Daney | 3be6022 | 2010-04-28 12:16:17 -0700 | [diff] [blame] | 882 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 883 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
| 884 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ |
David Daney | 325f8a0 | 2009-12-04 13:52:36 -0800 | [diff] [blame] | 885 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | /* |
| 889 | * BVADDR is the faulting address, PTR is scratch. |
| 890 | * PTR will hold the pgd for vmalloc. |
| 891 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 892 | static void |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 893 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 894 | unsigned int bvaddr, unsigned int ptr, |
| 895 | enum vmalloc64_mode mode) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | { |
| 897 | long swpd = (long)swapper_pg_dir; |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 898 | int single_insn_swpd; |
| 899 | int did_vmalloc_branch = 0; |
| 900 | |
| 901 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 902 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 903 | uasm_l_vmalloc(l, *p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 904 | |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 905 | if (mode != not_refill && check_for_high_segbits) { |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 906 | if (single_insn_swpd) { |
| 907 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); |
| 908 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); |
| 909 | did_vmalloc_branch = 1; |
| 910 | /* fall through */ |
| 911 | } else { |
| 912 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); |
| 913 | } |
| 914 | } |
| 915 | if (!did_vmalloc_branch) { |
James Hogan | 2f8f8c0 | 2016-07-08 14:05:56 +0100 | [diff] [blame] | 916 | if (single_insn_swpd) { |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 917 | uasm_il_b(p, r, label_vmalloc_done); |
| 918 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); |
| 919 | } else { |
| 920 | UASM_i_LA_mostly(p, ptr, swpd); |
| 921 | uasm_il_b(p, r, label_vmalloc_done); |
| 922 | if (uasm_in_compat_space_p(swpd)) |
| 923 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); |
| 924 | else |
| 925 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); |
| 926 | } |
| 927 | } |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 928 | if (mode != not_refill && check_for_high_segbits) { |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 929 | uasm_l_large_segbits_fault(l, *p); |
Paul Burton | bfdf982 | 2019-10-18 15:38:48 -0700 | [diff] [blame] | 930 | |
| 931 | if (mode == refill_scratch && scratch_reg >= 0) |
| 932 | uasm_i_ehb(p); |
| 933 | |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 934 | /* |
| 935 | * We get here if we are an xsseg address, or if we are |
| 936 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. |
| 937 | * |
| 938 | * Ignoring xsseg (assume disabled so would generate |
| 939 | * (address errors?), the only remaining possibility |
| 940 | * is the upper xuseg addresses. On processors with |
| 941 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these |
| 942 | * addresses would have taken an address error. We try |
| 943 | * to mimic that here by taking a load/istream page |
| 944 | * fault. |
| 945 | */ |
| 946 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); |
| 947 | uasm_i_jr(p, ptr); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 948 | |
| 949 | if (mode == refill_scratch) { |
Paul Burton | bfdf982 | 2019-10-18 15:38:48 -0700 | [diff] [blame] | 950 | if (scratch_reg >= 0) |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 951 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
Paul Burton | bfdf982 | 2019-10-18 15:38:48 -0700 | [diff] [blame] | 952 | else |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 953 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); |
| 954 | } else { |
| 955 | uasm_i_nop(p); |
| 956 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | } |
| 958 | } |
| 959 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 960 | #else /* !CONFIG_64BIT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | |
| 962 | /* |
| 963 | * TMP and PTR are scratch. |
| 964 | * TMP will be clobbered, PTR will hold the pgd entry. |
| 965 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 966 | static void __maybe_unused |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
| 968 | { |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 969 | if (pgd_reg != -1) { |
| 970 | /* pgd is in pgd_reg */ |
| 971 | uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); |
| 972 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
| 973 | } else { |
| 974 | long pgdc = (long)pgd_current; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 976 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | #ifdef CONFIG_SMP |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 978 | uasm_i_mfc0(p, ptr, SMP_CPUID_REG); |
| 979 | UASM_i_LA_mostly(p, tmp, pgdc); |
| 980 | uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); |
| 981 | uasm_i_addu(p, ptr, tmp, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 982 | #else |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 983 | UASM_i_LA_mostly(p, ptr, pgdc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 984 | #endif |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 985 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
| 986 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); |
| 987 | } |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 988 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ |
| 989 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); |
| 990 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 991 | } |
| 992 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 993 | #endif /* !CONFIG_64BIT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 994 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 995 | static void build_adjust_context(u32 **p, unsigned int ctx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | { |
Ralf Baechle | 242954b | 2006-10-24 02:29:01 +0100 | [diff] [blame] | 997 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
| 999 | |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1000 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1001 | case CPU_VR41XX: |
| 1002 | case CPU_VR4111: |
| 1003 | case CPU_VR4121: |
| 1004 | case CPU_VR4122: |
| 1005 | case CPU_VR4131: |
| 1006 | case CPU_VR4181: |
| 1007 | case CPU_VR4181A: |
| 1008 | case CPU_VR4133: |
| 1009 | shift += 2; |
| 1010 | break; |
| 1011 | |
| 1012 | default: |
| 1013 | break; |
| 1014 | } |
| 1015 | |
| 1016 | if (shift) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1017 | UASM_i_SRL(p, ctx, ctx, shift); |
| 1018 | uasm_i_andi(p, ctx, ctx, mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1019 | } |
| 1020 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1021 | static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1022 | { |
| 1023 | /* |
| 1024 | * Bug workaround for the Nevada. It seems as if under certain |
| 1025 | * circumstances the move from cp0_context might produce a |
| 1026 | * bogus result when the mfc0 instruction and its consumer are |
| 1027 | * in a different cacheline or a load instruction, probably any |
| 1028 | * memory reference, is between them. |
| 1029 | */ |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1030 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1031 | case CPU_NEVADA: |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1032 | UASM_i_LW(p, ptr, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1033 | GET_CONTEXT(p, tmp); /* get context reg */ |
| 1034 | break; |
| 1035 | |
| 1036 | default: |
| 1037 | GET_CONTEXT(p, tmp); /* get context reg */ |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1038 | UASM_i_LW(p, ptr, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1039 | break; |
| 1040 | } |
| 1041 | |
| 1042 | build_adjust_context(p, tmp); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1043 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1044 | } |
| 1045 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1046 | static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1047 | { |
Paul Burton | 2caa89b | 2016-04-19 09:25:09 +0100 | [diff] [blame] | 1048 | int pte_off_even = 0; |
| 1049 | int pte_off_odd = sizeof(pte_t); |
Paul Burton | 7b2cb64 | 2016-04-19 09:25:05 +0100 | [diff] [blame] | 1050 | |
Paul Burton | 2caa89b | 2016-04-19 09:25:09 +0100 | [diff] [blame] | 1051 | #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) |
| 1052 | /* The low 32 bits of EntryLo is stored in pte_high */ |
| 1053 | pte_off_even += offsetof(pte_t, pte_high); |
| 1054 | pte_off_odd += offsetof(pte_t, pte_high); |
| 1055 | #endif |
| 1056 | |
Masahiro Yamada | 97f2645 | 2016-08-03 13:45:50 -0700 | [diff] [blame] | 1057 | if (IS_ENABLED(CONFIG_XPA)) { |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 1058 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 1059 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 1060 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); |
Paul Burton | 7b2cb64 | 2016-04-19 09:25:05 +0100 | [diff] [blame] | 1061 | |
James Hogan | 4b6f99d | 2016-04-19 09:25:10 +0100 | [diff] [blame] | 1062 | if (cpu_has_xpa && !mips_xpa_disabled) { |
| 1063 | uasm_i_lw(p, tmp, 0, ptep); |
| 1064 | uasm_i_ext(p, tmp, tmp, 0, 24); |
| 1065 | uasm_i_mthc0(p, tmp, C0_ENTRYLO0); |
| 1066 | } |
James Hogan | f383219 | 2016-04-19 09:25:06 +0100 | [diff] [blame] | 1067 | |
| 1068 | uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ |
| 1069 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
| 1070 | UASM_i_MTC0(p, tmp, C0_ENTRYLO1); |
| 1071 | |
James Hogan | 4b6f99d | 2016-04-19 09:25:10 +0100 | [diff] [blame] | 1072 | if (cpu_has_xpa && !mips_xpa_disabled) { |
| 1073 | uasm_i_lw(p, tmp, sizeof(pte_t), ptep); |
| 1074 | uasm_i_ext(p, tmp, tmp, 0, 24); |
| 1075 | uasm_i_mthc0(p, tmp, C0_ENTRYLO1); |
| 1076 | } |
Paul Burton | 7b2cb64 | 2016-04-19 09:25:05 +0100 | [diff] [blame] | 1077 | return; |
| 1078 | } |
| 1079 | |
Paul Burton | 2caa89b | 2016-04-19 09:25:09 +0100 | [diff] [blame] | 1080 | UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ |
| 1081 | UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1082 | if (r45k_bvahwbug()) |
| 1083 | build_tlb_probe_entry(p); |
Paul Burton | 974a0b6 | 2015-09-22 11:42:49 -0700 | [diff] [blame] | 1084 | build_convert_pte_to_entrylo(p, tmp); |
| 1085 | if (r4k_250MHZhwbug()) |
| 1086 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); |
| 1087 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
| 1088 | build_convert_pte_to_entrylo(p, ptep); |
| 1089 | if (r45k_bvahwbug()) |
| 1090 | uasm_i_mfc0(p, tmp, C0_INDEX); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | if (r4k_250MHZhwbug()) |
David Daney | 9b8c389 | 2010-02-10 15:12:44 -0800 | [diff] [blame] | 1092 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
| 1093 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1094 | } |
| 1095 | |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1096 | struct mips_huge_tlb_info { |
| 1097 | int huge_pte; |
| 1098 | int restore_scratch; |
David Daney | 9e0f162 | 2014-10-20 15:34:23 -0700 | [diff] [blame] | 1099 | bool need_reload_pte; |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1100 | }; |
| 1101 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1102 | static struct mips_huge_tlb_info |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1103 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, |
| 1104 | struct uasm_reloc **r, unsigned int tmp, |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1105 | unsigned int ptr, int c0_scratch_reg) |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1106 | { |
| 1107 | struct mips_huge_tlb_info rv; |
| 1108 | unsigned int even, odd; |
| 1109 | int vmalloc_branch_delay_filled = 0; |
| 1110 | const int scratch = 1; /* Our extra working register */ |
| 1111 | |
| 1112 | rv.huge_pte = scratch; |
| 1113 | rv.restore_scratch = 0; |
David Daney | 9e0f162 | 2014-10-20 15:34:23 -0700 | [diff] [blame] | 1114 | rv.need_reload_pte = false; |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1115 | |
| 1116 | if (check_for_high_segbits) { |
| 1117 | UASM_i_MFC0(p, tmp, C0_BADVADDR); |
| 1118 | |
| 1119 | if (pgd_reg != -1) |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1120 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1121 | else |
| 1122 | UASM_i_MFC0(p, ptr, C0_CONTEXT); |
| 1123 | |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1124 | if (c0_scratch_reg >= 0) |
| 1125 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1126 | else |
| 1127 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); |
| 1128 | |
| 1129 | uasm_i_dsrl_safe(p, scratch, tmp, |
| 1130 | PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); |
| 1131 | uasm_il_bnez(p, r, scratch, label_vmalloc); |
| 1132 | |
| 1133 | if (pgd_reg == -1) { |
| 1134 | vmalloc_branch_delay_filled = 1; |
| 1135 | /* Clear lower 23 bits of context. */ |
| 1136 | uasm_i_dins(p, ptr, 0, 0, 23); |
| 1137 | } |
| 1138 | } else { |
| 1139 | if (pgd_reg != -1) |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1140 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1141 | else |
| 1142 | UASM_i_MFC0(p, ptr, C0_CONTEXT); |
| 1143 | |
| 1144 | UASM_i_MFC0(p, tmp, C0_BADVADDR); |
| 1145 | |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1146 | if (c0_scratch_reg >= 0) |
| 1147 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1148 | else |
| 1149 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); |
| 1150 | |
| 1151 | if (pgd_reg == -1) |
| 1152 | /* Clear lower 23 bits of context. */ |
| 1153 | uasm_i_dins(p, ptr, 0, 0, 23); |
| 1154 | |
| 1155 | uasm_il_bltz(p, r, tmp, label_vmalloc); |
| 1156 | } |
| 1157 | |
| 1158 | if (pgd_reg == -1) { |
| 1159 | vmalloc_branch_delay_filled = 1; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1160 | /* 1 0 1 0 1 << 6 xkphys cached */ |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1161 | uasm_i_ori(p, ptr, ptr, 0x540); |
| 1162 | uasm_i_drotr(p, ptr, ptr, 11); |
| 1163 | } |
| 1164 | |
| 1165 | #ifdef __PAGETABLE_PMD_FOLDED |
| 1166 | #define LOC_PTEP scratch |
| 1167 | #else |
| 1168 | #define LOC_PTEP ptr |
| 1169 | #endif |
| 1170 | |
| 1171 | if (!vmalloc_branch_delay_filled) |
| 1172 | /* get pgd offset in bytes */ |
| 1173 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); |
| 1174 | |
| 1175 | uasm_l_vmalloc_done(l, *p); |
| 1176 | |
| 1177 | /* |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1178 | * tmp ptr |
| 1179 | * fall-through case = badvaddr *pgd_current |
| 1180 | * vmalloc case = badvaddr swapper_pg_dir |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1181 | */ |
| 1182 | |
| 1183 | if (vmalloc_branch_delay_filled) |
| 1184 | /* get pgd offset in bytes */ |
| 1185 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); |
| 1186 | |
| 1187 | #ifdef __PAGETABLE_PMD_FOLDED |
| 1188 | GET_CONTEXT(p, tmp); /* get context reg */ |
| 1189 | #endif |
| 1190 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); |
| 1191 | |
| 1192 | if (use_lwx_insns()) { |
| 1193 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); |
| 1194 | } else { |
| 1195 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ |
| 1196 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ |
| 1197 | } |
| 1198 | |
| 1199 | #ifndef __PAGETABLE_PMD_FOLDED |
| 1200 | /* get pmd offset in bytes */ |
| 1201 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); |
| 1202 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); |
| 1203 | GET_CONTEXT(p, tmp); /* get context reg */ |
| 1204 | |
| 1205 | if (use_lwx_insns()) { |
| 1206 | UASM_i_LWX(p, scratch, scratch, ptr); |
| 1207 | } else { |
| 1208 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ |
| 1209 | UASM_i_LW(p, scratch, 0, ptr); |
| 1210 | } |
| 1211 | #endif |
| 1212 | /* Adjust the context during the load latency. */ |
| 1213 | build_adjust_context(p, tmp); |
| 1214 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 1215 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1216 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
| 1217 | /* |
| 1218 | * The in the LWX case we don't want to do the load in the |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1219 | * delay slot. It cannot issue in the same cycle and may be |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1220 | * speculative and unneeded. |
| 1221 | */ |
| 1222 | if (use_lwx_insns()) |
| 1223 | uasm_i_nop(p); |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 1224 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1225 | |
| 1226 | |
| 1227 | /* build_update_entries */ |
| 1228 | if (use_lwx_insns()) { |
| 1229 | even = ptr; |
| 1230 | odd = tmp; |
| 1231 | UASM_i_LWX(p, even, scratch, tmp); |
| 1232 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); |
| 1233 | UASM_i_LWX(p, odd, scratch, tmp); |
| 1234 | } else { |
| 1235 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ |
| 1236 | even = tmp; |
| 1237 | odd = ptr; |
| 1238 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ |
| 1239 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ |
| 1240 | } |
Steven J. Hill | 05857c6 | 2012-09-13 16:51:46 -0500 | [diff] [blame] | 1241 | if (cpu_has_rixi) { |
David Daney | 748e787 | 2012-08-23 10:02:03 -0700 | [diff] [blame] | 1242 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1243 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
David Daney | 748e787 | 2012-08-23 10:02:03 -0700 | [diff] [blame] | 1244 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1245 | } else { |
| 1246 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); |
| 1247 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
| 1248 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
| 1249 | } |
| 1250 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ |
| 1251 | |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1252 | if (c0_scratch_reg >= 0) { |
Dmitry Korotin | dd8f65a | 2019-06-24 19:05:27 +0000 | [diff] [blame] | 1253 | uasm_i_ehb(p); |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1254 | UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1255 | build_tlb_write_entry(p, l, r, tlb_random); |
| 1256 | uasm_l_leave(l, *p); |
| 1257 | rv.restore_scratch = 1; |
| 1258 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { |
| 1259 | build_tlb_write_entry(p, l, r, tlb_random); |
| 1260 | uasm_l_leave(l, *p); |
| 1261 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); |
| 1262 | } else { |
| 1263 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); |
| 1264 | build_tlb_write_entry(p, l, r, tlb_random); |
| 1265 | uasm_l_leave(l, *p); |
| 1266 | rv.restore_scratch = 1; |
| 1267 | } |
| 1268 | |
| 1269 | uasm_i_eret(p); /* return from trap */ |
| 1270 | |
| 1271 | return rv; |
| 1272 | } |
| 1273 | |
David Daney | e6f72d3 | 2009-05-20 11:40:58 -0700 | [diff] [blame] | 1274 | /* |
| 1275 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception |
| 1276 | * because EXL == 0. If we wrap, we can also use the 32 instruction |
| 1277 | * slots before the XTLB refill exception handler which belong to the |
| 1278 | * unused TLB refill exception. |
| 1279 | */ |
| 1280 | #define MIPS64_REFILL_INSNS 32 |
| 1281 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1282 | static void build_r4000_tlb_refill_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1283 | { |
| 1284 | u32 *p = tlb_handler; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1285 | struct uasm_label *l = labels; |
| 1286 | struct uasm_reloc *r = relocs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | u32 *f; |
| 1288 | unsigned int final_len; |
Ralf Baechle | 4a9040f | 2011-03-29 10:54:54 +0200 | [diff] [blame] | 1289 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
| 1290 | enum vmalloc64_mode vmalloc_mode __maybe_unused; |
David Daney | 18280ed | 2014-05-28 23:52:13 +0200 | [diff] [blame] | 1291 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1292 | memset(tlb_handler, 0, sizeof(tlb_handler)); |
| 1293 | memset(labels, 0, sizeof(labels)); |
| 1294 | memset(relocs, 0, sizeof(relocs)); |
| 1295 | memset(final_handler, 0, sizeof(final_handler)); |
| 1296 | |
David Daney | 18280ed | 2014-05-28 23:52:13 +0200 | [diff] [blame] | 1297 | if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1298 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, |
| 1299 | scratch_reg); |
| 1300 | vmalloc_mode = refill_scratch; |
| 1301 | } else { |
| 1302 | htlb_info.huge_pte = K0; |
| 1303 | htlb_info.restore_scratch = 0; |
David Daney | 9e0f162 | 2014-10-20 15:34:23 -0700 | [diff] [blame] | 1304 | htlb_info.need_reload_pte = true; |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1305 | vmalloc_mode = refill_noscratch; |
| 1306 | /* |
| 1307 | * create the plain linear handler |
| 1308 | */ |
| 1309 | if (bcm1250_m3_war()) { |
| 1310 | unsigned int segbits = 44; |
| 1311 | |
| 1312 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); |
| 1313 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); |
| 1314 | uasm_i_xor(&p, K0, K0, K1); |
| 1315 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
| 1316 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); |
| 1317 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); |
| 1318 | uasm_i_or(&p, K0, K0, K1); |
| 1319 | uasm_il_bnez(&p, &r, K0, label_leave); |
| 1320 | /* No need for uasm_i_nop */ |
| 1321 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1322 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 1323 | #ifdef CONFIG_64BIT |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1324 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | #else |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1326 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1327 | #endif |
| 1328 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 1329 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1330 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 1331 | #endif |
| 1332 | |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1333 | build_get_ptep(&p, K0, K1); |
| 1334 | build_update_entries(&p, K0, K1); |
| 1335 | build_tlb_write_entry(&p, &l, &r, tlb_random); |
| 1336 | uasm_l_leave(&l, p); |
| 1337 | uasm_i_eret(&p); /* return from trap */ |
| 1338 | } |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 1339 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 1340 | uasm_l_tlb_huge_update(&l, p); |
David Daney | 9e0f162 | 2014-10-20 15:34:23 -0700 | [diff] [blame] | 1341 | if (htlb_info.need_reload_pte) |
| 1342 | UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1343 | build_huge_update_entries(&p, htlb_info.huge_pte, K1); |
| 1344 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, |
| 1345 | htlb_info.restore_scratch); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 1346 | #endif |
| 1347 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 1348 | #ifdef CONFIG_64BIT |
David Daney | 2c8c53e | 2010-12-27 18:07:57 -0800 | [diff] [blame] | 1349 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1350 | #endif |
| 1351 | |
| 1352 | /* |
| 1353 | * Overflow check: For the 64bit handler, we need at least one |
| 1354 | * free instruction slot for the wrap-around branch. In worst |
| 1355 | * case, if the intended insertion point is a delay slot, we |
Matt LaPlante | 4b3f686 | 2006-10-03 22:21:02 +0200 | [diff] [blame] | 1356 | * need three, with the second nop'ed and the third being |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1357 | * unused. |
| 1358 | */ |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1359 | switch (boot_cpu_type()) { |
| 1360 | default: |
| 1361 | if (sizeof(long) == 4) { |
| 1362 | case CPU_LOONGSON2: |
| 1363 | /* Loongson2 ebase is different than r4k, we have more space */ |
| 1364 | if ((p - tlb_handler) > 64) |
| 1365 | panic("TLB refill handler space exceeded"); |
| 1366 | /* |
| 1367 | * Now fold the handler in the TLB refill handler space. |
| 1368 | */ |
| 1369 | f = final_handler; |
| 1370 | /* Simplest case, just copy the handler. */ |
| 1371 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
| 1372 | final_len = p - tlb_handler; |
| 1373 | break; |
| 1374 | } else { |
| 1375 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
| 1376 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) |
| 1377 | && uasm_insn_has_bdelay(relocs, |
| 1378 | tlb_handler + MIPS64_REFILL_INSNS - 3))) |
| 1379 | panic("TLB refill handler space exceeded"); |
| 1380 | /* |
| 1381 | * Now fold the handler in the TLB refill handler space. |
| 1382 | */ |
| 1383 | f = final_handler + MIPS64_REFILL_INSNS; |
| 1384 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { |
| 1385 | /* Just copy the handler. */ |
| 1386 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
| 1387 | final_len = p - tlb_handler; |
| 1388 | } else { |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 1389 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1390 | const enum label_id ls = label_tlb_huge_update; |
David Daney | 95affdd | 2009-05-20 11:40:59 -0700 | [diff] [blame] | 1391 | #else |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1392 | const enum label_id ls = label_vmalloc; |
David Daney | 95affdd | 2009-05-20 11:40:59 -0700 | [diff] [blame] | 1393 | #endif |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1394 | u32 *split; |
| 1395 | int ov = 0; |
| 1396 | int i; |
David Daney | 95affdd | 2009-05-20 11:40:59 -0700 | [diff] [blame] | 1397 | |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1398 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) |
| 1399 | ; |
| 1400 | BUG_ON(i == ARRAY_SIZE(labels)); |
| 1401 | split = labels[i].addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1402 | |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1403 | /* |
| 1404 | * See if we have overflown one way or the other. |
| 1405 | */ |
| 1406 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
| 1407 | split < p - MIPS64_REFILL_INSNS) |
| 1408 | ov = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1409 | |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1410 | if (ov) { |
| 1411 | /* |
| 1412 | * Split two instructions before the end. One |
| 1413 | * for the branch and one for the instruction |
| 1414 | * in the delay slot. |
| 1415 | */ |
| 1416 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; |
David Daney | 95affdd | 2009-05-20 11:40:59 -0700 | [diff] [blame] | 1417 | |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1418 | /* |
| 1419 | * If the branch would fall in a delay slot, |
| 1420 | * we must back up an additional instruction |
| 1421 | * so that it is no longer in a delay slot. |
| 1422 | */ |
| 1423 | if (uasm_insn_has_bdelay(relocs, split - 1)) |
| 1424 | split--; |
| 1425 | } |
| 1426 | /* Copy first part of the handler. */ |
| 1427 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
| 1428 | f += split - tlb_handler; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1429 | |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1430 | if (ov) { |
| 1431 | /* Insert branch. */ |
| 1432 | uasm_l_split(&l, final_handler); |
| 1433 | uasm_il_b(&f, &r, label_split); |
| 1434 | if (uasm_insn_has_bdelay(relocs, split)) |
| 1435 | uasm_i_nop(&f); |
| 1436 | else { |
| 1437 | uasm_copy_handler(relocs, labels, |
| 1438 | split, split + 1, f); |
| 1439 | uasm_move_labels(labels, f, f + 1, -1); |
| 1440 | f++; |
| 1441 | split++; |
| 1442 | } |
| 1443 | } |
| 1444 | |
| 1445 | /* Copy the rest of the handler. */ |
| 1446 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
| 1447 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
| 1448 | (p - split); |
David Daney | 95affdd | 2009-05-20 11:40:59 -0700 | [diff] [blame] | 1449 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1450 | } |
Ralf Baechle | 14bd8c0 | 2013-09-25 18:21:26 +0200 | [diff] [blame] | 1451 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1452 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1453 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1454 | uasm_resolve_relocs(relocs, labels); |
| 1455 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
| 1456 | final_len); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1457 | |
Ralf Baechle | 91b05e6 | 2006-03-29 18:53:00 +0100 | [diff] [blame] | 1458 | memcpy((void *)ebase, final_handler, 0x100); |
Leonid Yegoshin | 1062080 | 2014-07-11 15:18:05 -0700 | [diff] [blame] | 1459 | local_flush_icache_range(ebase, ebase + 0x100); |
Franck Bui-Huu | 92b1e6a | 2007-10-18 09:11:17 +0200 | [diff] [blame] | 1460 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 1461 | dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1462 | } |
| 1463 | |
Huacai Chen | 380cd58 | 2016-03-03 09:45:12 +0800 | [diff] [blame] | 1464 | static void setup_pw(void) |
| 1465 | { |
| 1466 | unsigned long pgd_i, pgd_w; |
| 1467 | #ifndef __PAGETABLE_PMD_FOLDED |
| 1468 | unsigned long pmd_i, pmd_w; |
| 1469 | #endif |
| 1470 | unsigned long pt_i, pt_w; |
| 1471 | unsigned long pte_i, pte_w; |
| 1472 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
| 1473 | unsigned long psn; |
| 1474 | |
| 1475 | psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ |
| 1476 | #endif |
| 1477 | pgd_i = PGDIR_SHIFT; /* 1st level PGD */ |
| 1478 | #ifndef __PAGETABLE_PMD_FOLDED |
| 1479 | pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; |
| 1480 | |
| 1481 | pmd_i = PMD_SHIFT; /* 2nd level PMD */ |
| 1482 | pmd_w = PMD_SHIFT - PAGE_SHIFT; |
| 1483 | #else |
| 1484 | pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; |
| 1485 | #endif |
| 1486 | |
| 1487 | pt_i = PAGE_SHIFT; /* 3rd level PTE */ |
| 1488 | pt_w = PAGE_SHIFT - 3; |
| 1489 | |
| 1490 | pte_i = ilog2(_PAGE_GLOBAL); |
| 1491 | pte_w = 0; |
| 1492 | |
| 1493 | #ifndef __PAGETABLE_PMD_FOLDED |
| 1494 | write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); |
| 1495 | write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); |
| 1496 | #else |
| 1497 | write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); |
| 1498 | write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); |
| 1499 | #endif |
| 1500 | |
| 1501 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
| 1502 | write_c0_pwctl(1 << 6 | psn); |
| 1503 | #endif |
| 1504 | write_c0_kpgd(swapper_pg_dir); |
| 1505 | kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ |
| 1506 | } |
| 1507 | |
| 1508 | static void build_loongson3_tlb_refill_handler(void) |
| 1509 | { |
| 1510 | u32 *p = tlb_handler; |
| 1511 | struct uasm_label *l = labels; |
| 1512 | struct uasm_reloc *r = relocs; |
| 1513 | |
| 1514 | memset(labels, 0, sizeof(labels)); |
| 1515 | memset(relocs, 0, sizeof(relocs)); |
| 1516 | memset(tlb_handler, 0, sizeof(tlb_handler)); |
| 1517 | |
| 1518 | if (check_for_high_segbits) { |
| 1519 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); |
| 1520 | uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); |
| 1521 | uasm_il_beqz(&p, &r, K1, label_vmalloc); |
| 1522 | uasm_i_nop(&p); |
| 1523 | |
| 1524 | uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); |
| 1525 | uasm_i_nop(&p); |
| 1526 | uasm_l_vmalloc(&l, p); |
| 1527 | } |
| 1528 | |
| 1529 | uasm_i_dmfc0(&p, K1, C0_PGD); |
| 1530 | |
| 1531 | uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ |
| 1532 | #ifndef __PAGETABLE_PMD_FOLDED |
| 1533 | uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ |
| 1534 | #endif |
| 1535 | uasm_i_ldpte(&p, K1, 0); /* even */ |
| 1536 | uasm_i_ldpte(&p, K1, 1); /* odd */ |
| 1537 | uasm_i_tlbwr(&p); |
| 1538 | |
| 1539 | /* restore page mask */ |
| 1540 | if (PM_DEFAULT_MASK >> 16) { |
| 1541 | uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); |
| 1542 | uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); |
| 1543 | uasm_i_mtc0(&p, K0, C0_PAGEMASK); |
| 1544 | } else if (PM_DEFAULT_MASK) { |
| 1545 | uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); |
| 1546 | uasm_i_mtc0(&p, K0, C0_PAGEMASK); |
| 1547 | } else { |
| 1548 | uasm_i_mtc0(&p, 0, C0_PAGEMASK); |
| 1549 | } |
| 1550 | |
| 1551 | uasm_i_eret(&p); |
| 1552 | |
| 1553 | if (check_for_high_segbits) { |
| 1554 | uasm_l_large_segbits_fault(&l, p); |
| 1555 | UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); |
| 1556 | uasm_i_jr(&p, K1); |
| 1557 | uasm_i_nop(&p); |
| 1558 | } |
| 1559 | |
| 1560 | uasm_resolve_relocs(relocs, labels); |
| 1561 | memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); |
| 1562 | local_flush_icache_range(ebase + 0x80, ebase + 0x100); |
| 1563 | dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32); |
| 1564 | } |
| 1565 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1566 | extern u32 handle_tlbl[], handle_tlbl_end[]; |
| 1567 | extern u32 handle_tlbs[], handle_tlbs_end[]; |
| 1568 | extern u32 handle_tlbm[], handle_tlbm_end[]; |
Steven J. Hill | 7bb3940 | 2014-04-10 14:06:17 -0500 | [diff] [blame] | 1569 | extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[]; |
| 1570 | extern u32 tlbmiss_handler_setup_pgd_end[]; |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1571 | |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1572 | static void build_setup_pgd(void) |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1573 | { |
| 1574 | const int a0 = 4; |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1575 | const int __maybe_unused a1 = 5; |
| 1576 | const int __maybe_unused a2 = 6; |
Steven J. Hill | 7bb3940 | 2014-04-10 14:06:17 -0500 | [diff] [blame] | 1577 | u32 *p = tlbmiss_handler_setup_pgd_start; |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1578 | const int tlbmiss_handler_setup_pgd_size = |
Steven J. Hill | 7bb3940 | 2014-04-10 14:06:17 -0500 | [diff] [blame] | 1579 | tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1580 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
| 1581 | long pgdc = (long)pgd_current; |
| 1582 | #endif |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1583 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1584 | memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * |
| 1585 | sizeof(tlbmiss_handler_setup_pgd[0])); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1586 | memset(labels, 0, sizeof(labels)); |
| 1587 | memset(relocs, 0, sizeof(relocs)); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1588 | pgd_reg = allocate_kscratch(); |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1589 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1590 | if (pgd_reg == -1) { |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1591 | struct uasm_label *l = labels; |
| 1592 | struct uasm_reloc *r = relocs; |
| 1593 | |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1594 | /* PGD << 11 in c0_Context */ |
| 1595 | /* |
| 1596 | * If it is a ckseg0 address, convert to a physical |
| 1597 | * address. Shifting right by 29 and adding 4 will |
| 1598 | * result in zero for these addresses. |
| 1599 | * |
| 1600 | */ |
| 1601 | UASM_i_SRA(&p, a1, a0, 29); |
| 1602 | UASM_i_ADDIU(&p, a1, a1, 4); |
| 1603 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); |
| 1604 | uasm_i_nop(&p); |
| 1605 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); |
| 1606 | uasm_l_tlbl_goaround1(&l, p); |
| 1607 | UASM_i_SLL(&p, a0, a0, 11); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1608 | UASM_i_MTC0(&p, a0, C0_CONTEXT); |
Dmitry Korotin | dd8f65a | 2019-06-24 19:05:27 +0000 | [diff] [blame] | 1609 | uasm_i_jr(&p, 31); |
| 1610 | uasm_i_ehb(&p); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1611 | } else { |
| 1612 | /* PGD in c0_KScratch */ |
Huacai Chen | 380cd58 | 2016-03-03 09:45:12 +0800 | [diff] [blame] | 1613 | if (cpu_has_ldpte) |
| 1614 | UASM_i_MTC0(&p, a0, C0_PWBASE); |
| 1615 | else |
| 1616 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); |
Dmitry Korotin | dd8f65a | 2019-06-24 19:05:27 +0000 | [diff] [blame] | 1617 | uasm_i_jr(&p, 31); |
| 1618 | uasm_i_ehb(&p); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1619 | } |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1620 | #else |
| 1621 | #ifdef CONFIG_SMP |
| 1622 | /* Save PGD to pgd_current[smp_processor_id()] */ |
| 1623 | UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); |
| 1624 | UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); |
| 1625 | UASM_i_LA_mostly(&p, a2, pgdc); |
| 1626 | UASM_i_ADDU(&p, a2, a2, a1); |
| 1627 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); |
| 1628 | #else |
| 1629 | UASM_i_LA_mostly(&p, a2, pgdc); |
| 1630 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); |
| 1631 | #endif /* SMP */ |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1632 | |
| 1633 | /* if pgd_reg is allocated, save PGD also to scratch register */ |
Dmitry Korotin | dd8f65a | 2019-06-24 19:05:27 +0000 | [diff] [blame] | 1634 | if (pgd_reg != -1) { |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1635 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); |
Dmitry Korotin | dd8f65a | 2019-06-24 19:05:27 +0000 | [diff] [blame] | 1636 | uasm_i_jr(&p, 31); |
| 1637 | uasm_i_ehb(&p); |
| 1638 | } else { |
| 1639 | uasm_i_jr(&p, 31); |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1640 | uasm_i_nop(&p); |
Dmitry Korotin | dd8f65a | 2019-06-24 19:05:27 +0000 | [diff] [blame] | 1641 | } |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 1642 | #endif |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1643 | if (p >= tlbmiss_handler_setup_pgd_end) |
| 1644 | panic("tlbmiss_handler_setup_pgd space exceeded"); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1645 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1646 | uasm_resolve_relocs(relocs, labels); |
| 1647 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", |
| 1648 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); |
| 1649 | |
| 1650 | dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, |
| 1651 | tlbmiss_handler_setup_pgd_size); |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1652 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1653 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1654 | static void |
David Daney | bd1437e | 2009-05-08 15:10:50 -0700 | [diff] [blame] | 1655 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1656 | { |
| 1657 | #ifdef CONFIG_SMP |
Ralf Baechle | 34adb28 | 2014-11-22 00:16:48 +0100 | [diff] [blame] | 1658 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1659 | if (cpu_has_64bits) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1660 | uasm_i_lld(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1661 | else |
| 1662 | # endif |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1663 | UASM_i_LL(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1664 | #else |
Ralf Baechle | 34adb28 | 2014-11-22 00:16:48 +0100 | [diff] [blame] | 1665 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1666 | if (cpu_has_64bits) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1667 | uasm_i_ld(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1668 | else |
| 1669 | # endif |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1670 | UASM_i_LW(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1671 | #endif |
| 1672 | } |
| 1673 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1674 | static void |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1675 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1676 | unsigned int mode, unsigned int scratch) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1677 | { |
Thiemo Seufer | 63b2d2f | 2005-04-28 08:52:57 +0000 | [diff] [blame] | 1678 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); |
Paul Burton | b4ebbb8 | 2016-04-19 09:25:08 +0100 | [diff] [blame] | 1679 | unsigned int swmode = mode & ~hwmode; |
Thiemo Seufer | 63b2d2f | 2005-04-28 08:52:57 +0000 | [diff] [blame] | 1680 | |
Masahiro Yamada | 97f2645 | 2016-08-03 13:45:50 -0700 | [diff] [blame] | 1681 | if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { |
Paul Burton | b4ebbb8 | 2016-04-19 09:25:08 +0100 | [diff] [blame] | 1682 | uasm_i_lui(p, scratch, swmode >> 16); |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 1683 | uasm_i_or(p, pte, pte, scratch); |
Paul Burton | b4ebbb8 | 2016-04-19 09:25:08 +0100 | [diff] [blame] | 1684 | BUG_ON(swmode & 0xffff); |
| 1685 | } else { |
| 1686 | uasm_i_ori(p, pte, pte, mode); |
| 1687 | } |
| 1688 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1689 | #ifdef CONFIG_SMP |
Ralf Baechle | 34adb28 | 2014-11-22 00:16:48 +0100 | [diff] [blame] | 1690 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1691 | if (cpu_has_64bits) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1692 | uasm_i_scd(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1693 | else |
| 1694 | # endif |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1695 | UASM_i_SC(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1696 | |
| 1697 | if (r10000_llsc_war()) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1698 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | else |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1700 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1701 | |
Ralf Baechle | 34adb28 | 2014-11-22 00:16:48 +0100 | [diff] [blame] | 1702 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1703 | if (!cpu_has_64bits) { |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1704 | /* no uasm_i_nop needed */ |
| 1705 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); |
| 1706 | uasm_i_ori(p, pte, pte, hwmode); |
Paul Burton | b4ebbb8 | 2016-04-19 09:25:08 +0100 | [diff] [blame] | 1707 | BUG_ON(hwmode & ~0xffff); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1708 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); |
| 1709 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
| 1710 | /* no uasm_i_nop needed */ |
| 1711 | uasm_i_lw(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1712 | } else |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1713 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1714 | # else |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1715 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1716 | # endif |
| 1717 | #else |
Ralf Baechle | 34adb28 | 2014-11-22 00:16:48 +0100 | [diff] [blame] | 1718 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1719 | if (cpu_has_64bits) |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1720 | uasm_i_sd(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1721 | else |
| 1722 | # endif |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1723 | UASM_i_SW(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1724 | |
Ralf Baechle | 34adb28 | 2014-11-22 00:16:48 +0100 | [diff] [blame] | 1725 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1726 | if (!cpu_has_64bits) { |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1727 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
| 1728 | uasm_i_ori(p, pte, pte, hwmode); |
Paul Burton | b4ebbb8 | 2016-04-19 09:25:08 +0100 | [diff] [blame] | 1729 | BUG_ON(hwmode & ~0xffff); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1730 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); |
| 1731 | uasm_i_lw(p, pte, 0, ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1732 | } |
| 1733 | # endif |
| 1734 | #endif |
| 1735 | } |
| 1736 | |
| 1737 | /* |
| 1738 | * Check if PTE is present, if not then jump to LABEL. PTR points to |
| 1739 | * the page table where this PTE is located, PTE will be re-loaded |
| 1740 | * with it's original value. |
| 1741 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1742 | static void |
David Daney | bd1437e | 2009-05-08 15:10:50 -0700 | [diff] [blame] | 1743 | build_pte_present(u32 **p, struct uasm_reloc **r, |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1744 | int pte, int ptr, int scratch, enum label_id lid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1745 | { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1746 | int t = scratch >= 0 ? scratch : pte; |
James Hogan | 8fe4908 | 2015-04-27 15:07:18 +0100 | [diff] [blame] | 1747 | int cur = pte; |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1748 | |
Steven J. Hill | 05857c6 | 2012-09-13 16:51:46 -0500 | [diff] [blame] | 1749 | if (cpu_has_rixi) { |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 1750 | if (use_bbit_insns()) { |
| 1751 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); |
| 1752 | uasm_i_nop(p); |
| 1753 | } else { |
James Hogan | 8fe4908 | 2015-04-27 15:07:18 +0100 | [diff] [blame] | 1754 | if (_PAGE_PRESENT_SHIFT) { |
| 1755 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); |
| 1756 | cur = t; |
| 1757 | } |
| 1758 | uasm_i_andi(p, t, cur, 1); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1759 | uasm_il_beqz(p, r, t, lid); |
| 1760 | if (pte == t) |
| 1761 | /* You lose the SMP race :-(*/ |
| 1762 | iPTE_LW(p, pte, ptr); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 1763 | } |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 1764 | } else { |
James Hogan | 8fe4908 | 2015-04-27 15:07:18 +0100 | [diff] [blame] | 1765 | if (_PAGE_PRESENT_SHIFT) { |
| 1766 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); |
| 1767 | cur = t; |
| 1768 | } |
| 1769 | uasm_i_andi(p, t, cur, |
Paul Burton | 780602d | 2016-04-19 09:25:03 +0100 | [diff] [blame] | 1770 | (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); |
| 1771 | uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1772 | uasm_il_bnez(p, r, t, lid); |
| 1773 | if (pte == t) |
| 1774 | /* You lose the SMP race :-(*/ |
| 1775 | iPTE_LW(p, pte, ptr); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 1776 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1777 | } |
| 1778 | |
| 1779 | /* Make PTE valid, store result in PTR. */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1780 | static void |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1781 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1782 | unsigned int ptr, unsigned int scratch) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1783 | { |
Thiemo Seufer | 63b2d2f | 2005-04-28 08:52:57 +0000 | [diff] [blame] | 1784 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
| 1785 | |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1786 | iPTE_SW(p, r, pte, ptr, mode, scratch); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1787 | } |
| 1788 | |
| 1789 | /* |
| 1790 | * Check if PTE can be written to, if not branch to LABEL. Regardless |
| 1791 | * restore PTE with value from PTR when done. |
| 1792 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1793 | static void |
David Daney | bd1437e | 2009-05-08 15:10:50 -0700 | [diff] [blame] | 1794 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1795 | unsigned int pte, unsigned int ptr, int scratch, |
| 1796 | enum label_id lid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1797 | { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1798 | int t = scratch >= 0 ? scratch : pte; |
James Hogan | 8fe4908 | 2015-04-27 15:07:18 +0100 | [diff] [blame] | 1799 | int cur = pte; |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1800 | |
James Hogan | 8fe4908 | 2015-04-27 15:07:18 +0100 | [diff] [blame] | 1801 | if (_PAGE_PRESENT_SHIFT) { |
| 1802 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); |
| 1803 | cur = t; |
| 1804 | } |
| 1805 | uasm_i_andi(p, t, cur, |
James Hogan | a3ae565 | 2015-04-27 15:07:17 +0100 | [diff] [blame] | 1806 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); |
| 1807 | uasm_i_xori(p, t, t, |
| 1808 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1809 | uasm_il_bnez(p, r, t, lid); |
| 1810 | if (pte == t) |
| 1811 | /* You lose the SMP race :-(*/ |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 1812 | iPTE_LW(p, pte, ptr); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1813 | else |
| 1814 | uasm_i_nop(p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1815 | } |
| 1816 | |
| 1817 | /* Make PTE writable, update software status bits as well, then store |
| 1818 | * at PTR. |
| 1819 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1820 | static void |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1821 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1822 | unsigned int ptr, unsigned int scratch) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1823 | { |
Thiemo Seufer | 63b2d2f | 2005-04-28 08:52:57 +0000 | [diff] [blame] | 1824 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
| 1825 | | _PAGE_DIRTY); |
| 1826 | |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1827 | iPTE_SW(p, r, pte, ptr, mode, scratch); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1828 | } |
| 1829 | |
| 1830 | /* |
| 1831 | * Check if PTE can be modified, if not branch to LABEL. Regardless |
| 1832 | * restore PTE with value from PTR when done. |
| 1833 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1834 | static void |
David Daney | bd1437e | 2009-05-08 15:10:50 -0700 | [diff] [blame] | 1835 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1836 | unsigned int pte, unsigned int ptr, int scratch, |
| 1837 | enum label_id lid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1838 | { |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 1839 | if (use_bbit_insns()) { |
| 1840 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); |
| 1841 | uasm_i_nop(p); |
| 1842 | } else { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1843 | int t = scratch >= 0 ? scratch : pte; |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 1844 | uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); |
| 1845 | uasm_i_andi(p, t, t, 1); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1846 | uasm_il_beqz(p, r, t, lid); |
| 1847 | if (pte == t) |
| 1848 | /* You lose the SMP race :-(*/ |
| 1849 | iPTE_LW(p, pte, ptr); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 1850 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1851 | } |
| 1852 | |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 1853 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
David Daney | 3d8bfdd | 2010-12-21 14:19:11 -0800 | [diff] [blame] | 1854 | |
| 1855 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1856 | /* |
| 1857 | * R3000 style TLB load/store/modify handlers. |
| 1858 | */ |
| 1859 | |
Maciej W. Rozycki | fded2e5 | 2005-06-13 20:24:00 +0000 | [diff] [blame] | 1860 | /* |
| 1861 | * This places the pte into ENTRYLO0 and writes it with tlbwi. |
| 1862 | * Then it returns. |
| 1863 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1864 | static void |
Maciej W. Rozycki | fded2e5 | 2005-06-13 20:24:00 +0000 | [diff] [blame] | 1865 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1866 | { |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1867 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
| 1868 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ |
| 1869 | uasm_i_tlbwi(p); |
| 1870 | uasm_i_jr(p, tmp); |
| 1871 | uasm_i_rfe(p); /* branch delay */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1872 | } |
| 1873 | |
| 1874 | /* |
Maciej W. Rozycki | fded2e5 | 2005-06-13 20:24:00 +0000 | [diff] [blame] | 1875 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
| 1876 | * or tlbwr as appropriate. This is because the index register |
| 1877 | * may have the probe fail bit set as a result of a trap on a |
| 1878 | * kseg2 access, i.e. without refill. Then it returns. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1879 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1880 | static void |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1881 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
| 1882 | struct uasm_reloc **r, unsigned int pte, |
| 1883 | unsigned int tmp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1884 | { |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1885 | uasm_i_mfc0(p, tmp, C0_INDEX); |
| 1886 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
| 1887 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ |
| 1888 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ |
| 1889 | uasm_i_tlbwi(p); /* cp0 delay */ |
| 1890 | uasm_i_jr(p, tmp); |
| 1891 | uasm_i_rfe(p); /* branch delay */ |
| 1892 | uasm_l_r3000_write_probe_fail(l, *p); |
| 1893 | uasm_i_tlbwr(p); /* cp0 delay */ |
| 1894 | uasm_i_jr(p, tmp); |
| 1895 | uasm_i_rfe(p); /* branch delay */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1896 | } |
| 1897 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1898 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1899 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
| 1900 | unsigned int ptr) |
| 1901 | { |
| 1902 | long pgdc = (long)pgd_current; |
| 1903 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1904 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
| 1905 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ |
| 1906 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); |
| 1907 | uasm_i_srl(p, pte, pte, 22); /* load delay */ |
| 1908 | uasm_i_sll(p, pte, pte, 2); |
| 1909 | uasm_i_addu(p, ptr, ptr, pte); |
| 1910 | uasm_i_mfc0(p, pte, C0_CONTEXT); |
| 1911 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ |
| 1912 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ |
| 1913 | uasm_i_addu(p, ptr, ptr, pte); |
| 1914 | uasm_i_lw(p, pte, 0, ptr); |
| 1915 | uasm_i_tlbp(p); /* load delay */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1916 | } |
| 1917 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1918 | static void build_r3000_tlb_load_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1919 | { |
| 1920 | u32 *p = handle_tlbl; |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1921 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1922 | struct uasm_label *l = labels; |
| 1923 | struct uasm_reloc *r = relocs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1924 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1925 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1926 | memset(labels, 0, sizeof(labels)); |
| 1927 | memset(relocs, 0, sizeof(relocs)); |
| 1928 | |
| 1929 | build_r3000_tlbchange_handler_head(&p, K0, K1); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1930 | build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1931 | uasm_i_nop(&p); /* load delay */ |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1932 | build_make_valid(&p, &r, K0, K1, -1); |
Maciej W. Rozycki | fded2e5 | 2005-06-13 20:24:00 +0000 | [diff] [blame] | 1933 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1934 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1935 | uasm_l_nopage_tlbl(&l, p); |
| 1936 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
| 1937 | uasm_i_nop(&p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1938 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1939 | if (p >= handle_tlbl_end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1940 | panic("TLB load handler fastpath space exceeded"); |
| 1941 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1942 | uasm_resolve_relocs(relocs, labels); |
| 1943 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", |
| 1944 | (unsigned int)(p - handle_tlbl)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1945 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1946 | dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1947 | } |
| 1948 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1949 | static void build_r3000_tlb_store_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1950 | { |
| 1951 | u32 *p = handle_tlbs; |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1952 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1953 | struct uasm_label *l = labels; |
| 1954 | struct uasm_reloc *r = relocs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1955 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1956 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1957 | memset(labels, 0, sizeof(labels)); |
| 1958 | memset(relocs, 0, sizeof(relocs)); |
| 1959 | |
| 1960 | build_r3000_tlbchange_handler_head(&p, K0, K1); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 1961 | build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1962 | uasm_i_nop(&p); /* load delay */ |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1963 | build_make_write(&p, &r, K0, K1, -1); |
Maciej W. Rozycki | fded2e5 | 2005-06-13 20:24:00 +0000 | [diff] [blame] | 1964 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1965 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1966 | uasm_l_nopage_tlbs(&l, p); |
| 1967 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
| 1968 | uasm_i_nop(&p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1969 | |
Tony Wu | afc813a | 2013-07-18 09:45:47 +0000 | [diff] [blame] | 1970 | if (p >= handle_tlbs_end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1971 | panic("TLB store handler fastpath space exceeded"); |
| 1972 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1973 | uasm_resolve_relocs(relocs, labels); |
| 1974 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", |
| 1975 | (unsigned int)(p - handle_tlbs)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1976 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1977 | dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1978 | } |
| 1979 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1980 | static void build_r3000_tlb_modify_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1981 | { |
| 1982 | u32 *p = handle_tlbm; |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1983 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1984 | struct uasm_label *l = labels; |
| 1985 | struct uasm_reloc *r = relocs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1986 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 1987 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1988 | memset(labels, 0, sizeof(labels)); |
| 1989 | memset(relocs, 0, sizeof(relocs)); |
| 1990 | |
| 1991 | build_r3000_tlbchange_handler_head(&p, K0, K1); |
Ralf Baechle | d954ffe | 2011-08-02 22:52:48 +0100 | [diff] [blame] | 1992 | build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1993 | uasm_i_nop(&p); /* load delay */ |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 1994 | build_make_write(&p, &r, K0, K1, -1); |
Maciej W. Rozycki | fded2e5 | 2005-06-13 20:24:00 +0000 | [diff] [blame] | 1995 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1996 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 1997 | uasm_l_nopage_tlbm(&l, p); |
| 1998 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
| 1999 | uasm_i_nop(&p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2000 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2001 | if (p >= handle_tlbm_end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2002 | panic("TLB modify handler fastpath space exceeded"); |
| 2003 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2004 | uasm_resolve_relocs(relocs, labels); |
| 2005 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", |
| 2006 | (unsigned int)(p - handle_tlbm)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2007 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2008 | dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2009 | } |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 2010 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2011 | |
| 2012 | /* |
| 2013 | * R4000 style TLB load/store/modify handlers. |
| 2014 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2015 | static struct work_registers |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2016 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2017 | struct uasm_reloc **r) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2018 | { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2019 | struct work_registers wr = build_get_work_registers(p); |
| 2020 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 2021 | #ifdef CONFIG_64BIT |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2022 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2023 | #else |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2024 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2025 | #endif |
| 2026 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 2027 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2028 | /* |
| 2029 | * For huge tlb entries, pmd doesn't contain an address but |
| 2030 | * instead contains the tlb pte. Check the PAGE_HUGE bit and |
| 2031 | * see if we need to jump to huge tlb processing. |
| 2032 | */ |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2033 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2034 | #endif |
| 2035 | |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2036 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
| 2037 | UASM_i_LW(p, wr.r2, 0, wr.r2); |
| 2038 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); |
| 2039 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); |
| 2040 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2041 | |
| 2042 | #ifdef CONFIG_SMP |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2043 | uasm_l_smp_pgtable_change(l, *p); |
| 2044 | #endif |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2045 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
Leonid Yegoshin | 070e76c | 2014-11-27 11:13:08 +0000 | [diff] [blame] | 2046 | if (!m4kc_tlbp_war()) { |
Maciej W. Rozycki | 8df5bea | 2006-08-23 14:26:50 +0100 | [diff] [blame] | 2047 | build_tlb_probe_entry(p); |
Leonid Yegoshin | 070e76c | 2014-11-27 11:13:08 +0000 | [diff] [blame] | 2048 | if (cpu_has_htw) { |
| 2049 | /* race condition happens, leaving */ |
| 2050 | uasm_i_ehb(p); |
| 2051 | uasm_i_mfc0(p, wr.r3, C0_INDEX); |
| 2052 | uasm_il_bltz(p, r, wr.r3, label_leave); |
| 2053 | uasm_i_nop(p); |
| 2054 | } |
| 2055 | } |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2056 | return wr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2057 | } |
| 2058 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2059 | static void |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2060 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
| 2061 | struct uasm_reloc **r, unsigned int tmp, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2062 | unsigned int ptr) |
| 2063 | { |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2064 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
| 2065 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2066 | build_update_entries(p, tmp, ptr); |
| 2067 | build_tlb_write_entry(p, l, r, tlb_indexed); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2068 | uasm_l_leave(l, *p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2069 | build_restore_work_registers(p); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2070 | uasm_i_eret(p); /* return from trap */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2071 | |
Ralf Baechle | 875d43e | 2005-09-03 15:56:16 -0700 | [diff] [blame] | 2072 | #ifdef CONFIG_64BIT |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 2073 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2074 | #endif |
| 2075 | } |
| 2076 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2077 | static void build_r4000_tlb_load_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2078 | { |
| 2079 | u32 *p = handle_tlbl; |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2080 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2081 | struct uasm_label *l = labels; |
| 2082 | struct uasm_reloc *r = relocs; |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2083 | struct work_registers wr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2084 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2085 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2086 | memset(labels, 0, sizeof(labels)); |
| 2087 | memset(relocs, 0, sizeof(relocs)); |
| 2088 | |
| 2089 | if (bcm1250_m3_war()) { |
Ralf Baechle | 3d45285 | 2010-03-23 17:56:38 +0100 | [diff] [blame] | 2090 | unsigned int segbits = 44; |
| 2091 | |
| 2092 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); |
| 2093 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2094 | uasm_i_xor(&p, K0, K0, K1); |
David Daney | 3be6022 | 2010-04-28 12:16:17 -0700 | [diff] [blame] | 2095 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
| 2096 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); |
| 2097 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); |
Ralf Baechle | 3d45285 | 2010-03-23 17:56:38 +0100 | [diff] [blame] | 2098 | uasm_i_or(&p, K0, K0, K1); |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2099 | uasm_il_bnez(&p, &r, K0, label_leave); |
| 2100 | /* No need for uasm_i_nop */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2101 | } |
| 2102 | |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2103 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
| 2104 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); |
Maciej W. Rozycki | 8df5bea | 2006-08-23 14:26:50 +0100 | [diff] [blame] | 2105 | if (m4kc_tlbp_war()) |
| 2106 | build_tlb_probe_entry(&p); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2107 | |
Leonid Yegoshin | 5890f70 | 2014-07-15 14:09:56 +0100 | [diff] [blame] | 2108 | if (cpu_has_rixi && !cpu_has_rixiex) { |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2109 | /* |
| 2110 | * If the page is not _PAGE_VALID, RI or XI could not |
| 2111 | * have triggered it. Skip the expensive test.. |
| 2112 | */ |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2113 | if (use_bbit_insns()) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2114 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2115 | label_tlbl_goaround1); |
| 2116 | } else { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2117 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
| 2118 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2119 | } |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2120 | uasm_i_nop(&p); |
| 2121 | |
| 2122 | uasm_i_tlbr(&p); |
Ralf Baechle | 73acc7d | 2013-06-20 14:56:17 +0200 | [diff] [blame] | 2123 | |
| 2124 | switch (current_cpu_type()) { |
| 2125 | default: |
Leonid Yegoshin | 77f3ee5 | 2014-11-24 15:42:46 +0000 | [diff] [blame] | 2126 | if (cpu_has_mips_r2_exec_hazard) { |
Ralf Baechle | 73acc7d | 2013-06-20 14:56:17 +0200 | [diff] [blame] | 2127 | uasm_i_ehb(&p); |
| 2128 | |
| 2129 | case CPU_CAVIUM_OCTEON: |
| 2130 | case CPU_CAVIUM_OCTEON_PLUS: |
| 2131 | case CPU_CAVIUM_OCTEON2: |
| 2132 | break; |
| 2133 | } |
| 2134 | } |
| 2135 | |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2136 | /* Examine entrylo 0 or 1 based on ptr. */ |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2137 | if (use_bbit_insns()) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2138 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2139 | } else { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2140 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
| 2141 | uasm_i_beqz(&p, wr.r3, 8); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2142 | } |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2143 | /* load it in the delay slot*/ |
| 2144 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); |
| 2145 | /* load it if ptr is odd */ |
| 2146 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2147 | /* |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2148 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2149 | * XI must have triggered it. |
| 2150 | */ |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2151 | if (use_bbit_insns()) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2152 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
| 2153 | uasm_i_nop(&p); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2154 | uasm_l_tlbl_goaround1(&l, p); |
| 2155 | } else { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2156 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
| 2157 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); |
| 2158 | uasm_i_nop(&p); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2159 | } |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2160 | uasm_l_tlbl_goaround1(&l, p); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2161 | } |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 2162 | build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2163 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2164 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 2165 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2166 | /* |
| 2167 | * This is the entry point when build_r4000_tlbchange_handler_head |
| 2168 | * spots a huge page. |
| 2169 | */ |
| 2170 | uasm_l_tlb_huge_update(&l, p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2171 | iPTE_LW(&p, wr.r1, wr.r2); |
| 2172 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2173 | build_tlb_probe_entry(&p); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2174 | |
Leonid Yegoshin | 5890f70 | 2014-07-15 14:09:56 +0100 | [diff] [blame] | 2175 | if (cpu_has_rixi && !cpu_has_rixiex) { |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2176 | /* |
| 2177 | * If the page is not _PAGE_VALID, RI or XI could not |
| 2178 | * have triggered it. Skip the expensive test.. |
| 2179 | */ |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2180 | if (use_bbit_insns()) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2181 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2182 | label_tlbl_goaround2); |
| 2183 | } else { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2184 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
| 2185 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2186 | } |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2187 | uasm_i_nop(&p); |
| 2188 | |
| 2189 | uasm_i_tlbr(&p); |
Ralf Baechle | 73acc7d | 2013-06-20 14:56:17 +0200 | [diff] [blame] | 2190 | |
| 2191 | switch (current_cpu_type()) { |
| 2192 | default: |
Leonid Yegoshin | 77f3ee5 | 2014-11-24 15:42:46 +0000 | [diff] [blame] | 2193 | if (cpu_has_mips_r2_exec_hazard) { |
Ralf Baechle | 73acc7d | 2013-06-20 14:56:17 +0200 | [diff] [blame] | 2194 | uasm_i_ehb(&p); |
| 2195 | |
| 2196 | case CPU_CAVIUM_OCTEON: |
| 2197 | case CPU_CAVIUM_OCTEON_PLUS: |
| 2198 | case CPU_CAVIUM_OCTEON2: |
| 2199 | break; |
| 2200 | } |
| 2201 | } |
| 2202 | |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2203 | /* Examine entrylo 0 or 1 based on ptr. */ |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2204 | if (use_bbit_insns()) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2205 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2206 | } else { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2207 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
| 2208 | uasm_i_beqz(&p, wr.r3, 8); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2209 | } |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2210 | /* load it in the delay slot*/ |
| 2211 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); |
| 2212 | /* load it if ptr is odd */ |
| 2213 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2214 | /* |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2215 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2216 | * XI must have triggered it. |
| 2217 | */ |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2218 | if (use_bbit_insns()) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2219 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2220 | } else { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2221 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
| 2222 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); |
David Daney | cc33ae4 | 2010-12-20 15:54:50 -0800 | [diff] [blame] | 2223 | } |
David Daney | 0f4ccbc | 2011-09-16 18:06:02 -0700 | [diff] [blame] | 2224 | if (PM_DEFAULT_MASK == 0) |
| 2225 | uasm_i_nop(&p); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2226 | /* |
| 2227 | * We clobbered C0_PAGEMASK, restore it. On the other branch |
| 2228 | * it is restored in build_huge_tlb_write_entry. |
| 2229 | */ |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2230 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 2231 | |
| 2232 | uasm_l_tlbl_goaround2(&l, p); |
| 2233 | } |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2234 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
Huacai Chen | 59b8725 | 2017-03-16 21:00:27 +0800 | [diff] [blame] | 2235 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2236 | #endif |
| 2237 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2238 | uasm_l_nopage_tlbl(&l, p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2239 | build_restore_work_registers(&p); |
Steven J. Hill | 2a0b24f | 2013-03-25 12:15:55 -0500 | [diff] [blame] | 2240 | #ifdef CONFIG_CPU_MICROMIPS |
| 2241 | if ((unsigned long)tlb_do_page_fault_0 & 1) { |
| 2242 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); |
| 2243 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); |
| 2244 | uasm_i_jr(&p, K0); |
| 2245 | } else |
| 2246 | #endif |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2247 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
| 2248 | uasm_i_nop(&p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2249 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2250 | if (p >= handle_tlbl_end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2251 | panic("TLB load handler fastpath space exceeded"); |
| 2252 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2253 | uasm_resolve_relocs(relocs, labels); |
| 2254 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", |
| 2255 | (unsigned int)(p - handle_tlbl)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2256 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2257 | dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2258 | } |
| 2259 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2260 | static void build_r4000_tlb_store_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2261 | { |
| 2262 | u32 *p = handle_tlbs; |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2263 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2264 | struct uasm_label *l = labels; |
| 2265 | struct uasm_reloc *r = relocs; |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2266 | struct work_registers wr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2267 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2268 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2269 | memset(labels, 0, sizeof(labels)); |
| 2270 | memset(relocs, 0, sizeof(relocs)); |
| 2271 | |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2272 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
| 2273 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); |
Maciej W. Rozycki | 8df5bea | 2006-08-23 14:26:50 +0100 | [diff] [blame] | 2274 | if (m4kc_tlbp_war()) |
| 2275 | build_tlb_probe_entry(&p); |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 2276 | build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2277 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2278 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 2279 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2280 | /* |
| 2281 | * This is the entry point when |
| 2282 | * build_r4000_tlbchange_handler_head spots a huge page. |
| 2283 | */ |
| 2284 | uasm_l_tlb_huge_update(&l, p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2285 | iPTE_LW(&p, wr.r1, wr.r2); |
| 2286 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2287 | build_tlb_probe_entry(&p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2288 | uasm_i_ori(&p, wr.r1, wr.r1, |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2289 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
Huacai Chen | 59b8725 | 2017-03-16 21:00:27 +0800 | [diff] [blame] | 2290 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2291 | #endif |
| 2292 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2293 | uasm_l_nopage_tlbs(&l, p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2294 | build_restore_work_registers(&p); |
Steven J. Hill | 2a0b24f | 2013-03-25 12:15:55 -0500 | [diff] [blame] | 2295 | #ifdef CONFIG_CPU_MICROMIPS |
| 2296 | if ((unsigned long)tlb_do_page_fault_1 & 1) { |
| 2297 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); |
| 2298 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); |
| 2299 | uasm_i_jr(&p, K0); |
| 2300 | } else |
| 2301 | #endif |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2302 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
| 2303 | uasm_i_nop(&p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2304 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2305 | if (p >= handle_tlbs_end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2306 | panic("TLB store handler fastpath space exceeded"); |
| 2307 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2308 | uasm_resolve_relocs(relocs, labels); |
| 2309 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", |
| 2310 | (unsigned int)(p - handle_tlbs)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2311 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2312 | dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2313 | } |
| 2314 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2315 | static void build_r4000_tlb_modify_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2316 | { |
| 2317 | u32 *p = handle_tlbm; |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2318 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2319 | struct uasm_label *l = labels; |
| 2320 | struct uasm_reloc *r = relocs; |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2321 | struct work_registers wr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2322 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2323 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2324 | memset(labels, 0, sizeof(labels)); |
| 2325 | memset(relocs, 0, sizeof(relocs)); |
| 2326 | |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2327 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
| 2328 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); |
Maciej W. Rozycki | 8df5bea | 2006-08-23 14:26:50 +0100 | [diff] [blame] | 2329 | if (m4kc_tlbp_war()) |
| 2330 | build_tlb_probe_entry(&p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2331 | /* Present and writable bits set, set accessed and dirty bits. */ |
Paul Burton | bbeeffe | 2016-04-19 09:25:07 +0100 | [diff] [blame] | 2332 | build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2333 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2334 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 2335 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2336 | /* |
| 2337 | * This is the entry point when |
| 2338 | * build_r4000_tlbchange_handler_head spots a huge page. |
| 2339 | */ |
| 2340 | uasm_l_tlb_huge_update(&l, p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2341 | iPTE_LW(&p, wr.r1, wr.r2); |
| 2342 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2343 | build_tlb_probe_entry(&p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2344 | uasm_i_ori(&p, wr.r1, wr.r1, |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2345 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
Huacai Chen | 59b8725 | 2017-03-16 21:00:27 +0800 | [diff] [blame] | 2346 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); |
David Daney | fd062c8 | 2009-05-27 17:47:44 -0700 | [diff] [blame] | 2347 | #endif |
| 2348 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2349 | uasm_l_nopage_tlbm(&l, p); |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2350 | build_restore_work_registers(&p); |
Steven J. Hill | 2a0b24f | 2013-03-25 12:15:55 -0500 | [diff] [blame] | 2351 | #ifdef CONFIG_CPU_MICROMIPS |
| 2352 | if ((unsigned long)tlb_do_page_fault_1 & 1) { |
| 2353 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); |
| 2354 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); |
| 2355 | uasm_i_jr(&p, K0); |
| 2356 | } else |
| 2357 | #endif |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2358 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
| 2359 | uasm_i_nop(&p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2360 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2361 | if (p >= handle_tlbm_end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2362 | panic("TLB modify handler fastpath space exceeded"); |
| 2363 | |
Thiemo Seufer | e30ec45 | 2008-01-28 20:05:38 +0000 | [diff] [blame] | 2364 | uasm_resolve_relocs(relocs, labels); |
| 2365 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", |
| 2366 | (unsigned int)(p - handle_tlbm)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2367 | |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 2368 | dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2369 | } |
| 2370 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2371 | static void flush_tlb_handlers(void) |
Jonas Gorski | a3d9086 | 2013-06-21 17:48:48 +0000 | [diff] [blame] | 2372 | { |
| 2373 | local_flush_icache_range((unsigned long)handle_tlbl, |
Ralf Baechle | 6ac5310 | 2013-07-02 17:19:04 +0200 | [diff] [blame] | 2374 | (unsigned long)handle_tlbl_end); |
Jonas Gorski | a3d9086 | 2013-06-21 17:48:48 +0000 | [diff] [blame] | 2375 | local_flush_icache_range((unsigned long)handle_tlbs, |
Ralf Baechle | 6ac5310 | 2013-07-02 17:19:04 +0200 | [diff] [blame] | 2376 | (unsigned long)handle_tlbs_end); |
Jonas Gorski | a3d9086 | 2013-06-21 17:48:48 +0000 | [diff] [blame] | 2377 | local_flush_icache_range((unsigned long)handle_tlbm, |
Ralf Baechle | 6ac5310 | 2013-07-02 17:19:04 +0200 | [diff] [blame] | 2378 | (unsigned long)handle_tlbm_end); |
Ralf Baechle | 6ac5310 | 2013-07-02 17:19:04 +0200 | [diff] [blame] | 2379 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, |
| 2380 | (unsigned long)tlbmiss_handler_setup_pgd_end); |
Jonas Gorski | a3d9086 | 2013-06-21 17:48:48 +0000 | [diff] [blame] | 2381 | } |
| 2382 | |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2383 | static void print_htw_config(void) |
| 2384 | { |
| 2385 | unsigned long config; |
| 2386 | unsigned int pwctl; |
| 2387 | const int field = 2 * sizeof(unsigned long); |
| 2388 | |
| 2389 | config = read_c0_pwfield(); |
| 2390 | pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", |
| 2391 | field, config, |
| 2392 | (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, |
| 2393 | (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, |
| 2394 | (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, |
| 2395 | (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, |
| 2396 | (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); |
| 2397 | |
| 2398 | config = read_c0_pwsize(); |
James Hogan | 6446e6c | 2016-05-27 22:25:22 +0100 | [diff] [blame] | 2399 | pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2400 | field, config, |
James Hogan | 6446e6c | 2016-05-27 22:25:22 +0100 | [diff] [blame] | 2401 | (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2402 | (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, |
| 2403 | (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, |
| 2404 | (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, |
| 2405 | (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, |
| 2406 | (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); |
| 2407 | |
| 2408 | pwctl = read_c0_pwctl(); |
James Hogan | 6446e6c | 2016-05-27 22:25:22 +0100 | [diff] [blame] | 2409 | pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2410 | pwctl, |
| 2411 | (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, |
James Hogan | 6446e6c | 2016-05-27 22:25:22 +0100 | [diff] [blame] | 2412 | (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, |
| 2413 | (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, |
| 2414 | (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2415 | (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, |
| 2416 | (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, |
| 2417 | (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); |
| 2418 | } |
| 2419 | |
| 2420 | static void config_htw_params(void) |
| 2421 | { |
| 2422 | unsigned long pwfield, pwsize, ptei; |
| 2423 | unsigned int config; |
| 2424 | |
| 2425 | /* |
| 2426 | * We are using 2-level page tables, so we only need to |
| 2427 | * setup GDW and PTW appropriately. UDW and MDW will remain 0. |
| 2428 | * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to |
| 2429 | * write values less than 0xc in these fields because the entire |
| 2430 | * write will be dropped. As a result of which, we must preserve |
| 2431 | * the original reset values and overwrite only what we really want. |
| 2432 | */ |
| 2433 | |
| 2434 | pwfield = read_c0_pwfield(); |
| 2435 | /* re-initialize the GDI field */ |
| 2436 | pwfield &= ~MIPS_PWFIELD_GDI_MASK; |
| 2437 | pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; |
| 2438 | /* re-initialize the PTI field including the even/odd bit */ |
| 2439 | pwfield &= ~MIPS_PWFIELD_PTI_MASK; |
| 2440 | pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; |
Paul Burton | cab25bc | 2015-09-22 12:03:37 -0700 | [diff] [blame] | 2441 | if (CONFIG_PGTABLE_LEVELS >= 3) { |
| 2442 | pwfield &= ~MIPS_PWFIELD_MDI_MASK; |
| 2443 | pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; |
| 2444 | } |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2445 | /* Set the PTEI right shift */ |
| 2446 | ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; |
| 2447 | pwfield |= ptei; |
| 2448 | write_c0_pwfield(pwfield); |
| 2449 | /* Check whether the PTEI value is supported */ |
| 2450 | back_to_back_c0_hazard(); |
| 2451 | pwfield = read_c0_pwfield(); |
| 2452 | if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) |
| 2453 | != ptei) { |
| 2454 | pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", |
| 2455 | ptei); |
| 2456 | /* |
| 2457 | * Drop option to avoid HTW being enabled via another path |
| 2458 | * (eg htw_reset()) |
| 2459 | */ |
| 2460 | current_cpu_data.options &= ~MIPS_CPU_HTW; |
| 2461 | return; |
| 2462 | } |
| 2463 | |
| 2464 | pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; |
| 2465 | pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; |
Paul Burton | cab25bc | 2015-09-22 12:03:37 -0700 | [diff] [blame] | 2466 | if (CONFIG_PGTABLE_LEVELS >= 3) |
| 2467 | pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 2468 | |
James Hogan | aa76042 | 2016-05-27 22:25:23 +0100 | [diff] [blame] | 2469 | /* Set pointer size to size of directory pointers */ |
Masahiro Yamada | 97f2645 | 2016-08-03 13:45:50 -0700 | [diff] [blame] | 2470 | if (IS_ENABLED(CONFIG_64BIT)) |
James Hogan | aa76042 | 2016-05-27 22:25:23 +0100 | [diff] [blame] | 2471 | pwsize |= MIPS_PWSIZE_PS_MASK; |
| 2472 | /* PTEs may be multiple pointers long (e.g. with XPA) */ |
| 2473 | pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) |
| 2474 | & MIPS_PWSIZE_PTEW_MASK; |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 2475 | |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2476 | write_c0_pwsize(pwsize); |
| 2477 | |
| 2478 | /* Make sure everything is set before we enable the HTW */ |
| 2479 | back_to_back_c0_hazard(); |
| 2480 | |
James Hogan | aa76042 | 2016-05-27 22:25:23 +0100 | [diff] [blame] | 2481 | /* |
| 2482 | * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of |
| 2483 | * the pwctl fields. |
| 2484 | */ |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2485 | config = 1 << MIPS_PWCTL_PWEN_SHIFT; |
Masahiro Yamada | 97f2645 | 2016-08-03 13:45:50 -0700 | [diff] [blame] | 2486 | if (IS_ENABLED(CONFIG_64BIT)) |
James Hogan | aa76042 | 2016-05-27 22:25:23 +0100 | [diff] [blame] | 2487 | config |= MIPS_PWCTL_XU_MASK; |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2488 | write_c0_pwctl(config); |
| 2489 | pr_info("Hardware Page Table Walker enabled\n"); |
| 2490 | |
| 2491 | print_htw_config(); |
| 2492 | } |
| 2493 | |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 2494 | static void config_xpa_params(void) |
| 2495 | { |
| 2496 | #ifdef CONFIG_XPA |
| 2497 | unsigned int pagegrain; |
| 2498 | |
| 2499 | if (mips_xpa_disabled) { |
| 2500 | pr_info("Extended Physical Addressing (XPA) disabled\n"); |
| 2501 | return; |
| 2502 | } |
| 2503 | |
| 2504 | pagegrain = read_c0_pagegrain(); |
| 2505 | write_c0_pagegrain(pagegrain | PG_ELPA); |
| 2506 | back_to_back_c0_hazard(); |
| 2507 | pagegrain = read_c0_pagegrain(); |
| 2508 | |
| 2509 | if (pagegrain & PG_ELPA) |
| 2510 | pr_info("Extended Physical Addressing (XPA) enabled\n"); |
| 2511 | else |
| 2512 | panic("Extended Physical Addressing (XPA) disabled"); |
| 2513 | #endif |
| 2514 | } |
| 2515 | |
Paul Burton | 00bf1c6 | 2015-09-22 11:42:52 -0700 | [diff] [blame] | 2516 | static void check_pabits(void) |
| 2517 | { |
| 2518 | unsigned long entry; |
| 2519 | unsigned pabits, fillbits; |
| 2520 | |
| 2521 | if (!cpu_has_rixi || !_PAGE_NO_EXEC) { |
| 2522 | /* |
| 2523 | * We'll only be making use of the fact that we can rotate bits |
| 2524 | * into the fill if the CPU supports RIXI, so don't bother |
| 2525 | * probing this for CPUs which don't. |
| 2526 | */ |
| 2527 | return; |
| 2528 | } |
| 2529 | |
| 2530 | write_c0_entrylo0(~0ul); |
| 2531 | back_to_back_c0_hazard(); |
| 2532 | entry = read_c0_entrylo0(); |
| 2533 | |
| 2534 | /* clear all non-PFN bits */ |
| 2535 | entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); |
| 2536 | entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); |
| 2537 | |
| 2538 | /* find a lower bound on PABITS, and upper bound on fill bits */ |
| 2539 | pabits = fls_long(entry) + 6; |
| 2540 | fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); |
| 2541 | |
| 2542 | /* minus the RI & XI bits */ |
| 2543 | fillbits -= min_t(unsigned, fillbits, 2); |
| 2544 | |
| 2545 | if (fillbits >= ilog2(_PAGE_NO_EXEC)) |
| 2546 | fill_includes_sw_bits = true; |
| 2547 | |
| 2548 | pr_debug("Entry* registers contain %u fill bits\n", fillbits); |
| 2549 | } |
| 2550 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2551 | void build_tlb_refill_handler(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2552 | { |
| 2553 | /* |
| 2554 | * The refill handler is generated per-CPU, multi-node systems |
| 2555 | * may have local storage for it. The other handlers are only |
| 2556 | * needed once. |
| 2557 | */ |
| 2558 | static int run_once = 0; |
| 2559 | |
Masahiro Yamada | 97f2645 | 2016-08-03 13:45:50 -0700 | [diff] [blame] | 2560 | if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) |
Paul Burton | e56c7e1 | 2016-04-19 09:25:11 +0100 | [diff] [blame] | 2561 | panic("Kernels supporting XPA currently require CPUs with RIXI"); |
| 2562 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 2563 | output_pgtable_bits_defines(); |
Paul Burton | 00bf1c6 | 2015-09-22 11:42:52 -0700 | [diff] [blame] | 2564 | check_pabits(); |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 2565 | |
David Daney | 1ec5632 | 2010-04-28 12:16:18 -0700 | [diff] [blame] | 2566 | #ifdef CONFIG_64BIT |
| 2567 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); |
| 2568 | #endif |
| 2569 | |
Ralf Baechle | 10cc352 | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 2570 | switch (current_cpu_type()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2571 | case CPU_R2000: |
| 2572 | case CPU_R3000: |
| 2573 | case CPU_R3000A: |
| 2574 | case CPU_R3081E: |
| 2575 | case CPU_TX3912: |
| 2576 | case CPU_TX3922: |
| 2577 | case CPU_TX3927: |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 2578 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
Huacai Chen | 8759934 | 2013-03-17 11:49:38 +0000 | [diff] [blame] | 2579 | if (cpu_has_local_ebase) |
| 2580 | build_r3000_tlb_refill_handler(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2581 | if (!run_once) { |
Huacai Chen | 8759934 | 2013-03-17 11:49:38 +0000 | [diff] [blame] | 2582 | if (!cpu_has_local_ebase) |
| 2583 | build_r3000_tlb_refill_handler(); |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 2584 | build_setup_pgd(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2585 | build_r3000_tlb_load_handler(); |
| 2586 | build_r3000_tlb_store_handler(); |
| 2587 | build_r3000_tlb_modify_handler(); |
Jonas Gorski | a3d9086 | 2013-06-21 17:48:48 +0000 | [diff] [blame] | 2588 | flush_tlb_handlers(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2589 | run_once++; |
| 2590 | } |
David Daney | 82622284 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 2591 | #else |
| 2592 | panic("No R3000 TLB refill handler"); |
| 2593 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2594 | break; |
| 2595 | |
| 2596 | case CPU_R6000: |
| 2597 | case CPU_R6000A: |
| 2598 | panic("No R6000 TLB refill handler yet"); |
| 2599 | break; |
| 2600 | |
| 2601 | case CPU_R8000: |
| 2602 | panic("No R8000 TLB refill handler yet"); |
| 2603 | break; |
| 2604 | |
| 2605 | default: |
Huacai Chen | 380cd58 | 2016-03-03 09:45:12 +0800 | [diff] [blame] | 2606 | if (cpu_has_ldpte) |
| 2607 | setup_pw(); |
| 2608 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2609 | if (!run_once) { |
David Daney | bf28607 | 2011-07-05 16:34:46 -0700 | [diff] [blame] | 2610 | scratch_reg = allocate_kscratch(); |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 2611 | build_setup_pgd(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2612 | build_r4000_tlb_load_handler(); |
| 2613 | build_r4000_tlb_store_handler(); |
| 2614 | build_r4000_tlb_modify_handler(); |
Huacai Chen | 380cd58 | 2016-03-03 09:45:12 +0800 | [diff] [blame] | 2615 | if (cpu_has_ldpte) |
| 2616 | build_loongson3_tlb_refill_handler(); |
| 2617 | else if (!cpu_has_local_ebase) |
Huacai Chen | 8759934 | 2013-03-17 11:49:38 +0000 | [diff] [blame] | 2618 | build_r4000_tlb_refill_handler(); |
Jonas Gorski | a3d9086 | 2013-06-21 17:48:48 +0000 | [diff] [blame] | 2619 | flush_tlb_handlers(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2620 | run_once++; |
| 2621 | } |
Huacai Chen | 8759934 | 2013-03-17 11:49:38 +0000 | [diff] [blame] | 2622 | if (cpu_has_local_ebase) |
| 2623 | build_r4000_tlb_refill_handler(); |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 2624 | if (cpu_has_xpa) |
| 2625 | config_xpa_params(); |
Markos Chandras | f1014d1 | 2014-07-14 12:47:09 +0100 | [diff] [blame] | 2626 | if (cpu_has_htw) |
| 2627 | config_htw_params(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2628 | } |
| 2629 | } |