blob: 186eb8ebfda643e2155579f5d36ad7fc518fb4b6 [file] [log] [blame]
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
Stephen Hemminger747802a2005-06-27 11:33:16 -070010 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040011 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
Stephen Hemminger798b6b12006-10-22 20:16:57 -070014 * the Free Software Foundation; either version 2 of the License.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040015 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020026#include <linux/in.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040027#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
Al Viro40754002005-04-03 09:15:52 +010038#include <linux/dma-mapping.h>
Stephen Hemminger678aa1f2007-10-16 12:15:54 -070039#include <linux/debugfs.h>
40#include <linux/seq_file.h>
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -080041#include <linux/mii.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040042#include <asm/irq.h>
43
44#include "skge.h"
45
46#define DRV_NAME "skge"
Stephen Hemmingerbf9f56d2007-11-26 11:54:53 -080047#define DRV_VERSION "1.13"
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040048#define PFX DRV_NAME " "
49
50#define DEFAULT_TX_RING_SIZE 128
51#define DEFAULT_RX_RING_SIZE 512
52#define MAX_TX_RING_SIZE 1024
Stephen Hemminger9db96472006-06-06 10:11:12 -070053#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040054#define MAX_RX_RING_SIZE 4096
Stephen Hemminger19a33d42005-06-27 11:33:15 -070055#define RX_COPY_THRESHOLD 128
56#define RX_BUF_SIZE 1536
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040057#define PHY_RETRIES 1000
58#define ETH_JUMBO_MTU 9000
59#define TX_WATCHDOG (5 * HZ)
60#define NAPI_WEIGHT 64
Stephen Hemminger6abebb52005-07-22 16:26:10 -070061#define BLINK_MS 250
Stephen Hemminger501fb722007-10-16 12:15:51 -070062#define LINK_HZ HZ
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040063
Stephen Hemmingerafa151b2007-10-16 12:15:53 -070064#define SKGE_EEPROM_MAGIC 0x9933aabb
65
66
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040067MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
Stephen Hemminger65ebe632007-01-23 11:38:57 -080068MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040069MODULE_LICENSE("GPL");
70MODULE_VERSION(DRV_VERSION);
71
72static const u32 default_msg
73 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
74 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
75
76static int debug = -1; /* defaults above */
77module_param(debug, int, 0);
78MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
79
80static const struct pci_device_id skge_id_table[] = {
Stephen Hemminger275834d2005-06-27 11:33:03 -070081 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
82 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
83 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
84 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
Stephen Hemmingerf19841f2007-02-23 14:04:54 -080085 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
Stephen Hemminger2d2a3872006-05-17 14:37:04 -070086 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
Stephen Hemminger275834d2005-06-27 11:33:03 -070087 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
88 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
89 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
Stephen Hemminger275834d2005-06-27 11:33:03 -070090 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
Stephen Hemmingerf19841f2007-02-23 14:04:54 -080091 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040092 { 0 }
93};
94MODULE_DEVICE_TABLE(pci, skge_id_table);
95
96static int skge_up(struct net_device *dev);
97static int skge_down(struct net_device *dev);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -080098static void skge_phy_reset(struct skge_port *skge);
Stephen Hemminger513f5332006-09-01 15:53:49 -070099static void skge_tx_clean(struct net_device *dev);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800100static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
101static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400102static void genesis_get_stats(struct skge_port *skge, u64 *data);
103static void yukon_get_stats(struct skge_port *skge, u64 *data);
104static void yukon_init(struct skge_hw *hw, int port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400105static void genesis_mac_init(struct skge_hw *hw, int port);
Stephen Hemminger45bada62005-06-27 11:33:12 -0700106static void genesis_link_up(struct skge_port *skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400107
Stephen Hemminger7e676d92005-06-27 11:33:13 -0700108/* Avoid conditionals by using array */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400109static const int txqaddr[] = { Q_XA1, Q_XA2 };
110static const int rxqaddr[] = { Q_R1, Q_R2 };
111static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
112static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -0700113static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
114static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400115
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400116static int skge_get_regs_len(struct net_device *dev)
117{
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700118 return 0x4000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400119}
120
121/*
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700122 * Returns copy of whole control register region
123 * Note: skip RAM address register because accessing it will
124 * cause bus hangs!
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400125 */
126static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
127 void *p)
128{
129 const struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400130 const void __iomem *io = skge->hw->regs;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400131
132 regs->version = 1;
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700133 memset(p, 0, regs->len);
134 memcpy_fromio(p, io, B3_RAM_ADDR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400135
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700136 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
137 regs->len - B3_RI_WTO_R1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400138}
139
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800140/* Wake on Lan only supported on Yukon chips with rev 1 or above */
Stephen Hemmingera504e642007-02-02 08:22:53 -0800141static u32 wol_supported(const struct skge_hw *hw)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400142{
Stephen Hemmingerd17ecb22007-05-07 11:01:55 -0700143 if (hw->chip_id == CHIP_ID_GENESIS)
Stephen Hemmingera504e642007-02-02 08:22:53 -0800144 return 0;
Stephen Hemmingerd17ecb22007-05-07 11:01:55 -0700145
146 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
147 return 0;
148
149 return WAKE_MAGIC | WAKE_PHY;
Stephen Hemmingera504e642007-02-02 08:22:53 -0800150}
151
152static u32 pci_wake_enabled(struct pci_dev *dev)
153{
154 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
155 u16 value;
156
157 /* If device doesn't support PM Capabilities, but request is to disable
158 * wake events, it's a nop; otherwise fail */
159 if (!pm)
160 return 0;
161
162 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
163
164 value &= PCI_PM_CAP_PME_MASK;
165 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
166
167 return value != 0;
168}
169
170static void skge_wol_init(struct skge_port *skge)
171{
172 struct skge_hw *hw = skge->hw;
173 int port = skge->port;
Stephen Hemminger692412b2007-04-09 15:32:45 -0700174 u16 ctrl;
Stephen Hemmingera504e642007-02-02 08:22:53 -0800175
Stephen Hemmingera504e642007-02-02 08:22:53 -0800176 skge_write16(hw, B0_CTST, CS_RST_CLR);
177 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
178
Stephen Hemminger692412b2007-04-09 15:32:45 -0700179 /* Turn on Vaux */
180 skge_write8(hw, B0_POWER_CTRL,
181 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
182
183 /* WA code for COMA mode -- clear PHY reset */
184 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
185 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
186 u32 reg = skge_read32(hw, B2_GP_IO);
187 reg |= GP_DIR_9;
188 reg &= ~GP_IO_9;
189 skge_write32(hw, B2_GP_IO, reg);
190 }
191
192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_SET);
196
197 skge_write32(hw, SK_REG(port, GPHY_CTRL),
198 GPC_DIS_SLEEP |
199 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
200 GPC_ANEG_1 | GPC_RST_CLR);
201
202 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
Stephen Hemmingera504e642007-02-02 08:22:53 -0800203
204 /* Force to 10/100 skge_reset will re-enable on resume */
Stephen Hemminger692412b2007-04-09 15:32:45 -0700205 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
206 PHY_AN_100FULL | PHY_AN_100HALF |
207 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
208 /* no 1000 HD/FD */
209 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
210 gm_phy_write(hw, port, PHY_MARV_CTRL,
211 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
212 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
Stephen Hemmingera504e642007-02-02 08:22:53 -0800213
Stephen Hemmingera504e642007-02-02 08:22:53 -0800214
215 /* Set GMAC to no flow control and auto update for speed/duplex */
216 gma_write16(hw, port, GM_GP_CTRL,
217 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
218 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
219
220 /* Set WOL address */
221 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
222 skge->netdev->dev_addr, ETH_ALEN);
223
224 /* Turn on appropriate WOL control bits */
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
226 ctrl = 0;
227 if (skge->wol & WAKE_PHY)
228 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
231
232 if (skge->wol & WAKE_MAGIC)
233 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
234 else
235 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
236
237 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
238 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
239
240 /* block receiver */
241 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400242}
243
244static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245{
246 struct skge_port *skge = netdev_priv(dev);
247
Stephen Hemmingera504e642007-02-02 08:22:53 -0800248 wol->supported = wol_supported(skge->hw);
249 wol->wolopts = skge->wol;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400250}
251
252static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
253{
254 struct skge_port *skge = netdev_priv(dev);
255 struct skge_hw *hw = skge->hw;
256
Stephen Hemminger692412b2007-04-09 15:32:45 -0700257 if (wol->wolopts & ~wol_supported(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400258 return -EOPNOTSUPP;
259
Stephen Hemmingera504e642007-02-02 08:22:53 -0800260 skge->wol = wol->wolopts;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400261 return 0;
262}
263
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800264/* Determine supported/advertised modes based on hardware.
265 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700266 */
267static u32 skge_supported_modes(const struct skge_hw *hw)
268{
269 u32 supported;
270
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700271 if (hw->copper) {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700272 supported = SUPPORTED_10baseT_Half
273 | SUPPORTED_10baseT_Full
274 | SUPPORTED_100baseT_Half
275 | SUPPORTED_100baseT_Full
276 | SUPPORTED_1000baseT_Half
277 | SUPPORTED_1000baseT_Full
278 | SUPPORTED_Autoneg| SUPPORTED_TP;
279
280 if (hw->chip_id == CHIP_ID_GENESIS)
281 supported &= ~(SUPPORTED_10baseT_Half
282 | SUPPORTED_10baseT_Full
283 | SUPPORTED_100baseT_Half
284 | SUPPORTED_100baseT_Full);
285
286 else if (hw->chip_id == CHIP_ID_YUKON)
287 supported &= ~SUPPORTED_1000baseT_Half;
288 } else
Stephen Hemminger4b67be92006-10-05 15:49:51 -0700289 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
290 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700291
292 return supported;
293}
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400294
295static int skge_get_settings(struct net_device *dev,
296 struct ethtool_cmd *ecmd)
297{
298 struct skge_port *skge = netdev_priv(dev);
299 struct skge_hw *hw = skge->hw;
300
301 ecmd->transceiver = XCVR_INTERNAL;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700302 ecmd->supported = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400303
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700304 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400305 ecmd->port = PORT_TP;
306 ecmd->phy_address = hw->phy_addr;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700307 } else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400308 ecmd->port = PORT_FIBRE;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400309
310 ecmd->advertising = skge->advertising;
311 ecmd->autoneg = skge->autoneg;
312 ecmd->speed = skge->speed;
313 ecmd->duplex = skge->duplex;
314 return 0;
315}
316
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400317static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
318{
319 struct skge_port *skge = netdev_priv(dev);
320 const struct skge_hw *hw = skge->hw;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700321 u32 supported = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400322
323 if (ecmd->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700324 ecmd->advertising = supported;
325 skge->duplex = -1;
326 skge->speed = -1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400327 } else {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700328 u32 setting;
329
Stephen Hemminger2c668512005-07-22 16:26:07 -0700330 switch (ecmd->speed) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400331 case SPEED_1000:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700332 if (ecmd->duplex == DUPLEX_FULL)
333 setting = SUPPORTED_1000baseT_Full;
334 else if (ecmd->duplex == DUPLEX_HALF)
335 setting = SUPPORTED_1000baseT_Half;
336 else
337 return -EINVAL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400338 break;
339 case SPEED_100:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700340 if (ecmd->duplex == DUPLEX_FULL)
341 setting = SUPPORTED_100baseT_Full;
342 else if (ecmd->duplex == DUPLEX_HALF)
343 setting = SUPPORTED_100baseT_Half;
344 else
345 return -EINVAL;
346 break;
347
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400348 case SPEED_10:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700349 if (ecmd->duplex == DUPLEX_FULL)
350 setting = SUPPORTED_10baseT_Full;
351 else if (ecmd->duplex == DUPLEX_HALF)
352 setting = SUPPORTED_10baseT_Half;
353 else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400354 return -EINVAL;
355 break;
356 default:
357 return -EINVAL;
358 }
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700359
360 if ((setting & supported) == 0)
361 return -EINVAL;
362
363 skge->speed = ecmd->speed;
364 skge->duplex = ecmd->duplex;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400365 }
366
367 skge->autoneg = ecmd->autoneg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400368 skge->advertising = ecmd->advertising;
369
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800370 if (netif_running(dev))
371 skge_phy_reset(skge);
372
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400373 return (0);
374}
375
376static void skge_get_drvinfo(struct net_device *dev,
377 struct ethtool_drvinfo *info)
378{
379 struct skge_port *skge = netdev_priv(dev);
380
381 strcpy(info->driver, DRV_NAME);
382 strcpy(info->version, DRV_VERSION);
383 strcpy(info->fw_version, "N/A");
384 strcpy(info->bus_info, pci_name(skge->hw->pdev));
385}
386
387static const struct skge_stat {
388 char name[ETH_GSTRING_LEN];
389 u16 xmac_offset;
390 u16 gma_offset;
391} skge_stats[] = {
392 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
393 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
394
395 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
396 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
397 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
398 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
399 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
400 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
401 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
402 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
403
404 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
405 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
406 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
407 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
408 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
409 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
410
411 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
412 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
413 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
414 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
415 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
416};
417
Jeff Garzikb9f2c042007-10-03 18:07:32 -0700418static int skge_get_sset_count(struct net_device *dev, int sset)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400419{
Jeff Garzikb9f2c042007-10-03 18:07:32 -0700420 switch (sset) {
421 case ETH_SS_STATS:
422 return ARRAY_SIZE(skge_stats);
423 default:
424 return -EOPNOTSUPP;
425 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400426}
427
428static void skge_get_ethtool_stats(struct net_device *dev,
429 struct ethtool_stats *stats, u64 *data)
430{
431 struct skge_port *skge = netdev_priv(dev);
432
433 if (skge->hw->chip_id == CHIP_ID_GENESIS)
434 genesis_get_stats(skge, data);
435 else
436 yukon_get_stats(skge, data);
437}
438
439/* Use hardware MIB variables for critical path statistics and
440 * transmit feedback not reported at interrupt.
441 * Other errors are accounted for in interrupt handler.
442 */
443static struct net_device_stats *skge_get_stats(struct net_device *dev)
444{
445 struct skge_port *skge = netdev_priv(dev);
446 u64 data[ARRAY_SIZE(skge_stats)];
447
448 if (skge->hw->chip_id == CHIP_ID_GENESIS)
449 genesis_get_stats(skge, data);
450 else
451 yukon_get_stats(skge, data);
452
Stephen Hemmingerda007722007-10-16 12:15:52 -0700453 dev->stats.tx_bytes = data[0];
454 dev->stats.rx_bytes = data[1];
455 dev->stats.tx_packets = data[2] + data[4] + data[6];
456 dev->stats.rx_packets = data[3] + data[5] + data[7];
457 dev->stats.multicast = data[3] + data[5];
458 dev->stats.collisions = data[10];
459 dev->stats.tx_aborted_errors = data[12];
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400460
Stephen Hemmingerda007722007-10-16 12:15:52 -0700461 return &dev->stats;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400462}
463
464static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
465{
466 int i;
467
Stephen Hemminger95566062005-06-27 11:33:02 -0700468 switch (stringset) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400469 case ETH_SS_STATS:
470 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
471 memcpy(data + i * ETH_GSTRING_LEN,
472 skge_stats[i].name, ETH_GSTRING_LEN);
473 break;
474 }
475}
476
477static void skge_get_ring_param(struct net_device *dev,
478 struct ethtool_ringparam *p)
479{
480 struct skge_port *skge = netdev_priv(dev);
481
482 p->rx_max_pending = MAX_RX_RING_SIZE;
483 p->tx_max_pending = MAX_TX_RING_SIZE;
484 p->rx_mini_max_pending = 0;
485 p->rx_jumbo_max_pending = 0;
486
487 p->rx_pending = skge->rx_ring.count;
488 p->tx_pending = skge->tx_ring.count;
489 p->rx_mini_pending = 0;
490 p->rx_jumbo_pending = 0;
491}
492
493static int skge_set_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495{
496 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger3b8bb472005-12-14 15:47:48 -0800497 int err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400498
499 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
Stephen Hemminger9db96472006-06-06 10:11:12 -0700500 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400501 return -EINVAL;
502
503 skge->rx_ring.count = p->rx_pending;
504 skge->tx_ring.count = p->tx_pending;
505
506 if (netif_running(dev)) {
507 skge_down(dev);
Stephen Hemminger3b8bb472005-12-14 15:47:48 -0800508 err = skge_up(dev);
509 if (err)
510 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400511 }
512
513 return 0;
514}
515
516static u32 skge_get_msglevel(struct net_device *netdev)
517{
518 struct skge_port *skge = netdev_priv(netdev);
519 return skge->msg_enable;
520}
521
522static void skge_set_msglevel(struct net_device *netdev, u32 value)
523{
524 struct skge_port *skge = netdev_priv(netdev);
525 skge->msg_enable = value;
526}
527
528static int skge_nway_reset(struct net_device *dev)
529{
530 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400531
532 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
533 return -EINVAL;
534
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800535 skge_phy_reset(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400536 return 0;
537}
538
539static int skge_set_sg(struct net_device *dev, u32 data)
540{
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543
544 if (hw->chip_id == CHIP_ID_GENESIS && data)
545 return -EOPNOTSUPP;
546 return ethtool_op_set_sg(dev, data);
547}
548
549static int skge_set_tx_csum(struct net_device *dev, u32 data)
550{
551 struct skge_port *skge = netdev_priv(dev);
552 struct skge_hw *hw = skge->hw;
553
554 if (hw->chip_id == CHIP_ID_GENESIS && data)
555 return -EOPNOTSUPP;
556
557 return ethtool_op_set_tx_csum(dev, data);
558}
559
560static u32 skge_get_rx_csum(struct net_device *dev)
561{
562 struct skge_port *skge = netdev_priv(dev);
563
564 return skge->rx_csum;
565}
566
567/* Only Yukon supports checksum offload. */
568static int skge_set_rx_csum(struct net_device *dev, u32 data)
569{
570 struct skge_port *skge = netdev_priv(dev);
571
572 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
573 return -EOPNOTSUPP;
574
575 skge->rx_csum = data;
576 return 0;
577}
578
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400579static void skge_get_pauseparam(struct net_device *dev,
580 struct ethtool_pauseparam *ecmd)
581{
582 struct skge_port *skge = netdev_priv(dev);
583
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700584 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
585 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
586 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400587
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700588 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400589}
590
591static int skge_set_pauseparam(struct net_device *dev,
592 struct ethtool_pauseparam *ecmd)
593{
594 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700595 struct ethtool_pauseparam old;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400596
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700597 skge_get_pauseparam(dev, &old);
598
599 if (ecmd->autoneg != old.autoneg)
600 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
601 else {
602 if (ecmd->rx_pause && ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_SYMMETRIC;
604 else if (ecmd->rx_pause && !ecmd->tx_pause)
605 skge->flow_control = FLOW_MODE_SYM_OR_REM;
606 else if (!ecmd->rx_pause && ecmd->tx_pause)
607 skge->flow_control = FLOW_MODE_LOC_SEND;
608 else
609 skge->flow_control = FLOW_MODE_NONE;
610 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400611
Stephen Hemmingere8df8552005-12-14 15:47:45 -0800612 if (netif_running(dev))
613 skge_phy_reset(skge);
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700614
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400615 return 0;
616}
617
618/* Chip internal frequency for clock calculations */
619static inline u32 hwkhz(const struct skge_hw *hw)
620{
Stephen Hemminger187ff3b2006-07-19 14:08:42 -0700621 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400622}
623
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800624/* Chip HZ to microseconds */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400625static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
626{
627 return (ticks * 1000) / hwkhz(hw);
628}
629
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800630/* Microseconds to chip HZ */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400631static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
632{
633 return hwkhz(hw) * usec / 1000;
634}
635
636static int skge_get_coalesce(struct net_device *dev,
637 struct ethtool_coalesce *ecmd)
638{
639 struct skge_port *skge = netdev_priv(dev);
640 struct skge_hw *hw = skge->hw;
641 int port = skge->port;
642
643 ecmd->rx_coalesce_usecs = 0;
644 ecmd->tx_coalesce_usecs = 0;
645
646 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
647 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
648 u32 msk = skge_read32(hw, B2_IRQM_MSK);
649
650 if (msk & rxirqmask[port])
651 ecmd->rx_coalesce_usecs = delay;
652 if (msk & txirqmask[port])
653 ecmd->tx_coalesce_usecs = delay;
654 }
655
656 return 0;
657}
658
659/* Note: interrupt timer is per board, but can turn on/off per port */
660static int skge_set_coalesce(struct net_device *dev,
661 struct ethtool_coalesce *ecmd)
662{
663 struct skge_port *skge = netdev_priv(dev);
664 struct skge_hw *hw = skge->hw;
665 int port = skge->port;
666 u32 msk = skge_read32(hw, B2_IRQM_MSK);
667 u32 delay = 25;
668
669 if (ecmd->rx_coalesce_usecs == 0)
670 msk &= ~rxirqmask[port];
671 else if (ecmd->rx_coalesce_usecs < 25 ||
672 ecmd->rx_coalesce_usecs > 33333)
673 return -EINVAL;
674 else {
675 msk |= rxirqmask[port];
676 delay = ecmd->rx_coalesce_usecs;
677 }
678
679 if (ecmd->tx_coalesce_usecs == 0)
680 msk &= ~txirqmask[port];
681 else if (ecmd->tx_coalesce_usecs < 25 ||
682 ecmd->tx_coalesce_usecs > 33333)
683 return -EINVAL;
684 else {
685 msk |= txirqmask[port];
686 delay = min(delay, ecmd->rx_coalesce_usecs);
687 }
688
689 skge_write32(hw, B2_IRQM_MSK, msk);
690 if (msk == 0)
691 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
692 else {
693 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
694 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
695 }
696 return 0;
697}
698
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700699enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
700static void skge_led(struct skge_port *skge, enum led_mode mode)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400701{
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400702 struct skge_hw *hw = skge->hw;
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700703 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400704
Stephen Hemminger9cbe3302007-03-16 14:01:28 -0700705 spin_lock_bh(&hw->phy_lock);
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700706 if (hw->chip_id == CHIP_ID_GENESIS) {
707 switch (mode) {
708 case LED_MODE_OFF:
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700709 if (hw->phy_type == SK_PHY_BCOM)
710 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
711 else {
712 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
713 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
714 }
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700715 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
716 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
717 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
718 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400719
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700720 case LED_MODE_ON:
721 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
722 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
723
724 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
725 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
726
727 break;
728
729 case LED_MODE_TST:
730 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
731 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
732 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
733
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700734 if (hw->phy_type == SK_PHY_BCOM)
735 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
736 else {
737 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
738 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
739 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
740 }
741
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700742 }
743 } else {
744 switch (mode) {
745 case LED_MODE_OFF:
746 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
747 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
748 PHY_M_LED_MO_DUP(MO_LED_OFF) |
749 PHY_M_LED_MO_10(MO_LED_OFF) |
750 PHY_M_LED_MO_100(MO_LED_OFF) |
751 PHY_M_LED_MO_1000(MO_LED_OFF) |
752 PHY_M_LED_MO_RX(MO_LED_OFF));
753 break;
754 case LED_MODE_ON:
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
756 PHY_M_LED_PULS_DUR(PULS_170MS) |
757 PHY_M_LED_BLINK_RT(BLINK_84MS) |
758 PHY_M_LEDC_TX_CTRL |
759 PHY_M_LEDC_DP_CTRL);
Stephen Hemminger46a60f22005-09-09 12:54:56 -0700760
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700761 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
762 PHY_M_LED_MO_RX(MO_LED_OFF) |
763 (skge->speed == SPEED_100 ?
764 PHY_M_LED_MO_100(MO_LED_ON) : 0));
765 break;
766 case LED_MODE_TST:
767 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
768 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
769 PHY_M_LED_MO_DUP(MO_LED_ON) |
770 PHY_M_LED_MO_10(MO_LED_ON) |
771 PHY_M_LED_MO_100(MO_LED_ON) |
772 PHY_M_LED_MO_1000(MO_LED_ON) |
773 PHY_M_LED_MO_RX(MO_LED_ON));
774 }
775 }
Stephen Hemminger9cbe3302007-03-16 14:01:28 -0700776 spin_unlock_bh(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400777}
778
779/* blink LED's for finding board */
780static int skge_phys_id(struct net_device *dev, u32 data)
781{
782 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700783 unsigned long ms;
784 enum led_mode mode = LED_MODE_TST;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400785
Stephen Hemminger95566062005-06-27 11:33:02 -0700786 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700787 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
788 else
789 ms = data * 1000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400790
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700791 while (ms > 0) {
792 skge_led(skge, mode);
793 mode ^= LED_MODE_TST;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400794
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700795 if (msleep_interruptible(BLINK_MS))
796 break;
797 ms -= BLINK_MS;
798 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400799
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700800 /* back to regular LED state */
801 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400802
803 return 0;
804}
805
Stephen Hemmingerafa151b2007-10-16 12:15:53 -0700806static int skge_get_eeprom_len(struct net_device *dev)
807{
808 struct skge_port *skge = netdev_priv(dev);
809 u32 reg2;
810
811 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
812 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
813}
814
815static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
816{
817 u32 val;
818
819 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
820
821 do {
822 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
823 } while (!(offset & PCI_VPD_ADDR_F));
824
825 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
826 return val;
827}
828
829static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
830{
831 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
832 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
833 offset | PCI_VPD_ADDR_F);
834
835 do {
836 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
837 } while (offset & PCI_VPD_ADDR_F);
838}
839
840static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
841 u8 *data)
842{
843 struct skge_port *skge = netdev_priv(dev);
844 struct pci_dev *pdev = skge->hw->pdev;
845 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
846 int length = eeprom->len;
847 u16 offset = eeprom->offset;
848
849 if (!cap)
850 return -EINVAL;
851
852 eeprom->magic = SKGE_EEPROM_MAGIC;
853
854 while (length > 0) {
855 u32 val = skge_vpd_read(pdev, cap, offset);
856 int n = min_t(int, length, sizeof(val));
857
858 memcpy(data, &val, n);
859 length -= n;
860 data += n;
861 offset += n;
862 }
863 return 0;
864}
865
866static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
867 u8 *data)
868{
869 struct skge_port *skge = netdev_priv(dev);
870 struct pci_dev *pdev = skge->hw->pdev;
871 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
872 int length = eeprom->len;
873 u16 offset = eeprom->offset;
874
875 if (!cap)
876 return -EINVAL;
877
878 if (eeprom->magic != SKGE_EEPROM_MAGIC)
879 return -EINVAL;
880
881 while (length > 0) {
882 u32 val;
883 int n = min_t(int, length, sizeof(val));
884
885 if (n < sizeof(val))
886 val = skge_vpd_read(pdev, cap, offset);
887 memcpy(&val, data, n);
888
889 skge_vpd_write(pdev, cap, offset, val);
890
891 length -= n;
892 data += n;
893 offset += n;
894 }
895 return 0;
896}
897
Jeff Garzik7282d492006-09-13 14:30:00 -0400898static const struct ethtool_ops skge_ethtool_ops = {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400899 .get_settings = skge_get_settings,
900 .set_settings = skge_set_settings,
901 .get_drvinfo = skge_get_drvinfo,
902 .get_regs_len = skge_get_regs_len,
903 .get_regs = skge_get_regs,
904 .get_wol = skge_get_wol,
905 .set_wol = skge_set_wol,
906 .get_msglevel = skge_get_msglevel,
907 .set_msglevel = skge_set_msglevel,
908 .nway_reset = skge_nway_reset,
909 .get_link = ethtool_op_get_link,
Stephen Hemmingerafa151b2007-10-16 12:15:53 -0700910 .get_eeprom_len = skge_get_eeprom_len,
911 .get_eeprom = skge_get_eeprom,
912 .set_eeprom = skge_set_eeprom,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400913 .get_ringparam = skge_get_ring_param,
914 .set_ringparam = skge_set_ring_param,
915 .get_pauseparam = skge_get_pauseparam,
916 .set_pauseparam = skge_set_pauseparam,
917 .get_coalesce = skge_get_coalesce,
918 .set_coalesce = skge_set_coalesce,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400919 .set_sg = skge_set_sg,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400920 .set_tx_csum = skge_set_tx_csum,
921 .get_rx_csum = skge_get_rx_csum,
922 .set_rx_csum = skge_set_rx_csum,
923 .get_strings = skge_get_strings,
924 .phys_id = skge_phys_id,
Jeff Garzikb9f2c042007-10-03 18:07:32 -0700925 .get_sset_count = skge_get_sset_count,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400926 .get_ethtool_stats = skge_get_ethtool_stats,
927};
928
929/*
930 * Allocate ring elements and chain them together
931 * One-to-one association of board descriptors with ring elements
932 */
Stephen Hemmingerc3da1442006-03-21 10:57:01 -0800933static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400934{
935 struct skge_tx_desc *d;
936 struct skge_element *e;
937 int i;
938
Robert P. J. Daycd861282006-12-13 00:34:52 -0800939 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400940 if (!ring->start)
941 return -ENOMEM;
942
943 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
944 e->desc = d;
945 if (i == ring->count - 1) {
946 e->next = ring->start;
947 d->next_offset = base;
948 } else {
949 e->next = e + 1;
950 d->next_offset = base + (i+1) * sizeof(*d);
951 }
952 }
953 ring->to_use = ring->to_clean = ring->start;
954
955 return 0;
956}
957
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700958/* Allocate and setup a new buffer for receiving */
959static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
960 struct sk_buff *skb, unsigned int bufsize)
961{
962 struct skge_rx_desc *rd = e->desc;
963 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400964
965 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
966 PCI_DMA_FROMDEVICE);
967
968 rd->dma_lo = map;
969 rd->dma_hi = map >> 32;
970 e->skb = skb;
971 rd->csum1_start = ETH_HLEN;
972 rd->csum2_start = ETH_HLEN;
973 rd->csum1 = 0;
974 rd->csum2 = 0;
975
976 wmb();
977
978 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
979 pci_unmap_addr_set(e, mapaddr, map);
980 pci_unmap_len_set(e, maplen, bufsize);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400981}
982
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700983/* Resume receiving using existing skb,
984 * Note: DMA address is not changed by chip.
985 * MTU not changed while receiver active.
986 */
Stephen Hemminger5a011442006-03-23 11:07:25 -0800987static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700988{
989 struct skge_rx_desc *rd = e->desc;
990
991 rd->csum2 = 0;
992 rd->csum2_start = ETH_HLEN;
993
994 wmb();
995
996 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
997}
998
999
1000/* Free all buffers in receive ring, assumes receiver stopped */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001001static void skge_rx_clean(struct skge_port *skge)
1002{
1003 struct skge_hw *hw = skge->hw;
1004 struct skge_ring *ring = &skge->rx_ring;
1005 struct skge_element *e;
1006
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001007 e = ring->start;
1008 do {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001009 struct skge_rx_desc *rd = e->desc;
1010 rd->control = 0;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001011 if (e->skb) {
1012 pci_unmap_single(hw->pdev,
1013 pci_unmap_addr(e, mapaddr),
1014 pci_unmap_len(e, maplen),
1015 PCI_DMA_FROMDEVICE);
1016 dev_kfree_skb(e->skb);
1017 e->skb = NULL;
1018 }
1019 } while ((e = e->next) != ring->start);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001020}
1021
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001022
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001023/* Allocate buffers for receive ring
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001024 * For receive: to_clean is next received frame.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001025 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07001026static int skge_rx_fill(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001027{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07001028 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001029 struct skge_ring *ring = &skge->rx_ring;
1030 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001031
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001032 e = ring->start;
1033 do {
Stephen Hemminger383181a2005-09-19 15:37:16 -07001034 struct sk_buff *skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001035
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07001036 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1037 GFP_KERNEL);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001038 if (!skb)
1039 return -ENOMEM;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001040
Stephen Hemminger383181a2005-09-19 15:37:16 -07001041 skb_reserve(skb, NET_IP_ALIGN);
1042 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001043 } while ( (e = e->next) != ring->start);
1044
1045 ring->to_clean = ring->start;
1046 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001047}
1048
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001049static const char *skge_pause(enum pause_status status)
1050{
1051 switch(status) {
1052 case FLOW_STAT_NONE:
1053 return "none";
1054 case FLOW_STAT_REM_SEND:
1055 return "rx only";
1056 case FLOW_STAT_LOC_SEND:
1057 return "tx_only";
1058 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1059 return "both";
1060 default:
1061 return "indeterminated";
1062 }
1063}
1064
1065
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001066static void skge_link_up(struct skge_port *skge)
1067{
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001068 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -07001069 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1070
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001071 netif_carrier_on(skge->netdev);
Stephen Hemminger29b4e882006-03-23 11:07:28 -08001072 netif_wake_queue(skge->netdev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001073
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001074 if (netif_msg_link(skge)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001075 printk(KERN_INFO PFX
1076 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1077 skge->netdev->name, skge->speed,
1078 skge->duplex == DUPLEX_FULL ? "full" : "half",
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001079 skge_pause(skge->flow_status));
1080 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001081}
1082
1083static void skge_link_down(struct skge_port *skge)
1084{
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -07001085 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001086 netif_carrier_off(skge->netdev);
1087 netif_stop_queue(skge->netdev);
1088
1089 if (netif_msg_link(skge))
1090 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1091}
1092
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001093
1094static void xm_link_down(struct skge_hw *hw, int port)
1095{
1096 struct net_device *dev = hw->dev[port];
1097 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001098
Stephen Hemminger501fb722007-10-16 12:15:51 -07001099 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001100
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001101 if (netif_carrier_ok(dev))
1102 skge_link_down(skge);
1103}
1104
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001105static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001106{
1107 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001108
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001109 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemminger07811912006-02-22 10:28:34 -08001110 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001111
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001112 if (hw->phy_type == SK_PHY_XMAC)
1113 goto ready;
1114
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001115 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001116 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001117 goto ready;
Stephen Hemminger07811912006-02-22 10:28:34 -08001118 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001119 }
1120
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001121 return -ETIMEDOUT;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001122 ready:
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001123 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001124
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001125 return 0;
1126}
1127
1128static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1129{
1130 u16 v = 0;
1131 if (__xm_phy_read(hw, port, reg, &v))
1132 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1133 hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001134 return v;
1135}
1136
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001137static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001138{
1139 int i;
1140
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001141 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001142 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001143 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001144 goto ready;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001145 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001146 }
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001147 return -EIO;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001148
1149 ready:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001150 xm_write16(hw, port, XM_PHY_DATA, val);
Stephen Hemminger07811912006-02-22 10:28:34 -08001151 for (i = 0; i < PHY_RETRIES; i++) {
1152 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1153 return 0;
1154 udelay(1);
1155 }
1156 return -ETIMEDOUT;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001157}
1158
1159static void genesis_init(struct skge_hw *hw)
1160{
1161 /* set blink source counter */
1162 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1163 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1164
1165 /* configure mac arbiter */
1166 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1167
1168 /* configure mac arbiter timeout values */
1169 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1170 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1171 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1172 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1173
1174 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1175 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1176 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1177 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1178
1179 /* configure packet arbiter timeout */
1180 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1181 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1182 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1183 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1184 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1185}
1186
1187static void genesis_reset(struct skge_hw *hw, int port)
1188{
Stephen Hemminger45bada62005-06-27 11:33:12 -07001189 const u8 zero[8] = { 0 };
Stephen Hemminger21d7f672007-11-26 11:54:51 -08001190 u32 reg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001191
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001192 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1193
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001194 /* reset the statistics module */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001195 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001196 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001197 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1198 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1199 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001200
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001201 /* disable Broadcom PHY IRQ */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001202 if (hw->phy_type == SK_PHY_BCOM)
1203 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001204
Stephen Hemminger45bada62005-06-27 11:33:12 -07001205 xm_outhash(hw, port, XM_HSM, zero);
Stephen Hemminger21d7f672007-11-26 11:54:51 -08001206
1207 /* Flush TX and RX fifo */
1208 reg = xm_read32(hw, port, XM_MODE);
1209 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1210 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001211}
1212
1213
Stephen Hemminger45bada62005-06-27 11:33:12 -07001214/* Convert mode to MII values */
1215static const u16 phy_pause_map[] = {
1216 [FLOW_MODE_NONE] = 0,
1217 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1218 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001219 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
Stephen Hemminger45bada62005-06-27 11:33:12 -07001220};
1221
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001222/* special defines for FIBER (88E1011S only) */
1223static const u16 fiber_pause_map[] = {
1224 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1225 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1226 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001227 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001228};
1229
Stephen Hemminger45bada62005-06-27 11:33:12 -07001230
1231/* Check status of Broadcom phy link */
1232static void bcom_check_link(struct skge_hw *hw, int port)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001233{
Stephen Hemminger45bada62005-06-27 11:33:12 -07001234 struct net_device *dev = hw->dev[port];
1235 struct skge_port *skge = netdev_priv(dev);
1236 u16 status;
1237
1238 /* read twice because of latch */
Stephen Hemminger501fb722007-10-16 12:15:51 -07001239 xm_phy_read(hw, port, PHY_BCOM_STAT);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001240 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1241
Stephen Hemminger45bada62005-06-27 11:33:12 -07001242 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001243 xm_link_down(hw, port);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001244 return;
1245 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07001246
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001247 if (skge->autoneg == AUTONEG_ENABLE) {
1248 u16 lpa, aux;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001249
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001250 if (!(status & PHY_ST_AN_OVER))
1251 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001252
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001253 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1254 if (lpa & PHY_B_AN_RF) {
1255 printk(KERN_NOTICE PFX "%s: remote fault\n",
1256 dev->name);
1257 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001258 }
1259
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001260 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1261
1262 /* Check Duplex mismatch */
1263 switch (aux & PHY_B_AS_AN_RES_MSK) {
1264 case PHY_B_RES_1000FD:
1265 skge->duplex = DUPLEX_FULL;
1266 break;
1267 case PHY_B_RES_1000HD:
1268 skge->duplex = DUPLEX_HALF;
1269 break;
1270 default:
1271 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1272 dev->name);
1273 return;
1274 }
1275
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001276 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1277 switch (aux & PHY_B_AS_PAUSE_MSK) {
1278 case PHY_B_AS_PAUSE_MSK:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001279 skge->flow_status = FLOW_STAT_SYMMETRIC;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001280 break;
1281 case PHY_B_AS_PRR:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001282 skge->flow_status = FLOW_STAT_REM_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001283 break;
1284 case PHY_B_AS_PRT:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001285 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001286 break;
1287 default:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001288 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001289 }
1290 skge->speed = SPEED_1000;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001291 }
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001292
1293 if (!netif_carrier_ok(dev))
1294 genesis_link_up(skge);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001295}
1296
1297/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1298 * Phy on for 100 or 10Mbit operation
1299 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001300static void bcom_phy_init(struct skge_port *skge)
Stephen Hemminger45bada62005-06-27 11:33:12 -07001301{
1302 struct skge_hw *hw = skge->hw;
1303 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001304 int i;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001305 u16 id1, r, ext, ctl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001306
1307 /* magic workaround patterns for Broadcom */
1308 static const struct {
1309 u16 reg;
1310 u16 val;
1311 } A1hack[] = {
1312 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1313 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1314 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1315 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1316 }, C0hack[] = {
1317 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1318 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1319 };
1320
Stephen Hemminger45bada62005-06-27 11:33:12 -07001321 /* read Id from external PHY (all have the same address) */
1322 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1323
1324 /* Optimize MDIO transfer by suppressing preamble. */
1325 r = xm_read16(hw, port, XM_MMU_CMD);
1326 r |= XM_MMU_NO_PRE;
1327 xm_write16(hw, port, XM_MMU_CMD,r);
1328
Stephen Hemminger2c668512005-07-22 16:26:07 -07001329 switch (id1) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001330 case PHY_BCOM_ID1_C0:
1331 /*
1332 * Workaround BCOM Errata for the C0 type.
1333 * Write magic patterns to reserved registers.
1334 */
1335 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1336 xm_phy_write(hw, port,
1337 C0hack[i].reg, C0hack[i].val);
1338
1339 break;
1340 case PHY_BCOM_ID1_A1:
1341 /*
1342 * Workaround BCOM Errata for the A1 type.
1343 * Write magic patterns to reserved registers.
1344 */
1345 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1346 xm_phy_write(hw, port,
1347 A1hack[i].reg, A1hack[i].val);
1348 break;
1349 }
1350
1351 /*
1352 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1353 * Disable Power Management after reset.
1354 */
1355 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1356 r |= PHY_B_AC_DIS_PM;
1357 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1358
1359 /* Dummy read */
1360 xm_read16(hw, port, XM_ISRC);
1361
1362 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1363 ctl = PHY_CT_SP1000; /* always 1000mbit */
1364
1365 if (skge->autoneg == AUTONEG_ENABLE) {
1366 /*
1367 * Workaround BCOM Errata #1 for the C5 type.
1368 * 1000Base-T Link Acquisition Failure in Slave Mode
1369 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1370 */
1371 u16 adv = PHY_B_1000C_RD;
1372 if (skge->advertising & ADVERTISED_1000baseT_Half)
1373 adv |= PHY_B_1000C_AHD;
1374 if (skge->advertising & ADVERTISED_1000baseT_Full)
1375 adv |= PHY_B_1000C_AFD;
1376 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1377
1378 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1379 } else {
1380 if (skge->duplex == DUPLEX_FULL)
1381 ctl |= PHY_CT_DUP_MD;
1382 /* Force to slave */
1383 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1384 }
1385
1386 /* Set autonegotiation pause parameters */
1387 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1388 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1389
1390 /* Handle Jumbo frames */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001391 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001392 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1393 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1394
1395 ext |= PHY_B_PEC_HIGH_LA;
1396
1397 }
1398
1399 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1400 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1401
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001402 /* Use link status change interrupt */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001403 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001404}
Stephen Hemminger45bada62005-06-27 11:33:12 -07001405
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001406static void xm_phy_init(struct skge_port *skge)
1407{
1408 struct skge_hw *hw = skge->hw;
1409 int port = skge->port;
1410 u16 ctrl = 0;
1411
1412 if (skge->autoneg == AUTONEG_ENABLE) {
1413 if (skge->advertising & ADVERTISED_1000baseT_Half)
1414 ctrl |= PHY_X_AN_HD;
1415 if (skge->advertising & ADVERTISED_1000baseT_Full)
1416 ctrl |= PHY_X_AN_FD;
1417
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001418 ctrl |= fiber_pause_map[skge->flow_control];
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001419
1420 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1421
1422 /* Restart Auto-negotiation */
1423 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1424 } else {
1425 /* Set DuplexMode in Config register */
1426 if (skge->duplex == DUPLEX_FULL)
1427 ctrl |= PHY_CT_DUP_MD;
1428 /*
1429 * Do NOT enable Auto-negotiation here. This would hold
1430 * the link down because no IDLEs are transmitted
1431 */
1432 }
1433
1434 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1435
1436 /* Poll PHY for status changes */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07001437 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001438}
1439
Stephen Hemminger501fb722007-10-16 12:15:51 -07001440static int xm_check_link(struct net_device *dev)
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001441{
1442 struct skge_port *skge = netdev_priv(dev);
1443 struct skge_hw *hw = skge->hw;
1444 int port = skge->port;
1445 u16 status;
1446
1447 /* read twice because of latch */
Stephen Hemminger501fb722007-10-16 12:15:51 -07001448 xm_phy_read(hw, port, PHY_XMAC_STAT);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001449 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1450
1451 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001452 xm_link_down(hw, port);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001453 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001454 }
1455
1456 if (skge->autoneg == AUTONEG_ENABLE) {
1457 u16 lpa, res;
1458
1459 if (!(status & PHY_ST_AN_OVER))
Stephen Hemminger501fb722007-10-16 12:15:51 -07001460 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001461
1462 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1463 if (lpa & PHY_B_AN_RF) {
1464 printk(KERN_NOTICE PFX "%s: remote fault\n",
1465 dev->name);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001466 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001467 }
1468
1469 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1470
1471 /* Check Duplex mismatch */
1472 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1473 case PHY_X_RS_FD:
1474 skge->duplex = DUPLEX_FULL;
1475 break;
1476 case PHY_X_RS_HD:
1477 skge->duplex = DUPLEX_HALF;
1478 break;
1479 default:
1480 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1481 dev->name);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001482 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001483 }
1484
1485 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001486 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1487 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1488 (lpa & PHY_X_P_SYM_MD))
1489 skge->flow_status = FLOW_STAT_SYMMETRIC;
1490 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1491 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1492 /* Enable PAUSE receive, disable PAUSE transmit */
1493 skge->flow_status = FLOW_STAT_REM_SEND;
1494 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1495 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1496 /* Disable PAUSE receive, enable PAUSE transmit */
1497 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001498 else
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001499 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001500
1501 skge->speed = SPEED_1000;
1502 }
1503
1504 if (!netif_carrier_ok(dev))
1505 genesis_link_up(skge);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001506 return 1;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001507}
1508
1509/* Poll to check for link coming up.
Stephen Hemminger501fb722007-10-16 12:15:51 -07001510 *
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001511 * Since internal PHY is wired to a level triggered pin, can't
Stephen Hemminger501fb722007-10-16 12:15:51 -07001512 * get an interrupt when carrier is detected, need to poll for
1513 * link coming up.
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001514 */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07001515static void xm_link_timer(unsigned long arg)
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001516{
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07001517 struct skge_port *skge = (struct skge_port *) arg;
David Howellsc4028952006-11-22 14:57:56 +00001518 struct net_device *dev = skge->netdev;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001519 struct skge_hw *hw = skge->hw;
1520 int port = skge->port;
Stephen Hemminger501fb722007-10-16 12:15:51 -07001521 int i;
1522 unsigned long flags;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001523
1524 if (!netif_running(dev))
1525 return;
1526
Stephen Hemminger501fb722007-10-16 12:15:51 -07001527 spin_lock_irqsave(&hw->phy_lock, flags);
1528
1529 /*
1530 * Verify that the link by checking GPIO register three times.
1531 * This pin has the signal from the link_sync pin connected to it.
1532 */
1533 for (i = 0; i < 3; i++) {
1534 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1535 goto link_down;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001536 }
1537
Stephen Hemminger501fb722007-10-16 12:15:51 -07001538 /* Re-enable interrupt to detect link down */
1539 if (xm_check_link(dev)) {
1540 u16 msk = xm_read16(hw, port, XM_IMSK);
1541 msk &= ~XM_IS_INP_ASS;
1542 xm_write16(hw, port, XM_IMSK, msk);
1543 xm_read16(hw, port, XM_ISRC);
1544 } else {
1545link_down:
1546 mod_timer(&skge->link_timer,
1547 round_jiffies(jiffies + LINK_HZ));
1548 }
1549 spin_unlock_irqrestore(&hw->phy_lock, flags);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001550}
1551
1552static void genesis_mac_init(struct skge_hw *hw, int port)
1553{
1554 struct net_device *dev = hw->dev[port];
1555 struct skge_port *skge = netdev_priv(dev);
1556 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1557 int i;
1558 u32 r;
1559 const u8 zero[6] = { 0 };
1560
Stephen Hemminger07811912006-02-22 10:28:34 -08001561 for (i = 0; i < 10; i++) {
1562 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1563 MFF_SET_MAC_RST);
1564 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1565 goto reset_ok;
1566 udelay(1);
1567 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001568
Stephen Hemminger07811912006-02-22 10:28:34 -08001569 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1570
1571 reset_ok:
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001572 /* Unreset the XMAC. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001573 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001574
1575 /*
1576 * Perform additional initialization for external PHYs,
1577 * namely for the 1000baseTX cards that use the XMAC's
1578 * GMII mode.
1579 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001580 if (hw->phy_type != SK_PHY_XMAC) {
1581 /* Take external Phy out of reset */
1582 r = skge_read32(hw, B2_GP_IO);
1583 if (port == 0)
1584 r |= GP_DIR_0|GP_IO_0;
1585 else
1586 r |= GP_DIR_2|GP_IO_2;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001587
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001588 skge_write32(hw, B2_GP_IO, r);
1589
1590 /* Enable GMII interface */
1591 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1592 }
Stephen Hemminger07811912006-02-22 10:28:34 -08001593
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001594
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001595 switch(hw->phy_type) {
1596 case SK_PHY_XMAC:
1597 xm_phy_init(skge);
1598 break;
1599 case SK_PHY_BCOM:
1600 bcom_phy_init(skge);
1601 bcom_check_link(hw, port);
1602 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001603
Stephen Hemminger45bada62005-06-27 11:33:12 -07001604 /* Set Station Address */
1605 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001606
Stephen Hemminger45bada62005-06-27 11:33:12 -07001607 /* We don't use match addresses so clear */
1608 for (i = 1; i < 16; i++)
1609 xm_outaddr(hw, port, XM_EXM(i), zero);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001610
Stephen Hemminger07811912006-02-22 10:28:34 -08001611 /* Clear MIB counters */
1612 xm_write16(hw, port, XM_STAT_CMD,
1613 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1614 /* Clear two times according to Errata #3 */
1615 xm_write16(hw, port, XM_STAT_CMD,
1616 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1617
Stephen Hemminger45bada62005-06-27 11:33:12 -07001618 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1619 xm_write16(hw, port, XM_RX_HI_WM, 1450);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001620
1621 /* We don't need the FCS appended to the packet. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001622 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1623 if (jumbo)
1624 r |= XM_RX_BIG_PK_OK;
1625
1626 if (skge->duplex == DUPLEX_HALF) {
1627 /*
1628 * If in manual half duplex mode the other side might be in
1629 * full duplex mode, so ignore if a carrier extension is not seen
1630 * on frames received
1631 */
1632 r |= XM_RX_DIS_CEXT;
1633 }
1634 xm_write16(hw, port, XM_RX_CMD, r);
1635
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001636 /* We want short frames padded to 60 bytes. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001637 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1638
Stephen Hemminger485982a2007-11-26 11:54:52 -08001639 /* Increase threshold for jumbo frames on dual port */
1640 if (hw->ports > 1 && jumbo)
1641 xm_write16(hw, port, XM_TX_THR, 1020);
1642 else
1643 xm_write16(hw, port, XM_TX_THR, 512);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001644
1645 /*
1646 * Enable the reception of all error frames. This is is
1647 * a necessary evil due to the design of the XMAC. The
1648 * XMAC's receive FIFO is only 8K in size, however jumbo
1649 * frames can be up to 9000 bytes in length. When bad
1650 * frame filtering is enabled, the XMAC's RX FIFO operates
1651 * in 'store and forward' mode. For this to work, the
1652 * entire frame has to fit into the FIFO, but that means
1653 * that jumbo frames larger than 8192 bytes will be
1654 * truncated. Disabling all bad frame filtering causes
1655 * the RX FIFO to operate in streaming mode, in which
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001656 * case the XMAC will start transferring frames out of the
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001657 * RX FIFO as soon as the FIFO threshold is reached.
1658 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001659 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001660
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001661
1662 /*
Stephen Hemminger45bada62005-06-27 11:33:12 -07001663 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1664 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1665 * and 'Octets Rx OK Hi Cnt Ov'.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001666 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001667 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1668
1669 /*
1670 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1671 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1672 * and 'Octets Tx OK Hi Cnt Ov'.
1673 */
1674 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001675
1676 /* Configure MAC arbiter */
1677 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1678
1679 /* configure timeout values */
1680 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1681 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1682 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1683 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1684
1685 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1686 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1687 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1688 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1689
1690 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001691 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1692 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1693 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001694
1695 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001696 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1697 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1698 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001699
Stephen Hemminger45bada62005-06-27 11:33:12 -07001700 if (jumbo) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001701 /* Enable frame flushing if jumbo frames used */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001702 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001703 } else {
1704 /* enable timeout timers if normal frames */
1705 skge_write16(hw, B3_PA_CTRL,
Stephen Hemminger45bada62005-06-27 11:33:12 -07001706 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001707 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001708}
1709
1710static void genesis_stop(struct skge_port *skge)
1711{
1712 struct skge_hw *hw = skge->hw;
1713 int port = skge->port;
Stephen Hemminger799b21d2007-11-26 11:54:50 -08001714 unsigned retries = 1000;
Stephen Hemminger21d7f672007-11-26 11:54:51 -08001715 u16 cmd;
1716
1717 /* Disable Tx and Rx */
1718 cmd = xm_read16(hw, port, XM_MMU_CMD);
1719 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1720 xm_write16(hw, port, XM_MMU_CMD, cmd);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001721
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001722 genesis_reset(hw, port);
1723
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001724 /* Clear Tx packet arbiter timeout IRQ */
1725 skge_write16(hw, B3_PA_CTRL,
1726 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1727
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001728 /* Reset the MAC */
Stephen Hemminger799b21d2007-11-26 11:54:50 -08001729 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1730 do {
1731 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1732 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1733 break;
1734 } while (--retries > 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001735
1736 /* For external PHYs there must be special handling */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001737 if (hw->phy_type != SK_PHY_XMAC) {
Stephen Hemminger799b21d2007-11-26 11:54:50 -08001738 u32 reg = skge_read32(hw, B2_GP_IO);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001739 if (port == 0) {
1740 reg |= GP_DIR_0;
1741 reg &= ~GP_IO_0;
1742 } else {
1743 reg |= GP_DIR_2;
1744 reg &= ~GP_IO_2;
1745 }
1746 skge_write32(hw, B2_GP_IO, reg);
1747 skge_read32(hw, B2_GP_IO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001748 }
1749
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001750 xm_write16(hw, port, XM_MMU_CMD,
1751 xm_read16(hw, port, XM_MMU_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001752 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1753
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001754 xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001755}
1756
1757
1758static void genesis_get_stats(struct skge_port *skge, u64 *data)
1759{
1760 struct skge_hw *hw = skge->hw;
1761 int port = skge->port;
1762 int i;
1763 unsigned long timeout = jiffies + HZ;
1764
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001765 xm_write16(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001766 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1767
1768 /* wait for update to complete */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001769 while (xm_read16(hw, port, XM_STAT_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001770 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1771 if (time_after(jiffies, timeout))
1772 break;
1773 udelay(10);
1774 }
1775
1776 /* special case for 64 bit octet counter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001777 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1778 | xm_read32(hw, port, XM_TXO_OK_LO);
1779 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1780 | xm_read32(hw, port, XM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001781
1782 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001783 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001784}
1785
1786static void genesis_mac_intr(struct skge_hw *hw, int port)
1787{
Stephen Hemmingerda007722007-10-16 12:15:52 -07001788 struct net_device *dev = hw->dev[port];
1789 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001790 u16 status = xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001791
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001792 if (netif_msg_intr(skge))
1793 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
Stephen Hemmingerda007722007-10-16 12:15:52 -07001794 dev->name, status);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001795
Stephen Hemminger501fb722007-10-16 12:15:51 -07001796 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1797 xm_link_down(hw, port);
1798 mod_timer(&skge->link_timer, jiffies + 1);
1799 }
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001800
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001801 if (status & XM_IS_TXF_UR) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001802 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
Stephen Hemmingerda007722007-10-16 12:15:52 -07001803 ++dev->stats.tx_fifo_errors;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001804 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001805}
1806
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001807static void genesis_link_up(struct skge_port *skge)
1808{
1809 struct skge_hw *hw = skge->hw;
1810 int port = skge->port;
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001811 u16 cmd, msk;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001812 u32 mode;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001813
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001814 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001815
1816 /*
1817 * enabling pause frame reception is required for 1000BT
1818 * because the XMAC is not reset if the link is going down
1819 */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001820 if (skge->flow_status == FLOW_STAT_NONE ||
1821 skge->flow_status == FLOW_STAT_LOC_SEND)
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001822 /* Disable Pause Frame Reception */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001823 cmd |= XM_MMU_IGN_PF;
1824 else
1825 /* Enable Pause Frame Reception */
1826 cmd &= ~XM_MMU_IGN_PF;
1827
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001828 xm_write16(hw, port, XM_MMU_CMD, cmd);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001829
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001830 mode = xm_read32(hw, port, XM_MODE);
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001831 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1832 skge->flow_status == FLOW_STAT_LOC_SEND) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001833 /*
1834 * Configure Pause Frame Generation
1835 * Use internal and external Pause Frame Generation.
1836 * Sending pause frames is edge triggered.
1837 * Send a Pause frame with the maximum pause time if
1838 * internal oder external FIFO full condition occurs.
1839 * Send a zero pause time frame to re-start transmission.
1840 */
1841 /* XM_PAUSE_DA = '010000C28001' (default) */
1842 /* XM_MAC_PTIME = 0xffff (maximum) */
1843 /* remember this value is defined in big endian (!) */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001844 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001845
1846 mode |= XM_PAUSE_MODE;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001847 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001848 } else {
1849 /*
1850 * disable pause frame generation is required for 1000BT
1851 * because the XMAC is not reset if the link is going down
1852 */
1853 /* Disable Pause Mode in Mode Register */
1854 mode &= ~XM_PAUSE_MODE;
1855
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001856 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001857 }
1858
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001859 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001860
Stephen Hemmingerd08b9bd2007-11-26 11:54:49 -08001861 /* Turn on detection of Tx underrun */
Stephen Hemminger501fb722007-10-16 12:15:51 -07001862 msk = xm_read16(hw, port, XM_IMSK);
Stephen Hemmingerd08b9bd2007-11-26 11:54:49 -08001863 msk &= ~XM_IS_TXF_UR;
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001864 xm_write16(hw, port, XM_IMSK, msk);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001865
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001866 xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001867
1868 /* get MMU Command Reg. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001869 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001870 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001871 cmd |= XM_MMU_GMII_FD;
1872
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001873 /*
1874 * Workaround BCOM Errata (#10523) for all BCom Phys
1875 * Enable Power Management after link up
1876 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001877 if (hw->phy_type == SK_PHY_BCOM) {
1878 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1879 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1880 & ~PHY_B_AC_DIS_PM);
1881 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1882 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001883
1884 /* enable Rx/Tx */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001885 xm_write16(hw, port, XM_MMU_CMD,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001886 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1887 skge_link_up(skge);
1888}
1889
1890
Stephen Hemminger45bada62005-06-27 11:33:12 -07001891static inline void bcom_phy_intr(struct skge_port *skge)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001892{
1893 struct skge_hw *hw = skge->hw;
1894 int port = skge->port;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001895 u16 isrc;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001896
Stephen Hemminger45bada62005-06-27 11:33:12 -07001897 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001898 if (netif_msg_intr(skge))
1899 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1900 skge->netdev->name, isrc);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001901
1902 if (isrc & PHY_B_IS_PSE)
1903 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1904 hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001905
1906 /* Workaround BCom Errata:
1907 * enable and disable loopback mode if "NO HCD" occurs.
1908 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001909 if (isrc & PHY_B_IS_NO_HDCL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001910 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1911 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001912 ctrl | PHY_CT_LOOP);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001913 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001914 ctrl & ~PHY_CT_LOOP);
1915 }
1916
Stephen Hemminger45bada62005-06-27 11:33:12 -07001917 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1918 bcom_check_link(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001919
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001920}
1921
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001922static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1923{
1924 int i;
1925
1926 gma_write16(hw, port, GM_SMI_DATA, val);
1927 gma_write16(hw, port, GM_SMI_CTRL,
1928 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1929 for (i = 0; i < PHY_RETRIES; i++) {
1930 udelay(1);
1931
1932 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1933 return 0;
1934 }
1935
1936 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1937 hw->dev[port]->name);
1938 return -EIO;
1939}
1940
1941static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1942{
1943 int i;
1944
1945 gma_write16(hw, port, GM_SMI_CTRL,
1946 GM_SMI_CT_PHY_AD(hw->phy_addr)
1947 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1948
1949 for (i = 0; i < PHY_RETRIES; i++) {
1950 udelay(1);
1951 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1952 goto ready;
1953 }
1954
1955 return -ETIMEDOUT;
1956 ready:
1957 *val = gma_read16(hw, port, GM_SMI_DATA);
1958 return 0;
1959}
1960
1961static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1962{
1963 u16 v = 0;
1964 if (__gm_phy_read(hw, port, reg, &v))
1965 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1966 hw->dev[port]->name);
1967 return v;
1968}
1969
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001970/* Marvell Phy Initialization */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001971static void yukon_init(struct skge_hw *hw, int port)
1972{
1973 struct skge_port *skge = netdev_priv(hw->dev[port]);
1974 u16 ctrl, ct1000, adv;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001975
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001976 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001977 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001978
1979 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1980 PHY_M_EC_MAC_S_MSK);
1981 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1982
Stephen Hemmingerc506a502005-06-27 11:33:09 -07001983 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001984
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001985 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001986 }
1987
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001988 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001989 if (skge->autoneg == AUTONEG_DISABLE)
1990 ctrl &= ~PHY_CT_ANE;
1991
1992 ctrl |= PHY_CT_RESET;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001993 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001994
1995 ctrl = 0;
1996 ct1000 = 0;
Stephen Hemmingerb18f2092005-06-27 11:33:08 -07001997 adv = PHY_AN_CSMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001998
1999 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07002000 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002001 if (skge->advertising & ADVERTISED_1000baseT_Full)
2002 ct1000 |= PHY_M_1000C_AFD;
2003 if (skge->advertising & ADVERTISED_1000baseT_Half)
2004 ct1000 |= PHY_M_1000C_AHD;
2005 if (skge->advertising & ADVERTISED_100baseT_Full)
2006 adv |= PHY_M_AN_100_FD;
2007 if (skge->advertising & ADVERTISED_100baseT_Half)
2008 adv |= PHY_M_AN_100_HD;
2009 if (skge->advertising & ADVERTISED_10baseT_Full)
2010 adv |= PHY_M_AN_10_FD;
2011 if (skge->advertising & ADVERTISED_10baseT_Half)
2012 adv |= PHY_M_AN_10_HD;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002013
Stephen Hemminger4b67be92006-10-05 15:49:51 -07002014 /* Set Flow-control capabilities */
2015 adv |= phy_pause_map[skge->flow_control];
2016 } else {
2017 if (skge->advertising & ADVERTISED_1000baseT_Full)
2018 adv |= PHY_M_AN_1000X_AFD;
2019 if (skge->advertising & ADVERTISED_1000baseT_Half)
2020 adv |= PHY_M_AN_1000X_AHD;
2021
2022 adv |= fiber_pause_map[skge->flow_control];
2023 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07002024
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002025 /* Restart Auto-negotiation */
2026 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2027 } else {
2028 /* forced speed/duplex settings */
2029 ct1000 = PHY_M_1000C_MSE;
2030
2031 if (skge->duplex == DUPLEX_FULL)
2032 ctrl |= PHY_CT_DUP_MD;
2033
2034 switch (skge->speed) {
2035 case SPEED_1000:
2036 ctrl |= PHY_CT_SP1000;
2037 break;
2038 case SPEED_100:
2039 ctrl |= PHY_CT_SP100;
2040 break;
2041 }
2042
2043 ctrl |= PHY_CT_RESET;
2044 }
2045
Stephen Hemmingerc506a502005-06-27 11:33:09 -07002046 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002047
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002048 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2049 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002050
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002051 /* Enable phy interrupt on autonegotiation complete (or link up) */
2052 if (skge->autoneg == AUTONEG_ENABLE)
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002053 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002054 else
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002055 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002056}
2057
2058static void yukon_reset(struct skge_hw *hw, int port)
2059{
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002060 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2061 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2062 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2063 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2064 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002065
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002066 gma_write16(hw, port, GM_RX_CTRL,
2067 gma_read16(hw, port, GM_RX_CTRL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002068 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2069}
2070
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002071/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2072static int is_yukon_lite_a0(struct skge_hw *hw)
2073{
2074 u32 reg;
2075 int ret;
2076
2077 if (hw->chip_id != CHIP_ID_YUKON)
2078 return 0;
2079
2080 reg = skge_read32(hw, B2_FAR);
2081 skge_write8(hw, B2_FAR + 3, 0xff);
2082 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2083 skge_write32(hw, B2_FAR, reg);
2084 return ret;
2085}
2086
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002087static void yukon_mac_init(struct skge_hw *hw, int port)
2088{
2089 struct skge_port *skge = netdev_priv(hw->dev[port]);
2090 int i;
2091 u32 reg;
2092 const u8 *addr = hw->dev[port]->dev_addr;
2093
2094 /* WA code for COMA mode -- set PHY reset */
2095 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002096 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2097 reg = skge_read32(hw, B2_GP_IO);
2098 reg |= GP_DIR_9 | GP_IO_9;
2099 skge_write32(hw, B2_GP_IO, reg);
2100 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002101
2102 /* hard reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002103 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2104 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002105
2106 /* WA code for COMA mode -- clear PHY reset */
2107 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002108 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2109 reg = skge_read32(hw, B2_GP_IO);
2110 reg |= GP_DIR_9;
2111 reg &= ~GP_IO_9;
2112 skge_write32(hw, B2_GP_IO, reg);
2113 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002114
2115 /* Set hardware config mode */
2116 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2117 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07002118 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002119
2120 /* Clear GMC reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002121 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2122 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2123 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002124
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002125 if (skge->autoneg == AUTONEG_DISABLE) {
2126 reg = GM_GPCR_AU_ALL_DIS;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002127 gma_write16(hw, port, GM_GP_CTRL,
2128 gma_read16(hw, port, GM_GP_CTRL) | reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002129
2130 switch (skge->speed) {
2131 case SPEED_1000:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002132 reg &= ~GM_GPCR_SPEED_100;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002133 reg |= GM_GPCR_SPEED_1000;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002134 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002135 case SPEED_100:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002136 reg &= ~GM_GPCR_SPEED_1000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002137 reg |= GM_GPCR_SPEED_100;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002138 break;
2139 case SPEED_10:
2140 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2141 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002142 }
2143
2144 if (skge->duplex == DUPLEX_FULL)
2145 reg |= GM_GPCR_DUP_FULL;
2146 } else
2147 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002148
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002149 switch (skge->flow_control) {
2150 case FLOW_MODE_NONE:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002151 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002152 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2153 break;
2154 case FLOW_MODE_LOC_SEND:
2155 /* disable Rx flow-control */
2156 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002157 break;
2158 case FLOW_MODE_SYMMETRIC:
2159 case FLOW_MODE_SYM_OR_REM:
2160 /* enable Tx & Rx flow-control */
2161 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002162 }
2163
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002164 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002165 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002166
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002167 yukon_init(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002168
2169 /* MIB clear */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002170 reg = gma_read16(hw, port, GM_PHY_ADDR);
2171 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002172
2173 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002174 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2175 gma_write16(hw, port, GM_PHY_ADDR, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002176
2177 /* transmit control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002178 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002179
2180 /* receive control reg: unicast + multicast + no FCS */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002181 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002182 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2183
2184 /* transmit flow control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002185 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002186
2187 /* transmit parameter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002188 gma_write16(hw, port, GM_TX_PARAM,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002189 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2190 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2191 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2192
Stephen Hemminger44c7fcc2007-11-28 14:23:01 -08002193 /* configure the Serial Mode Register */
2194 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2195 | GM_SMOD_VLAN_ENA
2196 | IPG_DATA_VAL(IPG_DATA_DEF);
2197
2198 if (hw->dev[port]->mtu > ETH_DATA_LEN)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002199 reg |= GM_SMOD_JUMBO_ENA;
2200
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002201 gma_write16(hw, port, GM_SERIAL_MODE, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002202
2203 /* physical address: used for pause frames */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002204 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002205 /* virtual address for data */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002206 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002207
2208 /* enable interrupt mask for counter overflows */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002209 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2210 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2211 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002212
2213 /* Initialize Mac Fifo */
2214
2215 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002216 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002217 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002218
2219 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2220 if (is_yukon_lite_a0(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002221 reg &= ~GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002222
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002223 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2224 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
Stephen Hemmingerc5923082005-08-16 14:01:02 -07002225 /*
2226 * because Pause Packet Truncation in GMAC is not working
2227 * we have to increase the Flush Threshold to 64 bytes
2228 * in order to flush pause packets in Rx FIFO on Yukon-1
2229 */
2230 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002231
2232 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002233 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2234 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002235}
2236
Stephen Hemminger355ec572005-11-08 10:33:43 -08002237/* Go into power down mode */
2238static void yukon_suspend(struct skge_hw *hw, int port)
2239{
2240 u16 ctrl;
2241
2242 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2243 ctrl |= PHY_M_PC_POL_R_DIS;
2244 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2245
2246 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2247 ctrl |= PHY_CT_RESET;
2248 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2249
2250 /* switch IEEE compatible power down mode on */
2251 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2252 ctrl |= PHY_CT_PDOWN;
2253 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2254}
2255
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002256static void yukon_stop(struct skge_port *skge)
2257{
2258 struct skge_hw *hw = skge->hw;
2259 int port = skge->port;
2260
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002261 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2262 yukon_reset(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002263
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002264 gma_write16(hw, port, GM_GP_CTRL,
2265 gma_read16(hw, port, GM_GP_CTRL)
Stephen Hemminger0eedf4a2005-07-22 16:26:04 -07002266 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002267 gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002268
Stephen Hemminger355ec572005-11-08 10:33:43 -08002269 yukon_suspend(hw, port);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002270
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002271 /* set GPHY Control reset */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002272 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2273 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002274}
2275
2276static void yukon_get_stats(struct skge_port *skge, u64 *data)
2277{
2278 struct skge_hw *hw = skge->hw;
2279 int port = skge->port;
2280 int i;
2281
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002282 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2283 | gma_read32(hw, port, GM_TXO_OK_LO);
2284 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2285 | gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002286
2287 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002288 data[i] = gma_read32(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002289 skge_stats[i].gma_offset);
2290}
2291
2292static void yukon_mac_intr(struct skge_hw *hw, int port)
2293{
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002294 struct net_device *dev = hw->dev[port];
2295 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002296 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002297
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002298 if (netif_msg_intr(skge))
2299 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2300 dev->name, status);
2301
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002302 if (status & GM_IS_RX_FF_OR) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07002303 ++dev->stats.rx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002304 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002305 }
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002306
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002307 if (status & GM_IS_TX_FF_UR) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07002308 ++dev->stats.tx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002309 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002310 }
2311
2312}
2313
2314static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2315{
Stephen Hemminger95566062005-06-27 11:33:02 -07002316 switch (aux & PHY_M_PS_SPEED_MSK) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002317 case PHY_M_PS_SPEED_1000:
2318 return SPEED_1000;
2319 case PHY_M_PS_SPEED_100:
2320 return SPEED_100;
2321 default:
2322 return SPEED_10;
2323 }
2324}
2325
2326static void yukon_link_up(struct skge_port *skge)
2327{
2328 struct skge_hw *hw = skge->hw;
2329 int port = skge->port;
2330 u16 reg;
2331
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002332 /* Enable Transmit FIFO Underrun */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002333 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002334
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002335 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002336 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2337 reg |= GM_GPCR_DUP_FULL;
2338
2339 /* enable Rx/Tx */
2340 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002341 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002342
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002343 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002344 skge_link_up(skge);
2345}
2346
2347static void yukon_link_down(struct skge_port *skge)
2348{
2349 struct skge_hw *hw = skge->hw;
2350 int port = skge->port;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002351 u16 ctrl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002352
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002353 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2354 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2355 gma_write16(hw, port, GM_GP_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002356
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002357 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2358 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2359 ctrl |= PHY_M_AN_ASP;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002360 /* restore Asymmetric Pause bit */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002361 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002362 }
2363
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002364 skge_link_down(skge);
2365
2366 yukon_init(hw, port);
2367}
2368
2369static void yukon_phy_intr(struct skge_port *skge)
2370{
2371 struct skge_hw *hw = skge->hw;
2372 int port = skge->port;
2373 const char *reason = NULL;
2374 u16 istatus, phystat;
2375
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002376 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2377 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002378
2379 if (netif_msg_intr(skge))
2380 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2381 skge->netdev->name, istatus, phystat);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002382
2383 if (istatus & PHY_M_IS_AN_COMPL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002384 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002385 & PHY_M_AN_RF) {
2386 reason = "remote fault";
2387 goto failed;
2388 }
2389
Stephen Hemmingerc506a502005-06-27 11:33:09 -07002390 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002391 reason = "master/slave fault";
2392 goto failed;
2393 }
2394
2395 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2396 reason = "speed/duplex";
2397 goto failed;
2398 }
2399
2400 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2401 ? DUPLEX_FULL : DUPLEX_HALF;
2402 skge->speed = yukon_speed(hw, phystat);
2403
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002404 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2405 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2406 case PHY_M_PS_PAUSE_MSK:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002407 skge->flow_status = FLOW_STAT_SYMMETRIC;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002408 break;
2409 case PHY_M_PS_RX_P_EN:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002410 skge->flow_status = FLOW_STAT_REM_SEND;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002411 break;
2412 case PHY_M_PS_TX_P_EN:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002413 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002414 break;
2415 default:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002416 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002417 }
2418
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002419 if (skge->flow_status == FLOW_STAT_NONE ||
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002420 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002421 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002422 else
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002423 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002424 yukon_link_up(skge);
2425 return;
2426 }
2427
2428 if (istatus & PHY_M_IS_LSP_CHANGE)
2429 skge->speed = yukon_speed(hw, phystat);
2430
2431 if (istatus & PHY_M_IS_DUP_CHANGE)
2432 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2433 if (istatus & PHY_M_IS_LST_CHANGE) {
2434 if (phystat & PHY_M_PS_LINK_UP)
2435 yukon_link_up(skge);
2436 else
2437 yukon_link_down(skge);
2438 }
2439 return;
2440 failed:
2441 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2442 skge->netdev->name, reason);
2443
2444 /* XXX restart autonegotiation? */
2445}
2446
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002447static void skge_phy_reset(struct skge_port *skge)
2448{
2449 struct skge_hw *hw = skge->hw;
2450 int port = skge->port;
Jeff Garzikaae343d2006-12-02 07:14:39 -05002451 struct net_device *dev = hw->dev[port];
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002452
2453 netif_stop_queue(skge->netdev);
2454 netif_carrier_off(skge->netdev);
2455
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002456 spin_lock_bh(&hw->phy_lock);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002457 if (hw->chip_id == CHIP_ID_GENESIS) {
2458 genesis_reset(hw, port);
2459 genesis_mac_init(hw, port);
2460 } else {
2461 yukon_reset(hw, port);
2462 yukon_init(hw, port);
2463 }
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002464 spin_unlock_bh(&hw->phy_lock);
Stephen Hemminger75814092006-12-01 11:41:08 -08002465
2466 dev->set_multicast_list(dev);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002467}
2468
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002469/* Basic MII support */
2470static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2471{
2472 struct mii_ioctl_data *data = if_mii(ifr);
2473 struct skge_port *skge = netdev_priv(dev);
2474 struct skge_hw *hw = skge->hw;
2475 int err = -EOPNOTSUPP;
2476
2477 if (!netif_running(dev))
2478 return -ENODEV; /* Phy still in reset */
2479
2480 switch(cmd) {
2481 case SIOCGMIIPHY:
2482 data->phy_id = hw->phy_addr;
2483
2484 /* fallthru */
2485 case SIOCGMIIREG: {
2486 u16 val = 0;
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002487 spin_lock_bh(&hw->phy_lock);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002488 if (hw->chip_id == CHIP_ID_GENESIS)
2489 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2490 else
2491 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002492 spin_unlock_bh(&hw->phy_lock);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002493 data->val_out = val;
2494 break;
2495 }
2496
2497 case SIOCSMIIREG:
2498 if (!capable(CAP_NET_ADMIN))
2499 return -EPERM;
2500
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002501 spin_lock_bh(&hw->phy_lock);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002502 if (hw->chip_id == CHIP_ID_GENESIS)
2503 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2504 data->val_in);
2505 else
2506 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2507 data->val_in);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002508 spin_unlock_bh(&hw->phy_lock);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002509 break;
2510 }
2511 return err;
2512}
2513
Linus Torvalds279e1da2007-11-15 08:44:36 -08002514static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002515{
2516 u32 end;
2517
Linus Torvalds279e1da2007-11-15 08:44:36 -08002518 start /= 8;
2519 len /= 8;
2520 end = start + len - 1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002521
2522 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2523 skge_write32(hw, RB_ADDR(q, RB_START), start);
2524 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2525 skge_write32(hw, RB_ADDR(q, RB_RP), start);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002526 skge_write32(hw, RB_ADDR(q, RB_END), end);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002527
2528 if (q == Q_R1 || q == Q_R2) {
2529 /* Set thresholds on receive queue's */
Linus Torvalds279e1da2007-11-15 08:44:36 -08002530 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2531 start + (2*len)/3);
2532 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2533 start + (len/3));
2534 } else {
2535 /* Enable store & forward on Tx queue's because
2536 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2537 */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002538 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002539 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002540
2541 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2542}
2543
2544/* Setup Bus Memory Interface */
2545static void skge_qset(struct skge_port *skge, u16 q,
2546 const struct skge_element *e)
2547{
2548 struct skge_hw *hw = skge->hw;
2549 u32 watermark = 0x600;
2550 u64 base = skge->dma + (e->desc - skge->mem);
2551
2552 /* optimization to reduce window on 32bit/33mhz */
2553 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2554 watermark /= 2;
2555
2556 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2557 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2558 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2559 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2560}
2561
2562static int skge_up(struct net_device *dev)
2563{
2564 struct skge_port *skge = netdev_priv(dev);
2565 struct skge_hw *hw = skge->hw;
2566 int port = skge->port;
Linus Torvalds279e1da2007-11-15 08:44:36 -08002567 u32 chunk, ram_addr;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002568 size_t rx_size, tx_size;
2569 int err;
2570
Stephen Hemmingerfae87592007-02-02 08:22:51 -08002571 if (!is_valid_ether_addr(dev->dev_addr))
2572 return -EINVAL;
2573
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002574 if (netif_msg_ifup(skge))
2575 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2576
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002577 if (dev->mtu > RX_BUF_SIZE)
Stephen Hemminger901ccef2006-03-23 11:07:23 -08002578 skge->rx_buf_size = dev->mtu + ETH_HLEN;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002579 else
2580 skge->rx_buf_size = RX_BUF_SIZE;
2581
2582
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002583 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2584 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2585 skge->mem_size = tx_size + rx_size;
2586 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2587 if (!skge->mem)
2588 return -ENOMEM;
2589
Stephen Hemmingerc3da1442006-03-21 10:57:01 -08002590 BUG_ON(skge->dma & 7);
2591
2592 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08002593 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
Stephen Hemmingerc3da1442006-03-21 10:57:01 -08002594 err = -EINVAL;
2595 goto free_pci_mem;
2596 }
2597
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002598 memset(skge->mem, 0, skge->mem_size);
2599
Stephen Hemminger203babb2006-03-21 10:57:05 -08002600 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2601 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002602 goto free_pci_mem;
2603
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002604 err = skge_rx_fill(dev);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002605 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002606 goto free_rx_ring;
2607
Stephen Hemminger203babb2006-03-21 10:57:05 -08002608 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2609 skge->dma + rx_size);
2610 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002611 goto free_rx_ring;
2612
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002613 /* Initialize MAC */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002614 spin_lock_bh(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002615 if (hw->chip_id == CHIP_ID_GENESIS)
2616 genesis_mac_init(hw, port);
2617 else
2618 yukon_mac_init(hw, port);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002619 spin_unlock_bh(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002620
Stephen Hemminger29816d92007-11-26 11:54:48 -08002621 /* Configure RAMbuffers - equally between ports and tx/rx */
2622 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002623 ram_addr = hw->ram_offset + 2 * chunk * port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002624
Linus Torvalds279e1da2007-11-15 08:44:36 -08002625 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002626 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002627
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002628 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002629 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002630 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2631
2632 /* Start receiver BMU */
2633 wmb();
2634 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002635 skge_led(skge, LED_MODE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002636
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07002637 spin_lock_irq(&hw->hw_lock);
2638 hw->intr_mask |= portmask[port];
2639 skge_write32(hw, B0_IMSK, hw->intr_mask);
2640 spin_unlock_irq(&hw->hw_lock);
2641
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002642 napi_enable(&skge->napi);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002643 return 0;
2644
2645 free_rx_ring:
2646 skge_rx_clean(skge);
2647 kfree(skge->rx_ring.start);
2648 free_pci_mem:
2649 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002650 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002651
2652 return err;
2653}
2654
Stephen Hemminger60b24b52007-10-16 12:15:50 -07002655/* stop receiver */
2656static void skge_rx_stop(struct skge_hw *hw, int port)
2657{
2658 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2659 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2660 RB_RST_SET|RB_DIS_OP_MD);
2661 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2662}
2663
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002664static int skge_down(struct net_device *dev)
2665{
2666 struct skge_port *skge = netdev_priv(dev);
2667 struct skge_hw *hw = skge->hw;
2668 int port = skge->port;
2669
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002670 if (skge->mem == NULL)
2671 return 0;
2672
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002673 if (netif_msg_ifdown(skge))
2674 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2675
2676 netif_stop_queue(dev);
Stephen Hemminger692412b2007-04-09 15:32:45 -07002677
Stephen Hemminger64f6b642006-09-23 21:25:28 -07002678 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002679 del_timer_sync(&skge->link_timer);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002680
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002681 napi_disable(&skge->napi);
Stephen Hemminger692412b2007-04-09 15:32:45 -07002682 netif_carrier_off(dev);
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07002683
2684 spin_lock_irq(&hw->hw_lock);
2685 hw->intr_mask &= ~portmask[port];
2686 skge_write32(hw, B0_IMSK, hw->intr_mask);
2687 spin_unlock_irq(&hw->hw_lock);
2688
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002689 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2690 if (hw->chip_id == CHIP_ID_GENESIS)
2691 genesis_stop(skge);
2692 else
2693 yukon_stop(skge);
2694
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002695 /* Stop transmitter */
2696 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2697 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2698 RB_RST_SET|RB_DIS_OP_MD);
2699
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002700
2701 /* Disable Force Sync bit and Enable Alloc bit */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002702 skge_write8(hw, SK_REG(port, TXA_CTRL),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002703 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2704
2705 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002706 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2707 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002708
2709 /* Reset PCI FIFO */
2710 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2711 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2712
2713 /* Reset the RAM Buffer async Tx queue */
2714 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
Stephen Hemminger60b24b52007-10-16 12:15:50 -07002715
2716 skge_rx_stop(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002717
2718 if (hw->chip_id == CHIP_ID_GENESIS) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002719 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2720 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002721 } else {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002722 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2723 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002724 }
2725
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002726 skge_led(skge, LED_MODE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002727
Stephen Hemmingere3a1b992007-03-16 14:01:26 -07002728 netif_tx_lock_bh(dev);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002729 skge_tx_clean(dev);
Stephen Hemmingere3a1b992007-03-16 14:01:26 -07002730 netif_tx_unlock_bh(dev);
2731
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002732 skge_rx_clean(skge);
2733
2734 kfree(skge->rx_ring.start);
2735 kfree(skge->tx_ring.start);
2736 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002737 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002738 return 0;
2739}
2740
Stephen Hemminger29b4e882006-03-23 11:07:28 -08002741static inline int skge_avail(const struct skge_ring *ring)
2742{
Stephen Hemminger992c9622007-03-16 14:01:30 -07002743 smp_mb();
Stephen Hemminger29b4e882006-03-23 11:07:28 -08002744 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2745 + (ring->to_clean - ring->to_use) - 1;
2746}
2747
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002748static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2749{
2750 struct skge_port *skge = netdev_priv(dev);
2751 struct skge_hw *hw = skge->hw;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002752 struct skge_element *e;
2753 struct skge_tx_desc *td;
2754 int i;
2755 u32 control, len;
2756 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002757
Herbert Xu5b057c62006-06-23 02:06:41 -07002758 if (skb_padto(skb, ETH_ZLEN))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002759 return NETDEV_TX_OK;
2760
Stephen Hemminger513f5332006-09-01 15:53:49 -07002761 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002762 return NETDEV_TX_BUSY;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002763
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002764 e = skge->tx_ring.to_use;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002765 td = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002766 BUG_ON(td->control & BMU_OWN);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002767 e->skb = skb;
2768 len = skb_headlen(skb);
2769 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2770 pci_unmap_addr_set(e, mapaddr, map);
2771 pci_unmap_len_set(e, maplen, len);
2772
2773 td->dma_lo = map;
2774 td->dma_hi = map >> 32;
2775
Patrick McHardy84fa7932006-08-29 16:44:56 -07002776 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Arnaldo Carvalho de Meloea2ae172007-04-25 17:55:53 -07002777 const int offset = skb_transport_offset(skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002778
2779 /* This seems backwards, but it is what the sk98lin
2780 * does. Looks like hardware is wrong?
2781 */
Arnaldo Carvalho de Melob0061ce2007-04-25 18:02:22 -07002782 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
Stephen Hemminger981d0372005-06-27 11:33:06 -07002783 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002784 control = BMU_TCP_CHECK;
2785 else
2786 control = BMU_UDP_CHECK;
2787
2788 td->csum_offs = 0;
2789 td->csum_start = offset;
Al Viroff1dcad2006-11-20 18:07:29 -08002790 td->csum_write = offset + skb->csum_offset;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002791 } else
2792 control = BMU_CHECK;
2793
2794 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2795 control |= BMU_EOF| BMU_IRQ_EOF;
2796 else {
2797 struct skge_tx_desc *tf = td;
2798
2799 control |= BMU_STFWD;
2800 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2801 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2802
2803 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2804 frag->size, PCI_DMA_TODEVICE);
2805
2806 e = e->next;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002807 e->skb = skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002808 tf = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002809 BUG_ON(tf->control & BMU_OWN);
2810
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002811 tf->dma_lo = map;
2812 tf->dma_hi = (u64) map >> 32;
2813 pci_unmap_addr_set(e, mapaddr, map);
2814 pci_unmap_len_set(e, maplen, frag->size);
2815
2816 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2817 }
2818 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2819 }
2820 /* Make sure all the descriptors written */
2821 wmb();
2822 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2823 wmb();
2824
2825 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2826
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002827 if (unlikely(netif_msg_tx_queued(skge)))
Al Viro0b2d7fe2005-04-03 09:15:52 +01002828 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002829 dev->name, e - skge->tx_ring.start, skb->len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002830
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002831 skge->tx_ring.to_use = e->next;
Stephen Hemminger992c9622007-03-16 14:01:30 -07002832 smp_wmb();
2833
Stephen Hemminger9db96472006-06-06 10:11:12 -07002834 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002835 pr_debug("%s: transmit queue full\n", dev->name);
2836 netif_stop_queue(dev);
2837 }
2838
Stephen Hemmingerc68ce712006-03-21 10:57:04 -08002839 dev->trans_start = jiffies;
2840
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002841 return NETDEV_TX_OK;
2842}
2843
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002844
2845/* Free resources associated with this reing element */
2846static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2847 u32 control)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002848{
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002849 struct pci_dev *pdev = skge->hw->pdev;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002850
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002851 /* skb header vs. fragment */
2852 if (control & BMU_STF)
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002853 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002854 pci_unmap_len(e, maplen),
2855 PCI_DMA_TODEVICE);
2856 else
2857 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2858 pci_unmap_len(e, maplen),
2859 PCI_DMA_TODEVICE);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002860
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002861 if (control & BMU_EOF) {
2862 if (unlikely(netif_msg_tx_done(skge)))
2863 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2864 skge->netdev->name, e - skge->tx_ring.start);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002865
Stephen Hemminger513f5332006-09-01 15:53:49 -07002866 dev_kfree_skb(e->skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002867 }
2868}
2869
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002870/* Free all buffers in transmit ring */
Stephen Hemminger513f5332006-09-01 15:53:49 -07002871static void skge_tx_clean(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002872{
Stephen Hemminger513f5332006-09-01 15:53:49 -07002873 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002874 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002875
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002876 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2877 struct skge_tx_desc *td = e->desc;
2878 skge_tx_free(skge, e, td->control);
2879 td->control = 0;
2880 }
2881
2882 skge->tx_ring.to_clean = e;
Stephen Hemminger513f5332006-09-01 15:53:49 -07002883 netif_wake_queue(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002884}
2885
2886static void skge_tx_timeout(struct net_device *dev)
2887{
2888 struct skge_port *skge = netdev_priv(dev);
2889
2890 if (netif_msg_timer(skge))
2891 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2892
2893 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002894 skge_tx_clean(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002895}
2896
2897static int skge_change_mtu(struct net_device *dev, int new_mtu)
2898{
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002899 int err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002900
Stephen Hemminger95566062005-06-27 11:33:02 -07002901 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002902 return -EINVAL;
2903
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002904 if (!netif_running(dev)) {
2905 dev->mtu = new_mtu;
2906 return 0;
2907 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002908
Stephen Hemminger1a8098b2007-11-28 14:25:05 -08002909 skge_down(dev);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002910
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002911 dev->mtu = new_mtu;
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002912
Stephen Hemminger1a8098b2007-11-28 14:25:05 -08002913 err = skge_up(dev);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002914 if (err)
2915 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002916
2917 return err;
2918}
2919
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002920static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2921
2922static void genesis_add_filter(u8 filter[8], const u8 *addr)
2923{
2924 u32 crc, bit;
2925
2926 crc = ether_crc_le(ETH_ALEN, addr);
2927 bit = ~crc & 0x3f;
2928 filter[bit/8] |= 1 << (bit%8);
2929}
2930
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002931static void genesis_set_multicast(struct net_device *dev)
2932{
2933 struct skge_port *skge = netdev_priv(dev);
2934 struct skge_hw *hw = skge->hw;
2935 int port = skge->port;
2936 int i, count = dev->mc_count;
2937 struct dev_mc_list *list = dev->mc_list;
2938 u32 mode;
2939 u8 filter[8];
2940
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002941 mode = xm_read32(hw, port, XM_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002942 mode |= XM_MD_ENA_HASH;
2943 if (dev->flags & IFF_PROMISC)
2944 mode |= XM_MD_ENA_PROM;
2945 else
2946 mode &= ~XM_MD_ENA_PROM;
2947
2948 if (dev->flags & IFF_ALLMULTI)
2949 memset(filter, 0xff, sizeof(filter));
2950 else {
2951 memset(filter, 0, sizeof(filter));
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002952
2953 if (skge->flow_status == FLOW_STAT_REM_SEND
2954 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2955 genesis_add_filter(filter, pause_mc_addr);
2956
2957 for (i = 0; list && i < count; i++, list = list->next)
2958 genesis_add_filter(filter, list->dmi_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002959 }
2960
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002961 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemminger45bada62005-06-27 11:33:12 -07002962 xm_outhash(hw, port, XM_HSM, filter);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002963}
2964
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002965static void yukon_add_filter(u8 filter[8], const u8 *addr)
2966{
2967 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2968 filter[bit/8] |= 1 << (bit%8);
2969}
2970
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002971static void yukon_set_multicast(struct net_device *dev)
2972{
2973 struct skge_port *skge = netdev_priv(dev);
2974 struct skge_hw *hw = skge->hw;
2975 int port = skge->port;
2976 struct dev_mc_list *list = dev->mc_list;
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002977 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2978 || skge->flow_status == FLOW_STAT_SYMMETRIC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002979 u16 reg;
2980 u8 filter[8];
2981
2982 memset(filter, 0, sizeof(filter));
2983
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002984 reg = gma_read16(hw, port, GM_RX_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002985 reg |= GM_RXCR_UCF_ENA;
2986
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002987 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002988 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2989 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2990 memset(filter, 0xff, sizeof(filter));
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002991 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002992 reg &= ~GM_RXCR_MCF_ENA;
2993 else {
2994 int i;
2995 reg |= GM_RXCR_MCF_ENA;
2996
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002997 if (rx_pause)
2998 yukon_add_filter(filter, pause_mc_addr);
2999
3000 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3001 yukon_add_filter(filter, list->dmi_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003002 }
3003
3004
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003005 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003006 (u16)filter[0] | ((u16)filter[1] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003007 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003008 (u16)filter[2] | ((u16)filter[3] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003009 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003010 (u16)filter[4] | ((u16)filter[5] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003011 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003012 (u16)filter[6] | ((u16)filter[7] << 8));
3013
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003014 gma_write16(hw, port, GM_RX_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003015}
3016
Stephen Hemminger383181a2005-09-19 15:37:16 -07003017static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3018{
3019 if (hw->chip_id == CHIP_ID_GENESIS)
3020 return status >> XMR_FS_LEN_SHIFT;
3021 else
3022 return status >> GMR_FS_LEN_SHIFT;
3023}
3024
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003025static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3026{
3027 if (hw->chip_id == CHIP_ID_GENESIS)
3028 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3029 else
3030 return (status & GMR_FS_ANY_ERR) ||
3031 (status & GMR_FS_RX_OK) == 0;
3032}
3033
Stephen Hemminger383181a2005-09-19 15:37:16 -07003034
3035/* Get receive buffer from descriptor.
3036 * Handles copy of small buffers and reallocation failures
3037 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003038static struct sk_buff *skge_rx_get(struct net_device *dev,
3039 struct skge_element *e,
3040 u32 control, u32 status, u16 csum)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003041{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003042 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003043 struct sk_buff *skb;
3044 u16 len = control & BMU_BBC;
3045
3046 if (unlikely(netif_msg_rx_status(skge)))
3047 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003048 dev->name, e - skge->rx_ring.start,
Stephen Hemminger383181a2005-09-19 15:37:16 -07003049 status, len);
3050
3051 if (len > skge->rx_buf_size)
3052 goto error;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003053
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003054 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
Stephen Hemminger383181a2005-09-19 15:37:16 -07003055 goto error;
3056
3057 if (bad_phy_status(skge->hw, status))
3058 goto error;
3059
3060 if (phy_length(skge->hw, status) != len)
3061 goto error;
3062
3063 if (len < RX_COPY_THRESHOLD) {
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003064 skb = netdev_alloc_skb(dev, len + 2);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003065 if (!skb)
3066 goto resubmit;
3067
3068 skb_reserve(skb, 2);
3069 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3070 pci_unmap_addr(e, mapaddr),
3071 len, PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03003072 skb_copy_from_linear_data(e->skb, skb->data, len);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003073 pci_dma_sync_single_for_device(skge->hw->pdev,
3074 pci_unmap_addr(e, mapaddr),
3075 len, PCI_DMA_FROMDEVICE);
3076 skge_rx_reuse(e, skge->rx_buf_size);
3077 } else {
3078 struct sk_buff *nskb;
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003079 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003080 if (!nskb)
3081 goto resubmit;
3082
Stephen Hemminger901ccef2006-03-23 11:07:23 -08003083 skb_reserve(nskb, NET_IP_ALIGN);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003084 pci_unmap_single(skge->hw->pdev,
3085 pci_unmap_addr(e, mapaddr),
3086 pci_unmap_len(e, maplen),
3087 PCI_DMA_FROMDEVICE);
3088 skb = e->skb;
3089 prefetch(skb->data);
3090 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3091 }
3092
3093 skb_put(skb, len);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003094 if (skge->rx_csum) {
3095 skb->csum = csum;
Patrick McHardy84fa7932006-08-29 16:44:56 -07003096 skb->ip_summed = CHECKSUM_COMPLETE;
Stephen Hemminger383181a2005-09-19 15:37:16 -07003097 }
3098
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003099 skb->protocol = eth_type_trans(skb, dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003100
3101 return skb;
3102error:
3103
3104 if (netif_msg_rx_err(skge))
3105 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003106 dev->name, e - skge->rx_ring.start,
Stephen Hemminger383181a2005-09-19 15:37:16 -07003107 control, status);
3108
3109 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003110 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
Stephen Hemmingerda007722007-10-16 12:15:52 -07003111 dev->stats.rx_length_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003112 if (status & XMR_FS_FRA_ERR)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003113 dev->stats.rx_frame_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003114 if (status & XMR_FS_FCS_ERR)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003115 dev->stats.rx_crc_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003116 } else {
3117 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
Stephen Hemmingerda007722007-10-16 12:15:52 -07003118 dev->stats.rx_length_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003119 if (status & GMR_FS_FRAGMENT)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003120 dev->stats.rx_frame_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003121 if (status & GMR_FS_CRC_ERR)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003122 dev->stats.rx_crc_errors++;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003123 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003124
Stephen Hemminger383181a2005-09-19 15:37:16 -07003125resubmit:
3126 skge_rx_reuse(e, skge->rx_buf_size);
3127 return NULL;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003128}
3129
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003130/* Free all buffers in Tx ring which are no longer owned by device */
Stephen Hemminger513f5332006-09-01 15:53:49 -07003131static void skge_tx_done(struct net_device *dev)
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003132{
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003133 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003134 struct skge_ring *ring = &skge->tx_ring;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003135 struct skge_element *e;
3136
Stephen Hemminger513f5332006-09-01 15:53:49 -07003137 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003138
Stephen Hemminger866b4f32006-03-23 11:07:27 -08003139 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
Stephen Hemminger992c9622007-03-16 14:01:30 -07003140 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003141
Stephen Hemminger992c9622007-03-16 14:01:30 -07003142 if (control & BMU_OWN)
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003143 break;
3144
Stephen Hemminger992c9622007-03-16 14:01:30 -07003145 skge_tx_free(skge, e, control);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003146 }
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003147 skge->tx_ring.to_clean = e;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08003148
Stephen Hemminger992c9622007-03-16 14:01:30 -07003149 /* Can run lockless until we need to synchronize to restart queue. */
3150 smp_mb();
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003151
Stephen Hemminger992c9622007-03-16 14:01:30 -07003152 if (unlikely(netif_queue_stopped(dev) &&
3153 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3154 netif_tx_lock(dev);
3155 if (unlikely(netif_queue_stopped(dev) &&
3156 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3157 netif_wake_queue(dev);
3158
3159 }
3160 netif_tx_unlock(dev);
3161 }
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003162}
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003163
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003164static int skge_poll(struct napi_struct *napi, int to_do)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003165{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003166 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3167 struct net_device *dev = skge->netdev;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003168 struct skge_hw *hw = skge->hw;
3169 struct skge_ring *ring = &skge->rx_ring;
3170 struct skge_element *e;
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003171 int work_done = 0;
3172
Stephen Hemminger513f5332006-09-01 15:53:49 -07003173 skge_tx_done(dev);
3174
3175 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3176
Stephen Hemminger1631aef2005-11-08 10:33:44 -08003177 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003178 struct skge_rx_desc *rd = e->desc;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003179 struct sk_buff *skb;
Stephen Hemminger383181a2005-09-19 15:37:16 -07003180 u32 control;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003181
3182 rmb();
3183 control = rd->control;
3184 if (control & BMU_OWN)
3185 break;
3186
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003187 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003188 if (likely(skb)) {
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003189 dev->last_rx = jiffies;
3190 netif_receive_skb(skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003191
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003192 ++work_done;
Stephen Hemminger5a011442006-03-23 11:07:25 -08003193 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003194 }
3195 ring->to_clean = e;
3196
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003197 /* restart receiver */
3198 wmb();
Stephen Hemmingera9cdab82006-02-22 10:28:33 -08003199 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003200
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003201 if (work_done < to_do) {
3202 spin_lock_irq(&hw->hw_lock);
3203 __netif_rx_complete(dev, napi);
3204 hw->intr_mask |= napimask[skge->port];
3205 skge_write32(hw, B0_IMSK, hw->intr_mask);
3206 skge_read32(hw, B0_IMSK);
3207 spin_unlock_irq(&hw->hw_lock);
3208 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003209
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003210 return work_done;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003211}
3212
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07003213/* Parity errors seem to happen when Genesis is connected to a switch
3214 * with no other ports present. Heartbeat error??
3215 */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003216static void skge_mac_parity(struct skge_hw *hw, int port)
3217{
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07003218 struct net_device *dev = hw->dev[port];
3219
Stephen Hemmingerda007722007-10-16 12:15:52 -07003220 ++dev->stats.tx_heartbeat_errors;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003221
3222 if (hw->chip_id == CHIP_ID_GENESIS)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003223 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003224 MFF_CLR_PERR);
3225 else
3226 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003227 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
Stephen Hemminger981d0372005-06-27 11:33:06 -07003228 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003229 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3230}
3231
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003232static void skge_mac_intr(struct skge_hw *hw, int port)
3233{
Stephen Hemminger95566062005-06-27 11:33:02 -07003234 if (hw->chip_id == CHIP_ID_GENESIS)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003235 genesis_mac_intr(hw, port);
3236 else
3237 yukon_mac_intr(hw, port);
3238}
3239
3240/* Handle device specific framing and timeout interrupts */
3241static void skge_error_irq(struct skge_hw *hw)
3242{
Stephen Hemminger1479d132007-02-02 08:22:52 -08003243 struct pci_dev *pdev = hw->pdev;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003244 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3245
3246 if (hw->chip_id == CHIP_ID_GENESIS) {
3247 /* clear xmac errors */
3248 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003249 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003250 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003251 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003252 } else {
3253 /* Timestamp (unused) overflow */
3254 if (hwstatus & IS_IRQ_TIST_OV)
3255 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003256 }
3257
3258 if (hwstatus & IS_RAM_RD_PAR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003259 dev_err(&pdev->dev, "Ram read data parity error\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003260 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3261 }
3262
3263 if (hwstatus & IS_RAM_WR_PAR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003264 dev_err(&pdev->dev, "Ram write data parity error\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003265 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3266 }
3267
3268 if (hwstatus & IS_M1_PAR_ERR)
3269 skge_mac_parity(hw, 0);
3270
3271 if (hwstatus & IS_M2_PAR_ERR)
3272 skge_mac_parity(hw, 1);
3273
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003274 if (hwstatus & IS_R1_PAR_ERR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003275 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3276 hw->dev[0]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003277 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003278 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003279
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003280 if (hwstatus & IS_R2_PAR_ERR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003281 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3282 hw->dev[1]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003283 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003284 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003285
3286 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003287 u16 pci_status, pci_cmd;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003288
Stephen Hemminger1479d132007-02-02 08:22:52 -08003289 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3290 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003291
Stephen Hemminger1479d132007-02-02 08:22:52 -08003292 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3293 pci_cmd, pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003294
3295 /* Write the error bits back to clear them. */
3296 pci_status &= PCI_STATUS_ERROR_BITS;
3297 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger1479d132007-02-02 08:22:52 -08003298 pci_write_config_word(pdev, PCI_COMMAND,
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003299 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
Stephen Hemminger1479d132007-02-02 08:22:52 -08003300 pci_write_config_word(pdev, PCI_STATUS, pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003301 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003302
Stephen Hemminger050ec182005-08-16 14:00:54 -07003303 /* if error still set then just ignore it */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003304 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3305 if (hwstatus & IS_IRQ_STAT) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003306 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003307 hw->intr_mask &= ~IS_HW_ERR;
3308 }
3309 }
3310}
3311
3312/*
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003313 * Interrupt from PHY are handled in tasklet (softirq)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003314 * because accessing phy registers requires spin wait which might
3315 * cause excess interrupt latency.
3316 */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003317static void skge_extirq(unsigned long arg)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003318{
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003319 struct skge_hw *hw = (struct skge_hw *) arg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003320 int port;
3321
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003322 for (port = 0; port < hw->ports; port++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003323 struct net_device *dev = hw->dev[port];
3324
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003325 if (netif_running(dev)) {
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003326 struct skge_port *skge = netdev_priv(dev);
3327
3328 spin_lock(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003329 if (hw->chip_id != CHIP_ID_GENESIS)
3330 yukon_phy_intr(skge);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003331 else if (hw->phy_type == SK_PHY_BCOM)
Stephen Hemminger45bada62005-06-27 11:33:12 -07003332 bcom_phy_intr(skge);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003333 spin_unlock(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003334 }
3335 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003336
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003337 spin_lock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003338 hw->intr_mask |= IS_EXT_REG;
3339 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003340 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003341 spin_unlock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003342}
3343
David Howells7d12e782006-10-05 14:55:46 +01003344static irqreturn_t skge_intr(int irq, void *dev_id)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003345{
3346 struct skge_hw *hw = dev_id;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003347 u32 status;
Stephen Hemminger29365c92006-09-01 15:53:48 -07003348 int handled = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003349
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003350 spin_lock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003351 /* Reading this register masks IRQ */
3352 status = skge_read32(hw, B0_SP_ISRC);
Stephen Hemminger0486a8c2006-09-06 11:06:10 -07003353 if (status == 0 || status == ~0)
Stephen Hemminger29365c92006-09-01 15:53:48 -07003354 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003355
Stephen Hemminger29365c92006-09-01 15:53:48 -07003356 handled = 1;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003357 status &= hw->intr_mask;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003358 if (status & IS_EXT_REG) {
3359 hw->intr_mask &= ~IS_EXT_REG;
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003360 tasklet_schedule(&hw->phy_task);
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003361 }
3362
Stephen Hemminger513f5332006-09-01 15:53:49 -07003363 if (status & (IS_XA1_F|IS_R1_F)) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003364 struct skge_port *skge = netdev_priv(hw->dev[0]);
Stephen Hemminger513f5332006-09-01 15:53:49 -07003365 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003366 netif_rx_schedule(hw->dev[0], &skge->napi);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003367 }
3368
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003369 if (status & IS_PA_TO_TX1)
3370 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3371
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003372 if (status & IS_PA_TO_RX1) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07003373 ++hw->dev[0]->stats.rx_over_errors;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003374 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3375 }
3376
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003377
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003378 if (status & IS_MAC1)
3379 skge_mac_intr(hw, 0);
Stephen Hemminger95566062005-06-27 11:33:02 -07003380
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003381 if (hw->dev[1]) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003382 struct skge_port *skge = netdev_priv(hw->dev[1]);
3383
Stephen Hemminger513f5332006-09-01 15:53:49 -07003384 if (status & (IS_XA2_F|IS_R2_F)) {
3385 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003386 netif_rx_schedule(hw->dev[1], &skge->napi);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003387 }
3388
3389 if (status & IS_PA_TO_RX2) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07003390 ++hw->dev[1]->stats.rx_over_errors;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003391 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3392 }
3393
3394 if (status & IS_PA_TO_TX2)
3395 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3396
3397 if (status & IS_MAC2)
3398 skge_mac_intr(hw, 1);
3399 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003400
3401 if (status & IS_HW_ERR)
3402 skge_error_irq(hw);
3403
Stephen Hemminger7e676d92005-06-27 11:33:13 -07003404 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003405 skge_read32(hw, B0_IMSK);
Stephen Hemminger29365c92006-09-01 15:53:48 -07003406out:
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003407 spin_unlock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003408
Stephen Hemminger29365c92006-09-01 15:53:48 -07003409 return IRQ_RETVAL(handled);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003410}
3411
3412#ifdef CONFIG_NET_POLL_CONTROLLER
3413static void skge_netpoll(struct net_device *dev)
3414{
3415 struct skge_port *skge = netdev_priv(dev);
3416
3417 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +01003418 skge_intr(dev->irq, skge->hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003419 enable_irq(dev->irq);
3420}
3421#endif
3422
3423static int skge_set_mac_address(struct net_device *dev, void *p)
3424{
3425 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003426 struct skge_hw *hw = skge->hw;
3427 unsigned port = skge->port;
3428 const struct sockaddr *addr = p;
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003429 u16 ctrl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003430
3431 if (!is_valid_ether_addr(addr->sa_data))
3432 return -EADDRNOTAVAIL;
3433
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003434 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003435
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003436 if (!netif_running(dev)) {
3437 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3438 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3439 } else {
3440 /* disable Rx */
3441 spin_lock_bh(&hw->phy_lock);
3442 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3443 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003444
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003445 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3446 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003447
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003448 if (hw->chip_id == CHIP_ID_GENESIS)
3449 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3450 else {
3451 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3452 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3453 }
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003454
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003455 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3456 spin_unlock_bh(&hw->phy_lock);
3457 }
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003458
3459 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003460}
3461
3462static const struct {
3463 u8 id;
3464 const char *name;
3465} skge_chips[] = {
3466 { CHIP_ID_GENESIS, "Genesis" },
3467 { CHIP_ID_YUKON, "Yukon" },
3468 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3469 { CHIP_ID_YUKON_LP, "Yukon-LP"},
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003470};
3471
3472static const char *skge_board_name(const struct skge_hw *hw)
3473{
3474 int i;
3475 static char buf[16];
3476
3477 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3478 if (skge_chips[i].id == hw->chip_id)
3479 return skge_chips[i].name;
3480
3481 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3482 return buf;
3483}
3484
3485
3486/*
3487 * Setup the board data structure, but don't bring up
3488 * the port(s)
3489 */
3490static int skge_reset(struct skge_hw *hw)
3491{
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003492 u32 reg;
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003493 u16 ctst, pci_status;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003494 u8 t8, mac_cfg, pmd_type;
Stephen Hemminger981d0372005-06-27 11:33:06 -07003495 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003496
3497 ctst = skge_read16(hw, B0_CTST);
3498
3499 /* do a SW reset */
3500 skge_write8(hw, B0_CTST, CS_RST_SET);
3501 skge_write8(hw, B0_CTST, CS_RST_CLR);
3502
3503 /* clear PCI errors, if any */
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003504 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3505 skge_write8(hw, B2_TST_CTRL2, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003506
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003507 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3508 pci_write_config_word(hw->pdev, PCI_STATUS,
3509 pci_status | PCI_STATUS_ERROR_BITS);
3510 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003511 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3512
3513 /* restore CLK_RUN bits (for Yukon-Lite) */
3514 skge_write16(hw, B0_CTST,
3515 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3516
3517 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003518 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003519 pmd_type = skge_read8(hw, B2_PMD_TYP);
3520 hw->copper = (pmd_type == 'T' || pmd_type == '1');
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003521
Stephen Hemminger95566062005-06-27 11:33:02 -07003522 switch (hw->chip_id) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003523 case CHIP_ID_GENESIS:
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003524 switch (hw->phy_type) {
3525 case SK_PHY_XMAC:
3526 hw->phy_addr = PHY_ADDR_XMAC;
3527 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003528 case SK_PHY_BCOM:
3529 hw->phy_addr = PHY_ADDR_BCOM;
3530 break;
3531 default:
Stephen Hemminger1479d132007-02-02 08:22:52 -08003532 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3533 hw->phy_type);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003534 return -EOPNOTSUPP;
3535 }
3536 break;
3537
3538 case CHIP_ID_YUKON:
3539 case CHIP_ID_YUKON_LITE:
3540 case CHIP_ID_YUKON_LP:
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003541 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003542 hw->copper = 1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003543
3544 hw->phy_addr = PHY_ADDR_MARV;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003545 break;
3546
3547 default:
Stephen Hemminger1479d132007-02-02 08:22:52 -08003548 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3549 hw->chip_id);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003550 return -EOPNOTSUPP;
3551 }
3552
Stephen Hemminger981d0372005-06-27 11:33:06 -07003553 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3554 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3555 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003556
3557 /* read the adapters RAM size */
3558 t8 = skge_read8(hw, B2_E_0);
3559 if (hw->chip_id == CHIP_ID_GENESIS) {
3560 if (t8 == 3) {
3561 /* special case: 4 x 64k x 36, offset = 0x80000 */
Linus Torvalds279e1da2007-11-15 08:44:36 -08003562 hw->ram_size = 0x100000;
3563 hw->ram_offset = 0x80000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003564 } else
3565 hw->ram_size = t8 * 512;
Linus Torvalds279e1da2007-11-15 08:44:36 -08003566 }
3567 else if (t8 == 0)
3568 hw->ram_size = 0x20000;
3569 else
3570 hw->ram_size = t8 * 4096;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003571
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07003572 hw->intr_mask = IS_HW_ERR;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003573
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07003574 /* Use PHY IRQ for all but fiber based Genesis board */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003575 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3576 hw->intr_mask |= IS_EXT_REG;
3577
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003578 if (hw->chip_id == CHIP_ID_GENESIS)
3579 genesis_init(hw);
3580 else {
3581 /* switch power to VCC (WA for VAUX problem) */
3582 skge_write8(hw, B0_POWER_CTRL,
3583 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003584
Stephen Hemminger050ec182005-08-16 14:00:54 -07003585 /* avoid boards with stuck Hardware error bits */
3586 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3587 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003588 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
Stephen Hemminger050ec182005-08-16 14:00:54 -07003589 hw->intr_mask &= ~IS_HW_ERR;
3590 }
3591
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003592 /* Clear PHY COMA */
3593 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3594 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3595 reg &= ~PCI_PHY_COMA;
3596 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3597 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3598
3599
Stephen Hemminger981d0372005-06-27 11:33:06 -07003600 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003601 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3602 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003603 }
3604 }
3605
3606 /* turn off hardware timer (unused) */
3607 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3608 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3609 skge_write8(hw, B0_LED, LED_STAT_ON);
3610
3611 /* enable the Tx Arbiters */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003612 for (i = 0; i < hw->ports; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003613 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003614
3615 /* Initialize ram interface */
3616 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3617
3618 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3619 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3620 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3621 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3622 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3623 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3624 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3625 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3626 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3627 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3628 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3629 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3630
3631 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3632
3633 /* Set interrupt moderation for Transmit only
3634 * Receive interrupts avoided by NAPI
3635 */
3636 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3637 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3638 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3639
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003640 skge_write32(hw, B0_IMSK, hw->intr_mask);
3641
Stephen Hemminger981d0372005-06-27 11:33:06 -07003642 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003643 if (hw->chip_id == CHIP_ID_GENESIS)
3644 genesis_reset(hw, i);
3645 else
3646 yukon_reset(hw, i);
3647 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003648
3649 return 0;
3650}
3651
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003652
3653#ifdef CONFIG_SKGE_DEBUG
3654
3655static struct dentry *skge_debug;
3656
3657static int skge_debug_show(struct seq_file *seq, void *v)
3658{
3659 struct net_device *dev = seq->private;
3660 const struct skge_port *skge = netdev_priv(dev);
3661 const struct skge_hw *hw = skge->hw;
3662 const struct skge_element *e;
3663
3664 if (!netif_running(dev))
3665 return -ENETDOWN;
3666
3667 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3668 skge_read32(hw, B0_IMSK));
3669
3670 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3671 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3672 const struct skge_tx_desc *t = e->desc;
3673 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3674 t->control, t->dma_hi, t->dma_lo, t->status,
3675 t->csum_offs, t->csum_write, t->csum_start);
3676 }
3677
3678 seq_printf(seq, "\nRx Ring: \n");
3679 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3680 const struct skge_rx_desc *r = e->desc;
3681
3682 if (r->control & BMU_OWN)
3683 break;
3684
3685 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3686 r->control, r->dma_hi, r->dma_lo, r->status,
3687 r->timestamp, r->csum1, r->csum1_start);
3688 }
3689
3690 return 0;
3691}
3692
3693static int skge_debug_open(struct inode *inode, struct file *file)
3694{
3695 return single_open(file, skge_debug_show, inode->i_private);
3696}
3697
3698static const struct file_operations skge_debug_fops = {
3699 .owner = THIS_MODULE,
3700 .open = skge_debug_open,
3701 .read = seq_read,
3702 .llseek = seq_lseek,
3703 .release = single_release,
3704};
3705
3706/*
3707 * Use network device events to create/remove/rename
3708 * debugfs file entries
3709 */
3710static int skge_device_event(struct notifier_block *unused,
3711 unsigned long event, void *ptr)
3712{
3713 struct net_device *dev = ptr;
3714 struct skge_port *skge;
3715 struct dentry *d;
3716
3717 if (dev->open != &skge_up || !skge_debug)
3718 goto done;
3719
3720 skge = netdev_priv(dev);
3721 switch(event) {
3722 case NETDEV_CHANGENAME:
3723 if (skge->debugfs) {
3724 d = debugfs_rename(skge_debug, skge->debugfs,
3725 skge_debug, dev->name);
3726 if (d)
3727 skge->debugfs = d;
3728 else {
3729 pr_info(PFX "%s: rename failed\n", dev->name);
3730 debugfs_remove(skge->debugfs);
3731 }
3732 }
3733 break;
3734
3735 case NETDEV_GOING_DOWN:
3736 if (skge->debugfs) {
3737 debugfs_remove(skge->debugfs);
3738 skge->debugfs = NULL;
3739 }
3740 break;
3741
3742 case NETDEV_UP:
3743 d = debugfs_create_file(dev->name, S_IRUGO,
3744 skge_debug, dev,
3745 &skge_debug_fops);
3746 if (!d || IS_ERR(d))
3747 pr_info(PFX "%s: debugfs create failed\n",
3748 dev->name);
3749 else
3750 skge->debugfs = d;
3751 break;
3752 }
3753
3754done:
3755 return NOTIFY_DONE;
3756}
3757
3758static struct notifier_block skge_notifier = {
3759 .notifier_call = skge_device_event,
3760};
3761
3762
3763static __init void skge_debug_init(void)
3764{
3765 struct dentry *ent;
3766
3767 ent = debugfs_create_dir("skge", NULL);
3768 if (!ent || IS_ERR(ent)) {
3769 pr_info(PFX "debugfs create directory failed\n");
3770 return;
3771 }
3772
3773 skge_debug = ent;
3774 register_netdevice_notifier(&skge_notifier);
3775}
3776
3777static __exit void skge_debug_cleanup(void)
3778{
3779 if (skge_debug) {
3780 unregister_netdevice_notifier(&skge_notifier);
3781 debugfs_remove(skge_debug);
3782 skge_debug = NULL;
3783 }
3784}
3785
3786#else
3787#define skge_debug_init()
3788#define skge_debug_cleanup()
3789#endif
3790
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003791/* Initialize network device */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003792static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3793 int highmem)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003794{
3795 struct skge_port *skge;
3796 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3797
3798 if (!dev) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003799 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003800 return NULL;
3801 }
3802
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003803 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3804 dev->open = skge_up;
3805 dev->stop = skge_down;
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08003806 dev->do_ioctl = skge_ioctl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003807 dev->hard_start_xmit = skge_xmit_frame;
3808 dev->get_stats = skge_get_stats;
3809 if (hw->chip_id == CHIP_ID_GENESIS)
3810 dev->set_multicast_list = genesis_set_multicast;
3811 else
3812 dev->set_multicast_list = yukon_set_multicast;
3813
3814 dev->set_mac_address = skge_set_mac_address;
3815 dev->change_mtu = skge_change_mtu;
3816 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3817 dev->tx_timeout = skge_tx_timeout;
3818 dev->watchdog_timeo = TX_WATCHDOG;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003819#ifdef CONFIG_NET_POLL_CONTROLLER
3820 dev->poll_controller = skge_netpoll;
3821#endif
3822 dev->irq = hw->pdev->irq;
Stephen Hemminger513f5332006-09-01 15:53:49 -07003823
Stephen Hemminger981d0372005-06-27 11:33:06 -07003824 if (highmem)
3825 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003826
3827 skge = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003828 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003829 skge->netdev = dev;
3830 skge->hw = hw;
3831 skge->msg_enable = netif_msg_init(debug, default_msg);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003832
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003833 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3834 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3835
3836 /* Auto speed and flow control */
3837 skge->autoneg = AUTONEG_ENABLE;
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07003838 skge->flow_control = FLOW_MODE_SYM_OR_REM;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003839 skge->duplex = -1;
3840 skge->speed = -1;
Stephen Hemminger31b619c2005-06-27 11:33:11 -07003841 skge->advertising = skge_supported_modes(hw);
Stephen Hemminger5b982c52007-05-08 13:36:20 -07003842
3843 if (pci_wake_enabled(hw->pdev))
3844 skge->wol = wol_supported(hw) & WAKE_MAGIC;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003845
3846 hw->dev[port] = dev;
3847
3848 skge->port = port;
3849
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003850 /* Only used for Genesis XMAC */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003851 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003852
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003853 if (hw->chip_id != CHIP_ID_GENESIS) {
3854 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3855 skge->rx_csum = 1;
3856 }
3857
3858 /* read the mac address */
3859 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
John W. Linville56230d52005-09-12 10:48:57 -04003860 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003861
3862 /* device is off until link detection */
3863 netif_carrier_off(dev);
3864 netif_stop_queue(dev);
3865
3866 return dev;
3867}
3868
3869static void __devinit skge_show_addr(struct net_device *dev)
3870{
3871 const struct skge_port *skge = netdev_priv(dev);
Joe Perches0795af52007-10-03 17:59:30 -07003872 DECLARE_MAC_BUF(mac);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003873
3874 if (netif_msg_probe(skge))
Joe Perches0795af52007-10-03 17:59:30 -07003875 printk(KERN_INFO PFX "%s: addr %s\n",
3876 dev->name, print_mac(mac, dev->dev_addr));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003877}
3878
3879static int __devinit skge_probe(struct pci_dev *pdev,
3880 const struct pci_device_id *ent)
3881{
3882 struct net_device *dev, *dev1;
3883 struct skge_hw *hw;
3884 int err, using_dac = 0;
3885
Stephen Hemminger203babb2006-03-21 10:57:05 -08003886 err = pci_enable_device(pdev);
3887 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003888 dev_err(&pdev->dev, "cannot enable PCI device\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003889 goto err_out;
3890 }
3891
Stephen Hemminger203babb2006-03-21 10:57:05 -08003892 err = pci_request_regions(pdev, DRV_NAME);
3893 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003894 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003895 goto err_out_disable_pdev;
3896 }
3897
3898 pci_set_master(pdev);
3899
Stephen Hemminger93aea712006-03-21 10:57:02 -08003900 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003901 using_dac = 1;
Stephen Hemminger77783a72006-01-05 16:26:05 -08003902 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
Stephen Hemminger93aea712006-03-21 10:57:02 -08003903 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3904 using_dac = 0;
3905 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3906 }
3907
3908 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003909 dev_err(&pdev->dev, "no usable DMA configuration\n");
Stephen Hemminger93aea712006-03-21 10:57:02 -08003910 goto err_out_free_regions;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003911 }
3912
3913#ifdef __BIG_ENDIAN
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08003914 /* byte swap descriptors in hardware */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003915 {
3916 u32 reg;
3917
3918 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3919 reg |= PCI_REV_DESC;
3920 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3921 }
3922#endif
3923
3924 err = -ENOMEM;
Stephen Hemminger7e863062005-11-08 10:33:41 -08003925 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003926 if (!hw) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003927 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003928 goto err_out_free_regions;
3929 }
3930
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003931 hw->pdev = pdev;
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003932 spin_lock_init(&hw->hw_lock);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003933 spin_lock_init(&hw->phy_lock);
3934 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003935
3936 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3937 if (!hw->regs) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003938 dev_err(&pdev->dev, "cannot map device registers\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003939 goto err_out_free_hw;
3940 }
3941
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003942 err = skge_reset(hw);
3943 if (err)
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003944 goto err_out_iounmap;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003945
Greg Kroah-Hartman7c7459d2006-06-12 15:13:08 -07003946 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3947 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
Stephen Hemminger981d0372005-06-27 11:33:06 -07003948 skge_board_name(hw), hw->chip_rev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003949
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003950 dev = skge_devinit(hw, 0, using_dac);
3951 if (!dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003952 goto err_out_led_off;
3953
Stephen Hemmingerfae87592007-02-02 08:22:51 -08003954 /* Some motherboards are broken and has zero in ROM. */
Stephen Hemminger1479d132007-02-02 08:22:52 -08003955 if (!is_valid_ether_addr(dev->dev_addr))
3956 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
Stephen Hemminger631ae322006-06-06 10:11:14 -07003957
Stephen Hemminger203babb2006-03-21 10:57:05 -08003958 err = register_netdev(dev);
3959 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003960 dev_err(&pdev->dev, "cannot register net device\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003961 goto err_out_free_netdev;
3962 }
3963
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003964 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3965 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003966 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003967 dev->name, pdev->irq);
3968 goto err_out_unregister;
3969 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003970 skge_show_addr(dev);
3971
Stephen Hemminger981d0372005-06-27 11:33:06 -07003972 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003973 if (register_netdev(dev1) == 0)
3974 skge_show_addr(dev1);
3975 else {
3976 /* Failure to register second port need not be fatal */
Stephen Hemminger1479d132007-02-02 08:22:52 -08003977 dev_warn(&pdev->dev, "register of second port failed\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003978 hw->dev[1] = NULL;
3979 free_netdev(dev1);
3980 }
3981 }
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003982 pci_set_drvdata(pdev, hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003983
3984 return 0;
3985
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003986err_out_unregister:
3987 unregister_netdev(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003988err_out_free_netdev:
3989 free_netdev(dev);
3990err_out_led_off:
3991 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003992err_out_iounmap:
3993 iounmap(hw->regs);
3994err_out_free_hw:
3995 kfree(hw);
3996err_out_free_regions:
3997 pci_release_regions(pdev);
3998err_out_disable_pdev:
3999 pci_disable_device(pdev);
4000 pci_set_drvdata(pdev, NULL);
4001err_out:
4002 return err;
4003}
4004
4005static void __devexit skge_remove(struct pci_dev *pdev)
4006{
4007 struct skge_hw *hw = pci_get_drvdata(pdev);
4008 struct net_device *dev0, *dev1;
4009
Stephen Hemminger95566062005-06-27 11:33:02 -07004010 if (!hw)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004011 return;
4012
Stephen Hemminger208491d82007-02-16 15:37:39 -08004013 flush_scheduled_work();
4014
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004015 if ((dev1 = hw->dev[1]))
4016 unregister_netdev(dev1);
4017 dev0 = hw->dev[0];
4018 unregister_netdev(dev0);
4019
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07004020 tasklet_disable(&hw->phy_task);
4021
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07004022 spin_lock_irq(&hw->hw_lock);
4023 hw->intr_mask = 0;
Stephen Hemminger46a60f22005-09-09 12:54:56 -07004024 skge_write32(hw, B0_IMSK, 0);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07004025 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07004026 spin_unlock_irq(&hw->hw_lock);
4027
Stephen Hemminger46a60f22005-09-09 12:54:56 -07004028 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07004029 skge_write8(hw, B0_CTST, CS_RST_SET);
4030
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004031 free_irq(pdev->irq, hw);
4032 pci_release_regions(pdev);
4033 pci_disable_device(pdev);
4034 if (dev1)
4035 free_netdev(dev1);
4036 free_netdev(dev0);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07004037
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004038 iounmap(hw->regs);
4039 kfree(hw);
4040 pci_set_drvdata(pdev, NULL);
4041}
4042
4043#ifdef CONFIG_PM
Pavel Machek2a569572005-07-07 17:56:40 -07004044static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004045{
4046 struct skge_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingera504e642007-02-02 08:22:53 -08004047 int i, err, wol = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004048
Stephen Hemmingere3b7df12007-05-11 11:21:45 -07004049 if (!hw)
4050 return 0;
4051
Stephen Hemmingera504e642007-02-02 08:22:53 -08004052 err = pci_save_state(pdev);
4053 if (err)
4054 return err;
4055
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004056 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004057 struct net_device *dev = hw->dev[i];
Stephen Hemmingera504e642007-02-02 08:22:53 -08004058 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004059
Stephen Hemmingera504e642007-02-02 08:22:53 -08004060 if (netif_running(dev))
4061 skge_down(dev);
4062 if (skge->wol)
4063 skge_wol_init(skge);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004064
Stephen Hemmingera504e642007-02-02 08:22:53 -08004065 wol |= skge->wol;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004066 }
4067
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004068 skge_write32(hw, B0_IMSK, 0);
Pavel Machek2a569572005-07-07 17:56:40 -07004069 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004070 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4071
4072 return 0;
4073}
4074
4075static int skge_resume(struct pci_dev *pdev)
4076{
4077 struct skge_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004078 int i, err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004079
Stephen Hemmingere3b7df12007-05-11 11:21:45 -07004080 if (!hw)
4081 return 0;
4082
Stephen Hemmingera504e642007-02-02 08:22:53 -08004083 err = pci_set_power_state(pdev, PCI_D0);
4084 if (err)
4085 goto out;
4086
4087 err = pci_restore_state(pdev);
4088 if (err)
4089 goto out;
4090
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004091 pci_enable_wake(pdev, PCI_D0, 0);
4092
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004093 err = skge_reset(hw);
4094 if (err)
4095 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004096
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004097 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004098 struct net_device *dev = hw->dev[i];
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004099
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004100 if (netif_running(dev)) {
4101 err = skge_up(dev);
4102
4103 if (err) {
4104 printk(KERN_ERR PFX "%s: could not up: %d\n",
4105 dev->name, err);
Stephen Hemmingeredd702e2005-12-15 12:18:00 -08004106 dev_close(dev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004107 goto out;
4108 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004109 }
4110 }
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004111out:
4112 return err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004113}
4114#endif
4115
Stephen Hemminger692412b2007-04-09 15:32:45 -07004116static void skge_shutdown(struct pci_dev *pdev)
4117{
4118 struct skge_hw *hw = pci_get_drvdata(pdev);
4119 int i, wol = 0;
4120
Stephen Hemmingere3b7df12007-05-11 11:21:45 -07004121 if (!hw)
4122 return;
4123
Stephen Hemminger692412b2007-04-09 15:32:45 -07004124 for (i = 0; i < hw->ports; i++) {
4125 struct net_device *dev = hw->dev[i];
4126 struct skge_port *skge = netdev_priv(dev);
4127
4128 if (skge->wol)
4129 skge_wol_init(skge);
4130 wol |= skge->wol;
4131 }
4132
4133 pci_enable_wake(pdev, PCI_D3hot, wol);
4134 pci_enable_wake(pdev, PCI_D3cold, wol);
4135
4136 pci_disable_device(pdev);
4137 pci_set_power_state(pdev, PCI_D3hot);
4138
4139}
4140
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004141static struct pci_driver skge_driver = {
4142 .name = DRV_NAME,
4143 .id_table = skge_id_table,
4144 .probe = skge_probe,
4145 .remove = __devexit_p(skge_remove),
4146#ifdef CONFIG_PM
4147 .suspend = skge_suspend,
4148 .resume = skge_resume,
4149#endif
Stephen Hemminger692412b2007-04-09 15:32:45 -07004150 .shutdown = skge_shutdown,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004151};
4152
4153static int __init skge_init_module(void)
4154{
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07004155 skge_debug_init();
Jeff Garzik29917622006-08-19 17:48:59 -04004156 return pci_register_driver(&skge_driver);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004157}
4158
4159static void __exit skge_cleanup_module(void)
4160{
4161 pci_unregister_driver(&skge_driver);
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07004162 skge_debug_cleanup();
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004163}
4164
4165module_init(skge_init_module);
4166module_exit(skge_cleanup_module);