Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
| 26 | * Courtney Goeltzenleuchter <courtney@lunarg.com> |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 27 | */ |
| 28 | |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 29 | #include "genhw/genhw.h" |
| 30 | #include "kmd/winsys.h" |
| 31 | #include "dev.h" |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 32 | #include "mem.h" |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 33 | #include "obj.h" |
Chia-I Wu | 00a23b2 | 2014-08-20 15:28:08 +0800 | [diff] [blame] | 34 | #include "cmd_priv.h" |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 35 | |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 36 | /** |
| 37 | * Free all resources used by a writer. Note that the initial size is not |
| 38 | * reset. |
| 39 | */ |
| 40 | static void cmd_writer_reset(struct intel_cmd *cmd, |
| 41 | enum intel_cmd_writer_type which) |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 42 | { |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 43 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 44 | |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 45 | if (writer->ptr) { |
| 46 | intel_bo_unmap(writer->bo); |
| 47 | writer->ptr = NULL; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 48 | } |
| 49 | |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 50 | if (writer->bo) { |
| 51 | intel_bo_unreference(writer->bo); |
| 52 | writer->bo = NULL; |
| 53 | } |
| 54 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 55 | writer->used = 0; |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 56 | |
| 57 | if (writer->items) { |
| 58 | icd_free(writer->items); |
Courtney Goeltzenleuchter | 2ba7016 | 2014-09-25 18:14:53 -0600 | [diff] [blame] | 59 | writer->items = NULL; |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 60 | writer->item_alloc = 0; |
| 61 | writer->item_used = 0; |
| 62 | } |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | /** |
| 66 | * Discard everything written so far. |
| 67 | */ |
| 68 | static void cmd_writer_discard(struct intel_cmd *cmd, |
| 69 | enum intel_cmd_writer_type which) |
| 70 | { |
| 71 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 72 | |
| 73 | intel_bo_truncate_relocs(writer->bo, 0); |
| 74 | writer->used = 0; |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 75 | writer->item_used = 0; |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys, |
| 79 | enum intel_cmd_writer_type which, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 80 | XGL_SIZE size) |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 81 | { |
| 82 | static const char *writer_names[INTEL_CMD_WRITER_COUNT] = { |
| 83 | [INTEL_CMD_WRITER_BATCH] = "batch", |
| 84 | [INTEL_CMD_WRITER_INSTRUCTION] = "instruction", |
| 85 | }; |
| 86 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 87 | return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true); |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | /** |
| 91 | * Allocate and map the buffer for writing. |
| 92 | */ |
| 93 | static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd, |
| 94 | enum intel_cmd_writer_type which) |
| 95 | { |
| 96 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 97 | struct intel_bo *bo; |
| 98 | |
| 99 | bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size); |
| 100 | if (bo) { |
| 101 | if (writer->bo) |
| 102 | intel_bo_unreference(writer->bo); |
| 103 | writer->bo = bo; |
| 104 | } else if (writer->bo) { |
| 105 | /* reuse the old bo */ |
| 106 | cmd_writer_discard(cmd, which); |
| 107 | } else { |
| 108 | return XGL_ERROR_OUT_OF_GPU_MEMORY; |
| 109 | } |
| 110 | |
| 111 | writer->used = 0; |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 112 | writer->item_used = 0; |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 113 | |
| 114 | writer->ptr = intel_bo_map(writer->bo, true); |
| 115 | if (!writer->ptr) |
| 116 | return XGL_ERROR_UNKNOWN; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 117 | |
| 118 | return XGL_SUCCESS; |
| 119 | } |
| 120 | |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 121 | /** |
| 122 | * Unmap the buffer for submission. |
| 123 | */ |
| 124 | static void cmd_writer_unmap(struct intel_cmd *cmd, |
| 125 | enum intel_cmd_writer_type which) |
Chia-I Wu | 5e25c27 | 2014-08-21 20:19:12 +0800 | [diff] [blame] | 126 | { |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 127 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 128 | |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 129 | intel_bo_unmap(writer->bo); |
| 130 | writer->ptr = NULL; |
| 131 | } |
| 132 | |
| 133 | /** |
| 134 | * Grow a mapped writer to at least \p new_size. Failures are handled |
| 135 | * silently. |
| 136 | */ |
| 137 | void cmd_writer_grow(struct intel_cmd *cmd, |
| 138 | enum intel_cmd_writer_type which, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 139 | XGL_SIZE new_size) |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 140 | { |
| 141 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 142 | struct intel_bo *new_bo; |
| 143 | void *new_ptr; |
| 144 | |
| 145 | if (new_size < writer->size << 1) |
| 146 | new_size = writer->size << 1; |
| 147 | /* STATE_BASE_ADDRESS requires page-aligned buffers */ |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 148 | new_size = u_align(new_size, 4096); |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 149 | |
| 150 | new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size); |
| 151 | if (!new_bo) { |
| 152 | cmd_writer_discard(cmd, which); |
| 153 | cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY; |
| 154 | return; |
| 155 | } |
| 156 | |
| 157 | /* map and copy the data over */ |
| 158 | new_ptr = intel_bo_map(new_bo, true); |
| 159 | if (!new_ptr) { |
| 160 | intel_bo_unreference(new_bo); |
| 161 | cmd_writer_discard(cmd, which); |
| 162 | cmd->result = XGL_ERROR_UNKNOWN; |
| 163 | return; |
| 164 | } |
| 165 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 166 | memcpy(new_ptr, writer->ptr, writer->used); |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 167 | |
| 168 | intel_bo_unmap(writer->bo); |
| 169 | intel_bo_unreference(writer->bo); |
| 170 | |
| 171 | writer->size = new_size; |
| 172 | writer->bo = new_bo; |
| 173 | writer->ptr = new_ptr; |
Chia-I Wu | 5e25c27 | 2014-08-21 20:19:12 +0800 | [diff] [blame] | 174 | } |
| 175 | |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 176 | /** |
| 177 | * Record an item for later decoding. |
| 178 | */ |
| 179 | void cmd_writer_record(struct intel_cmd *cmd, |
| 180 | enum intel_cmd_writer_type which, |
| 181 | enum intel_cmd_item_type type, |
| 182 | XGL_SIZE offset, XGL_SIZE size) |
| 183 | { |
| 184 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 185 | struct intel_cmd_item *item; |
| 186 | |
| 187 | if (writer->item_used == writer->item_alloc) { |
| 188 | const unsigned new_alloc = (writer->item_alloc) ? |
| 189 | writer->item_alloc << 1 : 256; |
| 190 | struct intel_cmd_item *items; |
| 191 | |
| 192 | items = icd_alloc(sizeof(writer->items[0]) * new_alloc, |
| 193 | 0, XGL_SYSTEM_ALLOC_DEBUG); |
| 194 | if (!items) { |
| 195 | writer->item_used = 0; |
| 196 | cmd->result = XGL_ERROR_OUT_OF_MEMORY; |
| 197 | return; |
| 198 | } |
| 199 | |
| 200 | memcpy(items, writer->items, |
| 201 | sizeof(writer->items[0]) * writer->item_alloc); |
| 202 | |
| 203 | icd_free(writer->items); |
| 204 | |
| 205 | writer->items = items; |
| 206 | writer->item_alloc = new_alloc; |
| 207 | } |
| 208 | |
| 209 | item = &writer->items[writer->item_used++]; |
| 210 | item->type = type; |
| 211 | item->offset = offset; |
| 212 | item->size = size; |
| 213 | } |
| 214 | |
Chia-I Wu | 5e25c27 | 2014-08-21 20:19:12 +0800 | [diff] [blame] | 215 | static void cmd_writer_patch(struct intel_cmd *cmd, |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 216 | enum intel_cmd_writer_type which, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 217 | XGL_SIZE offset, uint32_t val) |
Chia-I Wu | 5e25c27 | 2014-08-21 20:19:12 +0800 | [diff] [blame] | 218 | { |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 219 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 220 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 221 | assert(offset + sizeof(val) <= writer->used); |
| 222 | *((uint32_t *) ((char *) writer->ptr + offset)) = val; |
Chia-I Wu | 5e25c27 | 2014-08-21 20:19:12 +0800 | [diff] [blame] | 223 | } |
| 224 | |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 225 | static void cmd_reset(struct intel_cmd *cmd) |
| 226 | { |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 227 | XGL_UINT i; |
| 228 | |
| 229 | for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) |
| 230 | cmd_writer_reset(cmd, i); |
Chia-I Wu | e97aa0e | 2014-08-27 12:51:26 +0800 | [diff] [blame] | 231 | |
Chia-I Wu | a57761b | 2014-10-14 14:27:44 +0800 | [diff] [blame] | 232 | if (cmd->bind.shader_cache.entries) |
| 233 | icd_free(cmd->bind.shader_cache.entries); |
| 234 | |
Chia-I Wu | e97aa0e | 2014-08-27 12:51:26 +0800 | [diff] [blame] | 235 | memset(&cmd->bind, 0, sizeof(cmd->bind)); |
| 236 | |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 237 | cmd->reloc_used = 0; |
Chia-I Wu | 0496670 | 2014-08-20 15:05:03 +0800 | [diff] [blame] | 238 | cmd->result = XGL_SUCCESS; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | static void cmd_destroy(struct intel_obj *obj) |
| 242 | { |
| 243 | struct intel_cmd *cmd = intel_cmd_from_obj(obj); |
| 244 | |
| 245 | intel_cmd_destroy(cmd); |
| 246 | } |
| 247 | |
| 248 | XGL_RESULT intel_cmd_create(struct intel_dev *dev, |
| 249 | const XGL_CMD_BUFFER_CREATE_INFO *info, |
| 250 | struct intel_cmd **cmd_ret) |
| 251 | { |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 252 | int pipeline_select; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 253 | struct intel_cmd *cmd; |
| 254 | |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 255 | switch (info->queueType) { |
| 256 | case XGL_QUEUE_TYPE_GRAPHICS: |
| 257 | pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D; |
| 258 | break; |
| 259 | case XGL_QUEUE_TYPE_COMPUTE: |
| 260 | pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA; |
| 261 | break; |
| 262 | case XGL_QUEUE_TYPE_DMA: |
| 263 | pipeline_select = -1; |
| 264 | break; |
| 265 | default: |
| 266 | return XGL_ERROR_INVALID_VALUE; |
| 267 | break; |
| 268 | } |
| 269 | |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 270 | cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd), |
| 271 | dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0); |
| 272 | if (!cmd) |
| 273 | return XGL_ERROR_OUT_OF_MEMORY; |
| 274 | |
| 275 | cmd->obj.destroy = cmd_destroy; |
| 276 | |
| 277 | cmd->dev = dev; |
Chia-I Wu | 0b78444 | 2014-08-25 22:54:16 +0800 | [diff] [blame] | 278 | cmd->scratch_bo = dev->cmd_scratch_bo; |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 279 | cmd->pipeline_select = pipeline_select; |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 280 | |
Chia-I Wu | e0cdd83 | 2014-08-25 12:38:56 +0800 | [diff] [blame] | 281 | /* |
| 282 | * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to |
| 283 | * batch_buffer_reloc_count, but we may emit up to two relocs, for start |
| 284 | * and end offsets, for each referenced memories. |
| 285 | */ |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 286 | cmd->reloc_count = dev->gpu->batch_buffer_reloc_count; |
| 287 | cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count, |
| 288 | 4096, XGL_SYSTEM_ALLOC_INTERNAL); |
| 289 | if (!cmd->relocs) { |
| 290 | intel_cmd_destroy(cmd); |
| 291 | return XGL_ERROR_OUT_OF_MEMORY; |
| 292 | } |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 293 | |
| 294 | *cmd_ret = cmd; |
| 295 | |
| 296 | return XGL_SUCCESS; |
| 297 | } |
| 298 | |
| 299 | void intel_cmd_destroy(struct intel_cmd *cmd) |
| 300 | { |
| 301 | cmd_reset(cmd); |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 302 | |
| 303 | icd_free(cmd->relocs); |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 304 | intel_base_destroy(&cmd->obj.base); |
| 305 | } |
| 306 | |
| 307 | XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags) |
| 308 | { |
Chia-I Wu | 24565ee | 2014-08-21 20:24:31 +0800 | [diff] [blame] | 309 | XGL_RESULT ret; |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 310 | XGL_UINT i; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 311 | |
| 312 | cmd_reset(cmd); |
| 313 | |
Chia-I Wu | 24565ee | 2014-08-21 20:24:31 +0800 | [diff] [blame] | 314 | if (cmd->flags != flags) { |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 315 | cmd->flags = flags; |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 316 | cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 317 | } |
| 318 | |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 319 | if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) { |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 320 | const XGL_UINT size = cmd->dev->gpu->max_batch_buffer_size / 2; |
Chia-I Wu | 1cbc005 | 2014-08-25 09:50:12 +0800 | [diff] [blame] | 321 | XGL_UINT divider = 1; |
Chia-I Wu | 24565ee | 2014-08-21 20:24:31 +0800 | [diff] [blame] | 322 | |
| 323 | if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT) |
| 324 | divider *= 4; |
| 325 | |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 326 | cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider; |
| 327 | cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider; |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 328 | cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider; |
Chia-I Wu | 24565ee | 2014-08-21 20:24:31 +0800 | [diff] [blame] | 329 | } |
| 330 | |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 331 | for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) { |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 332 | ret = cmd_writer_alloc_and_map(cmd, i); |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 333 | if (ret != XGL_SUCCESS) { |
| 334 | cmd_reset(cmd); |
| 335 | return ret; |
| 336 | } |
Chia-I Wu | 24565ee | 2014-08-21 20:24:31 +0800 | [diff] [blame] | 337 | } |
| 338 | |
Chia-I Wu | 79dfbb3 | 2014-08-25 12:19:02 +0800 | [diff] [blame] | 339 | cmd_batch_begin(cmd); |
| 340 | |
Chia-I Wu | 24565ee | 2014-08-21 20:24:31 +0800 | [diff] [blame] | 341 | return XGL_SUCCESS; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | XGL_RESULT intel_cmd_end(struct intel_cmd *cmd) |
| 345 | { |
| 346 | struct intel_winsys *winsys = cmd->dev->winsys; |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 347 | XGL_UINT i; |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 348 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 349 | cmd_batch_end(cmd); |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 350 | |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 351 | /* TODO we need a more "explicit" winsys */ |
Chia-I Wu | fdfb8ed | 2014-08-21 15:40:07 +0800 | [diff] [blame] | 352 | for (i = 0; i < cmd->reloc_used; i++) { |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 353 | const struct intel_cmd_reloc *reloc = &cmd->relocs[i]; |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 354 | const struct intel_cmd_writer *writer = &cmd->writers[reloc->which]; |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 355 | uint64_t presumed_offset; |
| 356 | int err; |
| 357 | |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame^] | 358 | /* |
| 359 | * Once a bo is used as a reloc target, libdrm_intel disallows more |
| 360 | * relocs to be added to it. That may happen when |
| 361 | * INTEL_CMD_RELOC_TARGET_IS_WRITER is set. We have to process them |
| 362 | * in another pass. |
| 363 | */ |
| 364 | if (reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER) |
| 365 | continue; |
| 366 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 367 | err = intel_bo_add_reloc(writer->bo, reloc->offset, |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame^] | 368 | (struct intel_bo *) reloc->target, reloc->target_offset, |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 369 | reloc->flags, &presumed_offset); |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 370 | if (err) { |
| 371 | cmd->result = XGL_ERROR_UNKNOWN; |
| 372 | break; |
| 373 | } |
| 374 | |
| 375 | assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset); |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 376 | cmd_writer_patch(cmd, reloc->which, reloc->offset, |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 377 | (uint32_t) presumed_offset); |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 378 | } |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame^] | 379 | for (i = 0; i < cmd->reloc_used; i++) { |
| 380 | const struct intel_cmd_reloc *reloc = &cmd->relocs[i]; |
| 381 | const struct intel_cmd_writer *writer = &cmd->writers[reloc->which]; |
| 382 | uint64_t presumed_offset; |
| 383 | int err; |
| 384 | |
| 385 | if (!(reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER)) |
| 386 | continue; |
| 387 | |
| 388 | err = intel_bo_add_reloc(writer->bo, reloc->offset, |
| 389 | cmd->writers[reloc->target].bo, reloc->target_offset, |
| 390 | reloc->flags & ~INTEL_CMD_RELOC_TARGET_IS_WRITER, |
| 391 | &presumed_offset); |
| 392 | if (err) { |
| 393 | cmd->result = XGL_ERROR_UNKNOWN; |
| 394 | break; |
| 395 | } |
| 396 | |
| 397 | assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset); |
| 398 | cmd_writer_patch(cmd, reloc->which, reloc->offset, |
| 399 | (uint32_t) presumed_offset); |
| 400 | } |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 401 | |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 402 | for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) |
| 403 | cmd_writer_unmap(cmd, i); |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 404 | |
Chia-I Wu | 0496670 | 2014-08-20 15:05:03 +0800 | [diff] [blame] | 405 | if (cmd->result != XGL_SUCCESS) |
| 406 | return cmd->result; |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 407 | |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 408 | if (intel_winsys_can_submit_bo(winsys, |
| 409 | &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1)) |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 410 | return XGL_SUCCESS; |
| 411 | else |
| 412 | return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES; |
| 413 | } |
| 414 | |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 415 | XGL_RESULT XGLAPI intelCreateCommandBuffer( |
| 416 | XGL_DEVICE device, |
| 417 | const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo, |
| 418 | XGL_CMD_BUFFER* pCmdBuffer) |
| 419 | { |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 420 | struct intel_dev *dev = intel_dev(device); |
| 421 | |
| 422 | return intel_cmd_create(dev, pCreateInfo, |
| 423 | (struct intel_cmd **) pCmdBuffer); |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 424 | } |
| 425 | |
| 426 | XGL_RESULT XGLAPI intelBeginCommandBuffer( |
| 427 | XGL_CMD_BUFFER cmdBuffer, |
| 428 | XGL_FLAGS flags) |
| 429 | { |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 430 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 431 | |
| 432 | return intel_cmd_begin(cmd, flags); |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | XGL_RESULT XGLAPI intelEndCommandBuffer( |
| 436 | XGL_CMD_BUFFER cmdBuffer) |
| 437 | { |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 438 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 439 | |
| 440 | return intel_cmd_end(cmd); |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 441 | } |
| 442 | |
| 443 | XGL_RESULT XGLAPI intelResetCommandBuffer( |
| 444 | XGL_CMD_BUFFER cmdBuffer) |
| 445 | { |
Chia-I Wu | 730e536 | 2014-08-19 12:15:09 +0800 | [diff] [blame] | 446 | struct intel_cmd *cmd = intel_cmd(cmdBuffer); |
| 447 | |
| 448 | cmd_reset(cmd); |
| 449 | |
| 450 | return XGL_SUCCESS; |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 451 | } |
| 452 | |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 453 | XGL_VOID XGLAPI intelCmdCopyMemory( |
| 454 | XGL_CMD_BUFFER cmdBuffer, |
| 455 | XGL_GPU_MEMORY srcMem, |
| 456 | XGL_GPU_MEMORY destMem, |
| 457 | XGL_UINT regionCount, |
| 458 | const XGL_MEMORY_COPY* pRegions) |
| 459 | { |
| 460 | } |
| 461 | |
| 462 | XGL_VOID XGLAPI intelCmdCopyImage( |
| 463 | XGL_CMD_BUFFER cmdBuffer, |
| 464 | XGL_IMAGE srcImage, |
| 465 | XGL_IMAGE destImage, |
| 466 | XGL_UINT regionCount, |
| 467 | const XGL_IMAGE_COPY* pRegions) |
| 468 | { |
| 469 | } |
| 470 | |
| 471 | XGL_VOID XGLAPI intelCmdCopyMemoryToImage( |
| 472 | XGL_CMD_BUFFER cmdBuffer, |
| 473 | XGL_GPU_MEMORY srcMem, |
| 474 | XGL_IMAGE destImage, |
| 475 | XGL_UINT regionCount, |
| 476 | const XGL_MEMORY_IMAGE_COPY* pRegions) |
| 477 | { |
| 478 | } |
| 479 | |
| 480 | XGL_VOID XGLAPI intelCmdCopyImageToMemory( |
| 481 | XGL_CMD_BUFFER cmdBuffer, |
| 482 | XGL_IMAGE srcImage, |
| 483 | XGL_GPU_MEMORY destMem, |
| 484 | XGL_UINT regionCount, |
| 485 | const XGL_MEMORY_IMAGE_COPY* pRegions) |
| 486 | { |
| 487 | } |
| 488 | |
| 489 | XGL_VOID XGLAPI intelCmdCloneImageData( |
| 490 | XGL_CMD_BUFFER cmdBuffer, |
| 491 | XGL_IMAGE srcImage, |
| 492 | XGL_IMAGE_STATE srcImageState, |
| 493 | XGL_IMAGE destImage, |
| 494 | XGL_IMAGE_STATE destImageState) |
| 495 | { |
| 496 | } |
| 497 | |
| 498 | XGL_VOID XGLAPI intelCmdUpdateMemory( |
| 499 | XGL_CMD_BUFFER cmdBuffer, |
| 500 | XGL_GPU_MEMORY destMem, |
| 501 | XGL_GPU_SIZE destOffset, |
| 502 | XGL_GPU_SIZE dataSize, |
| 503 | const XGL_UINT32* pData) |
| 504 | { |
| 505 | } |
| 506 | |
| 507 | XGL_VOID XGLAPI intelCmdFillMemory( |
| 508 | XGL_CMD_BUFFER cmdBuffer, |
| 509 | XGL_GPU_MEMORY destMem, |
| 510 | XGL_GPU_SIZE destOffset, |
| 511 | XGL_GPU_SIZE fillSize, |
| 512 | XGL_UINT32 data) |
| 513 | { |
| 514 | } |
| 515 | |
| 516 | XGL_VOID XGLAPI intelCmdClearColorImage( |
| 517 | XGL_CMD_BUFFER cmdBuffer, |
| 518 | XGL_IMAGE image, |
| 519 | const XGL_FLOAT color[4], |
| 520 | XGL_UINT rangeCount, |
| 521 | const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges) |
| 522 | { |
| 523 | } |
| 524 | |
| 525 | XGL_VOID XGLAPI intelCmdClearColorImageRaw( |
| 526 | XGL_CMD_BUFFER cmdBuffer, |
| 527 | XGL_IMAGE image, |
| 528 | const XGL_UINT32 color[4], |
| 529 | XGL_UINT rangeCount, |
| 530 | const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges) |
| 531 | { |
| 532 | } |
| 533 | |
| 534 | XGL_VOID XGLAPI intelCmdClearDepthStencil( |
| 535 | XGL_CMD_BUFFER cmdBuffer, |
| 536 | XGL_IMAGE image, |
| 537 | XGL_FLOAT depth, |
| 538 | XGL_UINT32 stencil, |
| 539 | XGL_UINT rangeCount, |
| 540 | const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges) |
| 541 | { |
| 542 | } |
| 543 | |
| 544 | XGL_VOID XGLAPI intelCmdResolveImage( |
| 545 | XGL_CMD_BUFFER cmdBuffer, |
| 546 | XGL_IMAGE srcImage, |
| 547 | XGL_IMAGE destImage, |
| 548 | XGL_UINT rectCount, |
| 549 | const XGL_IMAGE_RESOLVE* pRects) |
| 550 | { |
| 551 | } |
| 552 | |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 553 | XGL_VOID XGLAPI intelCmdMemoryAtomic( |
| 554 | XGL_CMD_BUFFER cmdBuffer, |
| 555 | XGL_GPU_MEMORY destMem, |
| 556 | XGL_GPU_SIZE destOffset, |
| 557 | XGL_UINT64 srcData, |
| 558 | XGL_ATOMIC_OP atomicOp) |
| 559 | { |
| 560 | } |
| 561 | |
Chia-I Wu | 0914213 | 2014-08-11 15:42:55 +0800 | [diff] [blame] | 562 | XGL_VOID XGLAPI intelCmdInitAtomicCounters( |
| 563 | XGL_CMD_BUFFER cmdBuffer, |
| 564 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 565 | XGL_UINT startCounter, |
| 566 | XGL_UINT counterCount, |
| 567 | const XGL_UINT32* pData) |
| 568 | { |
| 569 | } |
| 570 | |
| 571 | XGL_VOID XGLAPI intelCmdLoadAtomicCounters( |
| 572 | XGL_CMD_BUFFER cmdBuffer, |
| 573 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 574 | XGL_UINT startCounter, |
| 575 | XGL_UINT counterCount, |
| 576 | XGL_GPU_MEMORY srcMem, |
| 577 | XGL_GPU_SIZE srcOffset) |
| 578 | { |
| 579 | } |
| 580 | |
| 581 | XGL_VOID XGLAPI intelCmdSaveAtomicCounters( |
| 582 | XGL_CMD_BUFFER cmdBuffer, |
| 583 | XGL_PIPELINE_BIND_POINT pipelineBindPoint, |
| 584 | XGL_UINT startCounter, |
| 585 | XGL_UINT counterCount, |
| 586 | XGL_GPU_MEMORY destMem, |
| 587 | XGL_GPU_SIZE destOffset) |
| 588 | { |
| 589 | } |
| 590 | |
| 591 | XGL_VOID XGLAPI intelCmdDbgMarkerBegin( |
| 592 | XGL_CMD_BUFFER cmdBuffer, |
| 593 | const XGL_CHAR* pMarker) |
| 594 | { |
| 595 | } |
| 596 | |
| 597 | XGL_VOID XGLAPI intelCmdDbgMarkerEnd( |
| 598 | XGL_CMD_BUFFER cmdBuffer) |
| 599 | { |
| 600 | } |