blob: 6467589c7a7c49403779c2af9d003b67d62a4072 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080035
Chia-I Wu3c3edc02014-09-09 10:32:59 +080036/**
37 * Free all resources used by a writer. Note that the initial size is not
38 * reset.
39 */
40static void cmd_writer_reset(struct intel_cmd *cmd,
41 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080042{
Chia-I Wu68f319d2014-09-09 09:43:21 +080043 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080044
Chia-I Wu3c3edc02014-09-09 10:32:59 +080045 if (writer->ptr) {
46 intel_bo_unmap(writer->bo);
47 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080048 }
49
Chia-I Wu3c3edc02014-09-09 10:32:59 +080050 if (writer->bo) {
51 intel_bo_unreference(writer->bo);
52 writer->bo = NULL;
53 }
54
Chia-I Wue24c3292014-08-21 14:05:23 +080055 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080056
57 if (writer->items) {
58 icd_free(writer->items);
Courtney Goeltzenleuchter2ba70162014-09-25 18:14:53 -060059 writer->items = NULL;
Chia-I Wu00b51a82014-09-09 12:07:37 +080060 writer->item_alloc = 0;
61 writer->item_used = 0;
62 }
Chia-I Wu3c3edc02014-09-09 10:32:59 +080063}
64
65/**
66 * Discard everything written so far.
67 */
68static void cmd_writer_discard(struct intel_cmd *cmd,
69 enum intel_cmd_writer_type which)
70{
71 struct intel_cmd_writer *writer = &cmd->writers[which];
72
73 intel_bo_truncate_relocs(writer->bo, 0);
74 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080075 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080076}
77
78static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
79 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +080080 XGL_SIZE size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +080081{
82 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
83 [INTEL_CMD_WRITER_BATCH] = "batch",
84 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
85 };
86
Chia-I Wu72292b72014-09-09 10:48:33 +080087 return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true);
Chia-I Wu3c3edc02014-09-09 10:32:59 +080088}
89
90/**
91 * Allocate and map the buffer for writing.
92 */
93static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
94 enum intel_cmd_writer_type which)
95{
96 struct intel_cmd_writer *writer = &cmd->writers[which];
97 struct intel_bo *bo;
98
99 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
100 if (bo) {
101 if (writer->bo)
102 intel_bo_unreference(writer->bo);
103 writer->bo = bo;
104 } else if (writer->bo) {
105 /* reuse the old bo */
106 cmd_writer_discard(cmd, which);
107 } else {
108 return XGL_ERROR_OUT_OF_GPU_MEMORY;
109 }
110
111 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800112 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800113
114 writer->ptr = intel_bo_map(writer->bo, true);
115 if (!writer->ptr)
116 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800117
118 return XGL_SUCCESS;
119}
120
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800121/**
122 * Unmap the buffer for submission.
123 */
124static void cmd_writer_unmap(struct intel_cmd *cmd,
125 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800126{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800127 struct intel_cmd_writer *writer = &cmd->writers[which];
128
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800129 intel_bo_unmap(writer->bo);
130 writer->ptr = NULL;
131}
132
133/**
134 * Grow a mapped writer to at least \p new_size. Failures are handled
135 * silently.
136 */
137void cmd_writer_grow(struct intel_cmd *cmd,
138 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +0800139 XGL_SIZE new_size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800140{
141 struct intel_cmd_writer *writer = &cmd->writers[which];
142 struct intel_bo *new_bo;
143 void *new_ptr;
144
145 if (new_size < writer->size << 1)
146 new_size = writer->size << 1;
147 /* STATE_BASE_ADDRESS requires page-aligned buffers */
Chia-I Wu72292b72014-09-09 10:48:33 +0800148 new_size = u_align(new_size, 4096);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800149
150 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
151 if (!new_bo) {
152 cmd_writer_discard(cmd, which);
153 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
154 return;
155 }
156
157 /* map and copy the data over */
158 new_ptr = intel_bo_map(new_bo, true);
159 if (!new_ptr) {
160 intel_bo_unreference(new_bo);
161 cmd_writer_discard(cmd, which);
162 cmd->result = XGL_ERROR_UNKNOWN;
163 return;
164 }
165
Chia-I Wu72292b72014-09-09 10:48:33 +0800166 memcpy(new_ptr, writer->ptr, writer->used);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800167
168 intel_bo_unmap(writer->bo);
169 intel_bo_unreference(writer->bo);
170
171 writer->size = new_size;
172 writer->bo = new_bo;
173 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800174}
175
Chia-I Wu00b51a82014-09-09 12:07:37 +0800176/**
177 * Record an item for later decoding.
178 */
179void cmd_writer_record(struct intel_cmd *cmd,
180 enum intel_cmd_writer_type which,
181 enum intel_cmd_item_type type,
182 XGL_SIZE offset, XGL_SIZE size)
183{
184 struct intel_cmd_writer *writer = &cmd->writers[which];
185 struct intel_cmd_item *item;
186
187 if (writer->item_used == writer->item_alloc) {
188 const unsigned new_alloc = (writer->item_alloc) ?
189 writer->item_alloc << 1 : 256;
190 struct intel_cmd_item *items;
191
192 items = icd_alloc(sizeof(writer->items[0]) * new_alloc,
193 0, XGL_SYSTEM_ALLOC_DEBUG);
194 if (!items) {
195 writer->item_used = 0;
196 cmd->result = XGL_ERROR_OUT_OF_MEMORY;
197 return;
198 }
199
200 memcpy(items, writer->items,
201 sizeof(writer->items[0]) * writer->item_alloc);
202
203 icd_free(writer->items);
204
205 writer->items = items;
206 writer->item_alloc = new_alloc;
207 }
208
209 item = &writer->items[writer->item_used++];
210 item->type = type;
211 item->offset = offset;
212 item->size = size;
213}
214
Chia-I Wu5e25c272014-08-21 20:19:12 +0800215static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800216 enum intel_cmd_writer_type which,
Chia-I Wu72292b72014-09-09 10:48:33 +0800217 XGL_SIZE offset, uint32_t val)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800218{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800219 struct intel_cmd_writer *writer = &cmd->writers[which];
220
Chia-I Wu72292b72014-09-09 10:48:33 +0800221 assert(offset + sizeof(val) <= writer->used);
222 *((uint32_t *) ((char *) writer->ptr + offset)) = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800223}
224
Chia-I Wu730e5362014-08-19 12:15:09 +0800225static void cmd_reset(struct intel_cmd *cmd)
226{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800227 XGL_UINT i;
228
229 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
230 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800231
Chia-I Wua57761b2014-10-14 14:27:44 +0800232 if (cmd->bind.shader_cache.entries)
233 icd_free(cmd->bind.shader_cache.entries);
234
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800235 memset(&cmd->bind, 0, sizeof(cmd->bind));
236
Chia-I Wu343b1372014-08-20 16:39:20 +0800237 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800238 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800239}
240
241static void cmd_destroy(struct intel_obj *obj)
242{
243 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
244
245 intel_cmd_destroy(cmd);
246}
247
248XGL_RESULT intel_cmd_create(struct intel_dev *dev,
249 const XGL_CMD_BUFFER_CREATE_INFO *info,
250 struct intel_cmd **cmd_ret)
251{
Chia-I Wu63883292014-08-25 13:50:26 +0800252 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800253 struct intel_cmd *cmd;
254
Chia-I Wu63883292014-08-25 13:50:26 +0800255 switch (info->queueType) {
256 case XGL_QUEUE_TYPE_GRAPHICS:
257 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
258 break;
259 case XGL_QUEUE_TYPE_COMPUTE:
260 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
261 break;
262 case XGL_QUEUE_TYPE_DMA:
263 pipeline_select = -1;
264 break;
265 default:
266 return XGL_ERROR_INVALID_VALUE;
267 break;
268 }
269
Chia-I Wu730e5362014-08-19 12:15:09 +0800270 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
271 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
272 if (!cmd)
273 return XGL_ERROR_OUT_OF_MEMORY;
274
275 cmd->obj.destroy = cmd_destroy;
276
277 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800278 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800279 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800280
Chia-I Wue0cdd832014-08-25 12:38:56 +0800281 /*
282 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
283 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
284 * and end offsets, for each referenced memories.
285 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800286 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
287 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
288 4096, XGL_SYSTEM_ALLOC_INTERNAL);
289 if (!cmd->relocs) {
290 intel_cmd_destroy(cmd);
291 return XGL_ERROR_OUT_OF_MEMORY;
292 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800293
294 *cmd_ret = cmd;
295
296 return XGL_SUCCESS;
297}
298
299void intel_cmd_destroy(struct intel_cmd *cmd)
300{
301 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800302
303 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800304 intel_base_destroy(&cmd->obj.base);
305}
306
307XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
308{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800309 XGL_RESULT ret;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800310 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800311
312 cmd_reset(cmd);
313
Chia-I Wu24565ee2014-08-21 20:24:31 +0800314 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800315 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800316 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800317 }
318
Chia-I Wu68f319d2014-09-09 09:43:21 +0800319 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Chia-I Wu72292b72014-09-09 10:48:33 +0800320 const XGL_UINT size = cmd->dev->gpu->max_batch_buffer_size / 2;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800321 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800322
323 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
324 divider *= 4;
325
Chia-I Wu68f319d2014-09-09 09:43:21 +0800326 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
327 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider;
Chia-I Wu72292b72014-09-09 10:48:33 +0800328 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800329 }
330
Chia-I Wu68f319d2014-09-09 09:43:21 +0800331 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800332 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800333 if (ret != XGL_SUCCESS) {
334 cmd_reset(cmd);
335 return ret;
336 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800337 }
338
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800339 cmd_batch_begin(cmd);
340
Chia-I Wu24565ee2014-08-21 20:24:31 +0800341 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800342}
343
344XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
345{
346 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800347 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800348
Chia-I Wue24c3292014-08-21 14:05:23 +0800349 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800350
Chia-I Wu343b1372014-08-20 16:39:20 +0800351 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800352 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800353 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800354 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800355 uint64_t presumed_offset;
356 int err;
357
Chia-I Wud7d1e482014-10-18 13:25:10 +0800358 /*
359 * Once a bo is used as a reloc target, libdrm_intel disallows more
360 * relocs to be added to it. That may happen when
361 * INTEL_CMD_RELOC_TARGET_IS_WRITER is set. We have to process them
362 * in another pass.
363 */
364 if (reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER)
365 continue;
366
Chia-I Wu72292b72014-09-09 10:48:33 +0800367 err = intel_bo_add_reloc(writer->bo, reloc->offset,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800368 (struct intel_bo *) reloc->target, reloc->target_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800369 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800370 if (err) {
371 cmd->result = XGL_ERROR_UNKNOWN;
372 break;
373 }
374
375 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu72292b72014-09-09 10:48:33 +0800376 cmd_writer_patch(cmd, reloc->which, reloc->offset,
Chia-I Wue24c3292014-08-21 14:05:23 +0800377 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800378 }
Chia-I Wud7d1e482014-10-18 13:25:10 +0800379 for (i = 0; i < cmd->reloc_used; i++) {
380 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
381 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
382 uint64_t presumed_offset;
383 int err;
384
385 if (!(reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER))
386 continue;
387
388 err = intel_bo_add_reloc(writer->bo, reloc->offset,
389 cmd->writers[reloc->target].bo, reloc->target_offset,
390 reloc->flags & ~INTEL_CMD_RELOC_TARGET_IS_WRITER,
391 &presumed_offset);
392 if (err) {
393 cmd->result = XGL_ERROR_UNKNOWN;
394 break;
395 }
396
397 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
398 cmd_writer_patch(cmd, reloc->which, reloc->offset,
399 (uint32_t) presumed_offset);
400 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800401
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800402 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
403 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800404
Chia-I Wu04966702014-08-20 15:05:03 +0800405 if (cmd->result != XGL_SUCCESS)
406 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800407
Chia-I Wu68f319d2014-09-09 09:43:21 +0800408 if (intel_winsys_can_submit_bo(winsys,
409 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800410 return XGL_SUCCESS;
411 else
412 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
413}
414
Chia-I Wu09142132014-08-11 15:42:55 +0800415XGL_RESULT XGLAPI intelCreateCommandBuffer(
416 XGL_DEVICE device,
417 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
418 XGL_CMD_BUFFER* pCmdBuffer)
419{
Chia-I Wu730e5362014-08-19 12:15:09 +0800420 struct intel_dev *dev = intel_dev(device);
421
422 return intel_cmd_create(dev, pCreateInfo,
423 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800424}
425
426XGL_RESULT XGLAPI intelBeginCommandBuffer(
427 XGL_CMD_BUFFER cmdBuffer,
428 XGL_FLAGS flags)
429{
Chia-I Wu730e5362014-08-19 12:15:09 +0800430 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
431
432 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800433}
434
435XGL_RESULT XGLAPI intelEndCommandBuffer(
436 XGL_CMD_BUFFER cmdBuffer)
437{
Chia-I Wu730e5362014-08-19 12:15:09 +0800438 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
439
440 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800441}
442
443XGL_RESULT XGLAPI intelResetCommandBuffer(
444 XGL_CMD_BUFFER cmdBuffer)
445{
Chia-I Wu730e5362014-08-19 12:15:09 +0800446 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
447
448 cmd_reset(cmd);
449
450 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800451}
452
Chia-I Wu09142132014-08-11 15:42:55 +0800453XGL_VOID XGLAPI intelCmdCopyMemory(
454 XGL_CMD_BUFFER cmdBuffer,
455 XGL_GPU_MEMORY srcMem,
456 XGL_GPU_MEMORY destMem,
457 XGL_UINT regionCount,
458 const XGL_MEMORY_COPY* pRegions)
459{
460}
461
462XGL_VOID XGLAPI intelCmdCopyImage(
463 XGL_CMD_BUFFER cmdBuffer,
464 XGL_IMAGE srcImage,
465 XGL_IMAGE destImage,
466 XGL_UINT regionCount,
467 const XGL_IMAGE_COPY* pRegions)
468{
469}
470
471XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
472 XGL_CMD_BUFFER cmdBuffer,
473 XGL_GPU_MEMORY srcMem,
474 XGL_IMAGE destImage,
475 XGL_UINT regionCount,
476 const XGL_MEMORY_IMAGE_COPY* pRegions)
477{
478}
479
480XGL_VOID XGLAPI intelCmdCopyImageToMemory(
481 XGL_CMD_BUFFER cmdBuffer,
482 XGL_IMAGE srcImage,
483 XGL_GPU_MEMORY destMem,
484 XGL_UINT regionCount,
485 const XGL_MEMORY_IMAGE_COPY* pRegions)
486{
487}
488
489XGL_VOID XGLAPI intelCmdCloneImageData(
490 XGL_CMD_BUFFER cmdBuffer,
491 XGL_IMAGE srcImage,
492 XGL_IMAGE_STATE srcImageState,
493 XGL_IMAGE destImage,
494 XGL_IMAGE_STATE destImageState)
495{
496}
497
498XGL_VOID XGLAPI intelCmdUpdateMemory(
499 XGL_CMD_BUFFER cmdBuffer,
500 XGL_GPU_MEMORY destMem,
501 XGL_GPU_SIZE destOffset,
502 XGL_GPU_SIZE dataSize,
503 const XGL_UINT32* pData)
504{
505}
506
507XGL_VOID XGLAPI intelCmdFillMemory(
508 XGL_CMD_BUFFER cmdBuffer,
509 XGL_GPU_MEMORY destMem,
510 XGL_GPU_SIZE destOffset,
511 XGL_GPU_SIZE fillSize,
512 XGL_UINT32 data)
513{
514}
515
516XGL_VOID XGLAPI intelCmdClearColorImage(
517 XGL_CMD_BUFFER cmdBuffer,
518 XGL_IMAGE image,
519 const XGL_FLOAT color[4],
520 XGL_UINT rangeCount,
521 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
522{
523}
524
525XGL_VOID XGLAPI intelCmdClearColorImageRaw(
526 XGL_CMD_BUFFER cmdBuffer,
527 XGL_IMAGE image,
528 const XGL_UINT32 color[4],
529 XGL_UINT rangeCount,
530 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
531{
532}
533
534XGL_VOID XGLAPI intelCmdClearDepthStencil(
535 XGL_CMD_BUFFER cmdBuffer,
536 XGL_IMAGE image,
537 XGL_FLOAT depth,
538 XGL_UINT32 stencil,
539 XGL_UINT rangeCount,
540 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
541{
542}
543
544XGL_VOID XGLAPI intelCmdResolveImage(
545 XGL_CMD_BUFFER cmdBuffer,
546 XGL_IMAGE srcImage,
547 XGL_IMAGE destImage,
548 XGL_UINT rectCount,
549 const XGL_IMAGE_RESOLVE* pRects)
550{
551}
552
Chia-I Wu09142132014-08-11 15:42:55 +0800553XGL_VOID XGLAPI intelCmdMemoryAtomic(
554 XGL_CMD_BUFFER cmdBuffer,
555 XGL_GPU_MEMORY destMem,
556 XGL_GPU_SIZE destOffset,
557 XGL_UINT64 srcData,
558 XGL_ATOMIC_OP atomicOp)
559{
560}
561
Chia-I Wu09142132014-08-11 15:42:55 +0800562XGL_VOID XGLAPI intelCmdInitAtomicCounters(
563 XGL_CMD_BUFFER cmdBuffer,
564 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
565 XGL_UINT startCounter,
566 XGL_UINT counterCount,
567 const XGL_UINT32* pData)
568{
569}
570
571XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
572 XGL_CMD_BUFFER cmdBuffer,
573 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
574 XGL_UINT startCounter,
575 XGL_UINT counterCount,
576 XGL_GPU_MEMORY srcMem,
577 XGL_GPU_SIZE srcOffset)
578{
579}
580
581XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
582 XGL_CMD_BUFFER cmdBuffer,
583 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
584 XGL_UINT startCounter,
585 XGL_UINT counterCount,
586 XGL_GPU_MEMORY destMem,
587 XGL_GPU_SIZE destOffset)
588{
589}
590
591XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
592 XGL_CMD_BUFFER cmdBuffer,
593 const XGL_CHAR* pMarker)
594{
595}
596
597XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
598 XGL_CMD_BUFFER cmdBuffer)
599{
600}