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gerrit-public.fairphone.software / toolchain / llvm-project / 0efdd06b22e697ae072bbe76071cb53b8ffb1ee0 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 65fe45e27e34786f48c142249df25025b1e313b3 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]21#include "llvm/CodeGen/LivePhysRegs.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]22#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]27#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]28#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]29#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]31#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]32#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]33#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]34#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]35#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]36#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]37#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]40#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]61static cl::opt<unsigned>
62PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67static cl::opt<unsigned>
68UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
Marina Yatsina88f0c312016-08-11 07:32:08 +0000[diff] [blame]71 cl::init(128), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]72
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]73enum {
74 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]75 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]79 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]80 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]104};
105
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]106struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]107 uint16_t RegOp;
108 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]109 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]110};
111
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]112// Pin the vtable to this file.
113void X86InstrInfo::anchor() {}
114
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]115X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
Dean Michael Berris52735fc2016-07-14 04:06:33 +0000[diff] [blame]120 X86::CATCHRET,
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]122 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]123
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]124 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
133 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
134 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
136 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
139 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
140 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
142 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
145 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
146 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
148 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16rCL, X86::SHL16mCL, 0 },
232 { X86::SHL16ri, X86::SHL16mi, 0 },
233 { X86::SHL32rCL, X86::SHL32mCL, 0 },
234 { X86::SHL32ri, X86::SHL32mi, 0 },
235 { X86::SHL64rCL, X86::SHL64mCL, 0 },
236 { X86::SHL64ri, X86::SHL64mi, 0 },
237 { X86::SHL8rCL, X86::SHL8mCL, 0 },
238 { X86::SHL8ri, X86::SHL8mi, 0 },
239 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
240 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
241 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
242 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
243 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
244 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
245 { X86::SHR16r1, X86::SHR16m1, 0 },
246 { X86::SHR16rCL, X86::SHR16mCL, 0 },
247 { X86::SHR16ri, X86::SHR16mi, 0 },
248 { X86::SHR32r1, X86::SHR32m1, 0 },
249 { X86::SHR32rCL, X86::SHR32mCL, 0 },
250 { X86::SHR32ri, X86::SHR32mi, 0 },
251 { X86::SHR64r1, X86::SHR64m1, 0 },
252 { X86::SHR64rCL, X86::SHR64mCL, 0 },
253 { X86::SHR64ri, X86::SHR64mi, 0 },
254 { X86::SHR8r1, X86::SHR8m1, 0 },
255 { X86::SHR8rCL, X86::SHR8mCL, 0 },
256 { X86::SHR8ri, X86::SHR8mi, 0 },
257 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
258 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
259 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
260 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
261 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
262 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
263 { X86::SUB16ri, X86::SUB16mi, 0 },
264 { X86::SUB16ri8, X86::SUB16mi8, 0 },
265 { X86::SUB16rr, X86::SUB16mr, 0 },
266 { X86::SUB32ri, X86::SUB32mi, 0 },
267 { X86::SUB32ri8, X86::SUB32mi8, 0 },
268 { X86::SUB32rr, X86::SUB32mr, 0 },
269 { X86::SUB64ri32, X86::SUB64mi32, 0 },
270 { X86::SUB64ri8, X86::SUB64mi8, 0 },
271 { X86::SUB64rr, X86::SUB64mr, 0 },
272 { X86::SUB8ri, X86::SUB8mi, 0 },
273 { X86::SUB8rr, X86::SUB8mr, 0 },
274 { X86::XOR16ri, X86::XOR16mi, 0 },
275 { X86::XOR16ri8, X86::XOR16mi8, 0 },
276 { X86::XOR16rr, X86::XOR16mr, 0 },
277 { X86::XOR32ri, X86::XOR32mi, 0 },
278 { X86::XOR32ri8, X86::XOR32mi8, 0 },
279 { X86::XOR32rr, X86::XOR32mr, 0 },
280 { X86::XOR64ri32, X86::XOR64mi32, 0 },
281 { X86::XOR64ri8, X86::XOR64mi8, 0 },
282 { X86::XOR64rr, X86::XOR64mr, 0 },
283 { X86::XOR8ri, X86::XOR8mi, 0 },
284 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]285 };
286
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]287 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]289 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]290 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]291 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]292 }
293
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]294 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]295 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
296 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
297 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
298 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
299 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]300 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
301 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
302 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
303 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
304 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
305 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
306 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
307 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
308 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
309 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
310 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
311 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
312 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
313 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
314 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]315 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]316 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
317 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
318 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
319 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
320 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
321 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
322 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
323 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
324 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
325 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
326 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
327 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
328 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
329 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
330 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
331 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
332 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
333 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
334 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
336 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
337 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
339 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
340 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
341 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
342 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
343 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]344 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
345 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
346 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
347 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]348 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
349 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]350 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
351 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
352 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]353 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
354 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
355 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
356 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
357 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
358 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
359 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
360 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
361 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
362 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
363 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
364 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
365 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
366 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
367 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
368 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
369 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
370 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]371 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]372 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
373 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
374 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]375 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]378 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]379 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]380 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
382 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
383 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
384 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
386 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
387 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]389 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
390 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]391
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]392 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]393 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]394 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]398 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]399
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]400 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]401 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
403 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
404 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
405 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
406 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]408 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]410 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]411 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]412
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]413 // AVX-512 foldable instructions (256-bit versions)
414 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
415 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
416 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
417 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
418 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
423 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]424
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]425 // AVX-512 foldable instructions (128-bit versions)
426 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
427 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
428 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
429 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
430 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
431 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
432 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
433 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
434 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]435 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]436
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]437 // F16C foldable instructions
438 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
439 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]440 };
441
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]442 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]443 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]445 }
446
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]447 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]448 { X86::BSF16rr, X86::BSF16rm, 0 },
449 { X86::BSF32rr, X86::BSF32rm, 0 },
450 { X86::BSF64rr, X86::BSF64rm, 0 },
451 { X86::BSR16rr, X86::BSR16rm, 0 },
452 { X86::BSR32rr, X86::BSR32rm, 0 },
453 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]454 { X86::CMP16rr, X86::CMP16rm, 0 },
455 { X86::CMP32rr, X86::CMP32rm, 0 },
456 { X86::CMP64rr, X86::CMP64rm, 0 },
457 { X86::CMP8rr, X86::CMP8rm, 0 },
458 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
459 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
460 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
461 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
462 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
463 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
464 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
465 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
466 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
467 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]468 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
469 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
470 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
471 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
472 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
473 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
474 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
475 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]476 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
477 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]478 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
479 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Andrey Turetskiycde38b62016-09-01 18:50:02 +0000[diff] [blame]480 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]481 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]482 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]483 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]484 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Andrey Turetskiycde38b62016-09-01 18:50:02 +0000[diff] [blame]485 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]486 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
487 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
488 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
489 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
490 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
491 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
492 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
493 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]494 { X86::MOV16rr, X86::MOV16rm, 0 },
495 { X86::MOV32rr, X86::MOV32rm, 0 },
496 { X86::MOV64rr, X86::MOV64rm, 0 },
497 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
498 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
499 { X86::MOV8rr, X86::MOV8rm, 0 },
500 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
501 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]502 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
503 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
504 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
505 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]506 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
507 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
508 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
509 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
510 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
511 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
512 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
513 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
514 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
515 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]516 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
517 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
518 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
519 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
520 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper8877a022016-08-28 06:06:21 +0000[diff] [blame]521 { X86::PABSBrr, X86::PABSBrm, TB_ALIGN_16 },
522 { X86::PABSDrr, X86::PABSDrm, TB_ALIGN_16 },
523 { X86::PABSWrr, X86::PABSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]524 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
525 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
526 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
527 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
528 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
529 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
530 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
531 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
532 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
533 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
534 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
535 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
536 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
537 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
538 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
539 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
540 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]541 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
542 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
543 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]544 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]545 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]546 { X86::RCPSSr, X86::RCPSSm, 0 },
547 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]548 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
549 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]550 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]551 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
552 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
553 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]554 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]555 { X86::SQRTSDr, X86::SQRTSDm, 0 },
556 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
557 { X86::SQRTSSr, X86::SQRTSSm, 0 },
558 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
559 { X86::TEST16rr, X86::TEST16rm, 0 },
560 { X86::TEST32rr, X86::TEST32rm, 0 },
561 { X86::TEST64rr, X86::TEST64rm, 0 },
562 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]563 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]564 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
565 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]566
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]567 // MMX version of foldable instructions
568 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
569 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
570 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
571 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
572 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
573 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
574 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
575 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
576 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
577 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
578
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]579 // 3DNow! version of foldable instructions
580 { X86::PF2IDrr, X86::PF2IDrm, 0 },
581 { X86::PF2IWrr, X86::PF2IWrm, 0 },
582 { X86::PFRCPrr, X86::PFRCPrm, 0 },
583 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
584 { X86::PI2FDrr, X86::PI2FDrm, 0 },
585 { X86::PI2FWrr, X86::PI2FWrm, 0 },
586 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
587
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]588 // AVX 128-bit versions of foldable instructions
589 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
590 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]591 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
592 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]593 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
594 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]595 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]596 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
597 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
598 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
600 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
601 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
602 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
603 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
604 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]605 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]606 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]607 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]608 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]609 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]610 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]611 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
612 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]613 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
614 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
615 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
616 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
617 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
618 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
619 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
620 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]621 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
622 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]623 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]624 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]625 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper8877a022016-08-28 06:06:21 +0000[diff] [blame]626 { X86::VPABSBrr, X86::VPABSBrm, 0 },
627 { X86::VPABSDrr, X86::VPABSDrm, 0 },
628 { X86::VPABSWrr, X86::VPABSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]629 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
630 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
631 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
632 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
633 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]634 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
635 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]636 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
637 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
638 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
639 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
640 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
641 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
642 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
643 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
644 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
645 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
646 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
647 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]648 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
649 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
650 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]651 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]652 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]653 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
654 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]655 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]656 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]657 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]658 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
659 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]660 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]661 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]662
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]663 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]664 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]665 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]666 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]667 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]668 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]669 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]670 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
671 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]672 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
673 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]674 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]675 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]676 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
677 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]678 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]679 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]680 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
681 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]682 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]683 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]684 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
685 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]686 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
687 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
688 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]689 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
690 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]691
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]692 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]693
694 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]699 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
700 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
701 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper8877a022016-08-28 06:06:21 +0000[diff] [blame]702 { X86::VPABSBYrr, X86::VPABSBYrm, 0 },
703 { X86::VPABSDYrr, X86::VPABSDYrm, 0 },
704 { X86::VPABSWYrr, X86::VPABSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]705 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
706 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
707 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
708 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
709 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
710 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
711 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
712 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
713 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
714 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
715 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
716 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
717 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
718 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
719 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
720 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
721 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
722 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
723 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
724 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
725 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
726 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]727 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
728 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
729 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]730
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]731 // XOP foldable instructions
732 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
733 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
734 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
735 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
736 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
737 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
738 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
739 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
740 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
741 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
742 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
743 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
744 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
745 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
746 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
747 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
748 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
749 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
750 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
751 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
752 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
753 { X86::VPROTBri, X86::VPROTBmi, 0 },
754 { X86::VPROTBrr, X86::VPROTBmr, 0 },
755 { X86::VPROTDri, X86::VPROTDmi, 0 },
756 { X86::VPROTDrr, X86::VPROTDmr, 0 },
757 { X86::VPROTQri, X86::VPROTQmi, 0 },
758 { X86::VPROTQrr, X86::VPROTQmr, 0 },
759 { X86::VPROTWri, X86::VPROTWmi, 0 },
760 { X86::VPROTWrr, X86::VPROTWmr, 0 },
761 { X86::VPSHABrr, X86::VPSHABmr, 0 },
762 { X86::VPSHADrr, X86::VPSHADmr, 0 },
763 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
764 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
765 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
766 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
767 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
768 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
769
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]770 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]771 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
772 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]773 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
774 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
775 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
776 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
777 { X86::BLCI32rr, X86::BLCI32rm, 0 },
778 { X86::BLCI64rr, X86::BLCI64rm, 0 },
779 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
780 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
781 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
782 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
783 { X86::BLCS32rr, X86::BLCS32rm, 0 },
784 { X86::BLCS64rr, X86::BLCS64rm, 0 },
785 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
786 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]787 { X86::BLSI32rr, X86::BLSI32rm, 0 },
788 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]789 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
790 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]791 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
792 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
793 { X86::BLSR32rr, X86::BLSR32rm, 0 },
794 { X86::BLSR64rr, X86::BLSR64rm, 0 },
795 { X86::BZHI32rr, X86::BZHI32rm, 0 },
796 { X86::BZHI64rr, X86::BZHI64rm, 0 },
797 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
798 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
799 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
800 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
801 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
802 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]803 { X86::RORX32ri, X86::RORX32mi, 0 },
804 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]805 { X86::SARX32rr, X86::SARX32rm, 0 },
806 { X86::SARX64rr, X86::SARX64rm, 0 },
807 { X86::SHRX32rr, X86::SHRX32rm, 0 },
808 { X86::SHRX64rr, X86::SHRX64rm, 0 },
809 { X86::SHLX32rr, X86::SHLX32rm, 0 },
810 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]811 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
812 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]813 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
814 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
815 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]816 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
817 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]818
819 // AVX-512 foldable instructions
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]820 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
821 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
822 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
823 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
824 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
825 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
826 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
827 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
828 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
829 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
830 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
831 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
832 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
833 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
834 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
835 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
837 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]838
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]839 // AVX-512 foldable instructions (256-bit versions)
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]840 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
841 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
842 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
843 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
844 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
845 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
846 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
847 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
848 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
849 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
850 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
851 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
852 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
853 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]854
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]855 // AVX-512 foldable instructions (128-bit versions)
856 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
857 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
858 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
859 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
860 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
861 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
862 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
863 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
864 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
865 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
866 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
867 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]868 // F16C foldable instructions
869 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
870 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]871
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]872 // AES foldable instructions
873 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
874 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]875 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
876 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]877 };
878
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]879 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]880 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]881 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]882 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]883 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]884 }
885
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]886 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]887 { X86::ADC32rr, X86::ADC32rm, 0 },
888 { X86::ADC64rr, X86::ADC64rm, 0 },
889 { X86::ADD16rr, X86::ADD16rm, 0 },
890 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
891 { X86::ADD32rr, X86::ADD32rm, 0 },
892 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
893 { X86::ADD64rr, X86::ADD64rm, 0 },
894 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
895 { X86::ADD8rr, X86::ADD8rm, 0 },
896 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
897 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
898 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]899 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]900 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]901 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]902 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
903 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
904 { X86::AND16rr, X86::AND16rm, 0 },
905 { X86::AND32rr, X86::AND32rm, 0 },
906 { X86::AND64rr, X86::AND64rm, 0 },
907 { X86::AND8rr, X86::AND8rm, 0 },
908 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
909 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
910 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
911 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]912 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
913 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
914 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
915 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]916 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
917 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
918 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
919 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
920 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
921 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
922 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
923 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
924 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
925 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
926 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
927 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
928 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
929 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
930 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
931 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
932 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
933 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
934 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
935 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
936 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
937 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
938 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
939 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
940 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
941 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
942 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
943 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
944 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
945 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
946 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
947 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
948 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
949 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
950 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
951 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
952 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
953 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
954 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
955 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
956 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
957 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
958 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
959 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
960 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
961 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
962 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
963 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
964 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
965 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
966 { X86::CMPSDrr, X86::CMPSDrm, 0 },
967 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]968 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
969 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]970 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
971 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
972 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]973 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]974 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]975 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
976 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
977 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]978 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
979 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
980 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
981 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
982 { X86::IMUL16rr, X86::IMUL16rm, 0 },
983 { X86::IMUL32rr, X86::IMUL32rm, 0 },
984 { X86::IMUL64rr, X86::IMUL64rm, 0 },
985 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
986 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]987 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
988 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
989 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
990 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
991 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
992 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]993 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]994 { X86::MAXCPDrr, X86::MAXCPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]995 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]996 { X86::MAXCPSrr, X86::MAXCPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]997 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]998 { X86::MAXCSDrr, X86::MAXCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]999 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1000 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1001 { X86::MAXCSSrr, X86::MAXCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1002 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1003 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1004 { X86::MINCPDrr, X86::MINCPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1005 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1006 { X86::MINCPSrr, X86::MINCPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::MINSDrr, X86::MINSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1008 { X86::MINCSDrr, X86::MINCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1009 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1010 { X86::MINSSrr, X86::MINSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1011 { X86::MINCSSrr, X86::MINCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1012 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1013 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1014 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1015 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1016 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1017 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1018 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1019 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1020 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1021 { X86::OR16rr, X86::OR16rm, 0 },
1022 { X86::OR32rr, X86::OR32rm, 0 },
1023 { X86::OR64rr, X86::OR64rm, 0 },
1024 { X86::OR8rr, X86::OR8rm, 0 },
1025 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1026 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1027 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1028 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1029 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1030 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1031 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1032 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1033 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1034 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1035 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1036 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1037 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1038 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1039 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1040 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1041 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1042 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1043 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1044 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1045 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1046 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1047 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1048 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1049 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1050 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1051 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1052 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1053 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1054 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1055 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1056 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1057 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1058 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1059 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1060 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1061 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1062 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1063 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1064 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1065 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1066 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1067 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1068 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1069 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1070 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1071 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1072 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1073 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1074 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1075 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1076 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1077 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1078 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1079 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1080 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1081 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1082 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1083 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1084 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1085 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1086 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1087 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1088 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1089 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1090 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1091 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1092 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1093 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1094 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1095 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1096 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1097 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1098 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1099 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1100 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1101 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1102 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1103 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1104 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1105 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1106 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1107 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1108 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1109 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1110 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1111 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1112 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1113 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1114 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1115 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1116 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1117 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1118 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]1119 { X86::ROUNDSDr_Int, X86::ROUNDSDm_Int, 0 },
1120 { X86::ROUNDSSr_Int, X86::ROUNDSSm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1121 { X86::SBB32rr, X86::SBB32rm, 0 },
1122 { X86::SBB64rr, X86::SBB64rm, 0 },
1123 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1124 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1125 { X86::SUB16rr, X86::SUB16rm, 0 },
1126 { X86::SUB32rr, X86::SUB32rm, 0 },
1127 { X86::SUB64rr, X86::SUB64rm, 0 },
1128 { X86::SUB8rr, X86::SUB8rm, 0 },
1129 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1130 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1131 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1132 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1133 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1134 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1135 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1136 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1137 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1138 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1139 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1140 { X86::XOR16rr, X86::XOR16rm, 0 },
1141 { X86::XOR32rr, X86::XOR32rm, 0 },
1142 { X86::XOR64rr, X86::XOR64rm, 0 },
1143 { X86::XOR8rr, X86::XOR8rm, 0 },
1144 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1145 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1146
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1147 // MMX version of foldable instructions
1148 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1149 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1150 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1151 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1152 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1153 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1154 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1155 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1156 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1157 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1158 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1159 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1160 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1161 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1162 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1163 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1164 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1165 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1166 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1167 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1168 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1169 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1170 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1171 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1172 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1173 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1174 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1175 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1176 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1177 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1178 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1179 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1180 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1181 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1182 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1183 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1184 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1185 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1186 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1187 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1188 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1189 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1190 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1191 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1192 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1193 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1194 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1195 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1196 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1197 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1198 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1199 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1200 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1201 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1202 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1203 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1204 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1205 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1206 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1207 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1208 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1209 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1210 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1211 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1212 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1213 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1214 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1215 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1216 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1217 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1218
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1219 // 3DNow! version of foldable instructions
1220 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1221 { X86::PFACCrr, X86::PFACCrm, 0 },
1222 { X86::PFADDrr, X86::PFADDrm, 0 },
1223 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1224 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1225 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1226 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1227 { X86::PFMINrr, X86::PFMINrm, 0 },
1228 { X86::PFMULrr, X86::PFMULrm, 0 },
1229 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1230 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1231 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1232 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1233 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1234 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1235 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1236 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1237
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1238 // AVX 128-bit versions of foldable instructions
1239 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1240 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1241 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1242 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1243 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1244 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1245 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1246 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1247 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1248 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1249 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1250 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1251 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1252 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1253 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1254 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1255 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1256 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1257 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1258 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1259 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1260 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1261 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1262 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1263 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1264 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1265 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1266 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1267 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1268 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1269 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1270 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1271 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1272 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1273 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1274 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1275 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1276 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1277 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1278 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1279 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1280 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1281 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1282 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1283 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1284 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1285 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1286 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1287 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1288 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1289 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1290 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1291 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1292 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1293 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1294 { X86::VMAXCPDrr, X86::VMAXCPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1295 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1296 { X86::VMAXCPSrr, X86::VMAXCPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1297 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1298 { X86::VMAXCSDrr, X86::VMAXCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1299 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1300 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1301 { X86::VMAXCSSrr, X86::VMAXCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1302 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1303 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1304 { X86::VMINCPDrr, X86::VMINCPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1305 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1306 { X86::VMINCPSrr, X86::VMINCPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1307 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1308 { X86::VMINCSDrr, X86::VMINCSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1309 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1310 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1311 { X86::VMINCSSrr, X86::VMINCSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1312 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1313 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1314 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1315 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1316 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1317 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1318 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1319 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1320 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1321 { X86::VORPDrr, X86::VORPDrm, 0 },
1322 { X86::VORPSrr, X86::VORPSrm, 0 },
1323 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1324 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1325 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1326 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1327 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1328 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1329 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1330 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1331 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1332 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1333 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1334 { X86::VPADDWrr, X86::VPADDWrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1335 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1336 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1337 { X86::VPANDrr, X86::VPANDrm, 0 },
1338 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1339 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1340 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1341 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1342 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1343 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1344 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1345 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1346 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1347 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1348 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1349 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1350 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1351 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1352 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1353 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1354 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1355 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1356 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1357 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1358 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1359 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1360 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1361 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1362 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1363 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1364 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1365 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1366 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1367 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1368 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1369 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1370 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1371 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1372 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1373 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1374 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1375 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1376 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1377 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1378 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1379 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1380 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1381 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1382 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1383 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1384 { X86::VPORrr, X86::VPORrm, 0 },
1385 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1386 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1387 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1388 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1389 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1390 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1391 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1392 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1393 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1394 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1395 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1396 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1397 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1398 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1399 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1400 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1401 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1402 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1403 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1404 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1405 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1406 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1407 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1408 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1409 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1410 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1411 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1412 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1413 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1414 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1415 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1416 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]1417 { X86::VROUNDSDr_Int, X86::VROUNDSDm_Int, 0 },
1418 { X86::VROUNDSSr_Int, X86::VROUNDSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1419 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1420 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1421 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1422 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1423 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1424 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1425 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1426 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1427 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1428 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1429 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1430 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1431 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1432 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1433
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1434 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1435 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1436 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1437 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1438 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1439 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1440 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1441 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1442 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1443 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1444 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1445 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1446 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1447 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1448 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1449 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1450 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1451 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1452 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1453 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1454 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1455 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1456 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1457 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1458 { X86::VMAXCPDYrr, X86::VMAXCPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1459 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1460 { X86::VMAXCPSYrr, X86::VMAXCPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1461 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1462 { X86::VMINCPDYrr, X86::VMINCPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1463 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Craig Topper49841c32016-08-07 05:39:51 +0000[diff] [blame]1464 { X86::VMINCPSYrr, X86::VMINCPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1465 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1466 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1467 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1468 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1469 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1470 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1471 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1472 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1473 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1474 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1475 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1476 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1477 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1478 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1479 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1480 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1481 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1482
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1483 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1484 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1485 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1486 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1487 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1488 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1489 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1490 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1491 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1492 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1493 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1494 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1495 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1496 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1497 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1498 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1499 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1500 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1501 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1502 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1503 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1504 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1505 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1506 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1507 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1508 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1509 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1510 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1511 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1512 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1513 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1514 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1515 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1516 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1517 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1518 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1519 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1520 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1521 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1522 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1523 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1524 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1525 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1526 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1527 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1528 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1529 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1530 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1531 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1532 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1533 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1534 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1535 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1536 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1537 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1538 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1539 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1540 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1541 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1542 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1543 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1544 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1545 { X86::VPORYrr, X86::VPORYrm, 0 },
1546 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1547 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1548 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1549 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1550 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1551 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1552 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1553 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1554 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1555 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1556 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1557 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1558 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1559 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1560 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1561 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1562 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1563 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1564 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1565 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1566 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1567 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1568 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1569 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1570 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1571 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1572 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1573 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1574 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1575 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1576 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1577 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1578 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1579 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1580 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1581 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1582 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1583 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1584 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1585 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1586
1587 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1588 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1589 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1590 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1591 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1592 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Ymr, TB_ALIGN_NONE },
1593 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1594 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1595 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1596 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1597 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1598 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Ymr, TB_ALIGN_NONE },
1599 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1600 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1601 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1602 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1603 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1604 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Ymr, TB_ALIGN_NONE },
1605 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1606 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1607 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1608 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1609 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1610 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Ymr, TB_ALIGN_NONE },
1611 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1612 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1613 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1614 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Ymr, TB_ALIGN_NONE },
1615 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1616 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1617 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1618 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Ymr, TB_ALIGN_NONE },
1619 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Ymr, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1620
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1621 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1622 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1623 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1624 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1625 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1626 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1627 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1628 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1629 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1630 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1631 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1632 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1633 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1634 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1635 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1636 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1637 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1638 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1639 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1640 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1641 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1642 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1643 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1644 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1645 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1646 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1647 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1648 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1649 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1650 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1651 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1652 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1653 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1654 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1655 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1656 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1657 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1658 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1659 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1660 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1661
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1662 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1663 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1664 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1665 { X86::MULX32rr, X86::MULX32rm, 0 },
1666 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1667 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1668 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1669 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1670 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1671
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1672 // ADX foldable instructions
1673 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1674 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1675 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1676 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1677
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1678 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1679 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1680 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1681 { X86::VADDSSZrr, X86::VADDSSZrm, 0 },
1682 { X86::VADDSSZrr_Int, X86::VADDSSZrm_Int, 0 },
1683 { X86::VADDSDZrr, X86::VADDSDZrm, 0 },
1684 { X86::VADDSDZrr_Int, X86::VADDSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1685 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1686 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1687 { X86::VSUBSSZrr, X86::VSUBSSZrm, 0 },
1688 { X86::VSUBSSZrr_Int, X86::VSUBSSZrm_Int, 0 },
1689 { X86::VSUBSDZrr, X86::VSUBSDZrm, 0 },
1690 { X86::VSUBSDZrr_Int, X86::VSUBSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1691 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1692 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1693 { X86::VMULSSZrr, X86::VMULSSZrm, 0 },
1694 { X86::VMULSSZrr_Int, X86::VMULSSZrm_Int, 0 },
1695 { X86::VMULSDZrr, X86::VMULSDZrm, 0 },
1696 { X86::VMULSDZrr_Int, X86::VMULSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1697 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1698 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1699 { X86::VDIVSSZrr, X86::VDIVSSZrm, 0 },
1700 { X86::VDIVSSZrr_Int, X86::VDIVSSZrm_Int, 0 },
1701 { X86::VDIVSDZrr, X86::VDIVSDZrm, 0 },
1702 { X86::VDIVSDZrr_Int, X86::VDIVSDZrm_Int, 0 },
Craig Topper4891c722016-08-27 05:22:08 +0000[diff] [blame]1703 { X86::VCMPPDZrri, X86::VCMPPDZrmi, 0 },
1704 { X86::VCMPPSZrri, X86::VCMPPSZrmi, 0 },
1705 { X86::VCMPSDZrr, X86::VCMPSDZrm, 0 },
1706 { X86::VCMPSSZrr, X86::VCMPSSZrm, 0 },
Craig Topper8f27f512016-08-26 07:08:00 +0000[diff] [blame]1707 { X86::VCMPSDZrr_Int, X86::VCMPSDZrm_Int, 0 },
1708 { X86::VCMPSSZrr_Int, X86::VCMPSSZrm_Int, 0 },
Craig Topper2c51c742016-08-07 17:14:09 +0000[diff] [blame]1709 { X86::VANDPDZrr, X86::VANDPDZrm, 0 },
1710 { X86::VANDPSZrr, X86::VANDPSZrm, 0 },
1711 { X86::VANDNPDZrr, X86::VANDNPDZrm, 0 },
1712 { X86::VANDNPSZrr, X86::VANDNPSZrm, 0 },
1713 { X86::VORPDZrr, X86::VORPDZrm, 0 },
1714 { X86::VORPSZrr, X86::VORPSZrm, 0 },
1715 { X86::VXORPDZrr, X86::VXORPDZrm, 0 },
1716 { X86::VXORPSZrr, X86::VXORPSZrm, 0 },
1717 { X86::VPANDDZrr, X86::VPANDDZrm, 0 },
1718 { X86::VPANDQZrr, X86::VPANDQZrm, 0 },
1719 { X86::VPANDNDZrr, X86::VPANDNDZrm, 0 },
1720 { X86::VPANDNQZrr, X86::VPANDNQZrm, 0 },
1721 { X86::VPORDZrr, X86::VPORDZrm, 0 },
1722 { X86::VPORQZrr, X86::VPORQZrm, 0 },
1723 { X86::VPXORDZrr, X86::VPXORDZrm, 0 },
1724 { X86::VPXORQZrr, X86::VPXORQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1725 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Craig Topper938e7ab2016-08-07 17:14:05 +0000[diff] [blame]1726 { X86::VMAXCPDZrr, X86::VMAXCPDZrm, 0 },
1727 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1728 { X86::VMAXCPSZrr, X86::VMAXCPSZrm, 0 },
1729 { X86::VMAXSDZrr, X86::VMAXSDZrm, 0 },
1730 { X86::VMAXCSDZrr, X86::VMAXCSDZrm, 0 },
1731 { X86::VMAXSDZrr_Int, X86::VMAXSDZrm_Int, 0 },
1732 { X86::VMAXSSZrr, X86::VMAXSSZrm, 0 },
1733 { X86::VMAXCSSZrr, X86::VMAXCSSZrm, 0 },
1734 { X86::VMAXSSZrr_Int, X86::VMAXSSZrm_Int, 0 },
1735 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1736 { X86::VMINCPDZrr, X86::VMINCPDZrm, 0 },
1737 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1738 { X86::VMINCPSZrr, X86::VMINCPSZrm, 0 },
1739 { X86::VMINSDZrr, X86::VMINSDZrm, 0 },
1740 { X86::VMINCSDZrr, X86::VMINCSDZrm, 0 },
1741 { X86::VMINSDZrr_Int, X86::VMINSDZrm_Int, 0 },
1742 { X86::VMINSSZrr, X86::VMINSSZrm, 0 },
1743 { X86::VMINCSSZrr, X86::VMINCSSZrm, 0 },
1744 { X86::VMINSSZrr_Int, X86::VMINSSZrm_Int, 0 },
Craig Topper907b5802016-09-03 17:20:07 +0000[diff] [blame]1745 { X86::VPADDBZrr, X86::VPADDBZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1746 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1747 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Craig Topper907b5802016-09-03 17:20:07 +0000[diff] [blame]1748 { X86::VPADDSBZrr, X86::VPADDSBZrm, 0 },
1749 { X86::VPADDSWZrr, X86::VPADDSWZrm, 0 },
1750 { X86::VPADDUSBZrr, X86::VPADDUSBZrm, 0 },
1751 { X86::VPADDUSWZrr, X86::VPADDUSWZrm, 0 },
1752 { X86::VPADDWZrr, X86::VPADDWZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1753 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1754 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1755 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1756 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1757 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1758 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1759 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1760 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1761 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1762 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1763 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1764 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1765 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1766 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1767 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1768 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Craig Topper907b5802016-09-03 17:20:07 +0000[diff] [blame]1769 { X86::VPSUBBZrr, X86::VPSUBBZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1770 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1771 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Craig Topper907b5802016-09-03 17:20:07 +0000[diff] [blame]1772 { X86::VPSUBSBZrr, X86::VPSUBSBZrm, 0 },
1773 { X86::VPSUBSWZrr, X86::VPSUBSWZrm, 0 },
1774 { X86::VPSUBUSBZrr, X86::VPSUBUSBZrm, 0 },
1775 { X86::VPSUBUSWZrr, X86::VPSUBUSWZrm, 0 },
1776 { X86::VPSUBWZrr, X86::VPSUBWZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1777 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1778 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1779 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1780 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1781 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1782 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1783 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
Craig Topper892ce562016-09-03 04:37:50 +0000[diff] [blame]1784 { X86::VPCMPEQBZrr, X86::VPCMPEQBZrm, 0 },
1785 { X86::VPCMPEQDZrr, X86::VPCMPEQDZrm, 0 },
1786 { X86::VPCMPEQQZrr, X86::VPCMPEQQZrm, 0 },
1787 { X86::VPCMPEQWZrr, X86::VPCMPEQWZrm, 0 },
1788 { X86::VPCMPGTBZrr, X86::VPCMPGTBZrm, 0 },
1789 { X86::VPCMPGTDZrr, X86::VPCMPGTDZrm, 0 },
1790 { X86::VPCMPGTQZrr, X86::VPCMPGTQZrm, 0 },
1791 { X86::VPCMPGTWZrr, X86::VPCMPGTWZrm, 0 },
Craig Topper149e6bd2016-09-09 01:36:10 +0000[diff] [blame]1792 { X86::VPCMPBZrri, X86::VPCMPBZrmi, 0 },
1793 { X86::VPCMPDZrri, X86::VPCMPDZrmi, 0 },
1794 { X86::VPCMPQZrri, X86::VPCMPQZrmi, 0 },
1795 { X86::VPCMPWZrri, X86::VPCMPWZrmi, 0 },
1796 { X86::VPCMPUBZrri, X86::VPCMPUBZrmi, 0 },
1797 { X86::VPCMPUDZrri, X86::VPCMPUDZrmi, 0 },
1798 { X86::VPCMPUQZrri, X86::VPCMPUQZrmi, 0 },
1799 { X86::VPCMPUWZrri, X86::VPCMPUWZrmi, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1800
1801 // AVX-512{F,VL} foldable instructions
1802 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1803 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1804 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1805
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1806 // AVX-512{F,VL} foldable instructions
1807 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1808 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1809 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1810 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
Craig Topper0b907562016-07-22 05:00:39 +0000[diff] [blame]1811 { X86::VANDPDZ128rr, X86::VANDPDZ128rm, 0 },
1812 { X86::VANDPDZ256rr, X86::VANDPDZ256rm, 0 },
1813 { X86::VANDPSZ128rr, X86::VANDPSZ128rm, 0 },
1814 { X86::VANDPSZ256rr, X86::VANDPSZ256rm, 0 },
1815 { X86::VANDNPDZ128rr, X86::VANDNPDZ128rm, 0 },
1816 { X86::VANDNPDZ256rr, X86::VANDNPDZ256rm, 0 },
1817 { X86::VANDNPSZ128rr, X86::VANDNPSZ128rm, 0 },
1818 { X86::VANDNPSZ256rr, X86::VANDNPSZ256rm, 0 },
1819 { X86::VORPDZ128rr, X86::VORPDZ128rm, 0 },
1820 { X86::VORPDZ256rr, X86::VORPDZ256rm, 0 },
1821 { X86::VORPSZ128rr, X86::VORPSZ128rm, 0 },
1822 { X86::VORPSZ256rr, X86::VORPSZ256rm, 0 },
1823 { X86::VPANDDZ128rr, X86::VPANDDZ128rm, 0 },
1824 { X86::VPANDDZ256rr, X86::VPANDDZ256rm, 0 },
1825 { X86::VPANDQZ128rr, X86::VPANDQZ128rm, 0 },
1826 { X86::VPANDQZ256rr, X86::VPANDQZ256rm, 0 },
1827 { X86::VPANDNDZ128rr, X86::VPANDNDZ128rm, 0 },
1828 { X86::VPANDNDZ256rr, X86::VPANDNDZ256rm, 0 },
1829 { X86::VPANDNQZ128rr, X86::VPANDNQZ128rm, 0 },
1830 { X86::VPANDNQZ256rr, X86::VPANDNQZ256rm, 0 },
1831 { X86::VPORDZ128rr, X86::VPORDZ128rm, 0 },
1832 { X86::VPORDZ256rr, X86::VPORDZ256rm, 0 },
1833 { X86::VPORQZ128rr, X86::VPORQZ128rm, 0 },
1834 { X86::VPORQZ256rr, X86::VPORQZ256rm, 0 },
1835 { X86::VPXORDZ128rr, X86::VPXORDZ128rm, 0 },
1836 { X86::VPXORDZ256rr, X86::VPXORDZ256rm, 0 },
1837 { X86::VPXORQZ128rr, X86::VPXORQZ128rm, 0 },
1838 { X86::VPXORQZ256rr, X86::VPXORQZ256rm, 0 },
1839 { X86::VSUBPDZ128rr, X86::VSUBPDZ128rm, 0 },
1840 { X86::VSUBPDZ256rr, X86::VSUBPDZ256rm, 0 },
1841 { X86::VSUBPSZ128rr, X86::VSUBPSZ128rm, 0 },
1842 { X86::VSUBPSZ256rr, X86::VSUBPSZ256rm, 0 },
1843 { X86::VXORPDZ128rr, X86::VXORPDZ128rm, 0 },
1844 { X86::VXORPDZ256rr, X86::VXORPDZ256rm, 0 },
1845 { X86::VXORPSZ128rr, X86::VXORPSZ128rm, 0 },
1846 { X86::VXORPSZ256rr, X86::VXORPSZ256rm, 0 },
Craig Topper938e7ab2016-08-07 17:14:05 +0000[diff] [blame]1847 { X86::VMAXPDZ128rr, X86::VMAXPDZ128rm, 0 },
1848 { X86::VMAXPDZ256rr, X86::VMAXPDZ256rm, 0 },
1849 { X86::VMAXCPDZ128rr, X86::VMAXCPDZ128rm, 0 },
1850 { X86::VMAXCPDZ256rr, X86::VMAXCPDZ256rm, 0 },
1851 { X86::VMAXPSZ128rr, X86::VMAXPSZ128rm, 0 },
1852 { X86::VMAXPSZ256rr, X86::VMAXPSZ256rm, 0 },
1853 { X86::VMAXCPSZ128rr, X86::VMAXCPSZ128rm, 0 },
1854 { X86::VMAXCPSZ256rr, X86::VMAXCPSZ256rm, 0 },
1855 { X86::VMINPDZ128rr, X86::VMINPDZ128rm, 0 },
1856 { X86::VMINPDZ256rr, X86::VMINPDZ256rm, 0 },
1857 { X86::VMINCPDZ128rr, X86::VMINCPDZ128rm, 0 },
1858 { X86::VMINCPDZ256rr, X86::VMINCPDZ256rm, 0 },
1859 { X86::VMINPSZ128rr, X86::VMINPSZ128rm, 0 },
1860 { X86::VMINPSZ256rr, X86::VMINPSZ256rm, 0 },
1861 { X86::VMINCPSZ128rr, X86::VMINCPSZ128rm, 0 },
1862 { X86::VMINCPSZ256rr, X86::VMINCPSZ256rm, 0 },
Craig Topper4891c722016-08-27 05:22:08 +0000[diff] [blame]1863 { X86::VCMPPDZ128rri, X86::VCMPPDZ128rmi, 0 },
1864 { X86::VCMPPDZ256rri, X86::VCMPPDZ256rmi, 0 },
1865 { X86::VCMPPSZ128rri, X86::VCMPPSZ128rmi, 0 },
1866 { X86::VCMPPSZ256rri, X86::VCMPPSZ256rmi, 0 },
Craig Topper892ce562016-09-03 04:37:50 +0000[diff] [blame]1867 { X86::VPCMPEQBZ128rr, X86::VPCMPEQBZ128rm, 0 },
1868 { X86::VPCMPEQBZ256rr, X86::VPCMPEQBZ256rm, 0 },
1869 { X86::VPCMPEQDZ128rr, X86::VPCMPEQDZ128rm, 0 },
1870 { X86::VPCMPEQDZ256rr, X86::VPCMPEQDZ256rm, 0 },
1871 { X86::VPCMPEQQZ128rr, X86::VPCMPEQQZ128rm, 0 },
1872 { X86::VPCMPEQQZ256rr, X86::VPCMPEQQZ256rm, 0 },
1873 { X86::VPCMPEQWZ128rr, X86::VPCMPEQWZ128rm, 0 },
1874 { X86::VPCMPEQWZ256rr, X86::VPCMPEQWZ256rm, 0 },
1875 { X86::VPCMPGTBZ128rr, X86::VPCMPGTBZ128rm, 0 },
1876 { X86::VPCMPGTBZ256rr, X86::VPCMPGTBZ256rm, 0 },
1877 { X86::VPCMPGTDZ128rr, X86::VPCMPGTDZ128rm, 0 },
1878 { X86::VPCMPGTDZ256rr, X86::VPCMPGTDZ256rm, 0 },
1879 { X86::VPCMPGTQZ128rr, X86::VPCMPGTQZ128rm, 0 },
1880 { X86::VPCMPGTQZ256rr, X86::VPCMPGTQZ256rm, 0 },
1881 { X86::VPCMPGTWZ128rr, X86::VPCMPGTWZ128rm, 0 },
1882 { X86::VPCMPGTWZ256rr, X86::VPCMPGTWZ256rm, 0 },
Craig Topper149e6bd2016-09-09 01:36:10 +0000[diff] [blame]1883 { X86::VPCMPBZ128rri, X86::VPCMPBZ128rmi, 0 },
1884 { X86::VPCMPBZ256rri, X86::VPCMPBZ256rmi, 0 },
1885 { X86::VPCMPDZ128rri, X86::VPCMPDZ128rmi, 0 },
1886 { X86::VPCMPDZ256rri, X86::VPCMPDZ256rmi, 0 },
1887 { X86::VPCMPQZ128rri, X86::VPCMPQZ128rmi, 0 },
1888 { X86::VPCMPQZ256rri, X86::VPCMPQZ256rmi, 0 },
1889 { X86::VPCMPWZ128rri, X86::VPCMPWZ128rmi, 0 },
1890 { X86::VPCMPWZ256rri, X86::VPCMPWZ256rmi, 0 },
1891 { X86::VPCMPUBZ128rri, X86::VPCMPUBZ128rmi, 0 },
1892 { X86::VPCMPUBZ256rri, X86::VPCMPUBZ256rmi, 0 },
1893 { X86::VPCMPUDZ128rri, X86::VPCMPUDZ128rmi, 0 },
1894 { X86::VPCMPUDZ256rri, X86::VPCMPUDZ256rmi, 0 },
1895 { X86::VPCMPUQZ128rri, X86::VPCMPUQZ128rmi, 0 },
1896 { X86::VPCMPUQZ256rri, X86::VPCMPUQZ256rmi, 0 },
1897 { X86::VPCMPUWZ128rri, X86::VPCMPUWZ128rmi, 0 },
1898 { X86::VPCMPUWZ256rri, X86::VPCMPUWZ256rmi, 0 },
Craig Topper907b5802016-09-03 17:20:07 +0000[diff] [blame]1899 { X86::VPADDBZ128rr, X86::VPADDBZ128rm, 0 },
1900 { X86::VPADDBZ256rr, X86::VPADDBZ256rm, 0 },
1901 { X86::VPADDDZ128rr, X86::VPADDDZ128rm, 0 },
1902 { X86::VPADDDZ256rr, X86::VPADDDZ256rm, 0 },
1903 { X86::VPADDQZ128rr, X86::VPADDQZ128rm, 0 },
1904 { X86::VPADDQZ256rr, X86::VPADDQZ256rm, 0 },
1905 { X86::VPADDSBZ128rr, X86::VPADDSBZ128rm, 0 },
1906 { X86::VPADDSBZ256rr, X86::VPADDSBZ256rm, 0 },
1907 { X86::VPADDSWZ128rr, X86::VPADDSWZ128rm, 0 },
1908 { X86::VPADDSWZ256rr, X86::VPADDSWZ256rm, 0 },
1909 { X86::VPADDUSBZ128rr, X86::VPADDUSBZ128rm, 0 },
1910 { X86::VPADDUSBZ256rr, X86::VPADDUSBZ256rm, 0 },
1911 { X86::VPADDUSWZ128rr, X86::VPADDUSWZ128rm, 0 },
1912 { X86::VPADDUSWZ256rr, X86::VPADDUSWZ256rm, 0 },
1913 { X86::VPADDWZ128rr, X86::VPADDWZ128rm, 0 },
1914 { X86::VPADDWZ256rr, X86::VPADDWZ256rm, 0 },
1915 { X86::VPSUBBZ128rr, X86::VPSUBBZ128rm, 0 },
1916 { X86::VPSUBBZ256rr, X86::VPSUBBZ256rm, 0 },
1917 { X86::VPSUBDZ128rr, X86::VPSUBDZ128rm, 0 },
1918 { X86::VPSUBDZ256rr, X86::VPSUBDZ256rm, 0 },
1919 { X86::VPSUBQZ128rr, X86::VPSUBQZ128rm, 0 },
1920 { X86::VPSUBQZ256rr, X86::VPSUBQZ256rm, 0 },
1921 { X86::VPSUBSBZ128rr, X86::VPSUBSBZ128rm, 0 },
1922 { X86::VPSUBSBZ256rr, X86::VPSUBSBZ256rm, 0 },
1923 { X86::VPSUBSWZ128rr, X86::VPSUBSWZ128rm, 0 },
1924 { X86::VPSUBSWZ256rr, X86::VPSUBSWZ256rm, 0 },
1925 { X86::VPSUBUSBZ128rr, X86::VPSUBUSBZ128rm, 0 },
1926 { X86::VPSUBUSBZ256rr, X86::VPSUBUSBZ256rm, 0 },
1927 { X86::VPSUBUSWZ128rr, X86::VPSUBUSWZ128rm, 0 },
1928 { X86::VPSUBUSWZ256rr, X86::VPSUBUSWZ256rm, 0 },
1929 { X86::VPSUBWZ128rr, X86::VPSUBWZ128rm, 0 },
1930 { X86::VPSUBWZ256rr, X86::VPSUBWZ256rm, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1931
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1932 // AES foldable instructions
1933 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1934 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1935 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1936 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1937 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1938 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1939 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1940 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1941
1942 // SHA foldable instructions
1943 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1944 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1945 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1946 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1947 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1948 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1949 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1950 };
1951
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1952 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1953 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1954 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1955 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1956 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1957 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1958
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1959 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1960 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1961 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1962 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1963 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1964 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1965 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Yrm, TB_ALIGN_NONE },
1966 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1967 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1968 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1969 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1970 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1971 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Yrm, TB_ALIGN_NONE },
1972 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1973 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1974 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1975 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1976 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1977 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Yrm, TB_ALIGN_NONE },
1978 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1979 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1980 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1981 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1982 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1983 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Yrm, TB_ALIGN_NONE },
1984 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1985 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1986 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1987 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Yrm, TB_ALIGN_NONE },
1988 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1989 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1990 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1991 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Yrm, TB_ALIGN_NONE },
1992 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1993
1994 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1995 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
1996 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1997 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1998 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1999 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
2000 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]2001 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2002
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2003 // AVX-512 VPERMI instructions with 3 source operands.
2004 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
2005 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
2006 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
2007 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2008 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
2009 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
2010 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]2011 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
2012 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
2013 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
2014 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
2015 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2016 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
2017 // AVX-512 arithmetic instructions
2018 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
2019 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
2020 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
2021 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
2022 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
2023 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
2024 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
2025 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
2026 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
2027 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2028 { X86::VMINCPSZrrkz, X86::VMINCPSZrmkz, 0 },
2029 { X86::VMINCPDZrrkz, X86::VMINCPDZrmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2030 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
2031 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2032 { X86::VMAXCPSZrrkz, X86::VMAXCPSZrmkz, 0 },
2033 { X86::VMAXCPDZrrkz, X86::VMAXCPDZrmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2034 { X86::VANDPDZrrkz, X86::VANDPDZrmkz, 0 },
2035 { X86::VANDPSZrrkz, X86::VANDPSZrmkz, 0 },
2036 { X86::VANDNPDZrrkz, X86::VANDNPDZrmkz, 0 },
2037 { X86::VANDNPSZrrkz, X86::VANDNPSZrmkz, 0 },
2038 { X86::VORPDZrrkz, X86::VORPDZrmkz, 0 },
2039 { X86::VORPSZrrkz, X86::VORPSZrmkz, 0 },
2040 { X86::VXORPDZrrkz, X86::VXORPDZrmkz, 0 },
2041 { X86::VXORPSZrrkz, X86::VXORPSZrmkz, 0 },
2042 { X86::VPANDDZrrkz, X86::VPANDDZrmkz, 0 },
2043 { X86::VPANDQZrrkz, X86::VPANDQZrmkz, 0 },
2044 { X86::VPANDNDZrrkz, X86::VPANDNDZrmkz, 0 },
2045 { X86::VPANDNQZrrkz, X86::VPANDNQZrmkz, 0 },
2046 { X86::VPORDZrrkz, X86::VPORDZrmkz, 0 },
2047 { X86::VPORQZrrkz, X86::VPORQZrmkz, 0 },
2048 { X86::VPXORDZrrkz, X86::VPXORDZrmkz, 0 },
2049 { X86::VPXORQZrrkz, X86::VPXORQZrmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2050 // AVX-512{F,VL} arithmetic instructions 256-bit
2051 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
2052 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
2053 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
2054 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
2055 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
2056 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
2057 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
2058 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
2059 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
2060 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2061 { X86::VMINCPSZ256rrkz, X86::VMINCPSZ256rmkz, 0 },
2062 { X86::VMINCPDZ256rrkz, X86::VMINCPDZ256rmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2063 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
2064 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2065 { X86::VMAXCPSZ256rrkz, X86::VMAXCPSZ256rmkz, 0 },
2066 { X86::VMAXCPDZ256rrkz, X86::VMAXCPDZ256rmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2067 { X86::VANDPDZ256rrkz, X86::VANDPDZ256rmkz, 0 },
2068 { X86::VANDPSZ256rrkz, X86::VANDPSZ256rmkz, 0 },
2069 { X86::VANDNPDZ256rrkz, X86::VANDNPDZ256rmkz, 0 },
2070 { X86::VANDNPSZ256rrkz, X86::VANDNPSZ256rmkz, 0 },
2071 { X86::VORPDZ256rrkz, X86::VORPDZ256rmkz, 0 },
2072 { X86::VORPSZ256rrkz, X86::VORPSZ256rmkz, 0 },
2073 { X86::VXORPDZ256rrkz, X86::VXORPDZ256rmkz, 0 },
2074 { X86::VXORPSZ256rrkz, X86::VXORPSZ256rmkz, 0 },
2075 { X86::VPANDDZ256rrkz, X86::VPANDDZ256rmkz, 0 },
2076 { X86::VPANDQZ256rrkz, X86::VPANDQZ256rmkz, 0 },
2077 { X86::VPANDNDZ256rrkz, X86::VPANDNDZ256rmkz, 0 },
2078 { X86::VPANDNQZ256rrkz, X86::VPANDNQZ256rmkz, 0 },
2079 { X86::VPORDZ256rrkz, X86::VPORDZ256rmkz, 0 },
2080 { X86::VPORQZ256rrkz, X86::VPORQZ256rmkz, 0 },
2081 { X86::VPXORDZ256rrkz, X86::VPXORDZ256rmkz, 0 },
2082 { X86::VPXORQZ256rrkz, X86::VPXORQZ256rmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2083 // AVX-512{F,VL} arithmetic instructions 128-bit
2084 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
2085 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
2086 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
2087 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
2088 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
2089 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
2090 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
2091 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
2092 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
2093 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2094 { X86::VMINCPSZ128rrkz, X86::VMINCPSZ128rmkz, 0 },
2095 { X86::VMINCPDZ128rrkz, X86::VMINCPDZ128rmkz, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2096 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2097 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2098 { X86::VMAXCPSZ128rrkz, X86::VMAXCPSZ128rmkz, 0 },
2099 { X86::VMAXCPDZ128rrkz, X86::VMAXCPDZ128rmkz, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2100 { X86::VANDPDZ128rrkz, X86::VANDPDZ128rmkz, 0 },
2101 { X86::VANDPSZ128rrkz, X86::VANDPSZ128rmkz, 0 },
2102 { X86::VANDNPDZ128rrkz, X86::VANDNPDZ128rmkz, 0 },
2103 { X86::VANDNPSZ128rrkz, X86::VANDNPSZ128rmkz, 0 },
2104 { X86::VORPDZ128rrkz, X86::VORPDZ128rmkz, 0 },
2105 { X86::VORPSZ128rrkz, X86::VORPSZ128rmkz, 0 },
2106 { X86::VXORPDZ128rrkz, X86::VXORPDZ128rmkz, 0 },
2107 { X86::VXORPSZ128rrkz, X86::VXORPSZ128rmkz, 0 },
2108 { X86::VPANDDZ128rrkz, X86::VPANDDZ128rmkz, 0 },
2109 { X86::VPANDQZ128rrkz, X86::VPANDQZ128rmkz, 0 },
2110 { X86::VPANDNDZ128rrkz, X86::VPANDNDZ128rmkz, 0 },
2111 { X86::VPANDNQZ128rrkz, X86::VPANDNQZ128rmkz, 0 },
2112 { X86::VPORDZ128rrkz, X86::VPORDZ128rmkz, 0 },
2113 { X86::VPORQZ128rrkz, X86::VPORQZ128rmkz, 0 },
2114 { X86::VPXORDZ128rrkz, X86::VPXORDZ128rmkz, 0 },
2115 { X86::VPXORQZ128rrkz, X86::VPXORQZ128rmkz, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2116 };
2117
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2118 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2119 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2120 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2121 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2122 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2123 }
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]2124 auto I = X86InstrFMA3Info::rm_begin();
2125 auto E = X86InstrFMA3Info::rm_end();
2126 for (; I != E; ++I)
2127 if (!I.getGroup()->isKMasked())
2128 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2129 I.getRegOpcode(), I.getMemOpcode(),
2130 TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2131
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]2132 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2133 // AVX-512 foldable instructions
2134 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
2135 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
2136 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2137 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2138 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2139 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2140 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2141 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2142 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2143 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2144 { X86::VMINCPSZrrk, X86::VMINCPSZrmk, 0 },
2145 { X86::VMINCPDZrrk, X86::VMINCPDZrmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2146 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2147 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2148 { X86::VMAXCPSZrrk, X86::VMAXCPSZrmk, 0 },
2149 { X86::VMAXCPDZrrk, X86::VMAXCPDZrmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2150 { X86::VANDPDZrrk, X86::VANDPDZrmk, 0 },
2151 { X86::VANDPSZrrk, X86::VANDPSZrmk, 0 },
2152 { X86::VANDNPDZrrk, X86::VANDNPDZrmk, 0 },
2153 { X86::VANDNPSZrrk, X86::VANDNPSZrmk, 0 },
2154 { X86::VORPDZrrk, X86::VORPDZrmk, 0 },
2155 { X86::VORPSZrrk, X86::VORPSZrmk, 0 },
2156 { X86::VXORPDZrrk, X86::VXORPDZrmk, 0 },
2157 { X86::VXORPSZrrk, X86::VXORPSZrmk, 0 },
2158 { X86::VPANDDZrrk, X86::VPANDDZrmk, 0 },
2159 { X86::VPANDQZrrk, X86::VPANDQZrmk, 0 },
2160 { X86::VPANDNDZrrk, X86::VPANDNDZrmk, 0 },
2161 { X86::VPANDNQZrrk, X86::VPANDNQZrmk, 0 },
2162 { X86::VPORDZrrk, X86::VPORDZrmk, 0 },
2163 { X86::VPORQZrrk, X86::VPORQZrmk, 0 },
2164 { X86::VPXORDZrrk, X86::VPXORDZrmk, 0 },
2165 { X86::VPXORQZrrk, X86::VPXORQZrmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2166 // AVX-512{F,VL} foldable instructions 256-bit
2167 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2168 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2169 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2170 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2171 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2172 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2173 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2174 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2175 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2176 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2177 { X86::VMINCPSZ256rrk, X86::VMINCPSZ256rmk, 0 },
2178 { X86::VMINCPDZ256rrk, X86::VMINCPDZ256rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2179 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2180 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2181 { X86::VMAXCPSZ256rrk, X86::VMAXCPSZ256rmk, 0 },
2182 { X86::VMAXCPDZ256rrk, X86::VMAXCPDZ256rmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2183 { X86::VANDPDZ256rrk, X86::VANDPDZ256rmk, 0 },
2184 { X86::VANDPSZ256rrk, X86::VANDPSZ256rmk, 0 },
2185 { X86::VANDNPDZ256rrk, X86::VANDNPDZ256rmk, 0 },
2186 { X86::VANDNPSZ256rrk, X86::VANDNPSZ256rmk, 0 },
2187 { X86::VORPDZ256rrk, X86::VORPDZ256rmk, 0 },
2188 { X86::VORPSZ256rrk, X86::VORPSZ256rmk, 0 },
2189 { X86::VXORPDZ256rrk, X86::VXORPDZ256rmk, 0 },
2190 { X86::VXORPSZ256rrk, X86::VXORPSZ256rmk, 0 },
2191 { X86::VPANDDZ256rrk, X86::VPANDDZ256rmk, 0 },
2192 { X86::VPANDQZ256rrk, X86::VPANDQZ256rmk, 0 },
2193 { X86::VPANDNDZ256rrk, X86::VPANDNDZ256rmk, 0 },
2194 { X86::VPANDNQZ256rrk, X86::VPANDNQZ256rmk, 0 },
2195 { X86::VPORDZ256rrk, X86::VPORDZ256rmk, 0 },
2196 { X86::VPORQZ256rrk, X86::VPORQZ256rmk, 0 },
2197 { X86::VPXORDZ256rrk, X86::VPXORDZ256rmk, 0 },
2198 { X86::VPXORQZ256rrk, X86::VPXORQZ256rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2199 // AVX-512{F,VL} foldable instructions 128-bit
2200 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2201 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2202 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2203 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2204 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2205 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2206 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2207 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2208 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2209 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2210 { X86::VMINCPSZ128rrk, X86::VMINCPSZ128rmk, 0 },
2211 { X86::VMINCPDZ128rrk, X86::VMINCPDZ128rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2212 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2213 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 },
Craig Topperc677e972016-08-14 17:57:19 +0000[diff] [blame]2214 { X86::VMAXCPSZ128rrk, X86::VMAXCPSZ128rmk, 0 },
2215 { X86::VMAXCPDZ128rrk, X86::VMAXCPDZ128rmk, 0 },
Craig Topper29fbdc32016-08-14 17:57:16 +0000[diff] [blame]2216 { X86::VANDPDZ128rrk, X86::VANDPDZ128rmk, 0 },
2217 { X86::VANDPSZ128rrk, X86::VANDPSZ128rmk, 0 },
2218 { X86::VANDNPDZ128rrk, X86::VANDNPDZ128rmk, 0 },
2219 { X86::VANDNPSZ128rrk, X86::VANDNPSZ128rmk, 0 },
2220 { X86::VORPDZ128rrk, X86::VORPDZ128rmk, 0 },
2221 { X86::VORPSZ128rrk, X86::VORPSZ128rmk, 0 },
2222 { X86::VXORPDZ128rrk, X86::VXORPDZ128rmk, 0 },
2223 { X86::VXORPSZ128rrk, X86::VXORPSZ128rmk, 0 },
2224 { X86::VPANDDZ128rrk, X86::VPANDDZ128rmk, 0 },
2225 { X86::VPANDQZ128rrk, X86::VPANDQZ128rmk, 0 },
2226 { X86::VPANDNDZ128rrk, X86::VPANDNDZ128rmk, 0 },
2227 { X86::VPANDNQZ128rrk, X86::VPANDNQZ128rmk, 0 },
2228 { X86::VPORDZ128rrk, X86::VPORDZ128rmk, 0 },
2229 { X86::VPORQZ128rrk, X86::VPORQZ128rmk, 0 },
2230 { X86::VPXORDZ128rrk, X86::VPXORDZ128rmk, 0 },
2231 { X86::VPXORQZ128rrk, X86::VPXORQZ128rmk, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2232 };
2233
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2234 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2235 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2236 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2237 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2238 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2239 }
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]2240 for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I)
2241 if (I.getGroup()->isKMasked())
2242 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2243 I.getRegOpcode(), I.getMemOpcode(),
2244 TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2245}
2246
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2247void
2248X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2249 MemOp2RegOpTableType &M2RTable,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]2250 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
Craig Topper969e56a2016-08-25 04:16:08 +0000[diff] [blame]2251 if ((Flags & TB_NO_FORWARD) == 0) {
2252 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2253 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2254 }
2255 if ((Flags & TB_NO_REVERSE) == 0) {
2256 assert(!M2RTable.count(MemOp) &&
2257 "Duplicated entries in unfolding maps?");
2258 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2259 }
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2260}
2261
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2262bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2263X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2264 unsigned &SrcReg, unsigned &DstReg,
2265 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2266 switch (MI.getOpcode()) {
2267 default: break;
2268 case X86::MOVSX16rr8:
2269 case X86::MOVZX16rr8:
2270 case X86::MOVSX32rr8:
2271 case X86::MOVZX32rr8:
2272 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2273 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2274 // It's not always legal to reference the low 8-bit of the larger
2275 // register in 32-bit mode.
2276 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2277 case X86::MOVSX32rr16:
2278 case X86::MOVZX32rr16:
2279 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2280 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2281 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2282 // Be conservative.
2283 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2284 SrcReg = MI.getOperand(1).getReg();
2285 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2286 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2287 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2288 case X86::MOVSX16rr8:
2289 case X86::MOVZX16rr8:
2290 case X86::MOVSX32rr8:
2291 case X86::MOVZX32rr8:
2292 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2293 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2294 break;
2295 case X86::MOVSX32rr16:
2296 case X86::MOVZX32rr16:
2297 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2298 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2299 break;
2300 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2301 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2302 break;
2303 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2304 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2305 }
2306 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2307 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2308}
2309
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2310int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2311 const MachineFunction *MF = MI.getParent()->getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2312 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2313
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2314 if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2315 MI.getOpcode() == getCallFrameDestroyOpcode()) {
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2316 unsigned StackAlign = TFI->getStackAlignment();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2317 int SPAdj =
2318 (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2319
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2320 SPAdj -= MI.getOperand(1).getImm();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2321
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2322 if (MI.getOpcode() == getCallFrameSetupOpcode())
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2323 return SPAdj;
2324 else
2325 return -SPAdj;
2326 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2327
2328 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2329 // that is bound to the following ADJCALLSTACKUP pseudo.
2330 // Look for the next ADJCALLSTACKUP that follows the call.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2331 if (MI.isCall()) {
2332 const MachineBasicBlock *MBB = MI.getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2333 auto I = ++MachineBasicBlock::const_iterator(MI);
2334 for (auto E = MBB->end(); I != E; ++I) {
2335 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2336 I->isCall())
2337 break;
2338 }
2339
2340 // If we could not find a frame destroy opcode, then it has already
2341 // been simplified, so we don't care.
2342 if (I->getOpcode() != getCallFrameDestroyOpcode())
2343 return 0;
2344
2345 return -(I->getOperand(1).getImm());
2346 }
2347
2348 // Currently handle only PUSHes we can reasonably expect to see
2349 // in call sequences
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2350 switch (MI.getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2351 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2352 return 0;
2353 case X86::PUSH32i8:
2354 case X86::PUSH32r:
2355 case X86::PUSH32rmm:
2356 case X86::PUSH32rmr:
2357 case X86::PUSHi32:
2358 return 4;
David L Kreitzer0fe46322016-05-02 13:45:25 +0000[diff] [blame]2359 case X86::PUSH64i8:
2360 case X86::PUSH64r:
2361 case X86::PUSH64rmm:
2362 case X86::PUSH64rmr:
2363 case X86::PUSH64i32:
2364 return 8;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2365 }
2366}
2367
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2368/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2369/// operand and follow operands form a reference to the stack frame.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2370bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2371 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2372 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2373 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2374 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2375 MI.getOperand(Op + X86::AddrDisp).isImm() &&
2376 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2377 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2378 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2379 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2380 return true;
2381 }
2382 return false;
2383}
2384
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2385static bool isFrameLoadOpcode(int Opcode) {
2386 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2387 default:
2388 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2389 case X86::MOV8rm:
2390 case X86::MOV16rm:
2391 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2392 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2393 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2394 case X86::MOVSSrm:
2395 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2396 case X86::MOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2397 case X86::MOVUPSrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2398 case X86::MOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2399 case X86::MOVUPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2400 case X86::MOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2401 case X86::MOVDQUrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2402 case X86::VMOVSSrm:
2403 case X86::VMOVSDrm:
2404 case X86::VMOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2405 case X86::VMOVUPSrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2406 case X86::VMOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2407 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2408 case X86::VMOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2409 case X86::VMOVDQUrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2410 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2411 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2412 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2413 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2414 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2415 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2416 case X86::MMX_MOVD64rm:
2417 case X86::MMX_MOVQ64rm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2418 case X86::VMOVSSZrm:
2419 case X86::VMOVSDZrm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2420 case X86::VMOVAPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2421 case X86::VMOVAPSZ128rm:
2422 case X86::VMOVAPSZ256rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2423 case X86::VMOVUPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2424 case X86::VMOVUPSZ128rm:
2425 case X86::VMOVUPSZ256rm:
2426 case X86::VMOVAPDZrm:
2427 case X86::VMOVAPDZ128rm:
2428 case X86::VMOVAPDZ256rm:
2429 case X86::VMOVUPDZrm:
2430 case X86::VMOVUPDZ128rm:
2431 case X86::VMOVUPDZ256rm:
2432 case X86::VMOVDQA32Zrm:
2433 case X86::VMOVDQA32Z128rm:
2434 case X86::VMOVDQA32Z256rm:
2435 case X86::VMOVDQU32Zrm:
2436 case X86::VMOVDQU32Z128rm:
2437 case X86::VMOVDQU32Z256rm:
2438 case X86::VMOVDQA64Zrm:
2439 case X86::VMOVDQA64Z128rm:
2440 case X86::VMOVDQA64Z256rm:
2441 case X86::VMOVDQU64Zrm:
2442 case X86::VMOVDQU64Z128rm:
2443 case X86::VMOVDQU64Z256rm:
2444 case X86::VMOVDQU8Zrm:
2445 case X86::VMOVDQU8Z128rm:
2446 case X86::VMOVDQU8Z256rm:
2447 case X86::VMOVDQU16Zrm:
2448 case X86::VMOVDQU16Z128rm:
2449 case X86::VMOVDQU16Z256rm:
2450 case X86::KMOVBkm:
2451 case X86::KMOVWkm:
2452 case X86::KMOVDkm:
2453 case X86::KMOVQkm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2454 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2455 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2456}
2457
2458static bool isFrameStoreOpcode(int Opcode) {
2459 switch (Opcode) {
2460 default: break;
2461 case X86::MOV8mr:
2462 case X86::MOV16mr:
2463 case X86::MOV32mr:
2464 case X86::MOV64mr:
2465 case X86::ST_FpP64m:
2466 case X86::MOVSSmr:
2467 case X86::MOVSDmr:
2468 case X86::MOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2469 case X86::MOVUPSmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2470 case X86::MOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2471 case X86::MOVUPDmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2472 case X86::MOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2473 case X86::MOVDQUmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2474 case X86::VMOVSSmr:
2475 case X86::VMOVSDmr:
2476 case X86::VMOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2477 case X86::VMOVUPSmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2478 case X86::VMOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2479 case X86::VMOVUPDmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2480 case X86::VMOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2481 case X86::VMOVDQUmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2482 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2483 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2484 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2485 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2486 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2487 case X86::VMOVDQAYmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2488 case X86::VMOVSSZmr:
2489 case X86::VMOVSDZmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2490 case X86::VMOVUPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2491 case X86::VMOVUPSZ128mr:
2492 case X86::VMOVUPSZ256mr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2493 case X86::VMOVAPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2494 case X86::VMOVAPSZ128mr:
2495 case X86::VMOVAPSZ256mr:
2496 case X86::VMOVUPDZmr:
2497 case X86::VMOVUPDZ128mr:
2498 case X86::VMOVUPDZ256mr:
2499 case X86::VMOVAPDZmr:
2500 case X86::VMOVAPDZ128mr:
2501 case X86::VMOVAPDZ256mr:
2502 case X86::VMOVDQA32Zmr:
2503 case X86::VMOVDQA32Z128mr:
2504 case X86::VMOVDQA32Z256mr:
2505 case X86::VMOVDQU32Zmr:
2506 case X86::VMOVDQU32Z128mr:
2507 case X86::VMOVDQU32Z256mr:
2508 case X86::VMOVDQA64Zmr:
2509 case X86::VMOVDQA64Z128mr:
2510 case X86::VMOVDQA64Z256mr:
2511 case X86::VMOVDQU64Zmr:
2512 case X86::VMOVDQU64Z128mr:
2513 case X86::VMOVDQU64Z256mr:
2514 case X86::VMOVDQU8Zmr:
2515 case X86::VMOVDQU8Z128mr:
2516 case X86::VMOVDQU8Z256mr:
2517 case X86::VMOVDQU16Zmr:
2518 case X86::VMOVDQU16Z128mr:
2519 case X86::VMOVDQU16Z256mr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2520 case X86::MMX_MOVD64mr:
2521 case X86::MMX_MOVQ64mr:
2522 case X86::MMX_MOVNTQmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2523 case X86::KMOVBmk:
2524 case X86::KMOVWmk:
2525 case X86::KMOVDmk:
2526 case X86::KMOVQmk:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2527 return true;
2528 }
2529 return false;
2530}
2531
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2532unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2533 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2534 if (isFrameLoadOpcode(MI.getOpcode()))
2535 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2536 return MI.getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2537 return 0;
2538}
2539
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2540unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2541 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2542 if (isFrameLoadOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2543 unsigned Reg;
2544 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2545 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2546 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2547 const MachineMemOperand *Dummy;
2548 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2549 }
2550 return 0;
2551}
2552
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2553unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2554 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2555 if (isFrameStoreOpcode(MI.getOpcode()))
2556 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2557 isFrameOperand(MI, 0, FrameIndex))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2558 return MI.getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2559 return 0;
2560}
2561
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2562unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2563 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2564 if (isFrameStoreOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2565 unsigned Reg;
2566 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2567 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2568 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2569 const MachineMemOperand *Dummy;
2570 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2571 }
2572 return 0;
2573}
2574
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2575/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2576static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2577 // Don't waste compile time scanning use-def chains of physregs.
2578 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2579 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2580 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2581 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2582 E = MRI.def_instr_end(); I != E; ++I) {
2583 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2584 if (DefMI->getOpcode() != X86::MOVPC32r)
2585 return false;
2586 assert(!isPICBase && "More than one PIC base?");
2587 isPICBase = true;
2588 }
2589 return isPICBase;
2590}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2591
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2592bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2593 AliasAnalysis *AA) const {
2594 switch (MI.getOpcode()) {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2595 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2596 case X86::MOV8rm:
2597 case X86::MOV16rm:
2598 case X86::MOV32rm:
2599 case X86::MOV64rm:
2600 case X86::LD_Fp64m:
2601 case X86::MOVSSrm:
2602 case X86::MOVSDrm:
2603 case X86::MOVAPSrm:
2604 case X86::MOVUPSrm:
2605 case X86::MOVAPDrm:
2606 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2607 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2608 case X86::VMOVSSrm:
2609 case X86::VMOVSDrm:
2610 case X86::VMOVAPSrm:
2611 case X86::VMOVUPSrm:
2612 case X86::VMOVAPDrm:
2613 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2614 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2615 case X86::VMOVAPSYrm:
2616 case X86::VMOVUPSYrm:
2617 case X86::VMOVAPDYrm:
2618 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2619 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2620 case X86::MMX_MOVD64rm:
2621 case X86::MMX_MOVQ64rm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2622 // AVX-512
Craig Toppere4f868e2016-07-29 06:06:04 +0000[diff] [blame]2623 case X86::VMOVSSZrm:
2624 case X86::VMOVSDZrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2625 case X86::VMOVAPDZ128rm:
2626 case X86::VMOVAPDZ256rm:
2627 case X86::VMOVAPDZrm:
2628 case X86::VMOVAPSZ128rm:
2629 case X86::VMOVAPSZ256rm:
2630 case X86::VMOVAPSZrm:
2631 case X86::VMOVDQA32Z128rm:
2632 case X86::VMOVDQA32Z256rm:
2633 case X86::VMOVDQA32Zrm:
2634 case X86::VMOVDQA64Z128rm:
2635 case X86::VMOVDQA64Z256rm:
2636 case X86::VMOVDQA64Zrm:
2637 case X86::VMOVDQU16Z128rm:
2638 case X86::VMOVDQU16Z256rm:
2639 case X86::VMOVDQU16Zrm:
2640 case X86::VMOVDQU32Z128rm:
2641 case X86::VMOVDQU32Z256rm:
2642 case X86::VMOVDQU32Zrm:
2643 case X86::VMOVDQU64Z128rm:
2644 case X86::VMOVDQU64Z256rm:
2645 case X86::VMOVDQU64Zrm:
2646 case X86::VMOVDQU8Z128rm:
2647 case X86::VMOVDQU8Z256rm:
2648 case X86::VMOVDQU8Zrm:
2649 case X86::VMOVUPSZ128rm:
2650 case X86::VMOVUPSZ256rm:
2651 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2652 // Loads from constant pools are trivially rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2653 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2654 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2655 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2656 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2657 MI.isInvariantLoad(AA)) {
2658 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2659 if (BaseReg == 0 || BaseReg == X86::RIP)
2660 return true;
2661 // Allow re-materialization of PIC load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2662 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2663 return false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2664 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2665 const MachineRegisterInfo &MRI = MF.getRegInfo();
2666 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2667 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2668 return false;
2669 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2670
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2671 case X86::LEA32r:
2672 case X86::LEA64r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2673 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2674 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2675 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2676 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2677 // lea fi#, lea GV, etc. are all rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2678 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2679 return true;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2680 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2681 if (BaseReg == 0)
2682 return true;
2683 // Allow re-materialization of lea PICBase + x.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2684 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2685 const MachineRegisterInfo &MRI = MF.getRegInfo();
2686 return regIsPICBase(BaseReg, MRI);
2687 }
2688 return false;
2689 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2690 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2691
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2692 // All other instructions marked M_REMATERIALIZABLE are always trivially
2693 // rematerializable.
2694 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2695}
2696
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2697bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2698 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2699 MachineBasicBlock::iterator E = MBB.end();
2700
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2701 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2702 // safety after visiting 4 instructions in each direction, we will assume
2703 // it's not safe.
2704 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2705 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2706 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2707 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2708 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2709 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2710 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2711 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2712 continue;
2713 if (MO.getReg() == X86::EFLAGS) {
2714 if (MO.isUse())
2715 return false;
2716 SeenDef = true;
2717 }
2718 }
2719
2720 if (SeenDef)
2721 // This instruction defines EFLAGS, no need to look any further.
2722 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2723 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2724 // Skip over DBG_VALUE.
2725 while (Iter != E && Iter->isDebugValue())
2726 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2727 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2728
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2729 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2730 // live in.
2731 if (Iter == E) {
Craig Topperca66fc52015-12-20 18:41:57 +0000[diff] [blame]2732 for (MachineBasicBlock *S : MBB.successors())
2733 if (S->isLiveIn(X86::EFLAGS))
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2734 return false;
2735 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2736 }
2737
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2738 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2739 Iter = I;
2740 for (unsigned i = 0; i < 4; ++i) {
2741 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2742 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2743 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2744 return !MBB.isLiveIn(X86::EFLAGS);
2745
2746 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2747 // Skip over DBG_VALUE.
2748 while (Iter != B && Iter->isDebugValue())
2749 --Iter;
2750
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2751 bool SawKill = false;
2752 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2753 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2754 // A register mask may clobber EFLAGS, but we should still look for a
2755 // live EFLAGS def.
2756 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2757 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2758 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2759 if (MO.isDef()) return MO.isDead();
2760 if (MO.isKill()) SawKill = true;
2761 }
2762 }
2763
2764 if (SawKill)
2765 // This instruction kills EFLAGS and doesn't redefine it, so
2766 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2767 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2768 }
2769
2770 // Conservative answer.
2771 return false;
2772}
2773
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2774void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2775 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2776 unsigned DestReg, unsigned SubIdx,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2777 const MachineInstr &Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2778 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2779 bool ClobbersEFLAGS = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2780 for (const MachineOperand &MO : Orig.operands()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2781 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2782 ClobbersEFLAGS = true;
2783 break;
2784 }
2785 }
2786
2787 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2788 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2789 // effects.
2790 int Value;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2791 switch (Orig.getOpcode()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2792 case X86::MOV32r0: Value = 0; break;
2793 case X86::MOV32r1: Value = 1; break;
2794 case X86::MOV32r_1: Value = -1; break;
2795 default:
2796 llvm_unreachable("Unexpected instruction!");
2797 }
2798
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2799 const DebugLoc &DL = Orig.getDebugLoc();
2800 BuildMI(MBB, I, DL, get(X86::MOV32ri))
2801 .addOperand(Orig.getOperand(0))
2802 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2803 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2804 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2805 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2806 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2807
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]2808 MachineInstr &NewMI = *std::prev(I);
2809 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2810}
2811
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2812/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2813bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2814 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2815 MachineOperand &MO = MI.getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2816 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2817 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2818 return true;
2819 }
2820 }
2821 return false;
2822}
2823
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2824/// Check whether the shift count for a machine operand is non-zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2825inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2826 unsigned ShiftAmtOperandIdx) {
2827 // The shift count is six bits with the REX.W prefix and five bits without.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2828 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2829 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2830 return Imm & ShiftCountMask;
2831}
2832
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2833/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2834/// can be represented by a LEA instruction.
2835inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2836 // Left shift instructions can be transformed into load-effective-address
2837 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2838 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2839 // The SIB.scale field is two bits wide which means that we can encode any
2840 // shift amount less than 4.
2841 return ShAmt < 4 && ShAmt > 0;
2842}
2843
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2844bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2845 unsigned Opc, bool AllowSP, unsigned &NewSrc,
2846 bool &isKill, bool &isUndef,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]2847 MachineOperand &ImplicitOp,
2848 LiveVariables *LV) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2849 MachineFunction &MF = *MI.getParent()->getParent();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2850 const TargetRegisterClass *RC;
2851 if (AllowSP) {
2852 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2853 } else {
2854 RC = Opc != X86::LEA32r ?
2855 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2856 }
2857 unsigned SrcReg = Src.getReg();
2858
2859 // For both LEA64 and LEA32 the register already has essentially the right
2860 // type (32-bit or 64-bit) we may just need to forbid SP.
2861 if (Opc != X86::LEA64_32r) {
2862 NewSrc = SrcReg;
2863 isKill = Src.isKill();
2864 isUndef = Src.isUndef();
2865
2866 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2867 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2868 return false;
2869
2870 return true;
2871 }
2872
2873 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2874 // another we need to add 64-bit registers to the final MI.
2875 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2876 ImplicitOp = Src;
2877 ImplicitOp.setImplicit();
2878
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]2879 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
Matthias Braunca8210a2016-07-21 00:33:38 +0000[diff] [blame]2880 isKill = Src.isKill();
2881 isUndef = Src.isUndef();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2882 } else {
2883 // Virtual register of the wrong class, we have to create a temporary 64-bit
2884 // vreg to feed into the LEA.
2885 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]2886 MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
2887 get(TargetOpcode::COPY))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2888 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2889 .addOperand(Src);
2890
2891 // Which is obviously going to be dead after we're done with it.
2892 isKill = true;
2893 isUndef = false;
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]2894
2895 if (LV)
2896 LV->replaceKillInstruction(SrcReg, MI, *Copy);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2897 }
2898
2899 // We've set all the parameters without issue.
2900 return true;
2901}
2902
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2903/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2904/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2905/// truncating back down to a 16-bit subregister.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2906MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2907 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2908 LiveVariables *LV) const {
2909 MachineBasicBlock::iterator MBBI = MI.getIterator();
2910 unsigned Dest = MI.getOperand(0).getReg();
2911 unsigned Src = MI.getOperand(1).getReg();
2912 bool isDead = MI.getOperand(0).isDead();
2913 bool isKill = MI.getOperand(1).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2914
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2915 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2916 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2917 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2918 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2919 Opc = X86::LEA64_32r;
2920 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2921 } else {
2922 Opc = X86::LEA32r;
2923 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2924 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2925
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2926 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2927 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2928 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2929 // movw (%rbp,%rcx,2), %dx
2930 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2931 // But testing has shown this *does* help performance in 64-bit mode (at
2932 // least on modern x86 machines).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2933 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2934 MachineInstr *InsMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2935 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2936 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2937 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2938
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2939 MachineInstrBuilder MIB =
2940 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2941 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2942 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2943 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2944 unsigned ShAmt = MI.getOperand(2).getImm();
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2945 MIB.addReg(0).addImm(1ULL << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2946 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2947 break;
2948 }
2949 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2950 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2951 break;
2952 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2953 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2954 break;
2955 case X86::ADD16ri:
2956 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2957 case X86::ADD16ri_DB:
2958 case X86::ADD16ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2959 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2960 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2961 case X86::ADD16rr:
2962 case X86::ADD16rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2963 unsigned Src2 = MI.getOperand(2).getReg();
2964 bool isKill2 = MI.getOperand(2).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2965 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2966 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2967 if (Src == Src2) {
2968 // ADD16rr %reg1028<kill>, %reg1028
2969 // just a single insert_subreg.
2970 addRegReg(MIB, leaInReg, true, leaInReg, false);
2971 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2972 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2973 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2974 else
2975 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2976 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2977 // well be shifting and then extracting the lower 16-bits.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2978 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2979 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2980 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2981 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2982 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2983 }
2984 if (LV && isKill2 && InsMI2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2985 LV->replaceKillInstruction(Src2, MI, *InsMI2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2986 break;
2987 }
2988 }
2989
2990 MachineInstr *NewMI = MIB;
2991 MachineInstr *ExtMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2992 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2993 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2994 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2995
2996 if (LV) {
2997 // Update live variables
2998 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2999 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
3000 if (isKill)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3001 LV->replaceKillInstruction(Src, MI, *InsMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]3002 if (isDead)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3003 LV->replaceKillInstruction(Dest, MI, *ExtMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]3004 }
3005
3006 return ExtMI;
3007}
3008
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3009/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3010/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
3011/// may be able to convert a two-address instruction into a true
3012/// three-address instruction on demand. This allows the X86 target (for
3013/// example) to convert ADD and SHL instructions into LEA instructions if they
3014/// would require register copies due to two-addressness.
3015///
3016/// This method returns a null pointer if the transformation cannot be
3017/// performed, otherwise it returns the new instruction.
3018///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3019MachineInstr *
3020X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3021 MachineInstr &MI, LiveVariables *LV) const {
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3022 // The following opcodes also sets the condition code register(s). Only
3023 // convert them to equivalent lea if the condition code register def's
3024 // are dead!
3025 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3026 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3027
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3028 MachineFunction &MF = *MI.getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3029 // All instructions input are two-addr instructions. Get the known operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3030 const MachineOperand &Dest = MI.getOperand(0);
3031 const MachineOperand &Src = MI.getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3032
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3033 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3034 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3035 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]3036 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3037 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3038 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3039
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3040 unsigned MIOpc = MI.getOpcode();
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]3041 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3042 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]3043 case X86::SHL64ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3044 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3045 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3046 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3047
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3048 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3049 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
3050 !MF.getRegInfo().constrainRegClass(Src.getReg(),
3051 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3052 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3053
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3054 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3055 .addOperand(Dest)
3056 .addReg(0)
3057 .addImm(1ULL << ShAmt)
3058 .addOperand(Src)
3059 .addImm(0)
3060 .addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]3061 break;
3062 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3063 case X86::SHL32ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3064 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3065 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3066 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3067
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]3068 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3069
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3070 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]3071 bool isKill, isUndef;
3072 unsigned SrcReg;
3073 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3074 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3075 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3076 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3077
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3078 MachineInstrBuilder MIB =
3079 BuildMI(MF, MI.getDebugLoc(), get(Opc))
3080 .addOperand(Dest)
3081 .addReg(0)
3082 .addImm(1ULL << ShAmt)
3083 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
3084 .addImm(0)
3085 .addReg(0);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]3086 if (ImplicitOp.getReg() != 0)
3087 MIB.addOperand(ImplicitOp);
3088 NewMI = MIB;
3089
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3090 break;
3091 }
3092 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3093 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3094 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3095 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3096
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]3097 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3098 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3099 : nullptr;
3100 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3101 .addOperand(Dest)
3102 .addReg(0)
3103 .addImm(1ULL << ShAmt)
3104 .addOperand(Src)
3105 .addImm(0)
3106 .addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3107 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]3108 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3109 case X86::INC64r:
3110 case X86::INC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3111 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3112 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
3113 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3114 bool isKill, isUndef;
3115 unsigned SrcReg;
3116 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3117 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3118 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3119 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]3120
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3121 MachineInstrBuilder MIB =
3122 BuildMI(MF, MI.getDebugLoc(), get(Opc))
3123 .addOperand(Dest)
3124 .addReg(SrcReg,
3125 getKillRegState(isKill) | getUndefRegState(isUndef));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3126 if (ImplicitOp.getReg() != 0)
3127 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3128
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3129 NewMI = addOffset(MIB, 1);
3130 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]3131 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3132 case X86::INC16r:
3133 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3134 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3135 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3136 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3137 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3138 .addOperand(Dest)
3139 .addOperand(Src),
3140 1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3141 break;
3142 case X86::DEC64r:
3143 case X86::DEC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3144 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3145 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
3146 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3147
3148 bool isKill, isUndef;
3149 unsigned SrcReg;
3150 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3151 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3152 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3153 return nullptr;
3154
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3155 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3156 .addOperand(Dest)
3157 .addReg(SrcReg, getUndefRegState(isUndef) |
3158 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3159 if (ImplicitOp.getReg() != 0)
3160 MIB.addOperand(ImplicitOp);
3161
3162 NewMI = addOffset(MIB, -1);
3163
3164 break;
3165 }
3166 case X86::DEC16r:
3167 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3168 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3169 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3170 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3171 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3172 .addOperand(Dest)
3173 .addOperand(Src),
3174 -1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3175 break;
3176 case X86::ADD64rr:
3177 case X86::ADD64rr_DB:
3178 case X86::ADD32rr:
3179 case X86::ADD32rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3180 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3181 unsigned Opc;
3182 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3183 Opc = X86::LEA64r;
3184 else
3185 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3186
3187 bool isKill, isUndef;
3188 unsigned SrcReg;
3189 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3190 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3191 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3192 return nullptr;
3193
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3194 const MachineOperand &Src2 = MI.getOperand(2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3195 bool isKill2, isUndef2;
3196 unsigned SrcReg2;
3197 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3198 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3199 SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3200 return nullptr;
3201
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3202 MachineInstrBuilder MIB =
3203 BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3204 if (ImplicitOp.getReg() != 0)
3205 MIB.addOperand(ImplicitOp);
3206 if (ImplicitOp2.getReg() != 0)
3207 MIB.addOperand(ImplicitOp2);
3208
3209 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3210
3211 // Preserve undefness of the operands.
3212 NewMI->getOperand(1).setIsUndef(isUndef);
3213 NewMI->getOperand(3).setIsUndef(isUndef2);
3214
3215 if (LV && Src2.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3216 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3217 break;
3218 }
3219 case X86::ADD16rr:
3220 case X86::ADD16rr_DB: {
3221 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3222 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3223 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3224 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3225 unsigned Src2 = MI.getOperand(2).getReg();
3226 bool isKill2 = MI.getOperand(2).isKill();
3227 NewMI = addRegReg(
3228 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3229 Src.getReg(), Src.isKill(), Src2, isKill2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3230
3231 // Preserve undefness of the operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3232 bool isUndef = MI.getOperand(1).isUndef();
3233 bool isUndef2 = MI.getOperand(2).isUndef();
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3234 NewMI->getOperand(1).setIsUndef(isUndef);
3235 NewMI->getOperand(3).setIsUndef(isUndef2);
3236
3237 if (LV && isKill2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3238 LV->replaceKillInstruction(Src2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3239 break;
3240 }
3241 case X86::ADD64ri32:
3242 case X86::ADD64ri8:
3243 case X86::ADD64ri32_DB:
3244 case X86::ADD64ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3245 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3246 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3247 .addOperand(Dest)
3248 .addOperand(Src),
3249 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3250 break;
3251 case X86::ADD32ri:
3252 case X86::ADD32ri8:
3253 case X86::ADD32ri_DB:
3254 case X86::ADD32ri8_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3255 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3256 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3257
3258 bool isKill, isUndef;
3259 unsigned SrcReg;
3260 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3261 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
Matthias Braun7313ca62016-08-09 01:47:26 +0000[diff] [blame]3262 SrcReg, isKill, isUndef, ImplicitOp, LV))
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3263 return nullptr;
3264
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3265 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3266 .addOperand(Dest)
3267 .addReg(SrcReg, getUndefRegState(isUndef) |
3268 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3269 if (ImplicitOp.getReg() != 0)
3270 MIB.addOperand(ImplicitOp);
3271
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3272 NewMI = addOffset(MIB, MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3273 break;
3274 }
3275 case X86::ADD16ri:
3276 case X86::ADD16ri8:
3277 case X86::ADD16ri_DB:
3278 case X86::ADD16ri8_DB:
3279 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3280 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3281 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3282 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3283 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3284 .addOperand(Dest)
3285 .addOperand(Src),
3286 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3287 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3288 }
3289
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3290 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]3291
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3292 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3293 if (Src.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3294 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3295 if (Dest.isDead())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3296 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3297 }
3298
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3299 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]3300 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3301}
3302
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3303unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3304 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
3305 const X86InstrFMA3Group &FMA3Group) const {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3306
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3307 unsigned Opc = MI.getOpcode();
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3308
3309 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3310 if (SrcOpIdx1 > SrcOpIdx2)
3311 std::swap(SrcOpIdx1, SrcOpIdx2);
3312
3313 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3314 // analysis. The commute optimization is legal only if all users of FMA*_Int
3315 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3316 // not implemented yet. So, just return 0 in that case.
3317 // When such analysis are available this place will be the right place for
3318 // calling it.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3319 if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3320 return 0;
3321
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3322 unsigned FMAOp1 = 1, FMAOp2 = 2, FMAOp3 = 3;
3323 if (FMA3Group.isKMasked()) {
3324 // The k-mask operand cannot be commuted.
3325 if (SrcOpIdx1 == 2)
3326 return 0;
3327
3328 // For k-zero-masked operations it is Ok to commute the first vector
3329 // operand.
3330 // For regular k-masked operations a conservative choice is done as the
3331 // elements of the first vector operand, for which the corresponding bit
3332 // in the k-mask operand is set to 0, are copied to the result of FMA.
3333 // TODO/FIXME: The commute still may be legal if it is known that the
3334 // k-mask operand is set to either all ones or all zeroes.
3335 // It is also Ok to commute the 1st operand if all users of MI use only
3336 // the elements enabled by the k-mask operand. For example,
3337 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
3338 // : v1[i];
3339 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
3340 // // Ok, to commute v1 in FMADD213PSZrk.
3341 if (FMA3Group.isKMergeMasked() && SrcOpIdx1 == FMAOp1)
3342 return 0;
3343 FMAOp2++;
3344 FMAOp3++;
3345 }
3346
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3347 unsigned Case;
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3348 if (SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp2)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3349 Case = 0;
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3350 else if (SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp3)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3351 Case = 1;
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3352 else if (SrcOpIdx1 == FMAOp2 && SrcOpIdx2 == FMAOp3)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3353 Case = 2;
3354 else
3355 return 0;
3356
3357 // Define the FMA forms mapping array that helps to map input FMA form
3358 // to output FMA form to preserve the operation semantics after
3359 // commuting the operands.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3360 const unsigned Form132Index = 0;
3361 const unsigned Form213Index = 1;
3362 const unsigned Form231Index = 2;
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3363 static const unsigned FormMapping[][3] = {
3364 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3365 // FMA132 A, C, b; ==> FMA231 C, A, b;
3366 // FMA213 B, A, c; ==> FMA213 A, B, c;
3367 // FMA231 C, A, b; ==> FMA132 A, C, b;
3368 { Form231Index, Form213Index, Form132Index },
3369 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3370 // FMA132 A, c, B; ==> FMA132 B, c, A;
3371 // FMA213 B, a, C; ==> FMA231 C, a, B;
3372 // FMA231 C, a, B; ==> FMA213 B, a, C;
3373 { Form132Index, Form231Index, Form213Index },
3374 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3375 // FMA132 a, C, B; ==> FMA213 a, B, C;
3376 // FMA213 b, A, C; ==> FMA132 b, C, A;
3377 // FMA231 c, A, B; ==> FMA231 c, B, A;
3378 { Form213Index, Form132Index, Form231Index }
3379 };
3380
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3381 unsigned FMAForms[3];
3382 if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
3383 FMAForms[0] = FMA3Group.getReg132Opcode();
3384 FMAForms[1] = FMA3Group.getReg213Opcode();
3385 FMAForms[2] = FMA3Group.getReg231Opcode();
3386 } else {
3387 FMAForms[0] = FMA3Group.getMem132Opcode();
3388 FMAForms[1] = FMA3Group.getMem213Opcode();
3389 FMAForms[2] = FMA3Group.getMem231Opcode();
3390 }
3391 unsigned FormIndex;
3392 for (FormIndex = 0; FormIndex < 3; FormIndex++)
3393 if (Opc == FMAForms[FormIndex])
3394 break;
3395
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3396 // Everything is ready, just adjust the FMA opcode and return it.
3397 FormIndex = FormMapping[Case][FormIndex];
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3398 return FMAForms[FormIndex];
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3399}
3400
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3401MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3402 unsigned OpIdx1,
3403 unsigned OpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3404 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3405 if (NewMI)
3406 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3407 return MI;
3408 };
3409
3410 switch (MI.getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3411 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3412 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3413 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3414 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3415 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3416 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3417 unsigned Opc;
3418 unsigned Size;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3419 switch (MI.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3420 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3421 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3422 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3423 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3424 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3425 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3426 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3427 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3428 unsigned Amt = MI.getOperand(3).getImm();
3429 auto &WorkingMI = cloneIfNew(MI);
3430 WorkingMI.setDesc(get(Opc));
3431 WorkingMI.getOperand(3).setImm(Size - Amt);
3432 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3433 OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3434 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3435 case X86::BLENDPDrri:
3436 case X86::BLENDPSrri:
3437 case X86::PBLENDWrri:
3438 case X86::VBLENDPDrri:
3439 case X86::VBLENDPSrri:
3440 case X86::VBLENDPDYrri:
3441 case X86::VBLENDPSYrri:
3442 case X86::VPBLENDDrri:
3443 case X86::VPBLENDWrri:
3444 case X86::VPBLENDDYrri:
3445 case X86::VPBLENDWYrri:{
3446 unsigned Mask;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3447 switch (MI.getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3448 default: llvm_unreachable("Unreachable!");
3449 case X86::BLENDPDrri: Mask = 0x03; break;
3450 case X86::BLENDPSrri: Mask = 0x0F; break;
3451 case X86::PBLENDWrri: Mask = 0xFF; break;
3452 case X86::VBLENDPDrri: Mask = 0x03; break;
3453 case X86::VBLENDPSrri: Mask = 0x0F; break;
3454 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3455 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3456 case X86::VPBLENDDrri: Mask = 0x0F; break;
3457 case X86::VPBLENDWrri: Mask = 0xFF; break;
3458 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3459 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3460 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3461 // Only the least significant bits of Imm are used.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3462 unsigned Imm = MI.getOperand(3).getImm() & Mask;
3463 auto &WorkingMI = cloneIfNew(MI);
3464 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3465 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3466 OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3467 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3468 case X86::PCLMULQDQrr:
3469 case X86::VPCLMULQDQrr:{
3470 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3471 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3472 unsigned Imm = MI.getOperand(3).getImm();
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3473 unsigned Src1Hi = Imm & 0x01;
3474 unsigned Src2Hi = Imm & 0x10;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3475 auto &WorkingMI = cloneIfNew(MI);
3476 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3477 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3478 OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3479 }
Craig Topper144fdef2016-08-27 05:22:12 +0000[diff] [blame]3480 case X86::CMPSDrr:
3481 case X86::CMPSSrr:
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3482 case X86::CMPPDrri:
3483 case X86::CMPPSrri:
Craig Topper144fdef2016-08-27 05:22:12 +0000[diff] [blame]3484 case X86::VCMPSDrr:
3485 case X86::VCMPSSrr:
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3486 case X86::VCMPPDrri:
3487 case X86::VCMPPSrri:
3488 case X86::VCMPPDYrri:
Craig Topper225da2c2016-08-27 05:22:15 +0000[diff] [blame]3489 case X86::VCMPPSYrri:
3490 case X86::VCMPSDZrr:
3491 case X86::VCMPSSZrr:
3492 case X86::VCMPPDZrri:
3493 case X86::VCMPPSZrri:
3494 case X86::VCMPPDZ128rri:
3495 case X86::VCMPPSZ128rri:
3496 case X86::VCMPPDZ256rri:
3497 case X86::VCMPPSZ256rri: {
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3498 // Float comparison can be safely commuted for
3499 // Ordered/Unordered/Equal/NotEqual tests
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3500 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3501 switch (Imm) {
3502 case 0x00: // EQUAL
3503 case 0x03: // UNORDERED
3504 case 0x04: // NOT EQUAL
3505 case 0x07: // ORDERED
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3506 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3507 default:
3508 return nullptr;
3509 }
3510 }
Craig Topper149e6bd2016-09-09 01:36:10 +0000[diff] [blame]3511 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
3512 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
3513 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
3514 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
3515 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
3516 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
3517 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
3518 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
3519 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
3520 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
3521 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
3522 case X86::VPCMPWZrri: case X86::VPCMPUWZrri: {
3523 // Flip comparison mode immediate (if necessary).
3524 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3525 switch (Imm) {
3526 default: llvm_unreachable("Unreachable!");
3527 case 0x01: Imm = 0x06; break; // LT -> NLE
3528 case 0x02: Imm = 0x05; break; // LE -> NLT
3529 case 0x05: Imm = 0x02; break; // NLT -> LE
3530 case 0x06: Imm = 0x01; break; // NLE -> LT
3531 case 0x00: // EQ
3532 case 0x03: // FALSE
3533 case 0x04: // NE
3534 case 0x07: // TRUE
3535 break;
3536 }
3537 auto &WorkingMI = cloneIfNew(MI);
3538 WorkingMI.getOperand(3).setImm(Imm);
3539 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3540 OpIdx1, OpIdx2);
3541 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3542 case X86::VPCOMBri: case X86::VPCOMUBri:
3543 case X86::VPCOMDri: case X86::VPCOMUDri:
3544 case X86::VPCOMQri: case X86::VPCOMUQri:
3545 case X86::VPCOMWri: case X86::VPCOMUWri: {
3546 // Flip comparison mode immediate (if necessary).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3547 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3548 switch (Imm) {
Craig Topper149e6bd2016-09-09 01:36:10 +0000[diff] [blame]3549 default: llvm_unreachable("Unreachable!");
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3550 case 0x00: Imm = 0x02; break; // LT -> GT
3551 case 0x01: Imm = 0x03; break; // LE -> GE
3552 case 0x02: Imm = 0x00; break; // GT -> LT
3553 case 0x03: Imm = 0x01; break; // GE -> LE
3554 case 0x04: // EQ
3555 case 0x05: // NE
3556 case 0x06: // FALSE
3557 case 0x07: // TRUE
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3558 break;
3559 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3560 auto &WorkingMI = cloneIfNew(MI);
3561 WorkingMI.getOperand(3).setImm(Imm);
3562 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3563 OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3564 }
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3565 case X86::VPERM2F128rr:
3566 case X86::VPERM2I128rr: {
3567 // Flip permute source immediate.
3568 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3569 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3570 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3571 auto &WorkingMI = cloneIfNew(MI);
3572 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3573 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3574 OpIdx1, OpIdx2);
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3575 }
Simon Pilgrim7d168e12016-08-06 18:40:28 +0000[diff] [blame]3576 case X86::MOVHLPSrr:
3577 case X86::UNPCKHPDrr: {
3578 if (!Subtarget.hasSSE2())
3579 return nullptr;
3580
3581 unsigned Opc = MI.getOpcode();
3582 switch (Opc) {
3583 default: llvm_unreachable("Unreachable!");
3584 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
3585 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
3586 }
3587 auto &WorkingMI = cloneIfNew(MI);
3588 WorkingMI.setDesc(get(Opc));
3589 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3590 OpIdx1, OpIdx2);
3591 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3592 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3593 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3594 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3595 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3596 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3597 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3598 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3599 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3600 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3601 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3602 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3603 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3604 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3605 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3606 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3607 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3608 unsigned Opc;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3609 switch (MI.getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3610 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3611 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3612 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3613 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3614 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3615 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3616 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3617 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3618 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3619 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3620 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3621 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3622 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3623 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3624 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3625 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3626 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3627 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3628 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3629 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3630 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3631 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3632 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3633 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3634 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3635 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3636 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3637 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3638 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3639 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3640 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3641 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3642 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3643 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3644 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3645 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3646 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3647 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3648 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3649 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3650 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3651 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3652 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3653 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3654 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3655 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3656 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3657 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3658 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3659 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3660 auto &WorkingMI = cloneIfNew(MI);
3661 WorkingMI.setDesc(get(Opc));
3662 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3663 OpIdx1, OpIdx2);
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3664 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3665 default:
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3666 const X86InstrFMA3Group *FMA3Group =
3667 X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
3668 if (FMA3Group) {
3669 unsigned Opc =
3670 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3671 if (Opc == 0)
3672 return nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3673 auto &WorkingMI = cloneIfNew(MI);
3674 WorkingMI.setDesc(get(Opc));
3675 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3676 OpIdx1, OpIdx2);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3677 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3678
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3679 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3680 }
3681}
3682
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3683bool X86InstrInfo::findFMA3CommutedOpIndices(
3684 const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
3685 const X86InstrFMA3Group &FMA3Group) const {
3686 unsigned FirstCommutableVecOp = 1;
3687 unsigned LastCommutableVecOp = 3;
3688 unsigned KMaskOp = 0;
3689 if (FMA3Group.isKMasked()) {
3690 // The k-mask operand has index = 2 for masked and zero-masked operations.
3691 KMaskOp = 2;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3692
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3693 // The operand with index = 1 is used as a source for those elements for
3694 // which the corresponding bit in the k-mask is set to 0.
3695 if (FMA3Group.isKMergeMasked())
3696 FirstCommutableVecOp = 3;
3697
3698 LastCommutableVecOp++;
3699 }
3700
3701 if (isMem(MI, LastCommutableVecOp))
3702 LastCommutableVecOp--;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3703
3704 // Only the first RegOpsNum operands are commutable.
3705 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3706 // that the operand is not specified/fixed.
3707 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3708 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
3709 SrcOpIdx1 == KMaskOp))
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3710 return false;
3711 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3712 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
3713 SrcOpIdx2 == KMaskOp))
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3714 return false;
3715
3716 // Look for two different register operands assumed to be commutable
3717 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3718 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3719 SrcOpIdx2 == CommuteAnyOperandIndex) {
3720 unsigned CommutableOpIdx1 = SrcOpIdx1;
3721 unsigned CommutableOpIdx2 = SrcOpIdx2;
3722
3723 // At least one of operands to be commuted is not specified and
3724 // this method is free to choose appropriate commutable operands.
3725 if (SrcOpIdx1 == SrcOpIdx2)
3726 // Both of operands are not fixed. By default set one of commutable
3727 // operands to the last register operand of the instruction.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3728 CommutableOpIdx2 = LastCommutableVecOp;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3729 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3730 // Only one of operands is not fixed.
3731 CommutableOpIdx2 = SrcOpIdx1;
3732
3733 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3734 // operand and assign its index to CommutableOpIdx1.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3735 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3736 for (CommutableOpIdx1 = LastCommutableVecOp;
3737 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
3738 // Just ignore and skip the k-mask operand.
3739 if (CommutableOpIdx1 == KMaskOp)
3740 continue;
3741
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3742 // The commuted operands must have different registers.
3743 // Otherwise, the commute transformation does not change anything and
3744 // is useless then.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3745 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3746 break;
3747 }
3748
3749 // No appropriate commutable operands were found.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3750 if (CommutableOpIdx1 < FirstCommutableVecOp)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3751 return false;
3752
3753 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3754 // to return those values.
3755 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3756 CommutableOpIdx1, CommutableOpIdx2))
3757 return false;
3758 }
3759
3760 // Check if we can adjust the opcode to preserve the semantics when
3761 // commute the register operands.
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3762 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3763}
3764
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3765bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3766 unsigned &SrcOpIdx2) const {
Craig Topperb880ad32016-09-07 04:46:11 +0000[diff] [blame]3767 const MCInstrDesc &Desc = MI.getDesc();
3768 if (!Desc.isCommutable())
Craig Topper8c372a32016-08-13 06:48:44 +0000[diff] [blame]3769 return false;
3770
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3771 switch (MI.getOpcode()) {
Craig Topper144fdef2016-08-27 05:22:12 +0000[diff] [blame]3772 case X86::CMPSDrr:
3773 case X86::CMPSSrr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3774 case X86::CMPPDrri:
3775 case X86::CMPPSrri:
Craig Topper144fdef2016-08-27 05:22:12 +0000[diff] [blame]3776 case X86::VCMPSDrr:
3777 case X86::VCMPSSrr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3778 case X86::VCMPPDrri:
3779 case X86::VCMPPSrri:
3780 case X86::VCMPPDYrri:
Craig Topper225da2c2016-08-27 05:22:15 +0000[diff] [blame]3781 case X86::VCMPPSYrri:
3782 case X86::VCMPSDZrr:
3783 case X86::VCMPSSZrr:
3784 case X86::VCMPPDZrri:
3785 case X86::VCMPPSZrri:
3786 case X86::VCMPPDZ128rri:
3787 case X86::VCMPPSZ128rri:
3788 case X86::VCMPPDZ256rri:
3789 case X86::VCMPPSZ256rri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3790 // Float comparison can be safely commuted for
3791 // Ordered/Unordered/Equal/NotEqual tests
3792 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3793 switch (Imm) {
3794 case 0x00: // EQUAL
3795 case 0x03: // UNORDERED
3796 case 0x04: // NOT EQUAL
3797 case 0x07: // ORDERED
3798 // The indices of the commutable operands are 1 and 2.
3799 // Assign them to the returned operand indices here.
3800 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3801 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3802 return false;
3803 }
3804 default:
Vyacheslav Klochkov6daefcf2016-08-11 22:07:33 +0000[diff] [blame]3805 const X86InstrFMA3Group *FMA3Group =
3806 X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
3807 if (FMA3Group)
3808 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
Craig Topperb880ad32016-09-07 04:46:11 +0000[diff] [blame]3809
3810 // Handled masked instructions since we need to skip over the mask input
3811 // and the preserved input.
3812 if (Desc.TSFlags & X86II::EVEX_K) {
3813 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
3814 // If there is no preserved input we only need to skip 1 operand.
3815 if (MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
3816 MCOI::TIED_TO) != -1)
3817 ++CommutableOpIdx1;
3818 unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
3819 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3820 CommutableOpIdx1, CommutableOpIdx2))
3821 return false;
3822
3823 if (!MI.getOperand(SrcOpIdx1).isReg() ||
3824 !MI.getOperand(SrcOpIdx2).isReg())
3825 // No idea.
3826 return false;
3827 return true;
3828 }
3829
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3830 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3831 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3832 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3833}
3834
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3835static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3836 switch (BrOpc) {
3837 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3838 case X86::JE_1: return X86::COND_E;
3839 case X86::JNE_1: return X86::COND_NE;
3840 case X86::JL_1: return X86::COND_L;
3841 case X86::JLE_1: return X86::COND_LE;
3842 case X86::JG_1: return X86::COND_G;
3843 case X86::JGE_1: return X86::COND_GE;
3844 case X86::JB_1: return X86::COND_B;
3845 case X86::JBE_1: return X86::COND_BE;
3846 case X86::JA_1: return X86::COND_A;
3847 case X86::JAE_1: return X86::COND_AE;
3848 case X86::JS_1: return X86::COND_S;
3849 case X86::JNS_1: return X86::COND_NS;
3850 case X86::JP_1: return X86::COND_P;
3851 case X86::JNP_1: return X86::COND_NP;
3852 case X86::JO_1: return X86::COND_O;
3853 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3854 }
3855}
3856
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3857/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3858static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3859 switch (Opc) {
3860 default: return X86::COND_INVALID;
3861 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3862 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3863 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3864 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3865 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3866 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3867 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3868 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3869 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3870 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3871 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3872 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3873 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3874 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3875 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3876 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3877 }
3878}
3879
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3880/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3881X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3882 switch (Opc) {
3883 default: return X86::COND_INVALID;
3884 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3885 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3886 return X86::COND_A;
3887 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3888 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3889 return X86::COND_AE;
3890 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3891 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3892 return X86::COND_B;
3893 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3894 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3895 return X86::COND_BE;
3896 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3897 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3898 return X86::COND_E;
3899 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3900 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3901 return X86::COND_G;
3902 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3903 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3904 return X86::COND_GE;
3905 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3906 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3907 return X86::COND_L;
3908 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3909 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3910 return X86::COND_LE;
3911 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3912 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3913 return X86::COND_NE;
3914 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3915 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3916 return X86::COND_NO;
3917 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3918 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3919 return X86::COND_NP;
3920 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3921 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3922 return X86::COND_NS;
3923 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3924 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3925 return X86::COND_O;
3926 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3927 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3928 return X86::COND_P;
3929 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3930 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3931 return X86::COND_S;
3932 }
3933}
3934
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3935unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3936 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3937 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3938 case X86::COND_E: return X86::JE_1;
3939 case X86::COND_NE: return X86::JNE_1;
3940 case X86::COND_L: return X86::JL_1;
3941 case X86::COND_LE: return X86::JLE_1;
3942 case X86::COND_G: return X86::JG_1;
3943 case X86::COND_GE: return X86::JGE_1;
3944 case X86::COND_B: return X86::JB_1;
3945 case X86::COND_BE: return X86::JBE_1;
3946 case X86::COND_A: return X86::JA_1;
3947 case X86::COND_AE: return X86::JAE_1;
3948 case X86::COND_S: return X86::JS_1;
3949 case X86::COND_NS: return X86::JNS_1;
3950 case X86::COND_P: return X86::JP_1;
3951 case X86::COND_NP: return X86::JNP_1;
3952 case X86::COND_O: return X86::JO_1;
3953 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3954 }
3955}
3956
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3957/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3958/// e.g. turning COND_E to COND_NE.
3959X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3960 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3961 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3962 case X86::COND_E: return X86::COND_NE;
3963 case X86::COND_NE: return X86::COND_E;
3964 case X86::COND_L: return X86::COND_GE;
3965 case X86::COND_LE: return X86::COND_G;
3966 case X86::COND_G: return X86::COND_LE;
3967 case X86::COND_GE: return X86::COND_L;
3968 case X86::COND_B: return X86::COND_AE;
3969 case X86::COND_BE: return X86::COND_A;
3970 case X86::COND_A: return X86::COND_BE;
3971 case X86::COND_AE: return X86::COND_B;
3972 case X86::COND_S: return X86::COND_NS;
3973 case X86::COND_NS: return X86::COND_S;
3974 case X86::COND_P: return X86::COND_NP;
3975 case X86::COND_NP: return X86::COND_P;
3976 case X86::COND_O: return X86::COND_NO;
3977 case X86::COND_NO: return X86::COND_O;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3978 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
3979 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3980 }
3981}
3982
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3983/// Assuming the flags are set by MI(a,b), return the condition code if we
3984/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3985static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3986 switch (CC) {
3987 default: return X86::COND_INVALID;
3988 case X86::COND_E: return X86::COND_E;
3989 case X86::COND_NE: return X86::COND_NE;
3990 case X86::COND_L: return X86::COND_G;
3991 case X86::COND_LE: return X86::COND_GE;
3992 case X86::COND_G: return X86::COND_L;
3993 case X86::COND_GE: return X86::COND_LE;
3994 case X86::COND_B: return X86::COND_A;
3995 case X86::COND_BE: return X86::COND_AE;
3996 case X86::COND_A: return X86::COND_B;
3997 case X86::COND_AE: return X86::COND_BE;
3998 }
3999}
4000
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4001/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4002/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]4003unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]4004 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4005 { X86::SETAr, X86::SETAm },
4006 { X86::SETAEr, X86::SETAEm },
4007 { X86::SETBr, X86::SETBm },
4008 { X86::SETBEr, X86::SETBEm },
4009 { X86::SETEr, X86::SETEm },
4010 { X86::SETGr, X86::SETGm },
4011 { X86::SETGEr, X86::SETGEm },
4012 { X86::SETLr, X86::SETLm },
4013 { X86::SETLEr, X86::SETLEm },
4014 { X86::SETNEr, X86::SETNEm },
4015 { X86::SETNOr, X86::SETNOm },
4016 { X86::SETNPr, X86::SETNPm },
4017 { X86::SETNSr, X86::SETNSm },
4018 { X86::SETOr, X86::SETOm },
4019 { X86::SETPr, X86::SETPm },
4020 { X86::SETSr, X86::SETSm }
4021 };
4022
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]4023 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4024 return Opc[CC][HasMemoryOperand ? 1 : 0];
4025}
4026
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4027/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4028/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]4029unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
4030 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]4031 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4032 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
4033 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
4034 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
4035 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
4036 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
4037 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
4038 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
4039 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
4040 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
4041 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
4042 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
4043 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
4044 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
4045 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
4046 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4047 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
4048 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
4049 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
4050 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
4051 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
4052 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
4053 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
4054 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
4055 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
4056 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
4057 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
4058 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
4059 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
4060 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
4061 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
4062 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
4063 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4064 };
4065
4066 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4067 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4068 switch(RegBytes) {
4069 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4070 case 2: return Opc[Idx][0];
4071 case 4: return Opc[Idx][1];
4072 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4073 }
4074}
4075
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4076bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4077 if (!MI.isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4078
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4079 // Conditional branch is a special case.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4080 if (MI.isBranch() && !MI.isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4081 return true;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4082 if (!MI.isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4083 return true;
4084 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]4085}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4086
Hans Wennborg75e25f62016-09-07 17:52:14 +0000[diff] [blame]4087bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
4088 switch (MI.getOpcode()) {
4089 case X86::TCRETURNdi:
4090 case X86::TCRETURNri:
4091 case X86::TCRETURNmi:
4092 case X86::TCRETURNdi64:
4093 case X86::TCRETURNri64:
4094 case X86::TCRETURNmi64:
4095 return true;
4096 default:
4097 return false;
4098 }
4099}
4100
4101bool X86InstrInfo::canMakeTailCallConditional(
4102 SmallVectorImpl<MachineOperand> &BranchCond,
4103 const MachineInstr &TailCall) const {
4104 if (TailCall.getOpcode() != X86::TCRETURNdi) {
4105 // Only direct calls can be done with a conditional branch.
4106 return false;
4107 }
4108
4109 assert(BranchCond.size() == 1);
4110 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
4111 // Can't make a conditional tail call with this condition.
4112 return false;
4113 }
4114
4115 const X86MachineFunctionInfo *X86FI =
4116 TailCall.getParent()->getParent()->getInfo<X86MachineFunctionInfo>();
4117 if (X86FI->getTCReturnAddrDelta() != 0 ||
4118 TailCall.getOperand(1).getImm() != 0) {
4119 // A conditional tail call cannot do any stack adjustment.
4120 return false;
4121 }
4122
4123 return true;
4124}
4125
4126void X86InstrInfo::replaceBranchWithTailCall(
4127 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
4128 const MachineInstr &TailCall) const {
4129 assert(canMakeTailCallConditional(BranchCond, TailCall));
4130
4131 MachineBasicBlock::iterator I = MBB.end();
4132 while (I != MBB.begin()) {
4133 --I;
4134 if (I->isDebugValue())
4135 continue;
4136 if (!I->isBranch())
4137 assert(0 && "Can't find the branch to replace!");
4138
4139 X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
4140 assert(BranchCond.size() == 1);
4141 if (CC != BranchCond[0].getImm())
4142 continue;
4143
4144 break;
4145 }
4146
4147 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(X86::TCRETURNdicc));
4148 MIB->addOperand(TailCall.getOperand(0)); // Destination.
4149 MIB.addImm(0); // Stack offset (not used).
4150 MIB->addOperand(BranchCond[0]); // Condition.
4151 MIB->addOperand(TailCall.getOperand(2)); // Regmask.
4152
4153 I->eraseFromParent();
4154}
4155
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4156// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
4157// not be a fallthrough MBB now due to layout changes). Return nullptr if the
4158// fallthrough MBB cannot be identified.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4159static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
4160 MachineBasicBlock *TBB) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4161 // Look for non-EHPad successors other than TBB. If we find exactly one, it
4162 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
4163 // and fallthrough MBB. If we find more than one, we cannot identify the
4164 // fallthrough MBB and should return nullptr.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4165 MachineBasicBlock *FallthroughBB = nullptr;
4166 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4167 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4168 continue;
4169 // Return a nullptr if we found more than one fallthrough successor.
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4170 if (FallthroughBB && FallthroughBB != TBB)
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4171 return nullptr;
4172 FallthroughBB = *SI;
4173 }
4174 return FallthroughBB;
4175}
4176
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4177bool X86InstrInfo::AnalyzeBranchImpl(
4178 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
4179 SmallVectorImpl<MachineOperand> &Cond,
4180 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
4181
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4182 // Start from the bottom of the block and work up, examining the
4183 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4184 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4185 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4186 while (I != MBB.begin()) {
4187 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4188 if (I->isDebugValue())
4189 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4190
4191 // Working from the bottom, when we see a non-terminator instruction, we're
4192 // done.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4193 if (!isUnpredicatedTerminator(*I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4194 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4195
4196 // A terminator that isn't a branch can't easily be handled by this
4197 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]4198 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4199 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4200
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4201 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4202 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4203 UnCondBrIter = I;
4204
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4205 if (!AllowModify) {
4206 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]4207 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4208 }
4209
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4210 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]4211 while (std::next(I) != MBB.end())
4212 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4213
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4214 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4215 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4216
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4217 // Delete the JMP if it's equivalent to a fall-through.
4218 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4219 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4220 I->eraseFromParent();
4221 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4222 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4223 continue;
4224 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4225
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4226 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4227 TBB = I->getOperand(0).getMBB();
4228 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4229 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4230
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4231 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4232 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4233 if (BranchCode == X86::COND_INVALID)
4234 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4235
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4236 // Working from the bottom, handle the first conditional branch.
4237 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4238 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4239 if (AllowModify && UnCondBrIter != MBB.end() &&
4240 MBB.isLayoutSuccessor(TargetBB)) {
4241 // If we can modify the code and it ends in something like:
4242 //
4243 // jCC L1
4244 // jmp L2
4245 // L1:
4246 // ...
4247 // L2:
4248 //
4249 // Then we can change this to:
4250 //
4251 // jnCC L2
4252 // L1:
4253 // ...
4254 // L2:
4255 //
4256 // Which is a bit more efficient.
4257 // We conditionally jump to the fall-through block.
4258 BranchCode = GetOppositeBranchCondition(BranchCode);
4259 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4260 MachineBasicBlock::iterator OldInst = I;
4261
4262 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4263 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4264 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4265 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4266
4267 OldInst->eraseFromParent();
4268 UnCondBrIter->eraseFromParent();
4269
4270 // Restart the analysis.
4271 UnCondBrIter = MBB.end();
4272 I = MBB.end();
4273 continue;
4274 }
4275
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4276 FBB = TBB;
4277 TBB = I->getOperand(0).getMBB();
4278 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4279 CondBranches.push_back(&*I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4280 continue;
4281 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4282
4283 // Handle subsequent conditional branches. Only handle the case where all
4284 // conditional branches branch to the same destination and their condition
4285 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4286 assert(Cond.size() == 1);
4287 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4288
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4289 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4290 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4291 auto NewTBB = I->getOperand(0).getMBB();
4292 if (OldBranchCode == BranchCode && TBB == NewTBB)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4293 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4294
4295 // If they differ, see if they fit one of the known patterns. Theoretically,
4296 // we could handle more patterns here, but we shouldn't expect to see them
4297 // if instruction selection has done a reasonable job.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4298 if (TBB == NewTBB &&
4299 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4300 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4301 BranchCode = X86::COND_NE_OR_P;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4302 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4303 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4304 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4305 return true;
4306
4307 // X86::COND_E_AND_NP usually has two different branch destinations.
4308 //
4309 // JP B1
4310 // JE B2
4311 // JMP B1
4312 // B1:
4313 // B2:
4314 //
4315 // Here this condition branches to B2 only if NP && E. It has another
4316 // equivalent form:
4317 //
4318 // JNE B1
4319 // JNP B2
4320 // JMP B1
4321 // B1:
4322 // B2:
4323 //
4324 // Similarly it branches to B2 only if E && NP. That is why this condition
4325 // is named with COND_E_AND_NP.
4326 BranchCode = X86::COND_E_AND_NP;
4327 } else
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4328 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4329
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4330 // Update the MachineOperand.
4331 Cond[0].setImm(BranchCode);
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4332 CondBranches.push_back(&*I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4333 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4334
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4335 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4336}
4337
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4338bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4339 MachineBasicBlock *&TBB,
4340 MachineBasicBlock *&FBB,
4341 SmallVectorImpl<MachineOperand> &Cond,
4342 bool AllowModify) const {
4343 SmallVector<MachineInstr *, 4> CondBranches;
4344 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4345}
4346
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4347bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4348 MachineBranchPredicate &MBP,
4349 bool AllowModify) const {
4350 using namespace std::placeholders;
4351
4352 SmallVector<MachineOperand, 4> Cond;
4353 SmallVector<MachineInstr *, 4> CondBranches;
4354 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4355 AllowModify))
4356 return true;
4357
4358 if (Cond.size() != 1)
4359 return true;
4360
4361 assert(MBP.TrueDest && "expected!");
4362
4363 if (!MBP.FalseDest)
4364 MBP.FalseDest = MBB.getNextNode();
4365
4366 const TargetRegisterInfo *TRI = &getRegisterInfo();
4367
4368 MachineInstr *ConditionDef = nullptr;
4369 bool SingleUseCondition = true;
4370
4371 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4372 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4373 ConditionDef = &*I;
4374 break;
4375 }
4376
4377 if (I->readsRegister(X86::EFLAGS, TRI))
4378 SingleUseCondition = false;
4379 }
4380
4381 if (!ConditionDef)
4382 return true;
4383
4384 if (SingleUseCondition) {
4385 for (auto *Succ : MBB.successors())
4386 if (Succ->isLiveIn(X86::EFLAGS))
4387 SingleUseCondition = false;
4388 }
4389
4390 MBP.ConditionDef = ConditionDef;
4391 MBP.SingleUseCondition = SingleUseCondition;
4392
4393 // Currently we only recognize the simple pattern:
4394 //
4395 // test %reg, %reg
4396 // je %label
4397 //
4398 const unsigned TestOpcode =
4399 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4400
4401 if (ConditionDef->getOpcode() == TestOpcode &&
4402 ConditionDef->getNumOperands() == 3 &&
4403 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4404 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4405 MBP.LHS = ConditionDef->getOperand(0);
4406 MBP.RHS = MachineOperand::CreateImm(0);
4407 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4408 ? MachineBranchPredicate::PRED_NE
4409 : MachineBranchPredicate::PRED_EQ;
4410 return false;
4411 }
4412
4413 return true;
4414}
4415
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4416unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4417 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4418 unsigned Count = 0;
4419
4420 while (I != MBB.begin()) {
4421 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4422 if (I->isDebugValue())
4423 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4424 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4425 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4426 break;
4427 // Remove the branch.
4428 I->eraseFromParent();
4429 I = MBB.end();
4430 ++Count;
4431 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4432
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4433 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4434}
4435
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4436unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4437 MachineBasicBlock *TBB,
4438 MachineBasicBlock *FBB,
4439 ArrayRef<MachineOperand> Cond,
4440 const DebugLoc &DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4441 // Shouldn't be a fall through.
4442 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4443 assert((Cond.size() == 1 || Cond.size() == 0) &&
4444 "X86 branch conditions have one component!");
4445
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4446 if (Cond.empty()) {
4447 // Unconditional branch?
4448 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4449 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4450 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4451 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4452
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4453 // If FBB is null, it is implied to be a fall-through block.
4454 bool FallThru = FBB == nullptr;
4455
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4456 // Conditional branch.
4457 unsigned Count = 0;
4458 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4459 switch (CC) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4460 case X86::COND_NE_OR_P:
4461 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4462 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4463 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4464 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4465 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4466 break;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4467 case X86::COND_E_AND_NP:
4468 // Use the next block of MBB as FBB if it is null.
4469 if (FBB == nullptr) {
4470 FBB = getFallThroughMBB(&MBB, TBB);
4471 assert(FBB && "MBB cannot be the last block in function when the false "
4472 "body is a fall-through.");
4473 }
4474 // Synthesize COND_E_AND_NP with two branches.
4475 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4476 ++Count;
4477 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4478 ++Count;
4479 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4480 default: {
4481 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4482 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4483 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4484 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4485 }
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4486 if (!FallThru) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4487 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4488 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4489 ++Count;
4490 }
4491 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4492}
4493
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4494bool X86InstrInfo::
4495canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4496 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4497 unsigned TrueReg, unsigned FalseReg,
4498 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4499 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4500 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4501 return false;
4502 if (Cond.size() != 1)
4503 return false;
4504 // We cannot do the composite conditions, at least not in SSA form.
4505 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4506 return false;
4507
4508 // Check register classes.
4509 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4510 const TargetRegisterClass *RC =
4511 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4512 if (!RC)
4513 return false;
4514
4515 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4516 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4517 X86::GR32RegClass.hasSubClassEq(RC) ||
4518 X86::GR64RegClass.hasSubClassEq(RC)) {
4519 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4520 // Bridge. Probably Ivy Bridge as well.
4521 CondCycles = 2;
4522 TrueCycles = 2;
4523 FalseCycles = 2;
4524 return true;
4525 }
4526
4527 // Can't do vectors.
4528 return false;
4529}
4530
4531void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4532 MachineBasicBlock::iterator I,
4533 const DebugLoc &DL, unsigned DstReg,
4534 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4535 unsigned FalseReg) const {
4536 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4537 assert(Cond.size() == 1 && "Invalid Cond array");
4538 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4539 MRI.getRegClass(DstReg)->getSize(),
4540 false /*HasMemoryOperand*/);
4541 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4542}
4543
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4544/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4545static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4546 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4547}
4548
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4549// Try and copy between VR128/VR64 and GR64 registers.
Craig Topper93f7b562016-09-05 20:34:50 +0000[diff] [blame]4550static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4551 const X86Subtarget &Subtarget) {
Craig Topper93f7b562016-09-05 20:34:50 +0000[diff] [blame]4552 bool HasAVX = Subtarget.hasAVX();
4553 bool HasAVX512 = Subtarget.hasAVX512();
4554
4555 // SrcReg(MaskReg) -> DestReg(GR64)
4556 // SrcReg(MaskReg) -> DestReg(GR32)
4557 // SrcReg(MaskReg) -> DestReg(GR16)
4558 // SrcReg(MaskReg) -> DestReg(GR8)
4559
4560 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4561 if (X86::VK16RegClass.contains(SrcReg)) {
4562 if (X86::GR64RegClass.contains(DestReg)) {
4563 assert(Subtarget.hasBWI());
4564 return X86::KMOVQrk;
4565 }
4566 if (X86::GR32RegClass.contains(DestReg))
4567 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
4568 if (X86::GR16RegClass.contains(DestReg)) {
4569 DestReg = getX86SubSuperRegister(DestReg, 32);
4570 return X86::KMOVWrk;
4571 }
4572 if (X86::GR8RegClass.contains(DestReg)) {
4573 DestReg = getX86SubSuperRegister(DestReg, 32);
4574 return Subtarget.hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
4575 }
4576 }
4577
4578 // SrcReg(GR64) -> DestReg(MaskReg)
4579 // SrcReg(GR32) -> DestReg(MaskReg)
4580 // SrcReg(GR16) -> DestReg(MaskReg)
4581 // SrcReg(GR8) -> DestReg(MaskReg)
4582
4583 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4584 if (X86::VK16RegClass.contains(DestReg)) {
4585 if (X86::GR64RegClass.contains(SrcReg)) {
4586 assert(Subtarget.hasBWI());
4587 return X86::KMOVQkr;
4588 }
4589 if (X86::GR32RegClass.contains(SrcReg))
4590 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
4591 if (X86::GR16RegClass.contains(SrcReg)) {
4592 SrcReg = getX86SubSuperRegister(SrcReg, 32);
4593 return X86::KMOVWkr;
4594 }
4595 if (X86::GR8RegClass.contains(SrcReg)) {
4596 SrcReg = getX86SubSuperRegister(SrcReg, 32);
4597 return Subtarget.hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
4598 }
4599 }
4600
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4601
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4602 // SrcReg(VR128) -> DestReg(GR64)
4603 // SrcReg(VR64) -> DestReg(GR64)
4604 // SrcReg(GR64) -> DestReg(VR128)
4605 // SrcReg(GR64) -> DestReg(VR64)
4606
4607 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4608 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4609 // Copy from a VR128 register to a GR64 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4610 return HasAVX512 ? X86::VMOVPQIto64Zrr :
4611 HasAVX ? X86::VMOVPQIto64rr :
4612 X86::MOVPQIto64rr;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4613 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4614 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4615 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4616 } else if (X86::GR64RegClass.contains(SrcReg)) {
4617 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4618 if (X86::VR128XRegClass.contains(DestReg))
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4619 return HasAVX512 ? X86::VMOV64toPQIZrr :
4620 HasAVX ? X86::VMOV64toPQIrr :
4621 X86::MOV64toPQIrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4622 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4623 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4624 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4625 }
4626
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4627 // SrcReg(FR32) -> DestReg(GR32)
4628 // SrcReg(GR32) -> DestReg(FR32)
4629
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4630 if (X86::GR32RegClass.contains(DestReg) &&
4631 X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4632 // Copy from a FR32 register to a GR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4633 return HasAVX512 ? X86::VMOVSS2DIZrr :
4634 HasAVX ? X86::VMOVSS2DIrr :
4635 X86::MOVSS2DIrr;
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4636
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4637 if (X86::FR32XRegClass.contains(DestReg) &&
4638 X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4639 // Copy from a GR32 register to a FR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4640 return HasAVX512 ? X86::VMOVDI2SSZrr :
4641 HasAVX ? X86::VMOVDI2SSrr :
4642 X86::MOVDI2SSrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4643 return 0;
4644}
4645
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4646void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4647 MachineBasicBlock::iterator MI,
4648 const DebugLoc &DL, unsigned DestReg,
4649 unsigned SrcReg, bool KillSrc) const {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4650 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4651 bool HasAVX = Subtarget.hasAVX();
Craig Topperd9ca3d92016-09-05 06:43:06 +0000[diff] [blame]4652 bool HasVLX = Subtarget.hasVLX();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4653 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4654 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4655 Opc = X86::MOV64rr;
4656 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4657 Opc = X86::MOV32rr;
4658 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4659 Opc = X86::MOV16rr;
4660 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4661 // Copying to or from a physical H register on x86-64 requires a NOREX
4662 // move. Otherwise use a normal move.
4663 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4664 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4665 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4666 // Both operands must be encodable without an REX prefix.
4667 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4668 "8-bit H register can not be copied outside GR8_NOREX");
4669 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4670 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4671 }
4672 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4673 Opc = X86::MMX_MOVQ64rr;
Craig Topperd9ca3d92016-09-05 06:43:06 +0000[diff] [blame]4674 else if (X86::VR128XRegClass.contains(DestReg, SrcReg))
4675 Opc = HasVLX ? X86::VMOVAPSZ128rr : HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4676 else if (X86::VR256XRegClass.contains(DestReg, SrcReg))
4677 Opc = HasVLX ? X86::VMOVAPSZ256rr : X86::VMOVAPSYrr;
4678 else if (X86::VR512RegClass.contains(DestReg, SrcReg))
4679 Opc = X86::VMOVAPSZrr;
Craig Topper93f7b562016-09-05 20:34:50 +0000[diff] [blame]4680 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4681 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
4682 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4683 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4684 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4685
4686 if (Opc) {
4687 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4688 .addReg(SrcReg, getKillRegState(KillSrc));
4689 return;
4690 }
4691
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4692 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4693 bool ToEFLAGS = DestReg == X86::EFLAGS;
4694 int Reg = FromEFLAGS ? DestReg : SrcReg;
4695 bool is32 = X86::GR32RegClass.contains(Reg);
4696 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4697
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4698 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4699 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4700 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4701 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4702 int Pop = is64 ? X86::POP64r : X86::POP32r;
4703 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4704 int AX = is64 ? X86::RAX : X86::EAX;
4705
4706 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4707 assert(Subtarget.is64Bit() &&
4708 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4709 // Moving EFLAGS to / from another register requires a push and a pop.
4710 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemer33467632015-12-27 06:07:26 +0000[diff] [blame]4711 // first frame index. See X86FrameLowering.cpp - usesTheStack.
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4712 if (FromEFLAGS) {
4713 BuildMI(MBB, MI, DL, get(PushF));
4714 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4715 }
4716 if (ToEFLAGS) {
4717 BuildMI(MBB, MI, DL, get(Push))
4718 .addReg(SrcReg, getKillRegState(KillSrc));
4719 BuildMI(MBB, MI, DL, get(PopF));
4720 }
4721 return;
4722 }
4723
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4724 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4725 // inefficient. Instead:
4726 // - Save the overflow flag OF into AL using SETO, and restore it using a
4727 // signed 8-bit addition of AL and INT8_MAX.
4728 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4729 // using LAHF/SAHF.
4730 // - When RAX/EAX is live and isn't the destination register, make sure it
4731 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4732 // the flags.
4733 // This approach is ~2.25x faster than using PUSHF/POPF.
4734 //
4735 // This is still somewhat inefficient because we don't know which flags are
4736 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4737 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4738 //
4739 // PUSHF/POPF is also potentially incorrect because it affects other flags
4740 // such as TF/IF/DF, which LLVM doesn't model.
4741 //
4742 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemerca1c9f02016-01-04 04:49:41 +0000[diff] [blame]4743 // first frame index.
4744 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4745
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4746 const TargetRegisterInfo *TRI = &getRegisterInfo();
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4747 MachineBasicBlock::LivenessQueryResult LQR =
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4748 MBB.computeRegisterLiveness(TRI, AX, MI);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4749 // We do not want to save and restore AX if we do not have to.
4750 // Moreover, if we do so whereas AX is dead, we would need to set
4751 // an undef flag on the use of AX, otherwise the verifier will
4752 // complain that we read an undef value.
4753 // We do not want to change the behavior of the machine verifier
4754 // as this is usually wrong to read an undef value.
4755 if (MachineBasicBlock::LQR_Unknown == LQR) {
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4756 LivePhysRegs LPR(TRI);
Matthias Braund1aabb22016-05-03 00:24:32 +0000[diff] [blame]4757 LPR.addLiveOuts(MBB);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4758 MachineBasicBlock::iterator I = MBB.end();
4759 while (I != MI) {
4760 --I;
4761 LPR.stepBackward(*I);
4762 }
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4763 // AX contains the top most register in the aliasing hierarchy.
4764 // It may not be live, but one of its aliases may be.
4765 for (MCRegAliasIterator AI(AX, TRI, true);
4766 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4767 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4768 : MachineBasicBlock::LQR_Dead;
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4769 }
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4770 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4771 if (!AXDead)
4772 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4773 if (FromEFLAGS) {
4774 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4775 BuildMI(MBB, MI, DL, get(X86::LAHF));
4776 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4777 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4778 if (ToEFLAGS) {
4779 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4780 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4781 .addReg(X86::AL)
4782 .addImm(INT8_MAX);
4783 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4784 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4785 if (!AXDead)
4786 BuildMI(MBB, MI, DL, get(Pop), AX);
4787 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4788 }
4789
4790 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4791 << " to " << RI.getName(DestReg) << '\n');
4792 llvm_unreachable("Cannot emit physreg copy instruction");
4793}
4794
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4795static unsigned getLoadStoreRegOpcode(unsigned Reg,
4796 const TargetRegisterClass *RC,
4797 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4798 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4799 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4800 bool HasAVX = STI.hasAVX();
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4801 bool HasAVX512 = STI.hasAVX512();
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4802 bool HasVLX = STI.hasVLX();
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4803
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4804 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4805 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4806 llvm_unreachable("Unknown spill size");
4807 case 1:
4808 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4809 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4810 // Copying to or from a physical H register on x86-64 requires a NOREX
4811 // move. Otherwise use a normal move.
4812 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4813 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4814 return load ? X86::MOV8rm : X86::MOV8mr;
4815 case 2:
Craig Topperda50eec2016-08-01 04:29:11 +0000[diff] [blame]4816 if (X86::VK16RegClass.hasSubClassEq(RC))
4817 return load ? X86::KMOVWkm : X86::KMOVWmk;
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4818 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4819 return load ? X86::MOV16rm : X86::MOV16mr;
4820 case 4:
4821 if (X86::GR32RegClass.hasSubClassEq(RC))
4822 return load ? X86::MOV32rm : X86::MOV32mr;
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4823 if (X86::FR32XRegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4824 return load ?
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4825 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4826 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4827 if (X86::RFP32RegClass.hasSubClassEq(RC))
4828 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
Craig Topperda50eec2016-08-01 04:29:11 +0000[diff] [blame]4829 if (X86::VK32RegClass.hasSubClassEq(RC))
4830 return load ? X86::KMOVDkm : X86::KMOVDmk;
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4831 llvm_unreachable("Unknown 4-byte regclass");
4832 case 8:
4833 if (X86::GR64RegClass.hasSubClassEq(RC))
4834 return load ? X86::MOV64rm : X86::MOV64mr;
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4835 if (X86::FR64XRegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4836 return load ?
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4837 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4838 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4839 if (X86::VR64RegClass.hasSubClassEq(RC))
4840 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4841 if (X86::RFP64RegClass.hasSubClassEq(RC))
4842 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
Craig Topperda50eec2016-08-01 04:29:11 +0000[diff] [blame]4843 if (X86::VK64RegClass.hasSubClassEq(RC))
4844 return load ? X86::KMOVQkm : X86::KMOVQmk;
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4845 llvm_unreachable("Unknown 8-byte regclass");
4846 case 10:
4847 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4848 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4849 case 16: {
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4850 assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4851 // If stack is realigned we can use aligned stores.
4852 if (isStackAligned)
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4853 return load ?
4854 (HasVLX ? X86::VMOVAPSZ128rm : HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm):
4855 (HasVLX ? X86::VMOVAPSZ128mr : HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4856 else
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4857 return load ?
4858 (HasVLX ? X86::VMOVUPSZ128rm : HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm):
4859 (HasVLX ? X86::VMOVUPSZ128mr : HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4860 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4861 case 32:
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4862 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4863 // If stack is realigned we can use aligned stores.
4864 if (isStackAligned)
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4865 return load ?
4866 (HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm) :
4867 (HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr);
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4868 else
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4869 return load ?
4870 (HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm) :
4871 (HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr);
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4872 case 64:
4873 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
Craig Topper338ec9a2016-07-31 20:19:53 +0000[diff] [blame]4874 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4875 if (isStackAligned)
4876 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4877 else
4878 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4879 }
4880}
4881
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4882bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
Chad Rosierc27a18f2016-03-09 16:00:35 +0000[diff] [blame]4883 int64_t &Offset,
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4884 const TargetRegisterInfo *TRI) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4885 const MCInstrDesc &Desc = MemOp.getDesc();
Craig Topper477649a2016-04-28 05:58:46 +0000[diff] [blame]4886 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4887 if (MemRefBegin < 0)
4888 return false;
4889
4890 MemRefBegin += X86II::getOperandBias(Desc);
4891
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4892 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
Sanjoy Das881de4d2016-02-02 02:32:43 +0000[diff] [blame]4893 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4894 return false;
4895
4896 BaseReg = BaseMO.getReg();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4897 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4898 return false;
4899
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4900 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4901 X86::NoRegister)
4902 return false;
4903
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4904 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4905
4906 // Displacement can be symbolic
4907 if (!DispMO.isImm())
4908 return false;
4909
4910 Offset = DispMO.getImm();
4911
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4912 return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4913 X86::NoRegister;
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4914}
4915
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4916static unsigned getStoreRegOpcode(unsigned SrcReg,
4917 const TargetRegisterClass *RC,
4918 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4919 const X86Subtarget &STI) {
4920 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4921}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4922
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4923
4924static unsigned getLoadRegOpcode(unsigned DestReg,
4925 const TargetRegisterClass *RC,
4926 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4927 const X86Subtarget &STI) {
4928 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4929}
4930
4931void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4932 MachineBasicBlock::iterator MI,
4933 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4934 const TargetRegisterClass *RC,
4935 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4936 const MachineFunction &MF = *MBB.getParent();
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]4937 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4938 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4939 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4940 bool isAligned =
4941 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4942 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4943 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4944 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4945 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4946 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4947}
4948
4949void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4950 bool isKill,
4951 SmallVectorImpl<MachineOperand> &Addr,
4952 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4953 MachineInstr::mmo_iterator MMOBegin,
4954 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4955 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4956 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4957 bool isAligned = MMOBegin != MMOEnd &&
4958 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4959 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4960 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4961 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4962 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4963 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4964 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4965 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4966 NewMIs.push_back(MIB);
4967}
4968
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4969
4970void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4971 MachineBasicBlock::iterator MI,
4972 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4973 const TargetRegisterClass *RC,
4974 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4975 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4976 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4977 bool isAligned =
4978 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4979 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4980 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4981 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4982 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4983}
4984
4985void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4986 SmallVectorImpl<MachineOperand> &Addr,
4987 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4988 MachineInstr::mmo_iterator MMOBegin,
4989 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4990 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4991 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4992 bool isAligned = MMOBegin != MMOEnd &&
4993 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4994 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4995 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4996 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4997 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4998 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4999 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5000 NewMIs.push_back(MIB);
5001}
5002
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5003bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
5004 unsigned &SrcReg2, int &CmpMask,
5005 int &CmpValue) const {
5006 switch (MI.getOpcode()) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5007 default: break;
5008 case X86::CMP64ri32:
5009 case X86::CMP64ri8:
5010 case X86::CMP32ri:
5011 case X86::CMP32ri8:
5012 case X86::CMP16ri:
5013 case X86::CMP16ri8:
5014 case X86::CMP8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5015 SrcReg = MI.getOperand(0).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5016 SrcReg2 = 0;
5017 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5018 CmpValue = MI.getOperand(1).getImm();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5019 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5020 // A SUB can be used to perform comparison.
5021 case X86::SUB64rm:
5022 case X86::SUB32rm:
5023 case X86::SUB16rm:
5024 case X86::SUB8rm:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5025 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5026 SrcReg2 = 0;
5027 CmpMask = ~0;
5028 CmpValue = 0;
5029 return true;
5030 case X86::SUB64rr:
5031 case X86::SUB32rr:
5032 case X86::SUB16rr:
5033 case X86::SUB8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5034 SrcReg = MI.getOperand(1).getReg();
5035 SrcReg2 = MI.getOperand(2).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5036 CmpMask = ~0;
5037 CmpValue = 0;
5038 return true;
5039 case X86::SUB64ri32:
5040 case X86::SUB64ri8:
5041 case X86::SUB32ri:
5042 case X86::SUB32ri8:
5043 case X86::SUB16ri:
5044 case X86::SUB16ri8:
5045 case X86::SUB8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5046 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5047 SrcReg2 = 0;
5048 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5049 CmpValue = MI.getOperand(2).getImm();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5050 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5051 case X86::CMP64rr:
5052 case X86::CMP32rr:
5053 case X86::CMP16rr:
5054 case X86::CMP8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5055 SrcReg = MI.getOperand(0).getReg();
5056 SrcReg2 = MI.getOperand(1).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5057 CmpMask = ~0;
5058 CmpValue = 0;
5059 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5060 case X86::TEST8rr:
5061 case X86::TEST16rr:
5062 case X86::TEST32rr:
5063 case X86::TEST64rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5064 SrcReg = MI.getOperand(0).getReg();
5065 if (MI.getOperand(1).getReg() != SrcReg)
5066 return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5067 // Compare against zero.
5068 SrcReg2 = 0;
5069 CmpMask = ~0;
5070 CmpValue = 0;
5071 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5072 }
5073 return false;
5074}
5075
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5076/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5077/// purpose is to update flags, can be made redundant.
5078/// CMPrr can be made redundant by SUBrr if the operands are the same.
5079/// This function can be extended later on.
5080/// SrcReg, SrcRegs: register operands for FlagI.
5081/// ImmValue: immediate for FlagI if it takes an immediate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5082inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5083 unsigned SrcReg2, int ImmValue,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5084 MachineInstr &OI) {
5085 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
5086 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
5087 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
5088 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
5089 ((OI.getOperand(1).getReg() == SrcReg &&
5090 OI.getOperand(2).getReg() == SrcReg2) ||
5091 (OI.getOperand(1).getReg() == SrcReg2 &&
5092 OI.getOperand(2).getReg() == SrcReg)))
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5093 return true;
5094
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5095 if (((FlagI.getOpcode() == X86::CMP64ri32 &&
5096 OI.getOpcode() == X86::SUB64ri32) ||
5097 (FlagI.getOpcode() == X86::CMP64ri8 &&
5098 OI.getOpcode() == X86::SUB64ri8) ||
5099 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
5100 (FlagI.getOpcode() == X86::CMP32ri8 &&
5101 OI.getOpcode() == X86::SUB32ri8) ||
5102 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
5103 (FlagI.getOpcode() == X86::CMP16ri8 &&
5104 OI.getOpcode() == X86::SUB16ri8) ||
5105 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
5106 OI.getOperand(1).getReg() == SrcReg &&
5107 OI.getOperand(2).getImm() == ImmValue)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5108 return true;
5109 return false;
5110}
5111
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5112/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5113/// to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5114inline static bool isDefConvertible(MachineInstr &MI) {
5115 switch (MI.getOpcode()) {
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5116 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]5117
5118 // The shift instructions only modify ZF if their shift count is non-zero.
5119 // N.B.: The processor truncates the shift count depending on the encoding.
5120 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
5121 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
5122 return getTruncatedShiftCount(MI, 2) != 0;
5123
5124 // Some left shift instructions can be turned into LEA instructions but only
5125 // if their flags aren't used. Avoid transforming such instructions.
5126 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
5127 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
5128 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
5129 return ShAmt != 0;
5130 }
5131
5132 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
5133 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
5134 return getTruncatedShiftCount(MI, 3) != 0;
5135
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5136 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
5137 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
5138 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
5139 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
5140 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5141 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5142 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
5143 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
5144 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
5145 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
5146 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5147 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5148 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
5149 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
5150 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
5151 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
5152 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
5153 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
5154 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
5155 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
5156 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
5157 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
5158 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
5159 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
5160 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
5161 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
5162 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5163 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
5164 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
5165 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
5166 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
5167 case X86::ADC32ri: case X86::ADC32ri8:
5168 case X86::ADC32rr: case X86::ADC64ri32:
5169 case X86::ADC64ri8: case X86::ADC64rr:
5170 case X86::SBB32ri: case X86::SBB32ri8:
5171 case X86::SBB32rr: case X86::SBB64ri32:
5172 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]5173 case X86::ANDN32rr: case X86::ANDN32rm:
5174 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5175 case X86::BEXTR32rr: case X86::BEXTR64rr:
5176 case X86::BEXTR32rm: case X86::BEXTR64rm:
5177 case X86::BLSI32rr: case X86::BLSI32rm:
5178 case X86::BLSI64rr: case X86::BLSI64rm:
5179 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5180 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5181 case X86::BLSR32rr: case X86::BLSR32rm:
5182 case X86::BLSR64rr: case X86::BLSR64rm:
5183 case X86::BZHI32rr: case X86::BZHI32rm:
5184 case X86::BZHI64rr: case X86::BZHI64rm:
5185 case X86::LZCNT16rr: case X86::LZCNT16rm:
5186 case X86::LZCNT32rr: case X86::LZCNT32rm:
5187 case X86::LZCNT64rr: case X86::LZCNT64rm:
5188 case X86::POPCNT16rr:case X86::POPCNT16rm:
5189 case X86::POPCNT32rr:case X86::POPCNT32rm:
5190 case X86::POPCNT64rr:case X86::POPCNT64rm:
5191 case X86::TZCNT16rr: case X86::TZCNT16rm:
5192 case X86::TZCNT32rr: case X86::TZCNT32rm:
5193 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5194 return true;
5195 }
5196}
5197
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5198/// Check whether the use can be converted to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5199static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5200 switch (MI.getOpcode()) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5201 default: return X86::COND_INVALID;
5202 case X86::LZCNT16rr: case X86::LZCNT16rm:
5203 case X86::LZCNT32rr: case X86::LZCNT32rm:
5204 case X86::LZCNT64rr: case X86::LZCNT64rm:
5205 return X86::COND_B;
5206 case X86::POPCNT16rr:case X86::POPCNT16rm:
5207 case X86::POPCNT32rr:case X86::POPCNT32rm:
5208 case X86::POPCNT64rr:case X86::POPCNT64rm:
5209 return X86::COND_E;
5210 case X86::TZCNT16rr: case X86::TZCNT16rm:
5211 case X86::TZCNT32rr: case X86::TZCNT32rm:
5212 case X86::TZCNT64rr: case X86::TZCNT64rm:
5213 return X86::COND_B;
5214 }
5215}
5216
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5217/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5218/// operates on the same source operands and sets flags in the same way as
5219/// Compare; remove Compare if possible.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5220bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5221 unsigned SrcReg2, int CmpMask,
5222 int CmpValue,
5223 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5224 // Check whether we can replace SUB with CMP.
5225 unsigned NewOpcode = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5226 switch (CmpInstr.getOpcode()) {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5227 default: break;
5228 case X86::SUB64ri32:
5229 case X86::SUB64ri8:
5230 case X86::SUB32ri:
5231 case X86::SUB32ri8:
5232 case X86::SUB16ri:
5233 case X86::SUB16ri8:
5234 case X86::SUB8ri:
5235 case X86::SUB64rm:
5236 case X86::SUB32rm:
5237 case X86::SUB16rm:
5238 case X86::SUB8rm:
5239 case X86::SUB64rr:
5240 case X86::SUB32rr:
5241 case X86::SUB16rr:
5242 case X86::SUB8rr: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5243 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5244 return false;
5245 // There is no use of the destination register, we can replace SUB with CMP.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5246 switch (CmpInstr.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5247 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5248 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5249 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5250 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5251 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5252 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5253 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5254 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5255 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5256 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5257 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5258 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5259 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5260 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5261 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5262 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5263 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5264 CmpInstr.setDesc(get(NewOpcode));
5265 CmpInstr.RemoveOperand(0);
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5266 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5267 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5268 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5269 return false;
5270 }
5271 }
5272
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5273 // Get the unique definition of SrcReg.
5274 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5275 if (!MI) return false;
5276
5277 // CmpInstr is the first instruction of the BB.
5278 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5279
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5280 // If we are comparing against zero, check whether we can use MI to update
5281 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5282 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5283 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5284 return false;
5285
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5286 // If we have a use of the source register between the def and our compare
5287 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5288 // right way.
5289 bool ShouldUpdateCC = false;
5290 X86::CondCode NewCC = X86::COND_INVALID;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5291 if (IsCmpZero && !isDefConvertible(*MI)) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5292 // Scan forward from the use until we hit the use we're looking for or the
5293 // compare instruction.
5294 for (MachineBasicBlock::iterator J = MI;; ++J) {
5295 // Do we have a convertible instruction?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5296 NewCC = isUseDefConvertible(*J);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5297 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5298 J->getOperand(1).getReg() == SrcReg) {
5299 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5300 ShouldUpdateCC = true; // Update CC later on.
5301 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5302 // with the new def.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]5303 Def = J;
5304 MI = &*Def;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5305 break;
5306 }
5307
5308 if (J == I)
5309 return false;
5310 }
5311 }
5312
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5313 // We are searching for an earlier instruction that can make CmpInstr
5314 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5315 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5316 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5317
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5318 // We iterate backward, starting from the instruction before CmpInstr and
5319 // stop when reaching the definition of a source register or done with the BB.
5320 // RI points to the instruction before CmpInstr.
5321 // If the definition is in this basic block, RE points to the definition;
5322 // otherwise, RE is the rend of the basic block.
5323 MachineBasicBlock::reverse_iterator
5324 RI = MachineBasicBlock::reverse_iterator(I),
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5325 RE = CmpInstr.getParent() == MI->getParent()
5326 ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5327 : CmpInstr.getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5328 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5329 for (; RI != RE; ++RI) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5330 MachineInstr &Instr = *RI;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5331 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5332 if (!IsCmpZero &&
5333 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5334 Sub = &Instr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5335 break;
5336 }
5337
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5338 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5339 Instr.readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5340 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5341
5342 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5343 // They are safe to move up, if the definition to EFLAGS is dead and
5344 // earlier instructions do not read or write EFLAGS.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5345 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5346 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5347 Movr0Inst = &Instr;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5348 continue;
5349 }
5350
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5351 // We can't remove CmpInstr.
5352 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5353 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5354 }
5355
5356 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5357 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5358 return false;
5359
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5360 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5361 Sub->getOperand(2).getReg() == SrcReg);
5362
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5363 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5364 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5365 // If we are done with the basic block, we need to check whether EFLAGS is
5366 // live-out.
5367 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5368 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5369 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5370 for (++I; I != E; ++I) {
5371 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5372 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5373 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5374 // We should check the usage if this instruction uses and updates EFLAGS.
5375 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5376 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5377 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5378 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5379 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5380 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5381 continue;
5382
5383 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5384 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5385 bool OpcIsSET = false;
5386 if (IsCmpZero || IsSwapped) {
5387 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5388 if (Instr.isBranch())
5389 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5390 else {
5391 OldCC = getCondFromSETOpc(Instr.getOpcode());
5392 if (OldCC != X86::COND_INVALID)
5393 OpcIsSET = true;
5394 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5395 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5396 }
5397 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5398 }
5399 if (IsCmpZero) {
5400 switch (OldCC) {
5401 default: break;
5402 case X86::COND_A: case X86::COND_AE:
5403 case X86::COND_B: case X86::COND_BE:
5404 case X86::COND_G: case X86::COND_GE:
5405 case X86::COND_L: case X86::COND_LE:
5406 case X86::COND_O: case X86::COND_NO:
5407 // CF and OF are used, we can't perform this optimization.
5408 return false;
5409 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5410
5411 // If we're updating the condition code check if we have to reverse the
5412 // condition.
5413 if (ShouldUpdateCC)
5414 switch (OldCC) {
5415 default:
5416 return false;
5417 case X86::COND_E:
5418 break;
5419 case X86::COND_NE:
5420 NewCC = GetOppositeBranchCondition(NewCC);
5421 break;
5422 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5423 } else if (IsSwapped) {
5424 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5425 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5426 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5427 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5428 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5429 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5430
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5431 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5432 // Synthesize the new opcode.
5433 bool HasMemoryOperand = Instr.hasOneMemOperand();
5434 unsigned NewOpc;
5435 if (Instr.isBranch())
5436 NewOpc = GetCondBranchFromCond(NewCC);
5437 else if(OpcIsSET)
5438 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5439 else {
5440 unsigned DstReg = Instr.getOperand(0).getReg();
5441 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5442 HasMemoryOperand);
5443 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5444
5445 // Push the MachineInstr to OpsToUpdate.
5446 // If it is safe to remove CmpInstr, the condition code of these
5447 // instructions will be modified.
5448 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5449 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5450 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5451 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5452 IsSafe = true;
5453 break;
5454 }
5455 }
5456
5457 // If EFLAGS is not killed nor re-defined, we should check whether it is
5458 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5459 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5460 MachineBasicBlock *MBB = CmpInstr.getParent();
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5461 for (MachineBasicBlock *Successor : MBB->successors())
5462 if (Successor->isLiveIn(X86::EFLAGS))
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5463 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5464 }
5465
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5466 // The instruction to be updated is either Sub or MI.
5467 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5468 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5469 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5470 // Look backwards until we find a def that doesn't use the current EFLAGS.
5471 Def = Sub;
5472 MachineBasicBlock::reverse_iterator
5473 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5474 InsertE = Sub->getParent()->rend();
5475 for (; InsertI != InsertE; ++InsertI) {
5476 MachineInstr *Instr = &*InsertI;
5477 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5478 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5479 Sub->getParent()->remove(Movr0Inst);
5480 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5481 Movr0Inst);
5482 break;
5483 }
5484 }
5485 if (InsertI == InsertE)
5486 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5487 }
5488
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5489 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5490 unsigned i = 0, e = Sub->getNumOperands();
5491 for (; i != e; ++i) {
5492 MachineOperand &MO = Sub->getOperand(i);
5493 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5494 MO.setIsDead(false);
5495 break;
5496 }
5497 }
5498 assert(i != e && "Unable to locate a def EFLAGS operand");
5499
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5500 CmpInstr.eraseFromParent();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5501
5502 // Modify the condition code of instructions in OpsToUpdate.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5503 for (auto &Op : OpsToUpdate)
5504 Op.first->setDesc(get(Op.second));
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5505 return true;
5506}
5507
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5508/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5509/// operand at the use. We fold the load instructions if load defines a virtual
5510/// register, the virtual register is used once in the same BB, and the
5511/// instructions in-between do not load or store, and have no side effects.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5512MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5513 const MachineRegisterInfo *MRI,
5514 unsigned &FoldAsLoadDefReg,
5515 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5516 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5517 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5518 // To be conservative, if there exists another load, clear the load candidate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5519 if (MI.mayLoad()) {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5520 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5521 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5522 }
5523
5524 // Check whether we can move DefMI here.
5525 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5526 assert(DefMI);
5527 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5528 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5529 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5530
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5531 // Collect information about virtual register operands of MI.
5532 unsigned SrcOperandId = 0;
5533 bool FoundSrcOperand = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5534 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5535 MachineOperand &MO = MI.getOperand(i);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5536 if (!MO.isReg())
5537 continue;
5538 unsigned Reg = MO.getReg();
5539 if (Reg != FoldAsLoadDefReg)
5540 continue;
5541 // Do not fold if we have a subreg use or a def or multiple uses.
5542 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5543 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5544
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5545 SrcOperandId = i;
5546 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5547 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5548 if (!FoundSrcOperand)
5549 return nullptr;
5550
5551 // Check whether we can fold the def into SrcOperandId.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5552 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5553 FoldAsLoadDefReg = 0;
5554 return FoldMI;
5555 }
5556
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5557 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5558}
5559
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5560/// Expand a single-def pseudo instruction to a two-addr
5561/// instruction with two undef reads of the register being defined.
5562/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5563/// %xmm4 = V_SET0
5564/// to:
5565/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5566///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5567static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5568 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5569 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5570 unsigned Reg = MIB->getOperand(0).getReg();
5571 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5572
5573 // MachineInstr::addOperand() will insert explicit operands before any
5574 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5575 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5576 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5577 assert(MIB->getOperand(1).getReg() == Reg &&
5578 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5579 return true;
5580}
5581
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5582/// Expand a single-def pseudo instruction to a two-addr
5583/// instruction with two %k0 reads.
5584/// This is used for mapping:
5585/// %k4 = K_SET1
5586/// to:
5587/// %k4 = KXNORrr %k0, %k0
5588static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5589 const MCInstrDesc &Desc, unsigned Reg) {
5590 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5591 MIB->setDesc(Desc);
5592 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5593 return true;
5594}
5595
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5596static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5597 bool MinusOne) {
5598 MachineBasicBlock &MBB = *MIB->getParent();
5599 DebugLoc DL = MIB->getDebugLoc();
5600 unsigned Reg = MIB->getOperand(0).getReg();
5601
5602 // Insert the XOR.
5603 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5604 .addReg(Reg, RegState::Undef)
5605 .addReg(Reg, RegState::Undef);
5606
5607 // Turn the pseudo into an INC or DEC.
5608 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5609 MIB.addReg(Reg);
5610
5611 return true;
5612}
5613
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5614bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5615 MachineBasicBlock &MBB = *MIB->getParent();
5616 DebugLoc DL = MIB->getDebugLoc();
5617 int64_t Imm = MIB->getOperand(1).getImm();
5618 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5619 MachineBasicBlock::iterator I = MIB.getInstr();
5620
5621 int StackAdjustment;
5622
5623 if (Subtarget.is64Bit()) {
5624 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5625 MIB->getOpcode() == X86::MOV32ImmSExti8);
5626
5627 // Can't use push/pop lowering if the function might write to the red zone.
5628 X86MachineFunctionInfo *X86FI =
5629 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5630 if (X86FI->getUsesRedZone()) {
5631 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5632 : X86::MOV64ri));
5633 return true;
5634 }
5635
5636 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5637 // widen the register if necessary.
5638 StackAdjustment = 8;
5639 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5640 MIB->setDesc(get(X86::POP64r));
5641 MIB->getOperand(0)
5642 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5643 } else {
5644 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5645 StackAdjustment = 4;
5646 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5647 MIB->setDesc(get(X86::POP32r));
5648 }
5649
5650 // Build CFI if necessary.
5651 MachineFunction &MF = *MBB.getParent();
5652 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5653 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5654 bool NeedsDwarfCFI =
5655 !IsWin64Prologue &&
5656 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5657 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5658 if (EmitCFI) {
5659 TFL->BuildCFI(MBB, I, DL,
5660 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5661 TFL->BuildCFI(MBB, std::next(I), DL,
5662 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5663 }
5664
5665 return true;
5666}
5667
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5668// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5669// code sequence is needed for other targets.
5670static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5671 const TargetInstrInfo &TII) {
5672 MachineBasicBlock &MBB = *MIB->getParent();
5673 DebugLoc DL = MIB->getDebugLoc();
5674 unsigned Reg = MIB->getOperand(0).getReg();
5675 const GlobalValue *GV =
5676 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5677 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5678 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5679 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5680 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5681
5682 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5683 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5684 .addMemOperand(MMO);
5685 MIB->setDebugLoc(DL);
5686 MIB->setDesc(TII.get(X86::MOV64rm));
5687 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5688}
5689
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5690bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5691 bool HasAVX = Subtarget.hasAVX();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5692 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5693 switch (MI.getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5694 case X86::MOV32r0:
5695 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5696 case X86::MOV32r1:
5697 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5698 case X86::MOV32r_1:
5699 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5700 case X86::MOV32ImmSExti8:
5701 case X86::MOV64ImmSExti8:
5702 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5703 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5704 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5705 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5706 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5707 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5708 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5709 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5710 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5711 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5712 case X86::FsFLD0SS:
5713 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5714 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5715 case X86::AVX_SET0:
5716 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5717 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Craig Toppere5ce84a2016-05-08 21:33:53 +0000[diff] [blame]5718 case X86::AVX512_128_SET0:
5719 return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5720 case X86::AVX512_256_SET0:
5721 return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5722 case X86::AVX512_512_SET0:
5723 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5724 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5725 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5726 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5727 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]5728 case X86::AVX512_512_SETALLONES: {
5729 unsigned Reg = MIB->getOperand(0).getReg();
5730 MIB->setDesc(get(X86::VPTERNLOGDZrri));
5731 // VPTERNLOGD needs 3 register inputs and an immediate.
5732 // 0xff will return 1s for any input.
5733 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5734 .addReg(Reg, RegState::Undef).addImm(0xff);
5735 return true;
5736 }
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5737 case X86::TEST8ri_NOREX:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5738 MI.setDesc(get(X86::TEST8ri));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5739 return true;
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5740 case X86::MOV32ri64:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5741 MI.setDesc(get(X86::MOV32ri));
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5742 return true;
5743
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5744 // KNL does not recognize dependency-breaking idioms for mask registers,
5745 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5746 // Using %k0 as the undef input register is a performance heuristic based
5747 // on the assumption that %k0 is used less frequently than the other mask
5748 // registers, since it is not usable as a write mask.
5749 // FIXME: A more advanced approach would be to choose the best input mask
5750 // register based on context.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5751 case X86::KSET0B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5752 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5753 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5754 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5755 case X86::KSET1B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5756 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5757 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5758 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5759 case TargetOpcode::LOAD_STACK_GUARD:
5760 expandLoadStackGuard(MIB, *this);
5761 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5762 }
5763 return false;
5764}
5765
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5766static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5767 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5768 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5769
5770 if (NumAddrOps < 4) {
5771 // FrameIndex only - add an immediate offset (whether its zero or not).
5772 for (unsigned i = 0; i != NumAddrOps; ++i)
5773 MIB.addOperand(MOs[i]);
5774 addOffset(MIB, PtrOffset);
5775 } else {
5776 // General Memory Addressing - we need to add any offset to an existing
5777 // offset.
5778 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5779 for (unsigned i = 0; i != NumAddrOps; ++i) {
5780 const MachineOperand &MO = MOs[i];
5781 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5782 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5783 } else {
5784 MIB.addOperand(MO);
5785 }
5786 }
5787 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5788}
5789
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5790static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5791 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5792 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5793 MachineInstr &MI,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5794 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5795 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5796 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5797 MachineInstr *NewMI =
5798 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5799 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5800 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5801
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5802 // Loop over the rest of the ri operands, converting them over.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5803 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5804 for (unsigned i = 0; i != NumOps; ++i) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5805 MachineOperand &MO = MI.getOperand(i + 2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5806 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5807 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5808 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5809 MachineOperand &MO = MI.getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5810 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5811 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5812
5813 MachineBasicBlock *MBB = InsertPt->getParent();
5814 MBB->insert(InsertPt, NewMI);
5815
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5816 return MIB;
5817}
5818
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5819static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5820 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5821 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5822 MachineInstr &MI, const TargetInstrInfo &TII,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5823 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5824 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5825 MachineInstr *NewMI =
5826 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5827 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5828
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5829 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5830 MachineOperand &MO = MI.getOperand(i);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5831 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5832 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5833 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5834 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5835 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5836 }
5837 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5838
5839 MachineBasicBlock *MBB = InsertPt->getParent();
5840 MBB->insert(InsertPt, NewMI);
5841
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5842 return MIB;
5843}
5844
5845static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5846 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5847 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5848 MachineInstr &MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5849 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5850 MI.getDebugLoc(), TII.get(Opcode));
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5851 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5852 return MIB.addImm(0);
5853}
5854
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5855MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5856 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5857 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5858 unsigned Size, unsigned Align) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5859 switch (MI.getOpcode()) {
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5860 case X86::INSERTPSrr:
5861 case X86::VINSERTPSrr:
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5862 case X86::VINSERTPSZrr:
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5863 // Attempt to convert the load of inserted vector into a fold load
5864 // of a single float.
5865 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5866 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5867 unsigned ZMask = Imm & 15;
5868 unsigned DstIdx = (Imm >> 4) & 3;
5869 unsigned SrcIdx = (Imm >> 6) & 3;
5870
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5871 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5872 if (Size <= RCSize && 4 <= Align) {
5873 int PtrOffset = SrcIdx * 4;
5874 unsigned NewImm = (DstIdx << 4) | ZMask;
5875 unsigned NewOpCode =
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5876 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5877 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
5878 X86::INSERTPSrm;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5879 MachineInstr *NewMI =
5880 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5881 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5882 return NewMI;
5883 }
5884 }
5885 break;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5886 case X86::MOVHLPSrr:
5887 case X86::VMOVHLPSrr:
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5888 case X86::VMOVHLPSZrr:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5889 // Move the upper 64-bits of the second operand to the lower 64-bits.
5890 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5891 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5892 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5893 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5894 if (Size <= RCSize && 8 <= Align) {
5895 unsigned NewOpCode =
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5896 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5897 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
5898 X86::MOVLPSrm;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5899 MachineInstr *NewMI =
5900 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5901 return NewMI;
5902 }
5903 }
5904 break;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5905 };
5906
5907 return nullptr;
5908}
5909
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5910MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5911 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5912 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5913 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5914 const DenseMap<unsigned,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5915 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5916 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5917 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5918
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5919 // For CPUs that favor the register form of a call or push,
5920 // do not fold loads into calls or pushes, unless optimizing for size
5921 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5922 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5923 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5924 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5925 MI.getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5926 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5927
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5928 unsigned NumOps = MI.getDesc().getNumOperands();
5929 bool isTwoAddr =
5930 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5931
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5932 // FIXME: AsmPrinter doesn't know how to handle
5933 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5934 if (MI.getOpcode() == X86::ADD32ri &&
5935 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5936 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5937
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5938 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5939
5940 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5941 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5942 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5943 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5944
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5945 // Folding a memory location into the two-address part of a two-address
5946 // instruction is different than folding it other places. It requires
5947 // replacing the *two* registers with the memory location.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5948 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5949 MI.getOperand(1).isReg() &&
5950 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5951 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5952 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5953 } else if (OpNum == 0) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5954 if (MI.getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5955 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5956 if (NewMI)
5957 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5958 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5959
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5960 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5961 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5962 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5963 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5964 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5965 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]5966 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5967 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]5968 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5969 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5970
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5971 // If table selected...
5972 if (OpcodeTablePtr) {
5973 // Find the Opcode to fuse
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5974 auto I = OpcodeTablePtr->find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5975 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5976 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5977 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5978 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5979 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5980 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5981 if (Size) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5982 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5983 if (Size < RCSize) {
5984 // Check if it's safe to fold the load. If the size of the object is
5985 // narrower than the load width, then it's not.
5986 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5987 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5988 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5989 // a 32-bit load which is implicitly zero-extended. This likely is
5990 // due to live interval analysis remat'ing a load from stack slot.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5991 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5992 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5993 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5994 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5995 }
5996 }
5997
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5998 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5999 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6000 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6001 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6002
6003 if (NarrowToMOV32rm) {
6004 // If this is the special case where we use a MOV32rm to load a 32-bit
6005 // value and zero-extend the top bits. Change the destination register
6006 // to a 32-bit one.
6007 unsigned DstReg = NewMI->getOperand(0).getReg();
6008 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6009 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6010 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]6011 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6012 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6013 return NewMI;
6014 }
6015 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6016
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6017 // If the instruction and target operand are commutable, commute the
6018 // instruction and try again.
6019 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6020 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6021 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6022 bool HasDef = MI.getDesc().getNumDefs();
6023 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
6024 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
6025 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6026 bool Tied1 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6027 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6028 bool Tied2 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6029 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6030
6031 // If either of the commutable operands are tied to the destination
6032 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6033 if ((HasDef && Reg0 == Reg1 && Tied1) ||
6034 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6035 return nullptr;
6036
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6037 MachineInstr *CommutedMI =
6038 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6039 if (!CommutedMI) {
6040 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6041 return nullptr;
6042 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6043 if (CommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6044 // New instruction. We can't fold from this.
6045 CommutedMI->eraseFromParent();
6046 return nullptr;
6047 }
6048
6049 // Attempt to fold with the commuted version of the instruction.
6050 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
6051 Size, Align, /*AllowCommute=*/false);
6052 if (NewMI)
6053 return NewMI;
6054
6055 // Folding failed again - undo the commute before returning.
6056 MachineInstr *UncommutedMI =
6057 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6058 if (!UncommutedMI) {
6059 // Unable to commute.
6060 return nullptr;
6061 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6062 if (UncommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6063 // New instruction. It doesn't need to be kept.
6064 UncommutedMI->eraseFromParent();
6065 return nullptr;
6066 }
6067
6068 // Return here to prevent duplicate fuse failure report.
6069 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6070 }
6071 }
6072
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6073 // No fusion
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6074 if (PrintFailedFusing && !MI.isCopy())
6075 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6076 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6077}
6078
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6079/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6080/// the first 32 or 64-bits of the destination register and leave the rest
6081/// unmodified. This can be used to avoid folding loads if the instructions
6082/// only update part of the destination register, and the non-updated part is
6083/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6084/// instructions breaks the partial register dependency and it can improve
6085/// performance. e.g.:
6086///
6087/// movss (%rdi), %xmm0
6088/// cvtss2sd %xmm0, %xmm0
6089///
6090/// Instead of
6091/// cvtss2sd (%rdi), %xmm0
6092///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]6093/// FIXME: This should be turned into a TSFlags.
6094///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6095static bool hasPartialRegUpdate(unsigned Opcode) {
6096 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6097 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6098 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6099 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6100 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6101 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6102 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6103 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6104 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6105 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6106 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6107 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6108 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6109 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6110 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6111 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6112 case X86::Int_CVTSS2SDrm:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]6113 case X86::MOVHPDrm:
6114 case X86::MOVHPSrm:
6115 case X86::MOVLPDrm:
6116 case X86::MOVLPSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6117 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6118 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6119 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6120 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6121 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6122 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6123 case X86::ROUNDSDr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]6124 case X86::ROUNDSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6125 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6126 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6127 case X86::ROUNDSSr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]6128 case X86::ROUNDSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6129 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6130 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6131 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6132 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6133 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6134 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6135 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6136 case X86::SQRTSSm_Int:
6137 case X86::SQRTSDr:
6138 case X86::SQRTSDm:
6139 case X86::SQRTSDr_Int:
6140 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6141 return true;
6142 }
6143
6144 return false;
6145}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6146
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6147/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6148/// instructions we would like before a partial register update.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6149unsigned X86InstrInfo::getPartialRegUpdateClearance(
6150 const MachineInstr &MI, unsigned OpNum,
6151 const TargetRegisterInfo *TRI) const {
6152 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6153 return 0;
6154
6155 // If MI is marked as reading Reg, the partial register update is wanted.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6156 const MachineOperand &MO = MI.getOperand(0);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6157 unsigned Reg = MO.getReg();
6158 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6159 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6160 return 0;
6161 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6162 if (MI.readsRegister(Reg, TRI))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6163 return 0;
6164 }
6165
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6166 // If any instructions in the clearance range are reading Reg, insert a
6167 // dependency breaking instruction, which is inexpensive and is likely to
6168 // be hidden in other instruction's cycles.
6169 return PartialRegUpdateClearance;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6170}
6171
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6172// Return true for any instruction the copies the high bits of the first source
6173// operand into the unused high bits of the destination operand.
6174static bool hasUndefRegUpdate(unsigned Opcode) {
6175 switch (Opcode) {
6176 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6177 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6178 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6179 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6180 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6181 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6182 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6183 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6184 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6185 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6186 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6187 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6188 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6189 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6190 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6191 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6192 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6193 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6194 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6195 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6196 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6197 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6198 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6199 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6200 case X86::VRCPSSr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]6201 case X86::VRCPSSr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6202 case X86::VRCPSSm:
6203 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6204 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6205 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6206 case X86::VROUNDSDr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]6207 case X86::VROUNDSDm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6208 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6209 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6210 case X86::VROUNDSSr_Int:
Simon Pilgrim54c32dd2016-08-09 09:32:34 +0000[diff] [blame]6211 case X86::VROUNDSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6212 case X86::VRSQRTSSr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]6213 case X86::VRSQRTSSr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6214 case X86::VRSQRTSSm:
6215 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6216 case X86::VSQRTSSr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]6217 case X86::VSQRTSSr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6218 case X86::VSQRTSSm:
6219 case X86::VSQRTSSm_Int:
6220 case X86::VSQRTSDr:
Craig Topperf5d05fb2016-08-06 19:31:44 +0000[diff] [blame]6221 case X86::VSQRTSDr_Int:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6222 case X86::VSQRTSDm:
6223 case X86::VSQRTSDm_Int:
Craig Topper19505bc2016-08-06 19:31:50 +0000[diff] [blame]6224 // AVX-512
6225 case X86::VCVTSI2SSZrr:
6226 case X86::VCVTSI2SSZrm:
6227 case X86::Int_VCVTSI2SSZrr:
6228 case X86::Int_VCVTSI2SSZrm:
6229 case X86::VCVTSI2SSZrr_Int:
6230 case X86::VCVTSI2SSZrm_Int:
6231 case X86::VCVTSI642SSZrr:
6232 case X86::VCVTSI642SSZrm:
6233 case X86::Int_VCVTSI2SS64Zrr:
6234 case X86::Int_VCVTSI2SS64Zrm:
6235 case X86::VCVTSI642SSZrr_Int:
6236 case X86::VCVTSI642SSZrm_Int:
6237 case X86::VCVTSI2SDZrr:
6238 case X86::VCVTSI2SDZrm:
6239 case X86::Int_VCVTSI2SDZrr:
6240 case X86::Int_VCVTSI2SDZrm:
6241 case X86::VCVTSI2SDZrr_Int:
6242 case X86::VCVTSI2SDZrm_Int:
6243 case X86::VCVTSI642SDZrr:
6244 case X86::VCVTSI642SDZrm:
6245 case X86::Int_VCVTSI2SD64Zrr:
6246 case X86::Int_VCVTSI2SD64Zrm:
6247 case X86::VCVTSI642SDZrr_Int:
6248 case X86::VCVTSI642SDZrm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6249 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6250 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6251 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6252 case X86::VCVTSS2SDZrm:
Craig Topper9d8676a2016-08-06 19:31:52 +0000[diff] [blame]6253 case X86::VRNDSCALESDr:
6254 case X86::VRNDSCALESDm:
6255 case X86::VRNDSCALESSr:
6256 case X86::VRNDSCALESSm:
6257 case X86::VRCP14SSrr:
6258 case X86::VRCP14SSrm:
6259 case X86::VRSQRT14SSrr:
6260 case X86::VRSQRT14SSrm:
6261 case X86::VSQRTSSZr:
6262 case X86::VSQRTSSZr_Int:
6263 case X86::VSQRTSSZm:
6264 case X86::VSQRTSSZm_Int:
6265 case X86::VSQRTSDZr:
6266 case X86::VSQRTSDZr_Int:
6267 case X86::VSQRTSDZm:
6268 case X86::VSQRTSDZm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6269 return true;
6270 }
6271
6272 return false;
6273}
6274
6275/// Inform the ExeDepsFix pass how many idle instructions we would like before
6276/// certain undef register reads.
6277///
6278/// This catches the VCVTSI2SD family of instructions:
6279///
6280/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6281///
6282/// We should to be careful *not* to catch VXOR idioms which are presumably
6283/// handled specially in the pipeline:
6284///
6285/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6286///
6287/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6288/// high bits that are passed-through are not live.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6289unsigned
6290X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6291 const TargetRegisterInfo *TRI) const {
6292 if (!hasUndefRegUpdate(MI.getOpcode()))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6293 return 0;
6294
6295 // Set the OpNum parameter to the first source operand.
6296 OpNum = 1;
6297
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6298 const MachineOperand &MO = MI.getOperand(OpNum);
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6299 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6300 return UndefRegClearance;
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6301 }
6302 return 0;
6303}
6304
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6305void X86InstrInfo::breakPartialRegDependency(
6306 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6307 unsigned Reg = MI.getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6308 // If MI kills this register, the false dependence is already broken.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6309 if (MI.killsRegister(Reg, TRI))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6310 return;
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6311
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6312 if (X86::VR128RegClass.contains(Reg)) {
6313 // These instructions are all floating point domain, so xorps is the best
6314 // choice.
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6315 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6316 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6317 .addReg(Reg, RegState::Undef)
6318 .addReg(Reg, RegState::Undef);
6319 MI.addRegisterKilled(Reg, TRI, true);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6320 } else if (X86::VR256RegClass.contains(Reg)) {
6321 // Use vxorps to clear the full ymm register.
6322 // It wants to read and write the xmm sub-register.
6323 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6324 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6325 .addReg(XReg, RegState::Undef)
6326 .addReg(XReg, RegState::Undef)
6327 .addReg(Reg, RegState::ImplicitDefine);
6328 MI.addRegisterKilled(Reg, TRI, true);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6329 }
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6330}
6331
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6332MachineInstr *
6333X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6334 ArrayRef<unsigned> Ops,
6335 MachineBasicBlock::iterator InsertPt,
6336 int FrameIndex, LiveIntervals *LIS) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6337 // Check switch flag
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6338 if (NoFusing)
6339 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6340
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6341 // Unless optimizing for size, don't fold to avoid partial
6342 // register update stalls
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6343 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6344 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6345
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]6346 const MachineFrameInfo &MFI = MF.getFrameInfo();
6347 unsigned Size = MFI.getObjectSize(FrameIndex);
6348 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]6349 // If the function stack isn't realigned we don't want to fold instructions
6350 // that need increased alignment.
6351 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6352 Alignment =
6353 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6354 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6355 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6356 unsigned RCSize = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6357 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6358 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6359 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]6360 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6361 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6362 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6363 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6364 // Check if it's safe to fold the load. If the size of the object is
6365 // narrower than the load width, then it's not.
6366 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6367 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6368 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6369 MI.setDesc(get(NewOpc));
6370 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6371 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6372 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6373
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]6374 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6375 MachineOperand::CreateFI(FrameIndex), InsertPt,
6376 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6377}
6378
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6379/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6380/// because the latter uses contents that wouldn't be defined in the folded
6381/// version. For instance, this transformation isn't legal:
6382/// movss (%rdi), %xmm0
6383/// addps %xmm0, %xmm0
6384/// ->
6385/// addps (%rdi), %xmm0
6386///
6387/// But this one is:
6388/// movss (%rdi), %xmm0
6389/// addss %xmm0, %xmm0
6390/// ->
6391/// addss (%rdi), %xmm0
6392///
6393static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6394 const MachineInstr &UserMI,
6395 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6396 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6397 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6398 unsigned RegSize =
6399 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6400
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6401 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
6402 RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6403 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6404 // destination register is wider than 32 bits (4 bytes), and its user
6405 // instruction isn't scalar (SS).
6406 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6407 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
Craig Topper8f27f512016-08-26 07:08:00 +0000[diff] [blame]6408 case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6409 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
Simon Pilgrime14653e2016-08-24 18:40:53 +0000[diff] [blame]6410 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
6411 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6412 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6413 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
Craig Topper040b1072016-09-04 19:33:47 +0000[diff] [blame]6414 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
6415 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
6416 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
6417 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
6418 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
6419 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
6420 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
6421 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
6422 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
6423 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
6424 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
6425 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6426 return false;
6427 default:
6428 return true;
6429 }
6430 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6431
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6432 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
6433 RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6434 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6435 // destination register is wider than 64 bits (8 bytes), and its user
6436 // instruction isn't scalar (SD).
6437 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6438 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
Craig Topper8f27f512016-08-26 07:08:00 +0000[diff] [blame]6439 case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6440 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
Simon Pilgrime14653e2016-08-24 18:40:53 +0000[diff] [blame]6441 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6442 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6443 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6444 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
Craig Topper040b1072016-09-04 19:33:47 +0000[diff] [blame]6445 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
6446 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
6447 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
6448 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
6449 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
6450 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
6451 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6452 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6453 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6454 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6455 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6456 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6457 return false;
6458 default:
6459 return true;
6460 }
6461 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6462
6463 return false;
6464}
6465
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6466MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6467 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6468 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6469 LiveIntervals *LIS) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6470 // If loading from a FrameIndex, fold directly from the FrameIndex.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6471 unsigned NumOps = LoadMI.getDesc().getNumOperands();
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6472 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6473 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6474 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6475 return nullptr;
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6476 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6477 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6478
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6479 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6480 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6481
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6482 // Avoid partial register update stalls unless optimizing for size.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6483 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6484 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6485
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6486 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6487 unsigned Alignment = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6488 if (LoadMI.hasOneMemOperand())
6489 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6490 else
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6491 switch (LoadMI.getOpcode()) {
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6492 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6493 case X86::AVX512_512_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6494 Alignment = 64;
6495 break;
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6496 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6497 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6498 case X86::AVX512_256_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6499 Alignment = 32;
6500 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6501 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6502 case X86::V_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6503 case X86::AVX512_128_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6504 Alignment = 16;
6505 break;
6506 case X86::FsFLD0SD:
6507 Alignment = 8;
6508 break;
6509 case X86::FsFLD0SS:
6510 Alignment = 4;
6511 break;
6512 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6513 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6514 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6515 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6516 unsigned NewOpc = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6517 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6518 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6519 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6520 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6521 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6522 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6523 }
6524 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6525 MI.setDesc(get(NewOpc));
6526 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6527 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6528 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6529
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6530 // Make sure the subregisters match.
6531 // Otherwise we risk changing the size of the load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6532 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6533 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6534
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6535 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6536 switch (LoadMI.getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6537 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6538 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6539 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6540 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6541 case X86::AVX512_128_SET0:
6542 case X86::AVX512_256_SET0:
6543 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6544 case X86::AVX512_512_SETALLONES:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6545 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6546 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6547 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6548 // Create a constant-pool entry and operands to load from it.
6549
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6550 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6551 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6552 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6553 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6554
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6555 // x86-32 PIC requires a PIC base register for constant pools.
6556 unsigned PICBase = 0;
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]6557 if (MF.getTarget().isPositionIndependent()) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6558 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6559 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6560 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6561 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6562 // This doesn't work for several reasons.
6563 // 1. GlobalBaseReg may have been spilled.
6564 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6565 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6566 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6567
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6568 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6569 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6570 Type *Ty;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6571 unsigned Opc = LoadMI.getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6572 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6573 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6574 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6575 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6576 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6577 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6578 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6579 Opc == X86::AVX512_256_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6580 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6581 else
6582 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6583
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6584 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6585 Opc == X86::AVX512_512_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6586 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6587 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6588 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6589
6590 // Create operands to load from the constant pool entry.
6591 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6592 MOs.push_back(MachineOperand::CreateImm(1));
6593 MOs.push_back(MachineOperand::CreateReg(0, false));
6594 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6595 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6596 break;
6597 }
6598 default: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6599 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6600 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6601
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6602 // Folding a normal load. Just copy the load's address operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6603 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6604 LoadMI.operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6605 break;
6606 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6607 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6608 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6609 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6610}
6611
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6612bool X86InstrInfo::unfoldMemoryOperand(
6613 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6614 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6615 auto I = MemOp2RegOpTable.find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6616 if (I == MemOp2RegOpTable.end())
6617 return false;
6618 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6619 unsigned Index = I->second.second & TB_INDEX_MASK;
6620 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6621 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6622 if (UnfoldLoad && !FoldedLoad)
6623 return false;
6624 UnfoldLoad &= FoldedLoad;
6625 if (UnfoldStore && !FoldedStore)
6626 return false;
6627 UnfoldStore &= FoldedStore;
6628
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6629 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6630 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6631 // TODO: Check if 32-byte or greater accesses are slow too?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6632 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6633 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6634 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6635 // conservatively assume the address is unaligned. That's bad for
6636 // performance.
6637 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6638 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6639 SmallVector<MachineOperand,2> BeforeOps;
6640 SmallVector<MachineOperand,2> AfterOps;
6641 SmallVector<MachineOperand,4> ImpOps;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6642 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6643 MachineOperand &Op = MI.getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6644 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6645 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6646 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6647 ImpOps.push_back(Op);
6648 else if (i < Index)
6649 BeforeOps.push_back(Op);
6650 else if (i > Index)
6651 AfterOps.push_back(Op);
6652 }
6653
6654 // Emit the load instruction.
6655 if (UnfoldLoad) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6656 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6657 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6658 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6659 if (UnfoldStore) {
6660 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6661 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6662 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6663 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6664 MO.setIsKill(false);
6665 }
6666 }
6667 }
6668
6669 // Emit the data processing instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6670 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6671 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6672
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6673 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6674 MIB.addReg(Reg, RegState::Define);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6675 for (MachineOperand &BeforeOp : BeforeOps)
6676 MIB.addOperand(BeforeOp);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6677 if (FoldedLoad)
6678 MIB.addReg(Reg);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6679 for (MachineOperand &AfterOp : AfterOps)
6680 MIB.addOperand(AfterOp);
6681 for (MachineOperand &ImpOp : ImpOps) {
6682 MIB.addReg(ImpOp.getReg(),
6683 getDefRegState(ImpOp.isDef()) |
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6684 RegState::Implicit |
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6685 getKillRegState(ImpOp.isKill()) |
6686 getDeadRegState(ImpOp.isDead()) |
6687 getUndefRegState(ImpOp.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6688 }
6689 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6690 switch (DataMI->getOpcode()) {
6691 default: break;
6692 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6693 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6694 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6695 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6696 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6697 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6698 case X86::CMP8ri: {
6699 MachineOperand &MO0 = DataMI->getOperand(0);
6700 MachineOperand &MO1 = DataMI->getOperand(1);
6701 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6702 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6703 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6704 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6705 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6706 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6707 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6708 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6709 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6710 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6711 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6712 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6713 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6714 MO1.ChangeToRegister(MO0.getReg(), false);
6715 }
6716 }
6717 }
6718 NewMIs.push_back(DataMI);
6719
6720 // Emit the store instruction.
6721 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6722 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6723 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6724 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6725 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6726 }
6727
6728 return true;
6729}
6730
6731bool
6732X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6733 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6734 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6735 return false;
6736
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6737 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6738 if (I == MemOp2RegOpTable.end())
6739 return false;
6740 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6741 unsigned Index = I->second.second & TB_INDEX_MASK;
6742 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6743 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6744 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6745 MachineFunction &MF = DAG.getMachineFunction();
6746 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6747 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6748 std::vector<SDValue> AddrOps;
6749 std::vector<SDValue> BeforeOps;
6750 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6751 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6752 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6753 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6754 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6755 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6756 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6757 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6758 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6759 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6760 AfterOps.push_back(Op);
6761 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6762 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6763 AddrOps.push_back(Chain);
6764
6765 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6766 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6767 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6768 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6769 std::pair<MachineInstr::mmo_iterator,
6770 MachineInstr::mmo_iterator> MMOs =
6771 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6772 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6773 if (!(*MMOs.first) &&
6774 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6775 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6776 // Do not introduce a slow unaligned load.
6777 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6778 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6779 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6780 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6781 bool isAligned = (*MMOs.first) &&
6782 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6783 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6784 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6785 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6786
6787 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6788 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6789 }
6790
6791 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6792 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6793 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6794 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6795 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6796 VTs.push_back(*DstRC->vt_begin());
6797 }
6798 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6799 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6800 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6801 VTs.push_back(VT);
6802 }
6803 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6804 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6805 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6806 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6807 NewNodes.push_back(NewNode);
6808
6809 // Emit the store instruction.
6810 if (FoldedStore) {
6811 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6812 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6813 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6814 std::pair<MachineInstr::mmo_iterator,
6815 MachineInstr::mmo_iterator> MMOs =
6816 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6817 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6818 if (!(*MMOs.first) &&
6819 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6820 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6821 // Do not introduce a slow unaligned store.
6822 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6823 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6824 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6825 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6826 bool isAligned = (*MMOs.first) &&
6827 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6828 SDNode *Store =
6829 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6830 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6831 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6832
6833 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6834 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6835 }
6836
6837 return true;
6838}
6839
6840unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6841 bool UnfoldLoad, bool UnfoldStore,
6842 unsigned *LoadRegIndex) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6843 auto I = MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6844 if (I == MemOp2RegOpTable.end())
6845 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6846 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6847 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6848 if (UnfoldLoad && !FoldedLoad)
6849 return 0;
6850 if (UnfoldStore && !FoldedStore)
6851 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6852 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6853 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6854 return I->second.first;
6855}
6856
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6857bool
6858X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6859 int64_t &Offset1, int64_t &Offset2) const {
6860 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6861 return false;
6862 unsigned Opc1 = Load1->getMachineOpcode();
6863 unsigned Opc2 = Load2->getMachineOpcode();
6864 switch (Opc1) {
6865 default: return false;
6866 case X86::MOV8rm:
6867 case X86::MOV16rm:
6868 case X86::MOV32rm:
6869 case X86::MOV64rm:
6870 case X86::LD_Fp32m:
6871 case X86::LD_Fp64m:
6872 case X86::LD_Fp80m:
6873 case X86::MOVSSrm:
6874 case X86::MOVSDrm:
6875 case X86::MMX_MOVD64rm:
6876 case X86::MMX_MOVQ64rm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6877 case X86::MOVAPSrm:
6878 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6879 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6880 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6881 case X86::MOVDQArm:
6882 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6883 // AVX load instructions
6884 case X86::VMOVSSrm:
6885 case X86::VMOVSDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6886 case X86::VMOVAPSrm:
6887 case X86::VMOVUPSrm:
6888 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6889 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6890 case X86::VMOVDQArm:
6891 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6892 case X86::VMOVAPSYrm:
6893 case X86::VMOVUPSYrm:
6894 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6895 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6896 case X86::VMOVDQAYrm:
6897 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6898 // AVX512 load instructions
6899 case X86::VMOVSSZrm:
6900 case X86::VMOVSDZrm:
6901 case X86::VMOVAPSZ128rm:
6902 case X86::VMOVUPSZ128rm:
6903 case X86::VMOVAPDZ128rm:
6904 case X86::VMOVUPDZ128rm:
6905 case X86::VMOVDQU8Z128rm:
6906 case X86::VMOVDQU16Z128rm:
6907 case X86::VMOVDQA32Z128rm:
6908 case X86::VMOVDQU32Z128rm:
6909 case X86::VMOVDQA64Z128rm:
6910 case X86::VMOVDQU64Z128rm:
6911 case X86::VMOVAPSZ256rm:
6912 case X86::VMOVUPSZ256rm:
6913 case X86::VMOVAPDZ256rm:
6914 case X86::VMOVUPDZ256rm:
6915 case X86::VMOVDQU8Z256rm:
6916 case X86::VMOVDQU16Z256rm:
6917 case X86::VMOVDQA32Z256rm:
6918 case X86::VMOVDQU32Z256rm:
6919 case X86::VMOVDQA64Z256rm:
6920 case X86::VMOVDQU64Z256rm:
6921 case X86::VMOVAPSZrm:
6922 case X86::VMOVUPSZrm:
6923 case X86::VMOVAPDZrm:
6924 case X86::VMOVUPDZrm:
6925 case X86::VMOVDQU8Zrm:
6926 case X86::VMOVDQU16Zrm:
6927 case X86::VMOVDQA32Zrm:
6928 case X86::VMOVDQU32Zrm:
6929 case X86::VMOVDQA64Zrm:
6930 case X86::VMOVDQU64Zrm:
6931 case X86::KMOVBkm:
6932 case X86::KMOVWkm:
6933 case X86::KMOVDkm:
6934 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6935 break;
6936 }
6937 switch (Opc2) {
6938 default: return false;
6939 case X86::MOV8rm:
6940 case X86::MOV16rm:
6941 case X86::MOV32rm:
6942 case X86::MOV64rm:
6943 case X86::LD_Fp32m:
6944 case X86::LD_Fp64m:
6945 case X86::LD_Fp80m:
6946 case X86::MOVSSrm:
6947 case X86::MOVSDrm:
6948 case X86::MMX_MOVD64rm:
6949 case X86::MMX_MOVQ64rm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6950 case X86::MOVAPSrm:
6951 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6952 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6953 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6954 case X86::MOVDQArm:
6955 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6956 // AVX load instructions
6957 case X86::VMOVSSrm:
6958 case X86::VMOVSDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6959 case X86::VMOVAPSrm:
6960 case X86::VMOVUPSrm:
6961 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6962 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6963 case X86::VMOVDQArm:
6964 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6965 case X86::VMOVAPSYrm:
6966 case X86::VMOVUPSYrm:
6967 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6968 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6969 case X86::VMOVDQAYrm:
6970 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6971 // AVX512 load instructions
6972 case X86::VMOVSSZrm:
6973 case X86::VMOVSDZrm:
6974 case X86::VMOVAPSZ128rm:
6975 case X86::VMOVUPSZ128rm:
6976 case X86::VMOVAPDZ128rm:
6977 case X86::VMOVUPDZ128rm:
6978 case X86::VMOVDQU8Z128rm:
6979 case X86::VMOVDQU16Z128rm:
6980 case X86::VMOVDQA32Z128rm:
6981 case X86::VMOVDQU32Z128rm:
6982 case X86::VMOVDQA64Z128rm:
6983 case X86::VMOVDQU64Z128rm:
6984 case X86::VMOVAPSZ256rm:
6985 case X86::VMOVUPSZ256rm:
6986 case X86::VMOVAPDZ256rm:
6987 case X86::VMOVUPDZ256rm:
6988 case X86::VMOVDQU8Z256rm:
6989 case X86::VMOVDQU16Z256rm:
6990 case X86::VMOVDQA32Z256rm:
6991 case X86::VMOVDQU32Z256rm:
6992 case X86::VMOVDQA64Z256rm:
6993 case X86::VMOVDQU64Z256rm:
6994 case X86::VMOVAPSZrm:
6995 case X86::VMOVUPSZrm:
6996 case X86::VMOVAPDZrm:
6997 case X86::VMOVUPDZrm:
6998 case X86::VMOVDQU8Zrm:
6999 case X86::VMOVDQU16Zrm:
7000 case X86::VMOVDQA32Zrm:
7001 case X86::VMOVDQU32Zrm:
7002 case X86::VMOVDQA64Zrm:
7003 case X86::VMOVDQU64Zrm:
7004 case X86::KMOVBkm:
7005 case X86::KMOVWkm:
7006 case X86::KMOVDkm:
7007 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7008 break;
7009 }
7010
7011 // Check if chain operands and base addresses match.
7012 if (Load1->getOperand(0) != Load2->getOperand(0) ||
7013 Load1->getOperand(5) != Load2->getOperand(5))
7014 return false;
7015 // Segment operands should match as well.
7016 if (Load1->getOperand(4) != Load2->getOperand(4))
7017 return false;
7018 // Scale should be 1, Index should be Reg0.
7019 if (Load1->getOperand(1) == Load2->getOperand(1) &&
7020 Load1->getOperand(2) == Load2->getOperand(2)) {
7021 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
7022 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7023
7024 // Now let's examine the displacements.
7025 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
7026 isa<ConstantSDNode>(Load2->getOperand(3))) {
7027 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
7028 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
7029 return true;
7030 }
7031 }
7032 return false;
7033}
7034
7035bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
7036 int64_t Offset1, int64_t Offset2,
7037 unsigned NumLoads) const {
7038 assert(Offset2 > Offset1);
7039 if ((Offset2 - Offset1) / 8 > 64)
7040 return false;
7041
7042 unsigned Opc1 = Load1->getMachineOpcode();
7043 unsigned Opc2 = Load2->getMachineOpcode();
7044 if (Opc1 != Opc2)
7045 return false; // FIXME: overly conservative?
7046
7047 switch (Opc1) {
7048 default: break;
7049 case X86::LD_Fp32m:
7050 case X86::LD_Fp64m:
7051 case X86::LD_Fp80m:
7052 case X86::MMX_MOVD64rm:
7053 case X86::MMX_MOVQ64rm:
7054 return false;
7055 }
7056
7057 EVT VT = Load1->getValueType(0);
7058 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7059 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7060 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
7061 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7062 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7063 if (NumLoads >= 3)
7064 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7065 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7066 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7067 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7068 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7069 case MVT::i8:
7070 case MVT::i16:
7071 case MVT::i32:
7072 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]7073 case MVT::f32:
7074 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7075 if (NumLoads)
7076 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7077 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7078 }
7079
7080 return true;
7081}
7082
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7083bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
7084 MachineInstr &Second) const {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7085 // Check if this processor supports macro-fusion. Since this is a minor
7086 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
7087 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7088 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7089 return false;
7090
7091 enum {
7092 FuseTest,
7093 FuseCmp,
7094 FuseInc
7095 } FuseKind;
7096
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7097 switch (Second.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7098 default:
7099 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7100 case X86::JE_1:
7101 case X86::JNE_1:
7102 case X86::JL_1:
7103 case X86::JLE_1:
7104 case X86::JG_1:
7105 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7106 FuseKind = FuseInc;
7107 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7108 case X86::JB_1:
7109 case X86::JBE_1:
7110 case X86::JA_1:
7111 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7112 FuseKind = FuseCmp;
7113 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7114 case X86::JS_1:
7115 case X86::JNS_1:
7116 case X86::JP_1:
7117 case X86::JNP_1:
7118 case X86::JO_1:
7119 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7120 FuseKind = FuseTest;
7121 break;
7122 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7123 switch (First.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7124 default:
7125 return false;
7126 case X86::TEST8rr:
7127 case X86::TEST16rr:
7128 case X86::TEST32rr:
7129 case X86::TEST64rr:
7130 case X86::TEST8ri:
7131 case X86::TEST16ri:
7132 case X86::TEST32ri:
7133 case X86::TEST32i32:
7134 case X86::TEST64i32:
7135 case X86::TEST64ri32:
7136 case X86::TEST8rm:
7137 case X86::TEST16rm:
7138 case X86::TEST32rm:
7139 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]7140 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7141 case X86::AND16i16:
7142 case X86::AND16ri:
7143 case X86::AND16ri8:
7144 case X86::AND16rm:
7145 case X86::AND16rr:
7146 case X86::AND32i32:
7147 case X86::AND32ri:
7148 case X86::AND32ri8:
7149 case X86::AND32rm:
7150 case X86::AND32rr:
7151 case X86::AND64i32:
7152 case X86::AND64ri32:
7153 case X86::AND64ri8:
7154 case X86::AND64rm:
7155 case X86::AND64rr:
7156 case X86::AND8i8:
7157 case X86::AND8ri:
7158 case X86::AND8rm:
7159 case X86::AND8rr:
7160 return true;
7161 case X86::CMP16i16:
7162 case X86::CMP16ri:
7163 case X86::CMP16ri8:
7164 case X86::CMP16rm:
7165 case X86::CMP16rr:
7166 case X86::CMP32i32:
7167 case X86::CMP32ri:
7168 case X86::CMP32ri8:
7169 case X86::CMP32rm:
7170 case X86::CMP32rr:
7171 case X86::CMP64i32:
7172 case X86::CMP64ri32:
7173 case X86::CMP64ri8:
7174 case X86::CMP64rm:
7175 case X86::CMP64rr:
7176 case X86::CMP8i8:
7177 case X86::CMP8ri:
7178 case X86::CMP8rm:
7179 case X86::CMP8rr:
7180 case X86::ADD16i16:
7181 case X86::ADD16ri:
7182 case X86::ADD16ri8:
7183 case X86::ADD16ri8_DB:
7184 case X86::ADD16ri_DB:
7185 case X86::ADD16rm:
7186 case X86::ADD16rr:
7187 case X86::ADD16rr_DB:
7188 case X86::ADD32i32:
7189 case X86::ADD32ri:
7190 case X86::ADD32ri8:
7191 case X86::ADD32ri8_DB:
7192 case X86::ADD32ri_DB:
7193 case X86::ADD32rm:
7194 case X86::ADD32rr:
7195 case X86::ADD32rr_DB:
7196 case X86::ADD64i32:
7197 case X86::ADD64ri32:
7198 case X86::ADD64ri32_DB:
7199 case X86::ADD64ri8:
7200 case X86::ADD64ri8_DB:
7201 case X86::ADD64rm:
7202 case X86::ADD64rr:
7203 case X86::ADD64rr_DB:
7204 case X86::ADD8i8:
7205 case X86::ADD8mi:
7206 case X86::ADD8mr:
7207 case X86::ADD8ri:
7208 case X86::ADD8rm:
7209 case X86::ADD8rr:
7210 case X86::SUB16i16:
7211 case X86::SUB16ri:
7212 case X86::SUB16ri8:
7213 case X86::SUB16rm:
7214 case X86::SUB16rr:
7215 case X86::SUB32i32:
7216 case X86::SUB32ri:
7217 case X86::SUB32ri8:
7218 case X86::SUB32rm:
7219 case X86::SUB32rr:
7220 case X86::SUB64i32:
7221 case X86::SUB64ri32:
7222 case X86::SUB64ri8:
7223 case X86::SUB64rm:
7224 case X86::SUB64rr:
7225 case X86::SUB8i8:
7226 case X86::SUB8ri:
7227 case X86::SUB8rm:
7228 case X86::SUB8rr:
7229 return FuseKind == FuseCmp || FuseKind == FuseInc;
7230 case X86::INC16r:
7231 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7232 case X86::INC64r:
7233 case X86::INC8r:
7234 case X86::DEC16r:
7235 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7236 case X86::DEC64r:
7237 case X86::DEC8r:
7238 return FuseKind == FuseInc;
7239 }
7240}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7241
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7242bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]7243ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7244 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]7245 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7246 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7247 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7248}
7249
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7250bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7251isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7252 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7253 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7254 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7255 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7256}
7257
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7258/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7259/// the global base register value. Output instructions required to
7260/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7261///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7262/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7263///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7264unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7265 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7266 "X86-64 PIC uses RIP relative addressing");
7267
7268 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7269 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7270 if (GlobalBaseReg != 0)
7271 return GlobalBaseReg;
7272
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7273 // Create the register. The code to initialize it is inserted
7274 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7275 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]7276 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7277 X86FI->setGlobalBaseReg(GlobalBaseReg);
7278 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7279}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7280
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7281// These are the replaceable SSE instructions. Some of these have Int variants
7282// that we don't include here. We don't want to replace instructions selected
7283// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7284static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]7285 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7286 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
7287 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
7288 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
7289 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
7290 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]7291 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7292 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
7293 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
7294 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
7295 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
7296 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
7297 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
7298 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
7299 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
7300 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7301 // AVX 128-bit support
7302 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
7303 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
7304 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
7305 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
7306 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]7307 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7308 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7309 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
7310 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
7311 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
7312 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
7313 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
7314 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7315 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
7316 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]7317 // AVX 256-bit support
7318 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
7319 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
7320 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
7321 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
7322 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7323 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
7324 // AVX512 support
7325 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
7326 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7327 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7328 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7329};
7330
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7331static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7332 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]7333 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
7334 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
7335 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
7336 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
7337 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
7338 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
7339 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]7340 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
7341 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7342 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7343 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
7344 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
7345 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]7346 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
7347 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7348 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7349 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7350 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7351 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7352 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7353};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7354
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7355static const uint16_t ReplaceableInstrsAVX512[][4] = {
7356 // Two integer columns for 64-bit and 32-bit elements.
Craig Topperc48c0292016-08-01 07:55:33 +0000[diff] [blame]7357 //PackedSingle PackedDouble PackedInt PackedInt
7358 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
7359 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
7360 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
7361 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
7362 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
7363 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
7364 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
7365 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
7366 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
7367 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
7368 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
7369 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
7370 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
7371 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
7372 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7373};
7374
7375static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7376 // Two integer columns for 64-bit and 32-bit elements.
7377 //PackedSingle PackedDouble PackedInt PackedInt
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7378 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7379 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7380 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
7381 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
7382 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
7383 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
7384 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
7385 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
7386 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7387 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7388 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
7389 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
7390 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
7391 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
7392 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
7393 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
7394 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
7395 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
7396 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
7397 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
7398 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
7399 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
7400 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
7401 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7402};
7403
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7404static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7405 // Two integer columns for 64-bit and 32-bit elements.
7406 //PackedSingle PackedDouble
7407 //PackedInt PackedInt
7408 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
7409 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
7410 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7411 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7412 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
7413 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
7414 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7415 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7416 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
7417 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
7418 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
7419 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
7420 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
7421 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
7422 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
7423 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
7424 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
7425 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
7426 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
7427 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
7428 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
7429 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
7430 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
7431 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
7432 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
7433 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
7434 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
7435 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
7436 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
7437 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
7438 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
7439 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
7440 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
7441 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
7442 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7443 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7444 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
7445 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
7446 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7447 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7448 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
7449 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
7450 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
7451 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
7452 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
7453 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
7454 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
7455 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
7456 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
7457 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
7458 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
7459 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
7460 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
7461 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
7462 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
7463 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
7464 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
7465 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
7466 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
7467 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
7468 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
7469 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
7470 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
7471 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
7472 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
7473 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
7474 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
7475 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
7476 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
7477 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
7478 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
7479 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
7480 { X86::VANDPSZrmk, X86::VANDPDZrmk,
7481 X86::VPANDQZrmk, X86::VPANDDZrmk },
7482 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
7483 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
7484 { X86::VANDPSZrrk, X86::VANDPDZrrk,
7485 X86::VPANDQZrrk, X86::VPANDDZrrk },
7486 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
7487 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
7488 { X86::VORPSZrmk, X86::VORPDZrmk,
7489 X86::VPORQZrmk, X86::VPORDZrmk },
7490 { X86::VORPSZrmkz, X86::VORPDZrmkz,
7491 X86::VPORQZrmkz, X86::VPORDZrmkz },
7492 { X86::VORPSZrrk, X86::VORPDZrrk,
7493 X86::VPORQZrrk, X86::VPORDZrrk },
7494 { X86::VORPSZrrkz, X86::VORPDZrrkz,
7495 X86::VPORQZrrkz, X86::VPORDZrrkz },
7496 { X86::VXORPSZrmk, X86::VXORPDZrmk,
7497 X86::VPXORQZrmk, X86::VPXORDZrmk },
7498 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
7499 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
7500 { X86::VXORPSZrrk, X86::VXORPDZrrk,
7501 X86::VPXORQZrrk, X86::VPXORDZrrk },
7502 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
7503 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
Craig Topper00aecd92016-09-02 05:29:09 +0000[diff] [blame]7504 // Broadcast loads can be handled the same as masked operations to avoid
7505 // changing element size.
7506 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb,
7507 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb },
7508 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb,
7509 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb },
7510 { X86::VORPSZ128rmb, X86::VORPDZ128rmb,
7511 X86::VPORQZ128rmb, X86::VPORDZ128rmb },
7512 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb,
7513 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb },
7514 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb,
7515 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb },
7516 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb,
7517 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb },
7518 { X86::VORPSZ256rmb, X86::VORPDZ256rmb,
7519 X86::VPORQZ256rmb, X86::VPORDZ256rmb },
7520 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb,
7521 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb },
7522 { X86::VANDNPSZrmb, X86::VANDNPDZrmb,
7523 X86::VPANDNQZrmb, X86::VPANDNDZrmb },
7524 { X86::VANDPSZrmb, X86::VANDPDZrmb,
7525 X86::VPANDQZrmb, X86::VPANDDZrmb },
7526 { X86::VANDPSZrmb, X86::VANDPDZrmb,
7527 X86::VPANDQZrmb, X86::VPANDDZrmb },
7528 { X86::VORPSZrmb, X86::VORPDZrmb,
7529 X86::VPORQZrmb, X86::VPORDZrmb },
7530 { X86::VXORPSZrmb, X86::VXORPDZrmb,
7531 X86::VPXORQZrmb, X86::VPXORDZrmb },
7532 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7533 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7534 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk,
7535 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk },
7536 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk,
7537 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk },
7538 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk,
7539 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk },
7540 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7541 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7542 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk,
7543 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk },
7544 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk,
7545 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk },
7546 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk,
7547 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk },
7548 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk,
7549 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk },
7550 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
7551 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
7552 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
7553 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
7554 { X86::VORPSZrmbk, X86::VORPDZrmbk,
7555 X86::VPORQZrmbk, X86::VPORDZrmbk },
7556 { X86::VXORPSZrmbk, X86::VXORPDZrmbk,
7557 X86::VPXORQZrmbk, X86::VPXORDZrmbk },
7558 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7559 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7560 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7561 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7562 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz,
7563 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz },
7564 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7565 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7566 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7567 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7568 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7569 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7570 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz,
7571 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz },
7572 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7573 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7574 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz,
7575 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz },
7576 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
7577 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
7578 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
7579 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
7580 { X86::VORPSZrmbkz, X86::VORPDZrmbkz,
7581 X86::VPORQZrmbkz, X86::VPORDZrmbkz },
7582 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz,
7583 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz },
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7584};
7585
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7586// FIXME: Some shuffle and unpack instructions have equivalents in different
7587// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7588
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7589static const uint16_t *lookup(unsigned opcode, unsigned domain,
7590 ArrayRef<uint16_t[3]> Table) {
7591 for (const uint16_t (&Row)[3] : Table)
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7592 if (Row[domain-1] == opcode)
7593 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7594 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7595}
7596
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7597static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7598 ArrayRef<uint16_t[4]> Table) {
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7599 // If this is the integer domain make sure to check both integer columns.
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7600 for (const uint16_t (&Row)[4] : Table)
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7601 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7602 return Row;
7603 return nullptr;
7604}
7605
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7606std::pair<uint16_t, uint16_t>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7607X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7608 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7609 unsigned opcode = MI.getOpcode();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7610 uint16_t validDomains = 0;
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7611 if (domain) {
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7612 if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7613 validDomains = 0xe;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7614 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7615 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7616 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7617 validDomains = 0xe;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7618 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7619 validDomains = Subtarget.hasDQI() ? 0xe : 0x8;
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7620 } else if (const uint16_t *table = lookupAVX512(opcode, domain,
7621 ReplaceableInstrsAVX512DQMasked)) {
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7622 if (domain == 1 || (domain == 3 && table[3] == opcode))
7623 validDomains = Subtarget.hasDQI() ? 0xa : 0x8;
7624 else
7625 validDomains = Subtarget.hasDQI() ? 0xc : 0x8;
7626 }
7627 }
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7628 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7629}
7630
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7631void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7632 assert(Domain>0 && Domain<4 && "Invalid execution domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7633 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7634 assert(dom && "Not an SSE instruction");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7635 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7636 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7637 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7638 "256-bit vector operations only available in AVX2");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7639 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7640 }
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7641 if (!table) { // try the AVX512 table
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7642 assert(Subtarget.hasAVX512() && "Requires AVX-512");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7643 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7644 // Don't change integer Q instructions to D instructions.
Craig Topperc48c0292016-08-01 07:55:33 +0000[diff] [blame]7645 if (table && Domain == 3 && table[3] == MI.getOpcode())
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7646 Domain = 4;
7647 }
7648 if (!table) { // try the AVX512DQ table
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7649 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7650 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7651 // Don't change integer Q instructions to D instructions and
7652 // use D intructions if we started with a PS instruction.
7653 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7654 Domain = 4;
7655 }
7656 if (!table) { // try the AVX512DQMasked table
7657 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
Craig Toppera10549d2016-08-09 05:26:09 +0000[diff] [blame]7658 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
Craig Topper92a4ff12016-08-09 05:26:07 +0000[diff] [blame]7659 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7660 Domain = 4;
7661 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7662 assert(table && "Cannot change domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7663 MI.setDesc(get(table[Domain - 1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7664}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7665
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7666/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7667void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7668 NopInst.setOpcode(X86::NOOP);
7669}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7670
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7671// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7672// In particular, getJumpInstrTableEntryBound must always return an upper bound
7673// on the encoding lengths of the instructions generated by
7674// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7675void X86InstrInfo::getUnconditionalBranch(
7676 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7677 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]7678 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7679}
7680
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7681// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7682// In particular, getJumpInstrTableEntryBound must always return an upper bound
7683// on the encoding lengths of the instructions generated by
7684// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7685void X86InstrInfo::getTrap(MCInst &MI) const {
7686 MI.setOpcode(X86::TRAP);
7687}
7688
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7689// See getTrap and getUnconditionalBranch for conditions on the value returned
7690// by this function.
7691unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7692 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7693 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7694 return 5;
7695}
7696
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7697bool X86InstrInfo::isHighLatencyDef(int opc) const {
7698 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7699 default: return false;
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7700 case X86::DIVPDrm:
7701 case X86::DIVPDrr:
7702 case X86::DIVPSrm:
7703 case X86::DIVPSrr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7704 case X86::DIVSDrm:
7705 case X86::DIVSDrm_Int:
7706 case X86::DIVSDrr:
7707 case X86::DIVSDrr_Int:
7708 case X86::DIVSSrm:
7709 case X86::DIVSSrm_Int:
7710 case X86::DIVSSrr:
7711 case X86::DIVSSrr_Int:
7712 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7713 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7714 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7715 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7716 case X86::SQRTSDm:
7717 case X86::SQRTSDm_Int:
7718 case X86::SQRTSDr:
7719 case X86::SQRTSDr_Int:
7720 case X86::SQRTSSm:
7721 case X86::SQRTSSm_Int:
7722 case X86::SQRTSSr:
7723 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7724 // AVX instructions with high latency
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7725 case X86::VDIVPDrm:
7726 case X86::VDIVPDrr:
7727 case X86::VDIVPDYrm:
7728 case X86::VDIVPDYrr:
7729 case X86::VDIVPSrm:
7730 case X86::VDIVPSrr:
7731 case X86::VDIVPSYrm:
7732 case X86::VDIVPSYrr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7733 case X86::VDIVSDrm:
7734 case X86::VDIVSDrm_Int:
7735 case X86::VDIVSDrr:
7736 case X86::VDIVSDrr_Int:
7737 case X86::VDIVSSrm:
7738 case X86::VDIVSSrm_Int:
7739 case X86::VDIVSSrr:
7740 case X86::VDIVSSrr_Int:
7741 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7742 case X86::VSQRTPDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7743 case X86::VSQRTPDYm:
7744 case X86::VSQRTPDYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7745 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7746 case X86::VSQRTPSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7747 case X86::VSQRTPSYm:
7748 case X86::VSQRTPSYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7749 case X86::VSQRTSDm:
7750 case X86::VSQRTSDm_Int:
7751 case X86::VSQRTSDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7752 case X86::VSQRTSDr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7753 case X86::VSQRTSSm:
7754 case X86::VSQRTSSm_Int:
7755 case X86::VSQRTSSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7756 case X86::VSQRTSSr_Int:
7757 // AVX512 instructions with high latency
7758 case X86::VDIVPDZ128rm:
7759 case X86::VDIVPDZ128rmb:
7760 case X86::VDIVPDZ128rmbk:
7761 case X86::VDIVPDZ128rmbkz:
7762 case X86::VDIVPDZ128rmk:
7763 case X86::VDIVPDZ128rmkz:
7764 case X86::VDIVPDZ128rr:
7765 case X86::VDIVPDZ128rrk:
7766 case X86::VDIVPDZ128rrkz:
7767 case X86::VDIVPDZ256rm:
7768 case X86::VDIVPDZ256rmb:
7769 case X86::VDIVPDZ256rmbk:
7770 case X86::VDIVPDZ256rmbkz:
7771 case X86::VDIVPDZ256rmk:
7772 case X86::VDIVPDZ256rmkz:
7773 case X86::VDIVPDZ256rr:
7774 case X86::VDIVPDZ256rrk:
7775 case X86::VDIVPDZ256rrkz:
7776 case X86::VDIVPDZrb:
7777 case X86::VDIVPDZrbk:
7778 case X86::VDIVPDZrbkz:
7779 case X86::VDIVPDZrm:
7780 case X86::VDIVPDZrmb:
7781 case X86::VDIVPDZrmbk:
7782 case X86::VDIVPDZrmbkz:
7783 case X86::VDIVPDZrmk:
7784 case X86::VDIVPDZrmkz:
7785 case X86::VDIVPDZrr:
7786 case X86::VDIVPDZrrk:
7787 case X86::VDIVPDZrrkz:
7788 case X86::VDIVPSZ128rm:
7789 case X86::VDIVPSZ128rmb:
7790 case X86::VDIVPSZ128rmbk:
7791 case X86::VDIVPSZ128rmbkz:
7792 case X86::VDIVPSZ128rmk:
7793 case X86::VDIVPSZ128rmkz:
7794 case X86::VDIVPSZ128rr:
7795 case X86::VDIVPSZ128rrk:
7796 case X86::VDIVPSZ128rrkz:
7797 case X86::VDIVPSZ256rm:
7798 case X86::VDIVPSZ256rmb:
7799 case X86::VDIVPSZ256rmbk:
7800 case X86::VDIVPSZ256rmbkz:
7801 case X86::VDIVPSZ256rmk:
7802 case X86::VDIVPSZ256rmkz:
7803 case X86::VDIVPSZ256rr:
7804 case X86::VDIVPSZ256rrk:
7805 case X86::VDIVPSZ256rrkz:
7806 case X86::VDIVPSZrb:
7807 case X86::VDIVPSZrbk:
7808 case X86::VDIVPSZrbkz:
7809 case X86::VDIVPSZrm:
7810 case X86::VDIVPSZrmb:
7811 case X86::VDIVPSZrmbk:
7812 case X86::VDIVPSZrmbkz:
7813 case X86::VDIVPSZrmk:
7814 case X86::VDIVPSZrmkz:
7815 case X86::VDIVPSZrr:
7816 case X86::VDIVPSZrrk:
7817 case X86::VDIVPSZrrkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7818 case X86::VDIVSDZrm:
7819 case X86::VDIVSDZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7820 case X86::VDIVSDZrm_Int:
7821 case X86::VDIVSDZrm_Intk:
7822 case X86::VDIVSDZrm_Intkz:
7823 case X86::VDIVSDZrr_Int:
7824 case X86::VDIVSDZrr_Intk:
7825 case X86::VDIVSDZrr_Intkz:
7826 case X86::VDIVSDZrrb:
7827 case X86::VDIVSDZrrbk:
7828 case X86::VDIVSDZrrbkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7829 case X86::VDIVSSZrm:
7830 case X86::VDIVSSZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7831 case X86::VDIVSSZrm_Int:
7832 case X86::VDIVSSZrm_Intk:
7833 case X86::VDIVSSZrm_Intkz:
7834 case X86::VDIVSSZrr_Int:
7835 case X86::VDIVSSZrr_Intk:
7836 case X86::VDIVSSZrr_Intkz:
7837 case X86::VDIVSSZrrb:
7838 case X86::VDIVSSZrrbk:
7839 case X86::VDIVSSZrrbkz:
7840 case X86::VSQRTPDZ128m:
7841 case X86::VSQRTPDZ128mb:
7842 case X86::VSQRTPDZ128mbk:
7843 case X86::VSQRTPDZ128mbkz:
7844 case X86::VSQRTPDZ128mk:
7845 case X86::VSQRTPDZ128mkz:
7846 case X86::VSQRTPDZ128r:
7847 case X86::VSQRTPDZ128rk:
7848 case X86::VSQRTPDZ128rkz:
7849 case X86::VSQRTPDZ256m:
7850 case X86::VSQRTPDZ256mb:
7851 case X86::VSQRTPDZ256mbk:
7852 case X86::VSQRTPDZ256mbkz:
7853 case X86::VSQRTPDZ256mk:
7854 case X86::VSQRTPDZ256mkz:
7855 case X86::VSQRTPDZ256r:
7856 case X86::VSQRTPDZ256rk:
7857 case X86::VSQRTPDZ256rkz:
7858 case X86::VSQRTPDZm:
7859 case X86::VSQRTPDZmb:
7860 case X86::VSQRTPDZmbk:
7861 case X86::VSQRTPDZmbkz:
7862 case X86::VSQRTPDZmk:
7863 case X86::VSQRTPDZmkz:
7864 case X86::VSQRTPDZr:
7865 case X86::VSQRTPDZrb:
7866 case X86::VSQRTPDZrbk:
7867 case X86::VSQRTPDZrbkz:
7868 case X86::VSQRTPDZrk:
7869 case X86::VSQRTPDZrkz:
7870 case X86::VSQRTPSZ128m:
7871 case X86::VSQRTPSZ128mb:
7872 case X86::VSQRTPSZ128mbk:
7873 case X86::VSQRTPSZ128mbkz:
7874 case X86::VSQRTPSZ128mk:
7875 case X86::VSQRTPSZ128mkz:
7876 case X86::VSQRTPSZ128r:
7877 case X86::VSQRTPSZ128rk:
7878 case X86::VSQRTPSZ128rkz:
7879 case X86::VSQRTPSZ256m:
7880 case X86::VSQRTPSZ256mb:
7881 case X86::VSQRTPSZ256mbk:
7882 case X86::VSQRTPSZ256mbkz:
7883 case X86::VSQRTPSZ256mk:
7884 case X86::VSQRTPSZ256mkz:
7885 case X86::VSQRTPSZ256r:
7886 case X86::VSQRTPSZ256rk:
7887 case X86::VSQRTPSZ256rkz:
7888 case X86::VSQRTPSZm:
7889 case X86::VSQRTPSZmb:
7890 case X86::VSQRTPSZmbk:
7891 case X86::VSQRTPSZmbkz:
7892 case X86::VSQRTPSZmk:
7893 case X86::VSQRTPSZmkz:
7894 case X86::VSQRTPSZr:
7895 case X86::VSQRTPSZrb:
7896 case X86::VSQRTPSZrbk:
7897 case X86::VSQRTPSZrbkz:
7898 case X86::VSQRTPSZrk:
7899 case X86::VSQRTPSZrkz:
7900 case X86::VSQRTSDZm:
7901 case X86::VSQRTSDZm_Int:
7902 case X86::VSQRTSDZm_Intk:
7903 case X86::VSQRTSDZm_Intkz:
7904 case X86::VSQRTSDZr:
7905 case X86::VSQRTSDZr_Int:
7906 case X86::VSQRTSDZr_Intk:
7907 case X86::VSQRTSDZr_Intkz:
7908 case X86::VSQRTSDZrb_Int:
7909 case X86::VSQRTSDZrb_Intk:
7910 case X86::VSQRTSDZrb_Intkz:
7911 case X86::VSQRTSSZm:
7912 case X86::VSQRTSSZm_Int:
7913 case X86::VSQRTSSZm_Intk:
7914 case X86::VSQRTSSZm_Intkz:
7915 case X86::VSQRTSSZr:
7916 case X86::VSQRTSSZr_Int:
7917 case X86::VSQRTSSZr_Intk:
7918 case X86::VSQRTSSZr_Intkz:
7919 case X86::VSQRTSSZrb_Int:
7920 case X86::VSQRTSSZrb_Intk:
7921 case X86::VSQRTSSZrb_Intkz:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7922
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7923 case X86::VGATHERDPDYrm:
7924 case X86::VGATHERDPDZ128rm:
7925 case X86::VGATHERDPDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7926 case X86::VGATHERDPDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7927 case X86::VGATHERDPDrm:
7928 case X86::VGATHERDPSYrm:
7929 case X86::VGATHERDPSZ128rm:
7930 case X86::VGATHERDPSZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7931 case X86::VGATHERDPSZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7932 case X86::VGATHERDPSrm:
7933 case X86::VGATHERPF0DPDm:
7934 case X86::VGATHERPF0DPSm:
7935 case X86::VGATHERPF0QPDm:
7936 case X86::VGATHERPF0QPSm:
7937 case X86::VGATHERPF1DPDm:
7938 case X86::VGATHERPF1DPSm:
7939 case X86::VGATHERPF1QPDm:
7940 case X86::VGATHERPF1QPSm:
7941 case X86::VGATHERQPDYrm:
7942 case X86::VGATHERQPDZ128rm:
7943 case X86::VGATHERQPDZ256rm:
7944 case X86::VGATHERQPDZrm:
7945 case X86::VGATHERQPDrm:
7946 case X86::VGATHERQPSYrm:
7947 case X86::VGATHERQPSZ128rm:
7948 case X86::VGATHERQPSZ256rm:
7949 case X86::VGATHERQPSZrm:
7950 case X86::VGATHERQPSrm:
7951 case X86::VPGATHERDDYrm:
7952 case X86::VPGATHERDDZ128rm:
7953 case X86::VPGATHERDDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7954 case X86::VPGATHERDDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7955 case X86::VPGATHERDDrm:
7956 case X86::VPGATHERDQYrm:
7957 case X86::VPGATHERDQZ128rm:
7958 case X86::VPGATHERDQZ256rm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7959 case X86::VPGATHERDQZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7960 case X86::VPGATHERDQrm:
7961 case X86::VPGATHERQDYrm:
7962 case X86::VPGATHERQDZ128rm:
7963 case X86::VPGATHERQDZ256rm:
7964 case X86::VPGATHERQDZrm:
7965 case X86::VPGATHERQDrm:
7966 case X86::VPGATHERQQYrm:
7967 case X86::VPGATHERQQZ128rm:
7968 case X86::VPGATHERQQZ256rm:
7969 case X86::VPGATHERQQZrm:
7970 case X86::VPGATHERQQrm:
7971 case X86::VSCATTERDPDZ128mr:
7972 case X86::VSCATTERDPDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7973 case X86::VSCATTERDPDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7974 case X86::VSCATTERDPSZ128mr:
7975 case X86::VSCATTERDPSZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7976 case X86::VSCATTERDPSZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7977 case X86::VSCATTERPF0DPDm:
7978 case X86::VSCATTERPF0DPSm:
7979 case X86::VSCATTERPF0QPDm:
7980 case X86::VSCATTERPF0QPSm:
7981 case X86::VSCATTERPF1DPDm:
7982 case X86::VSCATTERPF1DPSm:
7983 case X86::VSCATTERPF1QPDm:
7984 case X86::VSCATTERPF1QPSm:
7985 case X86::VSCATTERQPDZ128mr:
7986 case X86::VSCATTERQPDZ256mr:
7987 case X86::VSCATTERQPDZmr:
7988 case X86::VSCATTERQPSZ128mr:
7989 case X86::VSCATTERQPSZ256mr:
7990 case X86::VSCATTERQPSZmr:
7991 case X86::VPSCATTERDDZ128mr:
7992 case X86::VPSCATTERDDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7993 case X86::VPSCATTERDDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7994 case X86::VPSCATTERDQZ128mr:
7995 case X86::VPSCATTERDQZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7996 case X86::VPSCATTERDQZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7997 case X86::VPSCATTERQDZ128mr:
7998 case X86::VPSCATTERQDZ256mr:
7999 case X86::VPSCATTERQDZmr:
8000 case X86::VPSCATTERQQZ128mr:
8001 case X86::VPSCATTERQQZ256mr:
8002 case X86::VPSCATTERQQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]8003 return true;
8004 }
8005}
8006
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]8007bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8008 const MachineRegisterInfo *MRI,
8009 const MachineInstr &DefMI,
8010 unsigned DefIdx,
8011 const MachineInstr &UseMI,
8012 unsigned UseIdx) const {
8013 return isHighLatencyDef(DefMI.getOpcode());
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]8014}
8015
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]8016bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8017 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]8018 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
8019 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]8020
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]8021 // Integer binary math/logic instructions have a third source operand:
8022 // the EFLAGS register. That operand must be both defined here and never
8023 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8024 // not change anything because rearranging the operands could affect other
8025 // instructions that depend on the exact status flags (zero, sign, etc.)
8026 // that are set by using these particular operands with this operation.
8027 if (Inst.getNumOperands() == 4) {
8028 assert(Inst.getOperand(3).isReg() &&
8029 Inst.getOperand(3).getReg() == X86::EFLAGS &&
8030 "Unexpected operand in reassociable instruction");
8031 if (!Inst.getOperand(3).isDead())
8032 return false;
8033 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]8034
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]8035 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]8036}
8037
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]8038// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]8039// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]8040// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]8041// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]8042bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]8043 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]8044 case X86::AND8rr:
8045 case X86::AND16rr:
8046 case X86::AND32rr:
8047 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]8048 case X86::OR8rr:
8049 case X86::OR16rr:
8050 case X86::OR32rr:
8051 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]8052 case X86::XOR8rr:
8053 case X86::XOR16rr:
8054 case X86::XOR32rr:
8055 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]8056 case X86::IMUL16rr:
8057 case X86::IMUL32rr:
8058 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]8059 case X86::PANDrr:
8060 case X86::PORrr:
8061 case X86::PXORrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]8062 case X86::ANDPDrr:
8063 case X86::ANDPSrr:
8064 case X86::ORPDrr:
8065 case X86::ORPSrr:
8066 case X86::XORPDrr:
8067 case X86::XORPSrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]8068 case X86::PADDBrr:
8069 case X86::PADDWrr:
8070 case X86::PADDDrr:
8071 case X86::PADDQrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]8072 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]8073 case X86::VPANDYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8074 case X86::VPANDDZ128rr:
8075 case X86::VPANDDZ256rr:
8076 case X86::VPANDDZrr:
8077 case X86::VPANDQZ128rr:
8078 case X86::VPANDQZ256rr:
8079 case X86::VPANDQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]8080 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]8081 case X86::VPORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8082 case X86::VPORDZ128rr:
8083 case X86::VPORDZ256rr:
8084 case X86::VPORDZrr:
8085 case X86::VPORQZ128rr:
8086 case X86::VPORQZ256rr:
8087 case X86::VPORQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]8088 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]8089 case X86::VPXORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8090 case X86::VPXORDZ128rr:
8091 case X86::VPXORDZ256rr:
8092 case X86::VPXORDZrr:
8093 case X86::VPXORQZ128rr:
8094 case X86::VPXORQZ256rr:
8095 case X86::VPXORQZrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]8096 case X86::VANDPDrr:
8097 case X86::VANDPSrr:
8098 case X86::VANDPDYrr:
8099 case X86::VANDPSYrr:
8100 case X86::VANDPDZ128rr:
8101 case X86::VANDPSZ128rr:
8102 case X86::VANDPDZ256rr:
8103 case X86::VANDPSZ256rr:
8104 case X86::VANDPDZrr:
8105 case X86::VANDPSZrr:
8106 case X86::VORPDrr:
8107 case X86::VORPSrr:
8108 case X86::VORPDYrr:
8109 case X86::VORPSYrr:
8110 case X86::VORPDZ128rr:
8111 case X86::VORPSZ128rr:
8112 case X86::VORPDZ256rr:
8113 case X86::VORPSZ256rr:
8114 case X86::VORPDZrr:
8115 case X86::VORPSZrr:
8116 case X86::VXORPDrr:
8117 case X86::VXORPSrr:
8118 case X86::VXORPDYrr:
8119 case X86::VXORPSYrr:
8120 case X86::VXORPDZ128rr:
8121 case X86::VXORPSZ128rr:
8122 case X86::VXORPDZ256rr:
8123 case X86::VXORPSZ256rr:
8124 case X86::VXORPDZrr:
8125 case X86::VXORPSZrr:
Craig Topper16a07442016-07-18 06:14:59 +0000[diff] [blame]8126 case X86::KADDBrr:
8127 case X86::KADDWrr:
8128 case X86::KADDDrr:
8129 case X86::KADDQrr:
8130 case X86::KANDBrr:
8131 case X86::KANDWrr:
8132 case X86::KANDDrr:
8133 case X86::KANDQrr:
8134 case X86::KORBrr:
8135 case X86::KORWrr:
8136 case X86::KORDrr:
8137 case X86::KORQrr:
8138 case X86::KXORBrr:
8139 case X86::KXORWrr:
8140 case X86::KXORDrr:
8141 case X86::KXORQrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]8142 case X86::VPADDBrr:
8143 case X86::VPADDWrr:
8144 case X86::VPADDDrr:
8145 case X86::VPADDQrr:
8146 case X86::VPADDBYrr:
8147 case X86::VPADDWYrr:
8148 case X86::VPADDDYrr:
8149 case X86::VPADDQYrr:
8150 case X86::VPADDBZ128rr:
8151 case X86::VPADDWZ128rr:
8152 case X86::VPADDDZ128rr:
8153 case X86::VPADDQZ128rr:
8154 case X86::VPADDBZ256rr:
8155 case X86::VPADDWZ256rr:
8156 case X86::VPADDDZ256rr:
8157 case X86::VPADDQZ256rr:
8158 case X86::VPADDBZrr:
8159 case X86::VPADDWZrr:
8160 case X86::VPADDDZrr:
8161 case X86::VPADDQZrr:
Craig Topper463f9492016-07-18 06:14:57 +0000[diff] [blame]8162 case X86::VPMULLWrr:
8163 case X86::VPMULLWYrr:
8164 case X86::VPMULLWZ128rr:
8165 case X86::VPMULLWZ256rr:
8166 case X86::VPMULLWZrr:
8167 case X86::VPMULLDrr:
8168 case X86::VPMULLDYrr:
8169 case X86::VPMULLDZ128rr:
8170 case X86::VPMULLDZ256rr:
8171 case X86::VPMULLDZrr:
8172 case X86::VPMULLQZ128rr:
8173 case X86::VPMULLQZ256rr:
8174 case X86::VPMULLQZrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]8175 // Normal min/max instructions are not commutative because of NaN and signed
8176 // zero semantics, but these are. Thus, there's no need to check for global
8177 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]8178 case X86::MAXCPDrr:
8179 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]8180 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]8181 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]8182 case X86::MINCPDrr:
8183 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]8184 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]8185 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]8186 case X86::VMAXCPDrr:
8187 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]8188 case X86::VMAXCPDYrr:
8189 case X86::VMAXCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8190 case X86::VMAXCPDZ128rr:
8191 case X86::VMAXCPSZ128rr:
8192 case X86::VMAXCPDZ256rr:
8193 case X86::VMAXCPSZ256rr:
8194 case X86::VMAXCPDZrr:
8195 case X86::VMAXCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]8196 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]8197 case X86::VMAXCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8198 case X86::VMAXCSDZrr:
8199 case X86::VMAXCSSZrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]8200 case X86::VMINCPDrr:
8201 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]8202 case X86::VMINCPDYrr:
8203 case X86::VMINCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8204 case X86::VMINCPDZ128rr:
8205 case X86::VMINCPSZ128rr:
8206 case X86::VMINCPDZ256rr:
8207 case X86::VMINCPSZ256rr:
8208 case X86::VMINCPDZrr:
8209 case X86::VMINCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]8210 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]8211 case X86::VMINCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8212 case X86::VMINCSDZrr:
8213 case X86::VMINCSSZrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]8214 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]8215 case X86::ADDPDrr:
8216 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]8217 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]8218 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]8219 case X86::MULPDrr:
8220 case X86::MULPSrr:
8221 case X86::MULSDrr:
8222 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]8223 case X86::VADDPDrr:
8224 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]8225 case X86::VADDPDYrr:
8226 case X86::VADDPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8227 case X86::VADDPDZ128rr:
8228 case X86::VADDPSZ128rr:
8229 case X86::VADDPDZ256rr:
8230 case X86::VADDPSZ256rr:
8231 case X86::VADDPDZrr:
8232 case X86::VADDPSZrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]8233 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]8234 case X86::VADDSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8235 case X86::VADDSDZrr:
8236 case X86::VADDSSZrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]8237 case X86::VMULPDrr:
8238 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]8239 case X86::VMULPDYrr:
8240 case X86::VMULPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8241 case X86::VMULPDZ128rr:
8242 case X86::VMULPSZ128rr:
8243 case X86::VMULPDZ256rr:
8244 case X86::VMULPSZ256rr:
8245 case X86::VMULPDZrr:
8246 case X86::VMULPSZrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]8247 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]8248 case X86::VMULSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8249 case X86::VMULSDZrr:
8250 case X86::VMULSSZrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]8251 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]8252 default:
8253 return false;
8254 }
8255}
8256
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]8257/// This is an architecture-specific helper function of reassociateOps.
8258/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]8259void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8260 MachineInstr &OldMI2,
8261 MachineInstr &NewMI1,
8262 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]8263 // Integer instructions define an implicit EFLAGS source register operand as
8264 // the third source (fourth total) operand.
8265 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
8266 return;
8267
8268 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
8269 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]8270
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]8271 MachineOperand &OldOp1 = OldMI1.getOperand(3);
8272 MachineOperand &OldOp2 = OldMI2.getOperand(3);
8273 MachineOperand &NewOp1 = NewMI1.getOperand(3);
8274 MachineOperand &NewOp2 = NewMI2.getOperand(3);
8275
8276 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
8277 "Must have dead EFLAGS operand in reassociable instruction");
8278 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
8279 "Must have dead EFLAGS operand in reassociable instruction");
8280
8281 (void)OldOp1;
8282 (void)OldOp2;
8283
8284 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
8285 "Unexpected operand in reassociable instruction");
8286 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
8287 "Unexpected operand in reassociable instruction");
8288
8289 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8290 // of this pass or other passes. The EFLAGS operands must be dead in these new
8291 // instructions because the EFLAGS operands in the original instructions must
8292 // be dead in order for reassociation to occur.
8293 NewOp1.setIsDead();
8294 NewOp2.setIsDead();
8295}
8296
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8297std::pair<unsigned, unsigned>
8298X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8299 return std::make_pair(TF, 0u);
8300}
8301
8302ArrayRef<std::pair<unsigned, const char *>>
8303X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8304 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]8305 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8306 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8307 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8308 {MO_GOT, "x86-got"},
8309 {MO_GOTOFF, "x86-gotoff"},
8310 {MO_GOTPCREL, "x86-gotpcrel"},
8311 {MO_PLT, "x86-plt"},
8312 {MO_TLSGD, "x86-tlsgd"},
8313 {MO_TLSLD, "x86-tlsld"},
8314 {MO_TLSLDM, "x86-tlsldm"},
8315 {MO_GOTTPOFF, "x86-gottpoff"},
8316 {MO_INDNTPOFF, "x86-indntpoff"},
8317 {MO_TPOFF, "x86-tpoff"},
8318 {MO_DTPOFF, "x86-dtpoff"},
8319 {MO_NTPOFF, "x86-ntpoff"},
8320 {MO_GOTNTPOFF, "x86-gotntpoff"},
8321 {MO_DLLIMPORT, "x86-dllimport"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8322 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8323 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8324 {MO_TLVP, "x86-tlvp"},
8325 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8326 {MO_SECREL, "x86-secrel"}};
8327 return makeArrayRef(TargetFlags);
8328}
8329
Dean Michael Berris40e6ba12016-09-01 01:03:22 +0000[diff] [blame]8330bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const {
8331 switch (Inst.getOpcode()) {
8332 case X86::TCRETURNdi:
8333 case X86::TCRETURNmi:
8334 case X86::TCRETURNri:
8335 case X86::TCRETURNdi64:
8336 case X86::TCRETURNmi64:
8337 case X86::TCRETURNri64:
8338 case X86::TAILJMPd:
8339 case X86::TAILJMPm:
8340 case X86::TAILJMPr:
8341 case X86::TAILJMPd64:
8342 case X86::TAILJMPm64:
8343 case X86::TAILJMPr64:
Dean Michael Berris40e6ba12016-09-01 01:03:22 +0000[diff] [blame]8344 case X86::TAILJMPm64_REX:
8345 case X86::TAILJMPr64_REX:
8346 return true;
8347 default:
8348 return false;
8349 }
8350}
8351
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8352namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]8353 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8354 /// global base register for x86-32.
8355 struct CGBR : public MachineFunctionPass {
8356 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]8357 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8358
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8359 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8360 const X86TargetMachine *TM =
8361 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8362 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8363
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]8364 // Don't do anything if this is 64-bit as 64-bit PIC
8365 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8366 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]8367 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8368
8369 // Only emit a global base reg in PIC mode.
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]8370 if (!TM->isPositionIndependent())
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8371 return false;
8372
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]8373 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8374 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8375
8376 // If we didn't need a GlobalBaseReg, don't insert code.
8377 if (GlobalBaseReg == 0)
8378 return false;
8379
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8380 // Insert the set of GlobalBaseReg into the first MBB of the function
8381 MachineBasicBlock &FirstMBB = MF.front();
8382 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8383 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8384 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8385 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8386
8387 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8388 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]8389 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8390 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]8391 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]8392
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8393 // Operand of MovePCtoStack is completely ignored by asm printer. It's
8394 // only used in JIT code emission as displacement to pc.
8395 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]8396
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8397 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
8398 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8399 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8400 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
8401 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8402 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8403 X86II::MO_GOT_ABSOLUTE_ADDRESS);
8404 }
8405
8406 return true;
8407 }
8408
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8409 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8410 return "X86 PIC Global Base Reg Initialization";
8411 }
8412
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8413 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8414 AU.setPreservesCFG();
8415 MachineFunctionPass::getAnalysisUsage(AU);
8416 }
8417 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8418}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8419
8420char CGBR::ID = 0;
8421FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]8422llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8423
8424namespace {
8425 struct LDTLSCleanup : public MachineFunctionPass {
8426 static char ID;
8427 LDTLSCleanup() : MachineFunctionPass(ID) {}
8428
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8429 bool runOnMachineFunction(MachineFunction &MF) override {
Andrew Kaylor2bee5ef2016-04-26 21:44:24 +0000[diff] [blame]8430 if (skipFunction(*MF.getFunction()))
8431 return false;
8432
8433 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8434 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8435 // No point folding accesses if there isn't at least two.
8436 return false;
8437 }
8438
8439 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8440 return VisitNode(DT->getRootNode(), 0);
8441 }
8442
8443 // Visit the dominator subtree rooted at Node in pre-order.
8444 // If TLSBaseAddrReg is non-null, then use that to replace any
8445 // TLS_base_addr instructions. Otherwise, create the register
8446 // when the first such instruction is seen, and then use it
8447 // as we encounter more instructions.
8448 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8449 MachineBasicBlock *BB = Node->getBlock();
8450 bool Changed = false;
8451
8452 // Traverse the current block.
8453 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8454 ++I) {
8455 switch (I->getOpcode()) {
8456 case X86::TLS_base_addr32:
8457 case X86::TLS_base_addr64:
8458 if (TLSBaseAddrReg)
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8459 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8460 else
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8461 I = SetRegister(*I, &TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8462 Changed = true;
8463 break;
8464 default:
8465 break;
8466 }
8467 }
8468
8469 // Visit the children of this block in the dominator tree.
8470 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8471 I != E; ++I) {
8472 Changed |= VisitNode(*I, TLSBaseAddrReg);
8473 }
8474
8475 return Changed;
8476 }
8477
8478 // Replace the TLS_base_addr instruction I with a copy from
8479 // TLSBaseAddrReg, returning the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8480 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8481 unsigned TLSBaseAddrReg) {
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8482 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8483 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8484 const bool is64Bit = STI.is64Bit();
8485 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8486
8487 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8488 MachineInstr *Copy =
8489 BuildMI(*I.getParent(), I, I.getDebugLoc(),
8490 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8491 .addReg(TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8492
8493 // Erase the TLS_base_addr instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8494 I.eraseFromParent();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8495
8496 return Copy;
8497 }
8498
8499 // Create a virtal register in *TLSBaseAddrReg, and populate it by
8500 // inserting a copy instruction after I. Returns the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8501 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8502 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8503 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8504 const bool is64Bit = STI.is64Bit();
8505 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8506
8507 // Create a virtual register for the TLS base address.
8508 MachineRegisterInfo &RegInfo = MF->getRegInfo();
8509 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8510 ? &X86::GR64RegClass
8511 : &X86::GR32RegClass);
8512
8513 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8514 MachineInstr *Next = I.getNextNode();
8515 MachineInstr *Copy =
8516 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8517 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8518 .addReg(is64Bit ? X86::RAX : X86::EAX);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8519
8520 return Copy;
8521 }
8522
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8523 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8524 return "Local Dynamic TLS Access Clean-up";
8525 }
8526
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8527 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8528 AU.setPreservesCFG();
8529 AU.addRequired<MachineDominatorTree>();
8530 MachineFunctionPass::getAnalysisUsage(AU);
8531 }
8532 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8533}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8534
8535char LDTLSCleanup::ID = 0;
8536FunctionPass*
8537llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }