Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1 | //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | f3ebc3f | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the interfaces that X86 uses to lower LLVM code into a |
| 11 | // selection DAG. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Benjamin Kramer | a7c40ef | 2014-08-13 16:26:38 +0000 | [diff] [blame] | 15 | #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H |
| 16 | #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 17 | |
Chandler Carruth | 802d755 | 2012-12-04 07:12:27 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/CallingConvLower.h" |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/SelectionDAG.h" |
Chandler Carruth | 802d755 | 2012-12-04 07:12:27 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetLowering.h" |
| 21 | #include "llvm/Target/TargetOptions.h" |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 22 | |
| 23 | namespace llvm { |
Eric Christopher | a08f30b | 2014-06-09 17:08:19 +0000 | [diff] [blame] | 24 | class X86Subtarget; |
Craig Topper | c6d4efa | 2014-03-19 06:53:25 +0000 | [diff] [blame] | 25 | class X86TargetMachine; |
| 26 | |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 27 | namespace X86ISD { |
Evan Cheng | 172fce7 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 28 | // X86 Specific DAG Nodes |
Matthias Braun | d04893f | 2015-05-07 21:33:59 +0000 | [diff] [blame] | 29 | enum NodeType : unsigned { |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 30 | // Start the numbering where the builtin ops leave off. |
Dan Gohman | ed1cf1a | 2008-09-23 18:42:32 +0000 | [diff] [blame] | 31 | FIRST_NUMBER = ISD::BUILTIN_OP_END, |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 32 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 33 | /// Bit scan forward. |
Evan Cheng | e9fbc3f | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 34 | BSF, |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 35 | /// Bit scan reverse. |
Evan Cheng | e9fbc3f | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 36 | BSR, |
| 37 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 38 | /// Double shift instructions. These correspond to |
Evan Cheng | 9c249c3 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 39 | /// X86::SHLDxx and X86::SHRDxx instructions. |
| 40 | SHLD, |
| 41 | SHRD, |
| 42 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 43 | /// Bitwise logical AND of floating point values. This corresponds |
Evan Cheng | 2dd217b | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 44 | /// to X86::ANDPS or X86::ANDPD. |
| 45 | FAND, |
| 46 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 47 | /// Bitwise logical OR of floating point values. This corresponds |
Evan Cheng | 4363e88 | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 48 | /// to X86::ORPS or X86::ORPD. |
| 49 | FOR, |
| 50 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 51 | /// Bitwise logical XOR of floating point values. This corresponds |
Evan Cheng | 72d5c25 | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 52 | /// to X86::XORPS or X86::XORPD. |
| 53 | FXOR, |
| 54 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 55 | /// Bitwise logical ANDNOT of floating point values. This |
Benjamin Kramer | 5bc180c | 2013-08-04 12:05:16 +0000 | [diff] [blame] | 56 | /// corresponds to X86::ANDNPS or X86::ANDNPD. |
| 57 | FANDN, |
| 58 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 59 | /// These operations represent an abstract X86 call |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 60 | /// instruction, which includes a bunch of information. In particular the |
| 61 | /// operands of these node are: |
| 62 | /// |
| 63 | /// #0 - The incoming token chain |
| 64 | /// #1 - The callee |
| 65 | /// #2 - The number of arg bytes the caller pushes on the stack. |
| 66 | /// #3 - The number of arg bytes the callee pops off the stack. |
| 67 | /// #4 - The value to pass in AL/AX/EAX (optional) |
| 68 | /// #5 - The value to pass in DL/DX/EDX (optional) |
| 69 | /// |
| 70 | /// The result values of these nodes are: |
| 71 | /// |
| 72 | /// #0 - The outgoing token chain |
| 73 | /// #1 - The first register result value (optional) |
| 74 | /// #2 - The second register result value (optional) |
| 75 | /// |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 76 | CALL, |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 77 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 78 | /// This operation implements the lowering for readcyclecounter. |
Andrew Lenharth | 0bf68ae | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 79 | RDTSC_DAG, |
Evan Cheng | 225a4d0 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 80 | |
Andrea Di Biagio | d1ab866 | 2014-04-24 17:18:27 +0000 | [diff] [blame] | 81 | /// X86 Read Time-Stamp Counter and Processor ID. |
| 82 | RDTSCP_DAG, |
| 83 | |
Andrea Di Biagio | 53b6830 | 2014-06-30 17:14:21 +0000 | [diff] [blame] | 84 | /// X86 Read Performance Monitoring Counters. |
| 85 | RDPMC_DAG, |
| 86 | |
Evan Cheng | 225a4d0 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 87 | /// X86 compare and logical compare instructions. |
Evan Cheng | 8070099 | 2007-09-17 17:42:53 +0000 | [diff] [blame] | 88 | CMP, COMI, UCOMI, |
Evan Cheng | 225a4d0 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 89 | |
Dan Gohman | 25a767d | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 90 | /// X86 bit-test instructions. |
| 91 | BT, |
| 92 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 93 | /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS |
| 94 | /// operand, usually produced by a CMP instruction. |
Evan Cheng | c1583db | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 95 | SETCC, |
| 96 | |
Elena Demikhovsky | 47fc44e | 2013-12-16 13:52:35 +0000 | [diff] [blame] | 97 | /// X86 Select |
Craig Topper | aeca046 | 2016-09-24 21:42:47 +0000 | [diff] [blame] | 98 | SELECT, SELECTS, |
Elena Demikhovsky | 47fc44e | 2013-12-16 13:52:35 +0000 | [diff] [blame] | 99 | |
Evan Cheng | 0e8b9e3 | 2009-12-15 00:53:42 +0000 | [diff] [blame] | 100 | // Same as SETCC except it's materialized with a sbb and the value is all |
| 101 | // one's or all zero's. |
Chris Lattner | 9edf3f5 | 2010-12-19 22:08:31 +0000 | [diff] [blame] | 102 | SETCC_CARRY, // R = carry_bit ? ~0 : 0 |
Evan Cheng | 0e8b9e3 | 2009-12-15 00:53:42 +0000 | [diff] [blame] | 103 | |
Stuart Hastings | be60549 | 2011-06-03 23:53:54 +0000 | [diff] [blame] | 104 | /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. |
| 105 | /// Operands are two FP values to compare; result is a mask of |
| 106 | /// 0s or 1s. Generally DTRT for C/C++ with NaNs. |
Elena Demikhovsky | 47fc44e | 2013-12-16 13:52:35 +0000 | [diff] [blame] | 107 | FSETCC, |
Stuart Hastings | be60549 | 2011-06-03 23:53:54 +0000 | [diff] [blame] | 108 | |
Craig Topper | 29f1a1f | 2016-09-21 06:37:54 +0000 | [diff] [blame] | 109 | /// X86 FP SETCC, similar to above, but with output as an i1 mask and |
| 110 | /// with optional rounding mode. |
| 111 | FSETCCM, FSETCCM_RND, |
| 112 | |
Chris Lattner | a492d29 | 2009-03-12 06:46:02 +0000 | [diff] [blame] | 113 | /// X86 conditional moves. Operand 0 and operand 1 are the two values |
| 114 | /// to select from. Operand 2 is the condition code, and operand 3 is the |
| 115 | /// flag operand produced by a CMP or TEST instruction. It also writes a |
| 116 | /// flag result. |
Evan Cheng | 225a4d0 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 117 | CMOV, |
Evan Cheng | 6fc3104 | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 118 | |
Dan Gohman | 4a68347 | 2009-03-23 15:40:10 +0000 | [diff] [blame] | 119 | /// X86 conditional branches. Operand 0 is the chain operand, operand 1 |
| 120 | /// is the block to branch if condition is true, operand 2 is the |
| 121 | /// condition code, and operand 3 is the flag operand produced by a CMP |
Evan Cheng | c1583db | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 122 | /// or TEST instruction. |
Evan Cheng | 6fc3104 | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 123 | BRCOND, |
Evan Cheng | a74ce62 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 124 | |
Dan Gohman | 4a68347 | 2009-03-23 15:40:10 +0000 | [diff] [blame] | 125 | /// Return with a flag operand. Operand 0 is the chain operand, operand |
| 126 | /// 1 is the number of bytes of stack to pop. |
Evan Cheng | a74ce62 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 127 | RET_FLAG, |
Evan Cheng | ae986f1 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 128 | |
Amjad Aboud | 60b5e1b | 2015-12-21 14:07:14 +0000 | [diff] [blame] | 129 | /// Return from interrupt. Operand 0 is the number of bytes to pop. |
| 130 | IRET, |
| 131 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 132 | /// Repeat fill, corresponds to X86::REP_STOSx. |
Evan Cheng | ae986f1 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 133 | REP_STOS, |
| 134 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 135 | /// Repeat move, corresponds to X86::REP_MOVSx. |
Evan Cheng | ae986f1 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 136 | REP_MOVS, |
Evan Cheng | 72d5c25 | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 137 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 138 | /// On Darwin, this node represents the result of the popl |
Evan Cheng | 5588de9 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 139 | /// at function entry, used for PIC code. |
| 140 | GlobalBaseReg, |
Evan Cheng | 1f342c2 | 2006-02-23 02:43:52 +0000 | [diff] [blame] | 141 | |
Peter Collingbourne | 7d0c869 | 2016-11-16 21:48:59 +0000 | [diff] [blame] | 142 | /// A wrapper node for TargetConstantPool, TargetJumpTable, |
| 143 | /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, |
| 144 | /// MCSymbol and TargetBlockAddress. |
Evan Cheng | e0ed6ec | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 145 | Wrapper, |
Evan Cheng | d5e905d | 2006-03-21 23:01:21 +0000 | [diff] [blame] | 146 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 147 | /// Special wrapper used under X86-64 PIC mode for RIP |
Evan Cheng | ae1cd75 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 148 | /// relative displacements. |
| 149 | WrapperRIP, |
| 150 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 151 | /// Copies a 64-bit value from the low word of an XMM vector |
Dale Johannesen | dd224d2 | 2010-09-30 23:57:10 +0000 | [diff] [blame] | 152 | /// to an MMX vector. If you think this is too close to the previous |
| 153 | /// mnemonic, so do I; blame Intel. |
| 154 | MOVDQ2Q, |
| 155 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 156 | /// Copies a 32-bit value from the low word of a MMX |
Manman Ren | acb8bec | 2012-10-30 22:15:38 +0000 | [diff] [blame] | 157 | /// vector to a GPR. |
| 158 | MMX_MOVD2W, |
| 159 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 160 | /// Copies a GPR into the low 32-bit word of a MMX vector |
Bruno Cardoso Lopes | ab9ae87 | 2015-02-05 13:23:07 +0000 | [diff] [blame] | 161 | /// and zero out the high word. |
| 162 | MMX_MOVW2D, |
| 163 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 164 | /// Extract an 8-bit value from a vector and zero extend it to |
Nate Begeman | 2d77e8e4 | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 165 | /// i32, corresponds to X86::PEXTRB. |
| 166 | PEXTRB, |
| 167 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 168 | /// Extract a 16-bit value from a vector and zero extend it to |
Evan Cheng | 5fd7c69 | 2006-03-31 21:55:24 +0000 | [diff] [blame] | 169 | /// i32, corresponds to X86::PEXTRW. |
Evan Cheng | cbffa46 | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 170 | PEXTRW, |
Evan Cheng | 5fd7c69 | 2006-03-31 21:55:24 +0000 | [diff] [blame] | 171 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 172 | /// Insert any element of a 4 x float vector into any element |
Nate Begeman | 2d77e8e4 | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 173 | /// of a destination 4 x floatvector. |
| 174 | INSERTPS, |
| 175 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 176 | /// Insert the lower 8-bits of a 32-bit value to a vector, |
Nate Begeman | 2d77e8e4 | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 177 | /// corresponds to X86::PINSRB. |
| 178 | PINSRB, |
| 179 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 180 | /// Insert the lower 16-bits of a 32-bit value to a vector, |
Evan Cheng | 5fd7c69 | 2006-03-31 21:55:24 +0000 | [diff] [blame] | 181 | /// corresponds to X86::PINSRW. |
Chris Lattner | a828850 | 2010-02-23 02:07:48 +0000 | [diff] [blame] | 182 | PINSRW, MMX_PINSRW, |
Evan Cheng | 49683ba | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 183 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 184 | /// Shuffle 16 8-bit values within a vector. |
Nate Begeman | e684da3 | 2009-02-23 08:49:38 +0000 | [diff] [blame] | 185 | PSHUFB, |
Owen Anderson | b2c80da | 2011-02-25 21:41:48 +0000 | [diff] [blame] | 186 | |
Chandler Carruth | 6ba9730 | 2015-05-30 03:20:59 +0000 | [diff] [blame] | 187 | /// Compute Sum of Absolute Differences. |
| 188 | PSADBW, |
Igor Breger | f3ded81 | 2015-08-31 13:09:30 +0000 | [diff] [blame] | 189 | /// Compute Double Block Packed Sum-Absolute-Differences |
| 190 | DBPSADBW, |
Chandler Carruth | 6ba9730 | 2015-05-30 03:20:59 +0000 | [diff] [blame] | 191 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 192 | /// Bitwise Logical AND NOT of Packed FP values. |
Bruno Cardoso Lopes | 7ba479d | 2011-07-13 21:36:47 +0000 | [diff] [blame] | 193 | ANDNP, |
Owen Anderson | b2c80da | 2011-02-25 21:41:48 +0000 | [diff] [blame] | 194 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 195 | /// Blend where the selector is an immediate. |
Elena Demikhovsky | cd3c1c4 | 2012-12-05 09:24:57 +0000 | [diff] [blame] | 196 | BLENDI, |
Nadav Rotem | 9bc178a | 2012-04-11 06:40:27 +0000 | [diff] [blame] | 197 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 198 | /// Blend where the condition has been shrunk. |
Quentin Colombet | dbe33e7 | 2014-11-06 02:25:03 +0000 | [diff] [blame] | 199 | /// This is used to emphasize that the condition mask is |
| 200 | /// no more valid for generic VSELECT optimizations. |
| 201 | SHRUNKBLEND, |
| 202 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 203 | /// Combined add and sub on an FP vector. |
Chandler Carruth | 204ad4c | 2014-09-15 20:09:47 +0000 | [diff] [blame] | 204 | ADDSUB, |
Asaf Badouh | 402ebb3 | 2015-06-03 13:41:48 +0000 | [diff] [blame] | 205 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 206 | // FP vector ops with rounding mode. |
Elena Demikhovsky | 714f23b | 2015-02-18 07:59:20 +0000 | [diff] [blame] | 207 | FADD_RND, |
| 208 | FSUB_RND, |
| 209 | FMUL_RND, |
| 210 | FDIV_RND, |
Elena Demikhovsky | 0d7e936 | 2015-05-11 06:05:05 +0000 | [diff] [blame] | 211 | FMAX_RND, |
| 212 | FMIN_RND, |
Craig Topper | d70ec9b | 2016-09-23 06:24:35 +0000 | [diff] [blame] | 213 | FSQRT_RND, FSQRTS_RND, |
Asaf Badouh | 402ebb3 | 2015-06-03 13:41:48 +0000 | [diff] [blame] | 214 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 215 | // FP vector get exponent. |
Craig Topper | d70ec9b | 2016-09-23 06:24:35 +0000 | [diff] [blame] | 216 | FGETEXP_RND, FGETEXPS_RND, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 217 | // Extract Normalized Mantissas. |
Craig Topper | d70ec9b | 2016-09-23 06:24:35 +0000 | [diff] [blame] | 218 | VGETMANT, VGETMANTS, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 219 | // FP Scale. |
Asaf Badouh | 7ec4b7a | 2015-06-28 14:30:39 +0000 | [diff] [blame] | 220 | SCALEF, |
Michael Zuckerman | 11b55b2 | 2016-05-21 11:09:53 +0000 | [diff] [blame] | 221 | SCALEFS, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 222 | |
Elena Demikhovsky | 5226638 | 2015-05-04 12:35:55 +0000 | [diff] [blame] | 223 | // Integer add/sub with unsigned saturation. |
| 224 | ADDUS, |
Benjamin Kramer | b16ccde | 2012-12-15 16:47:44 +0000 | [diff] [blame] | 225 | SUBUS, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 226 | |
Elena Demikhovsky | 5226638 | 2015-05-04 12:35:55 +0000 | [diff] [blame] | 227 | // Integer add/sub with signed saturation. |
| 228 | ADDS, |
| 229 | SUBS, |
Craig Topper | f984efb | 2011-11-19 09:02:40 +0000 | [diff] [blame] | 230 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 231 | // Unsigned Integer average. |
| 232 | AVG, |
| 233 | |
| 234 | /// Integer horizontal add/sub. |
| 235 | HADD, |
Craig Topper | f984efb | 2011-11-19 09:02:40 +0000 | [diff] [blame] | 236 | HSUB, |
| 237 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 238 | /// Floating point horizontal add/sub. |
Duncan Sands | 0e4fcb8 | 2011-09-22 20:15:48 +0000 | [diff] [blame] | 239 | FHADD, |
Duncan Sands | 0e4fcb8 | 2011-09-22 20:15:48 +0000 | [diff] [blame] | 240 | FHSUB, |
| 241 | |
Elena Demikhovsky | 5e2f8c4 | 2015-06-23 08:19:46 +0000 | [diff] [blame] | 242 | // Integer absolute value |
| 243 | ABS, |
| 244 | |
Igor Breger | 0dcd8bc | 2015-09-03 09:05:31 +0000 | [diff] [blame] | 245 | // Detect Conflicts Within a Vector |
| 246 | CONFLICT, |
| 247 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 248 | /// Floating point max and min. |
Lauro Ramos Venancio | 2518889 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 249 | FMAX, FMIN, |
Dan Gohman | 57111e7 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 250 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 251 | /// Commutative FMIN and FMAX. |
Nadav Rotem | 178250a | 2012-08-19 13:06:16 +0000 | [diff] [blame] | 252 | FMAXC, FMINC, |
| 253 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 254 | /// Floating point reciprocal-sqrt and reciprocal approximation. |
| 255 | /// Note that these typically require refinement |
Dan Gohman | 57111e7 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 256 | /// in order to obtain suitable precision. |
| 257 | FRSQRT, FRCP, |
Michael Zuckerman | a63a129 | 2016-05-21 14:44:18 +0000 | [diff] [blame] | 258 | FRSQRTS, FRCPS, |
Simon Pilgrim | 122b0de | 2016-09-04 13:28:46 +0000 | [diff] [blame] | 259 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 260 | // Thread Local Storage. |
Rafael Espindola | 3b2df10 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 261 | TLSADDR, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 262 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 263 | // Thread Local Storage. A call to get the start address |
Hans Wennborg | 789acfb | 2012-06-01 16:27:21 +0000 | [diff] [blame] | 264 | // of the TLS block for the current module. |
| 265 | TLSBASEADDR, |
| 266 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 267 | // Thread Local Storage. When calling to an OS provided |
Eric Christopher | b0e1a45 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 268 | // thunk at the address from an earlier relocation. |
| 269 | TLSCALL, |
Rafael Espindola | 3b2df10 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 270 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 271 | // Exception Handling helpers. |
Arnold Schwaighofer | 9ccea99 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 272 | EH_RETURN, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 273 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 274 | // SjLj exception handling setjmp. |
Michael Liao | 97bf363 | 2012-10-15 22:39:43 +0000 | [diff] [blame] | 275 | EH_SJLJ_SETJMP, |
| 276 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 277 | // SjLj exception handling longjmp. |
Michael Liao | 97bf363 | 2012-10-15 22:39:43 +0000 | [diff] [blame] | 278 | EH_SJLJ_LONGJMP, |
| 279 | |
Saleem Abdulrasool | d2f705d | 2016-05-31 01:48:07 +0000 | [diff] [blame] | 280 | // SjLj exception handling dispatch. |
| 281 | EH_SJLJ_SETUP_DISPATCH, |
| 282 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 283 | /// Tail call return. See X86TargetLowering::LowerCall for |
Eli Bendersky | a1c6635 | 2013-02-14 23:17:03 +0000 | [diff] [blame] | 284 | /// the list of operands. |
Anton Korobeynikov | 91460e4 | 2007-11-16 01:31:51 +0000 | [diff] [blame] | 285 | TC_RETURN, |
| 286 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 287 | // Vector move to low scalar and zero higher vector elements. |
Evan Cheng | 961339b | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 288 | VZEXT_MOVL, |
| 289 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 290 | // Vector integer zero-extend. |
Michael Liao | 1be96bb | 2012-10-23 17:34:00 +0000 | [diff] [blame] | 291 | VZEXT, |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 292 | // Vector integer signed-extend. |
Michael Liao | 1be96bb | 2012-10-23 17:34:00 +0000 | [diff] [blame] | 293 | VSEXT, |
| 294 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 295 | // Vector integer truncate. |
Elena Demikhovsky | 980c6b0 | 2013-08-29 11:56:53 +0000 | [diff] [blame] | 296 | VTRUNC, |
Igor Breger | 074a64e | 2015-07-24 17:24:15 +0000 | [diff] [blame] | 297 | // Vector integer truncate with unsigned/signed saturation. |
| 298 | VTRUNCUS, VTRUNCS, |
Elena Demikhovsky | 980c6b0 | 2013-08-29 11:56:53 +0000 | [diff] [blame] | 299 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 300 | // Vector FP extend. |
Craig Topper | a02e394 | 2016-09-23 06:24:43 +0000 | [diff] [blame] | 301 | VFPEXT, VFPEXT_RND, VFPEXTS_RND, |
Michael Liao | 34107b9 | 2012-08-14 21:24:47 +0000 | [diff] [blame] | 302 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 303 | // Vector FP round. |
Craig Topper | a02e394 | 2016-09-23 06:24:43 +0000 | [diff] [blame] | 304 | VFPROUND, VFPROUND_RND, VFPROUNDS_RND, |
Michael Liao | e999b86 | 2012-10-10 16:53:28 +0000 | [diff] [blame] | 305 | |
Igor Breger | 756c289 | 2015-12-27 13:56:16 +0000 | [diff] [blame] | 306 | // Convert a vector to mask, set bits base on MSB. |
| 307 | CVT2MASK, |
| 308 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 309 | // 128-bit vector logical left / right shift |
Craig Topper | 0946264 | 2012-01-22 19:15:14 +0000 | [diff] [blame] | 310 | VSHLDQ, VSRLDQ, |
| 311 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 312 | // Vector shift elements |
Craig Topper | 0946264 | 2012-01-22 19:15:14 +0000 | [diff] [blame] | 313 | VSHL, VSRL, VSRA, |
| 314 | |
Igor Breger | e59165c | 2016-06-20 07:05:43 +0000 | [diff] [blame] | 315 | // Vector variable shift right arithmetic. |
| 316 | // Unlike ISD::SRA, in case shift count greater then element size |
| 317 | // use sign bit to fill destination data element. |
| 318 | VSRAV, |
| 319 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 320 | // Vector shift elements by immediate |
Craig Topper | 0946264 | 2012-01-22 19:15:14 +0000 | [diff] [blame] | 321 | VSHLI, VSRLI, VSRAI, |
Nate Begeman | 8d6d4b9 | 2009-04-27 18:41:29 +0000 | [diff] [blame] | 322 | |
Michael Zuckerman | 2ddcbcf | 2016-01-12 21:19:17 +0000 | [diff] [blame] | 323 | // Bit rotate by immediate |
Michael Zuckerman | 298a680 | 2016-01-13 12:39:33 +0000 | [diff] [blame] | 324 | VROTLI, VROTRI, |
Michael Zuckerman | 2ddcbcf | 2016-01-12 21:19:17 +0000 | [diff] [blame] | 325 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 326 | // Vector packed double/float comparison. |
Craig Topper | 0b7ad76 | 2012-01-22 23:36:02 +0000 | [diff] [blame] | 327 | CMPP, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 328 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 329 | // Vector integer comparisons. |
Craig Topper | bd488437 | 2012-01-22 22:42:16 +0000 | [diff] [blame] | 330 | PCMPEQ, PCMPGT, |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 331 | // Vector integer comparisons, the result is in a mask vector. |
Elena Demikhovsky | 60b1f28 | 2013-08-13 13:24:07 +0000 | [diff] [blame] | 332 | PCMPEQM, PCMPGTM, |
| 333 | |
Asaf Badouh | 5a3a023 | 2016-02-01 15:48:21 +0000 | [diff] [blame] | 334 | MULTISHIFT, |
| 335 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 336 | /// Vector comparison generating mask bits for fp and |
Elena Demikhovsky | 60b1f28 | 2013-08-13 13:24:07 +0000 | [diff] [blame] | 337 | /// integer signed and unsigned data types. |
| 338 | CMPM, |
| 339 | CMPMU, |
Elena Demikhovsky | 29792e9 | 2015-05-07 11:24:42 +0000 | [diff] [blame] | 340 | // Vector comparison with rounding mode for FP values |
| 341 | CMPM_RND, |
Bill Wendling | 1a31767 | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 342 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 343 | // Arithmetic operations with FLAGS results. |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 344 | ADD, SUB, ADC, SBB, SMUL, |
Dan Gohman | 722b1ee | 2009-09-18 19:59:53 +0000 | [diff] [blame] | 345 | INC, DEC, OR, XOR, AND, |
Owen Anderson | b2c80da | 2011-02-25 21:41:48 +0000 | [diff] [blame] | 346 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 347 | // Bit field extract. |
| 348 | BEXTR, |
Craig Topper | 039a790 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 349 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 350 | // LOW, HI, FLAGS = umul LHS, RHS. |
| 351 | UMUL, |
Evan Cheng | a84a318 | 2009-03-30 21:36:47 +0000 | [diff] [blame] | 352 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 353 | // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS. |
Ahmed Bougacha | 5175bcf | 2014-10-23 21:55:31 +0000 | [diff] [blame] | 354 | SMUL8, UMUL8, |
| 355 | |
Ahmed Bougacha | 12eb558 | 2014-11-03 20:26:35 +0000 | [diff] [blame] | 356 | // 8-bit divrem that zero-extend the high result (AH). |
| 357 | UDIVREM8_ZEXT_HREG, |
| 358 | SDIVREM8_SEXT_HREG, |
| 359 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 360 | // X86-specific multiply by immediate. |
Eric Christopher | f7802a3 | 2009-07-29 00:28:05 +0000 | [diff] [blame] | 361 | MUL_IMM, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 362 | |
Simon Pilgrim | cd0dfc9 | 2016-04-03 18:22:03 +0000 | [diff] [blame] | 363 | // Vector sign bit extraction. |
| 364 | MOVMSK, |
| 365 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 366 | // Vector bitwise comparisons. |
Dan Gohman | 0700a56 | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 367 | PTEST, |
| 368 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 369 | // Vector packed fp sign bitwise comparisons. |
Bruno Cardoso Lopes | 91d61df | 2010-08-10 23:25:42 +0000 | [diff] [blame] | 370 | TESTP, |
| 371 | |
Sanjay Patel | 36a2dc8 | 2015-03-03 20:58:35 +0000 | [diff] [blame] | 372 | // Vector "test" in AVX-512, the result is in a mask vector. |
Elena Demikhovsky | 33d447a | 2013-08-21 09:36:02 +0000 | [diff] [blame] | 373 | TESTM, |
Elena Demikhovsky | a30e437 | 2014-02-05 07:05:03 +0000 | [diff] [blame] | 374 | TESTNM, |
Elena Demikhovsky | 33d447a | 2013-08-21 09:36:02 +0000 | [diff] [blame] | 375 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 376 | // OR/AND test for masks. |
Elena Demikhovsky | 40864b6 | 2013-08-05 08:52:21 +0000 | [diff] [blame] | 377 | KORTEST, |
Igor Breger | 5ea0a681 | 2015-08-31 13:30:19 +0000 | [diff] [blame] | 378 | KTEST, |
Elena Demikhovsky | 40864b6 | 2013-08-05 08:52:21 +0000 | [diff] [blame] | 379 | |
Bruno Cardoso Lopes | 6f3b38a | 2010-08-20 22:55:05 +0000 | [diff] [blame] | 380 | // Several flavors of instructions with vector shuffle behaviors. |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 381 | // Saturated signed/unnsigned packing. |
Chandler Carruth | 8366ceb | 2014-06-20 01:05:28 +0000 | [diff] [blame] | 382 | PACKSS, |
| 383 | PACKUS, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 384 | // Intra-lane alignr. |
Craig Topper | 8fb09f0 | 2013-01-28 06:48:25 +0000 | [diff] [blame] | 385 | PALIGNR, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 386 | // AVX512 inter-lane alignr. |
Adam Nemet | 2f10cc6 | 2014-08-05 17:22:55 +0000 | [diff] [blame] | 387 | VALIGN, |
Bruno Cardoso Lopes | 6f3b38a | 2010-08-20 22:55:05 +0000 | [diff] [blame] | 388 | PSHUFD, |
| 389 | PSHUFHW, |
| 390 | PSHUFLW, |
Craig Topper | 6e54ba7 | 2011-12-31 23:50:21 +0000 | [diff] [blame] | 391 | SHUFP, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 392 | //Shuffle Packed Values at 128-bit granularity. |
Elena Demikhovsky | 9e38086 | 2015-06-03 10:56:40 +0000 | [diff] [blame] | 393 | SHUF128, |
Bruno Cardoso Lopes | 6f3b38a | 2010-08-20 22:55:05 +0000 | [diff] [blame] | 394 | MOVDDUP, |
| 395 | MOVSHDUP, |
| 396 | MOVSLDUP, |
Bruno Cardoso Lopes | 6f3b38a | 2010-08-20 22:55:05 +0000 | [diff] [blame] | 397 | MOVLHPS, |
Bruno Cardoso Lopes | 6f3b38a | 2010-08-20 22:55:05 +0000 | [diff] [blame] | 398 | MOVLHPD, |
Bruno Cardoso Lopes | 03e4c35 | 2010-08-31 21:15:21 +0000 | [diff] [blame] | 399 | MOVHLPS, |
Bruno Cardoso Lopes | b382521 | 2010-09-01 05:08:25 +0000 | [diff] [blame] | 400 | MOVLPS, |
| 401 | MOVLPD, |
Bruno Cardoso Lopes | 6f3b38a | 2010-08-20 22:55:05 +0000 | [diff] [blame] | 402 | MOVSD, |
| 403 | MOVSS, |
Craig Topper | 8d4ba19 | 2011-12-06 08:21:25 +0000 | [diff] [blame] | 404 | UNPCKL, |
| 405 | UNPCKH, |
Chandler Carruth | 6d5916a | 2014-09-23 10:08:29 +0000 | [diff] [blame] | 406 | VPERMILPV, |
Chandler Carruth | ed5dfff | 2014-09-22 22:29:42 +0000 | [diff] [blame] | 407 | VPERMILPI, |
Craig Topper | b86fa40 | 2012-04-16 00:41:45 +0000 | [diff] [blame] | 408 | VPERMI, |
Craig Topper | 0a672ea | 2011-11-30 07:47:51 +0000 | [diff] [blame] | 409 | VPERM2X128, |
Ahmed Bougacha | 671795a | 2016-03-03 16:53:50 +0000 | [diff] [blame] | 410 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 411 | // Variable Permute (VPERM). |
Ahmed Bougacha | 671795a | 2016-03-03 16:53:50 +0000 | [diff] [blame] | 412 | // Res = VPERMV MaskV, V0 |
| 413 | VPERMV, |
| 414 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 415 | // 3-op Variable Permute (VPERMT2). |
Ahmed Bougacha | 671795a | 2016-03-03 16:53:50 +0000 | [diff] [blame] | 416 | // Res = VPERMV3 V0, MaskV, V1 |
| 417 | VPERMV3, |
| 418 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 419 | // 3-op Variable Permute overwriting the index (VPERMI2). |
Ahmed Bougacha | 671795a | 2016-03-03 16:53:50 +0000 | [diff] [blame] | 420 | // Res = VPERMIV3 V0, MaskV, V1 |
| 421 | VPERMIV3, |
| 422 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 423 | // Bitwise ternary logic. |
Igor Breger | b4bb190 | 2015-10-15 12:33:24 +0000 | [diff] [blame] | 424 | VPTERNLOG, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 425 | // Fix Up Special Packed Float32/64 values. |
Elena Demikhovsky | 42c96d9 | 2015-06-01 06:50:49 +0000 | [diff] [blame] | 426 | VFIXUPIMM, |
Asaf Badouh | d4a0d9a | 2016-01-19 14:21:39 +0000 | [diff] [blame] | 427 | VFIXUPIMMS, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 428 | // Range Restriction Calculation For Packed Pairs of Float32/64 values. |
Elena Demikhovsky | 3582eb3 | 2015-06-01 11:05:34 +0000 | [diff] [blame] | 429 | VRANGE, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 430 | // Reduce - Perform Reduction Transformation on scalar\packed FP. |
Craig Topper | d70ec9b | 2016-09-23 06:24:35 +0000 | [diff] [blame] | 431 | VREDUCE, VREDUCES, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 432 | // RndScale - Round FP Values To Include A Given Number Of Fraction Bits. |
Craig Topper | d70ec9b | 2016-09-23 06:24:35 +0000 | [diff] [blame] | 433 | VRNDSCALE, VRNDSCALES, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 434 | // Tests Types Of a FP Values for packed types. |
| 435 | VFPCLASS, |
| 436 | // Tests Types Of a FP Values for scalar types. |
| 437 | VFPCLASSS, |
| 438 | |
| 439 | // Broadcast scalar to vector. |
Bruno Cardoso Lopes | be5e987 | 2011-08-17 02:29:19 +0000 | [diff] [blame] | 440 | VBROADCAST, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 441 | // Broadcast mask to vector. |
Asaf Badouh | 0d957b8 | 2015-11-18 09:42:45 +0000 | [diff] [blame] | 442 | VBROADCASTM, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 443 | // Broadcast subvector to vector. |
Elena Demikhovsky | ad9c396 | 2015-05-18 06:42:57 +0000 | [diff] [blame] | 444 | SUBV_BROADCAST, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 445 | |
| 446 | // Insert/Extract vector element. |
Elena Demikhovsky | 8952974 | 2013-09-12 08:55:00 +0000 | [diff] [blame] | 447 | VINSERT, |
Elena Demikhovsky | 9f423d6 | 2014-02-10 07:02:39 +0000 | [diff] [blame] | 448 | VEXTRACT, |
Bruno Cardoso Lopes | 6f3b38a | 2010-08-20 22:55:05 +0000 | [diff] [blame] | 449 | |
Simon Pilgrim | d85cae3 | 2015-07-06 20:46:41 +0000 | [diff] [blame] | 450 | /// SSE4A Extraction and Insertion. |
| 451 | EXTRQI, INSERTQI, |
| 452 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 453 | // XOP variable/immediate rotations. |
Simon Pilgrim | 86c5e85 | 2015-10-17 19:04:24 +0000 | [diff] [blame] | 454 | VPROT, VPROTI, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 455 | // XOP arithmetic/logical shifts. |
Simon Pilgrim | 3d11c99 | 2015-09-30 08:17:50 +0000 | [diff] [blame] | 456 | VPSHA, VPSHL, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 457 | // XOP signed/unsigned integer comparisons. |
Simon Pilgrim | 52d47e5 | 2015-10-11 14:15:17 +0000 | [diff] [blame] | 458 | VPCOM, VPCOMU, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 459 | // XOP packed permute bytes. |
Simon Pilgrim | 572ca71 | 2016-03-24 11:52:43 +0000 | [diff] [blame] | 460 | VPPERM, |
Simon Pilgrim | e85506b | 2016-06-03 08:06:03 +0000 | [diff] [blame] | 461 | // XOP two source permutation. |
| 462 | VPERMIL2, |
Simon Pilgrim | 3d11c99 | 2015-09-30 08:17:50 +0000 | [diff] [blame] | 463 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 464 | // Vector multiply packed unsigned doubleword integers. |
Craig Topper | 1d471e3 | 2012-02-05 03:14:49 +0000 | [diff] [blame] | 465 | PMULUDQ, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 466 | // Vector multiply packed signed doubleword integers. |
Benjamin Kramer | 6d2dff6 | 2014-04-26 14:12:19 +0000 | [diff] [blame] | 467 | PMULDQ, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 468 | // Vector Multiply Packed UnsignedIntegers with Round and Scale. |
Asaf Badouh | c6f3c82 | 2015-07-06 14:03:40 +0000 | [diff] [blame] | 469 | MULHRS, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 470 | |
| 471 | // Multiply and Add Packed Integers. |
Igor Breger | f7fd547 | 2015-07-21 07:11:28 +0000 | [diff] [blame] | 472 | VPMADDUBSW, VPMADDWD, |
Asaf Badouh | 655822a | 2016-01-25 11:14:24 +0000 | [diff] [blame] | 473 | VPMADD52L, VPMADD52H, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 474 | |
| 475 | // FMA nodes. |
Elena Demikhovsky | 3cb3b00 | 2012-08-01 12:06:00 +0000 | [diff] [blame] | 476 | FMADD, |
| 477 | FNMADD, |
| 478 | FMSUB, |
| 479 | FNMSUB, |
| 480 | FMADDSUB, |
| 481 | FMSUBADD, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 482 | |
| 483 | // FMA with rounding mode. |
Elena Demikhovsky | 7b0dd39 | 2015-01-28 10:21:27 +0000 | [diff] [blame] | 484 | FMADD_RND, |
| 485 | FNMADD_RND, |
| 486 | FMSUB_RND, |
| 487 | FNMSUB_RND, |
| 488 | FMADDSUB_RND, |
Elena Demikhovsky | 52e81bc | 2015-02-23 15:12:31 +0000 | [diff] [blame] | 489 | FMSUBADD_RND, |
Elena Demikhovsky | 3cb3b00 | 2012-08-01 12:06:00 +0000 | [diff] [blame] | 490 | |
Craig Topper | a55b483 | 2016-12-09 06:42:28 +0000 | [diff] [blame] | 491 | // Scalar intrinsic FMA with rounding mode. |
| 492 | // Two versions, passthru bits on op1 or op3. |
| 493 | FMADDS1_RND, FMADDS3_RND, |
| 494 | FNMADDS1_RND, FNMADDS3_RND, |
| 495 | FMSUBS1_RND, FMSUBS3_RND, |
| 496 | FNMSUBS1_RND, FNMSUBS3_RND, |
| 497 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 498 | // Compress and expand. |
Elena Demikhovsky | 908dbf4 | 2014-12-11 15:02:24 +0000 | [diff] [blame] | 499 | COMPRESS, |
| 500 | EXPAND, |
| 501 | |
Craig Topper | 3174b6e | 2016-09-23 06:24:39 +0000 | [diff] [blame] | 502 | // Convert Unsigned/Integer to Floating-Point Value with rounding mode. |
| 503 | SINT_TO_FP_RND, UINT_TO_FP_RND, |
| 504 | SCALAR_SINT_TO_FP_RND, SCALAR_UINT_TO_FP_RND, |
Elena Demikhovsky | 0f37093 | 2015-07-13 13:26:20 +0000 | [diff] [blame] | 505 | |
| 506 | // Vector float/double to signed/unsigned integer. |
Craig Topper | 3174b6e | 2016-09-23 06:24:39 +0000 | [diff] [blame] | 507 | CVTP2SI, CVTP2UI, CVTP2SI_RND, CVTP2UI_RND, |
Asaf Badouh | ad5c3fc | 2016-02-07 14:59:13 +0000 | [diff] [blame] | 508 | // Scalar float/double to signed/unsigned integer. |
Craig Topper | 3174b6e | 2016-09-23 06:24:39 +0000 | [diff] [blame] | 509 | CVTS2SI_RND, CVTS2UI_RND, |
| 510 | |
| 511 | // Vector float/double to signed/unsigned integer with truncation. |
Simon Pilgrim | a3af796 | 2016-11-24 12:13:46 +0000 | [diff] [blame] | 512 | CVTTP2SI, CVTTP2UI, CVTTP2SI_RND, CVTTP2UI_RND, |
Craig Topper | 3174b6e | 2016-09-23 06:24:39 +0000 | [diff] [blame] | 513 | // Scalar float/double to signed/unsigned integer with truncation. |
| 514 | CVTTS2SI_RND, CVTTS2UI_RND, |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 515 | |
Simon Pilgrim | a3af796 | 2016-11-24 12:13:46 +0000 | [diff] [blame] | 516 | // Vector signed/unsigned integer to float/double. |
| 517 | CVTSI2P, CVTUI2P, |
| 518 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 519 | // Save xmm argument registers to the stack, according to %al. An operator |
| 520 | // is needed so that this can be expanded with control flow. |
Dan Gohman | 48b185d | 2009-09-25 20:36:54 +0000 | [diff] [blame] | 521 | VASTART_SAVE_XMM_REGS, |
| 522 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 523 | // Windows's _chkstk call to do stack probing. |
Michael J. Spencer | f509c6c | 2010-10-21 01:41:01 +0000 | [diff] [blame] | 524 | WIN_ALLOCA, |
Anton Korobeynikov | d5e3fd6 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 525 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 526 | // For allocating variable amounts of stack space when using |
Rafael Espindola | 3353017 | 2011-08-30 19:43:21 +0000 | [diff] [blame] | 527 | // segmented stacks. Check if the current stacklet has enough space, and |
Rafael Espindola | 9d96c94 | 2011-09-06 19:29:31 +0000 | [diff] [blame] | 528 | // falls back to heap allocation if not. |
Rafael Espindola | 3353017 | 2011-08-30 19:43:21 +0000 | [diff] [blame] | 529 | SEG_ALLOCA, |
| 530 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 531 | // Memory barriers. |
Duncan Sands | 7c601de | 2010-11-20 11:25:00 +0000 | [diff] [blame] | 532 | MEMBARRIER, |
| 533 | MFENCE, |
Duncan Sands | 7c601de | 2010-11-20 11:25:00 +0000 | [diff] [blame] | 534 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 535 | // Store FP status word into i16 register. |
Benjamin Kramer | 913da4b | 2012-04-27 12:07:43 +0000 | [diff] [blame] | 536 | FNSTSW16r, |
| 537 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 538 | // Store contents of %ah into %eflags. |
Benjamin Kramer | 913da4b | 2012-04-27 12:07:43 +0000 | [diff] [blame] | 539 | SAHF, |
| 540 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 541 | // Get a random integer and indicate whether it is valid in CF. |
Benjamin Kramer | 0ab2794 | 2012-07-12 09:31:43 +0000 | [diff] [blame] | 542 | RDRAND, |
| 543 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 544 | // Get a NIST SP800-90B & C compliant random integer and |
Michael Liao | a486a11 | 2013-03-28 23:41:26 +0000 | [diff] [blame] | 545 | // indicate whether it is valid in CF. |
| 546 | RDSEED, |
| 547 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 548 | // SSE42 string comparisons. |
Craig Topper | ab47fe4 | 2012-08-06 06:22:36 +0000 | [diff] [blame] | 549 | PCMPISTRI, |
| 550 | PCMPESTRI, |
| 551 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 552 | // Test if in transactional execution. |
Michael Liao | 03f9ad0 | 2013-03-26 22:47:01 +0000 | [diff] [blame] | 553 | XTEST, |
| 554 | |
Simon Pilgrim | 20d1d4f | 2016-04-03 14:14:32 +0000 | [diff] [blame] | 555 | // ERI instructions. |
Craig Topper | d70ec9b | 2016-09-23 06:24:35 +0000 | [diff] [blame] | 556 | RSQRT28, RSQRT28S, RCP28, RCP28S, EXP2, |
Elena Demikhovsky | be8808d | 2014-11-12 07:31:03 +0000 | [diff] [blame] | 557 | |
Craig Topper | e18258d | 2016-09-21 02:05:22 +0000 | [diff] [blame] | 558 | // Conversions between float and half-float. |
| 559 | CVTPS2PH, CVTPH2PS, |
| 560 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 561 | // Compare and swap. |
Tim Northover | 277066a | 2014-07-01 18:53:31 +0000 | [diff] [blame] | 562 | LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, |
Chris Lattner | 54e5329 | 2010-09-22 00:34:38 +0000 | [diff] [blame] | 563 | LCMPXCHG8_DAG, |
Eli Friedman | 5e57042 | 2011-08-26 21:21:21 +0000 | [diff] [blame] | 564 | LCMPXCHG16_DAG, |
Quentin Colombet | cf9732b | 2016-03-12 02:25:27 +0000 | [diff] [blame] | 565 | LCMPXCHG8_SAVE_EBX_DAG, |
| 566 | LCMPXCHG16_SAVE_RBX_DAG, |
Anton Korobeynikov | d5e3fd6 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 567 | |
Ahmed Bougacha | bb5d7d7 | 2016-02-29 19:28:07 +0000 | [diff] [blame] | 568 | /// LOCK-prefixed arithmetic read-modify-write instructions. |
| 569 | /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS) |
| 570 | LADD, LSUB, LOR, LXOR, LAND, |
| 571 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 572 | // Load, scalar_to_vector, and zero extend. |
Chris Lattner | 78f518b | 2010-09-22 01:05:16 +0000 | [diff] [blame] | 573 | VZEXT_LOAD, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 574 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 575 | // Store FP control world into i16 memory. |
Chris Lattner | ed85da5 | 2010-09-22 01:11:26 +0000 | [diff] [blame] | 576 | FNSTCW16m, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 577 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 578 | /// This instruction implements FP_TO_SINT with the |
Chris Lattner | 78f518b | 2010-09-22 01:05:16 +0000 | [diff] [blame] | 579 | /// integer destination in memory and a FP reg source. This corresponds |
| 580 | /// to the X86::FIST*m instructions and the rounding mode change stuff. It |
| 581 | /// has two inputs (token chain and address) and two outputs (int value |
| 582 | /// and token chain). |
| 583 | FP_TO_INT16_IN_MEM, |
| 584 | FP_TO_INT32_IN_MEM, |
Chris Lattner | a5156c3 | 2010-09-22 01:28:21 +0000 | [diff] [blame] | 585 | FP_TO_INT64_IN_MEM, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 586 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 587 | /// This instruction implements SINT_TO_FP with the |
Chris Lattner | a5156c3 | 2010-09-22 01:28:21 +0000 | [diff] [blame] | 588 | /// integer source in memory and FP reg result. This corresponds to the |
| 589 | /// X86::FILD*m instructions. It has three inputs (token chain, address, |
| 590 | /// and source type) and two outputs (FP value and token chain). FILD_FLAG |
| 591 | /// also produces a flag). |
| 592 | FILD, |
| 593 | FILD_FLAG, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 594 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 595 | /// This instruction implements an extending load to FP stack slots. |
Chris Lattner | a5156c3 | 2010-09-22 01:28:21 +0000 | [diff] [blame] | 596 | /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain |
| 597 | /// operand, ptr to load from, and a ValueType node indicating the type |
| 598 | /// to load to. |
| 599 | FLD, |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 600 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 601 | /// This instruction implements a truncating store to FP stack |
Chris Lattner | a5156c3 | 2010-09-22 01:28:21 +0000 | [diff] [blame] | 602 | /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a |
| 603 | /// chain operand, value to store, address, and a ValueType to store it |
| 604 | /// as. |
Dan Gohman | 395a898 | 2010-10-12 18:00:49 +0000 | [diff] [blame] | 605 | FST, |
| 606 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 607 | /// This instruction grabs the address of the next argument |
Dan Gohman | 395a898 | 2010-10-12 18:00:49 +0000 | [diff] [blame] | 608 | /// from a va_list. (reads and modifies the va_list in memory) |
| 609 | VAARG_64 |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 610 | |
Anton Korobeynikov | d5e3fd6 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 611 | // WARNING: Do not add anything in the end unless you want the node to |
Ahmed Bougacha | ffcab7b | 2016-02-26 22:59:57 +0000 | [diff] [blame] | 612 | // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all |
| 613 | // opcodes will be thought as target memory ops! |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 614 | }; |
Eugene Zelenko | 6ac3f73 | 2016-01-26 18:48:36 +0000 | [diff] [blame] | 615 | } // end namespace X86ISD |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 616 | |
Evan Cheng | 084a1cd | 2008-01-29 19:34:22 +0000 | [diff] [blame] | 617 | /// Define some predicates that are used for node matching. |
| 618 | namespace X86 { |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 619 | /// Return true if the specified |
David Greene | c4da110 | 2011-02-03 15:50:00 +0000 | [diff] [blame] | 620 | /// EXTRACT_SUBVECTOR operand specifies a vector extract that is |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 621 | /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions. |
| 622 | bool isVEXTRACT128Index(SDNode *N); |
David Greene | c4da110 | 2011-02-03 15:50:00 +0000 | [diff] [blame] | 623 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 624 | /// Return true if the specified |
David Greene | 653f1ee | 2011-02-04 16:08:29 +0000 | [diff] [blame] | 625 | /// INSERT_SUBVECTOR operand specifies a subvector insert that is |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 626 | /// suitable for input to VINSERTF128, VINSERTI128 instructions. |
| 627 | bool isVINSERT128Index(SDNode *N); |
David Greene | 653f1ee | 2011-02-04 16:08:29 +0000 | [diff] [blame] | 628 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 629 | /// Return true if the specified |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 630 | /// EXTRACT_SUBVECTOR operand specifies a vector extract that is |
| 631 | /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions. |
| 632 | bool isVEXTRACT256Index(SDNode *N); |
| 633 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 634 | /// Return true if the specified |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 635 | /// INSERT_SUBVECTOR operand specifies a subvector insert that is |
| 636 | /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions. |
| 637 | bool isVINSERT256Index(SDNode *N); |
| 638 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 639 | /// Return the appropriate |
David Greene | c4da110 | 2011-02-03 15:50:00 +0000 | [diff] [blame] | 640 | /// immediate to extract the specified EXTRACT_SUBVECTOR index |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 641 | /// with VEXTRACTF128, VEXTRACTI128 instructions. |
| 642 | unsigned getExtractVEXTRACT128Immediate(SDNode *N); |
David Greene | c4da110 | 2011-02-03 15:50:00 +0000 | [diff] [blame] | 643 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 644 | /// Return the appropriate |
David Greene | 653f1ee | 2011-02-04 16:08:29 +0000 | [diff] [blame] | 645 | /// immediate to insert at the specified INSERT_SUBVECTOR index |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 646 | /// with VINSERTF128, VINSERT128 instructions. |
| 647 | unsigned getInsertVINSERT128Immediate(SDNode *N); |
| 648 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 649 | /// Return the appropriate |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 650 | /// immediate to extract the specified EXTRACT_SUBVECTOR index |
| 651 | /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions. |
| 652 | unsigned getExtractVEXTRACT256Immediate(SDNode *N); |
| 653 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 654 | /// Return the appropriate |
Elena Demikhovsky | 67b05fc | 2013-07-31 11:35:14 +0000 | [diff] [blame] | 655 | /// immediate to insert at the specified INSERT_SUBVECTOR index |
| 656 | /// with VINSERTF64x4, VINSERTI64x4 instructions. |
| 657 | unsigned getInsertVINSERT256Immediate(SDNode *N); |
David Greene | 653f1ee | 2011-02-04 16:08:29 +0000 | [diff] [blame] | 658 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 659 | /// Returns true if Elt is a constant zero or floating point constant +0.0. |
Evan Cheng | e62288f | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 660 | bool isZeroNode(SDValue Elt); |
Anton Korobeynikov | 741ea0d | 2009-08-05 23:01:26 +0000 | [diff] [blame] | 661 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 662 | /// Returns true of the given offset can be |
Anton Korobeynikov | 741ea0d | 2009-08-05 23:01:26 +0000 | [diff] [blame] | 663 | /// fit into displacement field of the instruction. |
| 664 | bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, |
| 665 | bool hasSymbolicDisplacement = true); |
Evan Cheng | 3a0c5e5 | 2011-06-23 17:54:54 +0000 | [diff] [blame] | 666 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 667 | /// Determines whether the callee is required to pop its |
Evan Cheng | 3a0c5e5 | 2011-06-23 17:54:54 +0000 | [diff] [blame] | 668 | /// own arguments. Callee pop is necessary to support tail calls. |
| 669 | bool isCalleePop(CallingConv::ID CallingConv, |
Kevin B. Smith | c831a08 | 2016-01-16 00:08:36 +0000 | [diff] [blame] | 670 | bool is64Bit, bool IsVarArg, bool GuaranteeTCO); |
Adam Nemet | 50b83f0 | 2014-08-14 17:13:26 +0000 | [diff] [blame] | 671 | |
Eugene Zelenko | 6ac3f73 | 2016-01-26 18:48:36 +0000 | [diff] [blame] | 672 | } // end namespace X86 |
Evan Cheng | 084a1cd | 2008-01-29 19:34:22 +0000 | [diff] [blame] | 673 | |
Chris Lattner | f4aeff0 | 2006-10-18 18:26:48 +0000 | [diff] [blame] | 674 | //===--------------------------------------------------------------------===// |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 675 | // X86 Implementation of the TargetLowering interface |
Craig Topper | 26eec09 | 2014-03-31 06:22:15 +0000 | [diff] [blame] | 676 | class X86TargetLowering final : public TargetLowering { |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 677 | public: |
Eric Christopher | 05b8197 | 2015-02-02 17:38:43 +0000 | [diff] [blame] | 678 | explicit X86TargetLowering(const X86TargetMachine &TM, |
| 679 | const X86Subtarget &STI); |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 680 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 681 | unsigned getJumpTableEncoding() const override; |
Eric Christopher | 824f42f | 2015-05-12 01:26:05 +0000 | [diff] [blame] | 682 | bool useSoftFloat() const override; |
Chris Lattner | 9c1efcd | 2010-01-25 23:38:14 +0000 | [diff] [blame] | 683 | |
Mehdi Amini | eaabc51 | 2015-07-09 15:12:23 +0000 | [diff] [blame] | 684 | MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { |
Mehdi Amini | 9639d65 | 2015-07-09 02:09:20 +0000 | [diff] [blame] | 685 | return MVT::i8; |
| 686 | } |
Owen Anderson | b2c80da | 2011-02-25 21:41:48 +0000 | [diff] [blame] | 687 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 688 | const MCExpr * |
Chris Lattner | 4bfbe93 | 2010-01-26 05:02:42 +0000 | [diff] [blame] | 689 | LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, |
| 690 | const MachineBasicBlock *MBB, unsigned uid, |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 691 | MCContext &Ctx) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 692 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 693 | /// Returns relocation base for the given PIC jumptable. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 694 | SDValue getPICJumpTableRelocBase(SDValue Table, |
| 695 | SelectionDAG &DAG) const override; |
| 696 | const MCExpr * |
Chris Lattner | 8a785d7 | 2010-01-26 06:28:43 +0000 | [diff] [blame] | 697 | getPICJumpTableRelocBaseExpr(const MachineFunction *MF, |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 698 | unsigned JTI, MCContext &Ctx) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 699 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 700 | /// Return the desired alignment for ByVal aggregate |
Evan Cheng | 35abd84 | 2008-01-23 23:17:41 +0000 | [diff] [blame] | 701 | /// function arguments in the caller parameter area. For X86, aggregates |
| 702 | /// that contains are placed at 16-byte boundaries while the rest are at |
| 703 | /// 4-byte boundaries. |
Mehdi Amini | 5c183d5 | 2015-07-09 02:09:28 +0000 | [diff] [blame] | 704 | unsigned getByValTypeAlignment(Type *Ty, |
| 705 | const DataLayout &DL) const override; |
Evan Cheng | ef377ad | 2008-05-15 08:39:06 +0000 | [diff] [blame] | 706 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 707 | /// Returns the target specific optimal type for load |
Evan Cheng | 6139937 | 2010-04-02 19:36:14 +0000 | [diff] [blame] | 708 | /// and store operations as a result of memset, memcpy, and memmove |
| 709 | /// lowering. If DstAlign is zero that means it's safe to destination |
| 710 | /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it |
| 711 | /// means there isn't a need to check it against alignment requirement, |
Evan Cheng | 962711e | 2012-12-12 02:34:41 +0000 | [diff] [blame] | 712 | /// probably because the source does not need to be loaded. If 'IsMemset' is |
| 713 | /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that |
| 714 | /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy |
| 715 | /// source is constant so it does not need to be loaded. |
Dan Gohman | 148c69a | 2010-04-16 20:11:05 +0000 | [diff] [blame] | 716 | /// It returns EVT::Other if the type should be determined using generic |
| 717 | /// target-independent logic. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 718 | EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, |
| 719 | bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, |
| 720 | MachineFunction &MF) const override; |
Bill Wendling | bae6b2c | 2009-08-15 21:21:19 +0000 | [diff] [blame] | 721 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 722 | /// Returns true if it's safe to use load / store of the |
Evan Cheng | 04e5518 | 2012-12-12 00:42:09 +0000 | [diff] [blame] | 723 | /// specified type to expand memcpy / memset inline. This is mostly true |
Evan Cheng | c3d1aca | 2012-12-12 01:32:07 +0000 | [diff] [blame] | 724 | /// for all types except for some special cases. For example, on X86 |
Evan Cheng | 04e5518 | 2012-12-12 00:42:09 +0000 | [diff] [blame] | 725 | /// targets without SSE2 f64 load / store are done with fldl / fstpl which |
Evan Cheng | c3d1aca | 2012-12-12 01:32:07 +0000 | [diff] [blame] | 726 | /// also does type conversion. Note the specified type doesn't have to be |
| 727 | /// legal as the hook is used before type legalization. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 728 | bool isSafeMemOpType(MVT VT) const override; |
Evan Cheng | 04e5518 | 2012-12-12 00:42:09 +0000 | [diff] [blame] | 729 | |
Sanjay Patel | e4d95c6 | 2015-07-01 17:55:07 +0000 | [diff] [blame] | 730 | /// Returns true if the target allows unaligned memory accesses of the |
| 731 | /// specified type. Returns whether it is "fast" in the last argument. |
Matt Arsenault | 6f2a526 | 2014-07-27 17:46:40 +0000 | [diff] [blame] | 732 | bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 733 | bool *Fast) const override; |
Bill Wendling | 31ceb1b | 2009-06-30 22:38:32 +0000 | [diff] [blame] | 734 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 735 | /// Provide custom lowering hooks for some operations. |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 736 | /// |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 737 | SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 738 | |
Igor Breger | 1e5bafb | 2016-01-24 08:04:33 +0000 | [diff] [blame] | 739 | /// Places new result values for the node in Results (their number |
| 740 | /// and types must exactly match those of the original return values of |
| 741 | /// the node), or leaves Results empty, which indicates that the node is not |
| 742 | /// to be custom lowered after all. |
Eugene Zelenko | 6ac3f73 | 2016-01-26 18:48:36 +0000 | [diff] [blame] | 743 | void LowerOperationWrapper(SDNode *N, |
| 744 | SmallVectorImpl<SDValue> &Results, |
| 745 | SelectionDAG &DAG) const override; |
Igor Breger | 1e5bafb | 2016-01-24 08:04:33 +0000 | [diff] [blame] | 746 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 747 | /// Replace the results of node with an illegal result |
Duncan Sands | 6ed4014 | 2008-12-01 11:39:25 +0000 | [diff] [blame] | 748 | /// type with new values built out of custom code. |
Chris Lattner | f81d588 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 749 | /// |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 750 | void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, |
| 751 | SelectionDAG &DAG) const override; |
Chris Lattner | f81d588 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 752 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 753 | SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; |
Evan Cheng | 5987cfb | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 754 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 755 | /// Return true if the target has native support for |
Evan Cheng | f1bd5fc | 2010-04-17 06:13:15 +0000 | [diff] [blame] | 756 | /// the specified value type and it is 'desirable' to use the type for the |
| 757 | /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 |
| 758 | /// instruction encodings are longer and some i16 instructions are slow. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 759 | bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override; |
Evan Cheng | f1bd5fc | 2010-04-17 06:13:15 +0000 | [diff] [blame] | 760 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 761 | /// Return true if the target has native support for the |
Evan Cheng | f1bd5fc | 2010-04-17 06:13:15 +0000 | [diff] [blame] | 762 | /// specified value type and it is 'desirable' to use the type. e.g. On x86 |
| 763 | /// i16 is legal, but undesirable since i16 instruction encodings are longer |
| 764 | /// and some i16 instructions are slow. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 765 | bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override; |
Evan Cheng | af56fac | 2010-04-16 06:14:10 +0000 | [diff] [blame] | 766 | |
David Majnemer | ca1c9f0 | 2016-01-04 04:49:41 +0000 | [diff] [blame] | 767 | /// Return true if the MachineFunction contains a COPY which would imply |
| 768 | /// HasOpaqueSPAdjustment. |
| 769 | bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const override; |
| 770 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 771 | MachineBasicBlock * |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 772 | EmitInstrWithCustomInserter(MachineInstr &MI, |
| 773 | MachineBasicBlock *MBB) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 774 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 775 | /// This method returns the name of a target specific DAG node. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 776 | const char *getTargetNodeName(unsigned Opcode) const override; |
Evan Cheng | 6af0263 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 777 | |
Andrea Di Biagio | 22ee3f6 | 2014-12-28 11:07:35 +0000 | [diff] [blame] | 778 | bool isCheapToSpeculateCttz() const override; |
| 779 | |
| 780 | bool isCheapToSpeculateCtlz() const override; |
| 781 | |
Pierre Gousseau | b6d652a | 2016-10-14 16:41:38 +0000 | [diff] [blame] | 782 | bool isCtlzFast() const override; |
| 783 | |
Sanjay Patel | b114fd6 | 2016-06-10 20:33:50 +0000 | [diff] [blame] | 784 | bool hasBitPreservingFPLogic(EVT VT) const override { |
| 785 | return VT == MVT::f32 || VT == MVT::f64 || VT.isVector(); |
| 786 | } |
| 787 | |
Wei Mi | c54d129 | 2016-09-02 17:17:04 +0000 | [diff] [blame] | 788 | bool isMultiStoresCheaperThanBitsMerge(SDValue Lo, |
| 789 | SDValue Hi) const override { |
| 790 | // If the pair to store is a mixture of float and int values, we will |
| 791 | // save two bitwise instructions and one float-to-int instruction and |
| 792 | // increase one store instruction. There is potentially a more |
| 793 | // significant benefit because it avoids the float->int domain switch |
| 794 | // for input value. So It is more likely a win. |
| 795 | if (Lo.getOpcode() == ISD::BITCAST || Hi.getOpcode() == ISD::BITCAST) { |
| 796 | SDValue Opd = (Lo.getOpcode() == ISD::BITCAST) ? Lo.getOperand(0) |
| 797 | : Hi.getOperand(0); |
| 798 | if (Opd.getValueType().isFloatingPoint()) |
| 799 | return true; |
| 800 | } |
| 801 | // If the pair only contains int values, we will save two bitwise |
| 802 | // instructions and increase one store instruction (costing one more |
| 803 | // store buffer). Since the benefit is more blurred so we leave |
| 804 | // such pair out until we get testcase to prove it is a win. |
| 805 | return false; |
| 806 | } |
| 807 | |
Sanjay Patel | c2751e7 | 2016-05-07 15:03:40 +0000 | [diff] [blame] | 808 | bool hasAndNotCompare(SDValue Y) const override; |
| 809 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 810 | /// Return the value type to use for ISD::SETCC. |
Mehdi Amini | 44ede33 | 2015-07-09 02:09:04 +0000 | [diff] [blame] | 811 | EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, |
| 812 | EVT VT) const override; |
Scott Michel | a6729e8 | 2008-03-10 15:42:14 +0000 | [diff] [blame] | 813 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 814 | /// Determine which of the bits specified in Mask are known to be either |
| 815 | /// zero or one and return them in the KnownZero/KnownOne bitsets. |
Jay Foad | a0653a3 | 2014-05-14 21:14:37 +0000 | [diff] [blame] | 816 | void computeKnownBitsForTargetNode(const SDValue Op, |
| 817 | APInt &KnownZero, |
| 818 | APInt &KnownOne, |
| 819 | const SelectionDAG &DAG, |
| 820 | unsigned Depth = 0) const override; |
Evan Cheng | 2609d5e | 2008-05-12 19:56:52 +0000 | [diff] [blame] | 821 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 822 | /// Determine the number of bits in the operation that are sign bits. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 823 | unsigned ComputeNumSignBitsForTargetNode(SDValue Op, |
Matt Arsenault | cf6f688 | 2014-04-04 20:13:13 +0000 | [diff] [blame] | 824 | const SelectionDAG &DAG, |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 825 | unsigned Depth) const override; |
Owen Anderson | 5e65dfb | 2010-09-21 20:42:50 +0000 | [diff] [blame] | 826 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 827 | bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA, |
| 828 | int64_t &Offset) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 829 | |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 830 | SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 831 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 832 | bool ExpandInlineAsm(CallInst *CI) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 833 | |
Benjamin Kramer | 9bfb627 | 2015-07-05 19:29:18 +0000 | [diff] [blame] | 834 | ConstraintType getConstraintType(StringRef Constraint) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 835 | |
John Thompson | e8360b7 | 2010-10-29 17:29:13 +0000 | [diff] [blame] | 836 | /// Examine constraint string and operand type and determine a weight value. |
John Thompson | 1094c80 | 2010-09-13 18:15:37 +0000 | [diff] [blame] | 837 | /// The operand object must already have been set up with the operand type. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 838 | ConstraintWeight |
| 839 | getSingleConstraintMatchWeight(AsmOperandInfo &info, |
| 840 | const char *constraint) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 841 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 842 | const char *LowerXConstraint(EVT ConstraintVT) const override; |
Dale Johannesen | 2b3bc30 | 2008-01-29 02:21:21 +0000 | [diff] [blame] | 843 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 844 | /// Lower the specified operand into the Ops vector. If it is invalid, don't |
| 845 | /// add anything to Ops. If hasMemory is true it means one of the asm |
| 846 | /// constraint of the inline asm instruction being processed is 'm'. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 847 | void LowerAsmOperandForConstraint(SDValue Op, |
| 848 | std::string &Constraint, |
| 849 | std::vector<SDValue> &Ops, |
| 850 | SelectionDAG &DAG) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 851 | |
Benjamin Kramer | 9bfb627 | 2015-07-05 19:29:18 +0000 | [diff] [blame] | 852 | unsigned |
| 853 | getInlineAsmMemConstraint(StringRef ConstraintCode) const override { |
Daniel Sanders | d049669 | 2015-05-16 12:09:54 +0000 | [diff] [blame] | 854 | if (ConstraintCode == "i") |
| 855 | return InlineAsm::Constraint_i; |
| 856 | else if (ConstraintCode == "o") |
| 857 | return InlineAsm::Constraint_o; |
| 858 | else if (ConstraintCode == "v") |
| 859 | return InlineAsm::Constraint_v; |
| 860 | else if (ConstraintCode == "X") |
| 861 | return InlineAsm::Constraint_X; |
| 862 | return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); |
Daniel Sanders | bf5b80f | 2015-03-16 13:13:41 +0000 | [diff] [blame] | 863 | } |
| 864 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 865 | /// Given a physical register constraint |
Chris Lattner | f4aeff0 | 2006-10-18 18:26:48 +0000 | [diff] [blame] | 866 | /// (e.g. {edx}), return the register number and the register class for the |
| 867 | /// register. This should only be used for C_Register constraints. On |
| 868 | /// error, this returns a register number of 0. |
Eric Christopher | 11e4df7 | 2015-02-26 22:38:43 +0000 | [diff] [blame] | 869 | std::pair<unsigned, const TargetRegisterClass *> |
| 870 | getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, |
Benjamin Kramer | 9bfb627 | 2015-07-05 19:29:18 +0000 | [diff] [blame] | 871 | StringRef Constraint, MVT VT) const override; |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 872 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 873 | /// Return true if the addressing mode represented |
Chris Lattner | 1eb94d9 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 874 | /// by AM is legal for this target, for a load/store of the specified type. |
Mehdi Amini | 0cdec1e | 2015-07-09 02:09:40 +0000 | [diff] [blame] | 875 | bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, |
| 876 | Type *Ty, unsigned AS) const override; |
Chris Lattner | 1eb94d9 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 877 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 878 | /// Return true if the specified immediate is legal |
Evan Cheng | f579bec | 2012-07-17 06:53:39 +0000 | [diff] [blame] | 879 | /// icmp immediate, that is the target has icmp instructions which can |
| 880 | /// compare a register against the immediate without having to materialize |
| 881 | /// the immediate into a register. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 882 | bool isLegalICmpImmediate(int64_t Imm) const override; |
Evan Cheng | f579bec | 2012-07-17 06:53:39 +0000 | [diff] [blame] | 883 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 884 | /// Return true if the specified immediate is legal |
Evan Cheng | f579bec | 2012-07-17 06:53:39 +0000 | [diff] [blame] | 885 | /// add immediate, that is the target has add instructions which can |
| 886 | /// add a register and the immediate without having to materialize |
| 887 | /// the immediate into a register. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 888 | bool isLegalAddImmediate(int64_t Imm) const override; |
Evan Cheng | f579bec | 2012-07-17 06:53:39 +0000 | [diff] [blame] | 889 | |
Quentin Colombet | ea18933 | 2014-04-26 01:11:26 +0000 | [diff] [blame] | 890 | /// \brief Return the cost of the scaling factor used in the addressing |
| 891 | /// mode represented by AM for this target, for a load/store |
| 892 | /// of the specified type. |
| 893 | /// If the AM is supported, the return value must be >= 0. |
| 894 | /// If the AM is not supported, it returns a negative value. |
Mehdi Amini | 0cdec1e | 2015-07-09 02:09:40 +0000 | [diff] [blame] | 895 | int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, |
Matt Arsenault | bd7d80a | 2015-06-01 05:31:59 +0000 | [diff] [blame] | 896 | unsigned AS) const override; |
Tim Northover | aeb8e06 | 2014-02-19 10:02:43 +0000 | [diff] [blame] | 897 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 898 | bool isVectorShiftByScalarCheap(Type *Ty) const override; |
Tim Northover | aeb8e06 | 2014-02-19 10:02:43 +0000 | [diff] [blame] | 899 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 900 | /// Return true if it's free to truncate a value of |
Evan Cheng | 7f3d024 | 2007-10-26 01:56:11 +0000 | [diff] [blame] | 901 | /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in |
| 902 | /// register EAX to i16 by referencing its sub-register AX. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 903 | bool isTruncateFree(Type *Ty1, Type *Ty2) const override; |
| 904 | bool isTruncateFree(EVT VT1, EVT VT2) const override; |
Dan Gohman | ad3e549 | 2009-04-08 00:15:30 +0000 | [diff] [blame] | 905 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 906 | bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; |
Tim Northover | a441585 | 2013-08-06 09:12:35 +0000 | [diff] [blame] | 907 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 908 | /// Return true if any actual instruction that defines a |
Dan Gohman | ad3e549 | 2009-04-08 00:15:30 +0000 | [diff] [blame] | 909 | /// value of type Ty1 implicit zero-extends the value to Ty2 in the result |
| 910 | /// register. This does not necessarily include registers defined in |
| 911 | /// unknown ways, such as incoming arguments, or copies from unknown |
| 912 | /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this |
| 913 | /// does not necessarily apply to truncate instructions. e.g. on x86-64, |
| 914 | /// all instructions that define 32-bit values implicit zero-extend the |
| 915 | /// result out to 64 bits. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 916 | bool isZExtFree(Type *Ty1, Type *Ty2) const override; |
| 917 | bool isZExtFree(EVT VT1, EVT VT2) const override; |
| 918 | bool isZExtFree(SDValue Val, EVT VT2) const override; |
Dan Gohman | ad3e549 | 2009-04-08 00:15:30 +0000 | [diff] [blame] | 919 | |
Ahmed Bougacha | e892d13 | 2015-02-05 18:31:02 +0000 | [diff] [blame] | 920 | /// Return true if folding a vector load into ExtVal (a sign, zero, or any |
| 921 | /// extend node) is profitable. |
| 922 | bool isVectorLoadExtDesirable(SDValue) const override; |
| 923 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 924 | /// Return true if an FMA operation is faster than a pair of fmul and fadd |
| 925 | /// instructions. fmuladd intrinsics will be expanded to FMAs when this |
| 926 | /// method returns true, otherwise fmuladd is expanded to fmul + fadd. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 927 | bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; |
Elena Demikhovsky | 3cb3b00 | 2012-08-01 12:06:00 +0000 | [diff] [blame] | 928 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 929 | /// Return true if it's profitable to narrow |
Evan Cheng | a9cda8a | 2009-05-28 00:35:15 +0000 | [diff] [blame] | 930 | /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow |
| 931 | /// from i32 to i8 but not from i32 to i16. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 932 | bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; |
Evan Cheng | a9cda8a | 2009-05-28 00:35:15 +0000 | [diff] [blame] | 933 | |
Igor Breger | ea8e8e9 | 2016-01-12 10:02:32 +0000 | [diff] [blame] | 934 | /// Given an intrinsic, checks if on the target the intrinsic will need to map |
| 935 | /// to a MemIntrinsicNode (touches memory). If this is the case, it returns |
| 936 | /// true and stores the intrinsic information into the IntrinsicInfo that was |
| 937 | /// passed to the function. |
| 938 | bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, |
| 939 | unsigned Intrinsic) const override; |
| 940 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 941 | /// Returns true if the target can instruction select the |
Evan Cheng | 16993aa | 2009-10-27 19:56:55 +0000 | [diff] [blame] | 942 | /// specified FP immediate natively. If false, the legalizer will |
| 943 | /// materialize the FP immediate as a load from a constant pool. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 944 | bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; |
Evan Cheng | 16993aa | 2009-10-27 19:56:55 +0000 | [diff] [blame] | 945 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 946 | /// Targets can use this to indicate that they only support *some* |
| 947 | /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a |
| 948 | /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to |
| 949 | /// be legal. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 950 | bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, |
| 951 | EVT VT) const override; |
Evan Cheng | 60f0b89 | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 952 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 953 | /// Similar to isShuffleMaskLegal. This is used by Targets can use this to |
| 954 | /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to |
| 955 | /// replace a VAND with a constant pool entry. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 956 | bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, |
| 957 | EVT VT) const override; |
Evan Cheng | 0a62cb4 | 2008-03-05 01:30:59 +0000 | [diff] [blame] | 958 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 959 | /// If true, then instruction selection should |
Evan Cheng | 0a62cb4 | 2008-03-05 01:30:59 +0000 | [diff] [blame] | 960 | /// seek to shrink the FP constant of the specified type to a smaller type |
| 961 | /// in order to save space and / or reduce runtime. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 962 | bool ShouldShrinkFPConstant(EVT VT) const override { |
Evan Cheng | 0a62cb4 | 2008-03-05 01:30:59 +0000 | [diff] [blame] | 963 | // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more |
| 964 | // expensive than a straight movsd. On the other hand, it's important to |
| 965 | // shrink long double fp constant since fldt is very slow. |
Owen Anderson | 9f94459 | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 966 | return !X86ScalarSSEf64 || VT == MVT::f80; |
Evan Cheng | 0a62cb4 | 2008-03-05 01:30:59 +0000 | [diff] [blame] | 967 | } |
Michael J. Spencer | 9cafc87 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 968 | |
David Majnemer | 29c52f7 | 2015-01-06 07:12:52 +0000 | [diff] [blame] | 969 | /// Return true if we believe it is correct and profitable to reduce the |
| 970 | /// load node to a smaller type. |
| 971 | bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, |
| 972 | EVT NewVT) const override; |
| 973 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 974 | /// Return true if the specified scalar FP type is computed in an SSE |
| 975 | /// register, not on the X87 floating point stack. |
Owen Anderson | 53aa7a9 | 2009-08-10 22:56:29 +0000 | [diff] [blame] | 976 | bool isScalarFPTypeInSSEReg(EVT VT) const { |
Owen Anderson | 9f94459 | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 977 | return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 |
Craig Topper | 95ceb5a | 2015-11-02 05:24:22 +0000 | [diff] [blame] | 978 | (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 |
Chris Lattner | 7dc00e8 | 2008-01-18 06:52:41 +0000 | [diff] [blame] | 979 | } |
Dan Gohman | 4619e93 | 2008-08-19 21:32:53 +0000 | [diff] [blame] | 980 | |
Juergen Ributzka | 659ce00 | 2014-01-28 01:20:14 +0000 | [diff] [blame] | 981 | /// \brief Returns true if it is beneficial to convert a load of a constant |
| 982 | /// to just the constant itself. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 983 | bool shouldConvertConstantLoadToIntImm(const APInt &Imm, |
| 984 | Type *Ty) const override; |
Juergen Ributzka | 659ce00 | 2014-01-28 01:20:14 +0000 | [diff] [blame] | 985 | |
Michael Kuperstein | 047b1a0 | 2014-12-17 12:32:17 +0000 | [diff] [blame] | 986 | /// Return true if EXTRACT_SUBVECTOR is cheap for this result type |
| 987 | /// with this index. |
| 988 | bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override; |
| 989 | |
Renato Golin | c0a3c1d | 2014-03-26 12:52:28 +0000 | [diff] [blame] | 990 | /// Intel processors have a unified instruction and data cache |
Craig Topper | 9d74a5a | 2014-04-29 07:58:41 +0000 | [diff] [blame] | 991 | const char * getClearCacheBuiltinName() const override { |
Craig Topper | e73658d | 2014-04-28 04:05:08 +0000 | [diff] [blame] | 992 | return nullptr; // nothing to do, move along. |
Renato Golin | c0a3c1d | 2014-03-26 12:52:28 +0000 | [diff] [blame] | 993 | } |
| 994 | |
Pat Gavlin | a717f25 | 2015-07-09 17:40:29 +0000 | [diff] [blame] | 995 | unsigned getRegisterByName(const char* RegName, EVT VT, |
| 996 | SelectionDAG &DAG) const override; |
Renato Golin | c7aea40 | 2014-05-06 16:51:25 +0000 | [diff] [blame] | 997 | |
Joseph Tremoulet | f748c89 | 2015-11-07 01:11:31 +0000 | [diff] [blame] | 998 | /// If a physical register, this returns the register that receives the |
| 999 | /// exception address on entry to an EH pad. |
| 1000 | unsigned |
| 1001 | getExceptionPointerRegister(const Constant *PersonalityFn) const override; |
| 1002 | |
| 1003 | /// If a physical register, this returns the register that receives the |
| 1004 | /// exception typeid on entry to a landing pad. |
| 1005 | unsigned |
| 1006 | getExceptionSelectorRegister(const Constant *PersonalityFn) const override; |
| 1007 | |
David Majnemer | 1ef6540 | 2016-03-03 00:01:25 +0000 | [diff] [blame] | 1008 | virtual bool needsFixedCatchObjects() const override; |
| 1009 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 1010 | /// This method returns a target specific FastISel object, |
Dan Gohman | 4619e93 | 2008-08-19 21:32:53 +0000 | [diff] [blame] | 1011 | /// or null if the target does not support "fast" ISel. |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1012 | FastISel *createFastISel(FunctionLoweringInfo &funcInfo, |
| 1013 | const TargetLibraryInfo *libInfo) const override; |
Bill Wendling | 31ceb1b | 2009-06-30 22:38:32 +0000 | [diff] [blame] | 1014 | |
Evgeniy Stepanov | dde29e2 | 2016-04-05 22:41:50 +0000 | [diff] [blame] | 1015 | /// If the target has a standard location for the stack protector cookie, |
| 1016 | /// returns the address of that location. Otherwise, returns nullptr. |
Tim Shen | 0012756 | 2016-04-08 21:26:31 +0000 | [diff] [blame] | 1017 | Value *getIRStackGuard(IRBuilder<> &IRB) const override; |
| 1018 | |
Etienne Bergeron | 22bfa83 | 2016-06-07 20:15:35 +0000 | [diff] [blame] | 1019 | bool useLoadStackGuardNode() const override; |
Tim Shen | 0012756 | 2016-04-08 21:26:31 +0000 | [diff] [blame] | 1020 | void insertSSPDeclarations(Module &M) const override; |
Etienne Bergeron | 22bfa83 | 2016-06-07 20:15:35 +0000 | [diff] [blame] | 1021 | Value *getSDagStackGuard(const Module &M) const override; |
| 1022 | Value *getSSPStackGuardCheck(const Module &M) const override; |
Tim Shen | 0012756 | 2016-04-08 21:26:31 +0000 | [diff] [blame] | 1023 | |
Evgeniy Stepanov | a2002b0 | 2015-09-23 18:07:56 +0000 | [diff] [blame] | 1024 | /// Return true if the target stores SafeStack pointer at a fixed offset in |
| 1025 | /// some non-standard address space, and populates the address space and |
| 1026 | /// offset as appropriate. |
Evgeniy Stepanov | d1aad26 | 2015-10-26 18:28:25 +0000 | [diff] [blame] | 1027 | Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override; |
Evgeniy Stepanov | a2002b0 | 2015-09-23 18:07:56 +0000 | [diff] [blame] | 1028 | |
Stuart Hastings | e0d3426 | 2011-06-06 23:15:58 +0000 | [diff] [blame] | 1029 | SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, |
| 1030 | SelectionDAG &DAG) const; |
| 1031 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1032 | bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; |
Matt Arsenault | b03bd4d | 2013-11-15 01:34:59 +0000 | [diff] [blame] | 1033 | |
Chandler Carruth | 49a8b10 | 2014-07-03 02:11:29 +0000 | [diff] [blame] | 1034 | /// \brief Customize the preferred legalization strategy for certain types. |
| 1035 | LegalizeTypeAction getPreferredVectorAction(EVT VT) const override; |
| 1036 | |
Steve King | 5cdbd20 | 2015-08-25 02:31:21 +0000 | [diff] [blame] | 1037 | bool isIntDivCheap(EVT VT, AttributeSet Attr) const override; |
Michael Kuperstein | 9fe4260 | 2015-08-19 11:21:43 +0000 | [diff] [blame] | 1038 | |
Arnold Schwaighofer | 0fd32c0 | 2016-09-22 20:06:25 +0000 | [diff] [blame] | 1039 | bool supportSwiftError() const override; |
Manman Ren | 5751814 | 2016-04-11 21:08:06 +0000 | [diff] [blame] | 1040 | |
David L Kreitzer | 01a057a | 2016-10-14 18:20:41 +0000 | [diff] [blame] | 1041 | unsigned getMaxSupportedInterleaveFactor() const override { return 4; } |
| 1042 | |
| 1043 | /// \brief Lower interleaved load(s) into target specific |
| 1044 | /// instructions/intrinsics. |
| 1045 | bool lowerInterleavedLoad(LoadInst *LI, |
| 1046 | ArrayRef<ShuffleVectorInst *> Shuffles, |
| 1047 | ArrayRef<unsigned> Indices, |
| 1048 | unsigned Factor) const override; |
Evan Cheng | d4218b8 | 2010-07-26 21:50:05 +0000 | [diff] [blame] | 1049 | protected: |
Eric Christopher | 23a3a7c | 2015-02-26 00:00:24 +0000 | [diff] [blame] | 1050 | std::pair<const TargetRegisterClass *, uint8_t> |
| 1051 | findRepresentativeClass(const TargetRegisterInfo *TRI, |
| 1052 | MVT VT) const override; |
Evan Cheng | d4218b8 | 2010-07-26 21:50:05 +0000 | [diff] [blame] | 1053 | |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1054 | private: |
Sanjay Patel | 06fe918 | 2016-01-26 22:08:58 +0000 | [diff] [blame] | 1055 | /// Keep a reference to the X86Subtarget around so that we can |
Evan Cheng | a9467aa | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 1056 | /// make the right decision when generating code for different targets. |
Sanjay Patel | 06fe918 | 2016-01-26 22:08:58 +0000 | [diff] [blame] | 1057 | const X86Subtarget &Subtarget; |
Evan Cheng | a9467aa | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 1058 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 1059 | /// Select between SSE or x87 floating point ops. |
Dale Johannesen | e36c400 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 1060 | /// When SSE is available, use it for f32 operations. |
| 1061 | /// When SSE2 is available, use it for f64 operations. |
| 1062 | bool X86ScalarSSEf32; |
| 1063 | bool X86ScalarSSEf64; |
Evan Cheng | 084a1cd | 2008-01-29 19:34:22 +0000 | [diff] [blame] | 1064 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 1065 | /// A list of legal FP immediates. |
Evan Cheng | 16993aa | 2009-10-27 19:56:55 +0000 | [diff] [blame] | 1066 | std::vector<APFloat> LegalFPImmediates; |
| 1067 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 1068 | /// Indicate that this x86 target can instruction |
Evan Cheng | 16993aa | 2009-10-27 19:56:55 +0000 | [diff] [blame] | 1069 | /// select the specified FP immediate natively. |
| 1070 | void addLegalFPImmediate(const APFloat& Imm) { |
| 1071 | LegalFPImmediates.push_back(Imm); |
| 1072 | } |
| 1073 | |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 1074 | SDValue LowerCallResult(SDValue Chain, SDValue InFlag, |
Sandeep Patel | 68c5f47 | 2009-09-02 08:44:58 +0000 | [diff] [blame] | 1075 | CallingConv::ID CallConv, bool isVarArg, |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 1076 | const SmallVectorImpl<ISD::InputArg> &Ins, |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1077 | const SDLoc &dl, SelectionDAG &DAG, |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1078 | SmallVectorImpl<SDValue> &InVals) const; |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1079 | SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 1080 | const SmallVectorImpl<ISD::InputArg> &ArgInfo, |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1081 | const SDLoc &dl, SelectionDAG &DAG, |
Matthias Braun | 941a705 | 2016-07-28 18:40:00 +0000 | [diff] [blame] | 1082 | const CCValAssign &VA, MachineFrameInfo &MFI, |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1083 | unsigned i) const; |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 1084 | SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1085 | const SDLoc &dl, SelectionDAG &DAG, |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 1086 | const CCValAssign &VA, |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1087 | ISD::ArgFlagsTy Flags) const; |
Rafael Espindola | e636fc0 | 2007-08-31 15:06:30 +0000 | [diff] [blame] | 1088 | |
Gordon Henriksen | 9231958 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1089 | // Call lowering helpers. |
Evan Cheng | 67a69dd | 2010-01-27 00:07:07 +0000 | [diff] [blame] | 1090 | |
Sanjay Patel | 0e4a83e | 2014-10-01 19:39:32 +0000 | [diff] [blame] | 1091 | /// Check whether the call is eligible for tail call optimization. Targets |
| 1092 | /// that want to do tail call optimization should implement this function. |
Evan Cheng | 6f36a08 | 2010-02-02 23:55:14 +0000 | [diff] [blame] | 1093 | bool IsEligibleForTailCallOptimization(SDValue Callee, |
Evan Cheng | 67a69dd | 2010-01-27 00:07:07 +0000 | [diff] [blame] | 1094 | CallingConv::ID CalleeCC, |
| 1095 | bool isVarArg, |
Evan Cheng | ae5edee | 2010-03-15 18:54:48 +0000 | [diff] [blame] | 1096 | bool isCalleeStructRet, |
| 1097 | bool isCallerStructRet, |
Evan Cheng | 446ff28 | 2012-09-25 05:32:34 +0000 | [diff] [blame] | 1098 | Type *RetTy, |
Evan Cheng | 85476f3 | 2010-01-27 06:25:16 +0000 | [diff] [blame] | 1099 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
Dan Gohman | fe7532a | 2010-07-07 15:54:55 +0000 | [diff] [blame] | 1100 | const SmallVectorImpl<SDValue> &OutVals, |
Evan Cheng | 85476f3 | 2010-01-27 06:25:16 +0000 | [diff] [blame] | 1101 | const SmallVectorImpl<ISD::InputArg> &Ins, |
Evan Cheng | 67a69dd | 2010-01-27 00:07:07 +0000 | [diff] [blame] | 1102 | SelectionDAG& DAG) const; |
Dan Gohman | 2ce6f2a | 2008-07-27 21:46:04 +0000 | [diff] [blame] | 1103 | SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1104 | SDValue Chain, bool IsTailCall, |
| 1105 | bool Is64Bit, int FPDiff, |
| 1106 | const SDLoc &dl) const; |
Arnold Schwaighofer | 634fc9a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1107 | |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1108 | unsigned GetAlignedArgumentStackSize(unsigned StackSize, |
| 1109 | SelectionDAG &DAG) const; |
Evan Cheng | cde9e30 | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 1110 | |
Davide Italiano | 2ec4717 | 2016-02-22 21:06:46 +0000 | [diff] [blame] | 1111 | unsigned getAddressSpace(void) const; |
| 1112 | |
Eli Friedman | dfe4f25 | 2009-05-23 09:59:16 +0000 | [diff] [blame] | 1113 | std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, |
NAKAMURA Takumi | bdf9487 | 2012-02-25 03:37:25 +0000 | [diff] [blame] | 1114 | bool isSigned, |
| 1115 | bool isReplace) const; |
Evan Cheng | 493b882 | 2009-12-09 21:00:30 +0000 | [diff] [blame] | 1116 | |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1117 | SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; |
Elena Demikhovsky | 40864b6 | 2013-08-05 08:52:21 +0000 | [diff] [blame] | 1118 | SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const; |
Filipe Cabecinhas | 17254aa | 2014-05-16 22:47:43 +0000 | [diff] [blame] | 1119 | SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1120 | SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; |
Elena Demikhovsky | 9737e38 | 2014-03-02 09:19:44 +0000 | [diff] [blame] | 1121 | SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const; |
Elena Demikhovsky | cf0b9ba | 2014-04-09 12:37:50 +0000 | [diff] [blame] | 1122 | SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1123 | SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; |
Peter Collingbourne | de1f039 | 2016-10-20 01:21:26 +0000 | [diff] [blame] | 1124 | |
Peter Collingbourne | 235c275 | 2016-12-08 19:01:00 +0000 | [diff] [blame] | 1125 | unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1126 | SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; |
| 1127 | SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1128 | SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &dl, |
Dale Johannesen | 021052a | 2009-02-04 20:06:27 +0000 | [diff] [blame] | 1129 | int64_t Offset, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1130 | SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; |
| 1131 | SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; |
| 1132 | SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; |
Peter Collingbourne | de1f039 | 2016-10-20 01:21:26 +0000 | [diff] [blame] | 1133 | |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1134 | SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; |
| 1135 | SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; |
| 1136 | SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; |
| 1137 | SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; |
Michael Liao | c03c03d | 2012-10-23 17:36:08 +0000 | [diff] [blame] | 1138 | SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const; |
Craig Topper | e65a08b | 2013-01-20 21:34:37 +0000 | [diff] [blame] | 1139 | SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; |
Craig Topper | 18b57da | 2016-12-10 19:35:39 +0000 | [diff] [blame] | 1140 | SDValue LowerFP_TO_INT(SDValue Op, const X86Subtarget &Subtarget, |
| 1141 | SelectionDAG &DAG) const; |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1142 | SDValue LowerToBT(SDValue And, ISD::CondCode CC, const SDLoc &dl, |
| 1143 | SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1144 | SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; |
Hans Wennborg | dcc2500 | 2015-11-19 16:35:08 +0000 | [diff] [blame] | 1145 | SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1146 | SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; |
| 1147 | SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1148 | SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; |
| 1149 | SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; |
| 1150 | SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; |
| 1151 | SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1152 | SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; |
Albert Gutowski | 795d7d6 | 2016-10-12 22:13:19 +0000 | [diff] [blame] | 1153 | SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1154 | SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; |
| 1155 | SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; |
| 1156 | SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; |
Michael Liao | 97bf363 | 2012-10-15 22:39:43 +0000 | [diff] [blame] | 1157 | SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; |
| 1158 | SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; |
Saleem Abdulrasool | d2f705d | 2016-05-31 01:48:07 +0000 | [diff] [blame] | 1159 | SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; |
Duncan Sands | a098436 | 2011-09-06 13:37:06 +0000 | [diff] [blame] | 1160 | SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; |
Dan Gohman | 21cea8a | 2010-04-17 15:26:15 +0000 | [diff] [blame] | 1161 | SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; |
Reid Kleckner | 4a406d3 | 2014-05-06 01:20:42 +0000 | [diff] [blame] | 1162 | SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const; |
Pat Gavlin | cc0431d | 2015-05-08 18:07:42 +0000 | [diff] [blame] | 1163 | SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const; |
| 1164 | SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const; |
Duncan Sands | 6ed4014 | 2008-12-01 11:39:25 +0000 | [diff] [blame] | 1165 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1166 | SDValue |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1167 | LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
| 1168 | const SmallVectorImpl<ISD::InputArg> &Ins, |
| 1169 | const SDLoc &dl, SelectionDAG &DAG, |
| 1170 | SmallVectorImpl<SDValue> &InVals) const override; |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1171 | SDValue LowerCall(CallLoweringInfo &CLI, |
| 1172 | SmallVectorImpl<SDValue> &InVals) const override; |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 1173 | |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1174 | SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1175 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
| 1176 | const SmallVectorImpl<SDValue> &OutVals, |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1177 | const SDLoc &dl, SelectionDAG &DAG) const override; |
Dan Gohman | f9bbcd1 | 2009-08-05 01:29:28 +0000 | [diff] [blame] | 1178 | |
Manman Ren | ed967f3 | 2016-01-12 01:08:46 +0000 | [diff] [blame] | 1179 | bool supportSplitCSR(MachineFunction *MF) const override { |
| 1180 | return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && |
| 1181 | MF->getFunction()->hasFnAttribute(Attribute::NoUnwind); |
| 1182 | } |
| 1183 | void initializeSplitCSR(MachineBasicBlock *Entry) const override; |
| 1184 | void insertCopiesSplitCSR( |
| 1185 | MachineBasicBlock *Entry, |
| 1186 | const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; |
| 1187 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1188 | bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; |
Evan Cheng | d4b0873 | 2010-11-30 23:55:39 +0000 | [diff] [blame] | 1189 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1190 | bool mayBeEmittedAsTailCall(CallInst *CI) const override; |
Evan Cheng | 0663f23 | 2011-03-21 01:19:09 +0000 | [diff] [blame] | 1191 | |
Hans Wennborg | 850ec6c | 2016-02-08 19:34:30 +0000 | [diff] [blame] | 1192 | EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, |
| 1193 | ISD::NodeType ExtendKind) const override; |
Cameron Zwarich | ac10627 | 2011-03-16 22:20:18 +0000 | [diff] [blame] | 1194 | |
Craig Topper | 2d9361e | 2014-03-09 07:44:38 +0000 | [diff] [blame] | 1195 | bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, |
| 1196 | bool isVarArg, |
| 1197 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
| 1198 | LLVMContext &Context) const override; |
Kenneth Uildriks | 0711973 | 2009-11-07 02:11:54 +0000 | [diff] [blame] | 1199 | |
Craig Topper | 840beec | 2014-04-04 05:16:06 +0000 | [diff] [blame] | 1200 | const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; |
Juergen Ributzka | 87ed906 | 2013-11-09 01:51:33 +0000 | [diff] [blame] | 1201 | |
Ahmed Bougacha | 5246867 | 2015-09-11 17:08:28 +0000 | [diff] [blame] | 1202 | TargetLoweringBase::AtomicExpansionKind |
| 1203 | shouldExpandAtomicLoadInIR(LoadInst *SI) const override; |
Robin Morisset | 25c8e31 | 2014-09-17 00:06:58 +0000 | [diff] [blame] | 1204 | bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; |
Ahmed Bougacha | 9d67713 | 2015-09-11 17:08:17 +0000 | [diff] [blame] | 1205 | TargetLoweringBase::AtomicExpansionKind |
JF Bastien | f14889e | 2015-03-04 15:47:57 +0000 | [diff] [blame] | 1206 | shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; |
Robin Morisset | 25c8e31 | 2014-09-17 00:06:58 +0000 | [diff] [blame] | 1207 | |
Robin Morisset | 810739d | 2014-09-25 17:27:43 +0000 | [diff] [blame] | 1208 | LoadInst * |
| 1209 | lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; |
| 1210 | |
Craig Topper | e3dcce9 | 2015-08-01 22:20:21 +0000 | [diff] [blame] | 1211 | bool needsCmpXchgNb(Type *MemType) const; |
Robin Morisset | 25c8e31 | 2014-09-17 00:06:58 +0000 | [diff] [blame] | 1212 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1213 | void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, |
Saleem Abdulrasool | d2f705d | 2016-05-31 01:48:07 +0000 | [diff] [blame] | 1214 | MachineBasicBlock *DispatchBB, int FI) const; |
| 1215 | |
Dan Gohman | 395a898 | 2010-10-12 18:00:49 +0000 | [diff] [blame] | 1216 | // Utility function to emit the low-level va_arg code for X86-64. |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1217 | MachineBasicBlock * |
| 1218 | EmitVAARG64WithCustomInserter(MachineInstr &MI, |
| 1219 | MachineBasicBlock *MBB) const; |
Dan Gohman | 395a898 | 2010-10-12 18:00:49 +0000 | [diff] [blame] | 1220 | |
Dan Gohman | 0700a56 | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 1221 | /// Utility function to emit the xmm reg save portion of va_start. |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1222 | MachineBasicBlock * |
| 1223 | EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr, |
| 1224 | MachineBasicBlock *BB) const; |
Dan Gohman | 0700a56 | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 1225 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1226 | MachineBasicBlock *EmitLoweredSelect(MachineInstr &I, |
Dan Gohman | 25c1653 | 2010-05-01 00:01:06 +0000 | [diff] [blame] | 1227 | MachineBasicBlock *BB) const; |
Anton Korobeynikov | d5e3fd6 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 1228 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1229 | MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &I, |
JF Bastien | 8662083 | 2015-08-05 21:04:59 +0000 | [diff] [blame] | 1230 | MachineBasicBlock *BB) const; |
| 1231 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1232 | MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI, |
Reid Kleckner | 51460c1 | 2015-11-06 01:49:05 +0000 | [diff] [blame] | 1233 | MachineBasicBlock *BB) const; |
| 1234 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1235 | MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI, |
David Majnemer | 2652b75 | 2015-11-09 23:07:48 +0000 | [diff] [blame] | 1236 | MachineBasicBlock *BB) const; |
| 1237 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1238 | MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI, |
Pavel Chupin | be9f121 | 2014-09-22 13:11:35 +0000 | [diff] [blame] | 1239 | MachineBasicBlock *BB) const; |
Rafael Espindola | 94d3253 | 2011-08-30 19:47:04 +0000 | [diff] [blame] | 1240 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1241 | MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI, |
Davide Italiano | 228978c | 2016-02-20 00:44:47 +0000 | [diff] [blame] | 1242 | MachineBasicBlock *BB) const; |
| 1243 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1244 | MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI, |
Eric Christopher | b0e1a45 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 1245 | MachineBasicBlock *BB) const; |
Anton Korobeynikov | d5e3fd6 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 1246 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1247 | MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, |
Michael Liao | 97bf363 | 2012-10-15 22:39:43 +0000 | [diff] [blame] | 1248 | MachineBasicBlock *MBB) const; |
| 1249 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1250 | MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, |
Michael Liao | 97bf363 | 2012-10-15 22:39:43 +0000 | [diff] [blame] | 1251 | MachineBasicBlock *MBB) const; |
| 1252 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1253 | MachineBasicBlock *emitFMA3Instr(MachineInstr &MI, |
Lang Hames | 23de211 | 2014-01-23 20:23:36 +0000 | [diff] [blame] | 1254 | MachineBasicBlock *MBB) const; |
| 1255 | |
Duncan P. N. Exon Smith | e4f5e4f | 2016-06-30 22:52:52 +0000 | [diff] [blame] | 1256 | MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI, |
Saleem Abdulrasool | d2f705d | 2016-05-31 01:48:07 +0000 | [diff] [blame] | 1257 | MachineBasicBlock *MBB) const; |
| 1258 | |
Dan Gohman | 55d7b2a | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 1259 | /// Emit nodes that will be selected as "test Op0,Op0", or something |
Dan Gohman | ff659b5 | 2009-03-07 01:58:32 +0000 | [diff] [blame] | 1260 | /// equivalent, for use with the given x86 condition code. |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1261 | SDValue EmitTest(SDValue Op0, unsigned X86CC, const SDLoc &dl, |
David Blaikie | 269e0fb | 2014-04-13 06:39:55 +0000 | [diff] [blame] | 1262 | SelectionDAG &DAG) const; |
Dan Gohman | 55d7b2a | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 1263 | |
| 1264 | /// Emit nodes that will be selected as "cmp Op0,Op1", or something |
Tim Northover | 7b9f86d | 2014-06-10 10:50:11 +0000 | [diff] [blame] | 1265 | /// equivalent, for use with the given x86 condition code. |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 1266 | SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl, |
Tim Northover | 7b9f86d | 2014-06-10 10:50:11 +0000 | [diff] [blame] | 1267 | SelectionDAG &DAG) const; |
Benjamin Kramer | 913da4b | 2012-04-27 12:07:43 +0000 | [diff] [blame] | 1268 | |
| 1269 | /// Convert a comparison if required by the subtarget. |
| 1270 | SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const; |
Sanjay Patel | 957efc23 | 2014-10-24 17:02:16 +0000 | [diff] [blame] | 1271 | |
Nikolai Bozhenov | f679530 | 2016-08-04 12:47:28 +0000 | [diff] [blame] | 1272 | /// Check if replacement of SQRT with RSQRT should be disabled. |
| 1273 | bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override; |
| 1274 | |
Sanjay Patel | 957efc23 | 2014-10-24 17:02:16 +0000 | [diff] [blame] | 1275 | /// Use rsqrt* to speed up sqrt calculations. |
Evandro Menezes | 21f9ce1 | 2016-11-10 23:31:06 +0000 | [diff] [blame] | 1276 | SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, |
| 1277 | int &RefinementSteps, bool &UseOneConstNR, |
| 1278 | bool Reciprocal) const override; |
Sanjay Patel | e2e5892 | 2014-11-11 20:51:00 +0000 | [diff] [blame] | 1279 | |
| 1280 | /// Use rcp* to speed up fdiv calculations. |
Sanjay Patel | 0051efc | 2016-10-20 16:55:45 +0000 | [diff] [blame] | 1281 | SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, |
| 1282 | int &RefinementSteps) const override; |
Sanjay Patel | 7024b81 | 2015-04-15 15:22:55 +0000 | [diff] [blame] | 1283 | |
| 1284 | /// Reassociate floating point divisions into multiply by reciprocal. |
Sanjay Patel | 1dd1559 | 2015-07-28 23:05:48 +0000 | [diff] [blame] | 1285 | unsigned combineRepeatedFPDivisors() const override; |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1286 | }; |
Evan Cheng | 24422d4 | 2008-09-03 00:03:49 +0000 | [diff] [blame] | 1287 | |
| 1288 | namespace X86 { |
Bob Wilson | 3e6fa46 | 2012-08-03 04:06:28 +0000 | [diff] [blame] | 1289 | FastISel *createFastISel(FunctionLoweringInfo &funcInfo, |
| 1290 | const TargetLibraryInfo *libInfo); |
Eugene Zelenko | 6ac3f73 | 2016-01-26 18:48:36 +0000 | [diff] [blame] | 1291 | } // end namespace X86 |
| 1292 | } // end namespace llvm |
Chris Lattner | 76ac068 | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1293 | |
Eugene Zelenko | 6ac3f73 | 2016-01-26 18:48:36 +0000 | [diff] [blame] | 1294 | #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H |