Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	10	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	11	#include "MCTargetDesc/ARMAddressingModes.h"
				12	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	14	#include "llvm/MC/MCContext.h"
				15	#include "llvm/MC/MCExpr.h"
				16	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	17	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	18	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	19	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	20	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	21	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	22	#include "llvm/Support/LEB128.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	23	#include "llvm/Support/MemoryObject.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	24	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	25	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	26	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	27
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	28	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	29
Chandler Carruth	84e68b2	2014-04-22 02:41:26 +0000	[diff] [blame]	30	#define DEBUG_TYPE "arm-disassembler"
				31
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	32	typedef MCDisassembler::DecodeStatus DecodeStatus;
				33
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	34	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	35	// Handles the condition code status of instructions in IT blocks
				36	class ITStatus
				37	{
				38	public:
				39	// Returns the condition code for instruction in IT block
				40	unsigned getITCC() {
				41	unsigned CC = ARMCC::AL;
				42	if (instrInITBlock())
				43	CC = ITStates.back();
				44	return CC;
				45	}
				46
				47	// Advances the IT block state to the next T or E
				48	void advanceITState() {
				49	ITStates.pop_back();
				50	}
				51
				52	// Returns true if the current instruction is in an IT block
				53	bool instrInITBlock() {
				54	return !ITStates.empty();
				55	}
				56
				57	// Returns true if current instruction is the last instruction in an IT block
				58	bool instrLastInITBlock() {
				59	return ITStates.size() == 1;
				60	}
				61
				62	// Called when decoding an IT instruction. Sets the IT state for the following
				63	// instructions that for the IT block. Firstcond and Mask correspond to the
				64	// fields in the IT instruction encoding.
				65	void setITState(char Firstcond, char Mask) {
				66	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	67	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	68	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				70	assert(NumTZ <= 3 && "Invalid IT mask!");
				71	// push condition codes onto the stack the correct order for the pops
				72	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				73	bool T = ((Mask >> Pos) & 1) == CondBit0;
				74	if (T)
				75	ITStates.push_back(CCBits);
				76	else
				77	ITStates.push_back(CCBits ^ 1);
				78	}
				79	ITStates.push_back(CCBits);
				80	}
				81
				82	private:
				83	std::vector<unsigned char> ITStates;
				84	};
				85	}
				86
				87	namespace {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				89	class ARMDisassembler : public MCDisassembler {
				90	public:
				91	/// Constructor - Initializes the disassembler.
				92	///
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	93	ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				94	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95	}
				96
				97	~ARMDisassembler() {
				98	}
				99
				100	/// getInstruction - See MCDisassembler.
Craig Topper	ca7e3e5	2014-03-10 03:19:03 +0000	[diff] [blame]	101	DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
				102	const MemoryObject &region, uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	103	raw_ostream &vStream,
Craig Topper	ca7e3e5	2014-03-10 03:19:03 +0000	[diff] [blame]	104	raw_ostream &cStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	105	};
				106
				107	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				108	class ThumbDisassembler : public MCDisassembler {
				109	public:
				110	/// Constructor - Initializes the disassembler.
				111	///
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	112	ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				113	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	114	}
				115
				116	~ThumbDisassembler() {
				117	}
				118
				119	/// getInstruction - See MCDisassembler.
Craig Topper	ca7e3e5	2014-03-10 03:19:03 +0000	[diff] [blame]	120	DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
				121	const MemoryObject &region, uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	122	raw_ostream &vStream,
Craig Topper	ca7e3e5	2014-03-10 03:19:03 +0000	[diff] [blame]	123	raw_ostream &cStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	124
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	125	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	126	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	127	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	128	void UpdateThumbVFPPredicate(MCInst&) const;
				129	};
				130	}
				131
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	132	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	133	switch (In) {
				134	case MCDisassembler::Success:
				135	// Out stays the same.
				136	return true;
				137	case MCDisassembler::SoftFail:
				138	Out = In;
				139	return true;
				140	case MCDisassembler::Fail:
				141	Out = In;
				142	return false;
				143	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	144	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	145	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	146
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	147
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	148	// Forward declare these because the autogenerated code will reference them.
				149	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	150	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	151	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	152	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	153	unsigned RegNo, uint64_t Address,
				154	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	155	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				156	unsigned RegNo, uint64_t Address,
				157	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	158	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	159	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	160	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	161	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	162	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	163	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	164	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				165	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	168	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	169	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	173	unsigned RegNo,
				174	uint64_t Address,
				175	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	176	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	177	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	178	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	179	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	180	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	181	unsigned RegNo, uint64_t Address,
				182	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	183
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	184	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	185	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	187	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	196
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	197	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	198	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	199	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	200	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	201	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	202	unsigned Insn,
				203	uint64_t Address,
				204	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	205	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	206	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
				213
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	214	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	215	unsigned Insn,
				216	uint64_t Adddress,
				217	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	218	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	219	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	220	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	221	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	222	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	223	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	234	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				235	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	236	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	237	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	238	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	239	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	240	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				241	uint64_t Address, const void *Decoder);
				242	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				243	uint64_t Address, const void *Decoder);
				244	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				245	uint64_t Address, const void *Decoder);
				246	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				247	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	248	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	249	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	250	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	251	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	280	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				281	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	284	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
				285	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	318	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	319	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
				324
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	325
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	326	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	327	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	328	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				347	uint64_t Address, const void* Decoder);
				348	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				349	uint64_t Address, const void* Decoder);
				350	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				351	uint64_t Address, const void* Decoder);
				352	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				353	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	354	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	355	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	356	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	357	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	370	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				371	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	382	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	383	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	384	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	385	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	386	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	387	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	388	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	389	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	390	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	391	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	392	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	393	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	394	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	395	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	396	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	397	uint64_t Address, const void *Decoder);
				398
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	399	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	400	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	401	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				402	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	403	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	404
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	405	static MCDisassembler *createARMDisassembler(const Target &T,
				406	const MCSubtargetInfo &STI,
				407	MCContext &Ctx) {
				408	return new ARMDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	409	}
				410
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	411	static MCDisassembler *createThumbDisassembler(const Target &T,
				412	const MCSubtargetInfo &STI,
				413	MCContext &Ctx) {
				414	return new ThumbDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	415	}
				416
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	417	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	418	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	419	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	420	raw_ostream &os,
				421	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	422	CommentStream = &cs;
				423
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	424	uint8_t bytes[4];
				425
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	426	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				427	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				428
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	429	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	430	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	431	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	432	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	433	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	434
				435	// Encoded as a small-endian 32-bit word in the stream.
				436	uint32_t insn = (bytes[3] << 24) \|
				437	(bytes[2] << 16) \|
				438	(bytes[1] << 8) \|
				439	(bytes[0] << 0);
				440
				441	// Calling the auto-generated decoder function.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	442	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				443	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	444	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	445	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	446	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	447	}
				448
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	449	// VFP and NEON instructions, similarly, are shared between ARM
				450	// and Thumb modes.
				451	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	452	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	453	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	454	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	455	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	456	}
				457
				458	MI.clear();
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	459	result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
				460	if (result != MCDisassembler::Fail) {
				461	Size = 4;
				462	return result;
				463	}
				464
				465	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	466	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				467	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	468	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	469	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	470	// Add a fake predicate operand, because we share these instruction
				471	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	472	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				473	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	474	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	475	}
				476
				477	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	478	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				479	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	480	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	481	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	482	// Add a fake predicate operand, because we share these instruction
				483	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	484	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				485	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	486	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	487	}
				488
				489	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	490	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				491	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	492	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	493	Size = 4;
				494	// Add a fake predicate operand, because we share these instruction
				495	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	496	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				497	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	498	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	499	}
				500
				501	MI.clear();
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	502	result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
				503	this, STI);
				504	if (result != MCDisassembler::Fail) {
				505	Size = 4;
				506	return result;
				507	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	508
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	509	MI.clear();
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	510	result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
				511	this, STI);
				512	if (result != MCDisassembler::Fail) {
				513	Size = 4;
				514	return result;
				515	}
				516
				517	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	518	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	519	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	520	}
				521
				522	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	523	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	524	}
				525
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	526	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				527	/// immediate Value in the MCInst. The immediate Value has had any PC
				528	/// adjustment made by the caller. If the instruction is a branch instruction
				529	/// then isBranch is true, else false. If the getOpInfo() function was set as
				530	/// part of the setupForSymbolicDisassembly() call then that function is called
				531	/// to get any symbolic information at the Address for this instruction. If
				532	/// that returns non-zero then the symbolic information it returns is used to
				533	/// create an MCExpr and that is added as an operand to the MCInst. If
				534	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				535	/// Value is done and if a symbol is found an MCExpr is created with that, else
				536	/// an MCExpr with Value is created. This function returns true if it adds an
				537	/// operand to the MCInst and false otherwise.
				538	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				539	bool isBranch, uint64_t InstSize,
				540	MCInst &MI, const void *Decoder) {
				541	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	542	// FIXME: Does it make sense for value to be negative?
				543	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				544	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	545	}
				546
				547	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				548	/// referenced by a load instruction with the base register that is the Pc.
				549	/// These can often be values in a literal pool near the Address of the
				550	/// instruction. The Address of the instruction and its immediate Value are
				551	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	552	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	553	/// the referenced address is that of a symbol. Or it will return a pointer to
				554	/// a literal 'C' string if the referenced address of the literal pool's entry
				555	/// is an address into a section with 'C' string literals.
				556	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	557	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	558	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	559	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	560	}
				561
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	562	// Thumb1 instructions don't have explicit S bits. Rather, they
				563	// implicitly set CPSR. Since it's not represented in the encoding, the
				564	// auto-generated decoder won't inject the CPSR operand. We need to fix
				565	// that as a post-pass.
				566	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				567	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	568	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	569	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	570	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				571	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	572	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	573	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	574	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				575	return;
				576	}
				577	}
				578
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	579	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	580	}
				581
				582	// Most Thumb instructions don't have explicit predicates in the
				583	// encoding, but rather get their predicates from IT context. We need
				584	// to fix up the predicate operands using this context information as a
				585	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	586	MCDisassembler::DecodeStatus
				587	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	588	MCDisassembler::DecodeStatus S = Success;
				589
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	590	// A few instructions actually have predicates encoded in them. Don't
				591	// try to overwrite it if we're seeing one of those.
				592	switch (MI.getOpcode()) {
				593	case ARM::tBcc:
				594	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	595	case ARM::tCBZ:
				596	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	597	case ARM::tCPS:
				598	case ARM::t2CPS3p:
				599	case ARM::t2CPS2p:
				600	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	601	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	602	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	603	// Some instructions (mostly conditional branches) are not
				604	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	605	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	606	S = SoftFail;
				607	else
				608	return Success;
				609	break;
				610	case ARM::tB:
				611	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	612	case ARM::t2TBB:
				613	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	614	// Some instructions (mostly unconditional branches) can
				615	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	616	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	617	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	618	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	619	default:
				620	break;
				621	}
				622
				623	// If we're in an IT block, base the predicate on that. Otherwise,
				624	// assume a predicate of AL.
				625	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	626	CC = ITBlock.getITCC();
				627	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	628	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	629	if (ITBlock.instrInITBlock())
				630	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	631
				632	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	633	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	634	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	635	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				636	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	637	if (OpInfo[i].isPredicate()) {
				638	I = MI.insert(I, MCOperand::CreateImm(CC));
				639	++I;
				640	if (CC == ARMCC::AL)
				641	MI.insert(I, MCOperand::CreateReg(0));
				642	else
				643	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	644	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	645	}
				646	}
				647
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	648	I = MI.insert(I, MCOperand::CreateImm(CC));
				649	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	650	if (CC == ARMCC::AL)
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	651	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	652	else
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	653	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	654
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	655	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	656	}
				657
				658	// Thumb VFP instructions are a special case. Because we share their
				659	// encodings between ARM and Thumb modes, and they are predicable in ARM
				660	// mode, the auto-generated decoder will give them an (incorrect)
				661	// predicate operand. We need to rewrite these operands based on the IT
				662	// context as a post-pass.
				663	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				664	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	665	CC = ITBlock.getITCC();
				666	if (ITBlock.instrInITBlock())
				667	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	668
				669	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				670	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	671	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				672	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	673	if (OpInfo[i].isPredicate() ) {
				674	I->setImm(CC);
				675	++I;
				676	if (CC == ARMCC::AL)
				677	I->setReg(0);
				678	else
				679	I->setReg(ARM::CPSR);
				680	return;
				681	}
				682	}
				683	}
				684
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	685	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	686	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	687	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	688	raw_ostream &os,
				689	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	690	CommentStream = &cs;
				691
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	692	uint8_t bytes[4];
				693
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	694	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				695	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				696
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	697	// We want to read exactly 2 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	698	if (Region.readBytes(Address, 2, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	699	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	700	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	701	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	702
				703	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	704	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				705	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	706	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	707	Size = 2;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	708	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	709	return result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	710	}
				711
				712	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	713	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				714	Address, this, STI);
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	715	if (result) {
				716	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	717	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	718	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	719	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	720	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	721	}
				722
				723	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	724	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				725	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	726	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	727	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	728
				729	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				730	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	731	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	732	result = MCDisassembler::SoftFail;
				733
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	734	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	735
				736	// If we find an IT instruction, we need to parse its condition
				737	// code and mask operands so that we can apply them correctly
				738	// to the subsequent instructions.
				739	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	740
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	741	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	742	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	743	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	744	}
				745
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	746	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	747	}
				748
				749	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	750	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	751	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	752	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	753	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	754
				755	uint32_t insn32 = (bytes[3] << 8) \|
				756	(bytes[2] << 0) \|
				757	(bytes[1] << 24) \|
				758	(bytes[0] << 16);
				759	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	760	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				761	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	762	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	763	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	764	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	765	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	766	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	767	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	768	}
				769
				770	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	771	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				772	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	773	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	774	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	775	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	776	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	777	}
				778
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	779	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				780	MI.clear();
				781	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
				782	if (result != MCDisassembler::Fail) {
				783	Size = 4;
				784	UpdateThumbVFPPredicate(MI);
				785	return result;
				786	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	787	}
				788
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	789	MI.clear();
				790	result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
				791	if (result != MCDisassembler::Fail) {
				792	Size = 4;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	793	return result;
				794	}
				795
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	796	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				797	MI.clear();
				798	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				799	this, STI);
				800	if (result != MCDisassembler::Fail) {
				801	Size = 4;
				802	Check(result, AddThumbPredicate(MI));
				803	return result;
				804	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	805	}
				806
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	807	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	808	MI.clear();
				809	uint32_t NEONLdStInsn = insn32;
				810	NEONLdStInsn &= 0xF0FFFFFF;
				811	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	812	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				813	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	814	if (result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	815	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	816	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	817	return result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	818	}
				819	}
				820
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	821	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	822	MI.clear();
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	823	uint32_t NEONDataInsn = insn32;
				824	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				825	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				826	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	827	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				828	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	829	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	830	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	831	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	832	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	833	}
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	834
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	835	MI.clear();
				836	uint32_t NEONCryptoInsn = insn32;
				837	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				838	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				839	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
				840	result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
				841	Address, this, STI);
				842	if (result != MCDisassembler::Fail) {
				843	Size = 4;
				844	return result;
				845	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	846
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	847	MI.clear();
				848	uint32_t NEONv8Insn = insn32;
				849	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
				850	result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
				851	this, STI);
				852	if (result != MCDisassembler::Fail) {
				853	Size = 4;
				854	return result;
				855	}
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	856	}
				857
				858	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	859	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	860	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	861	}
				862
				863
				864	extern "C" void LLVMInitializeARMDisassembler() {
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	865	TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	866	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	867	TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	868	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	869	TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	870	createThumbDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	871	TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	872	createThumbDisassembler);
				873	}
				874
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	875	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	876	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				877	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				878	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				879	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				880	};
				881
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	882	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	883	uint64_t Address, const void *Decoder) {
				884	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	885	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	886
				887	unsigned Register = GPRDecoderTable[RegNo];
				888	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	889	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	890	}
				891
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	892	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	893	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	894	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	895	DecodeStatus S = MCDisassembler::Success;
				896
				897	if (RegNo == 15)
				898	S = MCDisassembler::SoftFail;
				899
				900	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				901
				902	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	903	}
				904
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	905	static DecodeStatus
				906	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				907	uint64_t Address, const void *Decoder) {
				908	DecodeStatus S = MCDisassembler::Success;
				909
				910	if (RegNo == 15)
				911	{
				912	Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
				913	return MCDisassembler::Success;
				914	}
				915
				916	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				917	return S;
				918	}
				919
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	920	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	921	uint64_t Address, const void *Decoder) {
				922	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	923	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	924	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				925	}
				926
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	927	static const uint16_t GPRPairDecoderTable[] = {
				928	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				929	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				930	};
				931
				932	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				933	uint64_t Address, const void *Decoder) {
				934	DecodeStatus S = MCDisassembler::Success;
				935
				936	if (RegNo > 13)
				937	return MCDisassembler::Fail;
				938
				939	if ((RegNo & 1) \|\| RegNo == 0xe)
				940	S = MCDisassembler::SoftFail;
				941
				942	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
				943	Inst.addOperand(MCOperand::CreateReg(RegisterPair));
				944	return S;
				945	}
				946
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	947	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	948	uint64_t Address, const void *Decoder) {
				949	unsigned Register = 0;
				950	switch (RegNo) {
				951	case 0:
				952	Register = ARM::R0;
				953	break;
				954	case 1:
				955	Register = ARM::R1;
				956	break;
				957	case 2:
				958	Register = ARM::R2;
				959	break;
				960	case 3:
				961	Register = ARM::R3;
				962	break;
				963	case 9:
				964	Register = ARM::R9;
				965	break;
				966	case 12:
				967	Register = ARM::R12;
				968	break;
				969	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	970	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	971	}
				972
				973	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	974	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	975	}
				976
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	977	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	978	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	979	DecodeStatus S = MCDisassembler::Success;
				980	if (RegNo == 13 \|\| RegNo == 15)
				981	S = MCDisassembler::SoftFail;
				982	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				983	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	984	}
				985
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	986	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	987	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				988	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				989	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				990	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				991	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				992	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				993	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				994	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				995	};
				996
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	997	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	998	uint64_t Address, const void *Decoder) {
				999	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1000	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1001
				1002	unsigned Register = SPRDecoderTable[RegNo];
				1003	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1004	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1005	}
				1006
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1007	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1008	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1009	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1010	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1011	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1012	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1013	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1014	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1015	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1016	};
				1017
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1018	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1019	uint64_t Address, const void *Decoder) {
				1020	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1021	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1022
				1023	unsigned Register = DPRDecoderTable[RegNo];
				1024	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1025	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1026	}
				1027
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1028	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1029	uint64_t Address, const void *Decoder) {
				1030	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1031	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1032	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1033	}
				1034
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1035	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1036	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1037	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1038	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1039	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1040	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1041	}
				1042
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1043	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1044	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1045	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1046	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1047	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1048	};
				1049
				1050
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1051	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1052	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1053	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1054	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1055	RegNo >>= 1;
				1056
				1057	unsigned Register = QPRDecoderTable[RegNo];
				1058	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1059	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1060	}
				1061
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1062	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1063	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1064	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1065	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1066	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1067	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1068	ARM::Q15
				1069	};
				1070
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1071	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1072	uint64_t Address, const void *Decoder) {
				1073	if (RegNo > 30)
				1074	return MCDisassembler::Fail;
				1075
				1076	unsigned Register = DPairDecoderTable[RegNo];
				1077	Inst.addOperand(MCOperand::CreateReg(Register));
				1078	return MCDisassembler::Success;
				1079	}
				1080
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1081	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1082	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1083	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1084	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1085	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1086	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1087	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1088	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1089	ARM::D28_D30, ARM::D29_D31
				1090	};
				1091
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1092	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1093	unsigned RegNo,
				1094	uint64_t Address,
				1095	const void *Decoder) {
				1096	if (RegNo > 29)
				1097	return MCDisassembler::Fail;
				1098
				1099	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1100	Inst.addOperand(MCOperand::CreateReg(Register));
				1101	return MCDisassembler::Success;
				1102	}
				1103
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1104	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1105	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1106	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1107	// AL predicate is not allowed on Thumb1 branches.
				1108	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1109	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1110	Inst.addOperand(MCOperand::CreateImm(Val));
				1111	if (Val == ARMCC::AL) {
				1112	Inst.addOperand(MCOperand::CreateReg(0));
				1113	} else
				1114	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1115	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1116	}
				1117
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1118	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1119	uint64_t Address, const void *Decoder) {
				1120	if (Val)
				1121	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1122	else
				1123	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1124	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1125	}
				1126
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1127	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1128	uint64_t Address, const void *Decoder) {
				1129	uint32_t imm = Val & 0xFF;
				1130	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	a7ad9f3	2011-10-13 23:36:06 +0000	[diff] [blame]	1131	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1132	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1133	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1134	}
				1135
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1136	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1137	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1138	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1139
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1140	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1141	unsigned type = fieldFromInstruction(Val, 5, 2);
				1142	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1143
				1144	// Register-immediate
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1145	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1146	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1147
				1148	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1149	switch (type) {
				1150	case 0:
				1151	Shift = ARM_AM::lsl;
				1152	break;
				1153	case 1:
				1154	Shift = ARM_AM::lsr;
				1155	break;
				1156	case 2:
				1157	Shift = ARM_AM::asr;
				1158	break;
				1159	case 3:
				1160	Shift = ARM_AM::ror;
				1161	break;
				1162	}
				1163
				1164	if (Shift == ARM_AM::ror && imm == 0)
				1165	Shift = ARM_AM::rrx;
				1166
				1167	unsigned Op = Shift \| (imm << 3);
				1168	Inst.addOperand(MCOperand::CreateImm(Op));
				1169
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1170	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1171	}
				1172
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1173	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1174	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1175	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1176
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1177	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1178	unsigned type = fieldFromInstruction(Val, 5, 2);
				1179	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1180
				1181	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1182	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1183	return MCDisassembler::Fail;
				1184	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1185	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1186
				1187	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1188	switch (type) {
				1189	case 0:
				1190	Shift = ARM_AM::lsl;
				1191	break;
				1192	case 1:
				1193	Shift = ARM_AM::lsr;
				1194	break;
				1195	case 2:
				1196	Shift = ARM_AM::asr;
				1197	break;
				1198	case 3:
				1199	Shift = ARM_AM::ror;
				1200	break;
				1201	}
				1202
				1203	Inst.addOperand(MCOperand::CreateImm(Shift));
				1204
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1205	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1206	}
				1207
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1208	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1209	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1210	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1211
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1212	bool NeedDisjointWriteback = false;
				1213	unsigned WritebackReg = 0;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1214	switch (Inst.getOpcode()) {
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1215	default:
				1216	break;
				1217	case ARM::LDMIA_UPD:
				1218	case ARM::LDMDB_UPD:
				1219	case ARM::LDMIB_UPD:
				1220	case ARM::LDMDA_UPD:
				1221	case ARM::t2LDMIA_UPD:
				1222	case ARM::t2LDMDB_UPD:
				1223	case ARM::t2STMIA_UPD:
				1224	case ARM::t2STMDB_UPD:
				1225	NeedDisjointWriteback = true;
				1226	WritebackReg = Inst.getOperand(0).getReg();
				1227	break;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1228	}
				1229
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1230	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1231	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1232	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1233	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1234	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1235	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1236	// Writeback not allowed if Rn is in the target list.
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1237	if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1238	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1239	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1240	}
				1241
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1242	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1243	}
				1244
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1245	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1246	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1247	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1248
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1249	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1250	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1251
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1252	// In case of unpredictable encoding, tweak the operands.
				1253	if (regs == 0 \|\| (Vd + regs) > 32) {
				1254	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1255	regs = std::max( 1u, regs);
				1256	S = MCDisassembler::SoftFail;
				1257	}
				1258
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1259	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1260	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1261	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1262	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1263	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1264	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1265
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1266	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1267	}
				1268
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1269	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1270	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1271	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1272
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1273	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1274	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1275
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1276	// In case of unpredictable encoding, tweak the operands.
				1277	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1278	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1279	regs = std::max( 1u, regs);
				1280	regs = std::min(16u, regs);
				1281	S = MCDisassembler::SoftFail;
				1282	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1283
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1284	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1285	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1286	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1287	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1288	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1289	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1290
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1291	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1292	}
				1293
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1294	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1295	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1296	// This operand encodes a mask of contiguous zeros between a specified MSB
				1297	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1298	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1299	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1300	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1301	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1302	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1303
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1304	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1305	if (lsb > msb) {
				1306	Check(S, MCDisassembler::SoftFail);
				1307	// The check above will cause the warning for the "potentially undefined
				1308	// instruction encoding" but we can't build a bad MCOperand value here
				1309	// with a lsb > msb or else printing the MCInst will cause a crash.
				1310	lsb = msb;
				1311	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1312
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1313	uint32_t msb_mask = 0xFFFFFFFF;
				1314	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1315	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1316
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1317	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1318	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1319	}
				1320
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1321	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1322	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1323	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1324
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1325	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1326	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1327	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1328	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1329	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1330	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1331
				1332	switch (Inst.getOpcode()) {
				1333	case ARM::LDC_OFFSET:
				1334	case ARM::LDC_PRE:
				1335	case ARM::LDC_POST:
				1336	case ARM::LDC_OPTION:
				1337	case ARM::LDCL_OFFSET:
				1338	case ARM::LDCL_PRE:
				1339	case ARM::LDCL_POST:
				1340	case ARM::LDCL_OPTION:
				1341	case ARM::STC_OFFSET:
				1342	case ARM::STC_PRE:
				1343	case ARM::STC_POST:
				1344	case ARM::STC_OPTION:
				1345	case ARM::STCL_OFFSET:
				1346	case ARM::STCL_PRE:
				1347	case ARM::STCL_POST:
				1348	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1349	case ARM::t2LDC_OFFSET:
				1350	case ARM::t2LDC_PRE:
				1351	case ARM::t2LDC_POST:
				1352	case ARM::t2LDC_OPTION:
				1353	case ARM::t2LDCL_OFFSET:
				1354	case ARM::t2LDCL_PRE:
				1355	case ARM::t2LDCL_POST:
				1356	case ARM::t2LDCL_OPTION:
				1357	case ARM::t2STC_OFFSET:
				1358	case ARM::t2STC_PRE:
				1359	case ARM::t2STC_POST:
				1360	case ARM::t2STC_OPTION:
				1361	case ARM::t2STCL_OFFSET:
				1362	case ARM::t2STCL_PRE:
				1363	case ARM::t2STCL_POST:
				1364	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1365	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1366	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1367	break;
				1368	default:
				1369	break;
				1370	}
				1371
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	1372	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				1373	.getFeatureBits();
				1374	if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
				1375	return MCDisassembler::Fail;
				1376
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1377	Inst.addOperand(MCOperand::CreateImm(coproc));
				1378	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1379	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1380	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1381
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1382	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1383	case ARM::t2LDC2_OFFSET:
				1384	case ARM::t2LDC2L_OFFSET:
				1385	case ARM::t2LDC2_PRE:
				1386	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1387	case ARM::t2STC2_OFFSET:
				1388	case ARM::t2STC2L_OFFSET:
				1389	case ARM::t2STC2_PRE:
				1390	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1391	case ARM::LDC2_OFFSET:
				1392	case ARM::LDC2L_OFFSET:
				1393	case ARM::LDC2_PRE:
				1394	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1395	case ARM::STC2_OFFSET:
				1396	case ARM::STC2L_OFFSET:
				1397	case ARM::STC2_PRE:
				1398	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1399	case ARM::t2LDC_OFFSET:
				1400	case ARM::t2LDCL_OFFSET:
				1401	case ARM::t2LDC_PRE:
				1402	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1403	case ARM::t2STC_OFFSET:
				1404	case ARM::t2STCL_OFFSET:
				1405	case ARM::t2STC_PRE:
				1406	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1407	case ARM::LDC_OFFSET:
				1408	case ARM::LDCL_OFFSET:
				1409	case ARM::LDC_PRE:
				1410	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1411	case ARM::STC_OFFSET:
				1412	case ARM::STCL_OFFSET:
				1413	case ARM::STC_PRE:
				1414	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1415	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1416	Inst.addOperand(MCOperand::CreateImm(imm));
				1417	break;
				1418	case ARM::t2LDC2_POST:
				1419	case ARM::t2LDC2L_POST:
				1420	case ARM::t2STC2_POST:
				1421	case ARM::t2STC2L_POST:
				1422	case ARM::LDC2_POST:
				1423	case ARM::LDC2L_POST:
				1424	case ARM::STC2_POST:
				1425	case ARM::STC2L_POST:
				1426	case ARM::t2LDC_POST:
				1427	case ARM::t2LDCL_POST:
				1428	case ARM::t2STC_POST:
				1429	case ARM::t2STCL_POST:
				1430	case ARM::LDC_POST:
				1431	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1432	case ARM::STC_POST:
				1433	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1434	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1435	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1436	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1437	// The 'option' variant doesn't encode 'U' in the immediate since
				1438	// the immediate is unsigned [0,255].
				1439	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1440	break;
				1441	}
				1442
				1443	switch (Inst.getOpcode()) {
				1444	case ARM::LDC_OFFSET:
				1445	case ARM::LDC_PRE:
				1446	case ARM::LDC_POST:
				1447	case ARM::LDC_OPTION:
				1448	case ARM::LDCL_OFFSET:
				1449	case ARM::LDCL_PRE:
				1450	case ARM::LDCL_POST:
				1451	case ARM::LDCL_OPTION:
				1452	case ARM::STC_OFFSET:
				1453	case ARM::STC_PRE:
				1454	case ARM::STC_POST:
				1455	case ARM::STC_OPTION:
				1456	case ARM::STCL_OFFSET:
				1457	case ARM::STCL_PRE:
				1458	case ARM::STCL_POST:
				1459	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1460	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1461	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1462	break;
				1463	default:
				1464	break;
				1465	}
				1466
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1467	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1468	}
				1469
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1470	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1471	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1472	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1473	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1474
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1475	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1476	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1477	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1478	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1479	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1480	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1481	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1482	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1483
				1484	// On stores, the writeback operand precedes Rt.
				1485	switch (Inst.getOpcode()) {
				1486	case ARM::STR_POST_IMM:
				1487	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1488	case ARM::STRB_POST_IMM:
				1489	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1490	case ARM::STRT_POST_REG:
				1491	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1492	case ARM::STRBT_POST_REG:
				1493	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1494	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1495	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1496	break;
				1497	default:
				1498	break;
				1499	}
				1500
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1501	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1502	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1503
				1504	// On loads, the writeback operand comes after Rt.
				1505	switch (Inst.getOpcode()) {
				1506	case ARM::LDR_POST_IMM:
				1507	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1508	case ARM::LDRB_POST_IMM:
				1509	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1510	case ARM::LDRBT_POST_REG:
				1511	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1512	case ARM::LDRT_POST_REG:
				1513	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1514	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1515	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1516	break;
				1517	default:
				1518	break;
				1519	}
				1520
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1521	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1522	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1523
				1524	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1525	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1526	Op = ARM_AM::sub;
				1527
				1528	bool writeback = (P == 0) \|\| (W == 1);
				1529	unsigned idx_mode = 0;
				1530	if (P && writeback)
				1531	idx_mode = ARMII::IndexModePre;
				1532	else if (!P && writeback)
				1533	idx_mode = ARMII::IndexModePost;
				1534
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1535	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1536	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1537
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1538	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1539	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1540	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1541	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1542	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1543	case 0:
				1544	Opc = ARM_AM::lsl;
				1545	break;
				1546	case 1:
				1547	Opc = ARM_AM::lsr;
				1548	break;
				1549	case 2:
				1550	Opc = ARM_AM::asr;
				1551	break;
				1552	case 3:
				1553	Opc = ARM_AM::ror;
				1554	break;
				1555	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1556	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1557	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1558	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1559	if (Opc == ARM_AM::ror && amt == 0)
				1560	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1561	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1562
				1563	Inst.addOperand(MCOperand::CreateImm(imm));
				1564	} else {
				1565	Inst.addOperand(MCOperand::CreateReg(0));
				1566	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1567	Inst.addOperand(MCOperand::CreateImm(tmp));
				1568	}
				1569
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1570	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1571	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1572
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1573	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1574	}
				1575
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1576	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1577	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1578	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1579
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1580	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1581	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1582	unsigned type = fieldFromInstruction(Val, 5, 2);
				1583	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1584	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1585
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1586	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1587	switch (type) {
				1588	case 0:
				1589	ShOp = ARM_AM::lsl;
				1590	break;
				1591	case 1:
				1592	ShOp = ARM_AM::lsr;
				1593	break;
				1594	case 2:
				1595	ShOp = ARM_AM::asr;
				1596	break;
				1597	case 3:
				1598	ShOp = ARM_AM::ror;
				1599	break;
				1600	}
				1601
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1602	if (ShOp == ARM_AM::ror && imm == 0)
				1603	ShOp = ARM_AM::rrx;
				1604
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1605	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1606	return MCDisassembler::Fail;
				1607	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1608	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1609	unsigned shift;
				1610	if (U)
				1611	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1612	else
				1613	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1614	Inst.addOperand(MCOperand::CreateImm(shift));
				1615
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1616	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1617	}
				1618
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1619	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1620	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1621	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1622	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1623
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1624	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1625	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1626	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1627	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1628	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1629	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1630	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1631	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1632	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1633	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1634
				1635	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1636
				1637	// For {LD,ST}RD, Rt must be even, else undefined.
				1638	switch (Inst.getOpcode()) {
				1639	case ARM::STRD:
				1640	case ARM::STRD_PRE:
				1641	case ARM::STRD_POST:
				1642	case ARM::LDRD:
				1643	case ARM::LDRD_PRE:
				1644	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1645	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1646	break;
				1647	default:
				1648	break;
				1649	}
				1650	switch (Inst.getOpcode()) {
				1651	case ARM::STRD:
				1652	case ARM::STRD_PRE:
				1653	case ARM::STRD_POST:
				1654	if (P == 0 && W == 1)
				1655	S = MCDisassembler::SoftFail;
				1656
				1657	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1658	S = MCDisassembler::SoftFail;
				1659	if (type && Rm == 15)
				1660	S = MCDisassembler::SoftFail;
				1661	if (Rt2 == 15)
				1662	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1663	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1664	S = MCDisassembler::SoftFail;
				1665	break;
				1666	case ARM::STRH:
				1667	case ARM::STRH_PRE:
				1668	case ARM::STRH_POST:
				1669	if (Rt == 15)
				1670	S = MCDisassembler::SoftFail;
				1671	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1672	S = MCDisassembler::SoftFail;
				1673	if (!type && Rm == 15)
				1674	S = MCDisassembler::SoftFail;
				1675	break;
				1676	case ARM::LDRD:
				1677	case ARM::LDRD_PRE:
				1678	case ARM::LDRD_POST:
				1679	if (type && Rn == 15){
				1680	if (Rt2 == 15)
				1681	S = MCDisassembler::SoftFail;
				1682	break;
				1683	}
				1684	if (P == 0 && W == 1)
				1685	S = MCDisassembler::SoftFail;
				1686	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1687	S = MCDisassembler::SoftFail;
				1688	if (!type && writeback && Rn == 15)
				1689	S = MCDisassembler::SoftFail;
				1690	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1691	S = MCDisassembler::SoftFail;
				1692	break;
				1693	case ARM::LDRH:
				1694	case ARM::LDRH_PRE:
				1695	case ARM::LDRH_POST:
				1696	if (type && Rn == 15){
				1697	if (Rt == 15)
				1698	S = MCDisassembler::SoftFail;
				1699	break;
				1700	}
				1701	if (Rt == 15)
				1702	S = MCDisassembler::SoftFail;
				1703	if (!type && Rm == 15)
				1704	S = MCDisassembler::SoftFail;
				1705	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1706	S = MCDisassembler::SoftFail;
				1707	break;
				1708	case ARM::LDRSH:
				1709	case ARM::LDRSH_PRE:
				1710	case ARM::LDRSH_POST:
				1711	case ARM::LDRSB:
				1712	case ARM::LDRSB_PRE:
				1713	case ARM::LDRSB_POST:
				1714	if (type && Rn == 15){
				1715	if (Rt == 15)
				1716	S = MCDisassembler::SoftFail;
				1717	break;
				1718	}
				1719	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1720	S = MCDisassembler::SoftFail;
				1721	if (!type && (Rt == 15 \|\| Rm == 15))
				1722	S = MCDisassembler::SoftFail;
				1723	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1724	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1725	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1726	default:
				1727	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1728	}
				1729
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1730	if (writeback) { // Writeback
				1731	if (P)
				1732	U \|= ARMII::IndexModePre << 9;
				1733	else
				1734	U \|= ARMII::IndexModePost << 9;
				1735
				1736	// On stores, the writeback operand precedes Rt.
				1737	switch (Inst.getOpcode()) {
				1738	case ARM::STRD:
				1739	case ARM::STRD_PRE:
				1740	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1741	case ARM::STRH:
				1742	case ARM::STRH_PRE:
				1743	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1744	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1745	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1746	break;
				1747	default:
				1748	break;
				1749	}
				1750	}
				1751
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1752	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1753	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1754	switch (Inst.getOpcode()) {
				1755	case ARM::STRD:
				1756	case ARM::STRD_PRE:
				1757	case ARM::STRD_POST:
				1758	case ARM::LDRD:
				1759	case ARM::LDRD_PRE:
				1760	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1761	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1762	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1763	break;
				1764	default:
				1765	break;
				1766	}
				1767
				1768	if (writeback) {
				1769	// On loads, the writeback operand comes after Rt.
				1770	switch (Inst.getOpcode()) {
				1771	case ARM::LDRD:
				1772	case ARM::LDRD_PRE:
				1773	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1774	case ARM::LDRH:
				1775	case ARM::LDRH_PRE:
				1776	case ARM::LDRH_POST:
				1777	case ARM::LDRSH:
				1778	case ARM::LDRSH_PRE:
				1779	case ARM::LDRSH_POST:
				1780	case ARM::LDRSB:
				1781	case ARM::LDRSB_PRE:
				1782	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1783	case ARM::LDRHTr:
				1784	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1785	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1786	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1787	break;
				1788	default:
				1789	break;
				1790	}
				1791	}
				1792
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1793	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1794	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1795
				1796	if (type) {
				1797	Inst.addOperand(MCOperand::CreateReg(0));
				1798	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1799	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1800	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1801	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1802	Inst.addOperand(MCOperand::CreateImm(U));
				1803	}
				1804
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1805	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1806	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1807
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1808	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1809	}
				1810
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1811	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1812	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1813	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1814
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1815	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1816	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1817
				1818	switch (mode) {
				1819	case 0:
				1820	mode = ARM_AM::da;
				1821	break;
				1822	case 1:
				1823	mode = ARM_AM::ia;
				1824	break;
				1825	case 2:
				1826	mode = ARM_AM::db;
				1827	break;
				1828	case 3:
				1829	mode = ARM_AM::ib;
				1830	break;
				1831	}
				1832
				1833	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1834	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1835	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1836
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1837	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1838	}
				1839
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1840	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1841	uint64_t Address, const void *Decoder) {
				1842	DecodeStatus S = MCDisassembler::Success;
				1843
				1844	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1845	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1846	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1847	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1848
				1849	if (pred == 0xF)
				1850	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1851
				1852	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1853	return MCDisassembler::Fail;
				1854	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1855	return MCDisassembler::Fail;
				1856	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1857	return MCDisassembler::Fail;
				1858	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1859	return MCDisassembler::Fail;
				1860	return S;
				1861	}
				1862
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1863	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1864	unsigned Insn,
				1865	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1866	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1867
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1868	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1869	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1870	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1871
				1872	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1873	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1874	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1875	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1876	Inst.setOpcode(ARM::RFEDA);
				1877	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1878	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1879	Inst.setOpcode(ARM::RFEDA_UPD);
				1880	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1881	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1882	Inst.setOpcode(ARM::RFEDB);
				1883	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1884	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1885	Inst.setOpcode(ARM::RFEDB_UPD);
				1886	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1887	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1888	Inst.setOpcode(ARM::RFEIA);
				1889	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1890	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1891	Inst.setOpcode(ARM::RFEIA_UPD);
				1892	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1893	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1894	Inst.setOpcode(ARM::RFEIB);
				1895	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1896	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1897	Inst.setOpcode(ARM::RFEIB_UPD);
				1898	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1899	case ARM::STMDA:
				1900	Inst.setOpcode(ARM::SRSDA);
				1901	break;
				1902	case ARM::STMDA_UPD:
				1903	Inst.setOpcode(ARM::SRSDA_UPD);
				1904	break;
				1905	case ARM::STMDB:
				1906	Inst.setOpcode(ARM::SRSDB);
				1907	break;
				1908	case ARM::STMDB_UPD:
				1909	Inst.setOpcode(ARM::SRSDB_UPD);
				1910	break;
				1911	case ARM::STMIA:
				1912	Inst.setOpcode(ARM::SRSIA);
				1913	break;
				1914	case ARM::STMIA_UPD:
				1915	Inst.setOpcode(ARM::SRSIA_UPD);
				1916	break;
				1917	case ARM::STMIB:
				1918	Inst.setOpcode(ARM::SRSIB);
				1919	break;
				1920	case ARM::STMIB_UPD:
				1921	Inst.setOpcode(ARM::SRSIB_UPD);
				1922	break;
				1923	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1924	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1925	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1926
				1927	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1928	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1929	// Check SRS encoding constraints
				1930	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1931	fieldFromInstruction(Insn, 20, 1) == 0))
				1932	return MCDisassembler::Fail;
				1933
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1934	Inst.addOperand(
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1935	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1936	return S;
				1937	}
				1938
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1939	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1940	}
				1941
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1942	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1943	return MCDisassembler::Fail;
				1944	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1945	return MCDisassembler::Fail; // Tied
				1946	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1947	return MCDisassembler::Fail;
				1948	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1949	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1950
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1951	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1952	}
				1953
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1954	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1955	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1956	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1957	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1958	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1959	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1960
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1961	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1962
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1963	// This decoder is called from multiple location that do not check
				1964	// the full encoding is valid before they do.
				1965	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1966	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1967	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1968	return MCDisassembler::Fail;
				1969
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1970	// imod == '01' --> UNPREDICTABLE
				1971	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1972	// return failure here. The '01' imod value is unprintable, so there's
				1973	// nothing useful we could do even if we returned UNPREDICTABLE.
				1974
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1975	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1976
				1977	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1978	Inst.setOpcode(ARM::CPS3p);
				1979	Inst.addOperand(MCOperand::CreateImm(imod));
				1980	Inst.addOperand(MCOperand::CreateImm(iflags));
				1981	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1982	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1983	Inst.setOpcode(ARM::CPS2p);
				1984	Inst.addOperand(MCOperand::CreateImm(imod));
				1985	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1986	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1987	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1988	Inst.setOpcode(ARM::CPS1p);
				1989	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1990	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1991	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1992	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1993	Inst.setOpcode(ARM::CPS1p);
				1994	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1995	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1996	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1997
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1998	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1999	}
				2000
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2001	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2002	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2003	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				2004	unsigned M = fieldFromInstruction(Insn, 8, 1);
				2005	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				2006	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2007
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2008	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2009
				2010	// imod == '01' --> UNPREDICTABLE
				2011	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2012	// return failure here. The '01' imod value is unprintable, so there's
				2013	// nothing useful we could do even if we returned UNPREDICTABLE.
				2014
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2015	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2016
				2017	if (imod && M) {
				2018	Inst.setOpcode(ARM::t2CPS3p);
				2019	Inst.addOperand(MCOperand::CreateImm(imod));
				2020	Inst.addOperand(MCOperand::CreateImm(iflags));
				2021	Inst.addOperand(MCOperand::CreateImm(mode));
				2022	} else if (imod && !M) {
				2023	Inst.setOpcode(ARM::t2CPS2p);
				2024	Inst.addOperand(MCOperand::CreateImm(imod));
				2025	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2026	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2027	} else if (!imod && M) {
				2028	Inst.setOpcode(ARM::t2CPS1p);
				2029	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2030	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2031	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2032	// imod == '00' && M == '0' --> this is a HINT instruction
				2033	int imm = fieldFromInstruction(Insn, 0, 8);
				2034	// HINT are defined only for immediate in [0..4]
				2035	if(imm > 4) return MCDisassembler::Fail;
				2036	Inst.setOpcode(ARM::t2HINT);
				2037	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2038	}
				2039
				2040	return S;
				2041	}
				2042
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2043	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2044	uint64_t Address, const void *Decoder) {
				2045	DecodeStatus S = MCDisassembler::Success;
				2046
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2047	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2048	unsigned imm = 0;
				2049
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2050	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2051	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2052	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2053	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2054
				2055	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2056	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2057	return MCDisassembler::Fail;
				2058	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2059	return MCDisassembler::Fail;
				2060
				2061	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2062	Inst.addOperand(MCOperand::CreateImm(imm));
				2063
				2064	return S;
				2065	}
				2066
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2067	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2068	uint64_t Address, const void *Decoder) {
				2069	DecodeStatus S = MCDisassembler::Success;
				2070
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2071	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2072	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2073	unsigned imm = 0;
				2074
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2075	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2076	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2077
				2078	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2079	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2080	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2081
				2082	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2083	return MCDisassembler::Fail;
				2084
				2085	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2086	Inst.addOperand(MCOperand::CreateImm(imm));
				2087
				2088	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2089	return MCDisassembler::Fail;
				2090
				2091	return S;
				2092	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2093
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2094	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2095	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2096	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2097
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2098	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2099	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2100	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2101	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2102	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2103
				2104	if (pred == 0xF)
				2105	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2106
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2107	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2108	return MCDisassembler::Fail;
				2109	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2110	return MCDisassembler::Fail;
				2111	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2112	return MCDisassembler::Fail;
				2113	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2114	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2115
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2116	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2117	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2118
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2119	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2120	}
				2121
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2122	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2123	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2124	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2125
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2126	unsigned add = fieldFromInstruction(Val, 12, 1);
				2127	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2128	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2129
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2130	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2131	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2132
				2133	if (!add) imm *= -1;
				2134	if (imm == 0 && !add) imm = INT32_MIN;
				2135	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2136	if (Rn == 15)
				2137	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2138
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2139	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2140	}
				2141
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2142	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2143	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2144	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2145
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2146	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2147	unsigned U = fieldFromInstruction(Val, 8, 1);
				2148	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2149
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2150	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2151	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2152
				2153	if (U)
				2154	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2155	else
				2156	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2157
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2158	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2159	}
				2160
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2161	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2162	uint64_t Address, const void *Decoder) {
				2163	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2164	}
				2165
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2166	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2167	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2168	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2169	DecodeStatus Status = MCDisassembler::Success;
				2170
				2171	// Note the J1 and J2 values are from the encoded instruction. So here
				2172	// change them to I1 and I2 values via as documented:
				2173	// I1 = NOT(J1 EOR S);
				2174	// I2 = NOT(J2 EOR S);
				2175	// and build the imm32 with one trailing zero as documented:
				2176	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2177	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2178	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2179	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2180	unsigned I1 = !(J1 ^ S);
				2181	unsigned I2 = !(J2 ^ S);
				2182	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2183	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2184	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2185	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2186	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2187	true, 4, Inst, Decoder))
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2188	Inst.addOperand(MCOperand::CreateImm(imm32));
				2189
				2190	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2191	}
				2192
				2193	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2194	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2195	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2196	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2197
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2198	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2199	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2200
				2201	if (pred == 0xF) {
				2202	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2203	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2204	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2205	true, 4, Inst, Decoder))
Benjamin Kramer	406dc17	2011-08-09 22:02:50 +0000	[diff] [blame]	2206	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2207	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2208	}
				2209
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2210	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2211	true, 4, Inst, Decoder))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2212	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2213	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2214	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2215
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2216	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2217	}
				2218
				2219
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2220	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2221	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2222	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2223
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2224	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2225	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2226
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2227	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2228	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2229	if (!align)
				2230	Inst.addOperand(MCOperand::CreateImm(0));
				2231	else
				2232	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2233
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2234	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2235	}
				2236
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2237	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2238	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2239	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2240
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2241	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2242	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2243	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2244	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2245	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2246	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2247
				2248	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2249	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2250	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2251	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2252	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2253	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2254	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2255	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2256	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2257	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2258	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2259	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2260	return MCDisassembler::Fail;
				2261	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2262	case ARM::VLD2b16:
				2263	case ARM::VLD2b32:
				2264	case ARM::VLD2b8:
				2265	case ARM::VLD2b16wb_fixed:
				2266	case ARM::VLD2b16wb_register:
				2267	case ARM::VLD2b32wb_fixed:
				2268	case ARM::VLD2b32wb_register:
				2269	case ARM::VLD2b8wb_fixed:
				2270	case ARM::VLD2b8wb_register:
				2271	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2272	return MCDisassembler::Fail;
				2273	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2274	default:
				2275	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2276	return MCDisassembler::Fail;
				2277	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2278
				2279	// Second output register
				2280	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2281	case ARM::VLD3d8:
				2282	case ARM::VLD3d16:
				2283	case ARM::VLD3d32:
				2284	case ARM::VLD3d8_UPD:
				2285	case ARM::VLD3d16_UPD:
				2286	case ARM::VLD3d32_UPD:
				2287	case ARM::VLD4d8:
				2288	case ARM::VLD4d16:
				2289	case ARM::VLD4d32:
				2290	case ARM::VLD4d8_UPD:
				2291	case ARM::VLD4d16_UPD:
				2292	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2293	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2294	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2295	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2296	case ARM::VLD3q8:
				2297	case ARM::VLD3q16:
				2298	case ARM::VLD3q32:
				2299	case ARM::VLD3q8_UPD:
				2300	case ARM::VLD3q16_UPD:
				2301	case ARM::VLD3q32_UPD:
				2302	case ARM::VLD4q8:
				2303	case ARM::VLD4q16:
				2304	case ARM::VLD4q32:
				2305	case ARM::VLD4q8_UPD:
				2306	case ARM::VLD4q16_UPD:
				2307	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2308	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2309	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2310	default:
				2311	break;
				2312	}
				2313
				2314	// Third output register
				2315	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2316	case ARM::VLD3d8:
				2317	case ARM::VLD3d16:
				2318	case ARM::VLD3d32:
				2319	case ARM::VLD3d8_UPD:
				2320	case ARM::VLD3d16_UPD:
				2321	case ARM::VLD3d32_UPD:
				2322	case ARM::VLD4d8:
				2323	case ARM::VLD4d16:
				2324	case ARM::VLD4d32:
				2325	case ARM::VLD4d8_UPD:
				2326	case ARM::VLD4d16_UPD:
				2327	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2328	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2329	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2330	break;
				2331	case ARM::VLD3q8:
				2332	case ARM::VLD3q16:
				2333	case ARM::VLD3q32:
				2334	case ARM::VLD3q8_UPD:
				2335	case ARM::VLD3q16_UPD:
				2336	case ARM::VLD3q32_UPD:
				2337	case ARM::VLD4q8:
				2338	case ARM::VLD4q16:
				2339	case ARM::VLD4q32:
				2340	case ARM::VLD4q8_UPD:
				2341	case ARM::VLD4q16_UPD:
				2342	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2343	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2344	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2345	break;
				2346	default:
				2347	break;
				2348	}
				2349
				2350	// Fourth output register
				2351	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2352	case ARM::VLD4d8:
				2353	case ARM::VLD4d16:
				2354	case ARM::VLD4d32:
				2355	case ARM::VLD4d8_UPD:
				2356	case ARM::VLD4d16_UPD:
				2357	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2358	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2359	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2360	break;
				2361	case ARM::VLD4q8:
				2362	case ARM::VLD4q16:
				2363	case ARM::VLD4q32:
				2364	case ARM::VLD4q8_UPD:
				2365	case ARM::VLD4q16_UPD:
				2366	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2367	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2368	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2369	break;
				2370	default:
				2371	break;
				2372	}
				2373
				2374	// Writeback operand
				2375	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2376	case ARM::VLD1d8wb_fixed:
				2377	case ARM::VLD1d16wb_fixed:
				2378	case ARM::VLD1d32wb_fixed:
				2379	case ARM::VLD1d64wb_fixed:
				2380	case ARM::VLD1d8wb_register:
				2381	case ARM::VLD1d16wb_register:
				2382	case ARM::VLD1d32wb_register:
				2383	case ARM::VLD1d64wb_register:
				2384	case ARM::VLD1q8wb_fixed:
				2385	case ARM::VLD1q16wb_fixed:
				2386	case ARM::VLD1q32wb_fixed:
				2387	case ARM::VLD1q64wb_fixed:
				2388	case ARM::VLD1q8wb_register:
				2389	case ARM::VLD1q16wb_register:
				2390	case ARM::VLD1q32wb_register:
				2391	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2392	case ARM::VLD1d8Twb_fixed:
				2393	case ARM::VLD1d8Twb_register:
				2394	case ARM::VLD1d16Twb_fixed:
				2395	case ARM::VLD1d16Twb_register:
				2396	case ARM::VLD1d32Twb_fixed:
				2397	case ARM::VLD1d32Twb_register:
				2398	case ARM::VLD1d64Twb_fixed:
				2399	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2400	case ARM::VLD1d8Qwb_fixed:
				2401	case ARM::VLD1d8Qwb_register:
				2402	case ARM::VLD1d16Qwb_fixed:
				2403	case ARM::VLD1d16Qwb_register:
				2404	case ARM::VLD1d32Qwb_fixed:
				2405	case ARM::VLD1d32Qwb_register:
				2406	case ARM::VLD1d64Qwb_fixed:
				2407	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2408	case ARM::VLD2d8wb_fixed:
				2409	case ARM::VLD2d16wb_fixed:
				2410	case ARM::VLD2d32wb_fixed:
				2411	case ARM::VLD2q8wb_fixed:
				2412	case ARM::VLD2q16wb_fixed:
				2413	case ARM::VLD2q32wb_fixed:
				2414	case ARM::VLD2d8wb_register:
				2415	case ARM::VLD2d16wb_register:
				2416	case ARM::VLD2d32wb_register:
				2417	case ARM::VLD2q8wb_register:
				2418	case ARM::VLD2q16wb_register:
				2419	case ARM::VLD2q32wb_register:
				2420	case ARM::VLD2b8wb_fixed:
				2421	case ARM::VLD2b16wb_fixed:
				2422	case ARM::VLD2b32wb_fixed:
				2423	case ARM::VLD2b8wb_register:
				2424	case ARM::VLD2b16wb_register:
				2425	case ARM::VLD2b32wb_register:
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2426	Inst.addOperand(MCOperand::CreateImm(0));
				2427	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2428	case ARM::VLD3d8_UPD:
				2429	case ARM::VLD3d16_UPD:
				2430	case ARM::VLD3d32_UPD:
				2431	case ARM::VLD3q8_UPD:
				2432	case ARM::VLD3q16_UPD:
				2433	case ARM::VLD3q32_UPD:
				2434	case ARM::VLD4d8_UPD:
				2435	case ARM::VLD4d16_UPD:
				2436	case ARM::VLD4d32_UPD:
				2437	case ARM::VLD4q8_UPD:
				2438	case ARM::VLD4q16_UPD:
				2439	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2440	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2441	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2442	break;
				2443	default:
				2444	break;
				2445	}
				2446
				2447	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2448	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2449	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2450
				2451	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2452	switch (Inst.getOpcode()) {
				2453	default:
				2454	// The below have been updated to have explicit am6offset split
				2455	// between fixed and register offset. For those instructions not
				2456	// yet updated, we need to add an additional reg0 operand for the
				2457	// fixed variant.
				2458	//
				2459	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2460	if (Rm == 0xd) {
				2461	Inst.addOperand(MCOperand::CreateReg(0));
				2462	break;
				2463	}
				2464	// Fall through to handle the register offset variant.
				2465	case ARM::VLD1d8wb_fixed:
				2466	case ARM::VLD1d16wb_fixed:
				2467	case ARM::VLD1d32wb_fixed:
				2468	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2469	case ARM::VLD1d8Twb_fixed:
				2470	case ARM::VLD1d16Twb_fixed:
				2471	case ARM::VLD1d32Twb_fixed:
				2472	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2473	case ARM::VLD1d8Qwb_fixed:
				2474	case ARM::VLD1d16Qwb_fixed:
				2475	case ARM::VLD1d32Qwb_fixed:
				2476	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2477	case ARM::VLD1d8wb_register:
				2478	case ARM::VLD1d16wb_register:
				2479	case ARM::VLD1d32wb_register:
				2480	case ARM::VLD1d64wb_register:
				2481	case ARM::VLD1q8wb_fixed:
				2482	case ARM::VLD1q16wb_fixed:
				2483	case ARM::VLD1q32wb_fixed:
				2484	case ARM::VLD1q64wb_fixed:
				2485	case ARM::VLD1q8wb_register:
				2486	case ARM::VLD1q16wb_register:
				2487	case ARM::VLD1q32wb_register:
				2488	case ARM::VLD1q64wb_register:
				2489	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2490	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2491	// increment and we need to add the register operand to the instruction.
				2492	if (Rm != 0xD && Rm != 0xF &&
				2493	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2494	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2495	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2496	case ARM::VLD2d8wb_fixed:
				2497	case ARM::VLD2d16wb_fixed:
				2498	case ARM::VLD2d32wb_fixed:
				2499	case ARM::VLD2b8wb_fixed:
				2500	case ARM::VLD2b16wb_fixed:
				2501	case ARM::VLD2b32wb_fixed:
				2502	case ARM::VLD2q8wb_fixed:
				2503	case ARM::VLD2q16wb_fixed:
				2504	case ARM::VLD2q32wb_fixed:
				2505	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2506	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2507
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2508	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2509	}
				2510
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2511	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2512	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2513	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2514	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2515	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2516	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2517	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2518
				2519	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2520	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2521	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2522	}
				2523
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2524	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2525	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2526	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2527	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2528
				2529	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2530	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2531	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2532	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2533
				2534	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2535	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2536	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2537	}
				2538
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2539	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2540	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2541	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2542	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2543
				2544	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2545	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2546
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2547	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2548	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2549	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2550	}
				2551
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2552	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2553	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2554	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2555	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2556
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2557	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2558	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2559	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2560	}
				2561
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2562	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2563	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2564	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2565
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2566	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2567	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2568	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2569	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2570	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2571	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2572
				2573	// Writeback Operand
				2574	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2575	case ARM::VST1d8wb_fixed:
				2576	case ARM::VST1d16wb_fixed:
				2577	case ARM::VST1d32wb_fixed:
				2578	case ARM::VST1d64wb_fixed:
				2579	case ARM::VST1d8wb_register:
				2580	case ARM::VST1d16wb_register:
				2581	case ARM::VST1d32wb_register:
				2582	case ARM::VST1d64wb_register:
				2583	case ARM::VST1q8wb_fixed:
				2584	case ARM::VST1q16wb_fixed:
				2585	case ARM::VST1q32wb_fixed:
				2586	case ARM::VST1q64wb_fixed:
				2587	case ARM::VST1q8wb_register:
				2588	case ARM::VST1q16wb_register:
				2589	case ARM::VST1q32wb_register:
				2590	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2591	case ARM::VST1d8Twb_fixed:
				2592	case ARM::VST1d16Twb_fixed:
				2593	case ARM::VST1d32Twb_fixed:
				2594	case ARM::VST1d64Twb_fixed:
				2595	case ARM::VST1d8Twb_register:
				2596	case ARM::VST1d16Twb_register:
				2597	case ARM::VST1d32Twb_register:
				2598	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2599	case ARM::VST1d8Qwb_fixed:
				2600	case ARM::VST1d16Qwb_fixed:
				2601	case ARM::VST1d32Qwb_fixed:
				2602	case ARM::VST1d64Qwb_fixed:
				2603	case ARM::VST1d8Qwb_register:
				2604	case ARM::VST1d16Qwb_register:
				2605	case ARM::VST1d32Qwb_register:
				2606	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2607	case ARM::VST2d8wb_fixed:
				2608	case ARM::VST2d16wb_fixed:
				2609	case ARM::VST2d32wb_fixed:
				2610	case ARM::VST2d8wb_register:
				2611	case ARM::VST2d16wb_register:
				2612	case ARM::VST2d32wb_register:
				2613	case ARM::VST2q8wb_fixed:
				2614	case ARM::VST2q16wb_fixed:
				2615	case ARM::VST2q32wb_fixed:
				2616	case ARM::VST2q8wb_register:
				2617	case ARM::VST2q16wb_register:
				2618	case ARM::VST2q32wb_register:
				2619	case ARM::VST2b8wb_fixed:
				2620	case ARM::VST2b16wb_fixed:
				2621	case ARM::VST2b32wb_fixed:
				2622	case ARM::VST2b8wb_register:
				2623	case ARM::VST2b16wb_register:
				2624	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2625	if (Rm == 0xF)
				2626	return MCDisassembler::Fail;
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2627	Inst.addOperand(MCOperand::CreateImm(0));
				2628	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2629	case ARM::VST3d8_UPD:
				2630	case ARM::VST3d16_UPD:
				2631	case ARM::VST3d32_UPD:
				2632	case ARM::VST3q8_UPD:
				2633	case ARM::VST3q16_UPD:
				2634	case ARM::VST3q32_UPD:
				2635	case ARM::VST4d8_UPD:
				2636	case ARM::VST4d16_UPD:
				2637	case ARM::VST4d32_UPD:
				2638	case ARM::VST4q8_UPD:
				2639	case ARM::VST4q16_UPD:
				2640	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2641	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2642	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2643	break;
				2644	default:
				2645	break;
				2646	}
				2647
				2648	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2649	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2650	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2651
				2652	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2653	switch (Inst.getOpcode()) {
				2654	default:
				2655	if (Rm == 0xD)
				2656	Inst.addOperand(MCOperand::CreateReg(0));
				2657	else if (Rm != 0xF) {
				2658	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2659	return MCDisassembler::Fail;
				2660	}
				2661	break;
				2662	case ARM::VST1d8wb_fixed:
				2663	case ARM::VST1d16wb_fixed:
				2664	case ARM::VST1d32wb_fixed:
				2665	case ARM::VST1d64wb_fixed:
				2666	case ARM::VST1q8wb_fixed:
				2667	case ARM::VST1q16wb_fixed:
				2668	case ARM::VST1q32wb_fixed:
				2669	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2670	case ARM::VST1d8Twb_fixed:
				2671	case ARM::VST1d16Twb_fixed:
				2672	case ARM::VST1d32Twb_fixed:
				2673	case ARM::VST1d64Twb_fixed:
				2674	case ARM::VST1d8Qwb_fixed:
				2675	case ARM::VST1d16Qwb_fixed:
				2676	case ARM::VST1d32Qwb_fixed:
				2677	case ARM::VST1d64Qwb_fixed:
				2678	case ARM::VST2d8wb_fixed:
				2679	case ARM::VST2d16wb_fixed:
				2680	case ARM::VST2d32wb_fixed:
				2681	case ARM::VST2q8wb_fixed:
				2682	case ARM::VST2q16wb_fixed:
				2683	case ARM::VST2q32wb_fixed:
				2684	case ARM::VST2b8wb_fixed:
				2685	case ARM::VST2b16wb_fixed:
				2686	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2687	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2688	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2689
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2690
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2691	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2692	switch (Inst.getOpcode()) {
				2693	case ARM::VST1q16:
				2694	case ARM::VST1q32:
				2695	case ARM::VST1q64:
				2696	case ARM::VST1q8:
				2697	case ARM::VST1q16wb_fixed:
				2698	case ARM::VST1q16wb_register:
				2699	case ARM::VST1q32wb_fixed:
				2700	case ARM::VST1q32wb_register:
				2701	case ARM::VST1q64wb_fixed:
				2702	case ARM::VST1q64wb_register:
				2703	case ARM::VST1q8wb_fixed:
				2704	case ARM::VST1q8wb_register:
				2705	case ARM::VST2d16:
				2706	case ARM::VST2d32:
				2707	case ARM::VST2d8:
				2708	case ARM::VST2d16wb_fixed:
				2709	case ARM::VST2d16wb_register:
				2710	case ARM::VST2d32wb_fixed:
				2711	case ARM::VST2d32wb_register:
				2712	case ARM::VST2d8wb_fixed:
				2713	case ARM::VST2d8wb_register:
				2714	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2715	return MCDisassembler::Fail;
				2716	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2717	case ARM::VST2b16:
				2718	case ARM::VST2b32:
				2719	case ARM::VST2b8:
				2720	case ARM::VST2b16wb_fixed:
				2721	case ARM::VST2b16wb_register:
				2722	case ARM::VST2b32wb_fixed:
				2723	case ARM::VST2b32wb_register:
				2724	case ARM::VST2b8wb_fixed:
				2725	case ARM::VST2b8wb_register:
				2726	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2727	return MCDisassembler::Fail;
				2728	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2729	default:
				2730	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2731	return MCDisassembler::Fail;
				2732	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2733
				2734	// Second input register
				2735	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2736	case ARM::VST3d8:
				2737	case ARM::VST3d16:
				2738	case ARM::VST3d32:
				2739	case ARM::VST3d8_UPD:
				2740	case ARM::VST3d16_UPD:
				2741	case ARM::VST3d32_UPD:
				2742	case ARM::VST4d8:
				2743	case ARM::VST4d16:
				2744	case ARM::VST4d32:
				2745	case ARM::VST4d8_UPD:
				2746	case ARM::VST4d16_UPD:
				2747	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2748	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2749	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2750	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2751	case ARM::VST3q8:
				2752	case ARM::VST3q16:
				2753	case ARM::VST3q32:
				2754	case ARM::VST3q8_UPD:
				2755	case ARM::VST3q16_UPD:
				2756	case ARM::VST3q32_UPD:
				2757	case ARM::VST4q8:
				2758	case ARM::VST4q16:
				2759	case ARM::VST4q32:
				2760	case ARM::VST4q8_UPD:
				2761	case ARM::VST4q16_UPD:
				2762	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2763	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2764	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2765	break;
				2766	default:
				2767	break;
				2768	}
				2769
				2770	// Third input register
				2771	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2772	case ARM::VST3d8:
				2773	case ARM::VST3d16:
				2774	case ARM::VST3d32:
				2775	case ARM::VST3d8_UPD:
				2776	case ARM::VST3d16_UPD:
				2777	case ARM::VST3d32_UPD:
				2778	case ARM::VST4d8:
				2779	case ARM::VST4d16:
				2780	case ARM::VST4d32:
				2781	case ARM::VST4d8_UPD:
				2782	case ARM::VST4d16_UPD:
				2783	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2784	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2785	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2786	break;
				2787	case ARM::VST3q8:
				2788	case ARM::VST3q16:
				2789	case ARM::VST3q32:
				2790	case ARM::VST3q8_UPD:
				2791	case ARM::VST3q16_UPD:
				2792	case ARM::VST3q32_UPD:
				2793	case ARM::VST4q8:
				2794	case ARM::VST4q16:
				2795	case ARM::VST4q32:
				2796	case ARM::VST4q8_UPD:
				2797	case ARM::VST4q16_UPD:
				2798	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2799	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2800	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2801	break;
				2802	default:
				2803	break;
				2804	}
				2805
				2806	// Fourth input register
				2807	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2808	case ARM::VST4d8:
				2809	case ARM::VST4d16:
				2810	case ARM::VST4d32:
				2811	case ARM::VST4d8_UPD:
				2812	case ARM::VST4d16_UPD:
				2813	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2814	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2815	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2816	break;
				2817	case ARM::VST4q8:
				2818	case ARM::VST4q16:
				2819	case ARM::VST4q32:
				2820	case ARM::VST4q8_UPD:
				2821	case ARM::VST4q16_UPD:
				2822	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2823	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2824	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2825	break;
				2826	default:
				2827	break;
				2828	}
				2829
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2830	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2831	}
				2832
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2833	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2834	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2835	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2836
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2837	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2838	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2839	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2840	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2841	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2842	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2843
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2844	if (size == 0 && align == 1)
				2845	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2846	align *= (1 << size);
				2847
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2848	switch (Inst.getOpcode()) {
				2849	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2850	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2851	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2852	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2853	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2854	return MCDisassembler::Fail;
				2855	break;
				2856	default:
				2857	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2858	return MCDisassembler::Fail;
				2859	break;
				2860	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2861	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2862	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2863	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2864	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2865
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2866	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2867	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2868	Inst.addOperand(MCOperand::CreateImm(align));
				2869
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2870	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2871	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2872	// increment and we need to add the register operand to the instruction.
				2873	if (Rm != 0xD && Rm != 0xF &&
				2874	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2875	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2876
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2877	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2878	}
				2879
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2880	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2881	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2882	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2883
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2884	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2885	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2886	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2887	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2888	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2889	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2890	align = 2size;
				2891
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2892	switch (Inst.getOpcode()) {
				2893	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2894	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2895	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2896	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2897	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2898	return MCDisassembler::Fail;
				2899	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2900	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2901	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2902	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2903	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2904	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2905	return MCDisassembler::Fail;
				2906	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2907	default:
				2908	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2909	return MCDisassembler::Fail;
				2910	break;
				2911	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2912
				2913	if (Rm != 0xF)
				2914	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2915
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2916	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2917	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2918	Inst.addOperand(MCOperand::CreateImm(align));
				2919
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2920	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2921	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2922	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2923	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2924
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2925	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2926	}
				2927
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2928	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2929	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2930	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2931
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2932	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2933	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2934	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2935	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2936	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2937
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2938	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2939	return MCDisassembler::Fail;
				2940	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2941	return MCDisassembler::Fail;
				2942	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2943	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2944	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2945	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2946	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2947	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2948
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2949	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2950	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2951	Inst.addOperand(MCOperand::CreateImm(0));
				2952
				2953	if (Rm == 0xD)
				2954	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2955	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2956	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2957	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2958	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2959
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2960	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2961	}
				2962
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2963	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2964	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2965	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2966
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2967	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2968	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2969	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2970	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2971	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2972	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2973	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2974
				2975	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2976	if (align == 0)
				2977	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2978	size = 4;
				2979	align = 16;
				2980	} else {
				2981	if (size == 2) {
				2982	size = 1 << size;
				2983	align *= 8;
				2984	} else {
				2985	size = 1 << size;
				2986	align = 4size;
				2987	}
				2988	}
				2989
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2990	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2991	return MCDisassembler::Fail;
				2992	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2993	return MCDisassembler::Fail;
				2994	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2995	return MCDisassembler::Fail;
				2996	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2997	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2998	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2999	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3000	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3001	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3002
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3003	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3004	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3005	Inst.addOperand(MCOperand::CreateImm(align));
				3006
				3007	if (Rm == 0xD)
				3008	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3009	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3010	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3011	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3012	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3013
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3014	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3015	}
				3016
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3017	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3018	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3019	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3020	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3021
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3022	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3023	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3024	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3025	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3026	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3027	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3028	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3029	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3030
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3031	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3032	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3033	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3034	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3035	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3036	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3037	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3038
				3039	Inst.addOperand(MCOperand::CreateImm(imm));
				3040
				3041	switch (Inst.getOpcode()) {
				3042	case ARM::VORRiv4i16:
				3043	case ARM::VORRiv2i32:
				3044	case ARM::VBICiv4i16:
				3045	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3046	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3047	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3048	break;
				3049	case ARM::VORRiv8i16:
				3050	case ARM::VORRiv4i32:
				3051	case ARM::VBICiv8i16:
				3052	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3053	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3054	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3055	break;
				3056	default:
				3057	break;
				3058	}
				3059
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3060	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3061	}
				3062
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3063	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3064	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3065	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3066
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3067	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3068	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3069	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3070	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3071	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3072
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3073	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3074	return MCDisassembler::Fail;
				3075	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3076	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3077	Inst.addOperand(MCOperand::CreateImm(8 << size));
				3078
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3079	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3080	}
				3081
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3082	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3083	uint64_t Address, const void *Decoder) {
				3084	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3085	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3086	}
				3087
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3088	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3089	uint64_t Address, const void *Decoder) {
				3090	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3091	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3092	}
				3093
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3094	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3095	uint64_t Address, const void *Decoder) {
				3096	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3097	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3098	}
				3099
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3100	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3101	uint64_t Address, const void *Decoder) {
				3102	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3103	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3104	}
				3105
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3106	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3107	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3108	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3109
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3110	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3111	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3112	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3113	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3114	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3115	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3116	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3117
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3118	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3119	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3120	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3121	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3122	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3123	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3124
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3125	switch (Inst.getOpcode()) {
				3126	case ARM::VTBL2:
				3127	case ARM::VTBX2:
				3128	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3129	return MCDisassembler::Fail;
				3130	break;
				3131	default:
				3132	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3133	return MCDisassembler::Fail;
				3134	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3135
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3136	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3137	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3138
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3139	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3140	}
				3141
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3142	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3143	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3144	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3145
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3146	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3147	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3148
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3149	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3150	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3151
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3152	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3153	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3154	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3155	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3156	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3157	case ARM::tADDrSPi:
				3158	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3159	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3160	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3161
				3162	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3163	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3164	}
				3165
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3166	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3167	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3168	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3169	true, 2, Inst, Decoder))
				3170	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3171	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3172	}
				3173
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3174	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3175	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3176	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3177	true, 4, Inst, Decoder))
				3178	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3179	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3180	}
				3181
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3182	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3183	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3184	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3185	true, 2, Inst, Decoder))
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3186	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3187	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3188	}
				3189
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3190	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3191	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3192	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3193
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3194	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3195	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3196
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3197	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3198	return MCDisassembler::Fail;
				3199	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3200	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3201
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3202	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3203	}
				3204
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3205	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3206	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3207	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3208
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3209	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3210	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3211
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3212	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3213	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3214	Inst.addOperand(MCOperand::CreateImm(imm));
				3215
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3216	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3217	}
				3218
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3219	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3220	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3221	unsigned imm = Val << 2;
				3222
				3223	Inst.addOperand(MCOperand::CreateImm(imm));
				3224	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3225
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3226	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3227	}
				3228
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3229	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3230	uint64_t Address, const void *Decoder) {
				3231	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b498132	2011-08-22 17:56:58 +0000	[diff] [blame]	3232	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3233
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3234	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3235	}
				3236
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3237	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3238	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3239	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3240
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3241	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3242	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3243	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3244
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3245	// Thumb stores cannot use PC as dest register.
				3246	switch (Inst.getOpcode()) {
				3247	case ARM::t2STRHs:
				3248	case ARM::t2STRBs:
				3249	case ARM::t2STRs:
				3250	if (Rn == 15)
				3251	return MCDisassembler::Fail;
				3252	default:
				3253	break;
				3254	}
				3255
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3256	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3257	return MCDisassembler::Fail;
				3258	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3259	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3260	Inst.addOperand(MCOperand::CreateImm(imm));
				3261
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3262	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3263	}
				3264
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3265	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3266	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3267	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3268
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3269	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3270	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3271
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3272	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3273	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3274	case ARM::t2LDRBs:
				3275	Inst.setOpcode(ARM::t2LDRBpci);
				3276	break;
				3277	case ARM::t2LDRHs:
				3278	Inst.setOpcode(ARM::t2LDRHpci);
				3279	break;
				3280	case ARM::t2LDRSHs:
				3281	Inst.setOpcode(ARM::t2LDRSHpci);
				3282	break;
				3283	case ARM::t2LDRSBs:
				3284	Inst.setOpcode(ARM::t2LDRSBpci);
				3285	break;
				3286	case ARM::t2LDRs:
				3287	Inst.setOpcode(ARM::t2LDRpci);
				3288	break;
				3289	case ARM::t2PLDs:
				3290	Inst.setOpcode(ARM::t2PLDpci);
				3291	break;
				3292	case ARM::t2PLIs:
				3293	Inst.setOpcode(ARM::t2PLIpci);
				3294	break;
				3295	default:
				3296	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3297	}
				3298
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3299	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3300	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3301
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3302	if (Rt == 15) {
				3303	switch (Inst.getOpcode()) {
				3304	case ARM::t2LDRSHs:
				3305	return MCDisassembler::Fail;
				3306	case ARM::t2LDRHs:
				3307	// FIXME: this instruction is only available with MP extensions,
				3308	// this should be checked first but we don't have access to the
				3309	// feature bits here.
				3310	Inst.setOpcode(ARM::t2PLDWs);
				3311	break;
				3312	default:
				3313	break;
				3314	}
				3315	}
				3316
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3317	switch (Inst.getOpcode()) {
				3318	case ARM::t2PLDs:
				3319	case ARM::t2PLDWs:
				3320	case ARM::t2PLIs:
				3321	break;
				3322	default:
				3323	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3324	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3325	}
				3326
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3327	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3328	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3329	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3330	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3331	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3332
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3333	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3334	}
				3335
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3336	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3337	uint64_t Address, const void* Decoder) {
				3338	DecodeStatus S = MCDisassembler::Success;
				3339
				3340	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3341	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3342	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3343	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3344	imm \|= (U << 8);
				3345	imm \|= (Rn << 9);
				3346
				3347	if (Rn == 15) {
				3348	switch (Inst.getOpcode()) {
				3349	case ARM::t2LDRi8:
				3350	Inst.setOpcode(ARM::t2LDRpci);
				3351	break;
				3352	case ARM::t2LDRBi8:
				3353	Inst.setOpcode(ARM::t2LDRBpci);
				3354	break;
				3355	case ARM::t2LDRSBi8:
				3356	Inst.setOpcode(ARM::t2LDRSBpci);
				3357	break;
				3358	case ARM::t2LDRHi8:
				3359	Inst.setOpcode(ARM::t2LDRHpci);
				3360	break;
				3361	case ARM::t2LDRSHi8:
				3362	Inst.setOpcode(ARM::t2LDRSHpci);
				3363	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3364	case ARM::t2PLDi8:
				3365	Inst.setOpcode(ARM::t2PLDpci);
				3366	break;
				3367	case ARM::t2PLIi8:
				3368	Inst.setOpcode(ARM::t2PLIpci);
				3369	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3370	default:
				3371	return MCDisassembler::Fail;
				3372	}
				3373	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3374	}
				3375
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3376	if (Rt == 15) {
				3377	switch (Inst.getOpcode()) {
				3378	case ARM::t2LDRSHi8:
				3379	return MCDisassembler::Fail;
				3380	default:
				3381	break;
				3382	}
				3383	}
				3384
				3385	switch (Inst.getOpcode()) {
				3386	case ARM::t2PLDi8:
				3387	case ARM::t2PLIi8:
Mihai Popa	c34bf73	2013-08-06 16:07:46 +0000	[diff] [blame]	3388	case ARM::t2PLDWi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3389	break;
				3390	default:
				3391	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3392	return MCDisassembler::Fail;
				3393	}
				3394
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3395	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3396	return MCDisassembler::Fail;
				3397	return S;
				3398	}
				3399
				3400	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3401	uint64_t Address, const void* Decoder) {
				3402	DecodeStatus S = MCDisassembler::Success;
				3403
				3404	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3405	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3406	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3407	imm \|= (Rn << 13);
				3408
				3409	if (Rn == 15) {
				3410	switch (Inst.getOpcode()) {
				3411	case ARM::t2LDRi12:
				3412	Inst.setOpcode(ARM::t2LDRpci);
				3413	break;
				3414	case ARM::t2LDRHi12:
				3415	Inst.setOpcode(ARM::t2LDRHpci);
				3416	break;
				3417	case ARM::t2LDRSHi12:
				3418	Inst.setOpcode(ARM::t2LDRSHpci);
				3419	break;
				3420	case ARM::t2LDRBi12:
				3421	Inst.setOpcode(ARM::t2LDRBpci);
				3422	break;
				3423	case ARM::t2LDRSBi12:
				3424	Inst.setOpcode(ARM::t2LDRSBpci);
				3425	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3426	case ARM::t2PLDi12:
				3427	Inst.setOpcode(ARM::t2PLDpci);
				3428	break;
				3429	case ARM::t2PLIi12:
				3430	Inst.setOpcode(ARM::t2PLIpci);
				3431	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3432	default:
				3433	return MCDisassembler::Fail;
				3434	}
				3435	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3436	}
				3437
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3438	if (Rt == 15) {
				3439	switch (Inst.getOpcode()) {
				3440	case ARM::t2LDRSHi12:
				3441	return MCDisassembler::Fail;
				3442	case ARM::t2LDRHi12:
				3443	Inst.setOpcode(ARM::t2PLDi12);
				3444	break;
				3445	default:
				3446	break;
				3447	}
				3448	}
				3449
				3450	switch (Inst.getOpcode()) {
				3451	case ARM::t2PLDi12:
Mihai Popa	c34bf73	2013-08-06 16:07:46 +0000	[diff] [blame]	3452	case ARM::t2PLDWi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3453	case ARM::t2PLIi12:
				3454	break;
				3455	default:
				3456	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3457	return MCDisassembler::Fail;
				3458	}
				3459
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3460	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3461	return MCDisassembler::Fail;
				3462	return S;
				3463	}
				3464
				3465	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3466	uint64_t Address, const void* Decoder) {
				3467	DecodeStatus S = MCDisassembler::Success;
				3468
				3469	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3470	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3471	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3472	imm \|= (Rn << 9);
				3473
				3474	if (Rn == 15) {
				3475	switch (Inst.getOpcode()) {
				3476	case ARM::t2LDRT:
				3477	Inst.setOpcode(ARM::t2LDRpci);
				3478	break;
				3479	case ARM::t2LDRBT:
				3480	Inst.setOpcode(ARM::t2LDRBpci);
				3481	break;
				3482	case ARM::t2LDRHT:
				3483	Inst.setOpcode(ARM::t2LDRHpci);
				3484	break;
				3485	case ARM::t2LDRSBT:
				3486	Inst.setOpcode(ARM::t2LDRSBpci);
				3487	break;
				3488	case ARM::t2LDRSHT:
				3489	Inst.setOpcode(ARM::t2LDRSHpci);
				3490	break;
				3491	default:
				3492	return MCDisassembler::Fail;
				3493	}
				3494	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3495	}
				3496
				3497	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3498	return MCDisassembler::Fail;
				3499	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3500	return MCDisassembler::Fail;
				3501	return S;
				3502	}
				3503
				3504	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3505	uint64_t Address, const void* Decoder) {
				3506	DecodeStatus S = MCDisassembler::Success;
				3507
				3508	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3509	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3510	int imm = fieldFromInstruction(Insn, 0, 12);
				3511
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3512	if (Rt == 15) {
				3513	switch (Inst.getOpcode()) {
				3514	case ARM::t2LDRBpci:
				3515	case ARM::t2LDRHpci:
				3516	Inst.setOpcode(ARM::t2PLDpci);
				3517	break;
				3518	case ARM::t2LDRSBpci:
				3519	Inst.setOpcode(ARM::t2PLIpci);
				3520	break;
				3521	case ARM::t2LDRSHpci:
				3522	return MCDisassembler::Fail;
				3523	default:
				3524	break;
				3525	}
				3526	}
				3527
				3528	switch(Inst.getOpcode()) {
				3529	case ARM::t2PLDpci:
				3530	case ARM::t2PLIpci:
				3531	break;
				3532	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3533	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3534	return MCDisassembler::Fail;
				3535	}
				3536
				3537	if (!U) {
				3538	// Special case for #-0.
				3539	if (imm == 0)
				3540	imm = INT32_MIN;
				3541	else
				3542	imm = -imm;
				3543	}
				3544	Inst.addOperand(MCOperand::CreateImm(imm));
				3545
				3546	return S;
				3547	}
				3548
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3549	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3550	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3551	if (Val == 0)
				3552	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3553	else {
				3554	int imm = Val & 0xFF;
				3555
				3556	if (!(Val & 0x100)) imm *= -1;
Richard Smith	228e6d4	2012-08-24 23:29:28 +0000	[diff] [blame]	3557	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3558	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3559
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3560	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3561	}
				3562
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3563	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3564	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3565	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3566
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3567	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3568	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3569
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3570	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3571	return MCDisassembler::Fail;
				3572	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3573	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3574
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3575	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3576	}
				3577
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3578	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3579	uint64_t Address, const void *Decoder) {
				3580	DecodeStatus S = MCDisassembler::Success;
				3581
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3582	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3583	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3584
				3585	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3586	return MCDisassembler::Fail;
				3587
				3588	Inst.addOperand(MCOperand::CreateImm(imm));
				3589
				3590	return S;
				3591	}
				3592
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3593	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3594	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3595	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3596	if (Val == 0)
				3597	imm = INT32_MIN;
				3598	else if (!(Val & 0x100))
				3599	imm *= -1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3600	Inst.addOperand(MCOperand::CreateImm(imm));
				3601
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3602	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3603	}
				3604
				3605
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3606	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3607	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3608	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3609
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3610	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3611	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3612
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3613	// Thumb stores cannot use PC as dest register.
				3614	switch (Inst.getOpcode()) {
				3615	case ARM::t2STRT:
				3616	case ARM::t2STRBT:
				3617	case ARM::t2STRHT:
				3618	case ARM::t2STRi8:
				3619	case ARM::t2STRHi8:
				3620	case ARM::t2STRBi8:
				3621	if (Rn == 15)
				3622	return MCDisassembler::Fail;
				3623	break;
				3624	default:
				3625	break;
				3626	}
				3627
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3628	// Some instructions always use an additive offset.
				3629	switch (Inst.getOpcode()) {
				3630	case ARM::t2LDRT:
				3631	case ARM::t2LDRBT:
				3632	case ARM::t2LDRHT:
				3633	case ARM::t2LDRSBT:
				3634	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3635	case ARM::t2STRT:
				3636	case ARM::t2STRBT:
				3637	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3638	imm \|= 0x100;
				3639	break;
				3640	default:
				3641	break;
				3642	}
				3643
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3644	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3645	return MCDisassembler::Fail;
				3646	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3647	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3648
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3649	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3650	}
				3651
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3652	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3653	uint64_t Address, const void *Decoder) {
				3654	DecodeStatus S = MCDisassembler::Success;
				3655
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3656	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3657	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3658	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3659	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3660	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3661	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3662
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3663	if (Rn == 15) {
				3664	switch (Inst.getOpcode()) {
				3665	case ARM::t2LDR_PRE:
				3666	case ARM::t2LDR_POST:
				3667	Inst.setOpcode(ARM::t2LDRpci);
				3668	break;
				3669	case ARM::t2LDRB_PRE:
				3670	case ARM::t2LDRB_POST:
				3671	Inst.setOpcode(ARM::t2LDRBpci);
				3672	break;
				3673	case ARM::t2LDRH_PRE:
				3674	case ARM::t2LDRH_POST:
				3675	Inst.setOpcode(ARM::t2LDRHpci);
				3676	break;
				3677	case ARM::t2LDRSB_PRE:
				3678	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3679	if (Rt == 15)
				3680	Inst.setOpcode(ARM::t2PLIpci);
				3681	else
				3682	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3683	break;
				3684	case ARM::t2LDRSH_PRE:
				3685	case ARM::t2LDRSH_POST:
				3686	Inst.setOpcode(ARM::t2LDRSHpci);
				3687	break;
				3688	default:
				3689	return MCDisassembler::Fail;
				3690	}
				3691	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3692	}
				3693
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3694	if (!load) {
				3695	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3696	return MCDisassembler::Fail;
				3697	}
				3698
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3699	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3700	return MCDisassembler::Fail;
				3701
				3702	if (load) {
				3703	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3704	return MCDisassembler::Fail;
				3705	}
				3706
				3707	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3708	return MCDisassembler::Fail;
				3709
				3710	return S;
				3711	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3712
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3713	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3714	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3715	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3716
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3717	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3718	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3719
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3720	// Thumb stores cannot use PC as dest register.
				3721	switch (Inst.getOpcode()) {
				3722	case ARM::t2STRi12:
				3723	case ARM::t2STRBi12:
				3724	case ARM::t2STRHi12:
				3725	if (Rn == 15)
				3726	return MCDisassembler::Fail;
				3727	default:
				3728	break;
				3729	}
				3730
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3731	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3732	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3733	Inst.addOperand(MCOperand::CreateImm(imm));
				3734
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3735	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3736	}
				3737
				3738
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3739	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3740	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3741	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3742
				3743	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3744	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3745	Inst.addOperand(MCOperand::CreateImm(imm));
				3746
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3747	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3748	}
				3749
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3750	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3751	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3752	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3753
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3754	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3755	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3756	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3757
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3758	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3759	return MCDisassembler::Fail;
Jim Grosbach	9d8f6f3	2012-04-27 23:51:33 +0000	[diff] [blame]	3760	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3761	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3762	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3763	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3764	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3765
				3766	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3767	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3768	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3769	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3770	}
				3771
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3772	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3773	}
				3774
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3775	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3776	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3777	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3778	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3779
				3780	Inst.addOperand(MCOperand::CreateImm(imod));
				3781	Inst.addOperand(MCOperand::CreateImm(flags));
				3782
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3783	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3784	}
				3785
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3786	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3787	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3788	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3789	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3790	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3791
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3792	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3793	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3794	Inst.addOperand(MCOperand::CreateImm(add));
				3795
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3796	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3797	}
				3798
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3799	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3800	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3801	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3802	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3803	// the encoded instruction. So here change to I1 and I2 values via:
				3804	// I1 = NOT(J1 EOR S);
				3805	// I2 = NOT(J2 EOR S);
				3806	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3807	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3808	unsigned S = (Val >> 23) & 1;
				3809	unsigned J1 = (Val >> 22) & 1;
				3810	unsigned J2 = (Val >> 21) & 1;
				3811	unsigned I1 = !(J1 ^ S);
				3812	unsigned I2 = !(J2 ^ S);
				3813	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3814	int imm32 = SignExtend32<25>(tmp << 1);
				3815
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3816	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3817	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3818	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3819	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3820	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3821	}
				3822
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3823	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3824	uint64_t Address, const void *Decoder) {
				3825	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3826	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3827
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	3828	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3829	.getFeatureBits();
				3830	if ((featureBits & ARM::HasV8Ops) && !(Val == 14 \|\| Val == 15))
				3831	return MCDisassembler::Fail;
				3832
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3833	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3834	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3835	}
				3836
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3837	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3838	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3839	uint64_t Address, const void *Decoder) {
				3840	DecodeStatus S = MCDisassembler::Success;
				3841
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3842	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3843	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3844
				3845	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3846	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3847	return MCDisassembler::Fail;
				3848	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3849	return MCDisassembler::Fail;
				3850	return S;
				3851	}
				3852
				3853	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3854	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3855	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3856	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3857
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3858	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3859	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3860	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3861	switch (opc) {
				3862	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3863	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3864	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3865	Inst.setOpcode(ARM::t2DSB);
				3866	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3867	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3868	Inst.setOpcode(ARM::t2DMB);
				3869	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3870	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3871	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3872	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3873	}
				3874
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3875	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3876	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3877	}
				3878
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3879	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3880	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3881	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3882	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3883	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3884
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3885	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3886	return MCDisassembler::Fail;
				3887	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3888	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3889
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3890	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3891	}
				3892
				3893	// Decode a shifted immediate operand. These basically consist
				3894	// of an 8-bit value, and a 4-bit directive that specifies either
				3895	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3896	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3897	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3898	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3899	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3900	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3901	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3902	switch (byte) {
				3903	case 0:
				3904	Inst.addOperand(MCOperand::CreateImm(imm));
				3905	break;
				3906	case 1:
				3907	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3908	break;
				3909	case 2:
				3910	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3911	break;
				3912	case 3:
				3913	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3914	(imm << 8) \| imm));
				3915	break;
				3916	}
				3917	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3918	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3919	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3920	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3921	Inst.addOperand(MCOperand::CreateImm(imm));
				3922	}
				3923
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3924	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3925	}
				3926
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3927	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3928	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3929	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3930	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3931	true, 2, Inst, Decoder))
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3932	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3933	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3934	}
				3935
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3936	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3937	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3938	// Val is passed in as S:J1:J2:imm10:imm11
				3939	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3940	// the encoded instruction. So here change to I1 and I2 values via:
				3941	// I1 = NOT(J1 EOR S);
				3942	// I2 = NOT(J2 EOR S);
				3943	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3944	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3945	unsigned S = (Val >> 23) & 1;
				3946	unsigned J1 = (Val >> 22) & 1;
				3947	unsigned J2 = (Val >> 21) & 1;
				3948	unsigned I1 = !(J1 ^ S);
				3949	unsigned I2 = !(J2 ^ S);
				3950	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3951	int imm32 = SignExtend32<25>(tmp << 1);
				3952
				3953	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	3954	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3955	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3956	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3957	}
				3958
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3959	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3960	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	3961	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3962	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3963
				3964	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3965	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3966	}
				3967
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	3968	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				3969	uint64_t Address, const void *Decoder) {
				3970	if (Val & ~0xf)
				3971	return MCDisassembler::Fail;
				3972
				3973	Inst.addOperand(MCOperand::CreateImm(Val));
				3974	return MCDisassembler::Success;
				3975	}
				3976
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3977	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3978	uint64_t Address, const void *Decoder) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	3979	DecodeStatus S = MCDisassembler::Success;
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	3980	uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3981	.getFeatureBits();
				3982	if (FeatureBits & ARM::FeatureMClass) {
				3983	unsigned ValLow = Val & 0xff;
				3984
				3985	// Validate the SYSm value first.
				3986	switch (ValLow) {
				3987	case 0: // apsr
				3988	case 1: // iapsr
				3989	case 2: // eapsr
				3990	case 3: // xpsr
				3991	case 5: // ipsr
				3992	case 6: // epsr
				3993	case 7: // iepsr
				3994	case 8: // msp
				3995	case 9: // psp
				3996	case 16: // primask
				3997	case 20: // control
				3998	break;
				3999	case 17: // basepri
				4000	case 18: // basepri_max
				4001	case 19: // faultmask
				4002	if (!(FeatureBits & ARM::HasV7Ops))
				4003	// Values basepri, basepri_max and faultmask are only valid for v7m.
				4004	return MCDisassembler::Fail;
				4005	break;
				4006	default:
				4007	return MCDisassembler::Fail;
				4008	}
				4009
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4010	if (Inst.getOpcode() == ARM::t2MSR_M) {
				4011	unsigned Mask = fieldFromInstruction(Val, 10, 2);
				4012	if (!(FeatureBits & ARM::HasV7Ops)) {
				4013	// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
				4014	// unpredictable.
				4015	if (Mask != 2)
				4016	S = MCDisassembler::SoftFail;
				4017	}
				4018	else {
				4019	// The ARMv7-M architecture stores an additional 2-bit mask value in
				4020	// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
				4021	// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
				4022	// the NZCVQ bits should be moved by the instruction. Bit mask{0}
				4023	// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
				4024	// only if the processor includes the DSP extension.
				4025	if (Mask == 0 \|\| (Mask != 2 && ValLow > 3) \|\|
				4026	(!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
				4027	S = MCDisassembler::SoftFail;
				4028	}
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4029	}
				4030	} else {
				4031	// A/R class
				4032	if (Val == 0)
				4033	return MCDisassembler::Fail;
				4034	}
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4035	Inst.addOperand(MCOperand::CreateImm(Val));
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4036	return S;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4037	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4038
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4039	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
				4040	uint64_t Address, const void *Decoder) {
				4041
				4042	unsigned R = fieldFromInstruction(Val, 5, 1);
				4043	unsigned SysM = fieldFromInstruction(Val, 0, 5);
				4044
				4045	// The table of encodings for these banked registers comes from B9.2.3 of the
				4046	// ARM ARM. There are patterns, but nothing regular enough to make this logic
				4047	// neater. So by fiat, these values are UNPREDICTABLE:
				4048	if (!R) {
				4049	if (SysM == 0x7 \|\| SysM == 0xf \|\| SysM == 0x18 \|\| SysM == 0x19 \|\|
				4050	SysM == 0x1a \|\| SysM == 0x1b)
				4051	return MCDisassembler::SoftFail;
				4052	} else {
				4053	if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
				4054	SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
				4055	return MCDisassembler::SoftFail;
				4056	}
				4057
				4058	Inst.addOperand(MCOperand::CreateImm(Val));
				4059	return MCDisassembler::Success;
				4060	}
				4061
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4062	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4063	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4064	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4065
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4066	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4067	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4068	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4069
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4070	if (Rn == 0xF)
				4071	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4072
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4073	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4074	return MCDisassembler::Fail;
				4075	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4076	return MCDisassembler::Fail;
				4077	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4078	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4079
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4080	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4081	}
				4082
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4083	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4084	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4085	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4086
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4087	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4088	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				4089	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4090	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4091
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	4092	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4093	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4094
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4095	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4096	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4097
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4098	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4099	return MCDisassembler::Fail;
				4100	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4101	return MCDisassembler::Fail;
				4102	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4103	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4104
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4105	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4106	}
				4107
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4108	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4109	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4110	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4111
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4112	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4113	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4114	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4115	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4116	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4117	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4118
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4119	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4120
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4121	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4122	return MCDisassembler::Fail;
				4123	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4124	return MCDisassembler::Fail;
				4125	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4126	return MCDisassembler::Fail;
				4127	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4128	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4129
				4130	return S;
				4131	}
				4132
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4133	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4134	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4135	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4136
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4137	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4138	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4139	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4140	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4141	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4142	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4143	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4144
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4145	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4146	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4147
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4148	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4149	return MCDisassembler::Fail;
				4150	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4151	return MCDisassembler::Fail;
				4152	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4153	return MCDisassembler::Fail;
				4154	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4155	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4156
				4157	return S;
				4158	}
				4159
				4160
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4161	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4162	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4163	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4164
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4165	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4166	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4167	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4168	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4169	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4170	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4171
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4172	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4173
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4174	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4175	return MCDisassembler::Fail;
				4176	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4177	return MCDisassembler::Fail;
				4178	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4179	return MCDisassembler::Fail;
				4180	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4181	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4182
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4183	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4184	}
				4185
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4186	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4187	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4188	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4189
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4190	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4191	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4192	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4193	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4194	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4195	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4196
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4197	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4198
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4199	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4200	return MCDisassembler::Fail;
				4201	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4202	return MCDisassembler::Fail;
				4203	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4204	return MCDisassembler::Fail;
				4205	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4206	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4207
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4208	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4209	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4210
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4211	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4212	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4213	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4214
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4215	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4216	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4217	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4218	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4219	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4220
				4221	unsigned align = 0;
				4222	unsigned index = 0;
				4223	switch (size) {
				4224	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4225	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4226	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4227	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4228	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4229	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4230	break;
				4231	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4232	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4233	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4234	index = fieldFromInstruction(Insn, 6, 2);
				4235	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4236	align = 2;
				4237	break;
				4238	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4239	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4240	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4241	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4242
				4243	switch (fieldFromInstruction(Insn, 4, 2)) {
				4244	case 0 :
				4245	align = 0; break;
				4246	case 3:
				4247	align = 4; break;
				4248	default:
				4249	return MCDisassembler::Fail;
				4250	}
				4251	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4252	}
				4253
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4254	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4255	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4256	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4257	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4258	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4259	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4260	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4261	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4262	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4263	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4264	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4265	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4266	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4267	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4268	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4269	}
				4270
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4271	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4272	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4273	Inst.addOperand(MCOperand::CreateImm(index));
				4274
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4275	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4276	}
				4277
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4278	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4279	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4280	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4281
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4282	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4283	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4284	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4285	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4286	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4287
				4288	unsigned align = 0;
				4289	unsigned index = 0;
				4290	switch (size) {
				4291	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4292	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4293	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4294	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4295	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4296	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4297	break;
				4298	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4299	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4300	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4301	index = fieldFromInstruction(Insn, 6, 2);
				4302	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4303	align = 2;
				4304	break;
				4305	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4306	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4307	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4308	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4309
				4310	switch (fieldFromInstruction(Insn, 4, 2)) {
				4311	case 0:
				4312	align = 0; break;
				4313	case 3:
				4314	align = 4; break;
				4315	default:
				4316	return MCDisassembler::Fail;
				4317	}
				4318	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4319	}
				4320
				4321	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4322	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4323	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4324	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4325	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4326	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4327	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4328	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4329	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4330	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4331	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4332	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4333	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4334	}
				4335
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4336	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4337	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4338	Inst.addOperand(MCOperand::CreateImm(index));
				4339
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4340	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4341	}
				4342
				4343
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4344	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4345	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4346	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4347
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4348	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4349	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4350	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4351	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4352	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4353
				4354	unsigned align = 0;
				4355	unsigned index = 0;
				4356	unsigned inc = 1;
				4357	switch (size) {
				4358	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4359	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4360	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4361	index = fieldFromInstruction(Insn, 5, 3);
				4362	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4363	align = 2;
				4364	break;
				4365	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4366	index = fieldFromInstruction(Insn, 6, 2);
				4367	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4368	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4369	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4370	inc = 2;
				4371	break;
				4372	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4373	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4374	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4375	index = fieldFromInstruction(Insn, 7, 1);
				4376	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4377	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4378	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4379	inc = 2;
				4380	break;
				4381	}
				4382
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4383	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4384	return MCDisassembler::Fail;
				4385	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4386	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4387	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4388	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4389	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4390	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4391	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4392	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4393	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4394	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4395	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4396	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4397	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4398	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4399	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4400	}
				4401
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4402	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4403	return MCDisassembler::Fail;
				4404	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4405	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4406	Inst.addOperand(MCOperand::CreateImm(index));
				4407
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4408	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4409	}
				4410
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4411	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4412	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4413	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4414
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4415	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4416	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4417	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4418	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4419	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4420
				4421	unsigned align = 0;
				4422	unsigned index = 0;
				4423	unsigned inc = 1;
				4424	switch (size) {
				4425	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4426	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4427	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4428	index = fieldFromInstruction(Insn, 5, 3);
				4429	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4430	align = 2;
				4431	break;
				4432	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4433	index = fieldFromInstruction(Insn, 6, 2);
				4434	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4435	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4436	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4437	inc = 2;
				4438	break;
				4439	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4440	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4441	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4442	index = fieldFromInstruction(Insn, 7, 1);
				4443	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4444	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4445	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4446	inc = 2;
				4447	break;
				4448	}
				4449
				4450	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4451	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4452	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4453	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4454	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4455	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4456	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4457	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4458	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4459	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4460	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4461	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4462	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4463	}
				4464
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4465	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4466	return MCDisassembler::Fail;
				4467	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4468	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4469	Inst.addOperand(MCOperand::CreateImm(index));
				4470
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4471	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4472	}
				4473
				4474
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4475	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4476	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4477	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4478
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4479	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4480	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4481	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4482	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4483	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4484
				4485	unsigned align = 0;
				4486	unsigned index = 0;
				4487	unsigned inc = 1;
				4488	switch (size) {
				4489	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4490	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4491	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4492	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4493	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4494	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4495	break;
				4496	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4497	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4498	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4499	index = fieldFromInstruction(Insn, 6, 2);
				4500	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4501	inc = 2;
				4502	break;
				4503	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4504	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4505	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4506	index = fieldFromInstruction(Insn, 7, 1);
				4507	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4508	inc = 2;
				4509	break;
				4510	}
				4511
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4512	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4513	return MCDisassembler::Fail;
				4514	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4515	return MCDisassembler::Fail;
				4516	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4517	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4518
				4519	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4520	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4521	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4522	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4523	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4524	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4525	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4526	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4527	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4528	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4529	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4530	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4531	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4532	}
				4533
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4534	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4535	return MCDisassembler::Fail;
				4536	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4537	return MCDisassembler::Fail;
				4538	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4539	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4540	Inst.addOperand(MCOperand::CreateImm(index));
				4541
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4542	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4543	}
				4544
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4545	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4546	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4547	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4548
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4549	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4550	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4551	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4552	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4553	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4554
				4555	unsigned align = 0;
				4556	unsigned index = 0;
				4557	unsigned inc = 1;
				4558	switch (size) {
				4559	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4560	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4561	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4562	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4563	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4564	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4565	break;
				4566	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4567	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4568	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4569	index = fieldFromInstruction(Insn, 6, 2);
				4570	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4571	inc = 2;
				4572	break;
				4573	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4574	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4575	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4576	index = fieldFromInstruction(Insn, 7, 1);
				4577	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4578	inc = 2;
				4579	break;
				4580	}
				4581
				4582	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4583	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4584	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4585	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4586	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4587	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4588	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4589	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4590	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4591	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4592	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4593	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4594	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4595	}
				4596
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4597	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4598	return MCDisassembler::Fail;
				4599	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4600	return MCDisassembler::Fail;
				4601	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4602	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4603	Inst.addOperand(MCOperand::CreateImm(index));
				4604
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4605	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4606	}
				4607
				4608
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4609	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4610	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4611	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4612
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4613	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4614	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4615	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4616	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4617	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4618
				4619	unsigned align = 0;
				4620	unsigned index = 0;
				4621	unsigned inc = 1;
				4622	switch (size) {
				4623	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4624	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4625	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4626	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4627	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4628	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4629	break;
				4630	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4631	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4632	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4633	index = fieldFromInstruction(Insn, 6, 2);
				4634	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4635	inc = 2;
				4636	break;
				4637	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4638	switch (fieldFromInstruction(Insn, 4, 2)) {
				4639	case 0:
				4640	align = 0; break;
				4641	case 3:
				4642	return MCDisassembler::Fail;
				4643	default:
				4644	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4645	}
				4646
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4647	index = fieldFromInstruction(Insn, 7, 1);
				4648	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4649	inc = 2;
				4650	break;
				4651	}
				4652
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4653	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4654	return MCDisassembler::Fail;
				4655	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4656	return MCDisassembler::Fail;
				4657	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4658	return MCDisassembler::Fail;
				4659	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4660	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4661
				4662	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4663	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4664	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4665	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4666	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4667	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4668	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4669	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4670	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4671	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4672	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4673	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4674	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4675	}
				4676
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4677	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4678	return MCDisassembler::Fail;
				4679	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4680	return MCDisassembler::Fail;
				4681	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4682	return MCDisassembler::Fail;
				4683	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4684	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4685	Inst.addOperand(MCOperand::CreateImm(index));
				4686
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4687	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4688	}
				4689
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4690	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4691	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4692	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4693
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4694	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4695	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4696	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4697	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4698	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4699
				4700	unsigned align = 0;
				4701	unsigned index = 0;
				4702	unsigned inc = 1;
				4703	switch (size) {
				4704	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4705	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4706	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4707	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4708	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4709	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4710	break;
				4711	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4712	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4713	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4714	index = fieldFromInstruction(Insn, 6, 2);
				4715	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4716	inc = 2;
				4717	break;
				4718	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4719	switch (fieldFromInstruction(Insn, 4, 2)) {
				4720	case 0:
				4721	align = 0; break;
				4722	case 3:
				4723	return MCDisassembler::Fail;
				4724	default:
				4725	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4726	}
				4727
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4728	index = fieldFromInstruction(Insn, 7, 1);
				4729	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4730	inc = 2;
				4731	break;
				4732	}
				4733
				4734	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4735	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4736	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4737	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4738	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4739	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4740	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4741	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4742	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4743	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4744	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4745	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4746	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4747	}
				4748
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4749	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4750	return MCDisassembler::Fail;
				4751	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4752	return MCDisassembler::Fail;
				4753	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4754	return MCDisassembler::Fail;
				4755	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4756	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4757	Inst.addOperand(MCOperand::CreateImm(index));
				4758
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4759	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4760	}
				4761
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4762	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4763	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4764	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4765	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4766	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4767	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4768	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4769	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4770
				4771	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4772	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4773
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4774	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4775	return MCDisassembler::Fail;
				4776	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4777	return MCDisassembler::Fail;
				4778	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4779	return MCDisassembler::Fail;
				4780	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4781	return MCDisassembler::Fail;
				4782	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4783	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4784
				4785	return S;
				4786	}
				4787
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4788	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4789	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4790	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4791	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4792	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4793	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4794	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4795	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4796
				4797	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4798	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4799
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4800	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4801	return MCDisassembler::Fail;
				4802	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4803	return MCDisassembler::Fail;
				4804	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4805	return MCDisassembler::Fail;
				4806	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4807	return MCDisassembler::Fail;
				4808	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4809	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4810
				4811	return S;
				4812	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4813
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4814	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4815	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4816	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4817	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4818	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4819
				4820	if (pred == 0xF) {
				4821	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4822	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4823	}
				4824
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4825	if (mask == 0x0)
				4826	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4827
				4828	Inst.addOperand(MCOperand::CreateImm(pred));
				4829	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4830	return S;
				4831	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4832
				4833	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4834	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4835	uint64_t Address, const void *Decoder) {
				4836	DecodeStatus S = MCDisassembler::Success;
				4837
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4838	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4839	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4840	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4841	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4842	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4843	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4844	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4845	bool writeback = (W == 1) \| (P == 0);
				4846
				4847	addr \|= (U << 8) \| (Rn << 9);
				4848
				4849	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4850	Check(S, MCDisassembler::SoftFail);
				4851	if (Rt == Rt2)
				4852	Check(S, MCDisassembler::SoftFail);
				4853
				4854	// Rt
				4855	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4856	return MCDisassembler::Fail;
				4857	// Rt2
				4858	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4859	return MCDisassembler::Fail;
				4860	// Writeback operand
				4861	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4862	return MCDisassembler::Fail;
				4863	// addr
				4864	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4865	return MCDisassembler::Fail;
				4866
				4867	return S;
				4868	}
				4869
				4870	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4871	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4872	uint64_t Address, const void *Decoder) {
				4873	DecodeStatus S = MCDisassembler::Success;
				4874
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4875	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4876	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4877	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4878	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4879	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4880	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4881	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4882	bool writeback = (W == 1) \| (P == 0);
				4883
				4884	addr \|= (U << 8) \| (Rn << 9);
				4885
				4886	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4887	Check(S, MCDisassembler::SoftFail);
				4888
				4889	// Writeback operand
				4890	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4891	return MCDisassembler::Fail;
				4892	// Rt
				4893	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4894	return MCDisassembler::Fail;
				4895	// Rt2
				4896	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4897	return MCDisassembler::Fail;
				4898	// addr
				4899	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4900	return MCDisassembler::Fail;
				4901
				4902	return S;
				4903	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4904
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4905	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4906	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4907	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4908	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4909	if (sign1 != sign2) return MCDisassembler::Fail;
				4910
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4911	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4912	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4913	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4914	Val \|= sign1 << 12;
				4915	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4916
				4917	return MCDisassembler::Success;
				4918	}
				4919
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4920	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	4921	uint64_t Address,
				4922	const void *Decoder) {
				4923	DecodeStatus S = MCDisassembler::Success;
				4924
				4925	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4926	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4927	Inst.addOperand(MCOperand::CreateImm(Val));
				4928	return S;
				4929	}
				4930
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4931	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4932	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4933	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4934	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4935	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4936	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4937
				4938	if (pred == 0xF)
				4939	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4940
				4941	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	4942
				4943	if (Rt == Rn \|\| Rn == Rt2)
				4944	S = MCDisassembler::SoftFail;
				4945
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4946	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4947	return MCDisassembler::Fail;
				4948	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4949	return MCDisassembler::Fail;
				4950	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4951	return MCDisassembler::Fail;
				4952	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4953	return MCDisassembler::Fail;
				4954
				4955	return S;
				4956	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4957
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4958	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4959	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4960	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4961	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4962	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4963	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4964	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4965	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4966	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4967
				4968	DecodeStatus S = MCDisassembler::Success;
				4969
				4970	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	05060f0	2011-11-15 20:30:41 +0000	[diff] [blame]	4971	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4972	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4973	Inst.setOpcode(ARM::VMOVv2f32);
				4974	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4975	}
				4976
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4977	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4978
				4979	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4980	return MCDisassembler::Fail;
				4981	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4982	return MCDisassembler::Fail;
				4983	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4984
				4985	return S;
				4986	}
				4987
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4988	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4989	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4990	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4991	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4992	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4993	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4994	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4995	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4996	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4997
				4998	DecodeStatus S = MCDisassembler::Success;
				4999
				5000	// VMOVv4f32 is ambiguous with these decodings.
				5001	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5002	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5003	Inst.setOpcode(ARM::VMOVv4f32);
				5004	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5005	}
				5006
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5007	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5008
				5009	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				5010	return MCDisassembler::Fail;
				5011	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				5012	return MCDisassembler::Fail;
				5013	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				5014
				5015	return S;
				5016	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5017
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5018	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5019	uint64_t Address, const void *Decoder) {
				5020	DecodeStatus S = MCDisassembler::Success;
				5021
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5022	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				5023	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5024	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				5025	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				5026	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5027
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5028	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5029	S = MCDisassembler::SoftFail;
				5030
				5031	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5032	return MCDisassembler::Fail;
				5033	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5034	return MCDisassembler::Fail;
				5035	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				5036	return MCDisassembler::Fail;
				5037	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				5038	return MCDisassembler::Fail;
				5039	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				5040	return MCDisassembler::Fail;
				5041
				5042	return S;
				5043	}
				5044
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5045	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				5046	uint64_t Address, const void *Decoder) {
				5047
				5048	DecodeStatus S = MCDisassembler::Success;
				5049
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5050	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				5051	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				5052	unsigned cop = fieldFromInstruction(Val, 8, 4);
				5053	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5054	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5055
				5056	if ((cop & ~0x1) == 0xa)
				5057	return MCDisassembler::Fail;
				5058
				5059	if (Rt == Rt2)
				5060	S = MCDisassembler::SoftFail;
				5061
				5062	Inst.addOperand(MCOperand::CreateImm(cop));
				5063	Inst.addOperand(MCOperand::CreateImm(opc1));
				5064	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5065	return MCDisassembler::Fail;
				5066	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5067	return MCDisassembler::Fail;
				5068	Inst.addOperand(MCOperand::CreateImm(CRm));
				5069
				5070	return S;
				5071	}
				5072