Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	12	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMAddressingModes.h"
				14	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	16	#include "llvm/MC/MCContext.h"
				17	#include "llvm/MC/MCExpr.h"
				18	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	19	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	20	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	21	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	24	#include "llvm/Support/LEB128.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	25	#include "llvm/Support/MemoryObject.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	26	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	27	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	28	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	29
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	30	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	31
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	32	typedef MCDisassembler::DecodeStatus DecodeStatus;
				33
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	34	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	35	// Handles the condition code status of instructions in IT blocks
				36	class ITStatus
				37	{
				38	public:
				39	// Returns the condition code for instruction in IT block
				40	unsigned getITCC() {
				41	unsigned CC = ARMCC::AL;
				42	if (instrInITBlock())
				43	CC = ITStates.back();
				44	return CC;
				45	}
				46
				47	// Advances the IT block state to the next T or E
				48	void advanceITState() {
				49	ITStates.pop_back();
				50	}
				51
				52	// Returns true if the current instruction is in an IT block
				53	bool instrInITBlock() {
				54	return !ITStates.empty();
				55	}
				56
				57	// Returns true if current instruction is the last instruction in an IT block
				58	bool instrLastInITBlock() {
				59	return ITStates.size() == 1;
				60	}
				61
				62	// Called when decoding an IT instruction. Sets the IT state for the following
				63	// instructions that for the IT block. Firstcond and Mask correspond to the
				64	// fields in the IT instruction encoding.
				65	void setITState(char Firstcond, char Mask) {
				66	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	67	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	68	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				70	assert(NumTZ <= 3 && "Invalid IT mask!");
				71	// push condition codes onto the stack the correct order for the pops
				72	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				73	bool T = ((Mask >> Pos) & 1) == CondBit0;
				74	if (T)
				75	ITStates.push_back(CCBits);
				76	else
				77	ITStates.push_back(CCBits ^ 1);
				78	}
				79	ITStates.push_back(CCBits);
				80	}
				81
				82	private:
				83	std::vector<unsigned char> ITStates;
				84	};
				85	}
				86
				87	namespace {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				89	class ARMDisassembler : public MCDisassembler {
				90	public:
				91	/// Constructor - Initializes the disassembler.
				92	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	93	ARMDisassembler(const MCSubtargetInfo &STI) :
				94	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95	}
				96
				97	~ARMDisassembler() {
				98	}
				99
				100	/// getInstruction - See MCDisassembler.
				101	DecodeStatus getInstruction(MCInst &instr,
				102	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	103	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	104	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	105	raw_ostream &vStream,
				106	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	};
				108
				109	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				110	class ThumbDisassembler : public MCDisassembler {
				111	public:
				112	/// Constructor - Initializes the disassembler.
				113	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	114	ThumbDisassembler(const MCSubtargetInfo &STI) :
				115	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	}
				117
				118	~ThumbDisassembler() {
				119	}
				120
				121	/// getInstruction - See MCDisassembler.
				122	DecodeStatus getInstruction(MCInst &instr,
				123	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	124	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	125	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	126	raw_ostream &vStream,
				127	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	128
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	129	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	130	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	131	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	132	void UpdateThumbVFPPredicate(MCInst&) const;
				133	};
				134	}
				135
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	136	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	137	switch (In) {
				138	case MCDisassembler::Success:
				139	// Out stays the same.
				140	return true;
				141	case MCDisassembler::SoftFail:
				142	Out = In;
				143	return true;
				144	case MCDisassembler::Fail:
				145	Out = In;
				146	return false;
				147	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	148	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	149	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	150
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	151
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	// Forward declare these because the autogenerated code will reference them.
				153	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	154	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	156	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	157	unsigned RegNo, uint64_t Address,
				158	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	159	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				160	unsigned RegNo, uint64_t Address,
				161	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	162	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	163	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	164	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	165	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	168	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				169	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	175	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	176	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	177	unsigned RegNo,
				178	uint64_t Address,
				179	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	180	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	181	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	183	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	184	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	185	unsigned RegNo, uint64_t Address,
				186	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	187
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	200
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	201	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	205	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	206	unsigned Insn,
				207	uint64_t Address,
				208	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
				217
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	218	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	219	unsigned Insn,
				220	uint64_t Adddress,
				221	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	222	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	223	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	236	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	237	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	238	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				239	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	240	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	241	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	244	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				245	uint64_t Address, const void *Decoder);
				246	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				247	uint64_t Address, const void *Decoder);
				248	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				249	uint64_t Address, const void *Decoder);
				250	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				251	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	284	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				285	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	318	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	319	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	324	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	325	uint64_t Address, const void *Decoder);
				326
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	327
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	328	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				349	uint64_t Address, const void* Decoder);
				350	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				351	uint64_t Address, const void* Decoder);
				352	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				353	uint64_t Address, const void* Decoder);
				354	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				355	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	356	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	357	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	372	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				373	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	382	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	383	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	384	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	385	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	386	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	387	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	388	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	389	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	390	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	391	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	392	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	393	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	394	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	395	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	396	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	397	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	398	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	399	uint64_t Address, const void *Decoder);
				400
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	401	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	402	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	403	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				404	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	405	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	406
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	407	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				408	return new ARMDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	409	}
				410
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	411	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				412	return new ThumbDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	413	}
				414
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	415	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	416	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	417	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	418	raw_ostream &os,
				419	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	420	CommentStream = &cs;
				421
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	422	uint8_t bytes[4];
				423
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	424	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				425	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				426
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	427	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	428	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	429	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	430	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	431	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	432
				433	// Encoded as a small-endian 32-bit word in the stream.
				434	uint32_t insn = (bytes[3] << 24) \|
				435	(bytes[2] << 16) \|
				436	(bytes[1] << 8) \|
				437	(bytes[0] << 0);
				438
				439	// Calling the auto-generated decoder function.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	440	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				441	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	442	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	443	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	444	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	445	}
				446
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	447	// VFP and NEON instructions, similarly, are shared between ARM
				448	// and Thumb modes.
				449	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	450	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	451	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	452	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	453	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	454	}
				455
				456	MI.clear();
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	457	result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
				458	if (result != MCDisassembler::Fail) {
				459	Size = 4;
				460	return result;
				461	}
				462
				463	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	464	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				465	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	466	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	467	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	468	// Add a fake predicate operand, because we share these instruction
				469	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	470	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				471	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	472	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	473	}
				474
				475	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	476	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				477	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	478	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	479	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	480	// Add a fake predicate operand, because we share these instruction
				481	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	482	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				483	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	484	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	485	}
				486
				487	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	488	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				489	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	490	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	491	Size = 4;
				492	// Add a fake predicate operand, because we share these instruction
				493	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	494	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				495	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	496	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	497	}
				498
				499	MI.clear();
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	500	result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
				501	this, STI);
				502	if (result != MCDisassembler::Fail) {
				503	Size = 4;
				504	return result;
				505	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	506
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	507	MI.clear();
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	508	result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
				509	this, STI);
				510	if (result != MCDisassembler::Fail) {
				511	Size = 4;
				512	return result;
				513	}
				514
				515	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	516	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	517	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	518	}
				519
				520	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	521	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	522	}
				523
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	524	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				525	/// immediate Value in the MCInst. The immediate Value has had any PC
				526	/// adjustment made by the caller. If the instruction is a branch instruction
				527	/// then isBranch is true, else false. If the getOpInfo() function was set as
				528	/// part of the setupForSymbolicDisassembly() call then that function is called
				529	/// to get any symbolic information at the Address for this instruction. If
				530	/// that returns non-zero then the symbolic information it returns is used to
				531	/// create an MCExpr and that is added as an operand to the MCInst. If
				532	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				533	/// Value is done and if a symbol is found an MCExpr is created with that, else
				534	/// an MCExpr with Value is created. This function returns true if it adds an
				535	/// operand to the MCInst and false otherwise.
				536	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				537	bool isBranch, uint64_t InstSize,
				538	MCInst &MI, const void *Decoder) {
				539	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	540	// FIXME: Does it make sense for value to be negative?
				541	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				542	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	543	}
				544
				545	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				546	/// referenced by a load instruction with the base register that is the Pc.
				547	/// These can often be values in a literal pool near the Address of the
				548	/// instruction. The Address of the instruction and its immediate Value are
				549	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	550	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	551	/// the referenced address is that of a symbol. Or it will return a pointer to
				552	/// a literal 'C' string if the referenced address of the literal pool's entry
				553	/// is an address into a section with 'C' string literals.
				554	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	555	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	556	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	557	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	558	}
				559
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	560	// Thumb1 instructions don't have explicit S bits. Rather, they
				561	// implicitly set CPSR. Since it's not represented in the encoding, the
				562	// auto-generated decoder won't inject the CPSR operand. We need to fix
				563	// that as a post-pass.
				564	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				565	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	566	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	567	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	568	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				569	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	570	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	571	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	572	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				573	return;
				574	}
				575	}
				576
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	577	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	578	}
				579
				580	// Most Thumb instructions don't have explicit predicates in the
				581	// encoding, but rather get their predicates from IT context. We need
				582	// to fix up the predicate operands using this context information as a
				583	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	584	MCDisassembler::DecodeStatus
				585	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	586	MCDisassembler::DecodeStatus S = Success;
				587
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	588	// A few instructions actually have predicates encoded in them. Don't
				589	// try to overwrite it if we're seeing one of those.
				590	switch (MI.getOpcode()) {
				591	case ARM::tBcc:
				592	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	593	case ARM::tCBZ:
				594	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	595	case ARM::tCPS:
				596	case ARM::t2CPS3p:
				597	case ARM::t2CPS2p:
				598	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	599	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	600	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	601	// Some instructions (mostly conditional branches) are not
				602	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	603	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	604	S = SoftFail;
				605	else
				606	return Success;
				607	break;
				608	case ARM::tB:
				609	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	610	case ARM::t2TBB:
				611	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	612	// Some instructions (mostly unconditional branches) can
				613	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	614	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	615	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	616	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	617	default:
				618	break;
				619	}
				620
				621	// If we're in an IT block, base the predicate on that. Otherwise,
				622	// assume a predicate of AL.
				623	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	624	CC = ITBlock.getITCC();
				625	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	626	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	627	if (ITBlock.instrInITBlock())
				628	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	629
				630	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	631	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	632	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	633	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				634	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	635	if (OpInfo[i].isPredicate()) {
				636	I = MI.insert(I, MCOperand::CreateImm(CC));
				637	++I;
				638	if (CC == ARMCC::AL)
				639	MI.insert(I, MCOperand::CreateReg(0));
				640	else
				641	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	642	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	643	}
				644	}
				645
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	646	I = MI.insert(I, MCOperand::CreateImm(CC));
				647	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	648	if (CC == ARMCC::AL)
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	649	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	650	else
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	651	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	652
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	653	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	654	}
				655
				656	// Thumb VFP instructions are a special case. Because we share their
				657	// encodings between ARM and Thumb modes, and they are predicable in ARM
				658	// mode, the auto-generated decoder will give them an (incorrect)
				659	// predicate operand. We need to rewrite these operands based on the IT
				660	// context as a post-pass.
				661	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				662	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	663	CC = ITBlock.getITCC();
				664	if (ITBlock.instrInITBlock())
				665	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	666
				667	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				668	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	669	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				670	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	671	if (OpInfo[i].isPredicate() ) {
				672	I->setImm(CC);
				673	++I;
				674	if (CC == ARMCC::AL)
				675	I->setReg(0);
				676	else
				677	I->setReg(ARM::CPSR);
				678	return;
				679	}
				680	}
				681	}
				682
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	683	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	684	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	685	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	686	raw_ostream &os,
				687	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	688	CommentStream = &cs;
				689
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	690	uint8_t bytes[4];
				691
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	692	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				693	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				694
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	695	// We want to read exactly 2 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	696	if (Region.readBytes(Address, 2, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	697	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	698	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	699	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	700
				701	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	702	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				703	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	704	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	705	Size = 2;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	706	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	707	return result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	708	}
				709
				710	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	711	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				712	Address, this, STI);
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	713	if (result) {
				714	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	715	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	716	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	717	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	718	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	719	}
				720
				721	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	722	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				723	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	724	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	725	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	726
				727	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				728	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	729	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	730	result = MCDisassembler::SoftFail;
				731
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	732	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	733
				734	// If we find an IT instruction, we need to parse its condition
				735	// code and mask operands so that we can apply them correctly
				736	// to the subsequent instructions.
				737	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	738
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	739	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	740	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	741	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	742	}
				743
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	744	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	745	}
				746
				747	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	748	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	749	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	750	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	751	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	752
				753	uint32_t insn32 = (bytes[3] << 8) \|
				754	(bytes[2] << 0) \|
				755	(bytes[1] << 24) \|
				756	(bytes[0] << 16);
				757	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	758	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				759	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	760	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	761	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	762	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	763	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	764	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	765	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	766	}
				767
				768	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	769	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				770	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	771	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	772	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	773	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	774	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	775	}
				776
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	777	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				778	MI.clear();
				779	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
				780	if (result != MCDisassembler::Fail) {
				781	Size = 4;
				782	UpdateThumbVFPPredicate(MI);
				783	return result;
				784	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	785	}
				786
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	787	MI.clear();
				788	result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
				789	if (result != MCDisassembler::Fail) {
				790	Size = 4;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	791	return result;
				792	}
				793
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	794	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				795	MI.clear();
				796	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				797	this, STI);
				798	if (result != MCDisassembler::Fail) {
				799	Size = 4;
				800	Check(result, AddThumbPredicate(MI));
				801	return result;
				802	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	803	}
				804
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	805	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	806	MI.clear();
				807	uint32_t NEONLdStInsn = insn32;
				808	NEONLdStInsn &= 0xF0FFFFFF;
				809	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	810	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				811	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	812	if (result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	813	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	814	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	815	return result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	816	}
				817	}
				818
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	819	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	820	MI.clear();
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	821	uint32_t NEONDataInsn = insn32;
				822	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				823	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				824	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	825	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				826	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	827	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	828	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	829	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	830	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	831	}
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	832
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	833	MI.clear();
				834	uint32_t NEONCryptoInsn = insn32;
				835	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				836	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				837	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
				838	result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
				839	Address, this, STI);
				840	if (result != MCDisassembler::Fail) {
				841	Size = 4;
				842	return result;
				843	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	844
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	845	MI.clear();
				846	uint32_t NEONv8Insn = insn32;
				847	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
				848	result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
				849	this, STI);
				850	if (result != MCDisassembler::Fail) {
				851	Size = 4;
				852	return result;
				853	}
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	854	}
				855
				856	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	857	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	858	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	859	}
				860
				861
				862	extern "C" void LLVMInitializeARMDisassembler() {
				863	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				864	createARMDisassembler);
				865	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				866	createThumbDisassembler);
				867	}
				868
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	869	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	870	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				871	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				872	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				873	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				874	};
				875
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	876	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	877	uint64_t Address, const void *Decoder) {
				878	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	879	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	880
				881	unsigned Register = GPRDecoderTable[RegNo];
				882	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	883	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	884	}
				885
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	886	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	887	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	888	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	889	DecodeStatus S = MCDisassembler::Success;
				890
				891	if (RegNo == 15)
				892	S = MCDisassembler::SoftFail;
				893
				894	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				895
				896	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	897	}
				898
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	899	static DecodeStatus
				900	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				901	uint64_t Address, const void *Decoder) {
				902	DecodeStatus S = MCDisassembler::Success;
				903
				904	if (RegNo == 15)
				905	{
				906	Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
				907	return MCDisassembler::Success;
				908	}
				909
				910	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				911	return S;
				912	}
				913
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	914	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	915	uint64_t Address, const void *Decoder) {
				916	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	917	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	918	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				919	}
				920
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	921	static const uint16_t GPRPairDecoderTable[] = {
				922	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				923	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				924	};
				925
				926	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				927	uint64_t Address, const void *Decoder) {
				928	DecodeStatus S = MCDisassembler::Success;
				929
				930	if (RegNo > 13)
				931	return MCDisassembler::Fail;
				932
				933	if ((RegNo & 1) \|\| RegNo == 0xe)
				934	S = MCDisassembler::SoftFail;
				935
				936	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
				937	Inst.addOperand(MCOperand::CreateReg(RegisterPair));
				938	return S;
				939	}
				940
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	941	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	942	uint64_t Address, const void *Decoder) {
				943	unsigned Register = 0;
				944	switch (RegNo) {
				945	case 0:
				946	Register = ARM::R0;
				947	break;
				948	case 1:
				949	Register = ARM::R1;
				950	break;
				951	case 2:
				952	Register = ARM::R2;
				953	break;
				954	case 3:
				955	Register = ARM::R3;
				956	break;
				957	case 9:
				958	Register = ARM::R9;
				959	break;
				960	case 12:
				961	Register = ARM::R12;
				962	break;
				963	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	964	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	965	}
				966
				967	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	968	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	969	}
				970
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	971	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	972	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	973	DecodeStatus S = MCDisassembler::Success;
				974	if (RegNo == 13 \|\| RegNo == 15)
				975	S = MCDisassembler::SoftFail;
				976	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				977	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	978	}
				979
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	980	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	981	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				982	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				983	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				984	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				985	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				986	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				987	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				988	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				989	};
				990
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	991	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	992	uint64_t Address, const void *Decoder) {
				993	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	994	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	995
				996	unsigned Register = SPRDecoderTable[RegNo];
				997	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	998	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	999	}
				1000
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1001	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1002	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1003	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1004	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1005	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1006	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1007	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1008	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1009	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1010	};
				1011
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1012	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1013	uint64_t Address, const void *Decoder) {
				1014	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1015	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1016
				1017	unsigned Register = DPRDecoderTable[RegNo];
				1018	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1019	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1020	}
				1021
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1022	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1023	uint64_t Address, const void *Decoder) {
				1024	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1025	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1026	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1027	}
				1028
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1029	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1030	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1031	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1032	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1033	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1034	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1035	}
				1036
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1037	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1038	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1039	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1040	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1041	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1042	};
				1043
				1044
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1045	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1046	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1047	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1048	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1049	RegNo >>= 1;
				1050
				1051	unsigned Register = QPRDecoderTable[RegNo];
				1052	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1053	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1054	}
				1055
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1056	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1057	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1058	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1059	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1060	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1061	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1062	ARM::Q15
				1063	};
				1064
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1065	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1066	uint64_t Address, const void *Decoder) {
				1067	if (RegNo > 30)
				1068	return MCDisassembler::Fail;
				1069
				1070	unsigned Register = DPairDecoderTable[RegNo];
				1071	Inst.addOperand(MCOperand::CreateReg(Register));
				1072	return MCDisassembler::Success;
				1073	}
				1074
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1075	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1076	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1077	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1078	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1079	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1080	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1081	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1082	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1083	ARM::D28_D30, ARM::D29_D31
				1084	};
				1085
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1086	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1087	unsigned RegNo,
				1088	uint64_t Address,
				1089	const void *Decoder) {
				1090	if (RegNo > 29)
				1091	return MCDisassembler::Fail;
				1092
				1093	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1094	Inst.addOperand(MCOperand::CreateReg(Register));
				1095	return MCDisassembler::Success;
				1096	}
				1097
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1098	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1099	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1100	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1101	// AL predicate is not allowed on Thumb1 branches.
				1102	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1103	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1104	Inst.addOperand(MCOperand::CreateImm(Val));
				1105	if (Val == ARMCC::AL) {
				1106	Inst.addOperand(MCOperand::CreateReg(0));
				1107	} else
				1108	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1109	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1110	}
				1111
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1112	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1113	uint64_t Address, const void *Decoder) {
				1114	if (Val)
				1115	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1116	else
				1117	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1118	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1119	}
				1120
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1121	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1122	uint64_t Address, const void *Decoder) {
				1123	uint32_t imm = Val & 0xFF;
				1124	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	a7ad9f3	2011-10-13 23:36:06 +0000	[diff] [blame]	1125	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1126	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1127	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1128	}
				1129
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1130	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1131	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1132	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1133
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1134	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1135	unsigned type = fieldFromInstruction(Val, 5, 2);
				1136	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1137
				1138	// Register-immediate
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1139	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1140	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1141
				1142	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1143	switch (type) {
				1144	case 0:
				1145	Shift = ARM_AM::lsl;
				1146	break;
				1147	case 1:
				1148	Shift = ARM_AM::lsr;
				1149	break;
				1150	case 2:
				1151	Shift = ARM_AM::asr;
				1152	break;
				1153	case 3:
				1154	Shift = ARM_AM::ror;
				1155	break;
				1156	}
				1157
				1158	if (Shift == ARM_AM::ror && imm == 0)
				1159	Shift = ARM_AM::rrx;
				1160
				1161	unsigned Op = Shift \| (imm << 3);
				1162	Inst.addOperand(MCOperand::CreateImm(Op));
				1163
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1164	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1165	}
				1166
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1167	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1168	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1169	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1170
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1171	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1172	unsigned type = fieldFromInstruction(Val, 5, 2);
				1173	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1174
				1175	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1176	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1177	return MCDisassembler::Fail;
				1178	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1179	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1180
				1181	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1182	switch (type) {
				1183	case 0:
				1184	Shift = ARM_AM::lsl;
				1185	break;
				1186	case 1:
				1187	Shift = ARM_AM::lsr;
				1188	break;
				1189	case 2:
				1190	Shift = ARM_AM::asr;
				1191	break;
				1192	case 3:
				1193	Shift = ARM_AM::ror;
				1194	break;
				1195	}
				1196
				1197	Inst.addOperand(MCOperand::CreateImm(Shift));
				1198
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1199	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1200	}
				1201
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1202	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1203	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1204	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1205
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1206	bool NeedDisjointWriteback = false;
				1207	unsigned WritebackReg = 0;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1208	switch (Inst.getOpcode()) {
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1209	default:
				1210	break;
				1211	case ARM::LDMIA_UPD:
				1212	case ARM::LDMDB_UPD:
				1213	case ARM::LDMIB_UPD:
				1214	case ARM::LDMDA_UPD:
				1215	case ARM::t2LDMIA_UPD:
				1216	case ARM::t2LDMDB_UPD:
				1217	case ARM::t2STMIA_UPD:
				1218	case ARM::t2STMDB_UPD:
				1219	NeedDisjointWriteback = true;
				1220	WritebackReg = Inst.getOperand(0).getReg();
				1221	break;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1222	}
				1223
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1224	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1225	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1226	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1227	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1228	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1229	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1230	// Writeback not allowed if Rn is in the target list.
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1231	if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1232	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1233	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1234	}
				1235
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1236	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1237	}
				1238
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1239	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1240	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1241	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1242
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1243	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1244	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1245
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1246	// In case of unpredictable encoding, tweak the operands.
				1247	if (regs == 0 \|\| (Vd + regs) > 32) {
				1248	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1249	regs = std::max( 1u, regs);
				1250	S = MCDisassembler::SoftFail;
				1251	}
				1252
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1253	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1254	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1255	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1256	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1257	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1258	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1259
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1260	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1261	}
				1262
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1263	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1264	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1265	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1266
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1267	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1268	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1269
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1270	// In case of unpredictable encoding, tweak the operands.
				1271	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1272	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1273	regs = std::max( 1u, regs);
				1274	regs = std::min(16u, regs);
				1275	S = MCDisassembler::SoftFail;
				1276	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1277
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1278	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1279	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1280	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1281	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1282	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1283	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1284
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1285	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1286	}
				1287
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1288	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1289	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1290	// This operand encodes a mask of contiguous zeros between a specified MSB
				1291	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1292	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1293	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1294	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1295	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1296	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1297
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1298	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1299	if (lsb > msb) {
				1300	Check(S, MCDisassembler::SoftFail);
				1301	// The check above will cause the warning for the "potentially undefined
				1302	// instruction encoding" but we can't build a bad MCOperand value here
				1303	// with a lsb > msb or else printing the MCInst will cause a crash.
				1304	lsb = msb;
				1305	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1306
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1307	uint32_t msb_mask = 0xFFFFFFFF;
				1308	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1309	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1310
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1311	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1312	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1313	}
				1314
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1315	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1316	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1317	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1318
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1319	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1320	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1321	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1322	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1323	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1324	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1325
				1326	switch (Inst.getOpcode()) {
				1327	case ARM::LDC_OFFSET:
				1328	case ARM::LDC_PRE:
				1329	case ARM::LDC_POST:
				1330	case ARM::LDC_OPTION:
				1331	case ARM::LDCL_OFFSET:
				1332	case ARM::LDCL_PRE:
				1333	case ARM::LDCL_POST:
				1334	case ARM::LDCL_OPTION:
				1335	case ARM::STC_OFFSET:
				1336	case ARM::STC_PRE:
				1337	case ARM::STC_POST:
				1338	case ARM::STC_OPTION:
				1339	case ARM::STCL_OFFSET:
				1340	case ARM::STCL_PRE:
				1341	case ARM::STCL_POST:
				1342	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1343	case ARM::t2LDC_OFFSET:
				1344	case ARM::t2LDC_PRE:
				1345	case ARM::t2LDC_POST:
				1346	case ARM::t2LDC_OPTION:
				1347	case ARM::t2LDCL_OFFSET:
				1348	case ARM::t2LDCL_PRE:
				1349	case ARM::t2LDCL_POST:
				1350	case ARM::t2LDCL_OPTION:
				1351	case ARM::t2STC_OFFSET:
				1352	case ARM::t2STC_PRE:
				1353	case ARM::t2STC_POST:
				1354	case ARM::t2STC_OPTION:
				1355	case ARM::t2STCL_OFFSET:
				1356	case ARM::t2STCL_PRE:
				1357	case ARM::t2STCL_POST:
				1358	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1359	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1360	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1361	break;
				1362	default:
				1363	break;
				1364	}
				1365
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame^]	1366	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				1367	.getFeatureBits();
				1368	if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
				1369	return MCDisassembler::Fail;
				1370
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1371	Inst.addOperand(MCOperand::CreateImm(coproc));
				1372	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1373	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1374	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1375
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1376	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1377	case ARM::t2LDC2_OFFSET:
				1378	case ARM::t2LDC2L_OFFSET:
				1379	case ARM::t2LDC2_PRE:
				1380	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1381	case ARM::t2STC2_OFFSET:
				1382	case ARM::t2STC2L_OFFSET:
				1383	case ARM::t2STC2_PRE:
				1384	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1385	case ARM::LDC2_OFFSET:
				1386	case ARM::LDC2L_OFFSET:
				1387	case ARM::LDC2_PRE:
				1388	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1389	case ARM::STC2_OFFSET:
				1390	case ARM::STC2L_OFFSET:
				1391	case ARM::STC2_PRE:
				1392	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1393	case ARM::t2LDC_OFFSET:
				1394	case ARM::t2LDCL_OFFSET:
				1395	case ARM::t2LDC_PRE:
				1396	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1397	case ARM::t2STC_OFFSET:
				1398	case ARM::t2STCL_OFFSET:
				1399	case ARM::t2STC_PRE:
				1400	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1401	case ARM::LDC_OFFSET:
				1402	case ARM::LDCL_OFFSET:
				1403	case ARM::LDC_PRE:
				1404	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1405	case ARM::STC_OFFSET:
				1406	case ARM::STCL_OFFSET:
				1407	case ARM::STC_PRE:
				1408	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1409	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1410	Inst.addOperand(MCOperand::CreateImm(imm));
				1411	break;
				1412	case ARM::t2LDC2_POST:
				1413	case ARM::t2LDC2L_POST:
				1414	case ARM::t2STC2_POST:
				1415	case ARM::t2STC2L_POST:
				1416	case ARM::LDC2_POST:
				1417	case ARM::LDC2L_POST:
				1418	case ARM::STC2_POST:
				1419	case ARM::STC2L_POST:
				1420	case ARM::t2LDC_POST:
				1421	case ARM::t2LDCL_POST:
				1422	case ARM::t2STC_POST:
				1423	case ARM::t2STCL_POST:
				1424	case ARM::LDC_POST:
				1425	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1426	case ARM::STC_POST:
				1427	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1428	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1429	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1430	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1431	// The 'option' variant doesn't encode 'U' in the immediate since
				1432	// the immediate is unsigned [0,255].
				1433	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1434	break;
				1435	}
				1436
				1437	switch (Inst.getOpcode()) {
				1438	case ARM::LDC_OFFSET:
				1439	case ARM::LDC_PRE:
				1440	case ARM::LDC_POST:
				1441	case ARM::LDC_OPTION:
				1442	case ARM::LDCL_OFFSET:
				1443	case ARM::LDCL_PRE:
				1444	case ARM::LDCL_POST:
				1445	case ARM::LDCL_OPTION:
				1446	case ARM::STC_OFFSET:
				1447	case ARM::STC_PRE:
				1448	case ARM::STC_POST:
				1449	case ARM::STC_OPTION:
				1450	case ARM::STCL_OFFSET:
				1451	case ARM::STCL_PRE:
				1452	case ARM::STCL_POST:
				1453	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1454	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1455	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1456	break;
				1457	default:
				1458	break;
				1459	}
				1460
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1461	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1462	}
				1463
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1464	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1465	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1466	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1467	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1468
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1469	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1470	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1471	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1472	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1473	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1474	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1475	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1476	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1477
				1478	// On stores, the writeback operand precedes Rt.
				1479	switch (Inst.getOpcode()) {
				1480	case ARM::STR_POST_IMM:
				1481	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1482	case ARM::STRB_POST_IMM:
				1483	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1484	case ARM::STRT_POST_REG:
				1485	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1486	case ARM::STRBT_POST_REG:
				1487	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1488	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1489	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1490	break;
				1491	default:
				1492	break;
				1493	}
				1494
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1495	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1496	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1497
				1498	// On loads, the writeback operand comes after Rt.
				1499	switch (Inst.getOpcode()) {
				1500	case ARM::LDR_POST_IMM:
				1501	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1502	case ARM::LDRB_POST_IMM:
				1503	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1504	case ARM::LDRBT_POST_REG:
				1505	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1506	case ARM::LDRT_POST_REG:
				1507	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1508	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1509	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1510	break;
				1511	default:
				1512	break;
				1513	}
				1514
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1515	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1516	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1517
				1518	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1519	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1520	Op = ARM_AM::sub;
				1521
				1522	bool writeback = (P == 0) \|\| (W == 1);
				1523	unsigned idx_mode = 0;
				1524	if (P && writeback)
				1525	idx_mode = ARMII::IndexModePre;
				1526	else if (!P && writeback)
				1527	idx_mode = ARMII::IndexModePost;
				1528
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1529	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1530	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1531
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1532	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1533	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1534	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1535	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1536	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1537	case 0:
				1538	Opc = ARM_AM::lsl;
				1539	break;
				1540	case 1:
				1541	Opc = ARM_AM::lsr;
				1542	break;
				1543	case 2:
				1544	Opc = ARM_AM::asr;
				1545	break;
				1546	case 3:
				1547	Opc = ARM_AM::ror;
				1548	break;
				1549	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1550	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1551	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1552	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1553	if (Opc == ARM_AM::ror && amt == 0)
				1554	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1555	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1556
				1557	Inst.addOperand(MCOperand::CreateImm(imm));
				1558	} else {
				1559	Inst.addOperand(MCOperand::CreateReg(0));
				1560	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1561	Inst.addOperand(MCOperand::CreateImm(tmp));
				1562	}
				1563
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1564	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1565	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1566
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1567	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1568	}
				1569
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1570	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1571	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1572	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1573
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1574	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1575	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1576	unsigned type = fieldFromInstruction(Val, 5, 2);
				1577	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1578	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1579
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1580	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1581	switch (type) {
				1582	case 0:
				1583	ShOp = ARM_AM::lsl;
				1584	break;
				1585	case 1:
				1586	ShOp = ARM_AM::lsr;
				1587	break;
				1588	case 2:
				1589	ShOp = ARM_AM::asr;
				1590	break;
				1591	case 3:
				1592	ShOp = ARM_AM::ror;
				1593	break;
				1594	}
				1595
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1596	if (ShOp == ARM_AM::ror && imm == 0)
				1597	ShOp = ARM_AM::rrx;
				1598
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1599	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1600	return MCDisassembler::Fail;
				1601	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1602	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1603	unsigned shift;
				1604	if (U)
				1605	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1606	else
				1607	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1608	Inst.addOperand(MCOperand::CreateImm(shift));
				1609
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1610	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1611	}
				1612
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1613	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1614	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1615	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1616	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1617
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1618	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1619	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1620	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1621	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1622	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1623	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1624	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1625	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1626	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1627	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1628
				1629	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1630
				1631	// For {LD,ST}RD, Rt must be even, else undefined.
				1632	switch (Inst.getOpcode()) {
				1633	case ARM::STRD:
				1634	case ARM::STRD_PRE:
				1635	case ARM::STRD_POST:
				1636	case ARM::LDRD:
				1637	case ARM::LDRD_PRE:
				1638	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1639	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1640	break;
				1641	default:
				1642	break;
				1643	}
				1644	switch (Inst.getOpcode()) {
				1645	case ARM::STRD:
				1646	case ARM::STRD_PRE:
				1647	case ARM::STRD_POST:
				1648	if (P == 0 && W == 1)
				1649	S = MCDisassembler::SoftFail;
				1650
				1651	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1652	S = MCDisassembler::SoftFail;
				1653	if (type && Rm == 15)
				1654	S = MCDisassembler::SoftFail;
				1655	if (Rt2 == 15)
				1656	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1657	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1658	S = MCDisassembler::SoftFail;
				1659	break;
				1660	case ARM::STRH:
				1661	case ARM::STRH_PRE:
				1662	case ARM::STRH_POST:
				1663	if (Rt == 15)
				1664	S = MCDisassembler::SoftFail;
				1665	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1666	S = MCDisassembler::SoftFail;
				1667	if (!type && Rm == 15)
				1668	S = MCDisassembler::SoftFail;
				1669	break;
				1670	case ARM::LDRD:
				1671	case ARM::LDRD_PRE:
				1672	case ARM::LDRD_POST:
				1673	if (type && Rn == 15){
				1674	if (Rt2 == 15)
				1675	S = MCDisassembler::SoftFail;
				1676	break;
				1677	}
				1678	if (P == 0 && W == 1)
				1679	S = MCDisassembler::SoftFail;
				1680	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1681	S = MCDisassembler::SoftFail;
				1682	if (!type && writeback && Rn == 15)
				1683	S = MCDisassembler::SoftFail;
				1684	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1685	S = MCDisassembler::SoftFail;
				1686	break;
				1687	case ARM::LDRH:
				1688	case ARM::LDRH_PRE:
				1689	case ARM::LDRH_POST:
				1690	if (type && Rn == 15){
				1691	if (Rt == 15)
				1692	S = MCDisassembler::SoftFail;
				1693	break;
				1694	}
				1695	if (Rt == 15)
				1696	S = MCDisassembler::SoftFail;
				1697	if (!type && Rm == 15)
				1698	S = MCDisassembler::SoftFail;
				1699	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1700	S = MCDisassembler::SoftFail;
				1701	break;
				1702	case ARM::LDRSH:
				1703	case ARM::LDRSH_PRE:
				1704	case ARM::LDRSH_POST:
				1705	case ARM::LDRSB:
				1706	case ARM::LDRSB_PRE:
				1707	case ARM::LDRSB_POST:
				1708	if (type && Rn == 15){
				1709	if (Rt == 15)
				1710	S = MCDisassembler::SoftFail;
				1711	break;
				1712	}
				1713	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1714	S = MCDisassembler::SoftFail;
				1715	if (!type && (Rt == 15 \|\| Rm == 15))
				1716	S = MCDisassembler::SoftFail;
				1717	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1718	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1719	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1720	default:
				1721	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1722	}
				1723
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1724	if (writeback) { // Writeback
				1725	if (P)
				1726	U \|= ARMII::IndexModePre << 9;
				1727	else
				1728	U \|= ARMII::IndexModePost << 9;
				1729
				1730	// On stores, the writeback operand precedes Rt.
				1731	switch (Inst.getOpcode()) {
				1732	case ARM::STRD:
				1733	case ARM::STRD_PRE:
				1734	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1735	case ARM::STRH:
				1736	case ARM::STRH_PRE:
				1737	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1738	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1739	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1740	break;
				1741	default:
				1742	break;
				1743	}
				1744	}
				1745
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1746	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1747	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1748	switch (Inst.getOpcode()) {
				1749	case ARM::STRD:
				1750	case ARM::STRD_PRE:
				1751	case ARM::STRD_POST:
				1752	case ARM::LDRD:
				1753	case ARM::LDRD_PRE:
				1754	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1755	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1756	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1757	break;
				1758	default:
				1759	break;
				1760	}
				1761
				1762	if (writeback) {
				1763	// On loads, the writeback operand comes after Rt.
				1764	switch (Inst.getOpcode()) {
				1765	case ARM::LDRD:
				1766	case ARM::LDRD_PRE:
				1767	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1768	case ARM::LDRH:
				1769	case ARM::LDRH_PRE:
				1770	case ARM::LDRH_POST:
				1771	case ARM::LDRSH:
				1772	case ARM::LDRSH_PRE:
				1773	case ARM::LDRSH_POST:
				1774	case ARM::LDRSB:
				1775	case ARM::LDRSB_PRE:
				1776	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1777	case ARM::LDRHTr:
				1778	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1779	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1780	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1781	break;
				1782	default:
				1783	break;
				1784	}
				1785	}
				1786
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1787	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1788	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1789
				1790	if (type) {
				1791	Inst.addOperand(MCOperand::CreateReg(0));
				1792	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1793	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1794	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1795	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1796	Inst.addOperand(MCOperand::CreateImm(U));
				1797	}
				1798
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1799	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1800	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1801
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1802	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1803	}
				1804
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1805	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1806	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1807	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1808
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1809	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1810	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1811
				1812	switch (mode) {
				1813	case 0:
				1814	mode = ARM_AM::da;
				1815	break;
				1816	case 1:
				1817	mode = ARM_AM::ia;
				1818	break;
				1819	case 2:
				1820	mode = ARM_AM::db;
				1821	break;
				1822	case 3:
				1823	mode = ARM_AM::ib;
				1824	break;
				1825	}
				1826
				1827	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1828	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1829	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1830
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1831	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1832	}
				1833
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1834	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1835	uint64_t Address, const void *Decoder) {
				1836	DecodeStatus S = MCDisassembler::Success;
				1837
				1838	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1839	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1840	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1841	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1842
				1843	if (pred == 0xF)
				1844	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1845
				1846	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1847	return MCDisassembler::Fail;
				1848	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1849	return MCDisassembler::Fail;
				1850	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1851	return MCDisassembler::Fail;
				1852	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1853	return MCDisassembler::Fail;
				1854	return S;
				1855	}
				1856
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1857	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1858	unsigned Insn,
				1859	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1860	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1861
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1862	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1863	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1864	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1865
				1866	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1867	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1868	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1869	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1870	Inst.setOpcode(ARM::RFEDA);
				1871	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1872	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1873	Inst.setOpcode(ARM::RFEDA_UPD);
				1874	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1875	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1876	Inst.setOpcode(ARM::RFEDB);
				1877	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1878	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1879	Inst.setOpcode(ARM::RFEDB_UPD);
				1880	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1881	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1882	Inst.setOpcode(ARM::RFEIA);
				1883	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1884	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1885	Inst.setOpcode(ARM::RFEIA_UPD);
				1886	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1887	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1888	Inst.setOpcode(ARM::RFEIB);
				1889	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1890	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1891	Inst.setOpcode(ARM::RFEIB_UPD);
				1892	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1893	case ARM::STMDA:
				1894	Inst.setOpcode(ARM::SRSDA);
				1895	break;
				1896	case ARM::STMDA_UPD:
				1897	Inst.setOpcode(ARM::SRSDA_UPD);
				1898	break;
				1899	case ARM::STMDB:
				1900	Inst.setOpcode(ARM::SRSDB);
				1901	break;
				1902	case ARM::STMDB_UPD:
				1903	Inst.setOpcode(ARM::SRSDB_UPD);
				1904	break;
				1905	case ARM::STMIA:
				1906	Inst.setOpcode(ARM::SRSIA);
				1907	break;
				1908	case ARM::STMIA_UPD:
				1909	Inst.setOpcode(ARM::SRSIA_UPD);
				1910	break;
				1911	case ARM::STMIB:
				1912	Inst.setOpcode(ARM::SRSIB);
				1913	break;
				1914	case ARM::STMIB_UPD:
				1915	Inst.setOpcode(ARM::SRSIB_UPD);
				1916	break;
				1917	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1918	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1919	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1920
				1921	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1922	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1923	// Check SRS encoding constraints
				1924	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1925	fieldFromInstruction(Insn, 20, 1) == 0))
				1926	return MCDisassembler::Fail;
				1927
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1928	Inst.addOperand(
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1929	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1930	return S;
				1931	}
				1932
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1933	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1934	}
				1935
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1936	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1937	return MCDisassembler::Fail;
				1938	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1939	return MCDisassembler::Fail; // Tied
				1940	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1941	return MCDisassembler::Fail;
				1942	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1943	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1944
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1945	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1946	}
				1947
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1948	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1949	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1950	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1951	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1952	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1953	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1954
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1955	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1956
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1957	// This decoder is called from multiple location that do not check
				1958	// the full encoding is valid before they do.
				1959	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1960	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1961	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1962	return MCDisassembler::Fail;
				1963
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1964	// imod == '01' --> UNPREDICTABLE
				1965	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1966	// return failure here. The '01' imod value is unprintable, so there's
				1967	// nothing useful we could do even if we returned UNPREDICTABLE.
				1968
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1969	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1970
				1971	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1972	Inst.setOpcode(ARM::CPS3p);
				1973	Inst.addOperand(MCOperand::CreateImm(imod));
				1974	Inst.addOperand(MCOperand::CreateImm(iflags));
				1975	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1976	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1977	Inst.setOpcode(ARM::CPS2p);
				1978	Inst.addOperand(MCOperand::CreateImm(imod));
				1979	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1980	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1981	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1982	Inst.setOpcode(ARM::CPS1p);
				1983	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1984	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1985	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1986	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1987	Inst.setOpcode(ARM::CPS1p);
				1988	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1989	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1990	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1991
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1992	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1993	}
				1994
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1995	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1996	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1997	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1998	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1999	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				2000	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2001
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2002	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2003
				2004	// imod == '01' --> UNPREDICTABLE
				2005	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2006	// return failure here. The '01' imod value is unprintable, so there's
				2007	// nothing useful we could do even if we returned UNPREDICTABLE.
				2008
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2009	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2010
				2011	if (imod && M) {
				2012	Inst.setOpcode(ARM::t2CPS3p);
				2013	Inst.addOperand(MCOperand::CreateImm(imod));
				2014	Inst.addOperand(MCOperand::CreateImm(iflags));
				2015	Inst.addOperand(MCOperand::CreateImm(mode));
				2016	} else if (imod && !M) {
				2017	Inst.setOpcode(ARM::t2CPS2p);
				2018	Inst.addOperand(MCOperand::CreateImm(imod));
				2019	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2020	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2021	} else if (!imod && M) {
				2022	Inst.setOpcode(ARM::t2CPS1p);
				2023	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2024	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2025	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2026	// imod == '00' && M == '0' --> this is a HINT instruction
				2027	int imm = fieldFromInstruction(Insn, 0, 8);
				2028	// HINT are defined only for immediate in [0..4]
				2029	if(imm > 4) return MCDisassembler::Fail;
				2030	Inst.setOpcode(ARM::t2HINT);
				2031	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2032	}
				2033
				2034	return S;
				2035	}
				2036
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2037	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2038	uint64_t Address, const void *Decoder) {
				2039	DecodeStatus S = MCDisassembler::Success;
				2040
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2041	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2042	unsigned imm = 0;
				2043
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2044	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2045	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2046	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2047	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2048
				2049	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2050	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2051	return MCDisassembler::Fail;
				2052	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2053	return MCDisassembler::Fail;
				2054
				2055	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2056	Inst.addOperand(MCOperand::CreateImm(imm));
				2057
				2058	return S;
				2059	}
				2060
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2061	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2062	uint64_t Address, const void *Decoder) {
				2063	DecodeStatus S = MCDisassembler::Success;
				2064
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2065	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2066	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2067	unsigned imm = 0;
				2068
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2069	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2070	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2071
				2072	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2073	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2074	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2075
				2076	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2077	return MCDisassembler::Fail;
				2078
				2079	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2080	Inst.addOperand(MCOperand::CreateImm(imm));
				2081
				2082	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2083	return MCDisassembler::Fail;
				2084
				2085	return S;
				2086	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2087
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2088	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2089	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2090	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2091
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2092	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2093	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2094	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2095	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2096	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2097
				2098	if (pred == 0xF)
				2099	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2100
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2101	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2102	return MCDisassembler::Fail;
				2103	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2104	return MCDisassembler::Fail;
				2105	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2106	return MCDisassembler::Fail;
				2107	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2108	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2109
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2110	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2111	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2112
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2113	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2114	}
				2115
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2116	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2117	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2118	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2119
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2120	unsigned add = fieldFromInstruction(Val, 12, 1);
				2121	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2122	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2123
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2124	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2125	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2126
				2127	if (!add) imm *= -1;
				2128	if (imm == 0 && !add) imm = INT32_MIN;
				2129	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2130	if (Rn == 15)
				2131	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2132
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2133	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2134	}
				2135
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2136	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2137	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2138	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2139
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2140	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2141	unsigned U = fieldFromInstruction(Val, 8, 1);
				2142	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2143
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2144	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2145	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2146
				2147	if (U)
				2148	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2149	else
				2150	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2151
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2152	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2153	}
				2154
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2155	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2156	uint64_t Address, const void *Decoder) {
				2157	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2158	}
				2159
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2160	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2161	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2162	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2163	DecodeStatus Status = MCDisassembler::Success;
				2164
				2165	// Note the J1 and J2 values are from the encoded instruction. So here
				2166	// change them to I1 and I2 values via as documented:
				2167	// I1 = NOT(J1 EOR S);
				2168	// I2 = NOT(J2 EOR S);
				2169	// and build the imm32 with one trailing zero as documented:
				2170	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2171	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2172	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2173	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2174	unsigned I1 = !(J1 ^ S);
				2175	unsigned I2 = !(J2 ^ S);
				2176	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2177	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2178	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2179	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2180	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2181	true, 4, Inst, Decoder))
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2182	Inst.addOperand(MCOperand::CreateImm(imm32));
				2183
				2184	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2185	}
				2186
				2187	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2188	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2189	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2190	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2191
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2192	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2193	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2194
				2195	if (pred == 0xF) {
				2196	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2197	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2198	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2199	true, 4, Inst, Decoder))
Benjamin Kramer	406dc17	2011-08-09 22:02:50 +0000	[diff] [blame]	2200	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2201	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2202	}
				2203
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2204	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2205	true, 4, Inst, Decoder))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2206	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2207	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2208	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2209
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2210	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2211	}
				2212
				2213
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2214	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2215	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2216	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2217
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2218	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2219	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2220
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2221	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2222	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2223	if (!align)
				2224	Inst.addOperand(MCOperand::CreateImm(0));
				2225	else
				2226	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2227
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2228	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2229	}
				2230
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2231	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2232	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2233	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2234
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2235	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2236	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2237	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2238	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2239	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2240	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2241
				2242	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2243	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2244	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2245	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2246	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2247	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2248	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2249	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2250	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2251	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2252	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2253	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2254	return MCDisassembler::Fail;
				2255	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2256	case ARM::VLD2b16:
				2257	case ARM::VLD2b32:
				2258	case ARM::VLD2b8:
				2259	case ARM::VLD2b16wb_fixed:
				2260	case ARM::VLD2b16wb_register:
				2261	case ARM::VLD2b32wb_fixed:
				2262	case ARM::VLD2b32wb_register:
				2263	case ARM::VLD2b8wb_fixed:
				2264	case ARM::VLD2b8wb_register:
				2265	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2266	return MCDisassembler::Fail;
				2267	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2268	default:
				2269	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2270	return MCDisassembler::Fail;
				2271	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2272
				2273	// Second output register
				2274	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2275	case ARM::VLD3d8:
				2276	case ARM::VLD3d16:
				2277	case ARM::VLD3d32:
				2278	case ARM::VLD3d8_UPD:
				2279	case ARM::VLD3d16_UPD:
				2280	case ARM::VLD3d32_UPD:
				2281	case ARM::VLD4d8:
				2282	case ARM::VLD4d16:
				2283	case ARM::VLD4d32:
				2284	case ARM::VLD4d8_UPD:
				2285	case ARM::VLD4d16_UPD:
				2286	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2287	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2288	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2289	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2290	case ARM::VLD3q8:
				2291	case ARM::VLD3q16:
				2292	case ARM::VLD3q32:
				2293	case ARM::VLD3q8_UPD:
				2294	case ARM::VLD3q16_UPD:
				2295	case ARM::VLD3q32_UPD:
				2296	case ARM::VLD4q8:
				2297	case ARM::VLD4q16:
				2298	case ARM::VLD4q32:
				2299	case ARM::VLD4q8_UPD:
				2300	case ARM::VLD4q16_UPD:
				2301	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2302	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2303	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2304	default:
				2305	break;
				2306	}
				2307
				2308	// Third output register
				2309	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2310	case ARM::VLD3d8:
				2311	case ARM::VLD3d16:
				2312	case ARM::VLD3d32:
				2313	case ARM::VLD3d8_UPD:
				2314	case ARM::VLD3d16_UPD:
				2315	case ARM::VLD3d32_UPD:
				2316	case ARM::VLD4d8:
				2317	case ARM::VLD4d16:
				2318	case ARM::VLD4d32:
				2319	case ARM::VLD4d8_UPD:
				2320	case ARM::VLD4d16_UPD:
				2321	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2322	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2323	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2324	break;
				2325	case ARM::VLD3q8:
				2326	case ARM::VLD3q16:
				2327	case ARM::VLD3q32:
				2328	case ARM::VLD3q8_UPD:
				2329	case ARM::VLD3q16_UPD:
				2330	case ARM::VLD3q32_UPD:
				2331	case ARM::VLD4q8:
				2332	case ARM::VLD4q16:
				2333	case ARM::VLD4q32:
				2334	case ARM::VLD4q8_UPD:
				2335	case ARM::VLD4q16_UPD:
				2336	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2337	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2338	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2339	break;
				2340	default:
				2341	break;
				2342	}
				2343
				2344	// Fourth output register
				2345	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2346	case ARM::VLD4d8:
				2347	case ARM::VLD4d16:
				2348	case ARM::VLD4d32:
				2349	case ARM::VLD4d8_UPD:
				2350	case ARM::VLD4d16_UPD:
				2351	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2352	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2353	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2354	break;
				2355	case ARM::VLD4q8:
				2356	case ARM::VLD4q16:
				2357	case ARM::VLD4q32:
				2358	case ARM::VLD4q8_UPD:
				2359	case ARM::VLD4q16_UPD:
				2360	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2361	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2362	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2363	break;
				2364	default:
				2365	break;
				2366	}
				2367
				2368	// Writeback operand
				2369	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2370	case ARM::VLD1d8wb_fixed:
				2371	case ARM::VLD1d16wb_fixed:
				2372	case ARM::VLD1d32wb_fixed:
				2373	case ARM::VLD1d64wb_fixed:
				2374	case ARM::VLD1d8wb_register:
				2375	case ARM::VLD1d16wb_register:
				2376	case ARM::VLD1d32wb_register:
				2377	case ARM::VLD1d64wb_register:
				2378	case ARM::VLD1q8wb_fixed:
				2379	case ARM::VLD1q16wb_fixed:
				2380	case ARM::VLD1q32wb_fixed:
				2381	case ARM::VLD1q64wb_fixed:
				2382	case ARM::VLD1q8wb_register:
				2383	case ARM::VLD1q16wb_register:
				2384	case ARM::VLD1q32wb_register:
				2385	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2386	case ARM::VLD1d8Twb_fixed:
				2387	case ARM::VLD1d8Twb_register:
				2388	case ARM::VLD1d16Twb_fixed:
				2389	case ARM::VLD1d16Twb_register:
				2390	case ARM::VLD1d32Twb_fixed:
				2391	case ARM::VLD1d32Twb_register:
				2392	case ARM::VLD1d64Twb_fixed:
				2393	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2394	case ARM::VLD1d8Qwb_fixed:
				2395	case ARM::VLD1d8Qwb_register:
				2396	case ARM::VLD1d16Qwb_fixed:
				2397	case ARM::VLD1d16Qwb_register:
				2398	case ARM::VLD1d32Qwb_fixed:
				2399	case ARM::VLD1d32Qwb_register:
				2400	case ARM::VLD1d64Qwb_fixed:
				2401	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2402	case ARM::VLD2d8wb_fixed:
				2403	case ARM::VLD2d16wb_fixed:
				2404	case ARM::VLD2d32wb_fixed:
				2405	case ARM::VLD2q8wb_fixed:
				2406	case ARM::VLD2q16wb_fixed:
				2407	case ARM::VLD2q32wb_fixed:
				2408	case ARM::VLD2d8wb_register:
				2409	case ARM::VLD2d16wb_register:
				2410	case ARM::VLD2d32wb_register:
				2411	case ARM::VLD2q8wb_register:
				2412	case ARM::VLD2q16wb_register:
				2413	case ARM::VLD2q32wb_register:
				2414	case ARM::VLD2b8wb_fixed:
				2415	case ARM::VLD2b16wb_fixed:
				2416	case ARM::VLD2b32wb_fixed:
				2417	case ARM::VLD2b8wb_register:
				2418	case ARM::VLD2b16wb_register:
				2419	case ARM::VLD2b32wb_register:
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2420	Inst.addOperand(MCOperand::CreateImm(0));
				2421	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2422	case ARM::VLD3d8_UPD:
				2423	case ARM::VLD3d16_UPD:
				2424	case ARM::VLD3d32_UPD:
				2425	case ARM::VLD3q8_UPD:
				2426	case ARM::VLD3q16_UPD:
				2427	case ARM::VLD3q32_UPD:
				2428	case ARM::VLD4d8_UPD:
				2429	case ARM::VLD4d16_UPD:
				2430	case ARM::VLD4d32_UPD:
				2431	case ARM::VLD4q8_UPD:
				2432	case ARM::VLD4q16_UPD:
				2433	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2434	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2435	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2436	break;
				2437	default:
				2438	break;
				2439	}
				2440
				2441	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2442	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2443	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2444
				2445	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2446	switch (Inst.getOpcode()) {
				2447	default:
				2448	// The below have been updated to have explicit am6offset split
				2449	// between fixed and register offset. For those instructions not
				2450	// yet updated, we need to add an additional reg0 operand for the
				2451	// fixed variant.
				2452	//
				2453	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2454	if (Rm == 0xd) {
				2455	Inst.addOperand(MCOperand::CreateReg(0));
				2456	break;
				2457	}
				2458	// Fall through to handle the register offset variant.
				2459	case ARM::VLD1d8wb_fixed:
				2460	case ARM::VLD1d16wb_fixed:
				2461	case ARM::VLD1d32wb_fixed:
				2462	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2463	case ARM::VLD1d8Twb_fixed:
				2464	case ARM::VLD1d16Twb_fixed:
				2465	case ARM::VLD1d32Twb_fixed:
				2466	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2467	case ARM::VLD1d8Qwb_fixed:
				2468	case ARM::VLD1d16Qwb_fixed:
				2469	case ARM::VLD1d32Qwb_fixed:
				2470	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2471	case ARM::VLD1d8wb_register:
				2472	case ARM::VLD1d16wb_register:
				2473	case ARM::VLD1d32wb_register:
				2474	case ARM::VLD1d64wb_register:
				2475	case ARM::VLD1q8wb_fixed:
				2476	case ARM::VLD1q16wb_fixed:
				2477	case ARM::VLD1q32wb_fixed:
				2478	case ARM::VLD1q64wb_fixed:
				2479	case ARM::VLD1q8wb_register:
				2480	case ARM::VLD1q16wb_register:
				2481	case ARM::VLD1q32wb_register:
				2482	case ARM::VLD1q64wb_register:
				2483	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2484	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2485	// increment and we need to add the register operand to the instruction.
				2486	if (Rm != 0xD && Rm != 0xF &&
				2487	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2488	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2489	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2490	case ARM::VLD2d8wb_fixed:
				2491	case ARM::VLD2d16wb_fixed:
				2492	case ARM::VLD2d32wb_fixed:
				2493	case ARM::VLD2b8wb_fixed:
				2494	case ARM::VLD2b16wb_fixed:
				2495	case ARM::VLD2b32wb_fixed:
				2496	case ARM::VLD2q8wb_fixed:
				2497	case ARM::VLD2q16wb_fixed:
				2498	case ARM::VLD2q32wb_fixed:
				2499	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2500	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2501
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2502	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2503	}
				2504
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2505	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2506	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2507	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2508	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2509	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2510	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2511	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2512
				2513	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2514	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2515	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2516	}
				2517
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2518	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2519	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2520	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2521	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2522
				2523	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2524	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2525	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2526	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2527
				2528	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2529	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2530	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2531	}
				2532
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2533	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2534	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2535	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2536	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2537
				2538	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2539	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2540
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2541	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2542	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2543	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2544	}
				2545
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2546	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2547	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2548	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2549	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2550
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2551	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2552	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2553	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2554	}
				2555
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2556	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2557	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2558	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2559
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2560	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2561	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2562	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2563	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2564	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2565	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2566
				2567	// Writeback Operand
				2568	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2569	case ARM::VST1d8wb_fixed:
				2570	case ARM::VST1d16wb_fixed:
				2571	case ARM::VST1d32wb_fixed:
				2572	case ARM::VST1d64wb_fixed:
				2573	case ARM::VST1d8wb_register:
				2574	case ARM::VST1d16wb_register:
				2575	case ARM::VST1d32wb_register:
				2576	case ARM::VST1d64wb_register:
				2577	case ARM::VST1q8wb_fixed:
				2578	case ARM::VST1q16wb_fixed:
				2579	case ARM::VST1q32wb_fixed:
				2580	case ARM::VST1q64wb_fixed:
				2581	case ARM::VST1q8wb_register:
				2582	case ARM::VST1q16wb_register:
				2583	case ARM::VST1q32wb_register:
				2584	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2585	case ARM::VST1d8Twb_fixed:
				2586	case ARM::VST1d16Twb_fixed:
				2587	case ARM::VST1d32Twb_fixed:
				2588	case ARM::VST1d64Twb_fixed:
				2589	case ARM::VST1d8Twb_register:
				2590	case ARM::VST1d16Twb_register:
				2591	case ARM::VST1d32Twb_register:
				2592	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2593	case ARM::VST1d8Qwb_fixed:
				2594	case ARM::VST1d16Qwb_fixed:
				2595	case ARM::VST1d32Qwb_fixed:
				2596	case ARM::VST1d64Qwb_fixed:
				2597	case ARM::VST1d8Qwb_register:
				2598	case ARM::VST1d16Qwb_register:
				2599	case ARM::VST1d32Qwb_register:
				2600	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2601	case ARM::VST2d8wb_fixed:
				2602	case ARM::VST2d16wb_fixed:
				2603	case ARM::VST2d32wb_fixed:
				2604	case ARM::VST2d8wb_register:
				2605	case ARM::VST2d16wb_register:
				2606	case ARM::VST2d32wb_register:
				2607	case ARM::VST2q8wb_fixed:
				2608	case ARM::VST2q16wb_fixed:
				2609	case ARM::VST2q32wb_fixed:
				2610	case ARM::VST2q8wb_register:
				2611	case ARM::VST2q16wb_register:
				2612	case ARM::VST2q32wb_register:
				2613	case ARM::VST2b8wb_fixed:
				2614	case ARM::VST2b16wb_fixed:
				2615	case ARM::VST2b32wb_fixed:
				2616	case ARM::VST2b8wb_register:
				2617	case ARM::VST2b16wb_register:
				2618	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2619	if (Rm == 0xF)
				2620	return MCDisassembler::Fail;
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2621	Inst.addOperand(MCOperand::CreateImm(0));
				2622	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2623	case ARM::VST3d8_UPD:
				2624	case ARM::VST3d16_UPD:
				2625	case ARM::VST3d32_UPD:
				2626	case ARM::VST3q8_UPD:
				2627	case ARM::VST3q16_UPD:
				2628	case ARM::VST3q32_UPD:
				2629	case ARM::VST4d8_UPD:
				2630	case ARM::VST4d16_UPD:
				2631	case ARM::VST4d32_UPD:
				2632	case ARM::VST4q8_UPD:
				2633	case ARM::VST4q16_UPD:
				2634	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2635	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2636	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2637	break;
				2638	default:
				2639	break;
				2640	}
				2641
				2642	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2643	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2644	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2645
				2646	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2647	switch (Inst.getOpcode()) {
				2648	default:
				2649	if (Rm == 0xD)
				2650	Inst.addOperand(MCOperand::CreateReg(0));
				2651	else if (Rm != 0xF) {
				2652	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2653	return MCDisassembler::Fail;
				2654	}
				2655	break;
				2656	case ARM::VST1d8wb_fixed:
				2657	case ARM::VST1d16wb_fixed:
				2658	case ARM::VST1d32wb_fixed:
				2659	case ARM::VST1d64wb_fixed:
				2660	case ARM::VST1q8wb_fixed:
				2661	case ARM::VST1q16wb_fixed:
				2662	case ARM::VST1q32wb_fixed:
				2663	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2664	case ARM::VST1d8Twb_fixed:
				2665	case ARM::VST1d16Twb_fixed:
				2666	case ARM::VST1d32Twb_fixed:
				2667	case ARM::VST1d64Twb_fixed:
				2668	case ARM::VST1d8Qwb_fixed:
				2669	case ARM::VST1d16Qwb_fixed:
				2670	case ARM::VST1d32Qwb_fixed:
				2671	case ARM::VST1d64Qwb_fixed:
				2672	case ARM::VST2d8wb_fixed:
				2673	case ARM::VST2d16wb_fixed:
				2674	case ARM::VST2d32wb_fixed:
				2675	case ARM::VST2q8wb_fixed:
				2676	case ARM::VST2q16wb_fixed:
				2677	case ARM::VST2q32wb_fixed:
				2678	case ARM::VST2b8wb_fixed:
				2679	case ARM::VST2b16wb_fixed:
				2680	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2681	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2682	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2683
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2684
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2685	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2686	switch (Inst.getOpcode()) {
				2687	case ARM::VST1q16:
				2688	case ARM::VST1q32:
				2689	case ARM::VST1q64:
				2690	case ARM::VST1q8:
				2691	case ARM::VST1q16wb_fixed:
				2692	case ARM::VST1q16wb_register:
				2693	case ARM::VST1q32wb_fixed:
				2694	case ARM::VST1q32wb_register:
				2695	case ARM::VST1q64wb_fixed:
				2696	case ARM::VST1q64wb_register:
				2697	case ARM::VST1q8wb_fixed:
				2698	case ARM::VST1q8wb_register:
				2699	case ARM::VST2d16:
				2700	case ARM::VST2d32:
				2701	case ARM::VST2d8:
				2702	case ARM::VST2d16wb_fixed:
				2703	case ARM::VST2d16wb_register:
				2704	case ARM::VST2d32wb_fixed:
				2705	case ARM::VST2d32wb_register:
				2706	case ARM::VST2d8wb_fixed:
				2707	case ARM::VST2d8wb_register:
				2708	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2709	return MCDisassembler::Fail;
				2710	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2711	case ARM::VST2b16:
				2712	case ARM::VST2b32:
				2713	case ARM::VST2b8:
				2714	case ARM::VST2b16wb_fixed:
				2715	case ARM::VST2b16wb_register:
				2716	case ARM::VST2b32wb_fixed:
				2717	case ARM::VST2b32wb_register:
				2718	case ARM::VST2b8wb_fixed:
				2719	case ARM::VST2b8wb_register:
				2720	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2721	return MCDisassembler::Fail;
				2722	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2723	default:
				2724	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2725	return MCDisassembler::Fail;
				2726	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2727
				2728	// Second input register
				2729	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2730	case ARM::VST3d8:
				2731	case ARM::VST3d16:
				2732	case ARM::VST3d32:
				2733	case ARM::VST3d8_UPD:
				2734	case ARM::VST3d16_UPD:
				2735	case ARM::VST3d32_UPD:
				2736	case ARM::VST4d8:
				2737	case ARM::VST4d16:
				2738	case ARM::VST4d32:
				2739	case ARM::VST4d8_UPD:
				2740	case ARM::VST4d16_UPD:
				2741	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2742	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2743	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2744	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2745	case ARM::VST3q8:
				2746	case ARM::VST3q16:
				2747	case ARM::VST3q32:
				2748	case ARM::VST3q8_UPD:
				2749	case ARM::VST3q16_UPD:
				2750	case ARM::VST3q32_UPD:
				2751	case ARM::VST4q8:
				2752	case ARM::VST4q16:
				2753	case ARM::VST4q32:
				2754	case ARM::VST4q8_UPD:
				2755	case ARM::VST4q16_UPD:
				2756	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2757	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2758	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2759	break;
				2760	default:
				2761	break;
				2762	}
				2763
				2764	// Third input register
				2765	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2766	case ARM::VST3d8:
				2767	case ARM::VST3d16:
				2768	case ARM::VST3d32:
				2769	case ARM::VST3d8_UPD:
				2770	case ARM::VST3d16_UPD:
				2771	case ARM::VST3d32_UPD:
				2772	case ARM::VST4d8:
				2773	case ARM::VST4d16:
				2774	case ARM::VST4d32:
				2775	case ARM::VST4d8_UPD:
				2776	case ARM::VST4d16_UPD:
				2777	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2778	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2779	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2780	break;
				2781	case ARM::VST3q8:
				2782	case ARM::VST3q16:
				2783	case ARM::VST3q32:
				2784	case ARM::VST3q8_UPD:
				2785	case ARM::VST3q16_UPD:
				2786	case ARM::VST3q32_UPD:
				2787	case ARM::VST4q8:
				2788	case ARM::VST4q16:
				2789	case ARM::VST4q32:
				2790	case ARM::VST4q8_UPD:
				2791	case ARM::VST4q16_UPD:
				2792	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2793	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2794	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2795	break;
				2796	default:
				2797	break;
				2798	}
				2799
				2800	// Fourth input register
				2801	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2802	case ARM::VST4d8:
				2803	case ARM::VST4d16:
				2804	case ARM::VST4d32:
				2805	case ARM::VST4d8_UPD:
				2806	case ARM::VST4d16_UPD:
				2807	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2808	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2809	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2810	break;
				2811	case ARM::VST4q8:
				2812	case ARM::VST4q16:
				2813	case ARM::VST4q32:
				2814	case ARM::VST4q8_UPD:
				2815	case ARM::VST4q16_UPD:
				2816	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2817	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2818	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2819	break;
				2820	default:
				2821	break;
				2822	}
				2823
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2824	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2825	}
				2826
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2827	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2828	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2829	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2830
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2831	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2832	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2833	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2834	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2835	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2836	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2837
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2838	if (size == 0 && align == 1)
				2839	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2840	align *= (1 << size);
				2841
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2842	switch (Inst.getOpcode()) {
				2843	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2844	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2845	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2846	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2847	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2848	return MCDisassembler::Fail;
				2849	break;
				2850	default:
				2851	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2852	return MCDisassembler::Fail;
				2853	break;
				2854	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2855	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2856	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2857	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2858	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2859
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2860	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2861	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2862	Inst.addOperand(MCOperand::CreateImm(align));
				2863
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2864	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2865	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2866	// increment and we need to add the register operand to the instruction.
				2867	if (Rm != 0xD && Rm != 0xF &&
				2868	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2869	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2870
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2871	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2872	}
				2873
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2874	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2875	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2876	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2877
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2878	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2879	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2880	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2881	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2882	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2883	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2884	align = 2size;
				2885
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2886	switch (Inst.getOpcode()) {
				2887	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2888	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2889	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2890	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2891	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2892	return MCDisassembler::Fail;
				2893	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2894	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2895	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2896	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2897	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2898	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2899	return MCDisassembler::Fail;
				2900	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2901	default:
				2902	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2903	return MCDisassembler::Fail;
				2904	break;
				2905	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2906
				2907	if (Rm != 0xF)
				2908	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2909
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2910	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2911	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2912	Inst.addOperand(MCOperand::CreateImm(align));
				2913
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2914	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2915	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2916	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2917	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2918
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2919	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2920	}
				2921
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2922	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2923	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2924	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2925
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2926	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2927	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2928	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2929	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2930	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2931
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2932	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2933	return MCDisassembler::Fail;
				2934	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2935	return MCDisassembler::Fail;
				2936	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2937	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2938	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2939	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2940	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2941	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2942
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2943	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2944	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2945	Inst.addOperand(MCOperand::CreateImm(0));
				2946
				2947	if (Rm == 0xD)
				2948	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2949	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2950	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2951	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2952	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2953
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2954	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2955	}
				2956
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2957	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2958	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2959	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2960
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2961	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2962	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2963	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2964	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2965	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2966	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2967	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2968
				2969	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2970	if (align == 0)
				2971	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2972	size = 4;
				2973	align = 16;
				2974	} else {
				2975	if (size == 2) {
				2976	size = 1 << size;
				2977	align *= 8;
				2978	} else {
				2979	size = 1 << size;
				2980	align = 4size;
				2981	}
				2982	}
				2983
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2984	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2985	return MCDisassembler::Fail;
				2986	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2987	return MCDisassembler::Fail;
				2988	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2989	return MCDisassembler::Fail;
				2990	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2991	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2992	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2993	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2994	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2995	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2996
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2997	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2998	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2999	Inst.addOperand(MCOperand::CreateImm(align));
				3000
				3001	if (Rm == 0xD)
				3002	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3003	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3004	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3005	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3006	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3007
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3008	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3009	}
				3010
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3011	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3012	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3013	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3014	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3015
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3016	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3017	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3018	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3019	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3020	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3021	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3022	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3023	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3024
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3025	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3026	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3027	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3028	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3029	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3030	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3031	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3032
				3033	Inst.addOperand(MCOperand::CreateImm(imm));
				3034
				3035	switch (Inst.getOpcode()) {
				3036	case ARM::VORRiv4i16:
				3037	case ARM::VORRiv2i32:
				3038	case ARM::VBICiv4i16:
				3039	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3040	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3041	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3042	break;
				3043	case ARM::VORRiv8i16:
				3044	case ARM::VORRiv4i32:
				3045	case ARM::VBICiv8i16:
				3046	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3047	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3048	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3049	break;
				3050	default:
				3051	break;
				3052	}
				3053
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3054	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3055	}
				3056
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3057	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3058	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3059	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3060
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3061	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3062	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3063	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3064	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3065	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3066
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3067	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3068	return MCDisassembler::Fail;
				3069	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3070	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3071	Inst.addOperand(MCOperand::CreateImm(8 << size));
				3072
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3073	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3074	}
				3075
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3076	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3077	uint64_t Address, const void *Decoder) {
				3078	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3079	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3080	}
				3081
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3082	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3083	uint64_t Address, const void *Decoder) {
				3084	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3085	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3086	}
				3087
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3088	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3089	uint64_t Address, const void *Decoder) {
				3090	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3091	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3092	}
				3093
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3094	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3095	uint64_t Address, const void *Decoder) {
				3096	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3097	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3098	}
				3099
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3100	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3101	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3102	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3103
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3104	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3105	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3106	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3107	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3108	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3109	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3110	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3111
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3112	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3113	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3114	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3115	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3116	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3117	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3118
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3119	switch (Inst.getOpcode()) {
				3120	case ARM::VTBL2:
				3121	case ARM::VTBX2:
				3122	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3123	return MCDisassembler::Fail;
				3124	break;
				3125	default:
				3126	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3127	return MCDisassembler::Fail;
				3128	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3129
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3130	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3131	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3132
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3133	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3134	}
				3135
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3136	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3137	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3138	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3139
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3140	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3141	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3142
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3143	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3144	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3145
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3146	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3147	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3148	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3149	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3150	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3151	case ARM::tADDrSPi:
				3152	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3153	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3154	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3155
				3156	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3157	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3158	}
				3159
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3160	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3161	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3162	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3163	true, 2, Inst, Decoder))
				3164	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3165	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3166	}
				3167
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3168	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3169	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3170	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3171	true, 4, Inst, Decoder))
				3172	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3173	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3174	}
				3175
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3176	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3177	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3178	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3179	true, 2, Inst, Decoder))
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3180	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3181	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3182	}
				3183
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3184	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3185	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3186	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3187
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3188	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3189	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3190
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3191	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3192	return MCDisassembler::Fail;
				3193	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3194	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3195
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3196	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3197	}
				3198
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3199	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3200	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3201	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3202
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3203	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3204	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3205
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3206	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3207	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3208	Inst.addOperand(MCOperand::CreateImm(imm));
				3209
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3210	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3211	}
				3212
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3213	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3214	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3215	unsigned imm = Val << 2;
				3216
				3217	Inst.addOperand(MCOperand::CreateImm(imm));
				3218	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3219
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3220	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3221	}
				3222
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3223	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3224	uint64_t Address, const void *Decoder) {
				3225	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b498132	2011-08-22 17:56:58 +0000	[diff] [blame]	3226	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3227
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3228	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3229	}
				3230
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3231	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3232	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3233	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3234
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3235	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3236	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3237	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3238
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3239	// Thumb stores cannot use PC as dest register.
				3240	switch (Inst.getOpcode()) {
				3241	case ARM::t2STRHs:
				3242	case ARM::t2STRBs:
				3243	case ARM::t2STRs:
				3244	if (Rn == 15)
				3245	return MCDisassembler::Fail;
				3246	default:
				3247	break;
				3248	}
				3249
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3250	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3251	return MCDisassembler::Fail;
				3252	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3253	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3254	Inst.addOperand(MCOperand::CreateImm(imm));
				3255
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3256	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3257	}
				3258
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3259	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3260	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3261	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3262
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3263	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3264	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3265
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3266	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3267	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3268	case ARM::t2LDRBs:
				3269	Inst.setOpcode(ARM::t2LDRBpci);
				3270	break;
				3271	case ARM::t2LDRHs:
				3272	Inst.setOpcode(ARM::t2LDRHpci);
				3273	break;
				3274	case ARM::t2LDRSHs:
				3275	Inst.setOpcode(ARM::t2LDRSHpci);
				3276	break;
				3277	case ARM::t2LDRSBs:
				3278	Inst.setOpcode(ARM::t2LDRSBpci);
				3279	break;
				3280	case ARM::t2LDRs:
				3281	Inst.setOpcode(ARM::t2LDRpci);
				3282	break;
				3283	case ARM::t2PLDs:
				3284	Inst.setOpcode(ARM::t2PLDpci);
				3285	break;
				3286	case ARM::t2PLIs:
				3287	Inst.setOpcode(ARM::t2PLIpci);
				3288	break;
				3289	default:
				3290	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3291	}
				3292
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3293	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3294	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3295
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3296	if (Rt == 15) {
				3297	switch (Inst.getOpcode()) {
				3298	case ARM::t2LDRSHs:
				3299	return MCDisassembler::Fail;
				3300	case ARM::t2LDRHs:
				3301	// FIXME: this instruction is only available with MP extensions,
				3302	// this should be checked first but we don't have access to the
				3303	// feature bits here.
				3304	Inst.setOpcode(ARM::t2PLDWs);
				3305	break;
				3306	default:
				3307	break;
				3308	}
				3309	}
				3310
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3311	switch (Inst.getOpcode()) {
				3312	case ARM::t2PLDs:
				3313	case ARM::t2PLDWs:
				3314	case ARM::t2PLIs:
				3315	break;
				3316	default:
				3317	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3318	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3319	}
				3320
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3321	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3322	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3323	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3324	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3325	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3326
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3327	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3328	}
				3329
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3330	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3331	uint64_t Address, const void* Decoder) {
				3332	DecodeStatus S = MCDisassembler::Success;
				3333
				3334	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3335	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3336	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3337	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3338	imm \|= (U << 8);
				3339	imm \|= (Rn << 9);
				3340
				3341	if (Rn == 15) {
				3342	switch (Inst.getOpcode()) {
				3343	case ARM::t2LDRi8:
				3344	Inst.setOpcode(ARM::t2LDRpci);
				3345	break;
				3346	case ARM::t2LDRBi8:
				3347	Inst.setOpcode(ARM::t2LDRBpci);
				3348	break;
				3349	case ARM::t2LDRSBi8:
				3350	Inst.setOpcode(ARM::t2LDRSBpci);
				3351	break;
				3352	case ARM::t2LDRHi8:
				3353	Inst.setOpcode(ARM::t2LDRHpci);
				3354	break;
				3355	case ARM::t2LDRSHi8:
				3356	Inst.setOpcode(ARM::t2LDRSHpci);
				3357	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3358	case ARM::t2PLDi8:
				3359	Inst.setOpcode(ARM::t2PLDpci);
				3360	break;
				3361	case ARM::t2PLIi8:
				3362	Inst.setOpcode(ARM::t2PLIpci);
				3363	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3364	default:
				3365	return MCDisassembler::Fail;
				3366	}
				3367	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3368	}
				3369
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3370	if (Rt == 15) {
				3371	switch (Inst.getOpcode()) {
				3372	case ARM::t2LDRSHi8:
				3373	return MCDisassembler::Fail;
				3374	default:
				3375	break;
				3376	}
				3377	}
				3378
				3379	switch (Inst.getOpcode()) {
				3380	case ARM::t2PLDi8:
				3381	case ARM::t2PLIi8:
Mihai Popa	c34bf73	2013-08-06 16:07:46 +0000	[diff] [blame]	3382	case ARM::t2PLDWi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3383	break;
				3384	default:
				3385	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3386	return MCDisassembler::Fail;
				3387	}
				3388
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3389	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3390	return MCDisassembler::Fail;
				3391	return S;
				3392	}
				3393
				3394	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3395	uint64_t Address, const void* Decoder) {
				3396	DecodeStatus S = MCDisassembler::Success;
				3397
				3398	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3399	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3400	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3401	imm \|= (Rn << 13);
				3402
				3403	if (Rn == 15) {
				3404	switch (Inst.getOpcode()) {
				3405	case ARM::t2LDRi12:
				3406	Inst.setOpcode(ARM::t2LDRpci);
				3407	break;
				3408	case ARM::t2LDRHi12:
				3409	Inst.setOpcode(ARM::t2LDRHpci);
				3410	break;
				3411	case ARM::t2LDRSHi12:
				3412	Inst.setOpcode(ARM::t2LDRSHpci);
				3413	break;
				3414	case ARM::t2LDRBi12:
				3415	Inst.setOpcode(ARM::t2LDRBpci);
				3416	break;
				3417	case ARM::t2LDRSBi12:
				3418	Inst.setOpcode(ARM::t2LDRSBpci);
				3419	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3420	case ARM::t2PLDi12:
				3421	Inst.setOpcode(ARM::t2PLDpci);
				3422	break;
				3423	case ARM::t2PLIi12:
				3424	Inst.setOpcode(ARM::t2PLIpci);
				3425	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3426	default:
				3427	return MCDisassembler::Fail;
				3428	}
				3429	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3430	}
				3431
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3432	if (Rt == 15) {
				3433	switch (Inst.getOpcode()) {
				3434	case ARM::t2LDRSHi12:
				3435	return MCDisassembler::Fail;
				3436	case ARM::t2LDRHi12:
				3437	Inst.setOpcode(ARM::t2PLDi12);
				3438	break;
				3439	default:
				3440	break;
				3441	}
				3442	}
				3443
				3444	switch (Inst.getOpcode()) {
				3445	case ARM::t2PLDi12:
Mihai Popa	c34bf73	2013-08-06 16:07:46 +0000	[diff] [blame]	3446	case ARM::t2PLDWi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3447	case ARM::t2PLIi12:
				3448	break;
				3449	default:
				3450	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3451	return MCDisassembler::Fail;
				3452	}
				3453
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3454	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3455	return MCDisassembler::Fail;
				3456	return S;
				3457	}
				3458
				3459	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3460	uint64_t Address, const void* Decoder) {
				3461	DecodeStatus S = MCDisassembler::Success;
				3462
				3463	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3464	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3465	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3466	imm \|= (Rn << 9);
				3467
				3468	if (Rn == 15) {
				3469	switch (Inst.getOpcode()) {
				3470	case ARM::t2LDRT:
				3471	Inst.setOpcode(ARM::t2LDRpci);
				3472	break;
				3473	case ARM::t2LDRBT:
				3474	Inst.setOpcode(ARM::t2LDRBpci);
				3475	break;
				3476	case ARM::t2LDRHT:
				3477	Inst.setOpcode(ARM::t2LDRHpci);
				3478	break;
				3479	case ARM::t2LDRSBT:
				3480	Inst.setOpcode(ARM::t2LDRSBpci);
				3481	break;
				3482	case ARM::t2LDRSHT:
				3483	Inst.setOpcode(ARM::t2LDRSHpci);
				3484	break;
				3485	default:
				3486	return MCDisassembler::Fail;
				3487	}
				3488	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3489	}
				3490
				3491	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3492	return MCDisassembler::Fail;
				3493	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3494	return MCDisassembler::Fail;
				3495	return S;
				3496	}
				3497
				3498	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3499	uint64_t Address, const void* Decoder) {
				3500	DecodeStatus S = MCDisassembler::Success;
				3501
				3502	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3503	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3504	int imm = fieldFromInstruction(Insn, 0, 12);
				3505
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3506	if (Rt == 15) {
				3507	switch (Inst.getOpcode()) {
				3508	case ARM::t2LDRBpci:
				3509	case ARM::t2LDRHpci:
				3510	Inst.setOpcode(ARM::t2PLDpci);
				3511	break;
				3512	case ARM::t2LDRSBpci:
				3513	Inst.setOpcode(ARM::t2PLIpci);
				3514	break;
				3515	case ARM::t2LDRSHpci:
				3516	return MCDisassembler::Fail;
				3517	default:
				3518	break;
				3519	}
				3520	}
				3521
				3522	switch(Inst.getOpcode()) {
				3523	case ARM::t2PLDpci:
				3524	case ARM::t2PLIpci:
				3525	break;
				3526	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3527	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3528	return MCDisassembler::Fail;
				3529	}
				3530
				3531	if (!U) {
				3532	// Special case for #-0.
				3533	if (imm == 0)
				3534	imm = INT32_MIN;
				3535	else
				3536	imm = -imm;
				3537	}
				3538	Inst.addOperand(MCOperand::CreateImm(imm));
				3539
				3540	return S;
				3541	}
				3542
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3543	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3544	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3545	if (Val == 0)
				3546	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3547	else {
				3548	int imm = Val & 0xFF;
				3549
				3550	if (!(Val & 0x100)) imm *= -1;
Richard Smith	228e6d4	2012-08-24 23:29:28 +0000	[diff] [blame]	3551	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3552	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3553
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3554	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3555	}
				3556
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3557	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3558	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3559	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3560
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3561	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3562	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3563
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3564	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3565	return MCDisassembler::Fail;
				3566	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3567	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3568
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3569	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3570	}
				3571
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3572	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3573	uint64_t Address, const void *Decoder) {
				3574	DecodeStatus S = MCDisassembler::Success;
				3575
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3576	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3577	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3578
				3579	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3580	return MCDisassembler::Fail;
				3581
				3582	Inst.addOperand(MCOperand::CreateImm(imm));
				3583
				3584	return S;
				3585	}
				3586
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3587	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3588	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3589	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3590	if (Val == 0)
				3591	imm = INT32_MIN;
				3592	else if (!(Val & 0x100))
				3593	imm *= -1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3594	Inst.addOperand(MCOperand::CreateImm(imm));
				3595
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3596	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3597	}
				3598
				3599
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3600	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3601	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3602	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3603
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3604	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3605	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3606
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3607	// Thumb stores cannot use PC as dest register.
				3608	switch (Inst.getOpcode()) {
				3609	case ARM::t2STRT:
				3610	case ARM::t2STRBT:
				3611	case ARM::t2STRHT:
				3612	case ARM::t2STRi8:
				3613	case ARM::t2STRHi8:
				3614	case ARM::t2STRBi8:
				3615	if (Rn == 15)
				3616	return MCDisassembler::Fail;
				3617	break;
				3618	default:
				3619	break;
				3620	}
				3621
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3622	// Some instructions always use an additive offset.
				3623	switch (Inst.getOpcode()) {
				3624	case ARM::t2LDRT:
				3625	case ARM::t2LDRBT:
				3626	case ARM::t2LDRHT:
				3627	case ARM::t2LDRSBT:
				3628	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3629	case ARM::t2STRT:
				3630	case ARM::t2STRBT:
				3631	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3632	imm \|= 0x100;
				3633	break;
				3634	default:
				3635	break;
				3636	}
				3637
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3638	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3639	return MCDisassembler::Fail;
				3640	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3641	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3642
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3643	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3644	}
				3645
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3646	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3647	uint64_t Address, const void *Decoder) {
				3648	DecodeStatus S = MCDisassembler::Success;
				3649
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3650	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3651	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3652	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3653	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3654	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3655	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3656
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3657	if (Rn == 15) {
				3658	switch (Inst.getOpcode()) {
				3659	case ARM::t2LDR_PRE:
				3660	case ARM::t2LDR_POST:
				3661	Inst.setOpcode(ARM::t2LDRpci);
				3662	break;
				3663	case ARM::t2LDRB_PRE:
				3664	case ARM::t2LDRB_POST:
				3665	Inst.setOpcode(ARM::t2LDRBpci);
				3666	break;
				3667	case ARM::t2LDRH_PRE:
				3668	case ARM::t2LDRH_POST:
				3669	Inst.setOpcode(ARM::t2LDRHpci);
				3670	break;
				3671	case ARM::t2LDRSB_PRE:
				3672	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3673	if (Rt == 15)
				3674	Inst.setOpcode(ARM::t2PLIpci);
				3675	else
				3676	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3677	break;
				3678	case ARM::t2LDRSH_PRE:
				3679	case ARM::t2LDRSH_POST:
				3680	Inst.setOpcode(ARM::t2LDRSHpci);
				3681	break;
				3682	default:
				3683	return MCDisassembler::Fail;
				3684	}
				3685	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3686	}
				3687
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3688	if (!load) {
				3689	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3690	return MCDisassembler::Fail;
				3691	}
				3692
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3693	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3694	return MCDisassembler::Fail;
				3695
				3696	if (load) {
				3697	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3698	return MCDisassembler::Fail;
				3699	}
				3700
				3701	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3702	return MCDisassembler::Fail;
				3703
				3704	return S;
				3705	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3706
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3707	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3708	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3709	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3710
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3711	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3712	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3713
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3714	// Thumb stores cannot use PC as dest register.
				3715	switch (Inst.getOpcode()) {
				3716	case ARM::t2STRi12:
				3717	case ARM::t2STRBi12:
				3718	case ARM::t2STRHi12:
				3719	if (Rn == 15)
				3720	return MCDisassembler::Fail;
				3721	default:
				3722	break;
				3723	}
				3724
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3725	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3726	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3727	Inst.addOperand(MCOperand::CreateImm(imm));
				3728
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3729	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3730	}
				3731
				3732
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3733	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3734	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3735	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3736
				3737	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3738	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3739	Inst.addOperand(MCOperand::CreateImm(imm));
				3740
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3741	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3742	}
				3743
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3744	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3745	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3746	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3747
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3748	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3749	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3750	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3751
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3752	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3753	return MCDisassembler::Fail;
Jim Grosbach	9d8f6f3	2012-04-27 23:51:33 +0000	[diff] [blame]	3754	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3755	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3756	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3757	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3758	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3759
				3760	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3761	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3762	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3763	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3764	}
				3765
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3766	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3767	}
				3768
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3769	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3770	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3771	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3772	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3773
				3774	Inst.addOperand(MCOperand::CreateImm(imod));
				3775	Inst.addOperand(MCOperand::CreateImm(flags));
				3776
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3777	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3778	}
				3779
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3780	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3781	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3782	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3783	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3784	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3785
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3786	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3787	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3788	Inst.addOperand(MCOperand::CreateImm(add));
				3789
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3790	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3791	}
				3792
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3793	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3794	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3795	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3796	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3797	// the encoded instruction. So here change to I1 and I2 values via:
				3798	// I1 = NOT(J1 EOR S);
				3799	// I2 = NOT(J2 EOR S);
				3800	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3801	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3802	unsigned S = (Val >> 23) & 1;
				3803	unsigned J1 = (Val >> 22) & 1;
				3804	unsigned J2 = (Val >> 21) & 1;
				3805	unsigned I1 = !(J1 ^ S);
				3806	unsigned I2 = !(J2 ^ S);
				3807	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3808	int imm32 = SignExtend32<25>(tmp << 1);
				3809
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3810	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3811	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3812	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3813	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3814	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3815	}
				3816
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3817	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3818	uint64_t Address, const void *Decoder) {
				3819	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3820	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3821
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame^]	3822	uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
				3823	.getFeatureBits();
				3824	if ((featureBits & ARM::HasV8Ops) && !(Val == 14 \|\| Val == 15))
				3825	return MCDisassembler::Fail;
				3826
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3827	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3828	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3829	}
				3830
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3831	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3832	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3833	uint64_t Address, const void *Decoder) {
				3834	DecodeStatus S = MCDisassembler::Success;
				3835
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3836	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3837	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3838
				3839	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3840	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3841	return MCDisassembler::Fail;
				3842	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3843	return MCDisassembler::Fail;
				3844	return S;
				3845	}
				3846
				3847	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3848	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3849	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3850	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3851
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3852	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3853	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3854	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3855	switch (opc) {
				3856	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3857	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3858	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3859	Inst.setOpcode(ARM::t2DSB);
				3860	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3861	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3862	Inst.setOpcode(ARM::t2DMB);
				3863	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3864	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3865	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3866	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3867	}
				3868
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3869	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3870	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3871	}
				3872
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3873	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3874	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3875	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3876	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3877	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3878
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3879	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3880	return MCDisassembler::Fail;
				3881	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3882	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3883
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3884	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3885	}
				3886
				3887	// Decode a shifted immediate operand. These basically consist
				3888	// of an 8-bit value, and a 4-bit directive that specifies either
				3889	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3890	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3891	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3892	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3893	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3894	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3895	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3896	switch (byte) {
				3897	case 0:
				3898	Inst.addOperand(MCOperand::CreateImm(imm));
				3899	break;
				3900	case 1:
				3901	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3902	break;
				3903	case 2:
				3904	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3905	break;
				3906	case 3:
				3907	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3908	(imm << 8) \| imm));
				3909	break;
				3910	}
				3911	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3912	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3913	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3914	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3915	Inst.addOperand(MCOperand::CreateImm(imm));
				3916	}
				3917
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3918	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3919	}
				3920
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3921	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3922	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3923	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3924	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3925	true, 2, Inst, Decoder))
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3926	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3927	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3928	}
				3929
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3930	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3931	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3932	// Val is passed in as S:J1:J2:imm10:imm11
				3933	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3934	// the encoded instruction. So here change to I1 and I2 values via:
				3935	// I1 = NOT(J1 EOR S);
				3936	// I2 = NOT(J2 EOR S);
				3937	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3938	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3939	unsigned S = (Val >> 23) & 1;
				3940	unsigned J1 = (Val >> 22) & 1;
				3941	unsigned J2 = (Val >> 21) & 1;
				3942	unsigned I1 = !(J1 ^ S);
				3943	unsigned I2 = !(J2 ^ S);
				3944	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3945	int imm32 = SignExtend32<25>(tmp << 1);
				3946
				3947	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	3948	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3949	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3950	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3951	}
				3952
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3953	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3954	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	3955	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3956	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3957
				3958	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3959	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3960	}
				3961
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	3962	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				3963	uint64_t Address, const void *Decoder) {
				3964	if (Val & ~0xf)
				3965	return MCDisassembler::Fail;
				3966
				3967	Inst.addOperand(MCOperand::CreateImm(Val));
				3968	return MCDisassembler::Success;
				3969	}
				3970
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3971	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3972	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3973	if (!Val) return MCDisassembler::Fail;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3974	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3975	return MCDisassembler::Success;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3976	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3977
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3978	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3979	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3980	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3981
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3982	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3983	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3984	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3985
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3986	if (Rn == 0xF)
				3987	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3988
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3989	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3990	return MCDisassembler::Fail;
				3991	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3992	return MCDisassembler::Fail;
				3993	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3994	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3995
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3996	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3997	}
				3998
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3999	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4000	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4001	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4002
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4003	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4004	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				4005	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4006	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4007
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	4008	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4009	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4010
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4011	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4012	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4013
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4014	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4015	return MCDisassembler::Fail;
				4016	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4017	return MCDisassembler::Fail;
				4018	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4019	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4020
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4021	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4022	}
				4023
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4024	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4025	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4026	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4027
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4028	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4029	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4030	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4031	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4032	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4033	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4034
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4035	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4036
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4037	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4038	return MCDisassembler::Fail;
				4039	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4040	return MCDisassembler::Fail;
				4041	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4042	return MCDisassembler::Fail;
				4043	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4044	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4045
				4046	return S;
				4047	}
				4048
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4049	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4050	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4051	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4052
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4053	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4054	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4055	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4056	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4057	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4058	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4059	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4060
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4061	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4062	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4063
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4064	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4065	return MCDisassembler::Fail;
				4066	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4067	return MCDisassembler::Fail;
				4068	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4069	return MCDisassembler::Fail;
				4070	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4071	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4072
				4073	return S;
				4074	}
				4075
				4076
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4077	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4078	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4079	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4080
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4081	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4082	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4083	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4084	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4085	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4086	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4087
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4088	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4089
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4090	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4091	return MCDisassembler::Fail;
				4092	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4093	return MCDisassembler::Fail;
				4094	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4095	return MCDisassembler::Fail;
				4096	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4097	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4098
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4099	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4100	}
				4101
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4102	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4103	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4104	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4105
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4106	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4107	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4108	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4109	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4110	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4111	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4112
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4113	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4114
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4115	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4116	return MCDisassembler::Fail;
				4117	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4118	return MCDisassembler::Fail;
				4119	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4120	return MCDisassembler::Fail;
				4121	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4122	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4123
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4124	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4125	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4126
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4127	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4128	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4129	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4130
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4131	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4132	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4133	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4134	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4135	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4136
				4137	unsigned align = 0;
				4138	unsigned index = 0;
				4139	switch (size) {
				4140	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4141	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4142	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4143	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4144	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4145	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4146	break;
				4147	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4148	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4149	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4150	index = fieldFromInstruction(Insn, 6, 2);
				4151	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4152	align = 2;
				4153	break;
				4154	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4155	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4156	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4157	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4158
				4159	switch (fieldFromInstruction(Insn, 4, 2)) {
				4160	case 0 :
				4161	align = 0; break;
				4162	case 3:
				4163	align = 4; break;
				4164	default:
				4165	return MCDisassembler::Fail;
				4166	}
				4167	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4168	}
				4169
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4170	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4171	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4172	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4173	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4174	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4175	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4176	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4177	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4178	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4179	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4180	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4181	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4182	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4183	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4184	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4185	}
				4186
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4187	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4188	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4189	Inst.addOperand(MCOperand::CreateImm(index));
				4190
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4191	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4192	}
				4193
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4194	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4195	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4196	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4197
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4198	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4199	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4200	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4201	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4202	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4203
				4204	unsigned align = 0;
				4205	unsigned index = 0;
				4206	switch (size) {
				4207	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4208	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4209	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4210	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4211	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4212	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4213	break;
				4214	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4215	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4216	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4217	index = fieldFromInstruction(Insn, 6, 2);
				4218	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4219	align = 2;
				4220	break;
				4221	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4222	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4223	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4224	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4225
				4226	switch (fieldFromInstruction(Insn, 4, 2)) {
				4227	case 0:
				4228	align = 0; break;
				4229	case 3:
				4230	align = 4; break;
				4231	default:
				4232	return MCDisassembler::Fail;
				4233	}
				4234	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4235	}
				4236
				4237	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4238	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4239	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4240	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4241	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4242	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4243	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4244	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4245	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4246	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4247	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4248	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4249	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4250	}
				4251
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4252	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4253	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4254	Inst.addOperand(MCOperand::CreateImm(index));
				4255
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4256	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4257	}
				4258
				4259
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4260	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4261	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4262	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4263
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4264	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4265	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4266	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4267	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4268	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4269
				4270	unsigned align = 0;
				4271	unsigned index = 0;
				4272	unsigned inc = 1;
				4273	switch (size) {
				4274	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4275	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4276	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4277	index = fieldFromInstruction(Insn, 5, 3);
				4278	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4279	align = 2;
				4280	break;
				4281	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4282	index = fieldFromInstruction(Insn, 6, 2);
				4283	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4284	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4285	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4286	inc = 2;
				4287	break;
				4288	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4289	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4290	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4291	index = fieldFromInstruction(Insn, 7, 1);
				4292	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4293	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4294	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4295	inc = 2;
				4296	break;
				4297	}
				4298
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4299	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4300	return MCDisassembler::Fail;
				4301	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4302	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4303	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4304	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4305	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4306	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4307	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4308	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4309	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4310	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4311	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4312	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4313	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4314	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4315	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4316	}
				4317
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4318	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4319	return MCDisassembler::Fail;
				4320	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4321	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4322	Inst.addOperand(MCOperand::CreateImm(index));
				4323
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4324	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4325	}
				4326
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4327	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4328	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4329	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4330
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4331	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4332	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4333	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4334	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4335	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4336
				4337	unsigned align = 0;
				4338	unsigned index = 0;
				4339	unsigned inc = 1;
				4340	switch (size) {
				4341	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4342	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4343	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4344	index = fieldFromInstruction(Insn, 5, 3);
				4345	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4346	align = 2;
				4347	break;
				4348	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4349	index = fieldFromInstruction(Insn, 6, 2);
				4350	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4351	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4352	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4353	inc = 2;
				4354	break;
				4355	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4356	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4357	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4358	index = fieldFromInstruction(Insn, 7, 1);
				4359	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4360	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4361	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4362	inc = 2;
				4363	break;
				4364	}
				4365
				4366	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4367	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4368	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4369	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4370	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4371	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4372	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4373	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4374	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4375	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4376	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4377	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4378	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4379	}
				4380
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4381	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4382	return MCDisassembler::Fail;
				4383	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4384	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4385	Inst.addOperand(MCOperand::CreateImm(index));
				4386
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4387	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4388	}
				4389
				4390
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4391	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4392	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4393	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4394
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4395	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4396	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4397	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4398	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4399	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4400
				4401	unsigned align = 0;
				4402	unsigned index = 0;
				4403	unsigned inc = 1;
				4404	switch (size) {
				4405	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4406	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4407	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4408	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4409	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4410	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4411	break;
				4412	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4413	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4414	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4415	index = fieldFromInstruction(Insn, 6, 2);
				4416	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4417	inc = 2;
				4418	break;
				4419	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4420	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4421	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4422	index = fieldFromInstruction(Insn, 7, 1);
				4423	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4424	inc = 2;
				4425	break;
				4426	}
				4427
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4428	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4429	return MCDisassembler::Fail;
				4430	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4431	return MCDisassembler::Fail;
				4432	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4433	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4434
				4435	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4436	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4437	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4438	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4439	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4440	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4441	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4442	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4443	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4444	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4445	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4446	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4447	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4448	}
				4449
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4450	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4451	return MCDisassembler::Fail;
				4452	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4453	return MCDisassembler::Fail;
				4454	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4455	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4456	Inst.addOperand(MCOperand::CreateImm(index));
				4457
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4458	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4459	}
				4460
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4461	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4462	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4463	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4464
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4465	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4466	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4467	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4468	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4469	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4470
				4471	unsigned align = 0;
				4472	unsigned index = 0;
				4473	unsigned inc = 1;
				4474	switch (size) {
				4475	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4476	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4477	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4478	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4479	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4480	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4481	break;
				4482	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4483	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4484	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4485	index = fieldFromInstruction(Insn, 6, 2);
				4486	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4487	inc = 2;
				4488	break;
				4489	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4490	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4491	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4492	index = fieldFromInstruction(Insn, 7, 1);
				4493	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4494	inc = 2;
				4495	break;
				4496	}
				4497
				4498	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4499	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4500	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4501	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4502	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4503	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4504	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4505	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4506	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4507	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4508	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4509	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4510	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4511	}
				4512
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4513	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4514	return MCDisassembler::Fail;
				4515	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4516	return MCDisassembler::Fail;
				4517	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4518	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4519	Inst.addOperand(MCOperand::CreateImm(index));
				4520
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4521	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4522	}
				4523
				4524
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4525	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4526	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4527	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4528
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4529	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4530	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4531	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4532	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4533	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4534
				4535	unsigned align = 0;
				4536	unsigned index = 0;
				4537	unsigned inc = 1;
				4538	switch (size) {
				4539	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4540	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4541	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4542	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4543	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4544	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4545	break;
				4546	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4547	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4548	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4549	index = fieldFromInstruction(Insn, 6, 2);
				4550	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4551	inc = 2;
				4552	break;
				4553	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4554	switch (fieldFromInstruction(Insn, 4, 2)) {
				4555	case 0:
				4556	align = 0; break;
				4557	case 3:
				4558	return MCDisassembler::Fail;
				4559	default:
				4560	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4561	}
				4562
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4563	index = fieldFromInstruction(Insn, 7, 1);
				4564	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4565	inc = 2;
				4566	break;
				4567	}
				4568
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4569	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4570	return MCDisassembler::Fail;
				4571	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4572	return MCDisassembler::Fail;
				4573	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4574	return MCDisassembler::Fail;
				4575	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4576	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4577
				4578	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4579	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4580	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4581	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4582	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4583	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4584	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4585	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4586	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4587	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4588	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4589	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4590	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4591	}
				4592
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4593	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4594	return MCDisassembler::Fail;
				4595	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4596	return MCDisassembler::Fail;
				4597	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4598	return MCDisassembler::Fail;
				4599	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4600	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4601	Inst.addOperand(MCOperand::CreateImm(index));
				4602
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4603	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4604	}
				4605
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4606	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4607	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4608	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4609
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4610	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4611	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4612	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4613	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4614	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4615
				4616	unsigned align = 0;
				4617	unsigned index = 0;
				4618	unsigned inc = 1;
				4619	switch (size) {
				4620	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4621	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4622	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4623	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4624	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4625	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4626	break;
				4627	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4628	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4629	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4630	index = fieldFromInstruction(Insn, 6, 2);
				4631	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4632	inc = 2;
				4633	break;
				4634	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4635	switch (fieldFromInstruction(Insn, 4, 2)) {
				4636	case 0:
				4637	align = 0; break;
				4638	case 3:
				4639	return MCDisassembler::Fail;
				4640	default:
				4641	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4642	}
				4643
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4644	index = fieldFromInstruction(Insn, 7, 1);
				4645	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4646	inc = 2;
				4647	break;
				4648	}
				4649
				4650	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4651	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4652	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4653	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4654	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4655	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4656	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4657	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4658	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4659	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4660	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4661	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4662	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4663	}
				4664
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4665	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4666	return MCDisassembler::Fail;
				4667	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4668	return MCDisassembler::Fail;
				4669	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4670	return MCDisassembler::Fail;
				4671	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4672	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4673	Inst.addOperand(MCOperand::CreateImm(index));
				4674
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4675	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4676	}
				4677
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4678	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4679	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4680	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4681	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4682	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4683	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4684	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4685	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4686
				4687	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4688	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4689
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4690	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4691	return MCDisassembler::Fail;
				4692	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4693	return MCDisassembler::Fail;
				4694	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4695	return MCDisassembler::Fail;
				4696	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4697	return MCDisassembler::Fail;
				4698	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4699	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4700
				4701	return S;
				4702	}
				4703
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4704	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4705	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4706	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4707	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4708	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4709	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4710	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4711	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4712
				4713	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4714	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4715
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4716	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4717	return MCDisassembler::Fail;
				4718	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4719	return MCDisassembler::Fail;
				4720	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4721	return MCDisassembler::Fail;
				4722	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4723	return MCDisassembler::Fail;
				4724	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4725	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4726
				4727	return S;
				4728	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4729
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4730	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4731	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4732	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4733	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4734	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4735
				4736	if (pred == 0xF) {
				4737	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4738	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4739	}
				4740
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4741	if (mask == 0x0)
				4742	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4743
				4744	Inst.addOperand(MCOperand::CreateImm(pred));
				4745	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4746	return S;
				4747	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4748
				4749	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4750	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4751	uint64_t Address, const void *Decoder) {
				4752	DecodeStatus S = MCDisassembler::Success;
				4753
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4754	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4755	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4756	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4757	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4758	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4759	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4760	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4761	bool writeback = (W == 1) \| (P == 0);
				4762
				4763	addr \|= (U << 8) \| (Rn << 9);
				4764
				4765	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4766	Check(S, MCDisassembler::SoftFail);
				4767	if (Rt == Rt2)
				4768	Check(S, MCDisassembler::SoftFail);
				4769
				4770	// Rt
				4771	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4772	return MCDisassembler::Fail;
				4773	// Rt2
				4774	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4775	return MCDisassembler::Fail;
				4776	// Writeback operand
				4777	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4778	return MCDisassembler::Fail;
				4779	// addr
				4780	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4781	return MCDisassembler::Fail;
				4782
				4783	return S;
				4784	}
				4785
				4786	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4787	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4788	uint64_t Address, const void *Decoder) {
				4789	DecodeStatus S = MCDisassembler::Success;
				4790
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4791	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4792	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4793	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4794	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4795	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4796	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4797	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4798	bool writeback = (W == 1) \| (P == 0);
				4799
				4800	addr \|= (U << 8) \| (Rn << 9);
				4801
				4802	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4803	Check(S, MCDisassembler::SoftFail);
				4804
				4805	// Writeback operand
				4806	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4807	return MCDisassembler::Fail;
				4808	// Rt
				4809	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4810	return MCDisassembler::Fail;
				4811	// Rt2
				4812	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4813	return MCDisassembler::Fail;
				4814	// addr
				4815	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4816	return MCDisassembler::Fail;
				4817
				4818	return S;
				4819	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4820
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4821	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4822	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4823	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4824	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4825	if (sign1 != sign2) return MCDisassembler::Fail;
				4826
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4827	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4828	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4829	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4830	Val \|= sign1 << 12;
				4831	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4832
				4833	return MCDisassembler::Success;
				4834	}
				4835
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4836	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	4837	uint64_t Address,
				4838	const void *Decoder) {
				4839	DecodeStatus S = MCDisassembler::Success;
				4840
				4841	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4842	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4843	Inst.addOperand(MCOperand::CreateImm(Val));
				4844	return S;
				4845	}
				4846
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4847	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4848	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4849	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4850	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4851	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4852	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4853
				4854	if (pred == 0xF)
				4855	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4856
				4857	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	4858
				4859	if (Rt == Rn \|\| Rn == Rt2)
				4860	S = MCDisassembler::SoftFail;
				4861
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4862	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4863	return MCDisassembler::Fail;
				4864	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4865	return MCDisassembler::Fail;
				4866	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4867	return MCDisassembler::Fail;
				4868	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4869	return MCDisassembler::Fail;
				4870
				4871	return S;
				4872	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4873
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4874	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4875	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4876	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4877	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4878	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4879	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4880	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4881	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4882	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4883
				4884	DecodeStatus S = MCDisassembler::Success;
				4885
				4886	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	05060f0	2011-11-15 20:30:41 +0000	[diff] [blame]	4887	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4888	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4889	Inst.setOpcode(ARM::VMOVv2f32);
				4890	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4891	}
				4892
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4893	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4894
				4895	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4896	return MCDisassembler::Fail;
				4897	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4898	return MCDisassembler::Fail;
				4899	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4900
				4901	return S;
				4902	}
				4903
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4904	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4905	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4906	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4907	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4908	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4909	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4910	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4911	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4912	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4913
				4914	DecodeStatus S = MCDisassembler::Success;
				4915
				4916	// VMOVv4f32 is ambiguous with these decodings.
				4917	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4918	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4919	Inst.setOpcode(ARM::VMOVv4f32);
				4920	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4921	}
				4922
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4923	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4924
				4925	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4926	return MCDisassembler::Fail;
				4927	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4928	return MCDisassembler::Fail;
				4929	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4930
				4931	return S;
				4932	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4933
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4934	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4935	uint64_t Address, const void *Decoder) {
				4936	DecodeStatus S = MCDisassembler::Success;
				4937
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4938	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4939	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4940	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4941	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4942	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4943
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4944	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4945	S = MCDisassembler::SoftFail;
				4946
				4947	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4948	return MCDisassembler::Fail;
				4949	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4950	return MCDisassembler::Fail;
				4951	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4952	return MCDisassembler::Fail;
				4953	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4954	return MCDisassembler::Fail;
				4955	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4956	return MCDisassembler::Fail;
				4957
				4958	return S;
				4959	}
				4960
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4961	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4962	uint64_t Address, const void *Decoder) {
				4963
				4964	DecodeStatus S = MCDisassembler::Success;
				4965
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4966	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4967	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4968	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4969	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4970	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4971
				4972	if ((cop & ~0x1) == 0xa)
				4973	return MCDisassembler::Fail;
				4974
				4975	if (Rt == Rt2)
				4976	S = MCDisassembler::SoftFail;
				4977
				4978	Inst.addOperand(MCOperand::CreateImm(cop));
				4979	Inst.addOperand(MCOperand::CreateImm(opc1));
				4980	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4981	return MCDisassembler::Fail;
				4982	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4983	return MCDisassembler::Fail;
				4984	Inst.addOperand(MCOperand::CreateImm(CRm));
				4985
				4986	return S;
				4987	}
				4988