Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 423c7149dccf4be10aca069616c07527e7d77fa9 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: dda118092081d6bc6a3e276fb55d480d358a71fe [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]21#include "llvm/CodeGen/LivePhysRegs.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]22#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]27#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]28#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]29#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]31#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]32#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]33#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]34#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]35#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]36#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]37#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]40#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]61static cl::opt<unsigned>
62PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67static cl::opt<unsigned>
68UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
71 cl::init(64), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]72
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]73enum {
74 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]75 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]79 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]80 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]104};
105
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]106struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]107 uint16_t RegOp;
108 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]109 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]110};
111
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]112// Pin the vtable to this file.
113void X86InstrInfo::anchor() {}
114
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]115X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
Dean Michael Berris52735fc2016-07-14 04:06:33 +0000[diff] [blame]120 X86::CATCHRET,
121 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]122 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]123
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]124 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
133 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
134 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
136 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
139 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
140 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
142 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
145 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
146 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
148 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16rCL, X86::SHL16mCL, 0 },
232 { X86::SHL16ri, X86::SHL16mi, 0 },
233 { X86::SHL32rCL, X86::SHL32mCL, 0 },
234 { X86::SHL32ri, X86::SHL32mi, 0 },
235 { X86::SHL64rCL, X86::SHL64mCL, 0 },
236 { X86::SHL64ri, X86::SHL64mi, 0 },
237 { X86::SHL8rCL, X86::SHL8mCL, 0 },
238 { X86::SHL8ri, X86::SHL8mi, 0 },
239 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
240 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
241 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
242 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
243 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
244 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
245 { X86::SHR16r1, X86::SHR16m1, 0 },
246 { X86::SHR16rCL, X86::SHR16mCL, 0 },
247 { X86::SHR16ri, X86::SHR16mi, 0 },
248 { X86::SHR32r1, X86::SHR32m1, 0 },
249 { X86::SHR32rCL, X86::SHR32mCL, 0 },
250 { X86::SHR32ri, X86::SHR32mi, 0 },
251 { X86::SHR64r1, X86::SHR64m1, 0 },
252 { X86::SHR64rCL, X86::SHR64mCL, 0 },
253 { X86::SHR64ri, X86::SHR64mi, 0 },
254 { X86::SHR8r1, X86::SHR8m1, 0 },
255 { X86::SHR8rCL, X86::SHR8mCL, 0 },
256 { X86::SHR8ri, X86::SHR8mi, 0 },
257 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
258 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
259 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
260 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
261 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
262 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
263 { X86::SUB16ri, X86::SUB16mi, 0 },
264 { X86::SUB16ri8, X86::SUB16mi8, 0 },
265 { X86::SUB16rr, X86::SUB16mr, 0 },
266 { X86::SUB32ri, X86::SUB32mi, 0 },
267 { X86::SUB32ri8, X86::SUB32mi8, 0 },
268 { X86::SUB32rr, X86::SUB32mr, 0 },
269 { X86::SUB64ri32, X86::SUB64mi32, 0 },
270 { X86::SUB64ri8, X86::SUB64mi8, 0 },
271 { X86::SUB64rr, X86::SUB64mr, 0 },
272 { X86::SUB8ri, X86::SUB8mi, 0 },
273 { X86::SUB8rr, X86::SUB8mr, 0 },
274 { X86::XOR16ri, X86::XOR16mi, 0 },
275 { X86::XOR16ri8, X86::XOR16mi8, 0 },
276 { X86::XOR16rr, X86::XOR16mr, 0 },
277 { X86::XOR32ri, X86::XOR32mi, 0 },
278 { X86::XOR32ri8, X86::XOR32mi8, 0 },
279 { X86::XOR32rr, X86::XOR32mr, 0 },
280 { X86::XOR64ri32, X86::XOR64mi32, 0 },
281 { X86::XOR64ri8, X86::XOR64mi8, 0 },
282 { X86::XOR64rr, X86::XOR64mr, 0 },
283 { X86::XOR8ri, X86::XOR8mi, 0 },
284 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]285 };
286
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]287 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]289 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]290 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]291 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]292 }
293
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]294 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]295 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
296 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
297 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
298 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
299 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]300 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
301 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
302 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
303 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
304 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
305 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
306 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
307 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
308 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
309 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
310 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
311 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
312 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
313 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
314 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]315 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]316 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
317 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
318 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
319 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
320 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
321 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
322 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
323 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
324 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
325 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
326 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
327 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
328 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
329 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
330 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
331 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
332 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
333 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
334 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
336 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
337 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
339 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
340 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
341 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
342 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
343 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]344 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
345 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
346 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
347 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]348 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
349 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]350 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
351 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
352 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]353 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
354 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
355 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
356 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
357 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
358 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
359 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
360 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
361 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
362 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
363 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
364 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
365 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
366 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
367 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
368 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
369 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
370 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]371 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]372 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
373 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
374 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]375 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]378 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]379 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]380 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
382 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
383 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
384 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
386 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
387 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
388 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]389 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
390 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]391
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]392 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]393 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]394 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
397 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]398 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]399
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]400 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]401 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
403 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
404 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
405 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
406 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]408 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]410 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]411 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]412
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]413 // AVX-512 foldable instructions (256-bit versions)
414 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
415 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
416 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
417 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
418 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
423 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]424
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]425 // AVX-512 foldable instructions (128-bit versions)
426 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
427 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
428 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
429 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
430 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
431 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
432 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
433 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
434 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]435 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]436
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]437 // F16C foldable instructions
438 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
439 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]440 };
441
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]442 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]443 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]445 }
446
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]447 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]448 { X86::BSF16rr, X86::BSF16rm, 0 },
449 { X86::BSF32rr, X86::BSF32rm, 0 },
450 { X86::BSF64rr, X86::BSF64rm, 0 },
451 { X86::BSR16rr, X86::BSR16rm, 0 },
452 { X86::BSR32rr, X86::BSR32rm, 0 },
453 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]454 { X86::CMP16rr, X86::CMP16rm, 0 },
455 { X86::CMP32rr, X86::CMP32rm, 0 },
456 { X86::CMP64rr, X86::CMP64rm, 0 },
457 { X86::CMP8rr, X86::CMP8rm, 0 },
458 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
459 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
460 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
461 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
462 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
463 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
464 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
465 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
466 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
467 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]468 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
469 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
470 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
471 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
472 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
473 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
474 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
475 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]476 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
477 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]478 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
479 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]480 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]481 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]482 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]483 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]484 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]485 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]486 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
487 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
488 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
489 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
490 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
491 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
492 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
493 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]494 { X86::MOV16rr, X86::MOV16rm, 0 },
495 { X86::MOV32rr, X86::MOV32rm, 0 },
496 { X86::MOV64rr, X86::MOV64rm, 0 },
497 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
498 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
499 { X86::MOV8rr, X86::MOV8rm, 0 },
500 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
501 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]502 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
503 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
504 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
505 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]506 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
507 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
508 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
509 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
510 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
511 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
512 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
513 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
514 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
515 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]516 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
517 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
518 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
519 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
520 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]521 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
522 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
523 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]524 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
525 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
526 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
527 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
528 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
529 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
530 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
531 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
532 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
533 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
534 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
535 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
536 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
537 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
538 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
539 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
540 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]541 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
542 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
543 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]544 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]545 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]546 { X86::RCPSSr, X86::RCPSSm, 0 },
547 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]548 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
549 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]550 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]551 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
552 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
553 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]554 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]555 { X86::SQRTSDr, X86::SQRTSDm, 0 },
556 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
557 { X86::SQRTSSr, X86::SQRTSSm, 0 },
558 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
559 { X86::TEST16rr, X86::TEST16rm, 0 },
560 { X86::TEST32rr, X86::TEST32rm, 0 },
561 { X86::TEST64rr, X86::TEST64rm, 0 },
562 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]563 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]564 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
565 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]566
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]567 // MMX version of foldable instructions
568 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
569 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
570 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
571 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
572 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
573 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
574 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
575 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
576 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
577 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
578
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]579 // 3DNow! version of foldable instructions
580 { X86::PF2IDrr, X86::PF2IDrm, 0 },
581 { X86::PF2IWrr, X86::PF2IWrm, 0 },
582 { X86::PFRCPrr, X86::PFRCPrm, 0 },
583 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
584 { X86::PI2FDrr, X86::PI2FDrm, 0 },
585 { X86::PI2FWrr, X86::PI2FWrm, 0 },
586 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
587
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]588 // AVX 128-bit versions of foldable instructions
589 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
590 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]591 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
592 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]593 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
594 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]595 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]596 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
597 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
598 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
600 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
601 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
602 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
603 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
604 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]605 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]606 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]607 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]608 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]609 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]610 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]611 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
612 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]613 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
614 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
615 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
616 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
617 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
618 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
619 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
620 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]621 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
622 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]623 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]624 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]625 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]626 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
627 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
628 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]629 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
630 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
631 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
632 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
633 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]634 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
635 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]636 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
637 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
638 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
639 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
640 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
641 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
642 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
643 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
644 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
645 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
646 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
647 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]648 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
649 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
650 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]651 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]652 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]653 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
654 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]655 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]656 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]657 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]658 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
659 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]660 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]661 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]662
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]663 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]664 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]665 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]666 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]667 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]668 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]669 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]670 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
671 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]672 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
673 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]674 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]675 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]676 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
677 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]678 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]679 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]680 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
681 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]682 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]683 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]684 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
685 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]686 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
687 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
688 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]689 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
690 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]691
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]692 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]693
694 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]699 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
700 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
701 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]702 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
703 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
704 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]705 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
706 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
707 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
708 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
709 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
710 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
711 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
712 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
713 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
714 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
715 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
716 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
717 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
718 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
719 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
720 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
721 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
722 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
723 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
724 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
725 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
726 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]727 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
728 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
729 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]730
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]731 // XOP foldable instructions
732 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
733 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
734 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
735 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
736 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
737 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
738 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
739 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
740 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
741 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
742 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
743 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
744 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
745 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
746 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
747 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
748 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
749 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
750 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
751 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
752 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
753 { X86::VPROTBri, X86::VPROTBmi, 0 },
754 { X86::VPROTBrr, X86::VPROTBmr, 0 },
755 { X86::VPROTDri, X86::VPROTDmi, 0 },
756 { X86::VPROTDrr, X86::VPROTDmr, 0 },
757 { X86::VPROTQri, X86::VPROTQmi, 0 },
758 { X86::VPROTQrr, X86::VPROTQmr, 0 },
759 { X86::VPROTWri, X86::VPROTWmi, 0 },
760 { X86::VPROTWrr, X86::VPROTWmr, 0 },
761 { X86::VPSHABrr, X86::VPSHABmr, 0 },
762 { X86::VPSHADrr, X86::VPSHADmr, 0 },
763 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
764 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
765 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
766 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
767 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
768 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
769
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]770 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]771 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
772 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]773 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
774 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
775 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
776 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
777 { X86::BLCI32rr, X86::BLCI32rm, 0 },
778 { X86::BLCI64rr, X86::BLCI64rm, 0 },
779 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
780 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
781 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
782 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
783 { X86::BLCS32rr, X86::BLCS32rm, 0 },
784 { X86::BLCS64rr, X86::BLCS64rm, 0 },
785 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
786 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]787 { X86::BLSI32rr, X86::BLSI32rm, 0 },
788 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]789 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
790 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]791 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
792 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
793 { X86::BLSR32rr, X86::BLSR32rm, 0 },
794 { X86::BLSR64rr, X86::BLSR64rm, 0 },
795 { X86::BZHI32rr, X86::BZHI32rm, 0 },
796 { X86::BZHI64rr, X86::BZHI64rm, 0 },
797 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
798 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
799 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
800 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
801 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
802 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]803 { X86::RORX32ri, X86::RORX32mi, 0 },
804 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]805 { X86::SARX32rr, X86::SARX32rm, 0 },
806 { X86::SARX64rr, X86::SARX64rm, 0 },
807 { X86::SHRX32rr, X86::SHRX32rm, 0 },
808 { X86::SHRX64rr, X86::SHRX64rm, 0 },
809 { X86::SHLX32rr, X86::SHLX32rm, 0 },
810 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]811 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
812 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]813 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
814 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
815 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]816 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
817 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]818
819 // AVX-512 foldable instructions
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]820 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
821 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
822 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
823 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
824 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
825 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
826 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
827 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
828 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
829 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
830 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
831 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
832 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
833 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
834 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
835 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
837 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]838
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]839 // AVX-512 foldable instructions (256-bit versions)
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]840 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
841 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
842 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
843 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
844 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
845 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
846 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
847 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
848 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
849 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
850 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
851 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
852 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
853 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]854
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]855 // AVX-512 foldable instructions (128-bit versions)
856 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
857 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
858 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
859 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
860 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
861 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
862 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
863 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
864 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
865 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
866 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
867 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]868 // F16C foldable instructions
869 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
870 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]871
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]872 // AES foldable instructions
873 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
874 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]875 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
876 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]877 };
878
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]879 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]880 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]881 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]882 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]883 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]884 }
885
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]886 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]887 { X86::ADC32rr, X86::ADC32rm, 0 },
888 { X86::ADC64rr, X86::ADC64rm, 0 },
889 { X86::ADD16rr, X86::ADD16rm, 0 },
890 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
891 { X86::ADD32rr, X86::ADD32rm, 0 },
892 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
893 { X86::ADD64rr, X86::ADD64rm, 0 },
894 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
895 { X86::ADD8rr, X86::ADD8rm, 0 },
896 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
897 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
898 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]899 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]900 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]901 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]902 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
903 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
904 { X86::AND16rr, X86::AND16rm, 0 },
905 { X86::AND32rr, X86::AND32rm, 0 },
906 { X86::AND64rr, X86::AND64rm, 0 },
907 { X86::AND8rr, X86::AND8rm, 0 },
908 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
909 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
910 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
911 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]912 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
913 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
914 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
915 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]916 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
917 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
918 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
919 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
920 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
921 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
922 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
923 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
924 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
925 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
926 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
927 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
928 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
929 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
930 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
931 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
932 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
933 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
934 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
935 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
936 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
937 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
938 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
939 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
940 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
941 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
942 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
943 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
944 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
945 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
946 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
947 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
948 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
949 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
950 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
951 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
952 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
953 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
954 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
955 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
956 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
957 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
958 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
959 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
960 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
961 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
962 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
963 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
964 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
965 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
966 { X86::CMPSDrr, X86::CMPSDrm, 0 },
967 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]968 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
969 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]970 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
971 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
972 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]973 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]974 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]975 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
976 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
977 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]978
Sanjay Patel8c13e362015-07-28 00:48:32 +0000[diff] [blame]979 // Do not fold Fs* scalar logical op loads because there are no scalar
980 // load variants for these instructions. When folded, the load is required
981 // to be 128-bits, so the load size would not match.
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]982
983 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
984 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
985 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
986 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
987 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
988 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
989 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
990 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]991 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
992 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
993 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
994 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
995 { X86::IMUL16rr, X86::IMUL16rm, 0 },
996 { X86::IMUL32rr, X86::IMUL32rm, 0 },
997 { X86::IMUL64rr, X86::IMUL64rm, 0 },
998 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
999 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]1000 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
1001 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1002 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1003 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1004 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1005 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1006 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1008 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1009 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1010 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1011 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1012 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1013 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1014 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1015 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1016 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1017 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1018 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1019 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1020 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1021 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1022 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1023 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1024 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1025 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1026 { X86::OR16rr, X86::OR16rm, 0 },
1027 { X86::OR32rr, X86::OR32rm, 0 },
1028 { X86::OR64rr, X86::OR64rm, 0 },
1029 { X86::OR8rr, X86::OR8rm, 0 },
1030 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1031 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1032 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1033 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1034 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1035 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1036 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1037 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1038 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1039 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1040 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1041 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1042 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1043 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1044 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1045 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1046 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1047 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1048 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1049 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1050 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1051 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1052 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1053 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1054 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1055 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1056 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1057 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1058 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1059 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1060 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1061 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1062 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1063 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1064 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1065 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1066 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1067 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1068 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1069 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1070 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1071 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1072 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1073 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1074 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1075 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1076 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1077 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1078 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1079 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1080 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1081 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1082 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1083 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1084 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1085 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1086 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1087 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1088 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1089 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1090 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1091 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1092 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1093 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1094 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1095 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1096 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1097 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1098 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1099 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1100 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1101 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1102 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1103 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1104 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1105 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1106 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1107 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1108 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1109 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1110 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1111 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1112 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1113 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1114 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1115 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1116 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1117 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1118 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1119 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1120 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1121 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1122 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1123 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1124 { X86::SBB32rr, X86::SBB32rm, 0 },
1125 { X86::SBB64rr, X86::SBB64rm, 0 },
1126 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1127 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1128 { X86::SUB16rr, X86::SUB16rm, 0 },
1129 { X86::SUB32rr, X86::SUB32rm, 0 },
1130 { X86::SUB64rr, X86::SUB64rm, 0 },
1131 { X86::SUB8rr, X86::SUB8rm, 0 },
1132 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1133 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1134 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1135 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1136 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1137 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1138 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1139 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1140 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1141 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1142 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1143 { X86::XOR16rr, X86::XOR16rm, 0 },
1144 { X86::XOR32rr, X86::XOR32rm, 0 },
1145 { X86::XOR64rr, X86::XOR64rm, 0 },
1146 { X86::XOR8rr, X86::XOR8rm, 0 },
1147 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1148 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1149
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1150 // MMX version of foldable instructions
1151 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1152 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1153 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1154 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1155 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1156 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1157 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1158 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1159 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1160 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1161 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1162 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1163 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1164 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1165 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1166 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1167 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1168 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1169 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1170 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1171 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1172 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1173 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1174 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1175 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1176 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1177 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1178 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1179 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1180 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1181 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1182 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1183 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1184 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1185 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1186 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1187 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1188 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1189 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1190 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1191 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1192 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1193 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1194 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1195 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1196 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1197 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1198 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1199 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1200 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1201 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1202 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1203 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1204 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1205 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1206 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1207 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1208 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1209 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1210 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1211 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1212 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1213 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1214 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1215 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1216 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1217 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1218 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1219 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1220 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1221
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1222 // 3DNow! version of foldable instructions
1223 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1224 { X86::PFACCrr, X86::PFACCrm, 0 },
1225 { X86::PFADDrr, X86::PFADDrm, 0 },
1226 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1227 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1228 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1229 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1230 { X86::PFMINrr, X86::PFMINrm, 0 },
1231 { X86::PFMULrr, X86::PFMULrm, 0 },
1232 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1233 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1234 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1235 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1236 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1237 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1238 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1239 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1240
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1241 // AVX 128-bit versions of foldable instructions
1242 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1243 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1244 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1245 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1246 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1247 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1248 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1249 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1250 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1251 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1252 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1253 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1254 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1255 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1256 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1257 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1258 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1259 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1260 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1261 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1262 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1263 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1264 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1265 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1266 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1267 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1268 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1269 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1270 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1271 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1272 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1273 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1274 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1275 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1276 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1277 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1278 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1279 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1280 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1281 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1282 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1283 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1284 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1285 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1286 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1287 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1288 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1289 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]1290 // Do not fold VFs* loads because there are no scalar load variants for
1291 // these instructions. When folded, the load is required to be 128-bits, so
1292 // the load size would not match.
1293 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1294 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1295 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1296 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1297 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1298 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1299 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1300 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1301 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1302 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1303 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1304 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1305 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1306 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1307 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1308 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1309 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1310 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1311 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1312 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1313 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1314 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1315 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1316 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1317 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1318 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1319 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1320 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1321 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1322 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1323 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1324 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1325 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1326 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1327 { X86::VORPDrr, X86::VORPDrm, 0 },
1328 { X86::VORPSrr, X86::VORPSrm, 0 },
1329 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1330 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1331 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1332 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1333 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1334 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1335 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1336 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1337 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1338 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1339 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1340 { X86::VPADDWrr, X86::VPADDWrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1341 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1342 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1343 { X86::VPANDrr, X86::VPANDrm, 0 },
1344 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1345 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1346 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1347 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1348 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1349 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1350 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1351 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1352 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1353 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1354 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1355 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1356 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1357 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1358 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1359 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1360 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1361 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1362 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1363 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1364 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1365 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1366 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1367 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1368 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1369 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1370 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1371 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1372 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1373 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1374 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1375 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1376 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1377 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1378 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1379 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1380 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1381 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1382 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1383 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1384 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1385 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1386 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1387 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1388 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1389 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1390 { X86::VPORrr, X86::VPORrm, 0 },
1391 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1392 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1393 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1394 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1395 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1396 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1397 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1398 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1399 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1400 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1401 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1402 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1403 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1404 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1405 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1406 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1407 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1408 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1409 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1410 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1411 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1412 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1413 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1414 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1415 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1416 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1417 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1418 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1419 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1420 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1421 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1422 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1423 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1424 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1425 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1426 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1427 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1428 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1429 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1430 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1431 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1432 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1433 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1434 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1435 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1436 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1437
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1438 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1439 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1440 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1441 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1442 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1443 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1444 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1445 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1446 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1447 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1448 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1449 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1450 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1451 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1452 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1453 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1454 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1455 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1456 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1457 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1458 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1459 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1460 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1461 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1462 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1463 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1464 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1465 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1466 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1467 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1468 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1469 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1470 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1471 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1472 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1473 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1474 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1475 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1476 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1477 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1478 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1479 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1480 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1481 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1482
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1483 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1484 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1485 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1486 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1487 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1488 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1489 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1490 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1491 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1492 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1493 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1494 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1495 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1496 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1497 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1498 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1499 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1500 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1501 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1502 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1503 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1504 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1505 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1506 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1507 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1508 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1509 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1510 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1511 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1512 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1513 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1514 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1515 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1516 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1517 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1518 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1519 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1520 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1521 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1522 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1523 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1524 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1525 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1526 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1527 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1528 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1529 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1530 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1531 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1532 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1533 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1534 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1535 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1536 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1537 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1538 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1539 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1540 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1541 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1542 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1543 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1544 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1545 { X86::VPORYrr, X86::VPORYrm, 0 },
1546 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1547 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1548 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1549 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1550 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1551 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1552 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1553 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1554 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1555 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1556 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1557 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1558 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1559 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1560 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1561 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1562 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1563 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1564 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1565 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1566 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1567 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1568 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1569 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1570 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1571 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1572 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1573 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1574 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1575 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1576 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1577 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1578 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1579 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1580 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1581 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1582 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1583 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1584 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1585 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1586
1587 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1588 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1589 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1590 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1591 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1592 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Ymr, TB_ALIGN_NONE },
1593 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1594 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1595 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1596 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1597 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1598 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Ymr, TB_ALIGN_NONE },
1599 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1600 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1601 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1602 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1603 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1604 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Ymr, TB_ALIGN_NONE },
1605 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1606 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1607 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1608 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1609 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1610 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Ymr, TB_ALIGN_NONE },
1611 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1612 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1613 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1614 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Ymr, TB_ALIGN_NONE },
1615 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Ymr, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1616 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1617 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1618 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Ymr, TB_ALIGN_NONE },
1619 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Ymr, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1620
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1621 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1622 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1623 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1624 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1625 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1626 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1627 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1628 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1629 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1630 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1631 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1632 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1633 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1634 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1635 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1636 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1637 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1638 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1639 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1640 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1641 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1642 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1643 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1644 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1645 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1646 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1647 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1648 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1649 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1650 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1651 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1652 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1653 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1654 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1655 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1656 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1657 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1658 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1659 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1660 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1661
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1662 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1663 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1664 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1665 { X86::MULX32rr, X86::MULX32rm, 0 },
1666 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1667 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1668 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1669 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1670 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1671
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1672 // ADX foldable instructions
1673 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1674 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1675 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1676 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1677
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1678 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1679 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1680 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1681 { X86::VADDSSZrr, X86::VADDSSZrm, 0 },
1682 { X86::VADDSSZrr_Int, X86::VADDSSZrm_Int, 0 },
1683 { X86::VADDSDZrr, X86::VADDSDZrm, 0 },
1684 { X86::VADDSDZrr_Int, X86::VADDSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1685 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1686 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1687 { X86::VSUBSSZrr, X86::VSUBSSZrm, 0 },
1688 { X86::VSUBSSZrr_Int, X86::VSUBSSZrm_Int, 0 },
1689 { X86::VSUBSDZrr, X86::VSUBSDZrm, 0 },
1690 { X86::VSUBSDZrr_Int, X86::VSUBSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1691 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1692 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1693 { X86::VMULSSZrr, X86::VMULSSZrm, 0 },
1694 { X86::VMULSSZrr_Int, X86::VMULSSZrm_Int, 0 },
1695 { X86::VMULSDZrr, X86::VMULSDZrm, 0 },
1696 { X86::VMULSDZrr_Int, X86::VMULSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1697 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1698 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]1699 { X86::VDIVSSZrr, X86::VDIVSSZrm, 0 },
1700 { X86::VDIVSSZrr_Int, X86::VDIVSSZrm_Int, 0 },
1701 { X86::VDIVSDZrr, X86::VDIVSDZrm, 0 },
1702 { X86::VDIVSDZrr_Int, X86::VDIVSDZrm_Int, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1703 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1704 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1705 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1706 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1707 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1708 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1709 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1710 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1711 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1712 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1713 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1714 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1715 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1716 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1717 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1718 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1719 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1720 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1721 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1722 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1723 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1724 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1725 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1726 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1727 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1728 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1729 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1730 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1731 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1732 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1733 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1734
1735 // AVX-512{F,VL} foldable instructions
1736 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1737 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1738 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1739
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1740 // AVX-512{F,VL} foldable instructions
1741 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1742 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1743 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1744 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
Craig Topper0b907562016-07-22 05:00:39 +0000[diff] [blame]1745 { X86::VANDPDZ128rr, X86::VANDPDZ128rm, 0 },
1746 { X86::VANDPDZ256rr, X86::VANDPDZ256rm, 0 },
1747 { X86::VANDPSZ128rr, X86::VANDPSZ128rm, 0 },
1748 { X86::VANDPSZ256rr, X86::VANDPSZ256rm, 0 },
1749 { X86::VANDNPDZ128rr, X86::VANDNPDZ128rm, 0 },
1750 { X86::VANDNPDZ256rr, X86::VANDNPDZ256rm, 0 },
1751 { X86::VANDNPSZ128rr, X86::VANDNPSZ128rm, 0 },
1752 { X86::VANDNPSZ256rr, X86::VANDNPSZ256rm, 0 },
1753 { X86::VORPDZ128rr, X86::VORPDZ128rm, 0 },
1754 { X86::VORPDZ256rr, X86::VORPDZ256rm, 0 },
1755 { X86::VORPSZ128rr, X86::VORPSZ128rm, 0 },
1756 { X86::VORPSZ256rr, X86::VORPSZ256rm, 0 },
1757 { X86::VPANDDZ128rr, X86::VPANDDZ128rm, 0 },
1758 { X86::VPANDDZ256rr, X86::VPANDDZ256rm, 0 },
1759 { X86::VPANDQZ128rr, X86::VPANDQZ128rm, 0 },
1760 { X86::VPANDQZ256rr, X86::VPANDQZ256rm, 0 },
1761 { X86::VPANDNDZ128rr, X86::VPANDNDZ128rm, 0 },
1762 { X86::VPANDNDZ256rr, X86::VPANDNDZ256rm, 0 },
1763 { X86::VPANDNQZ128rr, X86::VPANDNQZ128rm, 0 },
1764 { X86::VPANDNQZ256rr, X86::VPANDNQZ256rm, 0 },
1765 { X86::VPORDZ128rr, X86::VPORDZ128rm, 0 },
1766 { X86::VPORDZ256rr, X86::VPORDZ256rm, 0 },
1767 { X86::VPORQZ128rr, X86::VPORQZ128rm, 0 },
1768 { X86::VPORQZ256rr, X86::VPORQZ256rm, 0 },
1769 { X86::VPXORDZ128rr, X86::VPXORDZ128rm, 0 },
1770 { X86::VPXORDZ256rr, X86::VPXORDZ256rm, 0 },
1771 { X86::VPXORQZ128rr, X86::VPXORQZ128rm, 0 },
1772 { X86::VPXORQZ256rr, X86::VPXORQZ256rm, 0 },
1773 { X86::VSUBPDZ128rr, X86::VSUBPDZ128rm, 0 },
1774 { X86::VSUBPDZ256rr, X86::VSUBPDZ256rm, 0 },
1775 { X86::VSUBPSZ128rr, X86::VSUBPSZ128rm, 0 },
1776 { X86::VSUBPSZ256rr, X86::VSUBPSZ256rm, 0 },
1777 { X86::VXORPDZ128rr, X86::VXORPDZ128rm, 0 },
1778 { X86::VXORPDZ256rr, X86::VXORPDZ256rm, 0 },
1779 { X86::VXORPSZ128rr, X86::VXORPSZ128rm, 0 },
1780 { X86::VXORPSZ256rr, X86::VXORPSZ256rm, 0 },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1781
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1782 // AES foldable instructions
1783 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1784 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1785 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1786 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1787 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1788 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1789 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1790 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1791
1792 // SHA foldable instructions
1793 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1794 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1795 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1796 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1797 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1798 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1799 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1800 };
1801
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1802 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1803 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1804 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1805 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1806 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1807 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1808
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1809 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1810 // FMA foldable instructions
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1811 { X86::VFMADD231SSr, X86::VFMADD231SSm, TB_ALIGN_NONE },
1812 { X86::VFMADD231SSr_Int, X86::VFMADD231SSm_Int, TB_ALIGN_NONE },
1813 { X86::VFMADD231SDr, X86::VFMADD231SDm, TB_ALIGN_NONE },
1814 { X86::VFMADD231SDr_Int, X86::VFMADD231SDm_Int, TB_ALIGN_NONE },
1815 { X86::VFMADD132SSr, X86::VFMADD132SSm, TB_ALIGN_NONE },
1816 { X86::VFMADD132SSr_Int, X86::VFMADD132SSm_Int, TB_ALIGN_NONE },
1817 { X86::VFMADD132SDr, X86::VFMADD132SDm, TB_ALIGN_NONE },
1818 { X86::VFMADD132SDr_Int, X86::VFMADD132SDm_Int, TB_ALIGN_NONE },
1819 { X86::VFMADD213SSr, X86::VFMADD213SSm, TB_ALIGN_NONE },
1820 { X86::VFMADD213SSr_Int, X86::VFMADD213SSm_Int, TB_ALIGN_NONE },
1821 { X86::VFMADD213SDr, X86::VFMADD213SDm, TB_ALIGN_NONE },
1822 { X86::VFMADD213SDr_Int, X86::VFMADD213SDm_Int, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]1823 { X86::VFMADD231SSZr, X86::VFMADD231SSZm, TB_ALIGN_NONE },
1824 { X86::VFMADD231SSZr_Int, X86::VFMADD231SSZm_Int, TB_ALIGN_NONE },
1825 { X86::VFMADD231SDZr, X86::VFMADD231SDZm, TB_ALIGN_NONE },
1826 { X86::VFMADD231SDZr_Int, X86::VFMADD231SDZm_Int, TB_ALIGN_NONE },
1827 { X86::VFMADD132SSZr, X86::VFMADD132SSZm, TB_ALIGN_NONE },
1828 { X86::VFMADD132SSZr_Int, X86::VFMADD132SSZm_Int, TB_ALIGN_NONE },
1829 { X86::VFMADD132SDZr, X86::VFMADD132SDZm, TB_ALIGN_NONE },
1830 { X86::VFMADD132SDZr_Int, X86::VFMADD132SDZm_Int, TB_ALIGN_NONE },
1831 { X86::VFMADD213SSZr, X86::VFMADD213SSZm, TB_ALIGN_NONE },
1832 { X86::VFMADD213SSZr_Int, X86::VFMADD213SSZm_Int, TB_ALIGN_NONE },
1833 { X86::VFMADD213SDZr, X86::VFMADD213SDZm, TB_ALIGN_NONE },
1834 { X86::VFMADD213SDZr_Int, X86::VFMADD213SDZm_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1835
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1836 { X86::VFMADD231PSr, X86::VFMADD231PSm, TB_ALIGN_NONE },
1837 { X86::VFMADD231PDr, X86::VFMADD231PDm, TB_ALIGN_NONE },
1838 { X86::VFMADD132PSr, X86::VFMADD132PSm, TB_ALIGN_NONE },
1839 { X86::VFMADD132PDr, X86::VFMADD132PDm, TB_ALIGN_NONE },
1840 { X86::VFMADD213PSr, X86::VFMADD213PSm, TB_ALIGN_NONE },
1841 { X86::VFMADD213PDr, X86::VFMADD213PDm, TB_ALIGN_NONE },
1842 { X86::VFMADD231PSYr, X86::VFMADD231PSYm, TB_ALIGN_NONE },
1843 { X86::VFMADD231PDYr, X86::VFMADD231PDYm, TB_ALIGN_NONE },
1844 { X86::VFMADD132PSYr, X86::VFMADD132PSYm, TB_ALIGN_NONE },
1845 { X86::VFMADD132PDYr, X86::VFMADD132PDYm, TB_ALIGN_NONE },
1846 { X86::VFMADD213PSYr, X86::VFMADD213PSYm, TB_ALIGN_NONE },
1847 { X86::VFMADD213PDYr, X86::VFMADD213PDYm, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]1848 { X86::VFMADD231PSZr, X86::VFMADD231PSZm, TB_ALIGN_NONE },
1849 { X86::VFMADD231PDZr, X86::VFMADD231PDZm, TB_ALIGN_NONE },
1850 { X86::VFMADD132PSZr, X86::VFMADD132PSZm, TB_ALIGN_NONE },
1851 { X86::VFMADD132PDZr, X86::VFMADD132PDZm, TB_ALIGN_NONE },
1852 { X86::VFMADD213PSZr, X86::VFMADD213PSZm, TB_ALIGN_NONE },
1853 { X86::VFMADD213PDZr, X86::VFMADD213PDZm, TB_ALIGN_NONE },
1854 { X86::VFMADD231PSZ128r, X86::VFMADD231PSZ128m, TB_ALIGN_NONE },
1855 { X86::VFMADD231PDZ128r, X86::VFMADD231PDZ128m, TB_ALIGN_NONE },
1856 { X86::VFMADD132PSZ128r, X86::VFMADD132PSZ128m, TB_ALIGN_NONE },
1857 { X86::VFMADD132PDZ128r, X86::VFMADD132PDZ128m, TB_ALIGN_NONE },
1858 { X86::VFMADD213PSZ128r, X86::VFMADD213PSZ128m, TB_ALIGN_NONE },
1859 { X86::VFMADD213PDZ128r, X86::VFMADD213PDZ128m, TB_ALIGN_NONE },
1860 { X86::VFMADD231PSZ256r, X86::VFMADD231PSZ256m, TB_ALIGN_NONE },
1861 { X86::VFMADD231PDZ256r, X86::VFMADD231PDZ256m, TB_ALIGN_NONE },
1862 { X86::VFMADD132PSZ256r, X86::VFMADD132PSZ256m, TB_ALIGN_NONE },
1863 { X86::VFMADD132PDZ256r, X86::VFMADD132PDZ256m, TB_ALIGN_NONE },
1864 { X86::VFMADD213PSZ256r, X86::VFMADD213PSZ256m, TB_ALIGN_NONE },
1865 { X86::VFMADD213PDZ256r, X86::VFMADD213PDZ256m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1866
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1867 { X86::VFNMADD231SSr, X86::VFNMADD231SSm, TB_ALIGN_NONE },
1868 { X86::VFNMADD231SSr_Int, X86::VFNMADD231SSm_Int, TB_ALIGN_NONE },
1869 { X86::VFNMADD231SDr, X86::VFNMADD231SDm, TB_ALIGN_NONE },
1870 { X86::VFNMADD231SDr_Int, X86::VFNMADD231SDm_Int, TB_ALIGN_NONE },
1871 { X86::VFNMADD132SSr, X86::VFNMADD132SSm, TB_ALIGN_NONE },
1872 { X86::VFNMADD132SSr_Int, X86::VFNMADD132SSm_Int, TB_ALIGN_NONE },
1873 { X86::VFNMADD132SDr, X86::VFNMADD132SDm, TB_ALIGN_NONE },
1874 { X86::VFNMADD132SDr_Int, X86::VFNMADD132SDm_Int, TB_ALIGN_NONE },
1875 { X86::VFNMADD213SSr, X86::VFNMADD213SSm, TB_ALIGN_NONE },
1876 { X86::VFNMADD213SSr_Int, X86::VFNMADD213SSm_Int, TB_ALIGN_NONE },
1877 { X86::VFNMADD213SDr, X86::VFNMADD213SDm, TB_ALIGN_NONE },
1878 { X86::VFNMADD213SDr_Int, X86::VFNMADD213SDm_Int, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]1879 { X86::VFNMADD231SSZr, X86::VFNMADD231SSZm, TB_ALIGN_NONE },
1880 { X86::VFNMADD231SSZr_Int, X86::VFNMADD231SSZm_Int, TB_ALIGN_NONE },
1881 { X86::VFNMADD231SDZr, X86::VFNMADD231SDZm, TB_ALIGN_NONE },
1882 { X86::VFNMADD231SDZr_Int, X86::VFNMADD231SDZm_Int, TB_ALIGN_NONE },
1883 { X86::VFNMADD132SSZr, X86::VFNMADD132SSZm, TB_ALIGN_NONE },
1884 { X86::VFNMADD132SSZr_Int, X86::VFNMADD132SSZm_Int, TB_ALIGN_NONE },
1885 { X86::VFNMADD132SDZr, X86::VFNMADD132SDZm, TB_ALIGN_NONE },
1886 { X86::VFNMADD132SDZr_Int, X86::VFNMADD132SDZm_Int, TB_ALIGN_NONE },
1887 { X86::VFNMADD213SSZr, X86::VFNMADD213SSZm, TB_ALIGN_NONE },
1888 { X86::VFNMADD213SSZr_Int, X86::VFNMADD213SSZm_Int, TB_ALIGN_NONE },
1889 { X86::VFNMADD213SDZr, X86::VFNMADD213SDZm, TB_ALIGN_NONE },
1890 { X86::VFNMADD213SDZr_Int, X86::VFNMADD213SDZm_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1891
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1892 { X86::VFNMADD231PSr, X86::VFNMADD231PSm, TB_ALIGN_NONE },
1893 { X86::VFNMADD231PDr, X86::VFNMADD231PDm, TB_ALIGN_NONE },
1894 { X86::VFNMADD132PSr, X86::VFNMADD132PSm, TB_ALIGN_NONE },
1895 { X86::VFNMADD132PDr, X86::VFNMADD132PDm, TB_ALIGN_NONE },
1896 { X86::VFNMADD213PSr, X86::VFNMADD213PSm, TB_ALIGN_NONE },
1897 { X86::VFNMADD213PDr, X86::VFNMADD213PDm, TB_ALIGN_NONE },
1898 { X86::VFNMADD231PSYr, X86::VFNMADD231PSYm, TB_ALIGN_NONE },
1899 { X86::VFNMADD231PDYr, X86::VFNMADD231PDYm, TB_ALIGN_NONE },
1900 { X86::VFNMADD132PSYr, X86::VFNMADD132PSYm, TB_ALIGN_NONE },
1901 { X86::VFNMADD132PDYr, X86::VFNMADD132PDYm, TB_ALIGN_NONE },
1902 { X86::VFNMADD213PSYr, X86::VFNMADD213PSYm, TB_ALIGN_NONE },
1903 { X86::VFNMADD213PDYr, X86::VFNMADD213PDYm, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]1904 { X86::VFNMADD231PSZr, X86::VFNMADD231PSZm, TB_ALIGN_NONE },
1905 { X86::VFNMADD231PDZr, X86::VFNMADD231PDZm, TB_ALIGN_NONE },
1906 { X86::VFNMADD132PSZr, X86::VFNMADD132PSZm, TB_ALIGN_NONE },
1907 { X86::VFNMADD132PDZr, X86::VFNMADD132PDZm, TB_ALIGN_NONE },
1908 { X86::VFNMADD213PSZr, X86::VFNMADD213PSZm, TB_ALIGN_NONE },
1909 { X86::VFNMADD213PDZr, X86::VFNMADD213PDZm, TB_ALIGN_NONE },
1910 { X86::VFNMADD231PSZ128r, X86::VFNMADD231PSZ128m, TB_ALIGN_NONE },
1911 { X86::VFNMADD231PDZ128r, X86::VFNMADD231PDZ128m, TB_ALIGN_NONE },
1912 { X86::VFNMADD132PSZ128r, X86::VFNMADD132PSZ128m, TB_ALIGN_NONE },
1913 { X86::VFNMADD132PDZ128r, X86::VFNMADD132PDZ128m, TB_ALIGN_NONE },
1914 { X86::VFNMADD213PSZ128r, X86::VFNMADD213PSZ128m, TB_ALIGN_NONE },
1915 { X86::VFNMADD213PDZ128r, X86::VFNMADD213PDZ128m, TB_ALIGN_NONE },
1916 { X86::VFNMADD231PSZ256r, X86::VFNMADD231PSZ256m, TB_ALIGN_NONE },
1917 { X86::VFNMADD231PDZ256r, X86::VFNMADD231PDZ256m, TB_ALIGN_NONE },
1918 { X86::VFNMADD132PSZ256r, X86::VFNMADD132PSZ256m, TB_ALIGN_NONE },
1919 { X86::VFNMADD132PDZ256r, X86::VFNMADD132PDZ256m, TB_ALIGN_NONE },
1920 { X86::VFNMADD213PSZ256r, X86::VFNMADD213PSZ256m, TB_ALIGN_NONE },
1921 { X86::VFNMADD213PDZ256r, X86::VFNMADD213PDZ256m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1922
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1923 { X86::VFMSUB231SSr, X86::VFMSUB231SSm, TB_ALIGN_NONE },
1924 { X86::VFMSUB231SSr_Int, X86::VFMSUB231SSm_Int, TB_ALIGN_NONE },
1925 { X86::VFMSUB231SDr, X86::VFMSUB231SDm, TB_ALIGN_NONE },
1926 { X86::VFMSUB231SDr_Int, X86::VFMSUB231SDm_Int, TB_ALIGN_NONE },
1927 { X86::VFMSUB132SSr, X86::VFMSUB132SSm, TB_ALIGN_NONE },
1928 { X86::VFMSUB132SSr_Int, X86::VFMSUB132SSm_Int, TB_ALIGN_NONE },
1929 { X86::VFMSUB132SDr, X86::VFMSUB132SDm, TB_ALIGN_NONE },
1930 { X86::VFMSUB132SDr_Int, X86::VFMSUB132SDm_Int, TB_ALIGN_NONE },
1931 { X86::VFMSUB213SSr, X86::VFMSUB213SSm, TB_ALIGN_NONE },
1932 { X86::VFMSUB213SSr_Int, X86::VFMSUB213SSm_Int, TB_ALIGN_NONE },
1933 { X86::VFMSUB213SDr, X86::VFMSUB213SDm, TB_ALIGN_NONE },
1934 { X86::VFMSUB213SDr_Int, X86::VFMSUB213SDm_Int, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]1935 { X86::VFMSUB231SSZr, X86::VFMSUB231SSZm, TB_ALIGN_NONE },
1936 { X86::VFMSUB231SSZr_Int, X86::VFMSUB231SSZm_Int, TB_ALIGN_NONE },
1937 { X86::VFMSUB231SDZr, X86::VFMSUB231SDZm, TB_ALIGN_NONE },
1938 { X86::VFMSUB231SDZr_Int, X86::VFMSUB231SDZm_Int, TB_ALIGN_NONE },
1939 { X86::VFMSUB132SSZr, X86::VFMSUB132SSZm, TB_ALIGN_NONE },
1940 { X86::VFMSUB132SSZr_Int, X86::VFMSUB132SSZm_Int, TB_ALIGN_NONE },
1941 { X86::VFMSUB132SDZr, X86::VFMSUB132SDZm, TB_ALIGN_NONE },
1942 { X86::VFMSUB132SDZr_Int, X86::VFMSUB132SDZm_Int, TB_ALIGN_NONE },
1943 { X86::VFMSUB213SSZr, X86::VFMSUB213SSZm, TB_ALIGN_NONE },
1944 { X86::VFMSUB213SSZr_Int, X86::VFMSUB213SSZm_Int, TB_ALIGN_NONE },
1945 { X86::VFMSUB213SDZr, X86::VFMSUB213SDZm, TB_ALIGN_NONE },
1946 { X86::VFMSUB213SDZr_Int, X86::VFMSUB213SDZm_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1947
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1948 { X86::VFMSUB231PSr, X86::VFMSUB231PSm, TB_ALIGN_NONE },
1949 { X86::VFMSUB231PDr, X86::VFMSUB231PDm, TB_ALIGN_NONE },
1950 { X86::VFMSUB132PSr, X86::VFMSUB132PSm, TB_ALIGN_NONE },
1951 { X86::VFMSUB132PDr, X86::VFMSUB132PDm, TB_ALIGN_NONE },
1952 { X86::VFMSUB213PSr, X86::VFMSUB213PSm, TB_ALIGN_NONE },
1953 { X86::VFMSUB213PDr, X86::VFMSUB213PDm, TB_ALIGN_NONE },
1954 { X86::VFMSUB231PSYr, X86::VFMSUB231PSYm, TB_ALIGN_NONE },
1955 { X86::VFMSUB231PDYr, X86::VFMSUB231PDYm, TB_ALIGN_NONE },
1956 { X86::VFMSUB132PSYr, X86::VFMSUB132PSYm, TB_ALIGN_NONE },
1957 { X86::VFMSUB132PDYr, X86::VFMSUB132PDYm, TB_ALIGN_NONE },
1958 { X86::VFMSUB213PSYr, X86::VFMSUB213PSYm, TB_ALIGN_NONE },
1959 { X86::VFMSUB213PDYr, X86::VFMSUB213PDYm, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]1960 { X86::VFMSUB231PSZr, X86::VFMSUB231PSZm, TB_ALIGN_NONE },
1961 { X86::VFMSUB231PDZr, X86::VFMSUB231PDZm, TB_ALIGN_NONE },
1962 { X86::VFMSUB132PSZr, X86::VFMSUB132PSZm, TB_ALIGN_NONE },
1963 { X86::VFMSUB132PDZr, X86::VFMSUB132PDZm, TB_ALIGN_NONE },
1964 { X86::VFMSUB213PSZr, X86::VFMSUB213PSZm, TB_ALIGN_NONE },
1965 { X86::VFMSUB213PDZr, X86::VFMSUB213PDZm, TB_ALIGN_NONE },
1966 { X86::VFMSUB231PSZ128r, X86::VFMSUB231PSZ128m, TB_ALIGN_NONE },
1967 { X86::VFMSUB231PDZ128r, X86::VFMSUB231PDZ128m, TB_ALIGN_NONE },
1968 { X86::VFMSUB132PSZ128r, X86::VFMSUB132PSZ128m, TB_ALIGN_NONE },
1969 { X86::VFMSUB132PDZ128r, X86::VFMSUB132PDZ128m, TB_ALIGN_NONE },
1970 { X86::VFMSUB213PSZ128r, X86::VFMSUB213PSZ128m, TB_ALIGN_NONE },
1971 { X86::VFMSUB213PDZ128r, X86::VFMSUB213PDZ128m, TB_ALIGN_NONE },
1972 { X86::VFMSUB231PSZ256r, X86::VFMSUB231PSZ256m, TB_ALIGN_NONE },
1973 { X86::VFMSUB231PDZ256r, X86::VFMSUB231PDZ256m, TB_ALIGN_NONE },
1974 { X86::VFMSUB132PSZ256r, X86::VFMSUB132PSZ256m, TB_ALIGN_NONE },
1975 { X86::VFMSUB132PDZ256r, X86::VFMSUB132PDZ256m, TB_ALIGN_NONE },
1976 { X86::VFMSUB213PSZ256r, X86::VFMSUB213PSZ256m, TB_ALIGN_NONE },
1977 { X86::VFMSUB213PDZ256r, X86::VFMSUB213PDZ256m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1978
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1979 { X86::VFNMSUB231SSr, X86::VFNMSUB231SSm, TB_ALIGN_NONE },
1980 { X86::VFNMSUB231SSr_Int, X86::VFNMSUB231SSm_Int, TB_ALIGN_NONE },
1981 { X86::VFNMSUB231SDr, X86::VFNMSUB231SDm, TB_ALIGN_NONE },
1982 { X86::VFNMSUB231SDr_Int, X86::VFNMSUB231SDm_Int, TB_ALIGN_NONE },
1983 { X86::VFNMSUB132SSr, X86::VFNMSUB132SSm, TB_ALIGN_NONE },
1984 { X86::VFNMSUB132SSr_Int, X86::VFNMSUB132SSm_Int, TB_ALIGN_NONE },
1985 { X86::VFNMSUB132SDr, X86::VFNMSUB132SDm, TB_ALIGN_NONE },
1986 { X86::VFNMSUB132SDr_Int, X86::VFNMSUB132SDm_Int, TB_ALIGN_NONE },
1987 { X86::VFNMSUB213SSr, X86::VFNMSUB213SSm, TB_ALIGN_NONE },
1988 { X86::VFNMSUB213SSr_Int, X86::VFNMSUB213SSm_Int, TB_ALIGN_NONE },
1989 { X86::VFNMSUB213SDr, X86::VFNMSUB213SDm, TB_ALIGN_NONE },
1990 { X86::VFNMSUB213SDr_Int, X86::VFNMSUB213SDm_Int, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1991
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]1992 { X86::VFNMSUB231PSr, X86::VFNMSUB231PSm, TB_ALIGN_NONE },
1993 { X86::VFNMSUB231PDr, X86::VFNMSUB231PDm, TB_ALIGN_NONE },
1994 { X86::VFNMSUB132PSr, X86::VFNMSUB132PSm, TB_ALIGN_NONE },
1995 { X86::VFNMSUB132PDr, X86::VFNMSUB132PDm, TB_ALIGN_NONE },
1996 { X86::VFNMSUB213PSr, X86::VFNMSUB213PSm, TB_ALIGN_NONE },
1997 { X86::VFNMSUB213PDr, X86::VFNMSUB213PDm, TB_ALIGN_NONE },
1998 { X86::VFNMSUB231PSYr, X86::VFNMSUB231PSYm, TB_ALIGN_NONE },
1999 { X86::VFNMSUB231PDYr, X86::VFNMSUB231PDYm, TB_ALIGN_NONE },
2000 { X86::VFNMSUB132PSYr, X86::VFNMSUB132PSYm, TB_ALIGN_NONE },
2001 { X86::VFNMSUB132PDYr, X86::VFNMSUB132PDYm, TB_ALIGN_NONE },
2002 { X86::VFNMSUB213PSYr, X86::VFNMSUB213PSYm, TB_ALIGN_NONE },
2003 { X86::VFNMSUB213PDYr, X86::VFNMSUB213PDYm, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]2004 { X86::VFNMSUB231PSZr, X86::VFNMSUB231PSZm, TB_ALIGN_NONE },
2005 { X86::VFNMSUB231PDZr, X86::VFNMSUB231PDZm, TB_ALIGN_NONE },
2006 { X86::VFNMSUB132PSZr, X86::VFNMSUB132PSZm, TB_ALIGN_NONE },
2007 { X86::VFNMSUB132PDZr, X86::VFNMSUB132PDZm, TB_ALIGN_NONE },
2008 { X86::VFNMSUB213PSZr, X86::VFNMSUB213PSZm, TB_ALIGN_NONE },
2009 { X86::VFNMSUB213PDZr, X86::VFNMSUB213PDZm, TB_ALIGN_NONE },
2010 { X86::VFNMSUB231PSZ128r, X86::VFNMSUB231PSZ128m, TB_ALIGN_NONE },
2011 { X86::VFNMSUB231PDZ128r, X86::VFNMSUB231PDZ128m, TB_ALIGN_NONE },
2012 { X86::VFNMSUB132PSZ128r, X86::VFNMSUB132PSZ128m, TB_ALIGN_NONE },
2013 { X86::VFNMSUB132PDZ128r, X86::VFNMSUB132PDZ128m, TB_ALIGN_NONE },
2014 { X86::VFNMSUB213PSZ128r, X86::VFNMSUB213PSZ128m, TB_ALIGN_NONE },
2015 { X86::VFNMSUB213PDZ128r, X86::VFNMSUB213PDZ128m, TB_ALIGN_NONE },
2016 { X86::VFNMSUB231PSZ256r, X86::VFNMSUB231PSZ256m, TB_ALIGN_NONE },
2017 { X86::VFNMSUB231PDZ256r, X86::VFNMSUB231PDZ256m, TB_ALIGN_NONE },
2018 { X86::VFNMSUB132PSZ256r, X86::VFNMSUB132PSZ256m, TB_ALIGN_NONE },
2019 { X86::VFNMSUB132PDZ256r, X86::VFNMSUB132PDZ256m, TB_ALIGN_NONE },
2020 { X86::VFNMSUB213PSZ256r, X86::VFNMSUB213PSZ256m, TB_ALIGN_NONE },
2021 { X86::VFNMSUB213PDZ256r, X86::VFNMSUB213PDZ256m, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]2022
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2023 { X86::VFMADDSUB231PSr, X86::VFMADDSUB231PSm, TB_ALIGN_NONE },
2024 { X86::VFMADDSUB231PDr, X86::VFMADDSUB231PDm, TB_ALIGN_NONE },
2025 { X86::VFMADDSUB132PSr, X86::VFMADDSUB132PSm, TB_ALIGN_NONE },
2026 { X86::VFMADDSUB132PDr, X86::VFMADDSUB132PDm, TB_ALIGN_NONE },
2027 { X86::VFMADDSUB213PSr, X86::VFMADDSUB213PSm, TB_ALIGN_NONE },
2028 { X86::VFMADDSUB213PDr, X86::VFMADDSUB213PDm, TB_ALIGN_NONE },
2029 { X86::VFMADDSUB231PSYr, X86::VFMADDSUB231PSYm, TB_ALIGN_NONE },
2030 { X86::VFMADDSUB231PDYr, X86::VFMADDSUB231PDYm, TB_ALIGN_NONE },
2031 { X86::VFMADDSUB132PSYr, X86::VFMADDSUB132PSYm, TB_ALIGN_NONE },
2032 { X86::VFMADDSUB132PDYr, X86::VFMADDSUB132PDYm, TB_ALIGN_NONE },
2033 { X86::VFMADDSUB213PSYr, X86::VFMADDSUB213PSYm, TB_ALIGN_NONE },
2034 { X86::VFMADDSUB213PDYr, X86::VFMADDSUB213PDYm, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]2035 { X86::VFMADDSUB231PSZr, X86::VFMADDSUB231PSZm, TB_ALIGN_NONE },
2036 { X86::VFMADDSUB231PDZr, X86::VFMADDSUB231PDZm, TB_ALIGN_NONE },
2037 { X86::VFMADDSUB132PSZr, X86::VFMADDSUB132PSZm, TB_ALIGN_NONE },
2038 { X86::VFMADDSUB132PDZr, X86::VFMADDSUB132PDZm, TB_ALIGN_NONE },
2039 { X86::VFMADDSUB213PSZr, X86::VFMADDSUB213PSZm, TB_ALIGN_NONE },
2040 { X86::VFMADDSUB213PDZr, X86::VFMADDSUB213PDZm, TB_ALIGN_NONE },
2041 { X86::VFMADDSUB231PSZ128r, X86::VFMADDSUB231PSZ128m, TB_ALIGN_NONE },
2042 { X86::VFMADDSUB231PDZ128r, X86::VFMADDSUB231PDZ128m, TB_ALIGN_NONE },
2043 { X86::VFMADDSUB132PSZ128r, X86::VFMADDSUB132PSZ128m, TB_ALIGN_NONE },
2044 { X86::VFMADDSUB132PDZ128r, X86::VFMADDSUB132PDZ128m, TB_ALIGN_NONE },
2045 { X86::VFMADDSUB213PSZ128r, X86::VFMADDSUB213PSZ128m, TB_ALIGN_NONE },
2046 { X86::VFMADDSUB213PDZ128r, X86::VFMADDSUB213PDZ128m, TB_ALIGN_NONE },
2047 { X86::VFMADDSUB231PSZ256r, X86::VFMADDSUB231PSZ256m, TB_ALIGN_NONE },
2048 { X86::VFMADDSUB231PDZ256r, X86::VFMADDSUB231PDZ256m, TB_ALIGN_NONE },
2049 { X86::VFMADDSUB132PSZ256r, X86::VFMADDSUB132PSZ256m, TB_ALIGN_NONE },
2050 { X86::VFMADDSUB132PDZ256r, X86::VFMADDSUB132PDZ256m, TB_ALIGN_NONE },
2051 { X86::VFMADDSUB213PSZ256r, X86::VFMADDSUB213PSZ256m, TB_ALIGN_NONE },
2052 { X86::VFMADDSUB213PDZ256r, X86::VFMADDSUB213PDZ256m, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]2053
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2054 { X86::VFMSUBADD231PSr, X86::VFMSUBADD231PSm, TB_ALIGN_NONE },
2055 { X86::VFMSUBADD231PDr, X86::VFMSUBADD231PDm, TB_ALIGN_NONE },
2056 { X86::VFMSUBADD132PSr, X86::VFMSUBADD132PSm, TB_ALIGN_NONE },
2057 { X86::VFMSUBADD132PDr, X86::VFMSUBADD132PDm, TB_ALIGN_NONE },
2058 { X86::VFMSUBADD213PSr, X86::VFMSUBADD213PSm, TB_ALIGN_NONE },
2059 { X86::VFMSUBADD213PDr, X86::VFMSUBADD213PDm, TB_ALIGN_NONE },
2060 { X86::VFMSUBADD231PSYr, X86::VFMSUBADD231PSYm, TB_ALIGN_NONE },
2061 { X86::VFMSUBADD231PDYr, X86::VFMSUBADD231PDYm, TB_ALIGN_NONE },
2062 { X86::VFMSUBADD132PSYr, X86::VFMSUBADD132PSYm, TB_ALIGN_NONE },
2063 { X86::VFMSUBADD132PDYr, X86::VFMSUBADD132PDYm, TB_ALIGN_NONE },
2064 { X86::VFMSUBADD213PSYr, X86::VFMSUBADD213PSYm, TB_ALIGN_NONE },
2065 { X86::VFMSUBADD213PDYr, X86::VFMSUBADD213PDYm, TB_ALIGN_NONE },
Craig Topperce415ff2016-07-25 07:20:35 +0000[diff] [blame]2066 { X86::VFMSUBADD231PSZr, X86::VFMSUBADD231PSZm, TB_ALIGN_NONE },
2067 { X86::VFMSUBADD231PDZr, X86::VFMSUBADD231PDZm, TB_ALIGN_NONE },
2068 { X86::VFMSUBADD132PSZr, X86::VFMSUBADD132PSZm, TB_ALIGN_NONE },
2069 { X86::VFMSUBADD132PDZr, X86::VFMSUBADD132PDZm, TB_ALIGN_NONE },
2070 { X86::VFMSUBADD213PSZr, X86::VFMSUBADD213PSZm, TB_ALIGN_NONE },
2071 { X86::VFMSUBADD213PDZr, X86::VFMSUBADD213PDZm, TB_ALIGN_NONE },
2072 { X86::VFMSUBADD231PSZ128r, X86::VFMSUBADD231PSZ128m, TB_ALIGN_NONE },
2073 { X86::VFMSUBADD231PDZ128r, X86::VFMSUBADD231PDZ128m, TB_ALIGN_NONE },
2074 { X86::VFMSUBADD132PSZ128r, X86::VFMSUBADD132PSZ128m, TB_ALIGN_NONE },
2075 { X86::VFMSUBADD132PDZ128r, X86::VFMSUBADD132PDZ128m, TB_ALIGN_NONE },
2076 { X86::VFMSUBADD213PSZ128r, X86::VFMSUBADD213PSZ128m, TB_ALIGN_NONE },
2077 { X86::VFMSUBADD213PDZ128r, X86::VFMSUBADD213PDZ128m, TB_ALIGN_NONE },
2078 { X86::VFMSUBADD231PSZ256r, X86::VFMSUBADD231PSZ256m, TB_ALIGN_NONE },
2079 { X86::VFMSUBADD231PDZ256r, X86::VFMSUBADD231PDZ256m, TB_ALIGN_NONE },
2080 { X86::VFMSUBADD132PSZ256r, X86::VFMSUBADD132PSZ256m, TB_ALIGN_NONE },
2081 { X86::VFMSUBADD132PDZ256r, X86::VFMSUBADD132PDZ256m, TB_ALIGN_NONE },
2082 { X86::VFMSUBADD213PSZ256r, X86::VFMSUBADD213PSZ256m, TB_ALIGN_NONE },
2083 { X86::VFMSUBADD213PDZ256r, X86::VFMSUBADD213PDZ256m, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]2084
2085 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]2086 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
2087 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
2088 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
2089 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2090 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Yrm, TB_ALIGN_NONE },
2091 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]2092 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
2093 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
2094 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
2095 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2096 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Yrm, TB_ALIGN_NONE },
2097 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]2098 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
2099 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
2100 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
2101 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2102 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Yrm, TB_ALIGN_NONE },
2103 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]2104 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
2105 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
2106 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
2107 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2108 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Yrm, TB_ALIGN_NONE },
2109 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]2110 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
2111 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2112 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Yrm, TB_ALIGN_NONE },
2113 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]2114 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
2115 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]2116 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Yrm, TB_ALIGN_NONE },
2117 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Yrm, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2118
2119 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]2120 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
2121 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2122 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
2123 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
2124 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
2125 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]2126 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2127
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2128 // AVX-512 VPERMI instructions with 3 source operands.
2129 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
2130 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
2131 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
2132 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2133 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
2134 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
2135 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]2136 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
2137 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
2138 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
2139 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
2140 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2141 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
2142 // AVX-512 arithmetic instructions
2143 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
2144 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
2145 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
2146 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
2147 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
2148 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
2149 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
2150 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
2151 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
2152 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
2153 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
2154 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
2155 // AVX-512{F,VL} arithmetic instructions 256-bit
2156 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
2157 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
2158 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
2159 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
2160 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
2161 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
2162 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
2163 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
2164 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
2165 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
2166 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
2167 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
2168 // AVX-512{F,VL} arithmetic instructions 128-bit
2169 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
2170 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
2171 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
2172 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
2173 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
2174 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
2175 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
2176 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
2177 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
2178 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
2179 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
2180 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2181 };
2182
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2183 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2184 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2185 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2186 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2187 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]2188 }
2189
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]2190 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2191 // AVX-512 foldable instructions
2192 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
2193 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
2194 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2195 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2196 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2197 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2198 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2199 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2200 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2201 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
2202 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2203 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
2204 // AVX-512{F,VL} foldable instructions 256-bit
2205 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2206 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2207 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2208 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2209 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2210 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2211 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2212 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2213 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2214 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2215 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2216 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2217 // AVX-512{F,VL} foldable instructions 128-bit
2218 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2219 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2220 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2221 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2222 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2223 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2224 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2225 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2226 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2227 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2228 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2229 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2230 };
2231
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2232 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2233 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2234 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2235 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2236 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2237 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2238}
2239
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2240void
2241X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2242 MemOp2RegOpTableType &M2RTable,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]2243 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2244 if ((Flags & TB_NO_FORWARD) == 0) {
2245 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2246 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2247 }
2248 if ((Flags & TB_NO_REVERSE) == 0) {
2249 assert(!M2RTable.count(MemOp) &&
2250 "Duplicated entries in unfolding maps?");
2251 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2252 }
2253}
2254
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2255bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2256X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2257 unsigned &SrcReg, unsigned &DstReg,
2258 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2259 switch (MI.getOpcode()) {
2260 default: break;
2261 case X86::MOVSX16rr8:
2262 case X86::MOVZX16rr8:
2263 case X86::MOVSX32rr8:
2264 case X86::MOVZX32rr8:
2265 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2266 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2267 // It's not always legal to reference the low 8-bit of the larger
2268 // register in 32-bit mode.
2269 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2270 case X86::MOVSX32rr16:
2271 case X86::MOVZX32rr16:
2272 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2273 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2274 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2275 // Be conservative.
2276 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2277 SrcReg = MI.getOperand(1).getReg();
2278 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2279 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2280 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2281 case X86::MOVSX16rr8:
2282 case X86::MOVZX16rr8:
2283 case X86::MOVSX32rr8:
2284 case X86::MOVZX32rr8:
2285 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2286 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2287 break;
2288 case X86::MOVSX32rr16:
2289 case X86::MOVZX32rr16:
2290 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2291 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2292 break;
2293 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2294 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2295 break;
2296 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2297 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2298 }
2299 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2300 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2301}
2302
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2303int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2304 const MachineFunction *MF = MI.getParent()->getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2305 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2306
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2307 if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2308 MI.getOpcode() == getCallFrameDestroyOpcode()) {
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2309 unsigned StackAlign = TFI->getStackAlignment();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2310 int SPAdj =
2311 (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2312
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2313 SPAdj -= MI.getOperand(1).getImm();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2314
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2315 if (MI.getOpcode() == getCallFrameSetupOpcode())
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2316 return SPAdj;
2317 else
2318 return -SPAdj;
2319 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2320
2321 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2322 // that is bound to the following ADJCALLSTACKUP pseudo.
2323 // Look for the next ADJCALLSTACKUP that follows the call.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2324 if (MI.isCall()) {
2325 const MachineBasicBlock *MBB = MI.getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2326 auto I = ++MachineBasicBlock::const_iterator(MI);
2327 for (auto E = MBB->end(); I != E; ++I) {
2328 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2329 I->isCall())
2330 break;
2331 }
2332
2333 // If we could not find a frame destroy opcode, then it has already
2334 // been simplified, so we don't care.
2335 if (I->getOpcode() != getCallFrameDestroyOpcode())
2336 return 0;
2337
2338 return -(I->getOperand(1).getImm());
2339 }
2340
2341 // Currently handle only PUSHes we can reasonably expect to see
2342 // in call sequences
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2343 switch (MI.getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2344 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2345 return 0;
2346 case X86::PUSH32i8:
2347 case X86::PUSH32r:
2348 case X86::PUSH32rmm:
2349 case X86::PUSH32rmr:
2350 case X86::PUSHi32:
2351 return 4;
David L Kreitzer0fe46322016-05-02 13:45:25 +0000[diff] [blame]2352 case X86::PUSH64i8:
2353 case X86::PUSH64r:
2354 case X86::PUSH64rmm:
2355 case X86::PUSH64rmr:
2356 case X86::PUSH64i32:
2357 return 8;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2358 }
2359}
2360
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2361/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2362/// operand and follow operands form a reference to the stack frame.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2363bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2364 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2365 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2366 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2367 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2368 MI.getOperand(Op + X86::AddrDisp).isImm() &&
2369 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2370 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2371 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2372 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2373 return true;
2374 }
2375 return false;
2376}
2377
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2378static bool isFrameLoadOpcode(int Opcode) {
2379 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2380 default:
2381 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2382 case X86::MOV8rm:
2383 case X86::MOV16rm:
2384 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2385 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2386 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2387 case X86::MOVSSrm:
2388 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2389 case X86::MOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2390 case X86::MOVUPSrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2391 case X86::MOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2392 case X86::MOVUPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2393 case X86::MOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2394 case X86::MOVDQUrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2395 case X86::VMOVSSrm:
2396 case X86::VMOVSDrm:
2397 case X86::VMOVAPSrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2398 case X86::VMOVUPSrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2399 case X86::VMOVAPDrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2400 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2401 case X86::VMOVDQArm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2402 case X86::VMOVDQUrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2403 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2404 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2405 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2406 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2407 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2408 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2409 case X86::MMX_MOVD64rm:
2410 case X86::MMX_MOVQ64rm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2411 case X86::VMOVSSZrm:
2412 case X86::VMOVSDZrm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2413 case X86::VMOVAPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2414 case X86::VMOVAPSZ128rm:
2415 case X86::VMOVAPSZ256rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2416 case X86::VMOVUPSZrm:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2417 case X86::VMOVUPSZ128rm:
2418 case X86::VMOVUPSZ256rm:
2419 case X86::VMOVAPDZrm:
2420 case X86::VMOVAPDZ128rm:
2421 case X86::VMOVAPDZ256rm:
2422 case X86::VMOVUPDZrm:
2423 case X86::VMOVUPDZ128rm:
2424 case X86::VMOVUPDZ256rm:
2425 case X86::VMOVDQA32Zrm:
2426 case X86::VMOVDQA32Z128rm:
2427 case X86::VMOVDQA32Z256rm:
2428 case X86::VMOVDQU32Zrm:
2429 case X86::VMOVDQU32Z128rm:
2430 case X86::VMOVDQU32Z256rm:
2431 case X86::VMOVDQA64Zrm:
2432 case X86::VMOVDQA64Z128rm:
2433 case X86::VMOVDQA64Z256rm:
2434 case X86::VMOVDQU64Zrm:
2435 case X86::VMOVDQU64Z128rm:
2436 case X86::VMOVDQU64Z256rm:
2437 case X86::VMOVDQU8Zrm:
2438 case X86::VMOVDQU8Z128rm:
2439 case X86::VMOVDQU8Z256rm:
2440 case X86::VMOVDQU16Zrm:
2441 case X86::VMOVDQU16Z128rm:
2442 case X86::VMOVDQU16Z256rm:
2443 case X86::KMOVBkm:
2444 case X86::KMOVWkm:
2445 case X86::KMOVDkm:
2446 case X86::KMOVQkm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2447 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2448 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2449}
2450
2451static bool isFrameStoreOpcode(int Opcode) {
2452 switch (Opcode) {
2453 default: break;
2454 case X86::MOV8mr:
2455 case X86::MOV16mr:
2456 case X86::MOV32mr:
2457 case X86::MOV64mr:
2458 case X86::ST_FpP64m:
2459 case X86::MOVSSmr:
2460 case X86::MOVSDmr:
2461 case X86::MOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2462 case X86::MOVUPSmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2463 case X86::MOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2464 case X86::MOVUPDmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2465 case X86::MOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2466 case X86::MOVDQUmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2467 case X86::VMOVSSmr:
2468 case X86::VMOVSDmr:
2469 case X86::VMOVAPSmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2470 case X86::VMOVUPSmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2471 case X86::VMOVAPDmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2472 case X86::VMOVUPDmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2473 case X86::VMOVDQAmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2474 case X86::VMOVDQUmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2475 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2476 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2477 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2478 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2479 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2480 case X86::VMOVDQAYmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2481 case X86::VMOVSSZmr:
2482 case X86::VMOVSDZmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2483 case X86::VMOVUPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2484 case X86::VMOVUPSZ128mr:
2485 case X86::VMOVUPSZ256mr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2486 case X86::VMOVAPSZmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2487 case X86::VMOVAPSZ128mr:
2488 case X86::VMOVAPSZ256mr:
2489 case X86::VMOVUPDZmr:
2490 case X86::VMOVUPDZ128mr:
2491 case X86::VMOVUPDZ256mr:
2492 case X86::VMOVAPDZmr:
2493 case X86::VMOVAPDZ128mr:
2494 case X86::VMOVAPDZ256mr:
2495 case X86::VMOVDQA32Zmr:
2496 case X86::VMOVDQA32Z128mr:
2497 case X86::VMOVDQA32Z256mr:
2498 case X86::VMOVDQU32Zmr:
2499 case X86::VMOVDQU32Z128mr:
2500 case X86::VMOVDQU32Z256mr:
2501 case X86::VMOVDQA64Zmr:
2502 case X86::VMOVDQA64Z128mr:
2503 case X86::VMOVDQA64Z256mr:
2504 case X86::VMOVDQU64Zmr:
2505 case X86::VMOVDQU64Z128mr:
2506 case X86::VMOVDQU64Z256mr:
2507 case X86::VMOVDQU8Zmr:
2508 case X86::VMOVDQU8Z128mr:
2509 case X86::VMOVDQU8Z256mr:
2510 case X86::VMOVDQU16Zmr:
2511 case X86::VMOVDQU16Z128mr:
2512 case X86::VMOVDQU16Z256mr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2513 case X86::MMX_MOVD64mr:
2514 case X86::MMX_MOVQ64mr:
2515 case X86::MMX_MOVNTQmr:
Craig Topper650a15e2016-07-18 06:14:39 +0000[diff] [blame]2516 case X86::KMOVBmk:
2517 case X86::KMOVWmk:
2518 case X86::KMOVDmk:
2519 case X86::KMOVQmk:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2520 return true;
2521 }
2522 return false;
2523}
2524
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2525unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2526 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2527 if (isFrameLoadOpcode(MI.getOpcode()))
2528 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2529 return MI.getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2530 return 0;
2531}
2532
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2533unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2534 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2535 if (isFrameLoadOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2536 unsigned Reg;
2537 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2538 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2539 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2540 const MachineMemOperand *Dummy;
2541 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2542 }
2543 return 0;
2544}
2545
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2546unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2547 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2548 if (isFrameStoreOpcode(MI.getOpcode()))
2549 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2550 isFrameOperand(MI, 0, FrameIndex))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2551 return MI.getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2552 return 0;
2553}
2554
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2555unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2556 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2557 if (isFrameStoreOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2558 unsigned Reg;
2559 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2560 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2561 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2562 const MachineMemOperand *Dummy;
2563 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2564 }
2565 return 0;
2566}
2567
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2568/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2569static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2570 // Don't waste compile time scanning use-def chains of physregs.
2571 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2572 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2573 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2574 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2575 E = MRI.def_instr_end(); I != E; ++I) {
2576 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2577 if (DefMI->getOpcode() != X86::MOVPC32r)
2578 return false;
2579 assert(!isPICBase && "More than one PIC base?");
2580 isPICBase = true;
2581 }
2582 return isPICBase;
2583}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2584
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2585bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2586 AliasAnalysis *AA) const {
2587 switch (MI.getOpcode()) {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2588 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2589 case X86::MOV8rm:
2590 case X86::MOV16rm:
2591 case X86::MOV32rm:
2592 case X86::MOV64rm:
2593 case X86::LD_Fp64m:
2594 case X86::MOVSSrm:
2595 case X86::MOVSDrm:
2596 case X86::MOVAPSrm:
2597 case X86::MOVUPSrm:
2598 case X86::MOVAPDrm:
2599 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2600 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2601 case X86::VMOVSSrm:
2602 case X86::VMOVSDrm:
2603 case X86::VMOVAPSrm:
2604 case X86::VMOVUPSrm:
2605 case X86::VMOVAPDrm:
2606 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2607 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2608 case X86::VMOVAPSYrm:
2609 case X86::VMOVUPSYrm:
2610 case X86::VMOVAPDYrm:
2611 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2612 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2613 case X86::MMX_MOVD64rm:
2614 case X86::MMX_MOVQ64rm:
2615 case X86::FsVMOVAPSrm:
2616 case X86::FsVMOVAPDrm:
2617 case X86::FsMOVAPSrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2618 case X86::FsMOVAPDrm:
2619 // AVX-512
Craig Toppere4f868e2016-07-29 06:06:04 +0000[diff] [blame]2620 case X86::VMOVSSZrm:
2621 case X86::VMOVSDZrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2622 case X86::VMOVAPDZ128rm:
2623 case X86::VMOVAPDZ256rm:
2624 case X86::VMOVAPDZrm:
2625 case X86::VMOVAPSZ128rm:
2626 case X86::VMOVAPSZ256rm:
2627 case X86::VMOVAPSZrm:
2628 case X86::VMOVDQA32Z128rm:
2629 case X86::VMOVDQA32Z256rm:
2630 case X86::VMOVDQA32Zrm:
2631 case X86::VMOVDQA64Z128rm:
2632 case X86::VMOVDQA64Z256rm:
2633 case X86::VMOVDQA64Zrm:
2634 case X86::VMOVDQU16Z128rm:
2635 case X86::VMOVDQU16Z256rm:
2636 case X86::VMOVDQU16Zrm:
2637 case X86::VMOVDQU32Z128rm:
2638 case X86::VMOVDQU32Z256rm:
2639 case X86::VMOVDQU32Zrm:
2640 case X86::VMOVDQU64Z128rm:
2641 case X86::VMOVDQU64Z256rm:
2642 case X86::VMOVDQU64Zrm:
2643 case X86::VMOVDQU8Z128rm:
2644 case X86::VMOVDQU8Z256rm:
2645 case X86::VMOVDQU8Zrm:
2646 case X86::VMOVUPSZ128rm:
2647 case X86::VMOVUPSZ256rm:
2648 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2649 // Loads from constant pools are trivially rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2650 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2651 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2652 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2653 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2654 MI.isInvariantLoad(AA)) {
2655 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2656 if (BaseReg == 0 || BaseReg == X86::RIP)
2657 return true;
2658 // Allow re-materialization of PIC load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2659 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2660 return false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2661 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2662 const MachineRegisterInfo &MRI = MF.getRegInfo();
2663 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2664 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2665 return false;
2666 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2667
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2668 case X86::LEA32r:
2669 case X86::LEA64r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2670 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2671 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2672 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2673 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2674 // lea fi#, lea GV, etc. are all rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2675 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2676 return true;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2677 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2678 if (BaseReg == 0)
2679 return true;
2680 // Allow re-materialization of lea PICBase + x.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2681 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2682 const MachineRegisterInfo &MRI = MF.getRegInfo();
2683 return regIsPICBase(BaseReg, MRI);
2684 }
2685 return false;
2686 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2687 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2688
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2689 // All other instructions marked M_REMATERIALIZABLE are always trivially
2690 // rematerializable.
2691 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2692}
2693
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2694bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2695 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2696 MachineBasicBlock::iterator E = MBB.end();
2697
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2698 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2699 // safety after visiting 4 instructions in each direction, we will assume
2700 // it's not safe.
2701 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2702 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2703 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2704 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2705 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2706 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2707 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2708 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2709 continue;
2710 if (MO.getReg() == X86::EFLAGS) {
2711 if (MO.isUse())
2712 return false;
2713 SeenDef = true;
2714 }
2715 }
2716
2717 if (SeenDef)
2718 // This instruction defines EFLAGS, no need to look any further.
2719 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2720 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2721 // Skip over DBG_VALUE.
2722 while (Iter != E && Iter->isDebugValue())
2723 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2724 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2725
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2726 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2727 // live in.
2728 if (Iter == E) {
Craig Topperca66fc52015-12-20 18:41:57 +0000[diff] [blame]2729 for (MachineBasicBlock *S : MBB.successors())
2730 if (S->isLiveIn(X86::EFLAGS))
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2731 return false;
2732 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2733 }
2734
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2735 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2736 Iter = I;
2737 for (unsigned i = 0; i < 4; ++i) {
2738 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2739 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2740 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2741 return !MBB.isLiveIn(X86::EFLAGS);
2742
2743 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2744 // Skip over DBG_VALUE.
2745 while (Iter != B && Iter->isDebugValue())
2746 --Iter;
2747
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2748 bool SawKill = false;
2749 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2750 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2751 // A register mask may clobber EFLAGS, but we should still look for a
2752 // live EFLAGS def.
2753 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2754 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2755 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2756 if (MO.isDef()) return MO.isDead();
2757 if (MO.isKill()) SawKill = true;
2758 }
2759 }
2760
2761 if (SawKill)
2762 // This instruction kills EFLAGS and doesn't redefine it, so
2763 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2764 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2765 }
2766
2767 // Conservative answer.
2768 return false;
2769}
2770
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2771void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2772 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2773 unsigned DestReg, unsigned SubIdx,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2774 const MachineInstr &Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2775 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2776 bool ClobbersEFLAGS = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2777 for (const MachineOperand &MO : Orig.operands()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2778 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2779 ClobbersEFLAGS = true;
2780 break;
2781 }
2782 }
2783
2784 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2785 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2786 // effects.
2787 int Value;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2788 switch (Orig.getOpcode()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2789 case X86::MOV32r0: Value = 0; break;
2790 case X86::MOV32r1: Value = 1; break;
2791 case X86::MOV32r_1: Value = -1; break;
2792 default:
2793 llvm_unreachable("Unexpected instruction!");
2794 }
2795
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2796 const DebugLoc &DL = Orig.getDebugLoc();
2797 BuildMI(MBB, I, DL, get(X86::MOV32ri))
2798 .addOperand(Orig.getOperand(0))
2799 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2800 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2801 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2802 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2803 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2804
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]2805 MachineInstr &NewMI = *std::prev(I);
2806 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2807}
2808
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2809/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2810bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2811 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2812 MachineOperand &MO = MI.getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2813 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2814 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2815 return true;
2816 }
2817 }
2818 return false;
2819}
2820
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2821/// Check whether the shift count for a machine operand is non-zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2822inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2823 unsigned ShiftAmtOperandIdx) {
2824 // The shift count is six bits with the REX.W prefix and five bits without.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2825 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2826 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2827 return Imm & ShiftCountMask;
2828}
2829
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2830/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2831/// can be represented by a LEA instruction.
2832inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2833 // Left shift instructions can be transformed into load-effective-address
2834 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2835 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2836 // The SIB.scale field is two bits wide which means that we can encode any
2837 // shift amount less than 4.
2838 return ShAmt < 4 && ShAmt > 0;
2839}
2840
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2841bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2842 unsigned Opc, bool AllowSP, unsigned &NewSrc,
2843 bool &isKill, bool &isUndef,
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2844 MachineOperand &ImplicitOp) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2845 MachineFunction &MF = *MI.getParent()->getParent();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2846 const TargetRegisterClass *RC;
2847 if (AllowSP) {
2848 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2849 } else {
2850 RC = Opc != X86::LEA32r ?
2851 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2852 }
2853 unsigned SrcReg = Src.getReg();
2854
2855 // For both LEA64 and LEA32 the register already has essentially the right
2856 // type (32-bit or 64-bit) we may just need to forbid SP.
2857 if (Opc != X86::LEA64_32r) {
2858 NewSrc = SrcReg;
2859 isKill = Src.isKill();
2860 isUndef = Src.isUndef();
2861
2862 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2863 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2864 return false;
2865
2866 return true;
2867 }
2868
2869 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2870 // another we need to add 64-bit registers to the final MI.
2871 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2872 ImplicitOp = Src;
2873 ImplicitOp.setImplicit();
2874
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]2875 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
Matthias Braunca8210a2016-07-21 00:33:38 +0000[diff] [blame]2876 isKill = Src.isKill();
2877 isUndef = Src.isUndef();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2878 } else {
2879 // Virtual register of the wrong class, we have to create a temporary 64-bit
2880 // vreg to feed into the LEA.
2881 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2882 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2883 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2884 .addOperand(Src);
2885
2886 // Which is obviously going to be dead after we're done with it.
2887 isKill = true;
2888 isUndef = false;
2889 }
2890
2891 // We've set all the parameters without issue.
2892 return true;
2893}
2894
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2895/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2896/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2897/// truncating back down to a 16-bit subregister.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2898MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2899 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2900 LiveVariables *LV) const {
2901 MachineBasicBlock::iterator MBBI = MI.getIterator();
2902 unsigned Dest = MI.getOperand(0).getReg();
2903 unsigned Src = MI.getOperand(1).getReg();
2904 bool isDead = MI.getOperand(0).isDead();
2905 bool isKill = MI.getOperand(1).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2906
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2907 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2908 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2909 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2910 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2911 Opc = X86::LEA64_32r;
2912 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2913 } else {
2914 Opc = X86::LEA32r;
2915 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2916 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2917
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2918 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2919 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2920 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2921 // movw (%rbp,%rcx,2), %dx
2922 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2923 // But testing has shown this *does* help performance in 64-bit mode (at
2924 // least on modern x86 machines).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2925 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2926 MachineInstr *InsMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2927 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2928 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2929 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2930
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2931 MachineInstrBuilder MIB =
2932 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2933 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2934 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2935 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2936 unsigned ShAmt = MI.getOperand(2).getImm();
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2937 MIB.addReg(0).addImm(1ULL << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2938 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2939 break;
2940 }
2941 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2942 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2943 break;
2944 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2945 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2946 break;
2947 case X86::ADD16ri:
2948 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2949 case X86::ADD16ri_DB:
2950 case X86::ADD16ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2951 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2952 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2953 case X86::ADD16rr:
2954 case X86::ADD16rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2955 unsigned Src2 = MI.getOperand(2).getReg();
2956 bool isKill2 = MI.getOperand(2).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2957 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2958 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2959 if (Src == Src2) {
2960 // ADD16rr %reg1028<kill>, %reg1028
2961 // just a single insert_subreg.
2962 addRegReg(MIB, leaInReg, true, leaInReg, false);
2963 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2964 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2965 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2966 else
2967 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2968 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2969 // well be shifting and then extracting the lower 16-bits.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2970 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2971 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2972 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2973 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2974 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2975 }
2976 if (LV && isKill2 && InsMI2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2977 LV->replaceKillInstruction(Src2, MI, *InsMI2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2978 break;
2979 }
2980 }
2981
2982 MachineInstr *NewMI = MIB;
2983 MachineInstr *ExtMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2984 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2985 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2986 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2987
2988 if (LV) {
2989 // Update live variables
2990 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2991 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2992 if (isKill)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2993 LV->replaceKillInstruction(Src, MI, *InsMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2994 if (isDead)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2995 LV->replaceKillInstruction(Dest, MI, *ExtMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2996 }
2997
2998 return ExtMI;
2999}
3000
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3001/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3002/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
3003/// may be able to convert a two-address instruction into a true
3004/// three-address instruction on demand. This allows the X86 target (for
3005/// example) to convert ADD and SHL instructions into LEA instructions if they
3006/// would require register copies due to two-addressness.
3007///
3008/// This method returns a null pointer if the transformation cannot be
3009/// performed, otherwise it returns the new instruction.
3010///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3011MachineInstr *
3012X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3013 MachineInstr &MI, LiveVariables *LV) const {
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3014 // The following opcodes also sets the condition code register(s). Only
3015 // convert them to equivalent lea if the condition code register def's
3016 // are dead!
3017 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3018 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3019
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3020 MachineFunction &MF = *MI.getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3021 // All instructions input are two-addr instructions. Get the known operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3022 const MachineOperand &Dest = MI.getOperand(0);
3023 const MachineOperand &Src = MI.getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3024
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3025 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3026 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3027 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]3028 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3029 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3030 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]3031
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3032 unsigned MIOpc = MI.getOpcode();
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]3033 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3034 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]3035 case X86::SHL64ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3036 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3037 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3038 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3039
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3040 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3041 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
3042 !MF.getRegInfo().constrainRegClass(Src.getReg(),
3043 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3044 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3045
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3046 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3047 .addOperand(Dest)
3048 .addReg(0)
3049 .addImm(1ULL << ShAmt)
3050 .addOperand(Src)
3051 .addImm(0)
3052 .addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]3053 break;
3054 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3055 case X86::SHL32ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3056 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3057 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3058 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3059
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]3060 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3061
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3062 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]3063 bool isKill, isUndef;
3064 unsigned SrcReg;
3065 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3066 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3067 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3068 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3069
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3070 MachineInstrBuilder MIB =
3071 BuildMI(MF, MI.getDebugLoc(), get(Opc))
3072 .addOperand(Dest)
3073 .addReg(0)
3074 .addImm(1ULL << ShAmt)
3075 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
3076 .addImm(0)
3077 .addReg(0);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]3078 if (ImplicitOp.getReg() != 0)
3079 MIB.addOperand(ImplicitOp);
3080 NewMI = MIB;
3081
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3082 break;
3083 }
3084 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3085 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]3086 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3087 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3088
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]3089 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3090 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3091 : nullptr;
3092 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3093 .addOperand(Dest)
3094 .addReg(0)
3095 .addImm(1ULL << ShAmt)
3096 .addOperand(Src)
3097 .addImm(0)
3098 .addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]3099 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]3100 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3101 case X86::INC64r:
3102 case X86::INC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3103 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3104 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
3105 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3106 bool isKill, isUndef;
3107 unsigned SrcReg;
3108 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3109 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3110 SrcReg, isKill, isUndef, ImplicitOp))
3111 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]3112
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3113 MachineInstrBuilder MIB =
3114 BuildMI(MF, MI.getDebugLoc(), get(Opc))
3115 .addOperand(Dest)
3116 .addReg(SrcReg,
3117 getKillRegState(isKill) | getUndefRegState(isUndef));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3118 if (ImplicitOp.getReg() != 0)
3119 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]3120
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3121 NewMI = addOffset(MIB, 1);
3122 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]3123 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3124 case X86::INC16r:
3125 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3126 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3127 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3128 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3129 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3130 .addOperand(Dest)
3131 .addOperand(Src),
3132 1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3133 break;
3134 case X86::DEC64r:
3135 case X86::DEC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3136 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3137 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
3138 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3139
3140 bool isKill, isUndef;
3141 unsigned SrcReg;
3142 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3143 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3144 SrcReg, isKill, isUndef, ImplicitOp))
3145 return nullptr;
3146
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3147 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3148 .addOperand(Dest)
3149 .addReg(SrcReg, getUndefRegState(isUndef) |
3150 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3151 if (ImplicitOp.getReg() != 0)
3152 MIB.addOperand(ImplicitOp);
3153
3154 NewMI = addOffset(MIB, -1);
3155
3156 break;
3157 }
3158 case X86::DEC16r:
3159 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3160 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3161 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3162 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3163 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3164 .addOperand(Dest)
3165 .addOperand(Src),
3166 -1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3167 break;
3168 case X86::ADD64rr:
3169 case X86::ADD64rr_DB:
3170 case X86::ADD32rr:
3171 case X86::ADD32rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3172 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3173 unsigned Opc;
3174 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3175 Opc = X86::LEA64r;
3176 else
3177 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3178
3179 bool isKill, isUndef;
3180 unsigned SrcReg;
3181 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3182 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3183 SrcReg, isKill, isUndef, ImplicitOp))
3184 return nullptr;
3185
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3186 const MachineOperand &Src2 = MI.getOperand(2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3187 bool isKill2, isUndef2;
3188 unsigned SrcReg2;
3189 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3190 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
3191 SrcReg2, isKill2, isUndef2, ImplicitOp2))
3192 return nullptr;
3193
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3194 MachineInstrBuilder MIB =
3195 BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3196 if (ImplicitOp.getReg() != 0)
3197 MIB.addOperand(ImplicitOp);
3198 if (ImplicitOp2.getReg() != 0)
3199 MIB.addOperand(ImplicitOp2);
3200
3201 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3202
3203 // Preserve undefness of the operands.
3204 NewMI->getOperand(1).setIsUndef(isUndef);
3205 NewMI->getOperand(3).setIsUndef(isUndef2);
3206
3207 if (LV && Src2.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3208 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3209 break;
3210 }
3211 case X86::ADD16rr:
3212 case X86::ADD16rr_DB: {
3213 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3214 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3215 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3216 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3217 unsigned Src2 = MI.getOperand(2).getReg();
3218 bool isKill2 = MI.getOperand(2).isKill();
3219 NewMI = addRegReg(
3220 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3221 Src.getReg(), Src.isKill(), Src2, isKill2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3222
3223 // Preserve undefness of the operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3224 bool isUndef = MI.getOperand(1).isUndef();
3225 bool isUndef2 = MI.getOperand(2).isUndef();
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3226 NewMI->getOperand(1).setIsUndef(isUndef);
3227 NewMI->getOperand(3).setIsUndef(isUndef2);
3228
3229 if (LV && isKill2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3230 LV->replaceKillInstruction(Src2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3231 break;
3232 }
3233 case X86::ADD64ri32:
3234 case X86::ADD64ri8:
3235 case X86::ADD64ri32_DB:
3236 case X86::ADD64ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3237 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3238 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3239 .addOperand(Dest)
3240 .addOperand(Src),
3241 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3242 break;
3243 case X86::ADD32ri:
3244 case X86::ADD32ri8:
3245 case X86::ADD32ri_DB:
3246 case X86::ADD32ri8_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3247 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3248 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3249
3250 bool isKill, isUndef;
3251 unsigned SrcReg;
3252 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3253 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3254 SrcReg, isKill, isUndef, ImplicitOp))
3255 return nullptr;
3256
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3257 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3258 .addOperand(Dest)
3259 .addReg(SrcReg, getUndefRegState(isUndef) |
3260 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3261 if (ImplicitOp.getReg() != 0)
3262 MIB.addOperand(ImplicitOp);
3263
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3264 NewMI = addOffset(MIB, MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3265 break;
3266 }
3267 case X86::ADD16ri:
3268 case X86::ADD16ri8:
3269 case X86::ADD16ri_DB:
3270 case X86::ADD16ri8_DB:
3271 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3272 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3273 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3274 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3275 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3276 .addOperand(Dest)
3277 .addOperand(Src),
3278 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3279 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3280 }
3281
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3282 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]3283
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3284 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3285 if (Src.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3286 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3287 if (Dest.isDead())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3288 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3289 }
3290
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3291 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]3292 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3293}
3294
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3295/// Returns true if the given instruction opcode is FMA3.
3296/// Otherwise, returns false.
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3297/// The second parameter is optional and is used as the second return from
3298/// the function. It is set to true if the given instruction has FMA3 opcode
3299/// that is used for lowering of scalar FMA intrinsics, and it is set to false
3300/// otherwise.
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3301static bool isFMA3(unsigned Opcode, bool &IsIntrinsic) {
3302 IsIntrinsic = false;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3303
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3304#define FMA3_CASE(Name, Modifier) \
3305case X86::Name##r##Modifier: case X86::Name##m##Modifier:
3306
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3307#define FMA3_SCALAR_PAIR(Name, Size, Modifier) \
3308 FMA3_CASE(Name##SD##Size, Modifier) \
3309 FMA3_CASE(Name##SS##Size, Modifier)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3310
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3311#define FMA3_PACKED_PAIR(Name, Size) \
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3312 FMA3_CASE(Name##PD##Size, ) \
3313 FMA3_CASE(Name##PS##Size, )
3314
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3315#define FMA3_PACKED_SET(Form, Size) \
3316 FMA3_PACKED_PAIR(VFMADD##Form, Size) \
3317 FMA3_PACKED_PAIR(VFMSUB##Form, Size) \
3318 FMA3_PACKED_PAIR(VFNMADD##Form, Size) \
3319 FMA3_PACKED_PAIR(VFNMSUB##Form, Size) \
3320 FMA3_PACKED_PAIR(VFMADDSUB##Form, Size) \
3321 FMA3_PACKED_PAIR(VFMSUBADD##Form, Size)
3322
3323#define FMA3_CASES(Form) \
3324 FMA3_SCALAR_PAIR(VFMADD##Form, ,) \
3325 FMA3_SCALAR_PAIR(VFMSUB##Form, ,) \
3326 FMA3_SCALAR_PAIR(VFNMADD##Form, ,) \
3327 FMA3_SCALAR_PAIR(VFNMSUB##Form, ,) \
3328 FMA3_PACKED_SET(Form, ) \
3329 FMA3_PACKED_SET(Form, Y) \
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3330
3331#define FMA3_CASES_AVX512(Form) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3332 FMA3_SCALAR_PAIR(VFMADD##Form, Z, ) \
3333 FMA3_SCALAR_PAIR(VFMSUB##Form, Z, ) \
3334 FMA3_SCALAR_PAIR(VFNMADD##Form, Z, ) \
3335 FMA3_SCALAR_PAIR(VFNMSUB##Form, Z, ) \
3336 FMA3_PACKED_SET(Form, Z128) \
3337 FMA3_PACKED_SET(Form, Z256) \
3338 FMA3_PACKED_SET(Form, Z)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3339
3340#define FMA3_CASES_SCALAR_INT(Form) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3341 FMA3_SCALAR_PAIR(VFMADD##Form, , _Int) \
3342 FMA3_SCALAR_PAIR(VFMSUB##Form, , _Int) \
3343 FMA3_SCALAR_PAIR(VFNMADD##Form, , _Int) \
3344 FMA3_SCALAR_PAIR(VFNMSUB##Form, , _Int)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3345
3346#define FMA3_CASES_SCALAR_INT_AVX512(Form) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3347 FMA3_SCALAR_PAIR(VFMADD##Form, Z, _Int) \
3348 FMA3_SCALAR_PAIR(VFMSUB##Form, Z, _Int) \
3349 FMA3_SCALAR_PAIR(VFNMADD##Form, Z, _Int) \
3350 FMA3_SCALAR_PAIR(VFNMSUB##Form, Z, _Int)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3351
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3352 switch (Opcode) {
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3353 FMA3_CASES(132)
3354 FMA3_CASES(213)
3355 FMA3_CASES(231)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3356
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3357 // AVX-512 instructions
3358 FMA3_CASES_AVX512(132)
3359 FMA3_CASES_AVX512(213)
3360 FMA3_CASES_AVX512(231)
Craig Topperca8f5f32016-07-23 07:16:50 +0000[diff] [blame]3361 return true;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3362
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3363 FMA3_CASES_SCALAR_INT(132)
3364 FMA3_CASES_SCALAR_INT(213)
3365 FMA3_CASES_SCALAR_INT(231)
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3366
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3367 // AVX-512 instructions
3368 FMA3_CASES_SCALAR_INT_AVX512(132)
3369 FMA3_CASES_SCALAR_INT_AVX512(213)
3370 FMA3_CASES_SCALAR_INT_AVX512(231)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3371 IsIntrinsic = true;
Craig Topperca8f5f32016-07-23 07:16:50 +0000[diff] [blame]3372 return true;
3373 default:
3374 return false;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3375 }
3376 llvm_unreachable("Opcode not handled by the switch");
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3377
3378#undef FMA3_CASE
3379#undef FMA3_SCALAR_PAIR
3380#undef FMA3_PACKED_PAIR
3381#undef FMA3_PACKED_SET
3382#undef FMA3_CASES
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3383#undef FMA3_CASES_AVX512
3384#undef FMA3_CASES_SCALAR_INT
3385#undef FMA3_CASES_SCALAR_INT_AVX512
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3386}
3387
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3388/// Returns an adjusted FMA opcode that must be used in FMA instruction that
3389/// performs the same computations as the given MI but which has the operands
3390/// \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
3391/// It may return 0 if it is unsafe to commute the operands.
3392///
3393/// The returned FMA opcode may differ from the opcode in the given \p MI.
3394/// For example, commuting the operands #1 and #3 in the following FMA
3395/// FMA213 #1, #2, #3
3396/// results into instruction with adjusted opcode:
3397/// FMA231 #3, #2, #1
3398static unsigned getFMA3OpcodeToCommuteOperands(unsigned Opc,
3399 bool IsIntrinOpcode,
3400 unsigned SrcOpIdx1,
3401 unsigned SrcOpIdx2) {
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3402#define FMA3_ENTRY(Name, Suffix) \
3403 { X86::Name##132##Suffix, X86::Name##213##Suffix, X86::Name##231##Suffix },
3404
3405#define FMA3_SCALAR_PAIR(Name, Suffix) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3406 FMA3_ENTRY(Name, SS##Suffix) \
3407 FMA3_ENTRY(Name, SD##Suffix)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3408
3409#define FMA3_PACKED_PAIR(Name, Suffix) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3410 FMA3_ENTRY(Name, PS##Suffix) \
3411 FMA3_ENTRY(Name, PD##Suffix)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3412
3413#define FMA3_PACKED_SIZES(Name, Suffix) \
3414 FMA3_PACKED_PAIR(Name, Suffix) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3415 FMA3_PACKED_PAIR(Name, Y##Suffix)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3416
3417#define FMA3_TABLE_ALL(Name) \
3418 FMA3_SCALAR_PAIR(Name, r) \
3419 FMA3_PACKED_SIZES(Name, r) \
3420 FMA3_SCALAR_PAIR(Name, m) \
3421 FMA3_PACKED_SIZES(Name, m)
3422
3423#define FMA3_TABLE_PACKED(Name) \
3424 FMA3_PACKED_SIZES(Name, r) \
3425 FMA3_PACKED_SIZES(Name, m)
3426
3427#define FMA3_TABLE_SCALAR_INT(Name) \
3428 FMA3_SCALAR_PAIR(Name, r_Int) \
3429 FMA3_SCALAR_PAIR(Name, m_Int)
3430
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3431#define FMA3_PACKED_SIZES_AVX512(Name, Suffix) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3432 FMA3_PACKED_PAIR(Name, Z128##Suffix) \
3433 FMA3_PACKED_PAIR(Name, Z256##Suffix) \
3434 FMA3_PACKED_PAIR(Name, Z##Suffix)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3435
3436#define FMA3_TABLE_ALL_AVX512(Name) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3437 FMA3_SCALAR_PAIR(Name, Zr) \
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3438 FMA3_PACKED_SIZES_AVX512(Name, r) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3439 FMA3_SCALAR_PAIR(Name, Zm) \
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3440 FMA3_PACKED_SIZES_AVX512(Name, m)
3441
3442#define FMA3_TABLE_PACKED_AVX512(Name) \
3443 FMA3_PACKED_SIZES_AVX512(Name, r) \
3444 FMA3_PACKED_SIZES_AVX512(Name, m)
3445
3446#define FMA3_TABLE_SCALAR_INT_AVX512(Name) \
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]3447 FMA3_SCALAR_PAIR(Name, Zr_Int) \
3448 FMA3_SCALAR_PAIR(Name, Zm_Int)
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3449
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3450 // Define the array that holds FMA opcodes in groups
3451 // of 3 opcodes(132, 213, 231) in each group.
3452 static const uint16_t RegularOpcodeGroups[][3] = {
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3453 FMA3_TABLE_ALL(VFMADD)
3454 FMA3_TABLE_ALL(VFMSUB)
3455 FMA3_TABLE_ALL(VFNMADD)
3456 FMA3_TABLE_ALL(VFNMSUB)
3457 FMA3_TABLE_PACKED(VFMADDSUB)
3458 FMA3_TABLE_PACKED(VFMSUBADD)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3459
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3460 // AVX-512 instructions
3461 FMA3_TABLE_ALL_AVX512(VFMADD)
3462 FMA3_TABLE_ALL_AVX512(VFMSUB)
3463 FMA3_TABLE_ALL_AVX512(VFNMADD)
3464 FMA3_TABLE_ALL_AVX512(VFNMSUB)
3465 FMA3_TABLE_PACKED_AVX512(VFMADDSUB)
3466 FMA3_TABLE_PACKED_AVX512(VFMSUBADD)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3467 };
3468
3469 // Define the array that holds FMA*_Int opcodes in groups
3470 // of 3 opcodes(132, 213, 231) in each group.
3471 static const uint16_t IntrinOpcodeGroups[][3] = {
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3472 FMA3_TABLE_SCALAR_INT(VFMADD)
3473 FMA3_TABLE_SCALAR_INT(VFMSUB)
3474 FMA3_TABLE_SCALAR_INT(VFNMADD)
3475 FMA3_TABLE_SCALAR_INT(VFNMSUB)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3476
Craig Topper8152b9c2016-07-23 16:44:08 +0000[diff] [blame]3477 // AVX-512 instructions
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3478 FMA3_TABLE_SCALAR_INT_AVX512(VFMADD)
3479 FMA3_TABLE_SCALAR_INT_AVX512(VFMSUB)
3480 FMA3_TABLE_SCALAR_INT_AVX512(VFNMADD)
3481 FMA3_TABLE_SCALAR_INT_AVX512(VFNMSUB)
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3482 };
3483
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3484#undef FMA3_ENTRY
3485#undef FMA3_SCALAR_PAIR
3486#undef FMA3_PACKED_PAIR
3487#undef FMA3_PACKED_SIZES
3488#undef FMA3_TABLE_ALL
3489#undef FMA3_TABLE_PACKED
3490#undef FMA3_TABLE_SCALAR_INT
3491#undef FMA3_SCALAR_PAIR_AVX512
Craig Topperb6519db2016-07-23 07:16:56 +0000[diff] [blame]3492#undef FMA3_PACKED_SIZES_AVX512
3493#undef FMA3_TABLE_ALL_AVX512
3494#undef FMA3_TABLE_PACKED_AVX512
3495#undef FMA3_TABLE_SCALAR_INT_AVX512
3496
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3497 const unsigned Form132Index = 0;
3498 const unsigned Form213Index = 1;
3499 const unsigned Form231Index = 2;
3500 const unsigned FormsNum = 3;
3501
3502 size_t GroupsNum;
3503 const uint16_t (*OpcodeGroups)[3];
3504 if (IsIntrinOpcode) {
3505 GroupsNum = array_lengthof(IntrinOpcodeGroups);
3506 OpcodeGroups = IntrinOpcodeGroups;
3507 } else {
3508 GroupsNum = array_lengthof(RegularOpcodeGroups);
3509 OpcodeGroups = RegularOpcodeGroups;
3510 }
3511
3512 const uint16_t *FoundOpcodesGroup = nullptr;
3513 size_t FormIndex;
3514
3515 // Look for the input opcode in the corresponding opcodes table.
3516 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3517 ++GroupIndex) {
3518 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
3519 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3520 FoundOpcodesGroup = OpcodeGroups[GroupIndex];
3521 break;
3522 }
3523 }
3524 }
3525
3526 // The input opcode does not match with any of the opcodes from the tables.
3527 // The unsupported FMA opcode must be added to one of the two opcode groups
3528 // defined above.
3529 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
3530
3531 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3532 if (SrcOpIdx1 > SrcOpIdx2)
3533 std::swap(SrcOpIdx1, SrcOpIdx2);
3534
3535 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3536 // analysis. The commute optimization is legal only if all users of FMA*_Int
3537 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3538 // not implemented yet. So, just return 0 in that case.
3539 // When such analysis are available this place will be the right place for
3540 // calling it.
3541 if (IsIntrinOpcode && SrcOpIdx1 == 1)
3542 return 0;
3543
3544 unsigned Case;
3545 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3546 Case = 0;
3547 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3548 Case = 1;
3549 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3550 Case = 2;
3551 else
3552 return 0;
3553
3554 // Define the FMA forms mapping array that helps to map input FMA form
3555 // to output FMA form to preserve the operation semantics after
3556 // commuting the operands.
3557 static const unsigned FormMapping[][3] = {
3558 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3559 // FMA132 A, C, b; ==> FMA231 C, A, b;
3560 // FMA213 B, A, c; ==> FMA213 A, B, c;
3561 // FMA231 C, A, b; ==> FMA132 A, C, b;
3562 { Form231Index, Form213Index, Form132Index },
3563 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3564 // FMA132 A, c, B; ==> FMA132 B, c, A;
3565 // FMA213 B, a, C; ==> FMA231 C, a, B;
3566 // FMA231 C, a, B; ==> FMA213 B, a, C;
3567 { Form132Index, Form231Index, Form213Index },
3568 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3569 // FMA132 a, C, B; ==> FMA213 a, B, C;
3570 // FMA213 b, A, C; ==> FMA132 b, C, A;
3571 // FMA231 c, A, B; ==> FMA231 c, B, A;
3572 { Form213Index, Form132Index, Form231Index }
3573 };
3574
3575 // Everything is ready, just adjust the FMA opcode and return it.
3576 FormIndex = FormMapping[Case][FormIndex];
3577 return FoundOpcodesGroup[FormIndex];
3578}
3579
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3580MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3581 unsigned OpIdx1,
3582 unsigned OpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3583 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3584 if (NewMI)
3585 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3586 return MI;
3587 };
3588
3589 switch (MI.getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3590 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3591 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3592 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3593 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3594 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3595 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3596 unsigned Opc;
3597 unsigned Size;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3598 switch (MI.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3599 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3600 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3601 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3602 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3603 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3604 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3605 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3606 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3607 unsigned Amt = MI.getOperand(3).getImm();
3608 auto &WorkingMI = cloneIfNew(MI);
3609 WorkingMI.setDesc(get(Opc));
3610 WorkingMI.getOperand(3).setImm(Size - Amt);
3611 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3612 OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3613 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3614 case X86::BLENDPDrri:
3615 case X86::BLENDPSrri:
3616 case X86::PBLENDWrri:
3617 case X86::VBLENDPDrri:
3618 case X86::VBLENDPSrri:
3619 case X86::VBLENDPDYrri:
3620 case X86::VBLENDPSYrri:
3621 case X86::VPBLENDDrri:
3622 case X86::VPBLENDWrri:
3623 case X86::VPBLENDDYrri:
3624 case X86::VPBLENDWYrri:{
3625 unsigned Mask;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3626 switch (MI.getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3627 default: llvm_unreachable("Unreachable!");
3628 case X86::BLENDPDrri: Mask = 0x03; break;
3629 case X86::BLENDPSrri: Mask = 0x0F; break;
3630 case X86::PBLENDWrri: Mask = 0xFF; break;
3631 case X86::VBLENDPDrri: Mask = 0x03; break;
3632 case X86::VBLENDPSrri: Mask = 0x0F; break;
3633 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3634 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3635 case X86::VPBLENDDrri: Mask = 0x0F; break;
3636 case X86::VPBLENDWrri: Mask = 0xFF; break;
3637 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3638 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3639 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3640 // Only the least significant bits of Imm are used.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3641 unsigned Imm = MI.getOperand(3).getImm() & Mask;
3642 auto &WorkingMI = cloneIfNew(MI);
3643 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3644 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3645 OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3646 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3647 case X86::PCLMULQDQrr:
3648 case X86::VPCLMULQDQrr:{
3649 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3650 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3651 unsigned Imm = MI.getOperand(3).getImm();
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3652 unsigned Src1Hi = Imm & 0x01;
3653 unsigned Src2Hi = Imm & 0x10;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3654 auto &WorkingMI = cloneIfNew(MI);
3655 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3656 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3657 OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3658 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3659 case X86::CMPPDrri:
3660 case X86::CMPPSrri:
3661 case X86::VCMPPDrri:
3662 case X86::VCMPPSrri:
3663 case X86::VCMPPDYrri:
3664 case X86::VCMPPSYrri: {
3665 // Float comparison can be safely commuted for
3666 // Ordered/Unordered/Equal/NotEqual tests
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3667 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3668 switch (Imm) {
3669 case 0x00: // EQUAL
3670 case 0x03: // UNORDERED
3671 case 0x04: // NOT EQUAL
3672 case 0x07: // ORDERED
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3673 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3674 default:
3675 return nullptr;
3676 }
3677 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3678 case X86::VPCOMBri: case X86::VPCOMUBri:
3679 case X86::VPCOMDri: case X86::VPCOMUDri:
3680 case X86::VPCOMQri: case X86::VPCOMUQri:
3681 case X86::VPCOMWri: case X86::VPCOMUWri: {
3682 // Flip comparison mode immediate (if necessary).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3683 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3684 switch (Imm) {
3685 case 0x00: Imm = 0x02; break; // LT -> GT
3686 case 0x01: Imm = 0x03; break; // LE -> GE
3687 case 0x02: Imm = 0x00; break; // GT -> LT
3688 case 0x03: Imm = 0x01; break; // GE -> LE
3689 case 0x04: // EQ
3690 case 0x05: // NE
3691 case 0x06: // FALSE
3692 case 0x07: // TRUE
3693 default:
3694 break;
3695 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3696 auto &WorkingMI = cloneIfNew(MI);
3697 WorkingMI.getOperand(3).setImm(Imm);
3698 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3699 OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3700 }
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3701 case X86::VPERM2F128rr:
3702 case X86::VPERM2I128rr: {
3703 // Flip permute source immediate.
3704 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3705 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3706 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3707 auto &WorkingMI = cloneIfNew(MI);
3708 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3709 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3710 OpIdx1, OpIdx2);
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3711 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3712 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3713 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3714 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3715 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3716 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3717 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3718 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3719 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3720 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3721 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3722 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3723 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3724 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3725 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3726 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3727 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3728 unsigned Opc;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3729 switch (MI.getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3730 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3731 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3732 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3733 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3734 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3735 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3736 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3737 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3738 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3739 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3740 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3741 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3742 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3743 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3744 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3745 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3746 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3747 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3748 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3749 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3750 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3751 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3752 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3753 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3754 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3755 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3756 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3757 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3758 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3759 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3760 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3761 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3762 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3763 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3764 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3765 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3766 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3767 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3768 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3769 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3770 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3771 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3772 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3773 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3774 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3775 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3776 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3777 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3778 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3779 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3780 auto &WorkingMI = cloneIfNew(MI);
3781 WorkingMI.setDesc(get(Opc));
3782 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3783 OpIdx1, OpIdx2);
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3784 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3785 default:
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3786 bool IsIntrinOpcode;
3787 if (isFMA3(MI.getOpcode(), IsIntrinOpcode)) {
3788 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI.getOpcode(),
3789 IsIntrinOpcode,
3790 OpIdx1, OpIdx2);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3791 if (Opc == 0)
3792 return nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3793 auto &WorkingMI = cloneIfNew(MI);
3794 WorkingMI.setDesc(get(Opc));
3795 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3796 OpIdx1, OpIdx2);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3797 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3798
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3799 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3800 }
3801}
3802
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3803bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3804 bool IsIntrinOpcode,
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3805 unsigned &SrcOpIdx1,
3806 unsigned &SrcOpIdx2) const {
3807
3808 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3809
3810 // Only the first RegOpsNum operands are commutable.
3811 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3812 // that the operand is not specified/fixed.
3813 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3814 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3815 return false;
3816 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3817 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3818 return false;
3819
3820 // Look for two different register operands assumed to be commutable
3821 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3822 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3823 SrcOpIdx2 == CommuteAnyOperandIndex) {
3824 unsigned CommutableOpIdx1 = SrcOpIdx1;
3825 unsigned CommutableOpIdx2 = SrcOpIdx2;
3826
3827 // At least one of operands to be commuted is not specified and
3828 // this method is free to choose appropriate commutable operands.
3829 if (SrcOpIdx1 == SrcOpIdx2)
3830 // Both of operands are not fixed. By default set one of commutable
3831 // operands to the last register operand of the instruction.
3832 CommutableOpIdx2 = RegOpsNum;
3833 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3834 // Only one of operands is not fixed.
3835 CommutableOpIdx2 = SrcOpIdx1;
3836
3837 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3838 // operand and assign its index to CommutableOpIdx1.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3839 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3840 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3841 // The commuted operands must have different registers.
3842 // Otherwise, the commute transformation does not change anything and
3843 // is useless then.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3844 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3845 break;
3846 }
3847
3848 // No appropriate commutable operands were found.
3849 if (CommutableOpIdx1 == 0)
3850 return false;
3851
3852 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3853 // to return those values.
3854 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3855 CommutableOpIdx1, CommutableOpIdx2))
3856 return false;
3857 }
3858
3859 // Check if we can adjust the opcode to preserve the semantics when
3860 // commute the register operands.
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3861 return getFMA3OpcodeToCommuteOperands(MI.getOpcode(), IsIntrinOpcode,
3862 SrcOpIdx1, SrcOpIdx2) != 0;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3863}
3864
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3865bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3866 unsigned &SrcOpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3867 switch (MI.getOpcode()) {
3868 case X86::CMPPDrri:
3869 case X86::CMPPSrri:
3870 case X86::VCMPPDrri:
3871 case X86::VCMPPSrri:
3872 case X86::VCMPPDYrri:
3873 case X86::VCMPPSYrri: {
3874 // Float comparison can be safely commuted for
3875 // Ordered/Unordered/Equal/NotEqual tests
3876 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3877 switch (Imm) {
3878 case 0x00: // EQUAL
3879 case 0x03: // UNORDERED
3880 case 0x04: // NOT EQUAL
3881 case 0x07: // ORDERED
3882 // The indices of the commutable operands are 1 and 2.
3883 // Assign them to the returned operand indices here.
3884 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3885 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3886 return false;
3887 }
3888 default:
Craig Topper6172b0b2016-07-23 07:16:53 +0000[diff] [blame]3889 bool IsIntrinOpcode;
3890 if (isFMA3(MI.getOpcode(), IsIntrinOpcode))
3891 return findFMA3CommutedOpIndices(MI, IsIntrinOpcode,
3892 SrcOpIdx1, SrcOpIdx2);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3893 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3894 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3895 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3896}
3897
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3898static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3899 switch (BrOpc) {
3900 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3901 case X86::JE_1: return X86::COND_E;
3902 case X86::JNE_1: return X86::COND_NE;
3903 case X86::JL_1: return X86::COND_L;
3904 case X86::JLE_1: return X86::COND_LE;
3905 case X86::JG_1: return X86::COND_G;
3906 case X86::JGE_1: return X86::COND_GE;
3907 case X86::JB_1: return X86::COND_B;
3908 case X86::JBE_1: return X86::COND_BE;
3909 case X86::JA_1: return X86::COND_A;
3910 case X86::JAE_1: return X86::COND_AE;
3911 case X86::JS_1: return X86::COND_S;
3912 case X86::JNS_1: return X86::COND_NS;
3913 case X86::JP_1: return X86::COND_P;
3914 case X86::JNP_1: return X86::COND_NP;
3915 case X86::JO_1: return X86::COND_O;
3916 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3917 }
3918}
3919
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3920/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3921static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3922 switch (Opc) {
3923 default: return X86::COND_INVALID;
3924 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3925 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3926 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3927 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3928 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3929 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3930 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3931 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3932 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3933 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3934 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3935 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3936 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3937 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3938 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3939 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3940 }
3941}
3942
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3943/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3944X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3945 switch (Opc) {
3946 default: return X86::COND_INVALID;
3947 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3948 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3949 return X86::COND_A;
3950 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3951 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3952 return X86::COND_AE;
3953 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3954 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3955 return X86::COND_B;
3956 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3957 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3958 return X86::COND_BE;
3959 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3960 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3961 return X86::COND_E;
3962 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3963 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3964 return X86::COND_G;
3965 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3966 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3967 return X86::COND_GE;
3968 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3969 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3970 return X86::COND_L;
3971 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3972 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3973 return X86::COND_LE;
3974 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3975 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3976 return X86::COND_NE;
3977 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3978 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3979 return X86::COND_NO;
3980 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3981 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3982 return X86::COND_NP;
3983 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3984 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3985 return X86::COND_NS;
3986 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3987 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3988 return X86::COND_O;
3989 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3990 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3991 return X86::COND_P;
3992 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3993 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3994 return X86::COND_S;
3995 }
3996}
3997
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3998unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3999 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]4000 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4001 case X86::COND_E: return X86::JE_1;
4002 case X86::COND_NE: return X86::JNE_1;
4003 case X86::COND_L: return X86::JL_1;
4004 case X86::COND_LE: return X86::JLE_1;
4005 case X86::COND_G: return X86::JG_1;
4006 case X86::COND_GE: return X86::JGE_1;
4007 case X86::COND_B: return X86::JB_1;
4008 case X86::COND_BE: return X86::JBE_1;
4009 case X86::COND_A: return X86::JA_1;
4010 case X86::COND_AE: return X86::JAE_1;
4011 case X86::COND_S: return X86::JS_1;
4012 case X86::COND_NS: return X86::JNS_1;
4013 case X86::COND_P: return X86::JP_1;
4014 case X86::COND_NP: return X86::JNP_1;
4015 case X86::COND_O: return X86::JO_1;
4016 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4017 }
4018}
4019
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4020/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4021/// e.g. turning COND_E to COND_NE.
4022X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
4023 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]4024 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4025 case X86::COND_E: return X86::COND_NE;
4026 case X86::COND_NE: return X86::COND_E;
4027 case X86::COND_L: return X86::COND_GE;
4028 case X86::COND_LE: return X86::COND_G;
4029 case X86::COND_G: return X86::COND_LE;
4030 case X86::COND_GE: return X86::COND_L;
4031 case X86::COND_B: return X86::COND_AE;
4032 case X86::COND_BE: return X86::COND_A;
4033 case X86::COND_A: return X86::COND_BE;
4034 case X86::COND_AE: return X86::COND_B;
4035 case X86::COND_S: return X86::COND_NS;
4036 case X86::COND_NS: return X86::COND_S;
4037 case X86::COND_P: return X86::COND_NP;
4038 case X86::COND_NP: return X86::COND_P;
4039 case X86::COND_O: return X86::COND_NO;
4040 case X86::COND_NO: return X86::COND_O;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4041 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
4042 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4043 }
4044}
4045
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4046/// Assuming the flags are set by MI(a,b), return the condition code if we
4047/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]4048static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4049 switch (CC) {
4050 default: return X86::COND_INVALID;
4051 case X86::COND_E: return X86::COND_E;
4052 case X86::COND_NE: return X86::COND_NE;
4053 case X86::COND_L: return X86::COND_G;
4054 case X86::COND_LE: return X86::COND_GE;
4055 case X86::COND_G: return X86::COND_L;
4056 case X86::COND_GE: return X86::COND_LE;
4057 case X86::COND_B: return X86::COND_A;
4058 case X86::COND_BE: return X86::COND_AE;
4059 case X86::COND_A: return X86::COND_B;
4060 case X86::COND_AE: return X86::COND_BE;
4061 }
4062}
4063
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4064/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4065/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]4066unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]4067 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4068 { X86::SETAr, X86::SETAm },
4069 { X86::SETAEr, X86::SETAEm },
4070 { X86::SETBr, X86::SETBm },
4071 { X86::SETBEr, X86::SETBEm },
4072 { X86::SETEr, X86::SETEm },
4073 { X86::SETGr, X86::SETGm },
4074 { X86::SETGEr, X86::SETGEm },
4075 { X86::SETLr, X86::SETLm },
4076 { X86::SETLEr, X86::SETLEm },
4077 { X86::SETNEr, X86::SETNEm },
4078 { X86::SETNOr, X86::SETNOm },
4079 { X86::SETNPr, X86::SETNPm },
4080 { X86::SETNSr, X86::SETNSm },
4081 { X86::SETOr, X86::SETOm },
4082 { X86::SETPr, X86::SETPm },
4083 { X86::SETSr, X86::SETSm }
4084 };
4085
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]4086 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4087 return Opc[CC][HasMemoryOperand ? 1 : 0];
4088}
4089
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4090/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4091/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]4092unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
4093 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]4094 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4095 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
4096 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
4097 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
4098 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
4099 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
4100 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
4101 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
4102 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
4103 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
4104 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
4105 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
4106 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
4107 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
4108 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
4109 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4110 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
4111 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
4112 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
4113 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
4114 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
4115 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
4116 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
4117 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
4118 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
4119 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
4120 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
4121 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
4122 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
4123 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
4124 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
4125 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
4126 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4127 };
4128
4129 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4130 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4131 switch(RegBytes) {
4132 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4133 case 2: return Opc[Idx][0];
4134 case 4: return Opc[Idx][1];
4135 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4136 }
4137}
4138
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4139bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4140 if (!MI.isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4141
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4142 // Conditional branch is a special case.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4143 if (MI.isBranch() && !MI.isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4144 return true;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4145 if (!MI.isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]4146 return true;
4147 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]4148}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4149
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4150// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
4151// not be a fallthrough MBB now due to layout changes). Return nullptr if the
4152// fallthrough MBB cannot be identified.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4153static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
4154 MachineBasicBlock *TBB) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4155 // Look for non-EHPad successors other than TBB. If we find exactly one, it
4156 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
4157 // and fallthrough MBB. If we find more than one, we cannot identify the
4158 // fallthrough MBB and should return nullptr.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4159 MachineBasicBlock *FallthroughBB = nullptr;
4160 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4161 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4162 continue;
4163 // Return a nullptr if we found more than one fallthrough successor.
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]4164 if (FallthroughBB && FallthroughBB != TBB)
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4165 return nullptr;
4166 FallthroughBB = *SI;
4167 }
4168 return FallthroughBB;
4169}
4170
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4171bool X86InstrInfo::AnalyzeBranchImpl(
4172 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
4173 SmallVectorImpl<MachineOperand> &Cond,
4174 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
4175
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4176 // Start from the bottom of the block and work up, examining the
4177 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4178 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4179 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4180 while (I != MBB.begin()) {
4181 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4182 if (I->isDebugValue())
4183 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4184
4185 // Working from the bottom, when we see a non-terminator instruction, we're
4186 // done.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]4187 if (!isUnpredicatedTerminator(*I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4188 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4189
4190 // A terminator that isn't a branch can't easily be handled by this
4191 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]4192 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4193 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4194
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4195 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4196 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4197 UnCondBrIter = I;
4198
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4199 if (!AllowModify) {
4200 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]4201 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]4202 }
4203
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4204 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]4205 while (std::next(I) != MBB.end())
4206 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4207
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4208 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4209 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4210
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4211 // Delete the JMP if it's equivalent to a fall-through.
4212 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4213 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4214 I->eraseFromParent();
4215 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4216 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4217 continue;
4218 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4219
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4220 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4221 TBB = I->getOperand(0).getMBB();
4222 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4223 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4224
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4225 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4226 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4227 if (BranchCode == X86::COND_INVALID)
4228 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4229
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4230 // Working from the bottom, handle the first conditional branch.
4231 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4232 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4233 if (AllowModify && UnCondBrIter != MBB.end() &&
4234 MBB.isLayoutSuccessor(TargetBB)) {
4235 // If we can modify the code and it ends in something like:
4236 //
4237 // jCC L1
4238 // jmp L2
4239 // L1:
4240 // ...
4241 // L2:
4242 //
4243 // Then we can change this to:
4244 //
4245 // jnCC L2
4246 // L1:
4247 // ...
4248 // L2:
4249 //
4250 // Which is a bit more efficient.
4251 // We conditionally jump to the fall-through block.
4252 BranchCode = GetOppositeBranchCondition(BranchCode);
4253 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4254 MachineBasicBlock::iterator OldInst = I;
4255
4256 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4257 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4258 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4259 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4260
4261 OldInst->eraseFromParent();
4262 UnCondBrIter->eraseFromParent();
4263
4264 // Restart the analysis.
4265 UnCondBrIter = MBB.end();
4266 I = MBB.end();
4267 continue;
4268 }
4269
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4270 FBB = TBB;
4271 TBB = I->getOperand(0).getMBB();
4272 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4273 CondBranches.push_back(&*I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4274 continue;
4275 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4276
4277 // Handle subsequent conditional branches. Only handle the case where all
4278 // conditional branches branch to the same destination and their condition
4279 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4280 assert(Cond.size() == 1);
4281 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4282
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4283 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4284 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4285 auto NewTBB = I->getOperand(0).getMBB();
4286 if (OldBranchCode == BranchCode && TBB == NewTBB)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4287 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4288
4289 // If they differ, see if they fit one of the known patterns. Theoretically,
4290 // we could handle more patterns here, but we shouldn't expect to see them
4291 // if instruction selection has done a reasonable job.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4292 if (TBB == NewTBB &&
4293 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4294 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4295 BranchCode = X86::COND_NE_OR_P;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4296 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4297 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4298 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4299 return true;
4300
4301 // X86::COND_E_AND_NP usually has two different branch destinations.
4302 //
4303 // JP B1
4304 // JE B2
4305 // JMP B1
4306 // B1:
4307 // B2:
4308 //
4309 // Here this condition branches to B2 only if NP && E. It has another
4310 // equivalent form:
4311 //
4312 // JNE B1
4313 // JNP B2
4314 // JMP B1
4315 // B1:
4316 // B2:
4317 //
4318 // Similarly it branches to B2 only if E && NP. That is why this condition
4319 // is named with COND_E_AND_NP.
4320 BranchCode = X86::COND_E_AND_NP;
4321 } else
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4322 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4323
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4324 // Update the MachineOperand.
4325 Cond[0].setImm(BranchCode);
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]4326 CondBranches.push_back(&*I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4327 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4328
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4329 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4330}
4331
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4332bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4333 MachineBasicBlock *&TBB,
4334 MachineBasicBlock *&FBB,
4335 SmallVectorImpl<MachineOperand> &Cond,
4336 bool AllowModify) const {
4337 SmallVector<MachineInstr *, 4> CondBranches;
4338 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4339}
4340
Jacques Pienaar71c30a12016-07-15 14:41:04 +0000[diff] [blame]4341bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4342 MachineBranchPredicate &MBP,
4343 bool AllowModify) const {
4344 using namespace std::placeholders;
4345
4346 SmallVector<MachineOperand, 4> Cond;
4347 SmallVector<MachineInstr *, 4> CondBranches;
4348 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4349 AllowModify))
4350 return true;
4351
4352 if (Cond.size() != 1)
4353 return true;
4354
4355 assert(MBP.TrueDest && "expected!");
4356
4357 if (!MBP.FalseDest)
4358 MBP.FalseDest = MBB.getNextNode();
4359
4360 const TargetRegisterInfo *TRI = &getRegisterInfo();
4361
4362 MachineInstr *ConditionDef = nullptr;
4363 bool SingleUseCondition = true;
4364
4365 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4366 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4367 ConditionDef = &*I;
4368 break;
4369 }
4370
4371 if (I->readsRegister(X86::EFLAGS, TRI))
4372 SingleUseCondition = false;
4373 }
4374
4375 if (!ConditionDef)
4376 return true;
4377
4378 if (SingleUseCondition) {
4379 for (auto *Succ : MBB.successors())
4380 if (Succ->isLiveIn(X86::EFLAGS))
4381 SingleUseCondition = false;
4382 }
4383
4384 MBP.ConditionDef = ConditionDef;
4385 MBP.SingleUseCondition = SingleUseCondition;
4386
4387 // Currently we only recognize the simple pattern:
4388 //
4389 // test %reg, %reg
4390 // je %label
4391 //
4392 const unsigned TestOpcode =
4393 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4394
4395 if (ConditionDef->getOpcode() == TestOpcode &&
4396 ConditionDef->getNumOperands() == 3 &&
4397 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4398 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4399 MBP.LHS = ConditionDef->getOperand(0);
4400 MBP.RHS = MachineOperand::CreateImm(0);
4401 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4402 ? MachineBranchPredicate::PRED_NE
4403 : MachineBranchPredicate::PRED_EQ;
4404 return false;
4405 }
4406
4407 return true;
4408}
4409
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4410unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4411 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4412 unsigned Count = 0;
4413
4414 while (I != MBB.begin()) {
4415 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4416 if (I->isDebugValue())
4417 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4418 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4419 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4420 break;
4421 // Remove the branch.
4422 I->eraseFromParent();
4423 I = MBB.end();
4424 ++Count;
4425 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4426
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4427 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4428}
4429
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4430unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4431 MachineBasicBlock *TBB,
4432 MachineBasicBlock *FBB,
4433 ArrayRef<MachineOperand> Cond,
4434 const DebugLoc &DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4435 // Shouldn't be a fall through.
4436 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4437 assert((Cond.size() == 1 || Cond.size() == 0) &&
4438 "X86 branch conditions have one component!");
4439
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4440 if (Cond.empty()) {
4441 // Unconditional branch?
4442 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4443 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4444 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4445 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4446
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4447 // If FBB is null, it is implied to be a fall-through block.
4448 bool FallThru = FBB == nullptr;
4449
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4450 // Conditional branch.
4451 unsigned Count = 0;
4452 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4453 switch (CC) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4454 case X86::COND_NE_OR_P:
4455 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4456 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4457 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4458 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4459 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4460 break;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4461 case X86::COND_E_AND_NP:
4462 // Use the next block of MBB as FBB if it is null.
4463 if (FBB == nullptr) {
4464 FBB = getFallThroughMBB(&MBB, TBB);
4465 assert(FBB && "MBB cannot be the last block in function when the false "
4466 "body is a fall-through.");
4467 }
4468 // Synthesize COND_E_AND_NP with two branches.
4469 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4470 ++Count;
4471 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4472 ++Count;
4473 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4474 default: {
4475 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4476 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4477 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4478 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4479 }
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4480 if (!FallThru) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4481 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4482 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4483 ++Count;
4484 }
4485 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4486}
4487
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4488bool X86InstrInfo::
4489canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4490 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4491 unsigned TrueReg, unsigned FalseReg,
4492 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4493 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4494 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4495 return false;
4496 if (Cond.size() != 1)
4497 return false;
4498 // We cannot do the composite conditions, at least not in SSA form.
4499 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4500 return false;
4501
4502 // Check register classes.
4503 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4504 const TargetRegisterClass *RC =
4505 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4506 if (!RC)
4507 return false;
4508
4509 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4510 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4511 X86::GR32RegClass.hasSubClassEq(RC) ||
4512 X86::GR64RegClass.hasSubClassEq(RC)) {
4513 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4514 // Bridge. Probably Ivy Bridge as well.
4515 CondCycles = 2;
4516 TrueCycles = 2;
4517 FalseCycles = 2;
4518 return true;
4519 }
4520
4521 // Can't do vectors.
4522 return false;
4523}
4524
4525void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4526 MachineBasicBlock::iterator I,
4527 const DebugLoc &DL, unsigned DstReg,
4528 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4529 unsigned FalseReg) const {
4530 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4531 assert(Cond.size() == 1 && "Invalid Cond array");
4532 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4533 MRI.getRegClass(DstReg)->getSize(),
4534 false /*HasMemoryOperand*/);
4535 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4536}
4537
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4538/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4539static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4540 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4541}
4542
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4543// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4544static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4545 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4546
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4547 // SrcReg(VR128) -> DestReg(GR64)
4548 // SrcReg(VR64) -> DestReg(GR64)
4549 // SrcReg(GR64) -> DestReg(VR128)
4550 // SrcReg(GR64) -> DestReg(VR64)
4551
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4552 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4553 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4554 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4555 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4556 // Copy from a VR128 register to a GR64 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4557 return HasAVX512 ? X86::VMOVPQIto64Zrr :
4558 HasAVX ? X86::VMOVPQIto64rr :
4559 X86::MOVPQIto64rr;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4560 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4561 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4562 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4563 } else if (X86::GR64RegClass.contains(SrcReg)) {
4564 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4565 if (X86::VR128XRegClass.contains(DestReg))
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4566 return HasAVX512 ? X86::VMOV64toPQIZrr :
4567 HasAVX ? X86::VMOV64toPQIrr :
4568 X86::MOV64toPQIrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4569 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4570 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4571 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4572 }
4573
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4574 // SrcReg(FR32) -> DestReg(GR32)
4575 // SrcReg(GR32) -> DestReg(FR32)
4576
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4577 if (X86::GR32RegClass.contains(DestReg) &&
4578 X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4579 // Copy from a FR32 register to a GR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4580 return HasAVX512 ? X86::VMOVSS2DIZrr :
4581 HasAVX ? X86::VMOVSS2DIrr :
4582 X86::MOVSS2DIrr;
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4583
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4584 if (X86::FR32XRegClass.contains(DestReg) &&
4585 X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4586 // Copy from a GR32 register to a FR32 register.
Craig Topper53f3d1b2016-07-18 06:14:26 +0000[diff] [blame]4587 return HasAVX512 ? X86::VMOVDI2SSZrr :
4588 HasAVX ? X86::VMOVDI2SSrr :
4589 X86::MOVDI2SSrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4590 return 0;
4591}
4592
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4593static bool isMaskRegClass(const TargetRegisterClass *RC) {
4594 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4595 return X86::VK16RegClass.hasSubClassEq(RC);
4596}
4597
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4598static bool MaskRegClassContains(unsigned Reg) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4599 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4600 return X86::VK16RegClass.contains(Reg);
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4601}
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4602
4603static bool GRRegClassContains(unsigned Reg) {
4604 return X86::GR64RegClass.contains(Reg) ||
4605 X86::GR32RegClass.contains(Reg) ||
4606 X86::GR16RegClass.contains(Reg) ||
4607 X86::GR8RegClass.contains(Reg);
4608}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4609static
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4610unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4611 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4612 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4613 return X86::KMOVBrk;
4614 }
4615 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4616 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4617 return X86::KMOVBkr;
4618 }
4619 return 0;
4620}
4621
4622static
4623unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4624 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4625 return X86::KMOVQkk;
4626 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4627 return X86::KMOVDrk;
4628 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4629 return X86::KMOVQrk;
4630 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4631 return X86::KMOVDkr;
4632 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4633 return X86::KMOVQkr;
4634 return 0;
4635}
4636
4637static
4638unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4639 const X86Subtarget &Subtarget)
4640{
4641 if (Subtarget.hasDQI())
4642 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4643 return Opc;
4644 if (Subtarget.hasBWI())
4645 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4646 return Opc;
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4647 if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
4648 if (Subtarget.hasVLX())
4649 return X86::VMOVAPSZ128rr;
4650 DestReg = get512BitSuperRegister(DestReg);
4651 SrcReg = get512BitSuperRegister(SrcReg);
4652 return X86::VMOVAPSZrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4653 }
Craig Topper5c913e82016-07-18 06:14:34 +0000[diff] [blame]4654 if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
4655 if (Subtarget.hasVLX())
4656 return X86::VMOVAPSZ256rr;
4657 DestReg = get512BitSuperRegister(DestReg);
4658 SrcReg = get512BitSuperRegister(SrcReg);
4659 return X86::VMOVAPSZrr;
4660 }
4661 if (X86::VR512RegClass.contains(DestReg, SrcReg))
4662 return X86::VMOVAPSZrr;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4663 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4664 return X86::KMOVWkk;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4665 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4666 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4667 return X86::KMOVWkr;
4668 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4669 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4670 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4671 return X86::KMOVWrk;
4672 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4673 return 0;
4674}
4675
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4676void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4677 MachineBasicBlock::iterator MI,
4678 const DebugLoc &DL, unsigned DestReg,
4679 unsigned SrcReg, bool KillSrc) const {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4680 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4681 bool HasAVX = Subtarget.hasAVX();
4682 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4683 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4684 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4685 Opc = X86::MOV64rr;
4686 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4687 Opc = X86::MOV32rr;
4688 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4689 Opc = X86::MOV16rr;
4690 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4691 // Copying to or from a physical H register on x86-64 requires a NOREX
4692 // move. Otherwise use a normal move.
4693 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4694 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4695 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4696 // Both operands must be encodable without an REX prefix.
4697 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4698 "8-bit H register can not be copied outside GR8_NOREX");
4699 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4700 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4701 }
4702 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4703 Opc = X86::MMX_MOVQ64rr;
4704 else if (HasAVX512)
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4705 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4706 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4707 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4708 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4709 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4710 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4711 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4712
4713 if (Opc) {
4714 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4715 .addReg(SrcReg, getKillRegState(KillSrc));
4716 return;
4717 }
4718
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4719 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4720 bool ToEFLAGS = DestReg == X86::EFLAGS;
4721 int Reg = FromEFLAGS ? DestReg : SrcReg;
4722 bool is32 = X86::GR32RegClass.contains(Reg);
4723 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4724
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4725 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4726 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4727 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4728 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4729 int Pop = is64 ? X86::POP64r : X86::POP32r;
4730 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4731 int AX = is64 ? X86::RAX : X86::EAX;
4732
4733 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4734 assert(Subtarget.is64Bit() &&
4735 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4736 // Moving EFLAGS to / from another register requires a push and a pop.
4737 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemer33467632015-12-27 06:07:26 +0000[diff] [blame]4738 // first frame index. See X86FrameLowering.cpp - usesTheStack.
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4739 if (FromEFLAGS) {
4740 BuildMI(MBB, MI, DL, get(PushF));
4741 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4742 }
4743 if (ToEFLAGS) {
4744 BuildMI(MBB, MI, DL, get(Push))
4745 .addReg(SrcReg, getKillRegState(KillSrc));
4746 BuildMI(MBB, MI, DL, get(PopF));
4747 }
4748 return;
4749 }
4750
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4751 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4752 // inefficient. Instead:
4753 // - Save the overflow flag OF into AL using SETO, and restore it using a
4754 // signed 8-bit addition of AL and INT8_MAX.
4755 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4756 // using LAHF/SAHF.
4757 // - When RAX/EAX is live and isn't the destination register, make sure it
4758 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4759 // the flags.
4760 // This approach is ~2.25x faster than using PUSHF/POPF.
4761 //
4762 // This is still somewhat inefficient because we don't know which flags are
4763 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4764 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4765 //
4766 // PUSHF/POPF is also potentially incorrect because it affects other flags
4767 // such as TF/IF/DF, which LLVM doesn't model.
4768 //
4769 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemerca1c9f02016-01-04 04:49:41 +0000[diff] [blame]4770 // first frame index.
4771 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4772
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4773 const TargetRegisterInfo *TRI = &getRegisterInfo();
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4774 MachineBasicBlock::LivenessQueryResult LQR =
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4775 MBB.computeRegisterLiveness(TRI, AX, MI);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4776 // We do not want to save and restore AX if we do not have to.
4777 // Moreover, if we do so whereas AX is dead, we would need to set
4778 // an undef flag on the use of AX, otherwise the verifier will
4779 // complain that we read an undef value.
4780 // We do not want to change the behavior of the machine verifier
4781 // as this is usually wrong to read an undef value.
4782 if (MachineBasicBlock::LQR_Unknown == LQR) {
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4783 LivePhysRegs LPR(TRI);
Matthias Braund1aabb22016-05-03 00:24:32 +0000[diff] [blame]4784 LPR.addLiveOuts(MBB);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4785 MachineBasicBlock::iterator I = MBB.end();
4786 while (I != MI) {
4787 --I;
4788 LPR.stepBackward(*I);
4789 }
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4790 // AX contains the top most register in the aliasing hierarchy.
4791 // It may not be live, but one of its aliases may be.
4792 for (MCRegAliasIterator AI(AX, TRI, true);
4793 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4794 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4795 : MachineBasicBlock::LQR_Dead;
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4796 }
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4797 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4798 if (!AXDead)
4799 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4800 if (FromEFLAGS) {
4801 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4802 BuildMI(MBB, MI, DL, get(X86::LAHF));
4803 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4804 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4805 if (ToEFLAGS) {
4806 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4807 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4808 .addReg(X86::AL)
4809 .addImm(INT8_MAX);
4810 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4811 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4812 if (!AXDead)
4813 BuildMI(MBB, MI, DL, get(Pop), AX);
4814 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4815 }
4816
4817 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4818 << " to " << RI.getName(DestReg) << '\n');
4819 llvm_unreachable("Cannot emit physreg copy instruction");
4820}
4821
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4822static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4823 bool load) {
4824 switch (RC->getSize()) {
4825 default:
4826 llvm_unreachable("Unknown spill size");
4827 case 2:
4828 return load ? X86::KMOVWkm : X86::KMOVWmk;
4829 case 4:
4830 return load ? X86::KMOVDkm : X86::KMOVDmk;
4831 case 8:
4832 return load ? X86::KMOVQkm : X86::KMOVQmk;
4833 }
4834}
4835
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4836static unsigned getLoadStoreRegOpcode(unsigned Reg,
4837 const TargetRegisterClass *RC,
4838 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4839 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4840 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4841 bool HasAVX = STI.hasAVX();
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4842 bool HasAVX512 = STI.hasAVX512();
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4843 bool HasVLX = STI.hasVLX();
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4844
4845 if (HasAVX512 && isMaskRegClass(RC))
4846 return getLoadStoreMaskRegOpcode(RC, load);
4847
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4848 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4849 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4850 llvm_unreachable("Unknown spill size");
4851 case 1:
4852 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4853 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4854 // Copying to or from a physical H register on x86-64 requires a NOREX
4855 // move. Otherwise use a normal move.
4856 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4857 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4858 return load ? X86::MOV8rm : X86::MOV8mr;
4859 case 2:
4860 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4861 return load ? X86::MOV16rm : X86::MOV16mr;
4862 case 4:
4863 if (X86::GR32RegClass.hasSubClassEq(RC))
4864 return load ? X86::MOV32rm : X86::MOV32mr;
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4865 if (X86::FR32XRegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4866 return load ?
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4867 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4868 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4869 if (X86::RFP32RegClass.hasSubClassEq(RC))
4870 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4871 llvm_unreachable("Unknown 4-byte regclass");
4872 case 8:
4873 if (X86::GR64RegClass.hasSubClassEq(RC))
4874 return load ? X86::MOV64rm : X86::MOV64mr;
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4875 if (X86::FR64XRegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4876 return load ?
Craig Toppereb1cc982016-07-31 20:19:55 +0000[diff] [blame]4877 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4878 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4879 if (X86::VR64RegClass.hasSubClassEq(RC))
4880 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4881 if (X86::RFP64RegClass.hasSubClassEq(RC))
4882 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4883 llvm_unreachable("Unknown 8-byte regclass");
4884 case 10:
4885 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4886 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4887 case 16: {
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4888 assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4889 // If stack is realigned we can use aligned stores.
4890 if (isStackAligned)
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4891 return load ?
4892 (HasVLX ? X86::VMOVAPSZ128rm : HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm):
4893 (HasVLX ? X86::VMOVAPSZ128mr : HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4894 else
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4895 return load ?
4896 (HasVLX ? X86::VMOVUPSZ128rm : HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm):
4897 (HasVLX ? X86::VMOVUPSZ128mr : HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4898 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4899 case 32:
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4900 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4901 // If stack is realigned we can use aligned stores.
4902 if (isStackAligned)
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4903 return load ?
4904 (HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm) :
4905 (HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr);
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4906 else
Craig Topper7afdc0f2016-07-31 20:20:05 +0000[diff] [blame]4907 return load ?
4908 (HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm) :
4909 (HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr);
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4910 case 64:
4911 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
Craig Topper338ec9a2016-07-31 20:19:53 +0000[diff] [blame]4912 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4913 if (isStackAligned)
4914 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4915 else
4916 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4917 }
4918}
4919
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4920bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
Chad Rosierc27a18f2016-03-09 16:00:35 +0000[diff] [blame]4921 int64_t &Offset,
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4922 const TargetRegisterInfo *TRI) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4923 const MCInstrDesc &Desc = MemOp.getDesc();
Craig Topper477649a2016-04-28 05:58:46 +0000[diff] [blame]4924 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4925 if (MemRefBegin < 0)
4926 return false;
4927
4928 MemRefBegin += X86II::getOperandBias(Desc);
4929
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4930 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
Sanjoy Das881de4d2016-02-02 02:32:43 +0000[diff] [blame]4931 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4932 return false;
4933
4934 BaseReg = BaseMO.getReg();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4935 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4936 return false;
4937
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4938 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4939 X86::NoRegister)
4940 return false;
4941
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4942 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4943
4944 // Displacement can be symbolic
4945 if (!DispMO.isImm())
4946 return false;
4947
4948 Offset = DispMO.getImm();
4949
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4950 return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4951 X86::NoRegister;
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4952}
4953
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4954static unsigned getStoreRegOpcode(unsigned SrcReg,
4955 const TargetRegisterClass *RC,
4956 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4957 const X86Subtarget &STI) {
4958 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4959}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4960
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4961
4962static unsigned getLoadRegOpcode(unsigned DestReg,
4963 const TargetRegisterClass *RC,
4964 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4965 const X86Subtarget &STI) {
4966 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4967}
4968
4969void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4970 MachineBasicBlock::iterator MI,
4971 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4972 const TargetRegisterClass *RC,
4973 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4974 const MachineFunction &MF = *MBB.getParent();
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]4975 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4976 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4977 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4978 bool isAligned =
4979 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4980 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4981 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4982 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4983 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4984 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4985}
4986
4987void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4988 bool isKill,
4989 SmallVectorImpl<MachineOperand> &Addr,
4990 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4991 MachineInstr::mmo_iterator MMOBegin,
4992 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4993 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4994 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4995 bool isAligned = MMOBegin != MMOEnd &&
4996 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4997 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4998 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4999 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5000 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5001 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5002 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5003 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5004 NewMIs.push_back(MIB);
5005}
5006
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5007
5008void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]5009 MachineBasicBlock::iterator MI,
5010 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]5011 const TargetRegisterClass *RC,
5012 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]5013 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]5014 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]5015 bool isAligned =
5016 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
5017 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5018 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]5019 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5020 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5021}
5022
5023void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]5024 SmallVectorImpl<MachineOperand> &Addr,
5025 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5026 MachineInstr::mmo_iterator MMOBegin,
5027 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5028 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]5029 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5030 bool isAligned = MMOBegin != MMOEnd &&
5031 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5032 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]5033 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]5034 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5035 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5036 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5037 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]5038 NewMIs.push_back(MIB);
5039}
5040
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5041bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
5042 unsigned &SrcReg2, int &CmpMask,
5043 int &CmpValue) const {
5044 switch (MI.getOpcode()) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5045 default: break;
5046 case X86::CMP64ri32:
5047 case X86::CMP64ri8:
5048 case X86::CMP32ri:
5049 case X86::CMP32ri8:
5050 case X86::CMP16ri:
5051 case X86::CMP16ri8:
5052 case X86::CMP8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5053 SrcReg = MI.getOperand(0).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5054 SrcReg2 = 0;
5055 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5056 CmpValue = MI.getOperand(1).getImm();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5057 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5058 // A SUB can be used to perform comparison.
5059 case X86::SUB64rm:
5060 case X86::SUB32rm:
5061 case X86::SUB16rm:
5062 case X86::SUB8rm:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5063 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5064 SrcReg2 = 0;
5065 CmpMask = ~0;
5066 CmpValue = 0;
5067 return true;
5068 case X86::SUB64rr:
5069 case X86::SUB32rr:
5070 case X86::SUB16rr:
5071 case X86::SUB8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5072 SrcReg = MI.getOperand(1).getReg();
5073 SrcReg2 = MI.getOperand(2).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5074 CmpMask = ~0;
5075 CmpValue = 0;
5076 return true;
5077 case X86::SUB64ri32:
5078 case X86::SUB64ri8:
5079 case X86::SUB32ri:
5080 case X86::SUB32ri8:
5081 case X86::SUB16ri:
5082 case X86::SUB16ri8:
5083 case X86::SUB8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5084 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5085 SrcReg2 = 0;
5086 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5087 CmpValue = MI.getOperand(2).getImm();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5088 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5089 case X86::CMP64rr:
5090 case X86::CMP32rr:
5091 case X86::CMP16rr:
5092 case X86::CMP8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5093 SrcReg = MI.getOperand(0).getReg();
5094 SrcReg2 = MI.getOperand(1).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5095 CmpMask = ~0;
5096 CmpValue = 0;
5097 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5098 case X86::TEST8rr:
5099 case X86::TEST16rr:
5100 case X86::TEST32rr:
5101 case X86::TEST64rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5102 SrcReg = MI.getOperand(0).getReg();
5103 if (MI.getOperand(1).getReg() != SrcReg)
5104 return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5105 // Compare against zero.
5106 SrcReg2 = 0;
5107 CmpMask = ~0;
5108 CmpValue = 0;
5109 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5110 }
5111 return false;
5112}
5113
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5114/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5115/// purpose is to update flags, can be made redundant.
5116/// CMPrr can be made redundant by SUBrr if the operands are the same.
5117/// This function can be extended later on.
5118/// SrcReg, SrcRegs: register operands for FlagI.
5119/// ImmValue: immediate for FlagI if it takes an immediate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5120inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5121 unsigned SrcReg2, int ImmValue,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5122 MachineInstr &OI) {
5123 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
5124 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
5125 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
5126 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
5127 ((OI.getOperand(1).getReg() == SrcReg &&
5128 OI.getOperand(2).getReg() == SrcReg2) ||
5129 (OI.getOperand(1).getReg() == SrcReg2 &&
5130 OI.getOperand(2).getReg() == SrcReg)))
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5131 return true;
5132
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5133 if (((FlagI.getOpcode() == X86::CMP64ri32 &&
5134 OI.getOpcode() == X86::SUB64ri32) ||
5135 (FlagI.getOpcode() == X86::CMP64ri8 &&
5136 OI.getOpcode() == X86::SUB64ri8) ||
5137 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
5138 (FlagI.getOpcode() == X86::CMP32ri8 &&
5139 OI.getOpcode() == X86::SUB32ri8) ||
5140 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
5141 (FlagI.getOpcode() == X86::CMP16ri8 &&
5142 OI.getOpcode() == X86::SUB16ri8) ||
5143 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
5144 OI.getOperand(1).getReg() == SrcReg &&
5145 OI.getOperand(2).getImm() == ImmValue)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5146 return true;
5147 return false;
5148}
5149
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5150/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5151/// to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5152inline static bool isDefConvertible(MachineInstr &MI) {
5153 switch (MI.getOpcode()) {
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5154 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]5155
5156 // The shift instructions only modify ZF if their shift count is non-zero.
5157 // N.B.: The processor truncates the shift count depending on the encoding.
5158 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
5159 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
5160 return getTruncatedShiftCount(MI, 2) != 0;
5161
5162 // Some left shift instructions can be turned into LEA instructions but only
5163 // if their flags aren't used. Avoid transforming such instructions.
5164 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
5165 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
5166 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
5167 return ShAmt != 0;
5168 }
5169
5170 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
5171 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
5172 return getTruncatedShiftCount(MI, 3) != 0;
5173
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5174 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
5175 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
5176 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
5177 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
5178 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5179 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5180 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
5181 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
5182 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
5183 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
5184 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]5185 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5186 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
5187 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
5188 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
5189 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
5190 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
5191 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
5192 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
5193 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
5194 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
5195 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
5196 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
5197 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
5198 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
5199 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
5200 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5201 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
5202 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
5203 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
5204 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
5205 case X86::ADC32ri: case X86::ADC32ri8:
5206 case X86::ADC32rr: case X86::ADC64ri32:
5207 case X86::ADC64ri8: case X86::ADC64rr:
5208 case X86::SBB32ri: case X86::SBB32ri8:
5209 case X86::SBB32rr: case X86::SBB64ri32:
5210 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]5211 case X86::ANDN32rr: case X86::ANDN32rm:
5212 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5213 case X86::BEXTR32rr: case X86::BEXTR64rr:
5214 case X86::BEXTR32rm: case X86::BEXTR64rm:
5215 case X86::BLSI32rr: case X86::BLSI32rm:
5216 case X86::BLSI64rr: case X86::BLSI64rm:
5217 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5218 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5219 case X86::BLSR32rr: case X86::BLSR32rm:
5220 case X86::BLSR64rr: case X86::BLSR64rm:
5221 case X86::BZHI32rr: case X86::BZHI32rm:
5222 case X86::BZHI64rr: case X86::BZHI64rm:
5223 case X86::LZCNT16rr: case X86::LZCNT16rm:
5224 case X86::LZCNT32rr: case X86::LZCNT32rm:
5225 case X86::LZCNT64rr: case X86::LZCNT64rm:
5226 case X86::POPCNT16rr:case X86::POPCNT16rm:
5227 case X86::POPCNT32rr:case X86::POPCNT32rm:
5228 case X86::POPCNT64rr:case X86::POPCNT64rm:
5229 case X86::TZCNT16rr: case X86::TZCNT16rm:
5230 case X86::TZCNT32rr: case X86::TZCNT32rm:
5231 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5232 return true;
5233 }
5234}
5235
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5236/// Check whether the use can be converted to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5237static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5238 switch (MI.getOpcode()) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5239 default: return X86::COND_INVALID;
5240 case X86::LZCNT16rr: case X86::LZCNT16rm:
5241 case X86::LZCNT32rr: case X86::LZCNT32rm:
5242 case X86::LZCNT64rr: case X86::LZCNT64rm:
5243 return X86::COND_B;
5244 case X86::POPCNT16rr:case X86::POPCNT16rm:
5245 case X86::POPCNT32rr:case X86::POPCNT32rm:
5246 case X86::POPCNT64rr:case X86::POPCNT64rm:
5247 return X86::COND_E;
5248 case X86::TZCNT16rr: case X86::TZCNT16rm:
5249 case X86::TZCNT32rr: case X86::TZCNT32rm:
5250 case X86::TZCNT64rr: case X86::TZCNT64rm:
5251 return X86::COND_B;
5252 }
5253}
5254
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5255/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5256/// operates on the same source operands and sets flags in the same way as
5257/// Compare; remove Compare if possible.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5258bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5259 unsigned SrcReg2, int CmpMask,
5260 int CmpValue,
5261 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5262 // Check whether we can replace SUB with CMP.
5263 unsigned NewOpcode = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5264 switch (CmpInstr.getOpcode()) {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5265 default: break;
5266 case X86::SUB64ri32:
5267 case X86::SUB64ri8:
5268 case X86::SUB32ri:
5269 case X86::SUB32ri8:
5270 case X86::SUB16ri:
5271 case X86::SUB16ri8:
5272 case X86::SUB8ri:
5273 case X86::SUB64rm:
5274 case X86::SUB32rm:
5275 case X86::SUB16rm:
5276 case X86::SUB8rm:
5277 case X86::SUB64rr:
5278 case X86::SUB32rr:
5279 case X86::SUB16rr:
5280 case X86::SUB8rr: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5281 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5282 return false;
5283 // There is no use of the destination register, we can replace SUB with CMP.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5284 switch (CmpInstr.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5285 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5286 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5287 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5288 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5289 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5290 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5291 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5292 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5293 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5294 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5295 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5296 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5297 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5298 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5299 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5300 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5301 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5302 CmpInstr.setDesc(get(NewOpcode));
5303 CmpInstr.RemoveOperand(0);
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5304 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5305 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5306 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5307 return false;
5308 }
5309 }
5310
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5311 // Get the unique definition of SrcReg.
5312 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5313 if (!MI) return false;
5314
5315 // CmpInstr is the first instruction of the BB.
5316 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5317
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5318 // If we are comparing against zero, check whether we can use MI to update
5319 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5320 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5321 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5322 return false;
5323
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5324 // If we have a use of the source register between the def and our compare
5325 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5326 // right way.
5327 bool ShouldUpdateCC = false;
5328 X86::CondCode NewCC = X86::COND_INVALID;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5329 if (IsCmpZero && !isDefConvertible(*MI)) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5330 // Scan forward from the use until we hit the use we're looking for or the
5331 // compare instruction.
5332 for (MachineBasicBlock::iterator J = MI;; ++J) {
5333 // Do we have a convertible instruction?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5334 NewCC = isUseDefConvertible(*J);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5335 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5336 J->getOperand(1).getReg() == SrcReg) {
5337 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5338 ShouldUpdateCC = true; // Update CC later on.
5339 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5340 // with the new def.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]5341 Def = J;
5342 MI = &*Def;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5343 break;
5344 }
5345
5346 if (J == I)
5347 return false;
5348 }
5349 }
5350
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5351 // We are searching for an earlier instruction that can make CmpInstr
5352 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5353 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5354 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5355
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5356 // We iterate backward, starting from the instruction before CmpInstr and
5357 // stop when reaching the definition of a source register or done with the BB.
5358 // RI points to the instruction before CmpInstr.
5359 // If the definition is in this basic block, RE points to the definition;
5360 // otherwise, RE is the rend of the basic block.
5361 MachineBasicBlock::reverse_iterator
5362 RI = MachineBasicBlock::reverse_iterator(I),
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5363 RE = CmpInstr.getParent() == MI->getParent()
5364 ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5365 : CmpInstr.getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5366 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5367 for (; RI != RE; ++RI) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5368 MachineInstr &Instr = *RI;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5369 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5370 if (!IsCmpZero &&
5371 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5372 Sub = &Instr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5373 break;
5374 }
5375
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5376 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5377 Instr.readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5378 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5379
5380 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5381 // They are safe to move up, if the definition to EFLAGS is dead and
5382 // earlier instructions do not read or write EFLAGS.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5383 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5384 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5385 Movr0Inst = &Instr;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5386 continue;
5387 }
5388
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5389 // We can't remove CmpInstr.
5390 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5391 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5392 }
5393
5394 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5395 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5396 return false;
5397
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5398 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5399 Sub->getOperand(2).getReg() == SrcReg);
5400
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5401 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5402 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5403 // If we are done with the basic block, we need to check whether EFLAGS is
5404 // live-out.
5405 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5406 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5407 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5408 for (++I; I != E; ++I) {
5409 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5410 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5411 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5412 // We should check the usage if this instruction uses and updates EFLAGS.
5413 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5414 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5415 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5416 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5417 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5418 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5419 continue;
5420
5421 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5422 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5423 bool OpcIsSET = false;
5424 if (IsCmpZero || IsSwapped) {
5425 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5426 if (Instr.isBranch())
5427 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5428 else {
5429 OldCC = getCondFromSETOpc(Instr.getOpcode());
5430 if (OldCC != X86::COND_INVALID)
5431 OpcIsSET = true;
5432 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5433 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5434 }
5435 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5436 }
5437 if (IsCmpZero) {
5438 switch (OldCC) {
5439 default: break;
5440 case X86::COND_A: case X86::COND_AE:
5441 case X86::COND_B: case X86::COND_BE:
5442 case X86::COND_G: case X86::COND_GE:
5443 case X86::COND_L: case X86::COND_LE:
5444 case X86::COND_O: case X86::COND_NO:
5445 // CF and OF are used, we can't perform this optimization.
5446 return false;
5447 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5448
5449 // If we're updating the condition code check if we have to reverse the
5450 // condition.
5451 if (ShouldUpdateCC)
5452 switch (OldCC) {
5453 default:
5454 return false;
5455 case X86::COND_E:
5456 break;
5457 case X86::COND_NE:
5458 NewCC = GetOppositeBranchCondition(NewCC);
5459 break;
5460 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5461 } else if (IsSwapped) {
5462 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5463 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5464 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5465 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5466 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5467 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5468
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5469 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5470 // Synthesize the new opcode.
5471 bool HasMemoryOperand = Instr.hasOneMemOperand();
5472 unsigned NewOpc;
5473 if (Instr.isBranch())
5474 NewOpc = GetCondBranchFromCond(NewCC);
5475 else if(OpcIsSET)
5476 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5477 else {
5478 unsigned DstReg = Instr.getOperand(0).getReg();
5479 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5480 HasMemoryOperand);
5481 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5482
5483 // Push the MachineInstr to OpsToUpdate.
5484 // If it is safe to remove CmpInstr, the condition code of these
5485 // instructions will be modified.
5486 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5487 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5488 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5489 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5490 IsSafe = true;
5491 break;
5492 }
5493 }
5494
5495 // If EFLAGS is not killed nor re-defined, we should check whether it is
5496 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5497 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5498 MachineBasicBlock *MBB = CmpInstr.getParent();
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5499 for (MachineBasicBlock *Successor : MBB->successors())
5500 if (Successor->isLiveIn(X86::EFLAGS))
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5501 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5502 }
5503
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5504 // The instruction to be updated is either Sub or MI.
5505 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5506 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5507 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5508 // Look backwards until we find a def that doesn't use the current EFLAGS.
5509 Def = Sub;
5510 MachineBasicBlock::reverse_iterator
5511 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5512 InsertE = Sub->getParent()->rend();
5513 for (; InsertI != InsertE; ++InsertI) {
5514 MachineInstr *Instr = &*InsertI;
5515 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5516 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5517 Sub->getParent()->remove(Movr0Inst);
5518 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5519 Movr0Inst);
5520 break;
5521 }
5522 }
5523 if (InsertI == InsertE)
5524 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5525 }
5526
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5527 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5528 unsigned i = 0, e = Sub->getNumOperands();
5529 for (; i != e; ++i) {
5530 MachineOperand &MO = Sub->getOperand(i);
5531 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5532 MO.setIsDead(false);
5533 break;
5534 }
5535 }
5536 assert(i != e && "Unable to locate a def EFLAGS operand");
5537
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5538 CmpInstr.eraseFromParent();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5539
5540 // Modify the condition code of instructions in OpsToUpdate.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5541 for (auto &Op : OpsToUpdate)
5542 Op.first->setDesc(get(Op.second));
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5543 return true;
5544}
5545
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5546/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5547/// operand at the use. We fold the load instructions if load defines a virtual
5548/// register, the virtual register is used once in the same BB, and the
5549/// instructions in-between do not load or store, and have no side effects.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5550MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5551 const MachineRegisterInfo *MRI,
5552 unsigned &FoldAsLoadDefReg,
5553 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5554 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5555 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5556 // To be conservative, if there exists another load, clear the load candidate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5557 if (MI.mayLoad()) {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5558 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5559 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5560 }
5561
5562 // Check whether we can move DefMI here.
5563 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5564 assert(DefMI);
5565 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5566 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5567 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5568
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5569 // Collect information about virtual register operands of MI.
5570 unsigned SrcOperandId = 0;
5571 bool FoundSrcOperand = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5572 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5573 MachineOperand &MO = MI.getOperand(i);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5574 if (!MO.isReg())
5575 continue;
5576 unsigned Reg = MO.getReg();
5577 if (Reg != FoldAsLoadDefReg)
5578 continue;
5579 // Do not fold if we have a subreg use or a def or multiple uses.
5580 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5581 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5582
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5583 SrcOperandId = i;
5584 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5585 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5586 if (!FoundSrcOperand)
5587 return nullptr;
5588
5589 // Check whether we can fold the def into SrcOperandId.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5590 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5591 FoldAsLoadDefReg = 0;
5592 return FoldMI;
5593 }
5594
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5595 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5596}
5597
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5598/// Expand a single-def pseudo instruction to a two-addr
5599/// instruction with two undef reads of the register being defined.
5600/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5601/// %xmm4 = V_SET0
5602/// to:
5603/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5604///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5605static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5606 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5607 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5608 unsigned Reg = MIB->getOperand(0).getReg();
5609 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5610
5611 // MachineInstr::addOperand() will insert explicit operands before any
5612 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5613 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5614 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5615 assert(MIB->getOperand(1).getReg() == Reg &&
5616 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5617 return true;
5618}
5619
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5620/// Expand a single-def pseudo instruction to a two-addr
5621/// instruction with two %k0 reads.
5622/// This is used for mapping:
5623/// %k4 = K_SET1
5624/// to:
5625/// %k4 = KXNORrr %k0, %k0
5626static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5627 const MCInstrDesc &Desc, unsigned Reg) {
5628 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5629 MIB->setDesc(Desc);
5630 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5631 return true;
5632}
5633
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5634static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5635 bool MinusOne) {
5636 MachineBasicBlock &MBB = *MIB->getParent();
5637 DebugLoc DL = MIB->getDebugLoc();
5638 unsigned Reg = MIB->getOperand(0).getReg();
5639
5640 // Insert the XOR.
5641 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5642 .addReg(Reg, RegState::Undef)
5643 .addReg(Reg, RegState::Undef);
5644
5645 // Turn the pseudo into an INC or DEC.
5646 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5647 MIB.addReg(Reg);
5648
5649 return true;
5650}
5651
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5652bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5653 MachineBasicBlock &MBB = *MIB->getParent();
5654 DebugLoc DL = MIB->getDebugLoc();
5655 int64_t Imm = MIB->getOperand(1).getImm();
5656 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5657 MachineBasicBlock::iterator I = MIB.getInstr();
5658
5659 int StackAdjustment;
5660
5661 if (Subtarget.is64Bit()) {
5662 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5663 MIB->getOpcode() == X86::MOV32ImmSExti8);
5664
5665 // Can't use push/pop lowering if the function might write to the red zone.
5666 X86MachineFunctionInfo *X86FI =
5667 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5668 if (X86FI->getUsesRedZone()) {
5669 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5670 : X86::MOV64ri));
5671 return true;
5672 }
5673
5674 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5675 // widen the register if necessary.
5676 StackAdjustment = 8;
5677 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5678 MIB->setDesc(get(X86::POP64r));
5679 MIB->getOperand(0)
5680 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5681 } else {
5682 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5683 StackAdjustment = 4;
5684 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5685 MIB->setDesc(get(X86::POP32r));
5686 }
5687
5688 // Build CFI if necessary.
5689 MachineFunction &MF = *MBB.getParent();
5690 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5691 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5692 bool NeedsDwarfCFI =
5693 !IsWin64Prologue &&
5694 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5695 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5696 if (EmitCFI) {
5697 TFL->BuildCFI(MBB, I, DL,
5698 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5699 TFL->BuildCFI(MBB, std::next(I), DL,
5700 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5701 }
5702
5703 return true;
5704}
5705
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5706// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5707// code sequence is needed for other targets.
5708static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5709 const TargetInstrInfo &TII) {
5710 MachineBasicBlock &MBB = *MIB->getParent();
5711 DebugLoc DL = MIB->getDebugLoc();
5712 unsigned Reg = MIB->getOperand(0).getReg();
5713 const GlobalValue *GV =
5714 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5715 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5716 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
Justin Lebar0af80cd2016-07-15 18:26:59 +0000[diff] [blame]5717 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5718 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5719
5720 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5721 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5722 .addMemOperand(MMO);
5723 MIB->setDebugLoc(DL);
5724 MIB->setDesc(TII.get(X86::MOV64rm));
5725 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5726}
5727
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5728bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5729 bool HasAVX = Subtarget.hasAVX();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5730 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5731 switch (MI.getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5732 case X86::MOV32r0:
5733 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5734 case X86::MOV32r1:
5735 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5736 case X86::MOV32r_1:
5737 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5738 case X86::MOV32ImmSExti8:
5739 case X86::MOV64ImmSExti8:
5740 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5741 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5742 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5743 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5744 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5745 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5746 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5747 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5748 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5749 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5750 case X86::FsFLD0SS:
5751 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5752 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5753 case X86::AVX_SET0:
5754 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5755 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Craig Toppere5ce84a2016-05-08 21:33:53 +0000[diff] [blame]5756 case X86::AVX512_128_SET0:
5757 return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5758 case X86::AVX512_256_SET0:
5759 return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5760 case X86::AVX512_512_SET0:
5761 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5762 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5763 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5764 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5765 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]5766 case X86::AVX512_512_SETALLONES: {
5767 unsigned Reg = MIB->getOperand(0).getReg();
5768 MIB->setDesc(get(X86::VPTERNLOGDZrri));
5769 // VPTERNLOGD needs 3 register inputs and an immediate.
5770 // 0xff will return 1s for any input.
5771 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5772 .addReg(Reg, RegState::Undef).addImm(0xff);
5773 return true;
5774 }
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5775 case X86::TEST8ri_NOREX:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5776 MI.setDesc(get(X86::TEST8ri));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5777 return true;
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5778 case X86::MOV32ri64:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5779 MI.setDesc(get(X86::MOV32ri));
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5780 return true;
5781
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5782 // KNL does not recognize dependency-breaking idioms for mask registers,
5783 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5784 // Using %k0 as the undef input register is a performance heuristic based
5785 // on the assumption that %k0 is used less frequently than the other mask
5786 // registers, since it is not usable as a write mask.
5787 // FIXME: A more advanced approach would be to choose the best input mask
5788 // register based on context.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5789 case X86::KSET0B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5790 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5791 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5792 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5793 case X86::KSET1B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5794 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5795 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5796 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5797 case TargetOpcode::LOAD_STACK_GUARD:
5798 expandLoadStackGuard(MIB, *this);
5799 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5800 }
5801 return false;
5802}
5803
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5804static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5805 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5806 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5807
5808 if (NumAddrOps < 4) {
5809 // FrameIndex only - add an immediate offset (whether its zero or not).
5810 for (unsigned i = 0; i != NumAddrOps; ++i)
5811 MIB.addOperand(MOs[i]);
5812 addOffset(MIB, PtrOffset);
5813 } else {
5814 // General Memory Addressing - we need to add any offset to an existing
5815 // offset.
5816 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5817 for (unsigned i = 0; i != NumAddrOps; ++i) {
5818 const MachineOperand &MO = MOs[i];
5819 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5820 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5821 } else {
5822 MIB.addOperand(MO);
5823 }
5824 }
5825 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5826}
5827
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5828static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5829 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5830 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5831 MachineInstr &MI,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5832 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5833 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5834 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5835 MachineInstr *NewMI =
5836 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5837 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5838 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5839
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5840 // Loop over the rest of the ri operands, converting them over.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5841 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5842 for (unsigned i = 0; i != NumOps; ++i) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5843 MachineOperand &MO = MI.getOperand(i + 2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5844 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5845 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5846 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5847 MachineOperand &MO = MI.getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5848 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5849 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5850
5851 MachineBasicBlock *MBB = InsertPt->getParent();
5852 MBB->insert(InsertPt, NewMI);
5853
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5854 return MIB;
5855}
5856
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5857static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5858 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5859 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5860 MachineInstr &MI, const TargetInstrInfo &TII,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5861 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5862 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5863 MachineInstr *NewMI =
5864 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5865 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5866
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5867 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5868 MachineOperand &MO = MI.getOperand(i);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5869 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5870 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5871 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5872 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5873 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5874 }
5875 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5876
5877 MachineBasicBlock *MBB = InsertPt->getParent();
5878 MBB->insert(InsertPt, NewMI);
5879
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5880 return MIB;
5881}
5882
5883static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5884 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5885 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5886 MachineInstr &MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5887 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5888 MI.getDebugLoc(), TII.get(Opcode));
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5889 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5890 return MIB.addImm(0);
5891}
5892
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5893MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5894 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5895 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5896 unsigned Size, unsigned Align) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5897 switch (MI.getOpcode()) {
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5898 case X86::INSERTPSrr:
5899 case X86::VINSERTPSrr:
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5900 case X86::VINSERTPSZrr:
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5901 // Attempt to convert the load of inserted vector into a fold load
5902 // of a single float.
5903 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5904 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5905 unsigned ZMask = Imm & 15;
5906 unsigned DstIdx = (Imm >> 4) & 3;
5907 unsigned SrcIdx = (Imm >> 6) & 3;
5908
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5909 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5910 if (Size <= RCSize && 4 <= Align) {
5911 int PtrOffset = SrcIdx * 4;
5912 unsigned NewImm = (DstIdx << 4) | ZMask;
5913 unsigned NewOpCode =
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5914 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5915 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
5916 X86::INSERTPSrm;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5917 MachineInstr *NewMI =
5918 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5919 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5920 return NewMI;
5921 }
5922 }
5923 break;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5924 case X86::MOVHLPSrr:
5925 case X86::VMOVHLPSrr:
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5926 case X86::VMOVHLPSZrr:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5927 // Move the upper 64-bits of the second operand to the lower 64-bits.
5928 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5929 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5930 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5931 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5932 if (Size <= RCSize && 8 <= Align) {
5933 unsigned NewOpCode =
Craig Topperab13b332016-07-22 05:00:35 +0000[diff] [blame]5934 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5935 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
5936 X86::MOVLPSrm;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5937 MachineInstr *NewMI =
5938 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5939 return NewMI;
5940 }
5941 }
5942 break;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5943 };
5944
5945 return nullptr;
5946}
5947
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5948MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5949 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5950 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5951 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5952 const DenseMap<unsigned,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5953 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5954 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5955 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5956
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5957 // For CPUs that favor the register form of a call or push,
5958 // do not fold loads into calls or pushes, unless optimizing for size
5959 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5960 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5961 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5962 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5963 MI.getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5964 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5965
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5966 unsigned NumOps = MI.getDesc().getNumOperands();
5967 bool isTwoAddr =
5968 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5969
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5970 // FIXME: AsmPrinter doesn't know how to handle
5971 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5972 if (MI.getOpcode() == X86::ADD32ri &&
5973 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5974 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5975
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5976 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5977
5978 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5979 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5980 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5981 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5982
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5983 // Folding a memory location into the two-address part of a two-address
5984 // instruction is different than folding it other places. It requires
5985 // replacing the *two* registers with the memory location.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5986 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5987 MI.getOperand(1).isReg() &&
5988 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5989 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5990 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5991 } else if (OpNum == 0) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5992 if (MI.getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5993 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5994 if (NewMI)
5995 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5996 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5997
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5998 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5999 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6000 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]6001 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6002 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]6003 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]6004 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]6005 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]6006 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6007 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6008
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6009 // If table selected...
6010 if (OpcodeTablePtr) {
6011 // Find the Opcode to fuse
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6012 auto I = OpcodeTablePtr->find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6013 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6014 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6015 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]6016 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6017 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6018 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6019 if (Size) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6020 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6021 if (Size < RCSize) {
6022 // Check if it's safe to fold the load. If the size of the object is
6023 // narrower than the load width, then it's not.
6024 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6025 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6026 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6027 // a 32-bit load which is implicitly zero-extended. This likely is
6028 // due to live interval analysis remat'ing a load from stack slot.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6029 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6030 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6031 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6032 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6033 }
6034 }
6035
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6036 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6037 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6038 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6039 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6040
6041 if (NarrowToMOV32rm) {
6042 // If this is the special case where we use a MOV32rm to load a 32-bit
6043 // value and zero-extend the top bits. Change the destination register
6044 // to a 32-bit one.
6045 unsigned DstReg = NewMI->getOperand(0).getReg();
6046 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6047 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6048 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]6049 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]6050 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6051 return NewMI;
6052 }
6053 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6054
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6055 // If the instruction and target operand are commutable, commute the
6056 // instruction and try again.
6057 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6058 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6059 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6060 bool HasDef = MI.getDesc().getNumDefs();
6061 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
6062 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
6063 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6064 bool Tied1 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6065 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6066 bool Tied2 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6067 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6068
6069 // If either of the commutable operands are tied to the destination
6070 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6071 if ((HasDef && Reg0 == Reg1 && Tied1) ||
6072 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6073 return nullptr;
6074
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6075 MachineInstr *CommutedMI =
6076 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6077 if (!CommutedMI) {
6078 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6079 return nullptr;
6080 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6081 if (CommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6082 // New instruction. We can't fold from this.
6083 CommutedMI->eraseFromParent();
6084 return nullptr;
6085 }
6086
6087 // Attempt to fold with the commuted version of the instruction.
6088 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
6089 Size, Align, /*AllowCommute=*/false);
6090 if (NewMI)
6091 return NewMI;
6092
6093 // Folding failed again - undo the commute before returning.
6094 MachineInstr *UncommutedMI =
6095 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6096 if (!UncommutedMI) {
6097 // Unable to commute.
6098 return nullptr;
6099 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6100 if (UncommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]6101 // New instruction. It doesn't need to be kept.
6102 UncommutedMI->eraseFromParent();
6103 return nullptr;
6104 }
6105
6106 // Return here to prevent duplicate fuse failure report.
6107 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6108 }
6109 }
6110
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6111 // No fusion
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6112 if (PrintFailedFusing && !MI.isCopy())
6113 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6114 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6115}
6116
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6117/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6118/// the first 32 or 64-bits of the destination register and leave the rest
6119/// unmodified. This can be used to avoid folding loads if the instructions
6120/// only update part of the destination register, and the non-updated part is
6121/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6122/// instructions breaks the partial register dependency and it can improve
6123/// performance. e.g.:
6124///
6125/// movss (%rdi), %xmm0
6126/// cvtss2sd %xmm0, %xmm0
6127///
6128/// Instead of
6129/// cvtss2sd (%rdi), %xmm0
6130///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]6131/// FIXME: This should be turned into a TSFlags.
6132///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6133static bool hasPartialRegUpdate(unsigned Opcode) {
6134 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6135 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6136 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6137 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6138 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6139 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6140 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6141 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6142 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6143 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6144 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6145 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6146 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6147 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6148 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6149 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6150 case X86::Int_CVTSS2SDrm:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]6151 case X86::MOVHPDrm:
6152 case X86::MOVHPSrm:
6153 case X86::MOVLPDrm:
6154 case X86::MOVLPSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6155 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6156 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6157 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6158 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6159 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6160 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6161 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6162 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6163 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]6164 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6165 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6166 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6167 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6168 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6169 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6170 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6171 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]6172 case X86::SQRTSSm_Int:
6173 case X86::SQRTSDr:
6174 case X86::SQRTSDm:
6175 case X86::SQRTSDr_Int:
6176 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6177 return true;
6178 }
6179
6180 return false;
6181}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6182
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6183/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6184/// instructions we would like before a partial register update.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6185unsigned X86InstrInfo::getPartialRegUpdateClearance(
6186 const MachineInstr &MI, unsigned OpNum,
6187 const TargetRegisterInfo *TRI) const {
6188 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6189 return 0;
6190
6191 // If MI is marked as reading Reg, the partial register update is wanted.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6192 const MachineOperand &MO = MI.getOperand(0);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6193 unsigned Reg = MO.getReg();
6194 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6195 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6196 return 0;
6197 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6198 if (MI.readsRegister(Reg, TRI))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6199 return 0;
6200 }
6201
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6202 // If any instructions in the clearance range are reading Reg, insert a
6203 // dependency breaking instruction, which is inexpensive and is likely to
6204 // be hidden in other instruction's cycles.
6205 return PartialRegUpdateClearance;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6206}
6207
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6208// Return true for any instruction the copies the high bits of the first source
6209// operand into the unused high bits of the destination operand.
6210static bool hasUndefRegUpdate(unsigned Opcode) {
6211 switch (Opcode) {
6212 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6213 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6214 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6215 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6216 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6217 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6218 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6219 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6220 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6221 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6222 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6223 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6224 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6225 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6226 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6227 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6228 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6229 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6230 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6231 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6232 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6233 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6234 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6235 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6236 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6237 case X86::VRCPSSm:
6238 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6239 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6240 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6241 case X86::VROUNDSDr_Int:
6242 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6243 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6244 case X86::VROUNDSSr_Int:
6245 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6246 case X86::VRSQRTSSm:
6247 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6248 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6249 case X86::VSQRTSSm:
6250 case X86::VSQRTSSm_Int:
6251 case X86::VSQRTSDr:
6252 case X86::VSQRTSDm:
6253 case X86::VSQRTSDm_Int:
6254 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6255 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6256 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6257 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6258 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6259 return true;
6260 }
6261
6262 return false;
6263}
6264
6265/// Inform the ExeDepsFix pass how many idle instructions we would like before
6266/// certain undef register reads.
6267///
6268/// This catches the VCVTSI2SD family of instructions:
6269///
6270/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6271///
6272/// We should to be careful *not* to catch VXOR idioms which are presumably
6273/// handled specially in the pipeline:
6274///
6275/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6276///
6277/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6278/// high bits that are passed-through are not live.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6279unsigned
6280X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6281 const TargetRegisterInfo *TRI) const {
6282 if (!hasUndefRegUpdate(MI.getOpcode()))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6283 return 0;
6284
6285 // Set the OpNum parameter to the first source operand.
6286 OpNum = 1;
6287
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6288 const MachineOperand &MO = MI.getOperand(OpNum);
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6289 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6290 return UndefRegClearance;
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6291 }
6292 return 0;
6293}
6294
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6295void X86InstrInfo::breakPartialRegDependency(
6296 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6297 unsigned Reg = MI.getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6298 // If MI kills this register, the false dependence is already broken.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6299 if (MI.killsRegister(Reg, TRI))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6300 return;
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6301
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6302 if (X86::VR128RegClass.contains(Reg)) {
6303 // These instructions are all floating point domain, so xorps is the best
6304 // choice.
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6305 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6306 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6307 .addReg(Reg, RegState::Undef)
6308 .addReg(Reg, RegState::Undef);
6309 MI.addRegisterKilled(Reg, TRI, true);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6310 } else if (X86::VR256RegClass.contains(Reg)) {
6311 // Use vxorps to clear the full ymm register.
6312 // It wants to read and write the xmm sub-register.
6313 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6314 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6315 .addReg(XReg, RegState::Undef)
6316 .addReg(XReg, RegState::Undef)
6317 .addReg(Reg, RegState::ImplicitDefine);
6318 MI.addRegisterKilled(Reg, TRI, true);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6319 }
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6320}
6321
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6322MachineInstr *
6323X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6324 ArrayRef<unsigned> Ops,
6325 MachineBasicBlock::iterator InsertPt,
6326 int FrameIndex, LiveIntervals *LIS) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6327 // Check switch flag
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6328 if (NoFusing)
6329 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6330
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6331 // Unless optimizing for size, don't fold to avoid partial
6332 // register update stalls
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6333 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6334 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6335
Matthias Braun941a7052016-07-28 18:40:00 +0000[diff] [blame]6336 const MachineFrameInfo &MFI = MF.getFrameInfo();
6337 unsigned Size = MFI.getObjectSize(FrameIndex);
6338 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]6339 // If the function stack isn't realigned we don't want to fold instructions
6340 // that need increased alignment.
6341 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6342 Alignment =
6343 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6344 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6345 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6346 unsigned RCSize = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6347 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6348 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6349 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]6350 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6351 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6352 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6353 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6354 // Check if it's safe to fold the load. If the size of the object is
6355 // narrower than the load width, then it's not.
6356 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6357 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6358 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6359 MI.setDesc(get(NewOpc));
6360 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6361 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6362 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6363
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]6364 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6365 MachineOperand::CreateFI(FrameIndex), InsertPt,
6366 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6367}
6368
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6369/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6370/// because the latter uses contents that wouldn't be defined in the folded
6371/// version. For instance, this transformation isn't legal:
6372/// movss (%rdi), %xmm0
6373/// addps %xmm0, %xmm0
6374/// ->
6375/// addps (%rdi), %xmm0
6376///
6377/// But this one is:
6378/// movss (%rdi), %xmm0
6379/// addss %xmm0, %xmm0
6380/// ->
6381/// addss (%rdi), %xmm0
6382///
6383static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6384 const MachineInstr &UserMI,
6385 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6386 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6387 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6388 unsigned RegSize =
6389 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6390
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6391 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
6392 RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6393 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6394 // destination register is wider than 32 bits (4 bytes), and its user
6395 // instruction isn't scalar (SS).
6396 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6397 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
6398 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
6399 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6400 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]6401 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
6402 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
6403 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
6404 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
6405 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
6406 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6407 return false;
6408 default:
6409 return true;
6410 }
6411 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6412
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6413 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
6414 RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6415 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6416 // destination register is wider than 64 bits (8 bytes), and its user
6417 // instruction isn't scalar (SD).
6418 switch (UserOpc) {
Craig Toppera3c55f52016-07-18 06:49:32 +0000[diff] [blame]6419 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6420 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6421 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6422 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
Craig Topper2dca3b22016-07-24 08:26:38 +0000[diff] [blame]6423 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
6424 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
6425 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
6426 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
6427 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
6428 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6429 return false;
6430 default:
6431 return true;
6432 }
6433 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6434
6435 return false;
6436}
6437
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6438MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6439 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6440 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6441 LiveIntervals *LIS) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6442 // If loading from a FrameIndex, fold directly from the FrameIndex.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6443 unsigned NumOps = LoadMI.getDesc().getNumOperands();
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6444 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6445 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6446 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6447 return nullptr;
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6448 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6449 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6450
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6451 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6452 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6453
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6454 // Avoid partial register update stalls unless optimizing for size.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6455 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6456 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6457
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6458 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6459 unsigned Alignment = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6460 if (LoadMI.hasOneMemOperand())
6461 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6462 else
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6463 switch (LoadMI.getOpcode()) {
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6464 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6465 case X86::AVX512_512_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6466 Alignment = 64;
6467 break;
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6468 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6469 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6470 case X86::AVX512_256_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6471 Alignment = 32;
6472 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6473 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6474 case X86::V_SETALLONES:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6475 case X86::AVX512_128_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6476 Alignment = 16;
6477 break;
6478 case X86::FsFLD0SD:
6479 Alignment = 8;
6480 break;
6481 case X86::FsFLD0SS:
6482 Alignment = 4;
6483 break;
6484 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6485 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6486 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6487 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6488 unsigned NewOpc = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6489 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6490 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6491 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6492 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6493 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6494 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6495 }
6496 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6497 MI.setDesc(get(NewOpc));
6498 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6499 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6500 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6501
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6502 // Make sure the subregisters match.
6503 // Otherwise we risk changing the size of the load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6504 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6505 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6506
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6507 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6508 switch (LoadMI.getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6509 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6510 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6511 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6512 case X86::AVX_SET0:
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6513 case X86::AVX512_128_SET0:
6514 case X86::AVX512_256_SET0:
6515 case X86::AVX512_512_SET0:
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6516 case X86::AVX512_512_SETALLONES:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6517 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6518 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6519 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6520 // Create a constant-pool entry and operands to load from it.
6521
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6522 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6523 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6524 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6525 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6526
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6527 // x86-32 PIC requires a PIC base register for constant pools.
6528 unsigned PICBase = 0;
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]6529 if (MF.getTarget().isPositionIndependent()) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6530 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6531 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6532 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6533 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6534 // This doesn't work for several reasons.
6535 // 1. GlobalBaseReg may have been spilled.
6536 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6537 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6538 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6539
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6540 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6541 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6542 Type *Ty;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6543 unsigned Opc = LoadMI.getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6544 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6545 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6546 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6547 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6548 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
Craig Topper86748492016-07-11 05:36:41 +0000[diff] [blame]6549 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6550 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6551 Opc == X86::AVX512_256_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6552 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6553 else
6554 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6555
Craig Topper516e14c2016-07-11 05:36:48 +0000[diff] [blame]6556 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6557 Opc == X86::AVX512_512_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6558 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6559 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6560 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6561
6562 // Create operands to load from the constant pool entry.
6563 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6564 MOs.push_back(MachineOperand::CreateImm(1));
6565 MOs.push_back(MachineOperand::CreateReg(0, false));
6566 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6567 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6568 break;
6569 }
6570 default: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6571 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6572 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6573
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6574 // Folding a normal load. Just copy the load's address operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6575 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6576 LoadMI.operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6577 break;
6578 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6579 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6580 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6581 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6582}
6583
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6584bool X86InstrInfo::unfoldMemoryOperand(
6585 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6586 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6587 auto I = MemOp2RegOpTable.find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6588 if (I == MemOp2RegOpTable.end())
6589 return false;
6590 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6591 unsigned Index = I->second.second & TB_INDEX_MASK;
6592 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6593 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6594 if (UnfoldLoad && !FoldedLoad)
6595 return false;
6596 UnfoldLoad &= FoldedLoad;
6597 if (UnfoldStore && !FoldedStore)
6598 return false;
6599 UnfoldStore &= FoldedStore;
6600
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6601 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6602 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6603 // TODO: Check if 32-byte or greater accesses are slow too?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6604 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6605 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6606 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6607 // conservatively assume the address is unaligned. That's bad for
6608 // performance.
6609 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6610 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6611 SmallVector<MachineOperand,2> BeforeOps;
6612 SmallVector<MachineOperand,2> AfterOps;
6613 SmallVector<MachineOperand,4> ImpOps;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6614 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6615 MachineOperand &Op = MI.getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6616 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6617 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6618 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6619 ImpOps.push_back(Op);
6620 else if (i < Index)
6621 BeforeOps.push_back(Op);
6622 else if (i > Index)
6623 AfterOps.push_back(Op);
6624 }
6625
6626 // Emit the load instruction.
6627 if (UnfoldLoad) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6628 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6629 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6630 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6631 if (UnfoldStore) {
6632 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6633 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6634 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6635 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6636 MO.setIsKill(false);
6637 }
6638 }
6639 }
6640
6641 // Emit the data processing instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6642 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6643 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6644
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6645 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6646 MIB.addReg(Reg, RegState::Define);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6647 for (MachineOperand &BeforeOp : BeforeOps)
6648 MIB.addOperand(BeforeOp);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6649 if (FoldedLoad)
6650 MIB.addReg(Reg);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6651 for (MachineOperand &AfterOp : AfterOps)
6652 MIB.addOperand(AfterOp);
6653 for (MachineOperand &ImpOp : ImpOps) {
6654 MIB.addReg(ImpOp.getReg(),
6655 getDefRegState(ImpOp.isDef()) |
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6656 RegState::Implicit |
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6657 getKillRegState(ImpOp.isKill()) |
6658 getDeadRegState(ImpOp.isDead()) |
6659 getUndefRegState(ImpOp.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6660 }
6661 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6662 switch (DataMI->getOpcode()) {
6663 default: break;
6664 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6665 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6666 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6667 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6668 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6669 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6670 case X86::CMP8ri: {
6671 MachineOperand &MO0 = DataMI->getOperand(0);
6672 MachineOperand &MO1 = DataMI->getOperand(1);
6673 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6674 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6675 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6676 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6677 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6678 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6679 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6680 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6681 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6682 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6683 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6684 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6685 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6686 MO1.ChangeToRegister(MO0.getReg(), false);
6687 }
6688 }
6689 }
6690 NewMIs.push_back(DataMI);
6691
6692 // Emit the store instruction.
6693 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6694 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6695 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6696 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6697 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6698 }
6699
6700 return true;
6701}
6702
6703bool
6704X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6705 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6706 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6707 return false;
6708
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6709 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6710 if (I == MemOp2RegOpTable.end())
6711 return false;
6712 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6713 unsigned Index = I->second.second & TB_INDEX_MASK;
6714 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6715 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6716 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6717 MachineFunction &MF = DAG.getMachineFunction();
6718 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6719 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6720 std::vector<SDValue> AddrOps;
6721 std::vector<SDValue> BeforeOps;
6722 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6723 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6724 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6725 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6726 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6727 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6728 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6729 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6730 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6731 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6732 AfterOps.push_back(Op);
6733 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6734 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6735 AddrOps.push_back(Chain);
6736
6737 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6738 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6739 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6740 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6741 std::pair<MachineInstr::mmo_iterator,
6742 MachineInstr::mmo_iterator> MMOs =
6743 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6744 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6745 if (!(*MMOs.first) &&
6746 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6747 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6748 // Do not introduce a slow unaligned load.
6749 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6750 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6751 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6752 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6753 bool isAligned = (*MMOs.first) &&
6754 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6755 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6756 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6757 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6758
6759 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6760 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6761 }
6762
6763 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6764 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6765 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6766 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6767 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6768 VTs.push_back(*DstRC->vt_begin());
6769 }
6770 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6771 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6772 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6773 VTs.push_back(VT);
6774 }
6775 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6776 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6777 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6778 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6779 NewNodes.push_back(NewNode);
6780
6781 // Emit the store instruction.
6782 if (FoldedStore) {
6783 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6784 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6785 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6786 std::pair<MachineInstr::mmo_iterator,
6787 MachineInstr::mmo_iterator> MMOs =
6788 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6789 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6790 if (!(*MMOs.first) &&
6791 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6792 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6793 // Do not introduce a slow unaligned store.
6794 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6795 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6796 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6797 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6798 bool isAligned = (*MMOs.first) &&
6799 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6800 SDNode *Store =
6801 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6802 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6803 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6804
6805 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6806 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6807 }
6808
6809 return true;
6810}
6811
6812unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6813 bool UnfoldLoad, bool UnfoldStore,
6814 unsigned *LoadRegIndex) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6815 auto I = MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6816 if (I == MemOp2RegOpTable.end())
6817 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6818 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6819 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6820 if (UnfoldLoad && !FoldedLoad)
6821 return 0;
6822 if (UnfoldStore && !FoldedStore)
6823 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6824 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6825 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6826 return I->second.first;
6827}
6828
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6829bool
6830X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6831 int64_t &Offset1, int64_t &Offset2) const {
6832 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6833 return false;
6834 unsigned Opc1 = Load1->getMachineOpcode();
6835 unsigned Opc2 = Load2->getMachineOpcode();
6836 switch (Opc1) {
6837 default: return false;
6838 case X86::MOV8rm:
6839 case X86::MOV16rm:
6840 case X86::MOV32rm:
6841 case X86::MOV64rm:
6842 case X86::LD_Fp32m:
6843 case X86::LD_Fp64m:
6844 case X86::LD_Fp80m:
6845 case X86::MOVSSrm:
6846 case X86::MOVSDrm:
6847 case X86::MMX_MOVD64rm:
6848 case X86::MMX_MOVQ64rm:
6849 case X86::FsMOVAPSrm:
6850 case X86::FsMOVAPDrm:
6851 case X86::MOVAPSrm:
6852 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6853 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6854 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6855 case X86::MOVDQArm:
6856 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6857 // AVX load instructions
6858 case X86::VMOVSSrm:
6859 case X86::VMOVSDrm:
6860 case X86::FsVMOVAPSrm:
6861 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6862 case X86::VMOVAPSrm:
6863 case X86::VMOVUPSrm:
6864 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6865 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6866 case X86::VMOVDQArm:
6867 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6868 case X86::VMOVAPSYrm:
6869 case X86::VMOVUPSYrm:
6870 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6871 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6872 case X86::VMOVDQAYrm:
6873 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6874 // AVX512 load instructions
6875 case X86::VMOVSSZrm:
6876 case X86::VMOVSDZrm:
6877 case X86::VMOVAPSZ128rm:
6878 case X86::VMOVUPSZ128rm:
6879 case X86::VMOVAPDZ128rm:
6880 case X86::VMOVUPDZ128rm:
6881 case X86::VMOVDQU8Z128rm:
6882 case X86::VMOVDQU16Z128rm:
6883 case X86::VMOVDQA32Z128rm:
6884 case X86::VMOVDQU32Z128rm:
6885 case X86::VMOVDQA64Z128rm:
6886 case X86::VMOVDQU64Z128rm:
6887 case X86::VMOVAPSZ256rm:
6888 case X86::VMOVUPSZ256rm:
6889 case X86::VMOVAPDZ256rm:
6890 case X86::VMOVUPDZ256rm:
6891 case X86::VMOVDQU8Z256rm:
6892 case X86::VMOVDQU16Z256rm:
6893 case X86::VMOVDQA32Z256rm:
6894 case X86::VMOVDQU32Z256rm:
6895 case X86::VMOVDQA64Z256rm:
6896 case X86::VMOVDQU64Z256rm:
6897 case X86::VMOVAPSZrm:
6898 case X86::VMOVUPSZrm:
6899 case X86::VMOVAPDZrm:
6900 case X86::VMOVUPDZrm:
6901 case X86::VMOVDQU8Zrm:
6902 case X86::VMOVDQU16Zrm:
6903 case X86::VMOVDQA32Zrm:
6904 case X86::VMOVDQU32Zrm:
6905 case X86::VMOVDQA64Zrm:
6906 case X86::VMOVDQU64Zrm:
6907 case X86::KMOVBkm:
6908 case X86::KMOVWkm:
6909 case X86::KMOVDkm:
6910 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6911 break;
6912 }
6913 switch (Opc2) {
6914 default: return false;
6915 case X86::MOV8rm:
6916 case X86::MOV16rm:
6917 case X86::MOV32rm:
6918 case X86::MOV64rm:
6919 case X86::LD_Fp32m:
6920 case X86::LD_Fp64m:
6921 case X86::LD_Fp80m:
6922 case X86::MOVSSrm:
6923 case X86::MOVSDrm:
6924 case X86::MMX_MOVD64rm:
6925 case X86::MMX_MOVQ64rm:
6926 case X86::FsMOVAPSrm:
6927 case X86::FsMOVAPDrm:
6928 case X86::MOVAPSrm:
6929 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6930 case X86::MOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6931 case X86::MOVUPDrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6932 case X86::MOVDQArm:
6933 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6934 // AVX load instructions
6935 case X86::VMOVSSrm:
6936 case X86::VMOVSDrm:
6937 case X86::FsVMOVAPSrm:
6938 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6939 case X86::VMOVAPSrm:
6940 case X86::VMOVUPSrm:
6941 case X86::VMOVAPDrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6942 case X86::VMOVUPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6943 case X86::VMOVDQArm:
6944 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6945 case X86::VMOVAPSYrm:
6946 case X86::VMOVUPSYrm:
6947 case X86::VMOVAPDYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6948 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6949 case X86::VMOVDQAYrm:
6950 case X86::VMOVDQUYrm:
Craig Topperf7a06c22016-07-18 06:14:43 +0000[diff] [blame]6951 // AVX512 load instructions
6952 case X86::VMOVSSZrm:
6953 case X86::VMOVSDZrm:
6954 case X86::VMOVAPSZ128rm:
6955 case X86::VMOVUPSZ128rm:
6956 case X86::VMOVAPDZ128rm:
6957 case X86::VMOVUPDZ128rm:
6958 case X86::VMOVDQU8Z128rm:
6959 case X86::VMOVDQU16Z128rm:
6960 case X86::VMOVDQA32Z128rm:
6961 case X86::VMOVDQU32Z128rm:
6962 case X86::VMOVDQA64Z128rm:
6963 case X86::VMOVDQU64Z128rm:
6964 case X86::VMOVAPSZ256rm:
6965 case X86::VMOVUPSZ256rm:
6966 case X86::VMOVAPDZ256rm:
6967 case X86::VMOVUPDZ256rm:
6968 case X86::VMOVDQU8Z256rm:
6969 case X86::VMOVDQU16Z256rm:
6970 case X86::VMOVDQA32Z256rm:
6971 case X86::VMOVDQU32Z256rm:
6972 case X86::VMOVDQA64Z256rm:
6973 case X86::VMOVDQU64Z256rm:
6974 case X86::VMOVAPSZrm:
6975 case X86::VMOVUPSZrm:
6976 case X86::VMOVAPDZrm:
6977 case X86::VMOVUPDZrm:
6978 case X86::VMOVDQU8Zrm:
6979 case X86::VMOVDQU16Zrm:
6980 case X86::VMOVDQA32Zrm:
6981 case X86::VMOVDQU32Zrm:
6982 case X86::VMOVDQA64Zrm:
6983 case X86::VMOVDQU64Zrm:
6984 case X86::KMOVBkm:
6985 case X86::KMOVWkm:
6986 case X86::KMOVDkm:
6987 case X86::KMOVQkm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6988 break;
6989 }
6990
6991 // Check if chain operands and base addresses match.
6992 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6993 Load1->getOperand(5) != Load2->getOperand(5))
6994 return false;
6995 // Segment operands should match as well.
6996 if (Load1->getOperand(4) != Load2->getOperand(4))
6997 return false;
6998 // Scale should be 1, Index should be Reg0.
6999 if (Load1->getOperand(1) == Load2->getOperand(1) &&
7000 Load1->getOperand(2) == Load2->getOperand(2)) {
7001 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
7002 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7003
7004 // Now let's examine the displacements.
7005 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
7006 isa<ConstantSDNode>(Load2->getOperand(3))) {
7007 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
7008 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
7009 return true;
7010 }
7011 }
7012 return false;
7013}
7014
7015bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
7016 int64_t Offset1, int64_t Offset2,
7017 unsigned NumLoads) const {
7018 assert(Offset2 > Offset1);
7019 if ((Offset2 - Offset1) / 8 > 64)
7020 return false;
7021
7022 unsigned Opc1 = Load1->getMachineOpcode();
7023 unsigned Opc2 = Load2->getMachineOpcode();
7024 if (Opc1 != Opc2)
7025 return false; // FIXME: overly conservative?
7026
7027 switch (Opc1) {
7028 default: break;
7029 case X86::LD_Fp32m:
7030 case X86::LD_Fp64m:
7031 case X86::LD_Fp80m:
7032 case X86::MMX_MOVD64rm:
7033 case X86::MMX_MOVQ64rm:
7034 return false;
7035 }
7036
7037 EVT VT = Load1->getValueType(0);
7038 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7039 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7040 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
7041 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7042 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7043 if (NumLoads >= 3)
7044 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7045 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7046 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7047 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7048 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7049 case MVT::i8:
7050 case MVT::i16:
7051 case MVT::i32:
7052 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]7053 case MVT::f32:
7054 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7055 if (NumLoads)
7056 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]7057 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7058 }
7059
7060 return true;
7061}
7062
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7063bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
7064 MachineInstr &Second) const {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7065 // Check if this processor supports macro-fusion. Since this is a minor
7066 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
7067 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7068 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7069 return false;
7070
7071 enum {
7072 FuseTest,
7073 FuseCmp,
7074 FuseInc
7075 } FuseKind;
7076
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7077 switch (Second.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7078 default:
7079 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7080 case X86::JE_1:
7081 case X86::JNE_1:
7082 case X86::JL_1:
7083 case X86::JLE_1:
7084 case X86::JG_1:
7085 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7086 FuseKind = FuseInc;
7087 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7088 case X86::JB_1:
7089 case X86::JBE_1:
7090 case X86::JA_1:
7091 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7092 FuseKind = FuseCmp;
7093 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7094 case X86::JS_1:
7095 case X86::JNS_1:
7096 case X86::JP_1:
7097 case X86::JNP_1:
7098 case X86::JO_1:
7099 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7100 FuseKind = FuseTest;
7101 break;
7102 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7103 switch (First.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7104 default:
7105 return false;
7106 case X86::TEST8rr:
7107 case X86::TEST16rr:
7108 case X86::TEST32rr:
7109 case X86::TEST64rr:
7110 case X86::TEST8ri:
7111 case X86::TEST16ri:
7112 case X86::TEST32ri:
7113 case X86::TEST32i32:
7114 case X86::TEST64i32:
7115 case X86::TEST64ri32:
7116 case X86::TEST8rm:
7117 case X86::TEST16rm:
7118 case X86::TEST32rm:
7119 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]7120 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7121 case X86::AND16i16:
7122 case X86::AND16ri:
7123 case X86::AND16ri8:
7124 case X86::AND16rm:
7125 case X86::AND16rr:
7126 case X86::AND32i32:
7127 case X86::AND32ri:
7128 case X86::AND32ri8:
7129 case X86::AND32rm:
7130 case X86::AND32rr:
7131 case X86::AND64i32:
7132 case X86::AND64ri32:
7133 case X86::AND64ri8:
7134 case X86::AND64rm:
7135 case X86::AND64rr:
7136 case X86::AND8i8:
7137 case X86::AND8ri:
7138 case X86::AND8rm:
7139 case X86::AND8rr:
7140 return true;
7141 case X86::CMP16i16:
7142 case X86::CMP16ri:
7143 case X86::CMP16ri8:
7144 case X86::CMP16rm:
7145 case X86::CMP16rr:
7146 case X86::CMP32i32:
7147 case X86::CMP32ri:
7148 case X86::CMP32ri8:
7149 case X86::CMP32rm:
7150 case X86::CMP32rr:
7151 case X86::CMP64i32:
7152 case X86::CMP64ri32:
7153 case X86::CMP64ri8:
7154 case X86::CMP64rm:
7155 case X86::CMP64rr:
7156 case X86::CMP8i8:
7157 case X86::CMP8ri:
7158 case X86::CMP8rm:
7159 case X86::CMP8rr:
7160 case X86::ADD16i16:
7161 case X86::ADD16ri:
7162 case X86::ADD16ri8:
7163 case X86::ADD16ri8_DB:
7164 case X86::ADD16ri_DB:
7165 case X86::ADD16rm:
7166 case X86::ADD16rr:
7167 case X86::ADD16rr_DB:
7168 case X86::ADD32i32:
7169 case X86::ADD32ri:
7170 case X86::ADD32ri8:
7171 case X86::ADD32ri8_DB:
7172 case X86::ADD32ri_DB:
7173 case X86::ADD32rm:
7174 case X86::ADD32rr:
7175 case X86::ADD32rr_DB:
7176 case X86::ADD64i32:
7177 case X86::ADD64ri32:
7178 case X86::ADD64ri32_DB:
7179 case X86::ADD64ri8:
7180 case X86::ADD64ri8_DB:
7181 case X86::ADD64rm:
7182 case X86::ADD64rr:
7183 case X86::ADD64rr_DB:
7184 case X86::ADD8i8:
7185 case X86::ADD8mi:
7186 case X86::ADD8mr:
7187 case X86::ADD8ri:
7188 case X86::ADD8rm:
7189 case X86::ADD8rr:
7190 case X86::SUB16i16:
7191 case X86::SUB16ri:
7192 case X86::SUB16ri8:
7193 case X86::SUB16rm:
7194 case X86::SUB16rr:
7195 case X86::SUB32i32:
7196 case X86::SUB32ri:
7197 case X86::SUB32ri8:
7198 case X86::SUB32rm:
7199 case X86::SUB32rr:
7200 case X86::SUB64i32:
7201 case X86::SUB64ri32:
7202 case X86::SUB64ri8:
7203 case X86::SUB64rm:
7204 case X86::SUB64rr:
7205 case X86::SUB8i8:
7206 case X86::SUB8ri:
7207 case X86::SUB8rm:
7208 case X86::SUB8rr:
7209 return FuseKind == FuseCmp || FuseKind == FuseInc;
7210 case X86::INC16r:
7211 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7212 case X86::INC64r:
7213 case X86::INC8r:
7214 case X86::DEC16r:
7215 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]7216 case X86::DEC64r:
7217 case X86::DEC8r:
7218 return FuseKind == FuseInc;
7219 }
7220}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]7221
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7222bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]7223ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7224 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]7225 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7226 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]7227 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]7228}
7229
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7230bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7231isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7232 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7233 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]7234 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7235 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]7236}
7237
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7238/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7239/// the global base register value. Output instructions required to
7240/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7241///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7242/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7243///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7244unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7245 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7246 "X86-64 PIC uses RIP relative addressing");
7247
7248 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7249 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7250 if (GlobalBaseReg != 0)
7251 return GlobalBaseReg;
7252
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7253 // Create the register. The code to initialize it is inserted
7254 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7255 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]7256 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]7257 X86FI->setGlobalBaseReg(GlobalBaseReg);
7258 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]7259}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7260
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7261// These are the replaceable SSE instructions. Some of these have Int variants
7262// that we don't include here. We don't want to replace instructions selected
7263// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7264static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]7265 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7266 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
7267 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
7268 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
7269 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
7270 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]7271 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]7272 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
7273 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
7274 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
7275 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
7276 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
7277 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
7278 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
7279 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
7280 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7281 // AVX 128-bit support
7282 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
7283 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
7284 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
7285 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
7286 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]7287 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7288 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7289 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
7290 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
7291 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
7292 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
7293 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
7294 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]7295 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
7296 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]7297 // AVX 256-bit support
7298 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
7299 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
7300 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
7301 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
7302 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7303 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
7304 // AVX512 support
7305 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
7306 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7307 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7308 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7309};
7310
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7311static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]7312 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]7313 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
7314 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
7315 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
7316 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
7317 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
7318 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
7319 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]7320 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
7321 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7322 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7323 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
7324 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
7325 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]7326 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
7327 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7328 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7329 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7330 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7331 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7332 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7333};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7334
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7335static const uint16_t ReplaceableInstrsAVX512[][4] = {
7336 // Two integer columns for 64-bit and 32-bit elements.
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7337 //PackedSingle PackedDouble PackedInt PackedInt
Craig Topper4c53e602016-07-31 20:20:01 +0000[diff] [blame]7338 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA64Z128mr },
7339 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA64Z128rm },
7340 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rr },
7341 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU64Z128mr },
7342 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU64Z128rm },
7343 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA64Z256mr },
7344 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA64Z256rm },
7345 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rr },
7346 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU64Z256mr },
7347 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU64Z256rm },
7348 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA64Zmr },
7349 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA64Zrm },
7350 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrr },
7351 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU64Zmr },
7352 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU64Zrm },
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7353};
7354
7355static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7356 // Two integer columns for 64-bit and 32-bit elements.
7357 //PackedSingle PackedDouble PackedInt PackedInt
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7358 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7359 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7360 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
7361 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
7362 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
7363 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
7364 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
7365 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
7366 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7367 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7368 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
7369 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
7370 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
7371 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
7372 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
7373 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
7374 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
7375 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
7376 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
7377 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
7378 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
7379 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
7380 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
7381 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7382};
7383
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7384// FIXME: Some shuffle and unpack instructions have equivalents in different
7385// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7386
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7387static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7388 for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7389 if (Row[domain-1] == opcode)
7390 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7391 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7392}
7393
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7394static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7395 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7396 if (Row[domain-1] == opcode)
7397 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7398 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7399}
7400
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7401static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain) {
7402 // If this is the integer domain make sure to check both integer columns.
7403 for (const uint16_t (&Row)[4] : ReplaceableInstrsAVX512)
7404 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7405 return Row;
7406 return nullptr;
7407}
7408
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7409static const uint16_t *lookupAVX512DQ(unsigned opcode, unsigned domain) {
7410 // If this is the integer domain make sure to check both integer columns.
7411 for (const uint16_t (&Row)[4] : ReplaceableInstrsAVX512DQ)
7412 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7413 return Row;
7414 return nullptr;
7415}
7416
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7417std::pair<uint16_t, uint16_t>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7418X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7419 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7420 uint16_t validDomains = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7421 if (domain && lookup(MI.getOpcode(), domain))
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7422 validDomains = 0xe;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7423 else if (domain && lookupAVX2(MI.getOpcode(), domain))
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7424 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7425 else if (domain && lookupAVX512(MI.getOpcode(), domain))
7426 validDomains = 0xe;
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7427 else if (domain && lookupAVX512DQ(MI.getOpcode(), domain))
7428 validDomains = Subtarget.hasDQI() ? 0xe : 0x8;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7429 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7430}
7431
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7432void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7433 assert(Domain>0 && Domain<4 && "Invalid execution domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7434 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7435 assert(dom && "Not an SSE instruction");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7436 const uint16_t *table = lookup(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7437 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7438 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7439 "256-bit vector operations only available in AVX2");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7440 table = lookupAVX2(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7441 }
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7442 if (!table) { // try the AVX512 table
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7443 assert(Subtarget.hasAVX512() && "Requires AVX-512");
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7444 table = lookupAVX512(MI.getOpcode(), dom);
7445 // Don't change integer Q instructions to D instructions.
Craig Topper00d34ed2016-07-31 17:15:07 +0000[diff] [blame]7446 if (table && dom == 3 && table[3] == MI.getOpcode())
7447 Domain = 4;
7448 }
7449 if (!table) { // try the AVX512DQ table
7450 assert((Subtarget.hasDQI() || Domain >=3) && "Requires AVX-512DQ");
7451 table = lookupAVX512DQ(MI.getOpcode(), dom);
7452 // Don't change integer Q instructions to D instructions.
7453 if (table && dom == 3 && table[3] == MI.getOpcode())
Craig Topperf4151be2016-07-22 05:00:52 +0000[diff] [blame]7454 Domain = 4;
7455 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7456 assert(table && "Cannot change domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7457 MI.setDesc(get(table[Domain - 1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7458}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7459
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7460/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7461void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7462 NopInst.setOpcode(X86::NOOP);
7463}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7464
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7465// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7466// In particular, getJumpInstrTableEntryBound must always return an upper bound
7467// on the encoding lengths of the instructions generated by
7468// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7469void X86InstrInfo::getUnconditionalBranch(
7470 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7471 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]7472 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7473}
7474
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7475// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7476// In particular, getJumpInstrTableEntryBound must always return an upper bound
7477// on the encoding lengths of the instructions generated by
7478// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7479void X86InstrInfo::getTrap(MCInst &MI) const {
7480 MI.setOpcode(X86::TRAP);
7481}
7482
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7483// See getTrap and getUnconditionalBranch for conditions on the value returned
7484// by this function.
7485unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7486 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7487 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7488 return 5;
7489}
7490
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7491bool X86InstrInfo::isHighLatencyDef(int opc) const {
7492 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7493 default: return false;
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7494 case X86::DIVPDrm:
7495 case X86::DIVPDrr:
7496 case X86::DIVPSrm:
7497 case X86::DIVPSrr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7498 case X86::DIVSDrm:
7499 case X86::DIVSDrm_Int:
7500 case X86::DIVSDrr:
7501 case X86::DIVSDrr_Int:
7502 case X86::DIVSSrm:
7503 case X86::DIVSSrm_Int:
7504 case X86::DIVSSrr:
7505 case X86::DIVSSrr_Int:
7506 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7507 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7508 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7509 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7510 case X86::SQRTSDm:
7511 case X86::SQRTSDm_Int:
7512 case X86::SQRTSDr:
7513 case X86::SQRTSDr_Int:
7514 case X86::SQRTSSm:
7515 case X86::SQRTSSm_Int:
7516 case X86::SQRTSSr:
7517 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7518 // AVX instructions with high latency
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7519 case X86::VDIVPDrm:
7520 case X86::VDIVPDrr:
7521 case X86::VDIVPDYrm:
7522 case X86::VDIVPDYrr:
7523 case X86::VDIVPSrm:
7524 case X86::VDIVPSrr:
7525 case X86::VDIVPSYrm:
7526 case X86::VDIVPSYrr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7527 case X86::VDIVSDrm:
7528 case X86::VDIVSDrm_Int:
7529 case X86::VDIVSDrr:
7530 case X86::VDIVSDrr_Int:
7531 case X86::VDIVSSrm:
7532 case X86::VDIVSSrm_Int:
7533 case X86::VDIVSSrr:
7534 case X86::VDIVSSrr_Int:
7535 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7536 case X86::VSQRTPDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7537 case X86::VSQRTPDYm:
7538 case X86::VSQRTPDYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7539 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7540 case X86::VSQRTPSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7541 case X86::VSQRTPSYm:
7542 case X86::VSQRTPSYr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7543 case X86::VSQRTSDm:
7544 case X86::VSQRTSDm_Int:
7545 case X86::VSQRTSDr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7546 case X86::VSQRTSDr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7547 case X86::VSQRTSSm:
7548 case X86::VSQRTSSm_Int:
7549 case X86::VSQRTSSr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7550 case X86::VSQRTSSr_Int:
7551 // AVX512 instructions with high latency
7552 case X86::VDIVPDZ128rm:
7553 case X86::VDIVPDZ128rmb:
7554 case X86::VDIVPDZ128rmbk:
7555 case X86::VDIVPDZ128rmbkz:
7556 case X86::VDIVPDZ128rmk:
7557 case X86::VDIVPDZ128rmkz:
7558 case X86::VDIVPDZ128rr:
7559 case X86::VDIVPDZ128rrk:
7560 case X86::VDIVPDZ128rrkz:
7561 case X86::VDIVPDZ256rm:
7562 case X86::VDIVPDZ256rmb:
7563 case X86::VDIVPDZ256rmbk:
7564 case X86::VDIVPDZ256rmbkz:
7565 case X86::VDIVPDZ256rmk:
7566 case X86::VDIVPDZ256rmkz:
7567 case X86::VDIVPDZ256rr:
7568 case X86::VDIVPDZ256rrk:
7569 case X86::VDIVPDZ256rrkz:
7570 case X86::VDIVPDZrb:
7571 case X86::VDIVPDZrbk:
7572 case X86::VDIVPDZrbkz:
7573 case X86::VDIVPDZrm:
7574 case X86::VDIVPDZrmb:
7575 case X86::VDIVPDZrmbk:
7576 case X86::VDIVPDZrmbkz:
7577 case X86::VDIVPDZrmk:
7578 case X86::VDIVPDZrmkz:
7579 case X86::VDIVPDZrr:
7580 case X86::VDIVPDZrrk:
7581 case X86::VDIVPDZrrkz:
7582 case X86::VDIVPSZ128rm:
7583 case X86::VDIVPSZ128rmb:
7584 case X86::VDIVPSZ128rmbk:
7585 case X86::VDIVPSZ128rmbkz:
7586 case X86::VDIVPSZ128rmk:
7587 case X86::VDIVPSZ128rmkz:
7588 case X86::VDIVPSZ128rr:
7589 case X86::VDIVPSZ128rrk:
7590 case X86::VDIVPSZ128rrkz:
7591 case X86::VDIVPSZ256rm:
7592 case X86::VDIVPSZ256rmb:
7593 case X86::VDIVPSZ256rmbk:
7594 case X86::VDIVPSZ256rmbkz:
7595 case X86::VDIVPSZ256rmk:
7596 case X86::VDIVPSZ256rmkz:
7597 case X86::VDIVPSZ256rr:
7598 case X86::VDIVPSZ256rrk:
7599 case X86::VDIVPSZ256rrkz:
7600 case X86::VDIVPSZrb:
7601 case X86::VDIVPSZrbk:
7602 case X86::VDIVPSZrbkz:
7603 case X86::VDIVPSZrm:
7604 case X86::VDIVPSZrmb:
7605 case X86::VDIVPSZrmbk:
7606 case X86::VDIVPSZrmbkz:
7607 case X86::VDIVPSZrmk:
7608 case X86::VDIVPSZrmkz:
7609 case X86::VDIVPSZrr:
7610 case X86::VDIVPSZrrk:
7611 case X86::VDIVPSZrrkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7612 case X86::VDIVSDZrm:
7613 case X86::VDIVSDZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7614 case X86::VDIVSDZrm_Int:
7615 case X86::VDIVSDZrm_Intk:
7616 case X86::VDIVSDZrm_Intkz:
7617 case X86::VDIVSDZrr_Int:
7618 case X86::VDIVSDZrr_Intk:
7619 case X86::VDIVSDZrr_Intkz:
7620 case X86::VDIVSDZrrb:
7621 case X86::VDIVSDZrrbk:
7622 case X86::VDIVSDZrrbkz:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7623 case X86::VDIVSSZrm:
7624 case X86::VDIVSSZrr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7625 case X86::VDIVSSZrm_Int:
7626 case X86::VDIVSSZrm_Intk:
7627 case X86::VDIVSSZrm_Intkz:
7628 case X86::VDIVSSZrr_Int:
7629 case X86::VDIVSSZrr_Intk:
7630 case X86::VDIVSSZrr_Intkz:
7631 case X86::VDIVSSZrrb:
7632 case X86::VDIVSSZrrbk:
7633 case X86::VDIVSSZrrbkz:
7634 case X86::VSQRTPDZ128m:
7635 case X86::VSQRTPDZ128mb:
7636 case X86::VSQRTPDZ128mbk:
7637 case X86::VSQRTPDZ128mbkz:
7638 case X86::VSQRTPDZ128mk:
7639 case X86::VSQRTPDZ128mkz:
7640 case X86::VSQRTPDZ128r:
7641 case X86::VSQRTPDZ128rk:
7642 case X86::VSQRTPDZ128rkz:
7643 case X86::VSQRTPDZ256m:
7644 case X86::VSQRTPDZ256mb:
7645 case X86::VSQRTPDZ256mbk:
7646 case X86::VSQRTPDZ256mbkz:
7647 case X86::VSQRTPDZ256mk:
7648 case X86::VSQRTPDZ256mkz:
7649 case X86::VSQRTPDZ256r:
7650 case X86::VSQRTPDZ256rk:
7651 case X86::VSQRTPDZ256rkz:
7652 case X86::VSQRTPDZm:
7653 case X86::VSQRTPDZmb:
7654 case X86::VSQRTPDZmbk:
7655 case X86::VSQRTPDZmbkz:
7656 case X86::VSQRTPDZmk:
7657 case X86::VSQRTPDZmkz:
7658 case X86::VSQRTPDZr:
7659 case X86::VSQRTPDZrb:
7660 case X86::VSQRTPDZrbk:
7661 case X86::VSQRTPDZrbkz:
7662 case X86::VSQRTPDZrk:
7663 case X86::VSQRTPDZrkz:
7664 case X86::VSQRTPSZ128m:
7665 case X86::VSQRTPSZ128mb:
7666 case X86::VSQRTPSZ128mbk:
7667 case X86::VSQRTPSZ128mbkz:
7668 case X86::VSQRTPSZ128mk:
7669 case X86::VSQRTPSZ128mkz:
7670 case X86::VSQRTPSZ128r:
7671 case X86::VSQRTPSZ128rk:
7672 case X86::VSQRTPSZ128rkz:
7673 case X86::VSQRTPSZ256m:
7674 case X86::VSQRTPSZ256mb:
7675 case X86::VSQRTPSZ256mbk:
7676 case X86::VSQRTPSZ256mbkz:
7677 case X86::VSQRTPSZ256mk:
7678 case X86::VSQRTPSZ256mkz:
7679 case X86::VSQRTPSZ256r:
7680 case X86::VSQRTPSZ256rk:
7681 case X86::VSQRTPSZ256rkz:
7682 case X86::VSQRTPSZm:
7683 case X86::VSQRTPSZmb:
7684 case X86::VSQRTPSZmbk:
7685 case X86::VSQRTPSZmbkz:
7686 case X86::VSQRTPSZmk:
7687 case X86::VSQRTPSZmkz:
7688 case X86::VSQRTPSZr:
7689 case X86::VSQRTPSZrb:
7690 case X86::VSQRTPSZrbk:
7691 case X86::VSQRTPSZrbkz:
7692 case X86::VSQRTPSZrk:
7693 case X86::VSQRTPSZrkz:
7694 case X86::VSQRTSDZm:
7695 case X86::VSQRTSDZm_Int:
7696 case X86::VSQRTSDZm_Intk:
7697 case X86::VSQRTSDZm_Intkz:
7698 case X86::VSQRTSDZr:
7699 case X86::VSQRTSDZr_Int:
7700 case X86::VSQRTSDZr_Intk:
7701 case X86::VSQRTSDZr_Intkz:
7702 case X86::VSQRTSDZrb_Int:
7703 case X86::VSQRTSDZrb_Intk:
7704 case X86::VSQRTSDZrb_Intkz:
7705 case X86::VSQRTSSZm:
7706 case X86::VSQRTSSZm_Int:
7707 case X86::VSQRTSSZm_Intk:
7708 case X86::VSQRTSSZm_Intkz:
7709 case X86::VSQRTSSZr:
7710 case X86::VSQRTSSZr_Int:
7711 case X86::VSQRTSSZr_Intk:
7712 case X86::VSQRTSSZr_Intkz:
7713 case X86::VSQRTSSZrb_Int:
7714 case X86::VSQRTSSZrb_Intk:
7715 case X86::VSQRTSSZrb_Intkz:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7716
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7717 case X86::VGATHERDPDYrm:
7718 case X86::VGATHERDPDZ128rm:
7719 case X86::VGATHERDPDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7720 case X86::VGATHERDPDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7721 case X86::VGATHERDPDrm:
7722 case X86::VGATHERDPSYrm:
7723 case X86::VGATHERDPSZ128rm:
7724 case X86::VGATHERDPSZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7725 case X86::VGATHERDPSZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7726 case X86::VGATHERDPSrm:
7727 case X86::VGATHERPF0DPDm:
7728 case X86::VGATHERPF0DPSm:
7729 case X86::VGATHERPF0QPDm:
7730 case X86::VGATHERPF0QPSm:
7731 case X86::VGATHERPF1DPDm:
7732 case X86::VGATHERPF1DPSm:
7733 case X86::VGATHERPF1QPDm:
7734 case X86::VGATHERPF1QPSm:
7735 case X86::VGATHERQPDYrm:
7736 case X86::VGATHERQPDZ128rm:
7737 case X86::VGATHERQPDZ256rm:
7738 case X86::VGATHERQPDZrm:
7739 case X86::VGATHERQPDrm:
7740 case X86::VGATHERQPSYrm:
7741 case X86::VGATHERQPSZ128rm:
7742 case X86::VGATHERQPSZ256rm:
7743 case X86::VGATHERQPSZrm:
7744 case X86::VGATHERQPSrm:
7745 case X86::VPGATHERDDYrm:
7746 case X86::VPGATHERDDZ128rm:
7747 case X86::VPGATHERDDZ256rm:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7748 case X86::VPGATHERDDZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7749 case X86::VPGATHERDDrm:
7750 case X86::VPGATHERDQYrm:
7751 case X86::VPGATHERDQZ128rm:
7752 case X86::VPGATHERDQZ256rm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7753 case X86::VPGATHERDQZrm:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7754 case X86::VPGATHERDQrm:
7755 case X86::VPGATHERQDYrm:
7756 case X86::VPGATHERQDZ128rm:
7757 case X86::VPGATHERQDZ256rm:
7758 case X86::VPGATHERQDZrm:
7759 case X86::VPGATHERQDrm:
7760 case X86::VPGATHERQQYrm:
7761 case X86::VPGATHERQQZ128rm:
7762 case X86::VPGATHERQQZ256rm:
7763 case X86::VPGATHERQQZrm:
7764 case X86::VPGATHERQQrm:
7765 case X86::VSCATTERDPDZ128mr:
7766 case X86::VSCATTERDPDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7767 case X86::VSCATTERDPDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7768 case X86::VSCATTERDPSZ128mr:
7769 case X86::VSCATTERDPSZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7770 case X86::VSCATTERDPSZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7771 case X86::VSCATTERPF0DPDm:
7772 case X86::VSCATTERPF0DPSm:
7773 case X86::VSCATTERPF0QPDm:
7774 case X86::VSCATTERPF0QPSm:
7775 case X86::VSCATTERPF1DPDm:
7776 case X86::VSCATTERPF1DPSm:
7777 case X86::VSCATTERPF1QPDm:
7778 case X86::VSCATTERPF1QPSm:
7779 case X86::VSCATTERQPDZ128mr:
7780 case X86::VSCATTERQPDZ256mr:
7781 case X86::VSCATTERQPDZmr:
7782 case X86::VSCATTERQPSZ128mr:
7783 case X86::VSCATTERQPSZ256mr:
7784 case X86::VSCATTERQPSZmr:
7785 case X86::VPSCATTERDDZ128mr:
7786 case X86::VPSCATTERDDZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7787 case X86::VPSCATTERDDZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7788 case X86::VPSCATTERDQZ128mr:
7789 case X86::VPSCATTERDQZ256mr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7790 case X86::VPSCATTERDQZmr:
Craig Topperfe5a6dc2016-07-18 06:14:45 +0000[diff] [blame]7791 case X86::VPSCATTERQDZ128mr:
7792 case X86::VPSCATTERQDZ256mr:
7793 case X86::VPSCATTERQDZmr:
7794 case X86::VPSCATTERQQZ128mr:
7795 case X86::VPSCATTERQQZ256mr:
7796 case X86::VPSCATTERQQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7797 return true;
7798 }
7799}
7800
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7801bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7802 const MachineRegisterInfo *MRI,
7803 const MachineInstr &DefMI,
7804 unsigned DefIdx,
7805 const MachineInstr &UseMI,
7806 unsigned UseIdx) const {
7807 return isHighLatencyDef(DefMI.getOpcode());
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7808}
7809
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7810bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7811 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7812 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7813 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7814
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7815 // Integer binary math/logic instructions have a third source operand:
7816 // the EFLAGS register. That operand must be both defined here and never
7817 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7818 // not change anything because rearranging the operands could affect other
7819 // instructions that depend on the exact status flags (zero, sign, etc.)
7820 // that are set by using these particular operands with this operation.
7821 if (Inst.getNumOperands() == 4) {
7822 assert(Inst.getOperand(3).isReg() &&
7823 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7824 "Unexpected operand in reassociable instruction");
7825 if (!Inst.getOperand(3).isDead())
7826 return false;
7827 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]7828
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7829 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7830}
7831
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7832// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7833// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7834// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7835// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7836bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7837 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7838 case X86::AND8rr:
7839 case X86::AND16rr:
7840 case X86::AND32rr:
7841 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]7842 case X86::OR8rr:
7843 case X86::OR16rr:
7844 case X86::OR32rr:
7845 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]7846 case X86::XOR8rr:
7847 case X86::XOR16rr:
7848 case X86::XOR32rr:
7849 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7850 case X86::IMUL16rr:
7851 case X86::IMUL32rr:
7852 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7853 case X86::PANDrr:
7854 case X86::PORrr:
7855 case X86::PXORrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]7856 case X86::ANDPDrr:
7857 case X86::ANDPSrr:
7858 case X86::ORPDrr:
7859 case X86::ORPSrr:
7860 case X86::XORPDrr:
7861 case X86::XORPSrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]7862 case X86::PADDBrr:
7863 case X86::PADDWrr:
7864 case X86::PADDDrr:
7865 case X86::PADDQrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7866 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7867 case X86::VPANDYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7868 case X86::VPANDDZ128rr:
7869 case X86::VPANDDZ256rr:
7870 case X86::VPANDDZrr:
7871 case X86::VPANDQZ128rr:
7872 case X86::VPANDQZ256rr:
7873 case X86::VPANDQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7874 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7875 case X86::VPORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7876 case X86::VPORDZ128rr:
7877 case X86::VPORDZ256rr:
7878 case X86::VPORDZrr:
7879 case X86::VPORQZ128rr:
7880 case X86::VPORQZ256rr:
7881 case X86::VPORQZrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7882 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7883 case X86::VPXORYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7884 case X86::VPXORDZ128rr:
7885 case X86::VPXORDZ256rr:
7886 case X86::VPXORDZrr:
7887 case X86::VPXORQZ128rr:
7888 case X86::VPXORQZ256rr:
7889 case X86::VPXORQZrr:
Craig Topperba9b93d2016-07-18 06:14:50 +0000[diff] [blame]7890 case X86::VANDPDrr:
7891 case X86::VANDPSrr:
7892 case X86::VANDPDYrr:
7893 case X86::VANDPSYrr:
7894 case X86::VANDPDZ128rr:
7895 case X86::VANDPSZ128rr:
7896 case X86::VANDPDZ256rr:
7897 case X86::VANDPSZ256rr:
7898 case X86::VANDPDZrr:
7899 case X86::VANDPSZrr:
7900 case X86::VORPDrr:
7901 case X86::VORPSrr:
7902 case X86::VORPDYrr:
7903 case X86::VORPSYrr:
7904 case X86::VORPDZ128rr:
7905 case X86::VORPSZ128rr:
7906 case X86::VORPDZ256rr:
7907 case X86::VORPSZ256rr:
7908 case X86::VORPDZrr:
7909 case X86::VORPSZrr:
7910 case X86::VXORPDrr:
7911 case X86::VXORPSrr:
7912 case X86::VXORPDYrr:
7913 case X86::VXORPSYrr:
7914 case X86::VXORPDZ128rr:
7915 case X86::VXORPSZ128rr:
7916 case X86::VXORPDZ256rr:
7917 case X86::VXORPSZ256rr:
7918 case X86::VXORPDZrr:
7919 case X86::VXORPSZrr:
Craig Topper16a07442016-07-18 06:14:59 +0000[diff] [blame]7920 case X86::KADDBrr:
7921 case X86::KADDWrr:
7922 case X86::KADDDrr:
7923 case X86::KADDQrr:
7924 case X86::KANDBrr:
7925 case X86::KANDWrr:
7926 case X86::KANDDrr:
7927 case X86::KANDQrr:
7928 case X86::KORBrr:
7929 case X86::KORWrr:
7930 case X86::KORDrr:
7931 case X86::KORQrr:
7932 case X86::KXORBrr:
7933 case X86::KXORWrr:
7934 case X86::KXORDrr:
7935 case X86::KXORQrr:
Craig Topper1af6cc02016-07-18 06:14:54 +0000[diff] [blame]7936 case X86::VPADDBrr:
7937 case X86::VPADDWrr:
7938 case X86::VPADDDrr:
7939 case X86::VPADDQrr:
7940 case X86::VPADDBYrr:
7941 case X86::VPADDWYrr:
7942 case X86::VPADDDYrr:
7943 case X86::VPADDQYrr:
7944 case X86::VPADDBZ128rr:
7945 case X86::VPADDWZ128rr:
7946 case X86::VPADDDZ128rr:
7947 case X86::VPADDQZ128rr:
7948 case X86::VPADDBZ256rr:
7949 case X86::VPADDWZ256rr:
7950 case X86::VPADDDZ256rr:
7951 case X86::VPADDQZ256rr:
7952 case X86::VPADDBZrr:
7953 case X86::VPADDWZrr:
7954 case X86::VPADDDZrr:
7955 case X86::VPADDQZrr:
Craig Topper463f9492016-07-18 06:14:57 +0000[diff] [blame]7956 case X86::VPMULLWrr:
7957 case X86::VPMULLWYrr:
7958 case X86::VPMULLWZ128rr:
7959 case X86::VPMULLWZ256rr:
7960 case X86::VPMULLWZrr:
7961 case X86::VPMULLDrr:
7962 case X86::VPMULLDYrr:
7963 case X86::VPMULLDZ128rr:
7964 case X86::VPMULLDZ256rr:
7965 case X86::VPMULLDZrr:
7966 case X86::VPMULLQZ128rr:
7967 case X86::VPMULLQZ256rr:
7968 case X86::VPMULLQZrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7969 // Normal min/max instructions are not commutative because of NaN and signed
7970 // zero semantics, but these are. Thus, there's no need to check for global
7971 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7972 case X86::MAXCPDrr:
7973 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7974 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7975 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7976 case X86::MINCPDrr:
7977 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7978 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7979 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7980 case X86::VMAXCPDrr:
7981 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7982 case X86::VMAXCPDYrr:
7983 case X86::VMAXCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7984 case X86::VMAXCPDZ128rr:
7985 case X86::VMAXCPSZ128rr:
7986 case X86::VMAXCPDZ256rr:
7987 case X86::VMAXCPSZ256rr:
7988 case X86::VMAXCPDZrr:
7989 case X86::VMAXCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7990 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7991 case X86::VMAXCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7992 case X86::VMAXCSDZrr:
7993 case X86::VMAXCSSZrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7994 case X86::VMINCPDrr:
7995 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7996 case X86::VMINCPDYrr:
7997 case X86::VMINCPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]7998 case X86::VMINCPDZ128rr:
7999 case X86::VMINCPSZ128rr:
8000 case X86::VMINCPDZ256rr:
8001 case X86::VMINCPSZ256rr:
8002 case X86::VMINCPDZrr:
8003 case X86::VMINCPSZrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]8004 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]8005 case X86::VMINCSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8006 case X86::VMINCSDZrr:
8007 case X86::VMINCSSZrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]8008 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]8009 case X86::ADDPDrr:
8010 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]8011 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]8012 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]8013 case X86::MULPDrr:
8014 case X86::MULPSrr:
8015 case X86::MULSDrr:
8016 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]8017 case X86::VADDPDrr:
8018 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]8019 case X86::VADDPDYrr:
8020 case X86::VADDPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8021 case X86::VADDPDZ128rr:
8022 case X86::VADDPSZ128rr:
8023 case X86::VADDPDZ256rr:
8024 case X86::VADDPSZ256rr:
8025 case X86::VADDPDZrr:
8026 case X86::VADDPSZrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]8027 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]8028 case X86::VADDSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8029 case X86::VADDSDZrr:
8030 case X86::VADDSSZrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]8031 case X86::VMULPDrr:
8032 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]8033 case X86::VMULPDYrr:
8034 case X86::VMULPSYrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8035 case X86::VMULPDZ128rr:
8036 case X86::VMULPSZ128rr:
8037 case X86::VMULPDZ256rr:
8038 case X86::VMULPSZ256rr:
8039 case X86::VMULPDZrr:
8040 case X86::VMULPSZrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]8041 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]8042 case X86::VMULSSrr:
Craig Topper3a99de42016-07-18 06:14:47 +0000[diff] [blame]8043 case X86::VMULSDZrr:
8044 case X86::VMULSSZrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]8045 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]8046 default:
8047 return false;
8048 }
8049}
8050
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]8051/// This is an architecture-specific helper function of reassociateOps.
8052/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]8053void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8054 MachineInstr &OldMI2,
8055 MachineInstr &NewMI1,
8056 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]8057 // Integer instructions define an implicit EFLAGS source register operand as
8058 // the third source (fourth total) operand.
8059 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
8060 return;
8061
8062 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
8063 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]8064
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]8065 MachineOperand &OldOp1 = OldMI1.getOperand(3);
8066 MachineOperand &OldOp2 = OldMI2.getOperand(3);
8067 MachineOperand &NewOp1 = NewMI1.getOperand(3);
8068 MachineOperand &NewOp2 = NewMI2.getOperand(3);
8069
8070 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
8071 "Must have dead EFLAGS operand in reassociable instruction");
8072 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
8073 "Must have dead EFLAGS operand in reassociable instruction");
8074
8075 (void)OldOp1;
8076 (void)OldOp2;
8077
8078 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
8079 "Unexpected operand in reassociable instruction");
8080 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
8081 "Unexpected operand in reassociable instruction");
8082
8083 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8084 // of this pass or other passes. The EFLAGS operands must be dead in these new
8085 // instructions because the EFLAGS operands in the original instructions must
8086 // be dead in order for reassociation to occur.
8087 NewOp1.setIsDead();
8088 NewOp2.setIsDead();
8089}
8090
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8091std::pair<unsigned, unsigned>
8092X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8093 return std::make_pair(TF, 0u);
8094}
8095
8096ArrayRef<std::pair<unsigned, const char *>>
8097X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8098 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]8099 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8100 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8101 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8102 {MO_GOT, "x86-got"},
8103 {MO_GOTOFF, "x86-gotoff"},
8104 {MO_GOTPCREL, "x86-gotpcrel"},
8105 {MO_PLT, "x86-plt"},
8106 {MO_TLSGD, "x86-tlsgd"},
8107 {MO_TLSLD, "x86-tlsld"},
8108 {MO_TLSLDM, "x86-tlsldm"},
8109 {MO_GOTTPOFF, "x86-gottpoff"},
8110 {MO_INDNTPOFF, "x86-indntpoff"},
8111 {MO_TPOFF, "x86-tpoff"},
8112 {MO_DTPOFF, "x86-dtpoff"},
8113 {MO_NTPOFF, "x86-ntpoff"},
8114 {MO_GOTNTPOFF, "x86-gotntpoff"},
8115 {MO_DLLIMPORT, "x86-dllimport"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8116 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8117 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]8118 {MO_TLVP, "x86-tlvp"},
8119 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8120 {MO_SECREL, "x86-secrel"}};
8121 return makeArrayRef(TargetFlags);
8122}
8123
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8124namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]8125 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8126 /// global base register for x86-32.
8127 struct CGBR : public MachineFunctionPass {
8128 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]8129 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8130
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8131 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8132 const X86TargetMachine *TM =
8133 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8134 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8135
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]8136 // Don't do anything if this is 64-bit as 64-bit PIC
8137 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8138 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]8139 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8140
8141 // Only emit a global base reg in PIC mode.
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]8142 if (!TM->isPositionIndependent())
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8143 return false;
8144
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]8145 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8146 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8147
8148 // If we didn't need a GlobalBaseReg, don't insert code.
8149 if (GlobalBaseReg == 0)
8150 return false;
8151
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8152 // Insert the set of GlobalBaseReg into the first MBB of the function
8153 MachineBasicBlock &FirstMBB = MF.front();
8154 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8155 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8156 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8157 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8158
8159 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8160 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]8161 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8162 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]8163 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]8164
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8165 // Operand of MovePCtoStack is completely ignored by asm printer. It's
8166 // only used in JIT code emission as displacement to pc.
8167 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]8168
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8169 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
8170 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8171 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8172 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
8173 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8174 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8175 X86II::MO_GOT_ABSOLUTE_ADDRESS);
8176 }
8177
8178 return true;
8179 }
8180
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8181 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8182 return "X86 PIC Global Base Reg Initialization";
8183 }
8184
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8185 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8186 AU.setPreservesCFG();
8187 MachineFunctionPass::getAnalysisUsage(AU);
8188 }
8189 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8190}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]8191
8192char CGBR::ID = 0;
8193FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]8194llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8195
8196namespace {
8197 struct LDTLSCleanup : public MachineFunctionPass {
8198 static char ID;
8199 LDTLSCleanup() : MachineFunctionPass(ID) {}
8200
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8201 bool runOnMachineFunction(MachineFunction &MF) override {
Andrew Kaylor2bee5ef2016-04-26 21:44:24 +0000[diff] [blame]8202 if (skipFunction(*MF.getFunction()))
8203 return false;
8204
8205 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8206 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8207 // No point folding accesses if there isn't at least two.
8208 return false;
8209 }
8210
8211 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8212 return VisitNode(DT->getRootNode(), 0);
8213 }
8214
8215 // Visit the dominator subtree rooted at Node in pre-order.
8216 // If TLSBaseAddrReg is non-null, then use that to replace any
8217 // TLS_base_addr instructions. Otherwise, create the register
8218 // when the first such instruction is seen, and then use it
8219 // as we encounter more instructions.
8220 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8221 MachineBasicBlock *BB = Node->getBlock();
8222 bool Changed = false;
8223
8224 // Traverse the current block.
8225 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8226 ++I) {
8227 switch (I->getOpcode()) {
8228 case X86::TLS_base_addr32:
8229 case X86::TLS_base_addr64:
8230 if (TLSBaseAddrReg)
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8231 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8232 else
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8233 I = SetRegister(*I, &TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8234 Changed = true;
8235 break;
8236 default:
8237 break;
8238 }
8239 }
8240
8241 // Visit the children of this block in the dominator tree.
8242 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8243 I != E; ++I) {
8244 Changed |= VisitNode(*I, TLSBaseAddrReg);
8245 }
8246
8247 return Changed;
8248 }
8249
8250 // Replace the TLS_base_addr instruction I with a copy from
8251 // TLSBaseAddrReg, returning the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8252 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8253 unsigned TLSBaseAddrReg) {
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8254 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8255 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8256 const bool is64Bit = STI.is64Bit();
8257 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8258
8259 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8260 MachineInstr *Copy =
8261 BuildMI(*I.getParent(), I, I.getDebugLoc(),
8262 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8263 .addReg(TLSBaseAddrReg);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8264
8265 // Erase the TLS_base_addr instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8266 I.eraseFromParent();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8267
8268 return Copy;
8269 }
8270
8271 // Create a virtal register in *TLSBaseAddrReg, and populate it by
8272 // inserting a copy instruction after I. Returns the new instruction.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8273 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8274 MachineFunction *MF = I.getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]8275 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8276 const bool is64Bit = STI.is64Bit();
8277 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8278
8279 // Create a virtual register for the TLS base address.
8280 MachineRegisterInfo &RegInfo = MF->getRegInfo();
8281 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8282 ? &X86::GR64RegClass
8283 : &X86::GR32RegClass);
8284
8285 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
Duncan P. N. Exon Smith7b4c18e2016-07-12 03:18:50 +0000[diff] [blame]8286 MachineInstr *Next = I.getNextNode();
8287 MachineInstr *Copy =
8288 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8289 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8290 .addReg(is64Bit ? X86::RAX : X86::EAX);
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8291
8292 return Copy;
8293 }
8294
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8295 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8296 return "Local Dynamic TLS Access Clean-up";
8297 }
8298
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]8299 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8300 AU.setPreservesCFG();
8301 AU.addRequired<MachineDominatorTree>();
8302 MachineFunctionPass::getAnalysisUsage(AU);
8303 }
8304 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]8305}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]8306
8307char LDTLSCleanup::ID = 0;
8308FunctionPass*
8309llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }