Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	10	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	11	#include "MCTargetDesc/ARMAddressingModes.h"
				12	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	14	#include "llvm/MC/MCContext.h"
				15	#include "llvm/MC/MCExpr.h"
				16	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	17	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	18	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	19	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	20	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	21	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	22	#include "llvm/Support/LEB128.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	23	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	24	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	25	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	26
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	27	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	28
Chandler Carruth	84e68b2	2014-04-22 02:41:26 +0000	[diff] [blame]	29	#define DEBUG_TYPE "arm-disassembler"
				30
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	31	typedef MCDisassembler::DecodeStatus DecodeStatus;
				32
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	33	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	34	// Handles the condition code status of instructions in IT blocks
				35	class ITStatus
				36	{
				37	public:
				38	// Returns the condition code for instruction in IT block
				39	unsigned getITCC() {
				40	unsigned CC = ARMCC::AL;
				41	if (instrInITBlock())
				42	CC = ITStates.back();
				43	return CC;
				44	}
				45
				46	// Advances the IT block state to the next T or E
				47	void advanceITState() {
				48	ITStates.pop_back();
				49	}
				50
				51	// Returns true if the current instruction is in an IT block
				52	bool instrInITBlock() {
				53	return !ITStates.empty();
				54	}
				55
				56	// Returns true if current instruction is the last instruction in an IT block
				57	bool instrLastInITBlock() {
				58	return ITStates.size() == 1;
				59	}
				60
				61	// Called when decoding an IT instruction. Sets the IT state for the following
				62	// instructions that for the IT block. Firstcond and Mask correspond to the
				63	// fields in the IT instruction encoding.
				64	void setITState(char Firstcond, char Mask) {
				65	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	66	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	67	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	68	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				69	assert(NumTZ <= 3 && "Invalid IT mask!");
				70	// push condition codes onto the stack the correct order for the pops
				71	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				72	bool T = ((Mask >> Pos) & 1) == CondBit0;
				73	if (T)
				74	ITStates.push_back(CCBits);
				75	else
				76	ITStates.push_back(CCBits ^ 1);
				77	}
				78	ITStates.push_back(CCBits);
				79	}
				80
				81	private:
				82	std::vector<unsigned char> ITStates;
				83	};
				84	}
				85
				86	namespace {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	87	/// ARM disassembler for all ARM platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	class ARMDisassembler : public MCDisassembler {
				89	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	90	ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				91	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	92	}
				93
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	94	~ARMDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	96	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	97	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	98	raw_ostream &VStream,
				99	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	100	};
				101
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	102	/// Thumb disassembler for all Thumb platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	103	class ThumbDisassembler : public MCDisassembler {
				104	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	105	ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				106	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	}
				108
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	109	~ThumbDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	110
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	111	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	112	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	113	raw_ostream &VStream,
				114	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	115
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	117	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	118	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	119	void UpdateThumbVFPPredicate(MCInst&) const;
				120	};
				121	}
				122
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	123	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	124	switch (In) {
				125	case MCDisassembler::Success:
				126	// Out stays the same.
				127	return true;
				128	case MCDisassembler::SoftFail:
				129	Out = In;
				130	return true;
				131	case MCDisassembler::Fail:
				132	Out = In;
				133	return false;
				134	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	135	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	136	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	137
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	138
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	139	// Forward declare these because the autogenerated code will reference them.
				140	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	141	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	142	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	143	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	144	unsigned RegNo, uint64_t Address,
				145	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	146	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				147	unsigned RegNo, uint64_t Address,
				148	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	149	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	150	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	151	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	153	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	154	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	155	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				156	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	157	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	158	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	159	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	160	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	161	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	164	unsigned RegNo,
				165	uint64_t Address,
				166	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	167	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	169	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	170	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	171	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	172	unsigned RegNo, uint64_t Address,
				173	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	174
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	175	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	177	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	178	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	179	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	180	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	181	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	183	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	185
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	187	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	191	unsigned Insn,
				192	uint64_t Address,
				193	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
				202
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	204	unsigned Insn,
				205	uint64_t Adddress,
				206	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	215	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				216	uint64_t Address, const void *Decoder);
				217	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				218	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	219	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	220	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	221	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	223	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	224	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	225	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	226	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	227	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				228	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	229	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	230	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	231	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	232	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	233	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				234	uint64_t Address, const void *Decoder);
				235	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				236	uint64_t Address, const void *Decoder);
				237	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				238	uint64_t Address, const void *Decoder);
				239	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				240	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	241	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	242	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	243	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	244	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	245	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	246	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	247	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	248	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	249	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	250	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	251	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	252	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	253	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	254	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	255	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	256	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	257	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	258	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	259	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	260	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	261	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	262	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	263	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	264	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	265	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	266	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	267	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	268	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	269	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	270	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	271	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	272	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	273	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				274	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	275	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	276	uint64_t Address, const void *Decoder);
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	277	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
				278	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	279	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	280	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	281	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	282	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	283	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	284	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	285	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	286	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	287	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	288	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	289	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	290	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	291	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	292	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	293	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	294	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	295	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	296	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	297	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	298	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	299	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	300	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	301	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	302	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	303	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	304	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	305	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	306	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	307	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	308	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	309	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	310	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	311	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	312	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	313	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	314	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	315	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	316	uint64_t Address, const void *Decoder);
				317
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	318
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	319	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	320	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	321	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	322	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	323	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	324	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	325	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	326	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	327	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	328	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	329	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	330	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	331	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	332	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	333	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	334	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	335	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	336	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	337	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	338	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	339	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				340	uint64_t Address, const void* Decoder);
				341	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				342	uint64_t Address, const void* Decoder);
				343	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				344	uint64_t Address, const void* Decoder);
				345	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				346	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	347	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	348	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	349	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	350	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	351	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	352	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	353	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	354	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	355	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	356	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	357	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	358	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	359	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	360	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	361	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	362	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	363	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				364	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	365	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	366	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	367	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	368	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	369	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	370	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	371	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	372	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	373	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	374	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	375	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	376	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	377	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	378	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	379	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	380	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	381	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	382	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	383	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	384	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	385	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	386	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	387	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	388	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	389	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	390	uint64_t Address, const void *Decoder);
				391
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	392	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	393	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	394	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				395	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	396	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	397
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	398	static MCDisassembler *createARMDisassembler(const Target &T,
				399	const MCSubtargetInfo &STI,
				400	MCContext &Ctx) {
				401	return new ARMDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	402	}
				403
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	404	static MCDisassembler *createThumbDisassembler(const Target &T,
				405	const MCSubtargetInfo &STI,
				406	MCContext &Ctx) {
				407	return new ThumbDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	408	}
				409
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	410	// Post-decoding checks
				411	static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
				412	uint64_t Address, raw_ostream &OS,
				413	raw_ostream &CS,
				414	uint32_t Insn,
				415	DecodeStatus Result)
				416	{
				417	switch (MI.getOpcode()) {
				418	case ARM::HVC: {
				419	// HVC is undefined if condition = 0xf otherwise upredictable
				420	// if condition != 0xe
				421	uint32_t Cond = (Insn >> 28) & 0xF;
				422	if (Cond == 0xF)
				423	return MCDisassembler::Fail;
				424	if (Cond != 0xE)
				425	return MCDisassembler::SoftFail;
				426	return Result;
				427	}
				428	default: return Result;
				429	}
				430	}
				431
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	432	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	433	ArrayRef<uint8_t> Bytes,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	434	uint64_t Address, raw_ostream &OS,
				435	raw_ostream &CS) const {
				436	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	437
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	438	assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	439	"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
				440	"mode!");
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	441
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	442	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	443	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	444	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	445	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	446	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	447
				448	// Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	449	uint32_t Insn =
				450	(Bytes[3] << 24) \| (Bytes[2] << 16) \| (Bytes[1] << 8) \| (Bytes[0] << 0);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	451
				452	// Calling the auto-generated decoder function.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	453	DecodeStatus Result =
				454	decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
				455	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	456	Size = 4;
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	457	return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	458	}
				459
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	460	// VFP and NEON instructions, similarly, are shared between ARM
				461	// and Thumb modes.
				462	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	463	Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
				464	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	465	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	466	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	467	}
				468
				469	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	470	Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
				471	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	472	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	473	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	474	}
				475
				476	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	477	Result =
				478	decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
				479	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	480	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	481	// Add a fake predicate operand, because we share these instruction
				482	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	483	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				484	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	485	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	486	}
				487
				488	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	489	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	490	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	491	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	492	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	493	// Add a fake predicate operand, because we share these instruction
				494	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	495	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				496	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	497	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	498	}
				499
				500	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	501	Result =
				502	decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
				503	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	504	Size = 4;
				505	// Add a fake predicate operand, because we share these instruction
				506	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	507	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				508	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	509	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	510	}
				511
				512	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	513	Result =
				514	decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
				515	if (Result != MCDisassembler::Fail) {
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	516	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	517	return Result;
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	518	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	519
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	520	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	521	Result =
				522	decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
				523	if (Result != MCDisassembler::Fail) {
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	524	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	525	return Result;
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	526	}
				527
				528	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	529	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	530	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	531	}
				532
				533	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	534	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	535	}
				536
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	537	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				538	/// immediate Value in the MCInst. The immediate Value has had any PC
				539	/// adjustment made by the caller. If the instruction is a branch instruction
				540	/// then isBranch is true, else false. If the getOpInfo() function was set as
				541	/// part of the setupForSymbolicDisassembly() call then that function is called
				542	/// to get any symbolic information at the Address for this instruction. If
				543	/// that returns non-zero then the symbolic information it returns is used to
				544	/// create an MCExpr and that is added as an operand to the MCInst. If
				545	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				546	/// Value is done and if a symbol is found an MCExpr is created with that, else
				547	/// an MCExpr with Value is created. This function returns true if it adds an
				548	/// operand to the MCInst and false otherwise.
				549	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				550	bool isBranch, uint64_t InstSize,
				551	MCInst &MI, const void *Decoder) {
				552	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	553	// FIXME: Does it make sense for value to be negative?
				554	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				555	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	556	}
				557
				558	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				559	/// referenced by a load instruction with the base register that is the Pc.
				560	/// These can often be values in a literal pool near the Address of the
				561	/// instruction. The Address of the instruction and its immediate Value are
				562	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	563	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	564	/// the referenced address is that of a symbol. Or it will return a pointer to
				565	/// a literal 'C' string if the referenced address of the literal pool's entry
				566	/// is an address into a section with 'C' string literals.
				567	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	568	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	569	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	570	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	571	}
				572
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	573	// Thumb1 instructions don't have explicit S bits. Rather, they
				574	// implicitly set CPSR. Since it's not represented in the encoding, the
				575	// auto-generated decoder won't inject the CPSR operand. We need to fix
				576	// that as a post-pass.
				577	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				578	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	579	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	580	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	581	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				582	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	583	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	584	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	585	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				586	return;
				587	}
				588	}
				589
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	590	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	591	}
				592
				593	// Most Thumb instructions don't have explicit predicates in the
				594	// encoding, but rather get their predicates from IT context. We need
				595	// to fix up the predicate operands using this context information as a
				596	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	597	MCDisassembler::DecodeStatus
				598	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	599	MCDisassembler::DecodeStatus S = Success;
				600
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	601	// A few instructions actually have predicates encoded in them. Don't
				602	// try to overwrite it if we're seeing one of those.
				603	switch (MI.getOpcode()) {
				604	case ARM::tBcc:
				605	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	606	case ARM::tCBZ:
				607	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	608	case ARM::tCPS:
				609	case ARM::t2CPS3p:
				610	case ARM::t2CPS2p:
				611	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	612	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	613	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	614	// Some instructions (mostly conditional branches) are not
				615	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	616	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	617	S = SoftFail;
				618	else
				619	return Success;
				620	break;
				621	case ARM::tB:
				622	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	623	case ARM::t2TBB:
				624	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	625	// Some instructions (mostly unconditional branches) can
				626	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	627	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	628	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	629	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	630	default:
				631	break;
				632	}
				633
				634	// If we're in an IT block, base the predicate on that. Otherwise,
				635	// assume a predicate of AL.
				636	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	637	CC = ITBlock.getITCC();
				638	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	639	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	640	if (ITBlock.instrInITBlock())
				641	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	642
				643	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	644	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	645	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	646	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				647	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	648	if (OpInfo[i].isPredicate()) {
				649	I = MI.insert(I, MCOperand::CreateImm(CC));
				650	++I;
				651	if (CC == ARMCC::AL)
				652	MI.insert(I, MCOperand::CreateReg(0));
				653	else
				654	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	655	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	656	}
				657	}
				658
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	659	I = MI.insert(I, MCOperand::CreateImm(CC));
				660	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	661	if (CC == ARMCC::AL)
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	662	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	663	else
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	664	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	665
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	666	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	667	}
				668
				669	// Thumb VFP instructions are a special case. Because we share their
				670	// encodings between ARM and Thumb modes, and they are predicable in ARM
				671	// mode, the auto-generated decoder will give them an (incorrect)
				672	// predicate operand. We need to rewrite these operands based on the IT
				673	// context as a post-pass.
				674	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				675	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	676	CC = ITBlock.getITCC();
				677	if (ITBlock.instrInITBlock())
				678	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	679
				680	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				681	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	682	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				683	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	684	if (OpInfo[i].isPredicate() ) {
				685	I->setImm(CC);
				686	++I;
				687	if (CC == ARMCC::AL)
				688	I->setReg(0);
				689	else
				690	I->setReg(ARM::CPSR);
				691	return;
				692	}
				693	}
				694	}
				695
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	696	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	697	ArrayRef<uint8_t> Bytes,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	698	uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	699	raw_ostream &OS,
				700	raw_ostream &CS) const {
				701	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	702
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	703	assert(STI.getFeatureBits()[ARM::ModeThumb] &&
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	704	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				705
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	706	// We want to read exactly 2 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	707	if (Bytes.size() < 2) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	708	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	709	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	710	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	711
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	712	uint16_t Insn16 = (Bytes[1] << 8) \| Bytes[0];
				713	DecodeStatus Result =
				714	decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
				715	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	716	Size = 2;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	717	Check(Result, AddThumbPredicate(MI));
				718	return Result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	719	}
				720
				721	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	722	Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
				723	STI);
				724	if (Result) {
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	725	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	726	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	727	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	728	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	729	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	730	}
				731
				732	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	733	Result =
				734	decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
				735	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	736	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	737
				738	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				739	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	740	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	741	Result = MCDisassembler::SoftFail;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	742
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	743	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	744
				745	// If we find an IT instruction, we need to parse its condition
				746	// code and mask operands so that we can apply them correctly
				747	// to the subsequent instructions.
				748	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	749
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	750	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	751	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	752	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	753	}
				754
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	755	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	756	}
				757
				758	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	759	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	760	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	761	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	762	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	763
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	764	uint32_t Insn32 =
				765	(Bytes[3] << 8) \| (Bytes[2] << 0) \| (Bytes[1] << 24) \| (Bytes[0] << 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	766	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	767	Result =
				768	decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
				769	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	770	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	771	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	772	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	773	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	774	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	775	}
				776
				777	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	778	Result =
				779	decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
				780	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	781	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	782	Check(Result, AddThumbPredicate(MI));
				783	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	784	}
				785
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	786	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	787	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	788	Result =
				789	decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
				790	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	791	Size = 4;
				792	UpdateThumbVFPPredicate(MI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	793	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	794	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	795	}
				796
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	797	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	798	Result =
				799	decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
				800	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	801	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	802	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	803	}
				804
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	805	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	806	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	807	Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
				808	STI);
				809	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	810	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	811	Check(Result, AddThumbPredicate(MI));
				812	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	813	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	814	}
				815
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	816	if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	817	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	818	uint32_t NEONLdStInsn = Insn32;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	819	NEONLdStInsn &= 0xF0FFFFFF;
				820	NEONLdStInsn \|= 0x04000000;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	821	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	822	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	823	if (Result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	824	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	825	Check(Result, AddThumbPredicate(MI));
				826	return Result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	827	}
				828	}
				829
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	830	if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	831	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	832	uint32_t NEONDataInsn = Insn32;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	833	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				834	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				835	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	836	Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	837	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	838	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	839	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	840	Check(Result, AddThumbPredicate(MI));
				841	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	842	}
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	843
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	844	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	845	uint32_t NEONCryptoInsn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	846	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				847	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				848	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	849	Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	850	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	851	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	852	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	853	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	854	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	855
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	856	MI.clear();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	857	uint32_t NEONv8Insn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	858	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	859	Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	860	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	861	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	862	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	863	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	864	}
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	865	}
				866
				867	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	868	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	869	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	870	}
				871
				872
				873	extern "C" void LLVMInitializeARMDisassembler() {
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	874	TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	875	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	876	TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	877	createARMDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	878	TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	879	createThumbDisassembler);
Christian Pirker	dc9ff75	2014-04-01 15:19:30 +0000	[diff] [blame]	880	TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	881	createThumbDisassembler);
				882	}
				883
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	884	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	885	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				886	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				887	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				888	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				889	};
				890
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	891	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	892	uint64_t Address, const void *Decoder) {
				893	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	894	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	895
				896	unsigned Register = GPRDecoderTable[RegNo];
				897	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	898	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	899	}
				900
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	901	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	902	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	903	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	904	DecodeStatus S = MCDisassembler::Success;
				905
				906	if (RegNo == 15)
				907	S = MCDisassembler::SoftFail;
				908
				909	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				910
				911	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	912	}
				913
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	914	static DecodeStatus
				915	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				916	uint64_t Address, const void *Decoder) {
				917	DecodeStatus S = MCDisassembler::Success;
				918
				919	if (RegNo == 15)
				920	{
				921	Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
				922	return MCDisassembler::Success;
				923	}
				924
				925	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				926	return S;
				927	}
				928
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	929	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	930	uint64_t Address, const void *Decoder) {
				931	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	932	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	933	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				934	}
				935
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	936	static const uint16_t GPRPairDecoderTable[] = {
				937	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				938	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				939	};
				940
				941	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				942	uint64_t Address, const void *Decoder) {
				943	DecodeStatus S = MCDisassembler::Success;
				944
				945	if (RegNo > 13)
				946	return MCDisassembler::Fail;
				947
				948	if ((RegNo & 1) \|\| RegNo == 0xe)
				949	S = MCDisassembler::SoftFail;
				950
				951	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
				952	Inst.addOperand(MCOperand::CreateReg(RegisterPair));
				953	return S;
				954	}
				955
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	956	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	957	uint64_t Address, const void *Decoder) {
				958	unsigned Register = 0;
				959	switch (RegNo) {
				960	case 0:
				961	Register = ARM::R0;
				962	break;
				963	case 1:
				964	Register = ARM::R1;
				965	break;
				966	case 2:
				967	Register = ARM::R2;
				968	break;
				969	case 3:
				970	Register = ARM::R3;
				971	break;
				972	case 9:
				973	Register = ARM::R9;
				974	break;
				975	case 12:
				976	Register = ARM::R12;
				977	break;
				978	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	979	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	980	}
				981
				982	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	983	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	984	}
				985
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	986	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	987	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	988	DecodeStatus S = MCDisassembler::Success;
				989	if (RegNo == 13 \|\| RegNo == 15)
				990	S = MCDisassembler::SoftFail;
				991	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				992	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	993	}
				994
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	995	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	996	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				997	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				998	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				999	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				1000	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				1001	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				1002	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				1003	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				1004	};
				1005
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1006	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1007	uint64_t Address, const void *Decoder) {
				1008	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1009	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1010
				1011	unsigned Register = SPRDecoderTable[RegNo];
				1012	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1013	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1014	}
				1015
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1016	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1017	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1018	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1019	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1020	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1021	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1022	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1023	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1024	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1025	};
				1026
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1027	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1028	uint64_t Address, const void *Decoder) {
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	1029	const FeatureBitset &featureBits =
				1030	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1031
				1032	bool hasD16 = featureBits[ARM::FeatureD16];
Oliver Stannard	9e89d8c	2014-11-05 12:06:39 +0000	[diff] [blame]	1033
				1034	if (RegNo > 31 \|\| (hasD16 && RegNo > 15))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1035	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1036
				1037	unsigned Register = DPRDecoderTable[RegNo];
				1038	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1039	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1040	}
				1041
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1042	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1043	uint64_t Address, const void *Decoder) {
				1044	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1045	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1046	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1047	}
				1048
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1049	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1050	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1051	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1052	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1053	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1054	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1055	}
				1056
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1057	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1058	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1059	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1060	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1061	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1062	};
				1063
				1064
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1065	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1066	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1067	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1068	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1069	RegNo >>= 1;
				1070
				1071	unsigned Register = QPRDecoderTable[RegNo];
				1072	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1073	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1074	}
				1075
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1076	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1077	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1078	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1079	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1080	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1081	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1082	ARM::Q15
				1083	};
				1084
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1085	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1086	uint64_t Address, const void *Decoder) {
				1087	if (RegNo > 30)
				1088	return MCDisassembler::Fail;
				1089
				1090	unsigned Register = DPairDecoderTable[RegNo];
				1091	Inst.addOperand(MCOperand::CreateReg(Register));
				1092	return MCDisassembler::Success;
				1093	}
				1094
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1095	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1096	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1097	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1098	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1099	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1100	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1101	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1102	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1103	ARM::D28_D30, ARM::D29_D31
				1104	};
				1105
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1106	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1107	unsigned RegNo,
				1108	uint64_t Address,
				1109	const void *Decoder) {
				1110	if (RegNo > 29)
				1111	return MCDisassembler::Fail;
				1112
				1113	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1114	Inst.addOperand(MCOperand::CreateReg(Register));
				1115	return MCDisassembler::Success;
				1116	}
				1117
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1118	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1119	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1120	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1121	// AL predicate is not allowed on Thumb1 branches.
				1122	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1123	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1124	Inst.addOperand(MCOperand::CreateImm(Val));
				1125	if (Val == ARMCC::AL) {
				1126	Inst.addOperand(MCOperand::CreateReg(0));
				1127	} else
				1128	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1129	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1130	}
				1131
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1132	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1133	uint64_t Address, const void *Decoder) {
				1134	if (Val)
				1135	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1136	else
				1137	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1138	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1139	}
				1140
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1141	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1142	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1143	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1144
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1145	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1146	unsigned type = fieldFromInstruction(Val, 5, 2);
				1147	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1148
				1149	// Register-immediate
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1150	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1151	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1152
				1153	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1154	switch (type) {
				1155	case 0:
				1156	Shift = ARM_AM::lsl;
				1157	break;
				1158	case 1:
				1159	Shift = ARM_AM::lsr;
				1160	break;
				1161	case 2:
				1162	Shift = ARM_AM::asr;
				1163	break;
				1164	case 3:
				1165	Shift = ARM_AM::ror;
				1166	break;
				1167	}
				1168
				1169	if (Shift == ARM_AM::ror && imm == 0)
				1170	Shift = ARM_AM::rrx;
				1171
				1172	unsigned Op = Shift \| (imm << 3);
				1173	Inst.addOperand(MCOperand::CreateImm(Op));
				1174
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1175	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1176	}
				1177
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1178	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1179	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1180	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1181
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1182	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1183	unsigned type = fieldFromInstruction(Val, 5, 2);
				1184	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1185
				1186	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1187	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1188	return MCDisassembler::Fail;
				1189	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1190	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1191
				1192	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1193	switch (type) {
				1194	case 0:
				1195	Shift = ARM_AM::lsl;
				1196	break;
				1197	case 1:
				1198	Shift = ARM_AM::lsr;
				1199	break;
				1200	case 2:
				1201	Shift = ARM_AM::asr;
				1202	break;
				1203	case 3:
				1204	Shift = ARM_AM::ror;
				1205	break;
				1206	}
				1207
				1208	Inst.addOperand(MCOperand::CreateImm(Shift));
				1209
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1210	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1211	}
				1212
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1213	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1214	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1215	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1216
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1217	bool NeedDisjointWriteback = false;
				1218	unsigned WritebackReg = 0;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1219	switch (Inst.getOpcode()) {
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1220	default:
				1221	break;
				1222	case ARM::LDMIA_UPD:
				1223	case ARM::LDMDB_UPD:
				1224	case ARM::LDMIB_UPD:
				1225	case ARM::LDMDA_UPD:
				1226	case ARM::t2LDMIA_UPD:
				1227	case ARM::t2LDMDB_UPD:
				1228	case ARM::t2STMIA_UPD:
				1229	case ARM::t2STMDB_UPD:
				1230	NeedDisjointWriteback = true;
				1231	WritebackReg = Inst.getOperand(0).getReg();
				1232	break;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1233	}
				1234
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1235	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1236	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1237	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1238	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1239	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1240	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1241	// Writeback not allowed if Rn is in the target list.
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1242	if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1243	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1244	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1245	}
				1246
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1247	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1248	}
				1249
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1250	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1251	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1252	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1253
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1254	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1255	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1256
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1257	// In case of unpredictable encoding, tweak the operands.
				1258	if (regs == 0 \|\| (Vd + regs) > 32) {
				1259	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1260	regs = std::max( 1u, regs);
				1261	S = MCDisassembler::SoftFail;
				1262	}
				1263
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1264	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1265	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1266	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1267	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1268	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1269	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1270
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1271	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1272	}
				1273
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1274	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1275	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1276	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1277
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1278	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1279	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1280
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1281	// In case of unpredictable encoding, tweak the operands.
				1282	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1283	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1284	regs = std::max( 1u, regs);
				1285	regs = std::min(16u, regs);
				1286	S = MCDisassembler::SoftFail;
				1287	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1288
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1289	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1290	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1291	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1292	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1293	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1294	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1295
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1296	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1297	}
				1298
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1299	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1300	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1301	// This operand encodes a mask of contiguous zeros between a specified MSB
				1302	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1303	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1304	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1305	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1306	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1307	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1308
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1309	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1310	if (lsb > msb) {
				1311	Check(S, MCDisassembler::SoftFail);
				1312	// The check above will cause the warning for the "potentially undefined
				1313	// instruction encoding" but we can't build a bad MCOperand value here
				1314	// with a lsb > msb or else printing the MCInst will cause a crash.
				1315	lsb = msb;
				1316	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1317
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1318	uint32_t msb_mask = 0xFFFFFFFF;
				1319	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1320	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1321
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1322	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1323	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1324	}
				1325
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1326	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1327	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1328	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1329
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1330	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1331	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1332	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1333	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1334	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1335	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1336
				1337	switch (Inst.getOpcode()) {
				1338	case ARM::LDC_OFFSET:
				1339	case ARM::LDC_PRE:
				1340	case ARM::LDC_POST:
				1341	case ARM::LDC_OPTION:
				1342	case ARM::LDCL_OFFSET:
				1343	case ARM::LDCL_PRE:
				1344	case ARM::LDCL_POST:
				1345	case ARM::LDCL_OPTION:
				1346	case ARM::STC_OFFSET:
				1347	case ARM::STC_PRE:
				1348	case ARM::STC_POST:
				1349	case ARM::STC_OPTION:
				1350	case ARM::STCL_OFFSET:
				1351	case ARM::STCL_PRE:
				1352	case ARM::STCL_POST:
				1353	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1354	case ARM::t2LDC_OFFSET:
				1355	case ARM::t2LDC_PRE:
				1356	case ARM::t2LDC_POST:
				1357	case ARM::t2LDC_OPTION:
				1358	case ARM::t2LDCL_OFFSET:
				1359	case ARM::t2LDCL_PRE:
				1360	case ARM::t2LDCL_POST:
				1361	case ARM::t2LDCL_OPTION:
				1362	case ARM::t2STC_OFFSET:
				1363	case ARM::t2STC_PRE:
				1364	case ARM::t2STC_POST:
				1365	case ARM::t2STC_OPTION:
				1366	case ARM::t2STCL_OFFSET:
				1367	case ARM::t2STCL_PRE:
				1368	case ARM::t2STCL_POST:
				1369	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1370	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1371	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1372	break;
				1373	default:
				1374	break;
				1375	}
				1376
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	1377	const FeatureBitset &featureBits =
				1378	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1379	if (featureBits[ARM::HasV8Ops] && (coproc != 14))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	1380	return MCDisassembler::Fail;
				1381
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1382	Inst.addOperand(MCOperand::CreateImm(coproc));
				1383	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1384	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1385	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1386
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1387	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1388	case ARM::t2LDC2_OFFSET:
				1389	case ARM::t2LDC2L_OFFSET:
				1390	case ARM::t2LDC2_PRE:
				1391	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1392	case ARM::t2STC2_OFFSET:
				1393	case ARM::t2STC2L_OFFSET:
				1394	case ARM::t2STC2_PRE:
				1395	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1396	case ARM::LDC2_OFFSET:
				1397	case ARM::LDC2L_OFFSET:
				1398	case ARM::LDC2_PRE:
				1399	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1400	case ARM::STC2_OFFSET:
				1401	case ARM::STC2L_OFFSET:
				1402	case ARM::STC2_PRE:
				1403	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1404	case ARM::t2LDC_OFFSET:
				1405	case ARM::t2LDCL_OFFSET:
				1406	case ARM::t2LDC_PRE:
				1407	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1408	case ARM::t2STC_OFFSET:
				1409	case ARM::t2STCL_OFFSET:
				1410	case ARM::t2STC_PRE:
				1411	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1412	case ARM::LDC_OFFSET:
				1413	case ARM::LDCL_OFFSET:
				1414	case ARM::LDC_PRE:
				1415	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1416	case ARM::STC_OFFSET:
				1417	case ARM::STCL_OFFSET:
				1418	case ARM::STC_PRE:
				1419	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1420	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1421	Inst.addOperand(MCOperand::CreateImm(imm));
				1422	break;
				1423	case ARM::t2LDC2_POST:
				1424	case ARM::t2LDC2L_POST:
				1425	case ARM::t2STC2_POST:
				1426	case ARM::t2STC2L_POST:
				1427	case ARM::LDC2_POST:
				1428	case ARM::LDC2L_POST:
				1429	case ARM::STC2_POST:
				1430	case ARM::STC2L_POST:
				1431	case ARM::t2LDC_POST:
				1432	case ARM::t2LDCL_POST:
				1433	case ARM::t2STC_POST:
				1434	case ARM::t2STCL_POST:
				1435	case ARM::LDC_POST:
				1436	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1437	case ARM::STC_POST:
				1438	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1439	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1440	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1441	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1442	// The 'option' variant doesn't encode 'U' in the immediate since
				1443	// the immediate is unsigned [0,255].
				1444	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1445	break;
				1446	}
				1447
				1448	switch (Inst.getOpcode()) {
				1449	case ARM::LDC_OFFSET:
				1450	case ARM::LDC_PRE:
				1451	case ARM::LDC_POST:
				1452	case ARM::LDC_OPTION:
				1453	case ARM::LDCL_OFFSET:
				1454	case ARM::LDCL_PRE:
				1455	case ARM::LDCL_POST:
				1456	case ARM::LDCL_OPTION:
				1457	case ARM::STC_OFFSET:
				1458	case ARM::STC_PRE:
				1459	case ARM::STC_POST:
				1460	case ARM::STC_OPTION:
				1461	case ARM::STCL_OFFSET:
				1462	case ARM::STCL_PRE:
				1463	case ARM::STCL_POST:
				1464	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1465	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1466	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1467	break;
				1468	default:
				1469	break;
				1470	}
				1471
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1472	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1473	}
				1474
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1475	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1476	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1477	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1478	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1479
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1480	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1481	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1482	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1483	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1484	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1485	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1486	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1487	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1488
				1489	// On stores, the writeback operand precedes Rt.
				1490	switch (Inst.getOpcode()) {
				1491	case ARM::STR_POST_IMM:
				1492	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1493	case ARM::STRB_POST_IMM:
				1494	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1495	case ARM::STRT_POST_REG:
				1496	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1497	case ARM::STRBT_POST_REG:
				1498	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1499	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1500	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1501	break;
				1502	default:
				1503	break;
				1504	}
				1505
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1506	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1507	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1508
				1509	// On loads, the writeback operand comes after Rt.
				1510	switch (Inst.getOpcode()) {
				1511	case ARM::LDR_POST_IMM:
				1512	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1513	case ARM::LDRB_POST_IMM:
				1514	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1515	case ARM::LDRBT_POST_REG:
				1516	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1517	case ARM::LDRT_POST_REG:
				1518	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1519	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1520	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1521	break;
				1522	default:
				1523	break;
				1524	}
				1525
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1526	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1527	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1528
				1529	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1530	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1531	Op = ARM_AM::sub;
				1532
				1533	bool writeback = (P == 0) \|\| (W == 1);
				1534	unsigned idx_mode = 0;
				1535	if (P && writeback)
				1536	idx_mode = ARMII::IndexModePre;
				1537	else if (!P && writeback)
				1538	idx_mode = ARMII::IndexModePost;
				1539
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1540	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1541	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1542
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1543	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1544	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1545	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1546	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1547	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1548	case 0:
				1549	Opc = ARM_AM::lsl;
				1550	break;
				1551	case 1:
				1552	Opc = ARM_AM::lsr;
				1553	break;
				1554	case 2:
				1555	Opc = ARM_AM::asr;
				1556	break;
				1557	case 3:
				1558	Opc = ARM_AM::ror;
				1559	break;
				1560	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1561	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1562	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1563	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1564	if (Opc == ARM_AM::ror && amt == 0)
				1565	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1566	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1567
				1568	Inst.addOperand(MCOperand::CreateImm(imm));
				1569	} else {
				1570	Inst.addOperand(MCOperand::CreateReg(0));
				1571	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1572	Inst.addOperand(MCOperand::CreateImm(tmp));
				1573	}
				1574
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1575	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1576	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1577
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1578	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1579	}
				1580
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1581	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1582	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1583	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1584
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1585	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1586	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1587	unsigned type = fieldFromInstruction(Val, 5, 2);
				1588	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1589	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1590
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1591	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1592	switch (type) {
				1593	case 0:
				1594	ShOp = ARM_AM::lsl;
				1595	break;
				1596	case 1:
				1597	ShOp = ARM_AM::lsr;
				1598	break;
				1599	case 2:
				1600	ShOp = ARM_AM::asr;
				1601	break;
				1602	case 3:
				1603	ShOp = ARM_AM::ror;
				1604	break;
				1605	}
				1606
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1607	if (ShOp == ARM_AM::ror && imm == 0)
				1608	ShOp = ARM_AM::rrx;
				1609
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1610	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1611	return MCDisassembler::Fail;
				1612	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1613	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1614	unsigned shift;
				1615	if (U)
				1616	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1617	else
				1618	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1619	Inst.addOperand(MCOperand::CreateImm(shift));
				1620
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1621	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1622	}
				1623
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1624	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1625	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1626	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1627	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1628
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1629	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1630	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1631	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1632	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1633	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1634	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1635	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1636	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1637	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1638	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1639
				1640	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1641
				1642	// For {LD,ST}RD, Rt must be even, else undefined.
				1643	switch (Inst.getOpcode()) {
				1644	case ARM::STRD:
				1645	case ARM::STRD_PRE:
				1646	case ARM::STRD_POST:
				1647	case ARM::LDRD:
				1648	case ARM::LDRD_PRE:
				1649	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1650	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1651	break;
				1652	default:
				1653	break;
				1654	}
				1655	switch (Inst.getOpcode()) {
				1656	case ARM::STRD:
				1657	case ARM::STRD_PRE:
				1658	case ARM::STRD_POST:
				1659	if (P == 0 && W == 1)
				1660	S = MCDisassembler::SoftFail;
				1661
				1662	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1663	S = MCDisassembler::SoftFail;
				1664	if (type && Rm == 15)
				1665	S = MCDisassembler::SoftFail;
				1666	if (Rt2 == 15)
				1667	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1668	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1669	S = MCDisassembler::SoftFail;
				1670	break;
				1671	case ARM::STRH:
				1672	case ARM::STRH_PRE:
				1673	case ARM::STRH_POST:
				1674	if (Rt == 15)
				1675	S = MCDisassembler::SoftFail;
				1676	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1677	S = MCDisassembler::SoftFail;
				1678	if (!type && Rm == 15)
				1679	S = MCDisassembler::SoftFail;
				1680	break;
				1681	case ARM::LDRD:
				1682	case ARM::LDRD_PRE:
				1683	case ARM::LDRD_POST:
				1684	if (type && Rn == 15){
				1685	if (Rt2 == 15)
				1686	S = MCDisassembler::SoftFail;
				1687	break;
				1688	}
				1689	if (P == 0 && W == 1)
				1690	S = MCDisassembler::SoftFail;
				1691	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1692	S = MCDisassembler::SoftFail;
				1693	if (!type && writeback && Rn == 15)
				1694	S = MCDisassembler::SoftFail;
				1695	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1696	S = MCDisassembler::SoftFail;
				1697	break;
				1698	case ARM::LDRH:
				1699	case ARM::LDRH_PRE:
				1700	case ARM::LDRH_POST:
				1701	if (type && Rn == 15){
				1702	if (Rt == 15)
				1703	S = MCDisassembler::SoftFail;
				1704	break;
				1705	}
				1706	if (Rt == 15)
				1707	S = MCDisassembler::SoftFail;
				1708	if (!type && Rm == 15)
				1709	S = MCDisassembler::SoftFail;
				1710	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1711	S = MCDisassembler::SoftFail;
				1712	break;
				1713	case ARM::LDRSH:
				1714	case ARM::LDRSH_PRE:
				1715	case ARM::LDRSH_POST:
				1716	case ARM::LDRSB:
				1717	case ARM::LDRSB_PRE:
				1718	case ARM::LDRSB_POST:
				1719	if (type && Rn == 15){
				1720	if (Rt == 15)
				1721	S = MCDisassembler::SoftFail;
				1722	break;
				1723	}
				1724	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1725	S = MCDisassembler::SoftFail;
				1726	if (!type && (Rt == 15 \|\| Rm == 15))
				1727	S = MCDisassembler::SoftFail;
				1728	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1729	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1730	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1731	default:
				1732	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1733	}
				1734
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1735	if (writeback) { // Writeback
				1736	if (P)
				1737	U \|= ARMII::IndexModePre << 9;
				1738	else
				1739	U \|= ARMII::IndexModePost << 9;
				1740
				1741	// On stores, the writeback operand precedes Rt.
				1742	switch (Inst.getOpcode()) {
				1743	case ARM::STRD:
				1744	case ARM::STRD_PRE:
				1745	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1746	case ARM::STRH:
				1747	case ARM::STRH_PRE:
				1748	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1749	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1750	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1751	break;
				1752	default:
				1753	break;
				1754	}
				1755	}
				1756
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1757	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1758	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1759	switch (Inst.getOpcode()) {
				1760	case ARM::STRD:
				1761	case ARM::STRD_PRE:
				1762	case ARM::STRD_POST:
				1763	case ARM::LDRD:
				1764	case ARM::LDRD_PRE:
				1765	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1766	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1767	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1768	break;
				1769	default:
				1770	break;
				1771	}
				1772
				1773	if (writeback) {
				1774	// On loads, the writeback operand comes after Rt.
				1775	switch (Inst.getOpcode()) {
				1776	case ARM::LDRD:
				1777	case ARM::LDRD_PRE:
				1778	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1779	case ARM::LDRH:
				1780	case ARM::LDRH_PRE:
				1781	case ARM::LDRH_POST:
				1782	case ARM::LDRSH:
				1783	case ARM::LDRSH_PRE:
				1784	case ARM::LDRSH_POST:
				1785	case ARM::LDRSB:
				1786	case ARM::LDRSB_PRE:
				1787	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1788	case ARM::LDRHTr:
				1789	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1790	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1791	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1792	break;
				1793	default:
				1794	break;
				1795	}
				1796	}
				1797
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1798	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1799	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1800
				1801	if (type) {
				1802	Inst.addOperand(MCOperand::CreateReg(0));
				1803	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1804	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1805	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1806	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1807	Inst.addOperand(MCOperand::CreateImm(U));
				1808	}
				1809
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1810	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1811	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1812
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1813	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1814	}
				1815
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1816	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1817	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1818	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1819
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1820	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1821	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1822
				1823	switch (mode) {
				1824	case 0:
				1825	mode = ARM_AM::da;
				1826	break;
				1827	case 1:
				1828	mode = ARM_AM::ia;
				1829	break;
				1830	case 2:
				1831	mode = ARM_AM::db;
				1832	break;
				1833	case 3:
				1834	mode = ARM_AM::ib;
				1835	break;
				1836	}
				1837
				1838	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1839	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1840	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1841
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1842	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1843	}
				1844
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1845	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1846	uint64_t Address, const void *Decoder) {
				1847	DecodeStatus S = MCDisassembler::Success;
				1848
				1849	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1850	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1851	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1852	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1853
				1854	if (pred == 0xF)
				1855	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1856
				1857	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1858	return MCDisassembler::Fail;
				1859	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1860	return MCDisassembler::Fail;
				1861	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1862	return MCDisassembler::Fail;
				1863	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1864	return MCDisassembler::Fail;
				1865	return S;
				1866	}
				1867
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1868	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1869	unsigned Insn,
				1870	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1871	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1872
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1873	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1874	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1875	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1876
				1877	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1878	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1879	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1880	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1881	Inst.setOpcode(ARM::RFEDA);
				1882	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1883	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1884	Inst.setOpcode(ARM::RFEDA_UPD);
				1885	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1886	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1887	Inst.setOpcode(ARM::RFEDB);
				1888	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1889	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1890	Inst.setOpcode(ARM::RFEDB_UPD);
				1891	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1892	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1893	Inst.setOpcode(ARM::RFEIA);
				1894	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1895	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1896	Inst.setOpcode(ARM::RFEIA_UPD);
				1897	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1898	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1899	Inst.setOpcode(ARM::RFEIB);
				1900	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1901	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1902	Inst.setOpcode(ARM::RFEIB_UPD);
				1903	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1904	case ARM::STMDA:
				1905	Inst.setOpcode(ARM::SRSDA);
				1906	break;
				1907	case ARM::STMDA_UPD:
				1908	Inst.setOpcode(ARM::SRSDA_UPD);
				1909	break;
				1910	case ARM::STMDB:
				1911	Inst.setOpcode(ARM::SRSDB);
				1912	break;
				1913	case ARM::STMDB_UPD:
				1914	Inst.setOpcode(ARM::SRSDB_UPD);
				1915	break;
				1916	case ARM::STMIA:
				1917	Inst.setOpcode(ARM::SRSIA);
				1918	break;
				1919	case ARM::STMIA_UPD:
				1920	Inst.setOpcode(ARM::SRSIA_UPD);
				1921	break;
				1922	case ARM::STMIB:
				1923	Inst.setOpcode(ARM::SRSIB);
				1924	break;
				1925	case ARM::STMIB_UPD:
				1926	Inst.setOpcode(ARM::SRSIB_UPD);
				1927	break;
				1928	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1929	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1930	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1931
				1932	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1933	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1934	// Check SRS encoding constraints
				1935	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1936	fieldFromInstruction(Insn, 20, 1) == 0))
				1937	return MCDisassembler::Fail;
				1938
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1939	Inst.addOperand(
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1940	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1941	return S;
				1942	}
				1943
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1944	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1945	}
				1946
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1947	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1948	return MCDisassembler::Fail;
				1949	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1950	return MCDisassembler::Fail; // Tied
				1951	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1952	return MCDisassembler::Fail;
				1953	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1954	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1955
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1956	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1957	}
				1958
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1959	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1960	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1961	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1962	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1963	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1964	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1965
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1966	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1967
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1968	// This decoder is called from multiple location that do not check
				1969	// the full encoding is valid before they do.
				1970	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1971	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1972	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1973	return MCDisassembler::Fail;
				1974
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1975	// imod == '01' --> UNPREDICTABLE
				1976	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1977	// return failure here. The '01' imod value is unprintable, so there's
				1978	// nothing useful we could do even if we returned UNPREDICTABLE.
				1979
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1980	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1981
				1982	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1983	Inst.setOpcode(ARM::CPS3p);
				1984	Inst.addOperand(MCOperand::CreateImm(imod));
				1985	Inst.addOperand(MCOperand::CreateImm(iflags));
				1986	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1987	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1988	Inst.setOpcode(ARM::CPS2p);
				1989	Inst.addOperand(MCOperand::CreateImm(imod));
				1990	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1991	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1992	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1993	Inst.setOpcode(ARM::CPS1p);
				1994	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1995	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1996	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1997	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1998	Inst.setOpcode(ARM::CPS1p);
				1999	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2000	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2001	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2002
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2003	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2004	}
				2005
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2006	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2007	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2008	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				2009	unsigned M = fieldFromInstruction(Insn, 8, 1);
				2010	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				2011	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2012
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2013	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2014
				2015	// imod == '01' --> UNPREDICTABLE
				2016	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2017	// return failure here. The '01' imod value is unprintable, so there's
				2018	// nothing useful we could do even if we returned UNPREDICTABLE.
				2019
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2020	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2021
				2022	if (imod && M) {
				2023	Inst.setOpcode(ARM::t2CPS3p);
				2024	Inst.addOperand(MCOperand::CreateImm(imod));
				2025	Inst.addOperand(MCOperand::CreateImm(iflags));
				2026	Inst.addOperand(MCOperand::CreateImm(mode));
				2027	} else if (imod && !M) {
				2028	Inst.setOpcode(ARM::t2CPS2p);
				2029	Inst.addOperand(MCOperand::CreateImm(imod));
				2030	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2031	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2032	} else if (!imod && M) {
				2033	Inst.setOpcode(ARM::t2CPS1p);
				2034	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2035	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2036	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2037	// imod == '00' && M == '0' --> this is a HINT instruction
				2038	int imm = fieldFromInstruction(Insn, 0, 8);
				2039	// HINT are defined only for immediate in [0..4]
				2040	if(imm > 4) return MCDisassembler::Fail;
				2041	Inst.setOpcode(ARM::t2HINT);
				2042	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2043	}
				2044
				2045	return S;
				2046	}
				2047
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2048	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2049	uint64_t Address, const void *Decoder) {
				2050	DecodeStatus S = MCDisassembler::Success;
				2051
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2052	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2053	unsigned imm = 0;
				2054
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2055	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2056	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2057	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2058	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2059
				2060	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2061	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2062	return MCDisassembler::Fail;
				2063	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2064	return MCDisassembler::Fail;
				2065
				2066	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2067	Inst.addOperand(MCOperand::CreateImm(imm));
				2068
				2069	return S;
				2070	}
				2071
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2072	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2073	uint64_t Address, const void *Decoder) {
				2074	DecodeStatus S = MCDisassembler::Success;
				2075
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2076	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2077	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2078	unsigned imm = 0;
				2079
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2080	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2081	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2082
				2083	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2084	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2085	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2086
				2087	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2088	return MCDisassembler::Fail;
				2089
				2090	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2091	Inst.addOperand(MCOperand::CreateImm(imm));
				2092
				2093	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2094	return MCDisassembler::Fail;
				2095
				2096	return S;
				2097	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2098
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2099	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2100	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2101	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2102
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2103	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2104	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2105	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2106	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2107	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2108
				2109	if (pred == 0xF)
				2110	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2111
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2112	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2113	return MCDisassembler::Fail;
				2114	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2115	return MCDisassembler::Fail;
				2116	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2117	return MCDisassembler::Fail;
				2118	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2119	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2120
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2121	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2122	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2123
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2124	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2125	}
				2126
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2127	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				2128	uint64_t Address, const void *Decoder) {
				2129	DecodeStatus S = MCDisassembler::Success;
				2130
				2131	unsigned Pred = fieldFromInstruction(Insn, 28, 4);
				2132	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2133	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2134
				2135	if (Pred == 0xF)
				2136	return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
				2137
				2138	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2139	return MCDisassembler::Fail;
				2140	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2141	return MCDisassembler::Fail;
				2142	if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
				2143	return MCDisassembler::Fail;
				2144
				2145	return S;
				2146	}
				2147
				2148	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				2149	uint64_t Address, const void *Decoder) {
				2150	DecodeStatus S = MCDisassembler::Success;
				2151
				2152	unsigned Imm = fieldFromInstruction(Insn, 9, 1);
				2153
				2154	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	2155	const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
				2156
				2157	if (!FeatureBits[ARM::HasV8_1aOps] \|\|
				2158	!FeatureBits[ARM::HasV8Ops])
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2159	return MCDisassembler::Fail;
				2160
				2161	// Decoder can be called from DecodeTST, which does not check the full
				2162	// encoding is valid.
				2163	if (fieldFromInstruction(Insn, 20,12) != 0xf11 \|\|
				2164	fieldFromInstruction(Insn, 4,4) != 0)
				2165	return MCDisassembler::Fail;
				2166	if (fieldFromInstruction(Insn, 10,10) != 0 \|\|
				2167	fieldFromInstruction(Insn, 0,4) != 0)
				2168	S = MCDisassembler::SoftFail;
				2169
				2170	Inst.setOpcode(ARM::SETPAN);
				2171	Inst.addOperand(MCOperand::CreateImm(Imm));
				2172
				2173	return S;
				2174	}
				2175
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2176	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2177	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2178	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2179
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2180	unsigned add = fieldFromInstruction(Val, 12, 1);
				2181	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2182	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2183
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2184	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2185	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2186
				2187	if (!add) imm *= -1;
				2188	if (imm == 0 && !add) imm = INT32_MIN;
				2189	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2190	if (Rn == 15)
				2191	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2192
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2193	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2194	}
				2195
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2196	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2197	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2198	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2199
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2200	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2201	unsigned U = fieldFromInstruction(Val, 8, 1);
				2202	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2203
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2204	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2205	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2206
				2207	if (U)
				2208	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2209	else
				2210	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2211
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2212	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2213	}
				2214
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2215	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2216	uint64_t Address, const void *Decoder) {
				2217	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2218	}
				2219
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2220	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2221	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2222	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2223	DecodeStatus Status = MCDisassembler::Success;
				2224
				2225	// Note the J1 and J2 values are from the encoded instruction. So here
				2226	// change them to I1 and I2 values via as documented:
				2227	// I1 = NOT(J1 EOR S);
				2228	// I2 = NOT(J2 EOR S);
				2229	// and build the imm32 with one trailing zero as documented:
				2230	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2231	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2232	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2233	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2234	unsigned I1 = !(J1 ^ S);
				2235	unsigned I2 = !(J2 ^ S);
				2236	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2237	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2238	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2239	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2240	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2241	true, 4, Inst, Decoder))
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2242	Inst.addOperand(MCOperand::CreateImm(imm32));
				2243
				2244	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2245	}
				2246
				2247	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2248	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2249	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2250	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2251
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2252	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2253	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2254
				2255	if (pred == 0xF) {
				2256	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2257	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2258	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2259	true, 4, Inst, Decoder))
Benjamin Kramer	406dc17	2011-08-09 22:02:50 +0000	[diff] [blame]	2260	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2261	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2262	}
				2263
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2264	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2265	true, 4, Inst, Decoder))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2266	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2267	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2268	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2269
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2270	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2271	}
				2272
				2273
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2274	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2275	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2276	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2277
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2278	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2279	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2280
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2281	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2282	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2283	if (!align)
				2284	Inst.addOperand(MCOperand::CreateImm(0));
				2285	else
				2286	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2287
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2288	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2289	}
				2290
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2291	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2292	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2293	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2294
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2295	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2296	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2297	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2298	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2299	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2300	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2301
				2302	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2303	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2304	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2305	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2306	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2307	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2308	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2309	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2310	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2311	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2312	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2313	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2314	return MCDisassembler::Fail;
				2315	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2316	case ARM::VLD2b16:
				2317	case ARM::VLD2b32:
				2318	case ARM::VLD2b8:
				2319	case ARM::VLD2b16wb_fixed:
				2320	case ARM::VLD2b16wb_register:
				2321	case ARM::VLD2b32wb_fixed:
				2322	case ARM::VLD2b32wb_register:
				2323	case ARM::VLD2b8wb_fixed:
				2324	case ARM::VLD2b8wb_register:
				2325	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2326	return MCDisassembler::Fail;
				2327	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2328	default:
				2329	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2330	return MCDisassembler::Fail;
				2331	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2332
				2333	// Second output register
				2334	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2335	case ARM::VLD3d8:
				2336	case ARM::VLD3d16:
				2337	case ARM::VLD3d32:
				2338	case ARM::VLD3d8_UPD:
				2339	case ARM::VLD3d16_UPD:
				2340	case ARM::VLD3d32_UPD:
				2341	case ARM::VLD4d8:
				2342	case ARM::VLD4d16:
				2343	case ARM::VLD4d32:
				2344	case ARM::VLD4d8_UPD:
				2345	case ARM::VLD4d16_UPD:
				2346	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2347	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2348	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2349	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2350	case ARM::VLD3q8:
				2351	case ARM::VLD3q16:
				2352	case ARM::VLD3q32:
				2353	case ARM::VLD3q8_UPD:
				2354	case ARM::VLD3q16_UPD:
				2355	case ARM::VLD3q32_UPD:
				2356	case ARM::VLD4q8:
				2357	case ARM::VLD4q16:
				2358	case ARM::VLD4q32:
				2359	case ARM::VLD4q8_UPD:
				2360	case ARM::VLD4q16_UPD:
				2361	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2362	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2363	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2364	default:
				2365	break;
				2366	}
				2367
				2368	// Third output register
				2369	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2370	case ARM::VLD3d8:
				2371	case ARM::VLD3d16:
				2372	case ARM::VLD3d32:
				2373	case ARM::VLD3d8_UPD:
				2374	case ARM::VLD3d16_UPD:
				2375	case ARM::VLD3d32_UPD:
				2376	case ARM::VLD4d8:
				2377	case ARM::VLD4d16:
				2378	case ARM::VLD4d32:
				2379	case ARM::VLD4d8_UPD:
				2380	case ARM::VLD4d16_UPD:
				2381	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2382	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2383	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2384	break;
				2385	case ARM::VLD3q8:
				2386	case ARM::VLD3q16:
				2387	case ARM::VLD3q32:
				2388	case ARM::VLD3q8_UPD:
				2389	case ARM::VLD3q16_UPD:
				2390	case ARM::VLD3q32_UPD:
				2391	case ARM::VLD4q8:
				2392	case ARM::VLD4q16:
				2393	case ARM::VLD4q32:
				2394	case ARM::VLD4q8_UPD:
				2395	case ARM::VLD4q16_UPD:
				2396	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2397	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2398	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2399	break;
				2400	default:
				2401	break;
				2402	}
				2403
				2404	// Fourth output register
				2405	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2406	case ARM::VLD4d8:
				2407	case ARM::VLD4d16:
				2408	case ARM::VLD4d32:
				2409	case ARM::VLD4d8_UPD:
				2410	case ARM::VLD4d16_UPD:
				2411	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2412	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2413	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2414	break;
				2415	case ARM::VLD4q8:
				2416	case ARM::VLD4q16:
				2417	case ARM::VLD4q32:
				2418	case ARM::VLD4q8_UPD:
				2419	case ARM::VLD4q16_UPD:
				2420	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2421	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2422	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2423	break;
				2424	default:
				2425	break;
				2426	}
				2427
				2428	// Writeback operand
				2429	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2430	case ARM::VLD1d8wb_fixed:
				2431	case ARM::VLD1d16wb_fixed:
				2432	case ARM::VLD1d32wb_fixed:
				2433	case ARM::VLD1d64wb_fixed:
				2434	case ARM::VLD1d8wb_register:
				2435	case ARM::VLD1d16wb_register:
				2436	case ARM::VLD1d32wb_register:
				2437	case ARM::VLD1d64wb_register:
				2438	case ARM::VLD1q8wb_fixed:
				2439	case ARM::VLD1q16wb_fixed:
				2440	case ARM::VLD1q32wb_fixed:
				2441	case ARM::VLD1q64wb_fixed:
				2442	case ARM::VLD1q8wb_register:
				2443	case ARM::VLD1q16wb_register:
				2444	case ARM::VLD1q32wb_register:
				2445	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2446	case ARM::VLD1d8Twb_fixed:
				2447	case ARM::VLD1d8Twb_register:
				2448	case ARM::VLD1d16Twb_fixed:
				2449	case ARM::VLD1d16Twb_register:
				2450	case ARM::VLD1d32Twb_fixed:
				2451	case ARM::VLD1d32Twb_register:
				2452	case ARM::VLD1d64Twb_fixed:
				2453	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2454	case ARM::VLD1d8Qwb_fixed:
				2455	case ARM::VLD1d8Qwb_register:
				2456	case ARM::VLD1d16Qwb_fixed:
				2457	case ARM::VLD1d16Qwb_register:
				2458	case ARM::VLD1d32Qwb_fixed:
				2459	case ARM::VLD1d32Qwb_register:
				2460	case ARM::VLD1d64Qwb_fixed:
				2461	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2462	case ARM::VLD2d8wb_fixed:
				2463	case ARM::VLD2d16wb_fixed:
				2464	case ARM::VLD2d32wb_fixed:
				2465	case ARM::VLD2q8wb_fixed:
				2466	case ARM::VLD2q16wb_fixed:
				2467	case ARM::VLD2q32wb_fixed:
				2468	case ARM::VLD2d8wb_register:
				2469	case ARM::VLD2d16wb_register:
				2470	case ARM::VLD2d32wb_register:
				2471	case ARM::VLD2q8wb_register:
				2472	case ARM::VLD2q16wb_register:
				2473	case ARM::VLD2q32wb_register:
				2474	case ARM::VLD2b8wb_fixed:
				2475	case ARM::VLD2b16wb_fixed:
				2476	case ARM::VLD2b32wb_fixed:
				2477	case ARM::VLD2b8wb_register:
				2478	case ARM::VLD2b16wb_register:
				2479	case ARM::VLD2b32wb_register:
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2480	Inst.addOperand(MCOperand::CreateImm(0));
				2481	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2482	case ARM::VLD3d8_UPD:
				2483	case ARM::VLD3d16_UPD:
				2484	case ARM::VLD3d32_UPD:
				2485	case ARM::VLD3q8_UPD:
				2486	case ARM::VLD3q16_UPD:
				2487	case ARM::VLD3q32_UPD:
				2488	case ARM::VLD4d8_UPD:
				2489	case ARM::VLD4d16_UPD:
				2490	case ARM::VLD4d32_UPD:
				2491	case ARM::VLD4q8_UPD:
				2492	case ARM::VLD4q16_UPD:
				2493	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2494	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2495	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2496	break;
				2497	default:
				2498	break;
				2499	}
				2500
				2501	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2502	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2503	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2504
				2505	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2506	switch (Inst.getOpcode()) {
				2507	default:
				2508	// The below have been updated to have explicit am6offset split
				2509	// between fixed and register offset. For those instructions not
				2510	// yet updated, we need to add an additional reg0 operand for the
				2511	// fixed variant.
				2512	//
				2513	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2514	if (Rm == 0xd) {
				2515	Inst.addOperand(MCOperand::CreateReg(0));
				2516	break;
				2517	}
				2518	// Fall through to handle the register offset variant.
				2519	case ARM::VLD1d8wb_fixed:
				2520	case ARM::VLD1d16wb_fixed:
				2521	case ARM::VLD1d32wb_fixed:
				2522	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2523	case ARM::VLD1d8Twb_fixed:
				2524	case ARM::VLD1d16Twb_fixed:
				2525	case ARM::VLD1d32Twb_fixed:
				2526	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2527	case ARM::VLD1d8Qwb_fixed:
				2528	case ARM::VLD1d16Qwb_fixed:
				2529	case ARM::VLD1d32Qwb_fixed:
				2530	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2531	case ARM::VLD1d8wb_register:
				2532	case ARM::VLD1d16wb_register:
				2533	case ARM::VLD1d32wb_register:
				2534	case ARM::VLD1d64wb_register:
				2535	case ARM::VLD1q8wb_fixed:
				2536	case ARM::VLD1q16wb_fixed:
				2537	case ARM::VLD1q32wb_fixed:
				2538	case ARM::VLD1q64wb_fixed:
				2539	case ARM::VLD1q8wb_register:
				2540	case ARM::VLD1q16wb_register:
				2541	case ARM::VLD1q32wb_register:
				2542	case ARM::VLD1q64wb_register:
				2543	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2544	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2545	// increment and we need to add the register operand to the instruction.
				2546	if (Rm != 0xD && Rm != 0xF &&
				2547	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2548	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2549	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2550	case ARM::VLD2d8wb_fixed:
				2551	case ARM::VLD2d16wb_fixed:
				2552	case ARM::VLD2d32wb_fixed:
				2553	case ARM::VLD2b8wb_fixed:
				2554	case ARM::VLD2b16wb_fixed:
				2555	case ARM::VLD2b32wb_fixed:
				2556	case ARM::VLD2q8wb_fixed:
				2557	case ARM::VLD2q16wb_fixed:
				2558	case ARM::VLD2q32wb_fixed:
				2559	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2560	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2561
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2562	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2563	}
				2564
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2565	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2566	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2567	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2568	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2569	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2570	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2571	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2572
				2573	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2574	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2575	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2576	}
				2577
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2578	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2579	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2580	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2581	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2582
				2583	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2584	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2585	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2586	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2587
				2588	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2589	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2590	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2591	}
				2592
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2593	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2594	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2595	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2596	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2597
				2598	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2599	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2600
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2601	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2602	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2603	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2604	}
				2605
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2606	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2607	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2608	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2609	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2610
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2611	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2612	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2613	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2614	}
				2615
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2616	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2617	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2618	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2619
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2620	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2621	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2622	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2623	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2624	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2625	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2626
				2627	// Writeback Operand
				2628	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2629	case ARM::VST1d8wb_fixed:
				2630	case ARM::VST1d16wb_fixed:
				2631	case ARM::VST1d32wb_fixed:
				2632	case ARM::VST1d64wb_fixed:
				2633	case ARM::VST1d8wb_register:
				2634	case ARM::VST1d16wb_register:
				2635	case ARM::VST1d32wb_register:
				2636	case ARM::VST1d64wb_register:
				2637	case ARM::VST1q8wb_fixed:
				2638	case ARM::VST1q16wb_fixed:
				2639	case ARM::VST1q32wb_fixed:
				2640	case ARM::VST1q64wb_fixed:
				2641	case ARM::VST1q8wb_register:
				2642	case ARM::VST1q16wb_register:
				2643	case ARM::VST1q32wb_register:
				2644	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2645	case ARM::VST1d8Twb_fixed:
				2646	case ARM::VST1d16Twb_fixed:
				2647	case ARM::VST1d32Twb_fixed:
				2648	case ARM::VST1d64Twb_fixed:
				2649	case ARM::VST1d8Twb_register:
				2650	case ARM::VST1d16Twb_register:
				2651	case ARM::VST1d32Twb_register:
				2652	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2653	case ARM::VST1d8Qwb_fixed:
				2654	case ARM::VST1d16Qwb_fixed:
				2655	case ARM::VST1d32Qwb_fixed:
				2656	case ARM::VST1d64Qwb_fixed:
				2657	case ARM::VST1d8Qwb_register:
				2658	case ARM::VST1d16Qwb_register:
				2659	case ARM::VST1d32Qwb_register:
				2660	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2661	case ARM::VST2d8wb_fixed:
				2662	case ARM::VST2d16wb_fixed:
				2663	case ARM::VST2d32wb_fixed:
				2664	case ARM::VST2d8wb_register:
				2665	case ARM::VST2d16wb_register:
				2666	case ARM::VST2d32wb_register:
				2667	case ARM::VST2q8wb_fixed:
				2668	case ARM::VST2q16wb_fixed:
				2669	case ARM::VST2q32wb_fixed:
				2670	case ARM::VST2q8wb_register:
				2671	case ARM::VST2q16wb_register:
				2672	case ARM::VST2q32wb_register:
				2673	case ARM::VST2b8wb_fixed:
				2674	case ARM::VST2b16wb_fixed:
				2675	case ARM::VST2b32wb_fixed:
				2676	case ARM::VST2b8wb_register:
				2677	case ARM::VST2b16wb_register:
				2678	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2679	if (Rm == 0xF)
				2680	return MCDisassembler::Fail;
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2681	Inst.addOperand(MCOperand::CreateImm(0));
				2682	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2683	case ARM::VST3d8_UPD:
				2684	case ARM::VST3d16_UPD:
				2685	case ARM::VST3d32_UPD:
				2686	case ARM::VST3q8_UPD:
				2687	case ARM::VST3q16_UPD:
				2688	case ARM::VST3q32_UPD:
				2689	case ARM::VST4d8_UPD:
				2690	case ARM::VST4d16_UPD:
				2691	case ARM::VST4d32_UPD:
				2692	case ARM::VST4q8_UPD:
				2693	case ARM::VST4q16_UPD:
				2694	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2695	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2696	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2697	break;
				2698	default:
				2699	break;
				2700	}
				2701
				2702	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2703	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2704	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2705
				2706	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2707	switch (Inst.getOpcode()) {
				2708	default:
				2709	if (Rm == 0xD)
				2710	Inst.addOperand(MCOperand::CreateReg(0));
				2711	else if (Rm != 0xF) {
				2712	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2713	return MCDisassembler::Fail;
				2714	}
				2715	break;
				2716	case ARM::VST1d8wb_fixed:
				2717	case ARM::VST1d16wb_fixed:
				2718	case ARM::VST1d32wb_fixed:
				2719	case ARM::VST1d64wb_fixed:
				2720	case ARM::VST1q8wb_fixed:
				2721	case ARM::VST1q16wb_fixed:
				2722	case ARM::VST1q32wb_fixed:
				2723	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2724	case ARM::VST1d8Twb_fixed:
				2725	case ARM::VST1d16Twb_fixed:
				2726	case ARM::VST1d32Twb_fixed:
				2727	case ARM::VST1d64Twb_fixed:
				2728	case ARM::VST1d8Qwb_fixed:
				2729	case ARM::VST1d16Qwb_fixed:
				2730	case ARM::VST1d32Qwb_fixed:
				2731	case ARM::VST1d64Qwb_fixed:
				2732	case ARM::VST2d8wb_fixed:
				2733	case ARM::VST2d16wb_fixed:
				2734	case ARM::VST2d32wb_fixed:
				2735	case ARM::VST2q8wb_fixed:
				2736	case ARM::VST2q16wb_fixed:
				2737	case ARM::VST2q32wb_fixed:
				2738	case ARM::VST2b8wb_fixed:
				2739	case ARM::VST2b16wb_fixed:
				2740	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2741	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2742	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2743
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2744
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2745	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2746	switch (Inst.getOpcode()) {
				2747	case ARM::VST1q16:
				2748	case ARM::VST1q32:
				2749	case ARM::VST1q64:
				2750	case ARM::VST1q8:
				2751	case ARM::VST1q16wb_fixed:
				2752	case ARM::VST1q16wb_register:
				2753	case ARM::VST1q32wb_fixed:
				2754	case ARM::VST1q32wb_register:
				2755	case ARM::VST1q64wb_fixed:
				2756	case ARM::VST1q64wb_register:
				2757	case ARM::VST1q8wb_fixed:
				2758	case ARM::VST1q8wb_register:
				2759	case ARM::VST2d16:
				2760	case ARM::VST2d32:
				2761	case ARM::VST2d8:
				2762	case ARM::VST2d16wb_fixed:
				2763	case ARM::VST2d16wb_register:
				2764	case ARM::VST2d32wb_fixed:
				2765	case ARM::VST2d32wb_register:
				2766	case ARM::VST2d8wb_fixed:
				2767	case ARM::VST2d8wb_register:
				2768	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2769	return MCDisassembler::Fail;
				2770	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2771	case ARM::VST2b16:
				2772	case ARM::VST2b32:
				2773	case ARM::VST2b8:
				2774	case ARM::VST2b16wb_fixed:
				2775	case ARM::VST2b16wb_register:
				2776	case ARM::VST2b32wb_fixed:
				2777	case ARM::VST2b32wb_register:
				2778	case ARM::VST2b8wb_fixed:
				2779	case ARM::VST2b8wb_register:
				2780	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2781	return MCDisassembler::Fail;
				2782	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2783	default:
				2784	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2785	return MCDisassembler::Fail;
				2786	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2787
				2788	// Second input register
				2789	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2790	case ARM::VST3d8:
				2791	case ARM::VST3d16:
				2792	case ARM::VST3d32:
				2793	case ARM::VST3d8_UPD:
				2794	case ARM::VST3d16_UPD:
				2795	case ARM::VST3d32_UPD:
				2796	case ARM::VST4d8:
				2797	case ARM::VST4d16:
				2798	case ARM::VST4d32:
				2799	case ARM::VST4d8_UPD:
				2800	case ARM::VST4d16_UPD:
				2801	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2802	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2803	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2804	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2805	case ARM::VST3q8:
				2806	case ARM::VST3q16:
				2807	case ARM::VST3q32:
				2808	case ARM::VST3q8_UPD:
				2809	case ARM::VST3q16_UPD:
				2810	case ARM::VST3q32_UPD:
				2811	case ARM::VST4q8:
				2812	case ARM::VST4q16:
				2813	case ARM::VST4q32:
				2814	case ARM::VST4q8_UPD:
				2815	case ARM::VST4q16_UPD:
				2816	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2817	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2818	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2819	break;
				2820	default:
				2821	break;
				2822	}
				2823
				2824	// Third input register
				2825	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2826	case ARM::VST3d8:
				2827	case ARM::VST3d16:
				2828	case ARM::VST3d32:
				2829	case ARM::VST3d8_UPD:
				2830	case ARM::VST3d16_UPD:
				2831	case ARM::VST3d32_UPD:
				2832	case ARM::VST4d8:
				2833	case ARM::VST4d16:
				2834	case ARM::VST4d32:
				2835	case ARM::VST4d8_UPD:
				2836	case ARM::VST4d16_UPD:
				2837	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2838	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2839	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2840	break;
				2841	case ARM::VST3q8:
				2842	case ARM::VST3q16:
				2843	case ARM::VST3q32:
				2844	case ARM::VST3q8_UPD:
				2845	case ARM::VST3q16_UPD:
				2846	case ARM::VST3q32_UPD:
				2847	case ARM::VST4q8:
				2848	case ARM::VST4q16:
				2849	case ARM::VST4q32:
				2850	case ARM::VST4q8_UPD:
				2851	case ARM::VST4q16_UPD:
				2852	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2853	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2854	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2855	break;
				2856	default:
				2857	break;
				2858	}
				2859
				2860	// Fourth input register
				2861	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2862	case ARM::VST4d8:
				2863	case ARM::VST4d16:
				2864	case ARM::VST4d32:
				2865	case ARM::VST4d8_UPD:
				2866	case ARM::VST4d16_UPD:
				2867	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2868	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2869	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2870	break;
				2871	case ARM::VST4q8:
				2872	case ARM::VST4q16:
				2873	case ARM::VST4q32:
				2874	case ARM::VST4q8_UPD:
				2875	case ARM::VST4q16_UPD:
				2876	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2877	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2878	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2879	break;
				2880	default:
				2881	break;
				2882	}
				2883
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2884	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2885	}
				2886
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2887	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2888	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2889	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2890
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2891	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2892	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2893	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2894	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2895	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2896	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2897
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2898	if (size == 0 && align == 1)
				2899	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2900	align *= (1 << size);
				2901
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2902	switch (Inst.getOpcode()) {
				2903	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2904	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2905	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2906	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2907	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2908	return MCDisassembler::Fail;
				2909	break;
				2910	default:
				2911	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2912	return MCDisassembler::Fail;
				2913	break;
				2914	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2915	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2916	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2917	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2918	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2919
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2920	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2921	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2922	Inst.addOperand(MCOperand::CreateImm(align));
				2923
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2924	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2925	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2926	// increment and we need to add the register operand to the instruction.
				2927	if (Rm != 0xD && Rm != 0xF &&
				2928	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2929	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2930
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2931	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2932	}
				2933
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2934	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2935	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2936	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2937
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2938	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2939	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2940	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2941	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2942	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2943	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2944	align = 2size;
				2945
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2946	switch (Inst.getOpcode()) {
				2947	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2948	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2949	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2950	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2951	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2952	return MCDisassembler::Fail;
				2953	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2954	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2955	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2956	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2957	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2958	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2959	return MCDisassembler::Fail;
				2960	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2961	default:
				2962	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2963	return MCDisassembler::Fail;
				2964	break;
				2965	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2966
				2967	if (Rm != 0xF)
				2968	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2969
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2970	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2971	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2972	Inst.addOperand(MCOperand::CreateImm(align));
				2973
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2974	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2975	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2976	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2977	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2978
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2979	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2980	}
				2981
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2982	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2983	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2984	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2985
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2986	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2987	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2988	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2989	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2990	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2991
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2992	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2993	return MCDisassembler::Fail;
				2994	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2995	return MCDisassembler::Fail;
				2996	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2997	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2998	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2999	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3000	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3001	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3002
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3003	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3004	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3005	Inst.addOperand(MCOperand::CreateImm(0));
				3006
				3007	if (Rm == 0xD)
				3008	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3009	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3010	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3011	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3012	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3013
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3014	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3015	}
				3016
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3017	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3018	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3019	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3020
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3021	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3022	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3023	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3024	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3025	unsigned size = fieldFromInstruction(Insn, 6, 2);
				3026	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				3027	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3028
				3029	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	3030	if (align == 0)
				3031	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3032	align = 16;
				3033	} else {
				3034	if (size == 2) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3035	align *= 8;
				3036	} else {
				3037	size = 1 << size;
				3038	align = 4size;
				3039	}
				3040	}
				3041
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3042	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3043	return MCDisassembler::Fail;
				3044	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3045	return MCDisassembler::Fail;
				3046	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3047	return MCDisassembler::Fail;
				3048	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				3049	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3050	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3051	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3052	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3053	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3054
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3055	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3056	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3057	Inst.addOperand(MCOperand::CreateImm(align));
				3058
				3059	if (Rm == 0xD)
				3060	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3061	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3062	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3063	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3064	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3065
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3066	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3067	}
				3068
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3069	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3070	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3071	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3072	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3073
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3074	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3075	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3076	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3077	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3078	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3079	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3080	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3081	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3082
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3083	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3084	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3085	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3086	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3087	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3088	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3089	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3090
				3091	Inst.addOperand(MCOperand::CreateImm(imm));
				3092
				3093	switch (Inst.getOpcode()) {
				3094	case ARM::VORRiv4i16:
				3095	case ARM::VORRiv2i32:
				3096	case ARM::VBICiv4i16:
				3097	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3098	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3099	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3100	break;
				3101	case ARM::VORRiv8i16:
				3102	case ARM::VORRiv4i32:
				3103	case ARM::VBICiv8i16:
				3104	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3105	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3106	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3107	break;
				3108	default:
				3109	break;
				3110	}
				3111
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3112	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3113	}
				3114
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3115	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3116	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3117	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3118
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3119	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3120	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3121	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3122	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3123	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3124
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3125	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3126	return MCDisassembler::Fail;
				3127	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3128	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3129	Inst.addOperand(MCOperand::CreateImm(8 << size));
				3130
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3131	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3132	}
				3133
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3134	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3135	uint64_t Address, const void *Decoder) {
				3136	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3137	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3138	}
				3139
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3140	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3141	uint64_t Address, const void *Decoder) {
				3142	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3143	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3144	}
				3145
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3146	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3147	uint64_t Address, const void *Decoder) {
				3148	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3149	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3150	}
				3151
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3152	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3153	uint64_t Address, const void *Decoder) {
				3154	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3155	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3156	}
				3157
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3158	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3159	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3160	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3161
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3162	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3163	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3164	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3165	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3166	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3167	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3168	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3169
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3170	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3171	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3172	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3173	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3174	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3175	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3176
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3177	switch (Inst.getOpcode()) {
				3178	case ARM::VTBL2:
				3179	case ARM::VTBX2:
				3180	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3181	return MCDisassembler::Fail;
				3182	break;
				3183	default:
				3184	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3185	return MCDisassembler::Fail;
				3186	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3187
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3188	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3189	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3190
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3191	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3192	}
				3193
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3194	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3195	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3196	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3197
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3198	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3199	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3200
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3201	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3202	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3203
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3204	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3205	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3206	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3207	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3208	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3209	case ARM::tADDrSPi:
				3210	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3211	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3212	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3213
				3214	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3215	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3216	}
				3217
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3218	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3219	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3220	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3221	true, 2, Inst, Decoder))
				3222	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3223	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3224	}
				3225
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3226	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3227	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3228	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3229	true, 4, Inst, Decoder))
				3230	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3231	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3232	}
				3233
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3234	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3235	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3236	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3237	true, 2, Inst, Decoder))
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3238	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3239	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3240	}
				3241
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3242	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3243	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3244	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3245
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3246	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3247	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3248
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3249	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3250	return MCDisassembler::Fail;
				3251	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3252	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3253
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3254	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3255	}
				3256
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3257	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3258	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3259	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3260
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3261	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3262	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3263
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3264	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3265	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3266	Inst.addOperand(MCOperand::CreateImm(imm));
				3267
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3268	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3269	}
				3270
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3271	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3272	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3273	unsigned imm = Val << 2;
				3274
				3275	Inst.addOperand(MCOperand::CreateImm(imm));
				3276	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3277
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3278	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3279	}
				3280
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3281	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3282	uint64_t Address, const void *Decoder) {
				3283	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b498132	2011-08-22 17:56:58 +0000	[diff] [blame]	3284	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3285
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3286	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3287	}
				3288
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3289	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3290	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3291	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3292
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3293	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3294	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3295	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3296
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3297	// Thumb stores cannot use PC as dest register.
				3298	switch (Inst.getOpcode()) {
				3299	case ARM::t2STRHs:
				3300	case ARM::t2STRBs:
				3301	case ARM::t2STRs:
				3302	if (Rn == 15)
				3303	return MCDisassembler::Fail;
				3304	default:
				3305	break;
				3306	}
				3307
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3308	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3309	return MCDisassembler::Fail;
				3310	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3311	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3312	Inst.addOperand(MCOperand::CreateImm(imm));
				3313
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3314	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3315	}
				3316
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3317	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3318	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3319	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3320
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3321	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3322	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3323
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	3324	const FeatureBitset &featureBits =
				3325	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3326
				3327	bool hasMP = featureBits[ARM::FeatureMP];
				3328	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3329
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3330	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3331	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3332	case ARM::t2LDRBs:
				3333	Inst.setOpcode(ARM::t2LDRBpci);
				3334	break;
				3335	case ARM::t2LDRHs:
				3336	Inst.setOpcode(ARM::t2LDRHpci);
				3337	break;
				3338	case ARM::t2LDRSHs:
				3339	Inst.setOpcode(ARM::t2LDRSHpci);
				3340	break;
				3341	case ARM::t2LDRSBs:
				3342	Inst.setOpcode(ARM::t2LDRSBpci);
				3343	break;
				3344	case ARM::t2LDRs:
				3345	Inst.setOpcode(ARM::t2LDRpci);
				3346	break;
				3347	case ARM::t2PLDs:
				3348	Inst.setOpcode(ARM::t2PLDpci);
				3349	break;
				3350	case ARM::t2PLIs:
				3351	Inst.setOpcode(ARM::t2PLIpci);
				3352	break;
				3353	default:
				3354	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3355	}
				3356
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3357	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3358	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3359
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3360	if (Rt == 15) {
				3361	switch (Inst.getOpcode()) {
				3362	case ARM::t2LDRSHs:
				3363	return MCDisassembler::Fail;
				3364	case ARM::t2LDRHs:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3365	Inst.setOpcode(ARM::t2PLDWs);
				3366	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3367	case ARM::t2LDRSBs:
				3368	Inst.setOpcode(ARM::t2PLIs);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3369	default:
				3370	break;
				3371	}
				3372	}
				3373
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3374	switch (Inst.getOpcode()) {
				3375	case ARM::t2PLDs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3376	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3377	case ARM::t2PLIs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3378	if (!hasV7Ops)
				3379	return MCDisassembler::Fail;
				3380	break;
				3381	case ARM::t2PLDWs:
				3382	if (!hasV7Ops \|\| !hasMP)
				3383	return MCDisassembler::Fail;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3384	break;
				3385	default:
				3386	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3387	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3388	}
				3389
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3390	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3391	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3392	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3393	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3394	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3395
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3396	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3397	}
				3398
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3399	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3400	uint64_t Address, const void* Decoder) {
				3401	DecodeStatus S = MCDisassembler::Success;
				3402
				3403	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3404	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3405	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3406	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3407	imm \|= (U << 8);
				3408	imm \|= (Rn << 9);
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3409	unsigned add = fieldFromInstruction(Insn, 9, 1);
				3410
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	3411	const FeatureBitset &featureBits =
				3412	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3413
				3414	bool hasMP = featureBits[ARM::FeatureMP];
				3415	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3416
				3417	if (Rn == 15) {
				3418	switch (Inst.getOpcode()) {
				3419	case ARM::t2LDRi8:
				3420	Inst.setOpcode(ARM::t2LDRpci);
				3421	break;
				3422	case ARM::t2LDRBi8:
				3423	Inst.setOpcode(ARM::t2LDRBpci);
				3424	break;
				3425	case ARM::t2LDRSBi8:
				3426	Inst.setOpcode(ARM::t2LDRSBpci);
				3427	break;
				3428	case ARM::t2LDRHi8:
				3429	Inst.setOpcode(ARM::t2LDRHpci);
				3430	break;
				3431	case ARM::t2LDRSHi8:
				3432	Inst.setOpcode(ARM::t2LDRSHpci);
				3433	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3434	case ARM::t2PLDi8:
				3435	Inst.setOpcode(ARM::t2PLDpci);
				3436	break;
				3437	case ARM::t2PLIi8:
				3438	Inst.setOpcode(ARM::t2PLIpci);
				3439	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3440	default:
				3441	return MCDisassembler::Fail;
				3442	}
				3443	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3444	}
				3445
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3446	if (Rt == 15) {
				3447	switch (Inst.getOpcode()) {
				3448	case ARM::t2LDRSHi8:
				3449	return MCDisassembler::Fail;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3450	case ARM::t2LDRHi8:
				3451	if (!add)
				3452	Inst.setOpcode(ARM::t2PLDWi8);
				3453	break;
				3454	case ARM::t2LDRSBi8:
				3455	Inst.setOpcode(ARM::t2PLIi8);
				3456	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3457	default:
				3458	break;
				3459	}
				3460	}
				3461
				3462	switch (Inst.getOpcode()) {
				3463	case ARM::t2PLDi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3464	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3465	case ARM::t2PLIi8:
				3466	if (!hasV7Ops)
				3467	return MCDisassembler::Fail;
				3468	break;
				3469	case ARM::t2PLDWi8:
				3470	if (!hasV7Ops \|\| !hasMP)
				3471	return MCDisassembler::Fail;
				3472	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3473	default:
				3474	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3475	return MCDisassembler::Fail;
				3476	}
				3477
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3478	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3479	return MCDisassembler::Fail;
				3480	return S;
				3481	}
				3482
				3483	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3484	uint64_t Address, const void* Decoder) {
				3485	DecodeStatus S = MCDisassembler::Success;
				3486
				3487	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3488	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3489	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3490	imm \|= (Rn << 13);
				3491
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	3492	const FeatureBitset &featureBits =
				3493	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3494
				3495	bool hasMP = featureBits[ARM::FeatureMP];
				3496	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3497
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3498	if (Rn == 15) {
				3499	switch (Inst.getOpcode()) {
				3500	case ARM::t2LDRi12:
				3501	Inst.setOpcode(ARM::t2LDRpci);
				3502	break;
				3503	case ARM::t2LDRHi12:
				3504	Inst.setOpcode(ARM::t2LDRHpci);
				3505	break;
				3506	case ARM::t2LDRSHi12:
				3507	Inst.setOpcode(ARM::t2LDRSHpci);
				3508	break;
				3509	case ARM::t2LDRBi12:
				3510	Inst.setOpcode(ARM::t2LDRBpci);
				3511	break;
				3512	case ARM::t2LDRSBi12:
				3513	Inst.setOpcode(ARM::t2LDRSBpci);
				3514	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3515	case ARM::t2PLDi12:
				3516	Inst.setOpcode(ARM::t2PLDpci);
				3517	break;
				3518	case ARM::t2PLIi12:
				3519	Inst.setOpcode(ARM::t2PLIpci);
				3520	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3521	default:
				3522	return MCDisassembler::Fail;
				3523	}
				3524	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3525	}
				3526
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3527	if (Rt == 15) {
				3528	switch (Inst.getOpcode()) {
				3529	case ARM::t2LDRSHi12:
				3530	return MCDisassembler::Fail;
				3531	case ARM::t2LDRHi12:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3532	Inst.setOpcode(ARM::t2PLDWi12);
				3533	break;
				3534	case ARM::t2LDRSBi12:
				3535	Inst.setOpcode(ARM::t2PLIi12);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3536	break;
				3537	default:
				3538	break;
				3539	}
				3540	}
				3541
				3542	switch (Inst.getOpcode()) {
				3543	case ARM::t2PLDi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3544	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3545	case ARM::t2PLIi12:
				3546	if (!hasV7Ops)
				3547	return MCDisassembler::Fail;
				3548	break;
				3549	case ARM::t2PLDWi12:
				3550	if (!hasV7Ops \|\| !hasMP)
				3551	return MCDisassembler::Fail;
				3552	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3553	default:
				3554	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3555	return MCDisassembler::Fail;
				3556	}
				3557
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3558	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3559	return MCDisassembler::Fail;
				3560	return S;
				3561	}
				3562
				3563	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3564	uint64_t Address, const void* Decoder) {
				3565	DecodeStatus S = MCDisassembler::Success;
				3566
				3567	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3568	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3569	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3570	imm \|= (Rn << 9);
				3571
				3572	if (Rn == 15) {
				3573	switch (Inst.getOpcode()) {
				3574	case ARM::t2LDRT:
				3575	Inst.setOpcode(ARM::t2LDRpci);
				3576	break;
				3577	case ARM::t2LDRBT:
				3578	Inst.setOpcode(ARM::t2LDRBpci);
				3579	break;
				3580	case ARM::t2LDRHT:
				3581	Inst.setOpcode(ARM::t2LDRHpci);
				3582	break;
				3583	case ARM::t2LDRSBT:
				3584	Inst.setOpcode(ARM::t2LDRSBpci);
				3585	break;
				3586	case ARM::t2LDRSHT:
				3587	Inst.setOpcode(ARM::t2LDRSHpci);
				3588	break;
				3589	default:
				3590	return MCDisassembler::Fail;
				3591	}
				3592	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3593	}
				3594
				3595	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3596	return MCDisassembler::Fail;
				3597	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3598	return MCDisassembler::Fail;
				3599	return S;
				3600	}
				3601
				3602	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3603	uint64_t Address, const void* Decoder) {
				3604	DecodeStatus S = MCDisassembler::Success;
				3605
				3606	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3607	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3608	int imm = fieldFromInstruction(Insn, 0, 12);
				3609
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	3610	const FeatureBitset &featureBits =
				3611	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3612
				3613	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3614
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3615	if (Rt == 15) {
				3616	switch (Inst.getOpcode()) {
				3617	case ARM::t2LDRBpci:
				3618	case ARM::t2LDRHpci:
				3619	Inst.setOpcode(ARM::t2PLDpci);
				3620	break;
				3621	case ARM::t2LDRSBpci:
				3622	Inst.setOpcode(ARM::t2PLIpci);
				3623	break;
				3624	case ARM::t2LDRSHpci:
				3625	return MCDisassembler::Fail;
				3626	default:
				3627	break;
				3628	}
				3629	}
				3630
				3631	switch(Inst.getOpcode()) {
				3632	case ARM::t2PLDpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3633	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3634	case ARM::t2PLIpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3635	if (!hasV7Ops)
				3636	return MCDisassembler::Fail;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3637	break;
				3638	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3639	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3640	return MCDisassembler::Fail;
				3641	}
				3642
				3643	if (!U) {
				3644	// Special case for #-0.
				3645	if (imm == 0)
				3646	imm = INT32_MIN;
				3647	else
				3648	imm = -imm;
				3649	}
				3650	Inst.addOperand(MCOperand::CreateImm(imm));
				3651
				3652	return S;
				3653	}
				3654
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3655	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3656	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3657	if (Val == 0)
				3658	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3659	else {
				3660	int imm = Val & 0xFF;
				3661
				3662	if (!(Val & 0x100)) imm *= -1;
Richard Smith	228e6d4	2012-08-24 23:29:28 +0000	[diff] [blame]	3663	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3664	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3665
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3666	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3667	}
				3668
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3669	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3670	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3671	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3672
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3673	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3674	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3675
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3676	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3677	return MCDisassembler::Fail;
				3678	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3679	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3680
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3681	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3682	}
				3683
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3684	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3685	uint64_t Address, const void *Decoder) {
				3686	DecodeStatus S = MCDisassembler::Success;
				3687
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3688	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3689	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3690
				3691	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3692	return MCDisassembler::Fail;
				3693
				3694	Inst.addOperand(MCOperand::CreateImm(imm));
				3695
				3696	return S;
				3697	}
				3698
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3699	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3700	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3701	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3702	if (Val == 0)
				3703	imm = INT32_MIN;
				3704	else if (!(Val & 0x100))
				3705	imm *= -1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3706	Inst.addOperand(MCOperand::CreateImm(imm));
				3707
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3708	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3709	}
				3710
				3711
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3712	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3713	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3714	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3715
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3716	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3717	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3718
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3719	// Thumb stores cannot use PC as dest register.
				3720	switch (Inst.getOpcode()) {
				3721	case ARM::t2STRT:
				3722	case ARM::t2STRBT:
				3723	case ARM::t2STRHT:
				3724	case ARM::t2STRi8:
				3725	case ARM::t2STRHi8:
				3726	case ARM::t2STRBi8:
				3727	if (Rn == 15)
				3728	return MCDisassembler::Fail;
				3729	break;
				3730	default:
				3731	break;
				3732	}
				3733
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3734	// Some instructions always use an additive offset.
				3735	switch (Inst.getOpcode()) {
				3736	case ARM::t2LDRT:
				3737	case ARM::t2LDRBT:
				3738	case ARM::t2LDRHT:
				3739	case ARM::t2LDRSBT:
				3740	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3741	case ARM::t2STRT:
				3742	case ARM::t2STRBT:
				3743	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3744	imm \|= 0x100;
				3745	break;
				3746	default:
				3747	break;
				3748	}
				3749
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3750	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3751	return MCDisassembler::Fail;
				3752	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3753	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3754
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3755	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3756	}
				3757
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3758	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3759	uint64_t Address, const void *Decoder) {
				3760	DecodeStatus S = MCDisassembler::Success;
				3761
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3762	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3763	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3764	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3765	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3766	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3767	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3768
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3769	if (Rn == 15) {
				3770	switch (Inst.getOpcode()) {
				3771	case ARM::t2LDR_PRE:
				3772	case ARM::t2LDR_POST:
				3773	Inst.setOpcode(ARM::t2LDRpci);
				3774	break;
				3775	case ARM::t2LDRB_PRE:
				3776	case ARM::t2LDRB_POST:
				3777	Inst.setOpcode(ARM::t2LDRBpci);
				3778	break;
				3779	case ARM::t2LDRH_PRE:
				3780	case ARM::t2LDRH_POST:
				3781	Inst.setOpcode(ARM::t2LDRHpci);
				3782	break;
				3783	case ARM::t2LDRSB_PRE:
				3784	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3785	if (Rt == 15)
				3786	Inst.setOpcode(ARM::t2PLIpci);
				3787	else
				3788	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3789	break;
				3790	case ARM::t2LDRSH_PRE:
				3791	case ARM::t2LDRSH_POST:
				3792	Inst.setOpcode(ARM::t2LDRSHpci);
				3793	break;
				3794	default:
				3795	return MCDisassembler::Fail;
				3796	}
				3797	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3798	}
				3799
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3800	if (!load) {
				3801	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3802	return MCDisassembler::Fail;
				3803	}
				3804
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3805	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3806	return MCDisassembler::Fail;
				3807
				3808	if (load) {
				3809	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3810	return MCDisassembler::Fail;
				3811	}
				3812
				3813	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3814	return MCDisassembler::Fail;
				3815
				3816	return S;
				3817	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3818
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3819	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3820	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3821	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3822
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3823	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3824	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3825
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3826	// Thumb stores cannot use PC as dest register.
				3827	switch (Inst.getOpcode()) {
				3828	case ARM::t2STRi12:
				3829	case ARM::t2STRBi12:
				3830	case ARM::t2STRHi12:
				3831	if (Rn == 15)
				3832	return MCDisassembler::Fail;
				3833	default:
				3834	break;
				3835	}
				3836
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3837	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3838	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3839	Inst.addOperand(MCOperand::CreateImm(imm));
				3840
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3841	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3842	}
				3843
				3844
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3845	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3846	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3847	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3848
				3849	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3850	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3851	Inst.addOperand(MCOperand::CreateImm(imm));
				3852
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3853	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3854	}
				3855
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3856	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3857	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3858	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3859
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3860	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3861	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3862	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3863
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3864	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3865	return MCDisassembler::Fail;
Jim Grosbach	9d8f6f3	2012-04-27 23:51:33 +0000	[diff] [blame]	3866	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3867	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3868	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3869	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3870	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3871
				3872	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3873	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3874	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3875	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3876	}
				3877
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3878	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3879	}
				3880
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3881	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3882	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3883	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3884	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3885
				3886	Inst.addOperand(MCOperand::CreateImm(imod));
				3887	Inst.addOperand(MCOperand::CreateImm(flags));
				3888
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3889	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3890	}
				3891
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3892	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3893	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3894	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3895	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3896	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3897
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3898	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3899	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3900	Inst.addOperand(MCOperand::CreateImm(add));
				3901
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3902	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3903	}
				3904
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3905	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3906	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3907	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3908	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3909	// the encoded instruction. So here change to I1 and I2 values via:
				3910	// I1 = NOT(J1 EOR S);
				3911	// I2 = NOT(J2 EOR S);
				3912	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3913	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3914	unsigned S = (Val >> 23) & 1;
				3915	unsigned J1 = (Val >> 22) & 1;
				3916	unsigned J2 = (Val >> 21) & 1;
				3917	unsigned I1 = !(J1 ^ S);
				3918	unsigned I2 = !(J2 ^ S);
				3919	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3920	int imm32 = SignExtend32<25>(tmp << 1);
				3921
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3922	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3923	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3924	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3925	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3926	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3927	}
				3928
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3929	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3930	uint64_t Address, const void *Decoder) {
				3931	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3932	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3933
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	3934	const FeatureBitset &featureBits =
				3935	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3936
				3937	if (featureBits[ARM::HasV8Ops] && !(Val == 14 \|\| Val == 15))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	3938	return MCDisassembler::Fail;
				3939
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3940	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3941	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3942	}
				3943
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3944	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3945	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3946	uint64_t Address, const void *Decoder) {
				3947	DecodeStatus S = MCDisassembler::Success;
				3948
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3949	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3950	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3951
				3952	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3953	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3954	return MCDisassembler::Fail;
				3955	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3956	return MCDisassembler::Fail;
				3957	return S;
				3958	}
				3959
				3960	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3961	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3962	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3963	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3964
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3965	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3966	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3967	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3968	switch (opc) {
				3969	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3970	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3971	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3972	Inst.setOpcode(ARM::t2DSB);
				3973	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3974	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3975	Inst.setOpcode(ARM::t2DMB);
				3976	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3977	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3978	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3979	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3980	}
				3981
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3982	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3983	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3984	}
				3985
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3986	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3987	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3988	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3989	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3990	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3991
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3992	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3993	return MCDisassembler::Fail;
				3994	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3995	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3996
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3997	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3998	}
				3999
				4000	// Decode a shifted immediate operand. These basically consist
				4001	// of an 8-bit value, and a 4-bit directive that specifies either
				4002	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4003	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4004	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4005	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4006	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4007	unsigned byte = fieldFromInstruction(Val, 8, 2);
				4008	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4009	switch (byte) {
				4010	case 0:
				4011	Inst.addOperand(MCOperand::CreateImm(imm));
				4012	break;
				4013	case 1:
				4014	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				4015	break;
				4016	case 2:
				4017	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				4018	break;
				4019	case 3:
				4020	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				4021	(imm << 8) \| imm));
				4022	break;
				4023	}
				4024	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4025	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				4026	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4027	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				4028	Inst.addOperand(MCOperand::CreateImm(imm));
				4029	}
				4030
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4031	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4032	}
				4033
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4034	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4035	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4036	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	4037	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	4038	true, 2, Inst, Decoder))
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	4039	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4040	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4041	}
				4042
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4043	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	4044	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4045	// Val is passed in as S:J1:J2:imm10:imm11
				4046	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				4047	// the encoded instruction. So here change to I1 and I2 values via:
				4048	// I1 = NOT(J1 EOR S);
				4049	// I2 = NOT(J2 EOR S);
				4050	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	4051	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4052	unsigned S = (Val >> 23) & 1;
				4053	unsigned J1 = (Val >> 22) & 1;
				4054	unsigned J2 = (Val >> 21) & 1;
				4055	unsigned I1 = !(J1 ^ S);
				4056	unsigned I2 = !(J2 ^ S);
				4057	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				4058	int imm32 = SignExtend32<25>(tmp << 1);
				4059
				4060	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	4061	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4062	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4063	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4064	}
				4065
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4066	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4067	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	4068	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4069	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4070
				4071	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4072	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4073	}
				4074
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4075	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				4076	uint64_t Address, const void *Decoder) {
				4077	if (Val & ~0xf)
				4078	return MCDisassembler::Fail;
				4079
				4080	Inst.addOperand(MCOperand::CreateImm(Val));
				4081	return MCDisassembler::Success;
				4082	}
				4083
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4084	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4085	uint64_t Address, const void *Decoder) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4086	DecodeStatus S = MCDisassembler::Success;
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	4087	const FeatureBitset &FeatureBits =
				4088	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				4089
				4090	if (FeatureBits[ARM::FeatureMClass]) {
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4091	unsigned ValLow = Val & 0xff;
				4092
				4093	// Validate the SYSm value first.
				4094	switch (ValLow) {
				4095	case 0: // apsr
				4096	case 1: // iapsr
				4097	case 2: // eapsr
				4098	case 3: // xpsr
				4099	case 5: // ipsr
				4100	case 6: // epsr
				4101	case 7: // iepsr
				4102	case 8: // msp
				4103	case 9: // psp
				4104	case 16: // primask
				4105	case 20: // control
				4106	break;
				4107	case 17: // basepri
				4108	case 18: // basepri_max
				4109	case 19: // faultmask
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	4110	if (!(FeatureBits[ARM::HasV7Ops]))
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4111	// Values basepri, basepri_max and faultmask are only valid for v7m.
				4112	return MCDisassembler::Fail;
				4113	break;
				4114	default:
				4115	return MCDisassembler::Fail;
				4116	}
				4117
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4118	if (Inst.getOpcode() == ARM::t2MSR_M) {
				4119	unsigned Mask = fieldFromInstruction(Val, 10, 2);
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	4120	if (!(FeatureBits[ARM::HasV7Ops])) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4121	// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
				4122	// unpredictable.
				4123	if (Mask != 2)
				4124	S = MCDisassembler::SoftFail;
				4125	}
				4126	else {
				4127	// The ARMv7-M architecture stores an additional 2-bit mask value in
				4128	// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
				4129	// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
				4130	// the NZCVQ bits should be moved by the instruction. Bit mask{0}
				4131	// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
				4132	// only if the processor includes the DSP extension.
				4133	if (Mask == 0 \|\| (Mask != 2 && ValLow > 3) \|\|
Michael Kuperstein	aba4a34	2015-05-13 08:27:08 +0000	[diff] [blame]	4134	(!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4135	S = MCDisassembler::SoftFail;
				4136	}
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4137	}
				4138	} else {
				4139	// A/R class
				4140	if (Val == 0)
				4141	return MCDisassembler::Fail;
				4142	}
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4143	Inst.addOperand(MCOperand::CreateImm(Val));
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4144	return S;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4145	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4146
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4147	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
				4148	uint64_t Address, const void *Decoder) {
				4149
				4150	unsigned R = fieldFromInstruction(Val, 5, 1);
				4151	unsigned SysM = fieldFromInstruction(Val, 0, 5);
				4152
				4153	// The table of encodings for these banked registers comes from B9.2.3 of the
				4154	// ARM ARM. There are patterns, but nothing regular enough to make this logic
				4155	// neater. So by fiat, these values are UNPREDICTABLE:
				4156	if (!R) {
				4157	if (SysM == 0x7 \|\| SysM == 0xf \|\| SysM == 0x18 \|\| SysM == 0x19 \|\|
				4158	SysM == 0x1a \|\| SysM == 0x1b)
				4159	return MCDisassembler::SoftFail;
				4160	} else {
				4161	if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
				4162	SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
				4163	return MCDisassembler::SoftFail;
				4164	}
				4165
				4166	Inst.addOperand(MCOperand::CreateImm(Val));
				4167	return MCDisassembler::Success;
				4168	}
				4169
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4170	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4171	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4172	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4173
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4174	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4175	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4176	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4177
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4178	if (Rn == 0xF)
				4179	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4180
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4181	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4182	return MCDisassembler::Fail;
				4183	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4184	return MCDisassembler::Fail;
				4185	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4186	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4187
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4188	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4189	}
				4190
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4191	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4192	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4193	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4194
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4195	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4196	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				4197	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4198	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4199
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	4200	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4201	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4202
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4203	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4204	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4205
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4206	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4207	return MCDisassembler::Fail;
				4208	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4209	return MCDisassembler::Fail;
				4210	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4211	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4212
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4213	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4214	}
				4215
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4216	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4217	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4218	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4219
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4220	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4221	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4222	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4223	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4224	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4225	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4226
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4227	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4228
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4229	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4230	return MCDisassembler::Fail;
				4231	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4232	return MCDisassembler::Fail;
				4233	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4234	return MCDisassembler::Fail;
				4235	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4236	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4237
				4238	return S;
				4239	}
				4240
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4241	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4242	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4243	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4244
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4245	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4246	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4247	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4248	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4249	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4250	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4251	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4252
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4253	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4254	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4255
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4256	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4257	return MCDisassembler::Fail;
				4258	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4259	return MCDisassembler::Fail;
				4260	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4261	return MCDisassembler::Fail;
				4262	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4263	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4264
				4265	return S;
				4266	}
				4267
				4268
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4269	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4270	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4271	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4272
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4273	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4274	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4275	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4276	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4277	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4278	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4279
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4280	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4281
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4282	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4283	return MCDisassembler::Fail;
				4284	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4285	return MCDisassembler::Fail;
				4286	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4287	return MCDisassembler::Fail;
				4288	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4289	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4290
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4291	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4292	}
				4293
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4294	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4295	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4296	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4297
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4298	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4299	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4300	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4301	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4302	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4303	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4304
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4305	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4306
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4307	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4308	return MCDisassembler::Fail;
				4309	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4310	return MCDisassembler::Fail;
				4311	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4312	return MCDisassembler::Fail;
				4313	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4314	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4315
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4316	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4317	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4318
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4319	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4320	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4321	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4322
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4323	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4324	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4325	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4326	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4327	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4328
				4329	unsigned align = 0;
				4330	unsigned index = 0;
				4331	switch (size) {
				4332	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4333	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4334	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4335	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4336	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4337	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4338	break;
				4339	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4340	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4341	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4342	index = fieldFromInstruction(Insn, 6, 2);
				4343	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4344	align = 2;
				4345	break;
				4346	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4347	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4348	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4349	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4350
				4351	switch (fieldFromInstruction(Insn, 4, 2)) {
				4352	case 0 :
				4353	align = 0; break;
				4354	case 3:
				4355	align = 4; break;
				4356	default:
				4357	return MCDisassembler::Fail;
				4358	}
				4359	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4360	}
				4361
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4362	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4363	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4364	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4365	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4366	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4367	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4368	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4369	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4370	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4371	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4372	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4373	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4374	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4375	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4376	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4377	}
				4378
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4379	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4380	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4381	Inst.addOperand(MCOperand::CreateImm(index));
				4382
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4383	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4384	}
				4385
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4386	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4387	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4388	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4389
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4390	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4391	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4392	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4393	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4394	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4395
				4396	unsigned align = 0;
				4397	unsigned index = 0;
				4398	switch (size) {
				4399	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4400	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4401	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4402	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4403	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4404	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4405	break;
				4406	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4407	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4408	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4409	index = fieldFromInstruction(Insn, 6, 2);
				4410	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4411	align = 2;
				4412	break;
				4413	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4414	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4415	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4416	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4417
				4418	switch (fieldFromInstruction(Insn, 4, 2)) {
				4419	case 0:
				4420	align = 0; break;
				4421	case 3:
				4422	align = 4; break;
				4423	default:
				4424	return MCDisassembler::Fail;
				4425	}
				4426	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4427	}
				4428
				4429	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4430	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4431	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4432	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4433	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4434	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4435	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4436	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4437	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4438	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4439	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4440	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4441	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4442	}
				4443
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4444	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4445	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4446	Inst.addOperand(MCOperand::CreateImm(index));
				4447
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4448	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4449	}
				4450
				4451
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4452	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4453	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4454	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4455
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4456	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4457	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4458	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4459	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4460	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4461
				4462	unsigned align = 0;
				4463	unsigned index = 0;
				4464	unsigned inc = 1;
				4465	switch (size) {
				4466	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4467	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4468	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4469	index = fieldFromInstruction(Insn, 5, 3);
				4470	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4471	align = 2;
				4472	break;
				4473	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4474	index = fieldFromInstruction(Insn, 6, 2);
				4475	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4476	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4477	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4478	inc = 2;
				4479	break;
				4480	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4481	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4482	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4483	index = fieldFromInstruction(Insn, 7, 1);
				4484	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4485	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4486	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4487	inc = 2;
				4488	break;
				4489	}
				4490
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4491	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4492	return MCDisassembler::Fail;
				4493	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4494	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4495	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4496	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4497	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4498	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4499	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4500	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4501	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4502	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4503	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4504	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4505	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4506	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4507	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4508	}
				4509
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4510	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4511	return MCDisassembler::Fail;
				4512	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4513	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4514	Inst.addOperand(MCOperand::CreateImm(index));
				4515
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4516	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4517	}
				4518
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4519	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4520	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4521	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4522
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4523	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4524	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4525	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4526	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4527	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4528
				4529	unsigned align = 0;
				4530	unsigned index = 0;
				4531	unsigned inc = 1;
				4532	switch (size) {
				4533	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4534	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4535	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4536	index = fieldFromInstruction(Insn, 5, 3);
				4537	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4538	align = 2;
				4539	break;
				4540	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4541	index = fieldFromInstruction(Insn, 6, 2);
				4542	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4543	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4544	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4545	inc = 2;
				4546	break;
				4547	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4548	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4549	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4550	index = fieldFromInstruction(Insn, 7, 1);
				4551	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4552	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4553	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4554	inc = 2;
				4555	break;
				4556	}
				4557
				4558	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4559	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4560	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4561	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4562	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4563	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4564	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4565	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4566	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4567	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4568	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4569	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4570	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4571	}
				4572
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4573	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4574	return MCDisassembler::Fail;
				4575	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4576	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4577	Inst.addOperand(MCOperand::CreateImm(index));
				4578
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4579	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4580	}
				4581
				4582
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4583	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4584	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4585	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4586
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4587	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4588	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4589	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4590	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4591	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4592
				4593	unsigned align = 0;
				4594	unsigned index = 0;
				4595	unsigned inc = 1;
				4596	switch (size) {
				4597	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4598	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4599	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4600	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4601	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4602	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4603	break;
				4604	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4605	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4606	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4607	index = fieldFromInstruction(Insn, 6, 2);
				4608	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4609	inc = 2;
				4610	break;
				4611	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4612	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4613	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4614	index = fieldFromInstruction(Insn, 7, 1);
				4615	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4616	inc = 2;
				4617	break;
				4618	}
				4619
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4620	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4621	return MCDisassembler::Fail;
				4622	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4623	return MCDisassembler::Fail;
				4624	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4625	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4626
				4627	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4628	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4629	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4630	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4631	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4632	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4633	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4634	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4635	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4636	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4637	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4638	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4639	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4640	}
				4641
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4642	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4643	return MCDisassembler::Fail;
				4644	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4645	return MCDisassembler::Fail;
				4646	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4647	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4648	Inst.addOperand(MCOperand::CreateImm(index));
				4649
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4650	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4651	}
				4652
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4653	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4654	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4655	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4656
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4657	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4658	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4659	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4660	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4661	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4662
				4663	unsigned align = 0;
				4664	unsigned index = 0;
				4665	unsigned inc = 1;
				4666	switch (size) {
				4667	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4668	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4669	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4670	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4671	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4672	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4673	break;
				4674	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4675	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4676	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4677	index = fieldFromInstruction(Insn, 6, 2);
				4678	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4679	inc = 2;
				4680	break;
				4681	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4682	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4683	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4684	index = fieldFromInstruction(Insn, 7, 1);
				4685	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4686	inc = 2;
				4687	break;
				4688	}
				4689
				4690	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4691	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4692	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4693	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4694	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4695	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4696	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4697	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4698	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4699	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4700	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4701	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4702	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4703	}
				4704
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4705	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4706	return MCDisassembler::Fail;
				4707	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4708	return MCDisassembler::Fail;
				4709	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4710	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4711	Inst.addOperand(MCOperand::CreateImm(index));
				4712
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4713	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4714	}
				4715
				4716
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4717	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4718	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4719	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4720
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4721	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4722	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4723	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4724	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4725	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4726
				4727	unsigned align = 0;
				4728	unsigned index = 0;
				4729	unsigned inc = 1;
				4730	switch (size) {
				4731	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4732	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4733	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4734	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4735	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4736	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4737	break;
				4738	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4739	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4740	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4741	index = fieldFromInstruction(Insn, 6, 2);
				4742	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4743	inc = 2;
				4744	break;
				4745	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4746	switch (fieldFromInstruction(Insn, 4, 2)) {
				4747	case 0:
				4748	align = 0; break;
				4749	case 3:
				4750	return MCDisassembler::Fail;
				4751	default:
				4752	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4753	}
				4754
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4755	index = fieldFromInstruction(Insn, 7, 1);
				4756	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4757	inc = 2;
				4758	break;
				4759	}
				4760
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4761	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4762	return MCDisassembler::Fail;
				4763	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4764	return MCDisassembler::Fail;
				4765	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4766	return MCDisassembler::Fail;
				4767	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4768	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4769
				4770	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4771	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4772	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4773	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4774	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4775	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4776	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4777	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4778	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4779	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4780	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4781	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4782	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4783	}
				4784
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4785	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4786	return MCDisassembler::Fail;
				4787	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4788	return MCDisassembler::Fail;
				4789	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4790	return MCDisassembler::Fail;
				4791	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4792	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4793	Inst.addOperand(MCOperand::CreateImm(index));
				4794
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4795	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4796	}
				4797
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4798	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4799	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4800	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4801
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4802	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4803	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4804	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4805	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4806	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4807
				4808	unsigned align = 0;
				4809	unsigned index = 0;
				4810	unsigned inc = 1;
				4811	switch (size) {
				4812	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4813	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4814	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4815	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4816	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4817	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4818	break;
				4819	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4820	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4821	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4822	index = fieldFromInstruction(Insn, 6, 2);
				4823	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4824	inc = 2;
				4825	break;
				4826	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4827	switch (fieldFromInstruction(Insn, 4, 2)) {
				4828	case 0:
				4829	align = 0; break;
				4830	case 3:
				4831	return MCDisassembler::Fail;
				4832	default:
				4833	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4834	}
				4835
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4836	index = fieldFromInstruction(Insn, 7, 1);
				4837	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4838	inc = 2;
				4839	break;
				4840	}
				4841
				4842	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4843	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4844	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4845	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4846	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4847	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4848	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4849	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4850	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4851	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4852	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4853	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4854	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4855	}
				4856
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4857	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4858	return MCDisassembler::Fail;
				4859	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4860	return MCDisassembler::Fail;
				4861	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4862	return MCDisassembler::Fail;
				4863	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4864	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4865	Inst.addOperand(MCOperand::CreateImm(index));
				4866
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4867	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4868	}
				4869
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4870	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4871	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4872	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4873	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4874	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4875	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4876	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4877	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4878
				4879	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4880	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4881
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4882	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4883	return MCDisassembler::Fail;
				4884	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4885	return MCDisassembler::Fail;
				4886	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4887	return MCDisassembler::Fail;
				4888	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4889	return MCDisassembler::Fail;
				4890	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4891	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4892
				4893	return S;
				4894	}
				4895
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4896	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4897	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4898	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4899	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4900	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4901	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4902	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4903	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4904
				4905	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4906	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4907
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4908	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4909	return MCDisassembler::Fail;
				4910	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4911	return MCDisassembler::Fail;
				4912	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4913	return MCDisassembler::Fail;
				4914	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4915	return MCDisassembler::Fail;
				4916	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4917	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4918
				4919	return S;
				4920	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4921
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4922	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4923	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4924	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4925	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4926	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4927
				4928	if (pred == 0xF) {
				4929	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4930	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4931	}
				4932
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4933	if (mask == 0x0)
				4934	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4935
				4936	Inst.addOperand(MCOperand::CreateImm(pred));
				4937	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4938	return S;
				4939	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4940
				4941	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4942	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4943	uint64_t Address, const void *Decoder) {
				4944	DecodeStatus S = MCDisassembler::Success;
				4945
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4946	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4947	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4948	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4949	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4950	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4951	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4952	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4953	bool writeback = (W == 1) \| (P == 0);
				4954
				4955	addr \|= (U << 8) \| (Rn << 9);
				4956
				4957	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4958	Check(S, MCDisassembler::SoftFail);
				4959	if (Rt == Rt2)
				4960	Check(S, MCDisassembler::SoftFail);
				4961
				4962	// Rt
				4963	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4964	return MCDisassembler::Fail;
				4965	// Rt2
				4966	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4967	return MCDisassembler::Fail;
				4968	// Writeback operand
				4969	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4970	return MCDisassembler::Fail;
				4971	// addr
				4972	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4973	return MCDisassembler::Fail;
				4974
				4975	return S;
				4976	}
				4977
				4978	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4979	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4980	uint64_t Address, const void *Decoder) {
				4981	DecodeStatus S = MCDisassembler::Success;
				4982
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4983	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4984	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4985	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4986	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4987	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4988	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4989	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4990	bool writeback = (W == 1) \| (P == 0);
				4991
				4992	addr \|= (U << 8) \| (Rn << 9);
				4993
				4994	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4995	Check(S, MCDisassembler::SoftFail);
				4996
				4997	// Writeback operand
				4998	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4999	return MCDisassembler::Fail;
				5000	// Rt
				5001	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				5002	return MCDisassembler::Fail;
				5003	// Rt2
				5004	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				5005	return MCDisassembler::Fail;
				5006	// addr
				5007	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				5008	return MCDisassembler::Fail;
				5009
				5010	return S;
				5011	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5012
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5013	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5014	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5015	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				5016	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5017	if (sign1 != sign2) return MCDisassembler::Fail;
				5018
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5019	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				5020	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				5021	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5022	Val \|= sign1 << 12;
				5023	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				5024
				5025	return MCDisassembler::Success;
				5026	}
				5027
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5028	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5029	uint64_t Address,
				5030	const void *Decoder) {
				5031	DecodeStatus S = MCDisassembler::Success;
				5032
				5033	// Shift of "asr #32" is not allowed in Thumb2 mode.
Bradley Smith	3131e85	2015-01-19 16:37:17 +0000	[diff] [blame]	5034	if (Val == 0x20) S = MCDisassembler::Fail;
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5035	Inst.addOperand(MCOperand::CreateImm(Val));
				5036	return S;
				5037	}
				5038
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5039	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5040	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5041	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5042	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				5043	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5044	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5045
				5046	if (pred == 0xF)
				5047	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				5048
				5049	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	5050
				5051	if (Rt == Rn \|\| Rn == Rt2)
				5052	S = MCDisassembler::SoftFail;
				5053
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5054	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5055	return MCDisassembler::Fail;
				5056	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5057	return MCDisassembler::Fail;
				5058	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5059	return MCDisassembler::Fail;
				5060	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				5061	return MCDisassembler::Fail;
				5062
				5063	return S;
				5064	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5065
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5066	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5067	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5068	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5069	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5070	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5071	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5072	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5073	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5074	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5075
				5076	DecodeStatus S = MCDisassembler::Success;
				5077
				5078	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	05060f0	2011-11-15 20:30:41 +0000	[diff] [blame]	5079	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5080	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5081	Inst.setOpcode(ARM::VMOVv2f32);
				5082	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5083	}
				5084
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5085	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5086
				5087	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				5088	return MCDisassembler::Fail;
				5089	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				5090	return MCDisassembler::Fail;
				5091	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				5092
				5093	return S;
				5094	}
				5095
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5096	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5097	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5098	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5099	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5100	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5101	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5102	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5103	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5104	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5105
				5106	DecodeStatus S = MCDisassembler::Success;
				5107
				5108	// VMOVv4f32 is ambiguous with these decodings.
				5109	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5110	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5111	Inst.setOpcode(ARM::VMOVv4f32);
				5112	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5113	}
				5114
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5115	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5116
				5117	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				5118	return MCDisassembler::Fail;
				5119	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				5120	return MCDisassembler::Fail;
				5121	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				5122
				5123	return S;
				5124	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5125
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5126	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5127	uint64_t Address, const void *Decoder) {
				5128	DecodeStatus S = MCDisassembler::Success;
				5129
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5130	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				5131	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5132	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				5133	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				5134	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5135
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5136	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5137	S = MCDisassembler::SoftFail;
				5138
				5139	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5140	return MCDisassembler::Fail;
				5141	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5142	return MCDisassembler::Fail;
				5143	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				5144	return MCDisassembler::Fail;
				5145	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				5146	return MCDisassembler::Fail;
				5147	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				5148	return MCDisassembler::Fail;
				5149
				5150	return S;
				5151	}
				5152
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5153	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				5154	uint64_t Address, const void *Decoder) {
				5155
				5156	DecodeStatus S = MCDisassembler::Success;
				5157
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5158	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				5159	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				5160	unsigned cop = fieldFromInstruction(Val, 8, 4);
				5161	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5162	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5163
				5164	if ((cop & ~0x1) == 0xa)
				5165	return MCDisassembler::Fail;
				5166
				5167	if (Rt == Rt2)
				5168	S = MCDisassembler::SoftFail;
				5169
				5170	Inst.addOperand(MCOperand::CreateImm(cop));
				5171	Inst.addOperand(MCOperand::CreateImm(opc1));
				5172	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5173	return MCDisassembler::Fail;
				5174	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5175	return MCDisassembler::Fail;
				5176	Inst.addOperand(MCOperand::CreateImm(CRm));
				5177
				5178	return S;
				5179	}
				5180