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Chris Lattner97f06932009-10-19 20:20:46 +00001//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattner95b2c7d2006-12-19 22:59:26 +000015#define DEBUG_TYPE "asm-printer"
Jim Grosbachbaf120f2010-12-01 03:45:07 +000016#include "ARMAsmPrinter.h"
Craig Topperc1f6f422012-03-17 07:33:42 +000017#include "ARM.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000018#include "ARMBuildAttrs.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000019#include "ARMConstantPoolValue.h"
Chris Lattner97f06932009-10-19 20:20:46 +000020#include "ARMMachineFunctionInfo.h"
Chris Lattner97f06932009-10-19 20:20:46 +000021#include "ARMTargetMachine.h"
Jason W Kim17b443d2010-10-11 23:01:44 +000022#include "ARMTargetObjectFile.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000023#include "InstPrinter/ARMInstPrinter.h"
Evan Chengee04a6d2011-07-20 23:34:39 +000024#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMMCExpr.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000026#include "llvm/Constants.h"
Bill Wendling0bcbd1d2012-06-28 00:05:13 +000027#include "llvm/DebugInfo.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000028#include "llvm/Module.h"
Benjamin Kramere55b15f2009-12-28 12:27:56 +000029#include "llvm/Type.h"
Dan Gohmancf20ac42009-08-13 01:36:44 +000030#include "llvm/Assembly/Writer.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000031#include "llvm/CodeGen/MachineModuleInfoImpls.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000032#include "llvm/CodeGen/MachineFunctionPass.h"
Evan Chenga8e29892007-01-19 07:51:42 +000033#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000034#include "llvm/MC/MCAsmInfo.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000035#include "llvm/MC/MCAssembler.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000036#include "llvm/MC/MCContext.h"
Chris Lattner97f06932009-10-19 20:20:46 +000037#include "llvm/MC/MCInst.h"
Chris Lattnerf9bdedd2009-08-10 18:15:01 +000038#include "llvm/MC/MCSectionMachO.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000039#include "llvm/MC/MCObjectStreamer.h"
Chris Lattner6c2f9e12009-08-19 05:49:37 +000040#include "llvm/MC/MCStreamer.h"
Chris Lattner325d3dc2009-09-13 17:14:04 +000041#include "llvm/MC/MCSymbol.h"
Chris Lattnerd62f1b42010-03-12 21:19:23 +000042#include "llvm/Target/Mangler.h"
Rafael Espindolab01c4bb2006-07-27 11:38:51 +000043#include "llvm/Target/TargetData.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000044#include "llvm/Target/TargetMachine.h"
Jim Grosbachc40d9f92009-09-01 18:49:12 +000045#include "llvm/ADT/SmallString.h"
Chris Lattner97f06932009-10-19 20:20:46 +000046#include "llvm/Support/CommandLine.h"
Devang Patel59135f42010-08-04 22:39:39 +000047#include "llvm/Support/Debug.h"
Torok Edwin30464702009-07-08 20:55:50 +000048#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +000049#include "llvm/Support/TargetRegistry.h"
Chris Lattnerb23569a2010-04-04 08:18:47 +000050#include "llvm/Support/raw_ostream.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000051#include <cctype>
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000052using namespace llvm;
53
Chris Lattner95b2c7d2006-12-19 22:59:26 +000054namespace {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000055
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
61 public:
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
Jason W Kimf009a962011-02-07 00:49:53 +000064 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000065 virtual void Finish() = 0;
Rafael Espindola4921e232010-10-25 18:38:32 +000066 virtual ~AttributeEmitter() {}
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000067 };
68
69 class AsmAttributeEmitter : public AttributeEmitter {
70 MCStreamer &Streamer;
71
72 public:
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
75
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
79 }
80
Jason W Kimf009a962011-02-07 00:49:53 +000081 void EmitTextAttribute(unsigned Attribute, StringRef String) {
82 switch (Attribute) {
Craig Topperbc219812012-02-07 02:50:20 +000083 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
Jason W Kimf009a962011-02-07 00:49:53 +000084 case ARMBuildAttrs::CPU_name:
Benjamin Kramer59085362011-11-06 20:37:06 +000085 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
Jason W Kimf009a962011-02-07 00:49:53 +000086 break;
Renato Golin728ff0d2011-02-28 22:04:27 +000087 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
Benjamin Kramer59085362011-11-06 20:37:06 +000090 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
Jim Grosbach8e0c7692011-09-02 18:46:15 +000091 break;
Jason W Kimf009a962011-02-07 00:49:53 +000092 }
93 }
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000094 void Finish() { }
95 };
96
97 class ObjectAttributeEmitter : public AttributeEmitter {
Renato Golin719927a2011-08-09 09:50:10 +000098 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
102 enum {
103 HiddenAttribute = 0,
104 NumericAttribute,
105 TextAttribute
106 } Type;
107 unsigned Tag;
108 unsigned IntValue;
109 StringRef StringValue;
110 } AttributeItem;
111
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000112 MCObjectStreamer &Streamer;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000113 StringRef CurrentVendor;
Renato Golin719927a2011-08-09 09:50:10 +0000114 SmallVector<AttributeItemType, 64> Contents;
115
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
118 size_t ContentsSize;
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
122 size_t Size = 0;
123 do {
124 Value >>= 7;
125 Size += sizeof(int8_t); // Is this really necessary?
126 } while (Value);
127 return Size;
128 }
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000129
130 public:
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
Renato Golin719927a2011-08-09 09:50:10 +0000132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000133
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
136
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
140 return;
141 else
142 Finish();
143
144 CurrentVendor = Vendor;
145
Rafael Espindola33363842010-10-25 22:26:55 +0000146 assert(Contents.size() == 0);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000147 }
148
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
Renato Golin719927a2011-08-09 09:50:10 +0000150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
152 Attribute,
153 Value,
154 StringRef("")
155 };
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000159 }
160
Jason W Kimf009a962011-02-07 00:49:53 +0000161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
Renato Golin719927a2011-08-09 09:50:10 +0000162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
164 Attribute,
165 0,
166 String
167 };
168 ContentsSize += getULEBSize(Attribute);
169 // String + \0
170 ContentsSize += String.size()+1;
171
172 Contents.push_back(attr);
Jason W Kimf009a962011-02-07 00:49:53 +0000173 }
174
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000175 void Finish() {
Rafael Espindola33363842010-10-25 22:26:55 +0000176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000178
Rafael Espindola33363842010-10-25 22:26:55 +0000179 // Tag + Tag Size
180 const size_t TagHeaderSize = 1 + 4;
181
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
185
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000188
Renato Golin719927a2011-08-09 09:50:10 +0000189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
194 switch (item.Type) {
Craig Topperbc219812012-02-07 02:50:20 +0000195 default: llvm_unreachable("Invalid attribute type");
Renato Golin719927a2011-08-09 09:50:10 +0000196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
198 break;
199 case AttributeItemType::TextAttribute:
Benjamin Kramer59085362011-11-06 20:37:06 +0000200 Streamer.EmitBytes(item.StringValue.upper(), 0);
Renato Golin719927a2011-08-09 09:50:10 +0000201 Streamer.EmitIntValue(0, 1); // '\0'
202 break;
Renato Golin719927a2011-08-09 09:50:10 +0000203 }
204 }
Rafael Espindola33363842010-10-25 22:26:55 +0000205
206 Contents.clear();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000207 }
208 };
209
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000210} // end of anonymous namespace
211
Jim Grosbachbaf120f2010-12-01 03:45:07 +0000212MachineLocation ARMAsmPrinter::
213getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
219 else {
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
221 }
222 return Location;
223}
224
Devang Patel27f5acb2011-04-21 22:48:26 +0000225/// EmitDwarfRegOp - Emit dwarf register operation.
Devang Patel0be77df2011-04-27 20:29:27 +0000226void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
Devang Patel27f5acb2011-04-21 22:48:26 +0000227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
Devang Patel0be77df2011-04-27 20:29:27 +0000229 AsmPrinter::EmitDwarfRegOp(MLoc);
Devang Patel27f5acb2011-04-21 22:48:26 +0000230 else {
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
Devang Patel0a6ea832011-04-22 16:44:29 +0000233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
Devang Patel27f5acb2011-04-21 22:48:26 +0000234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000237
Devang Patel27f5acb2011-04-21 22:48:26 +0000238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
Devang Patel27f5acb2011-04-21 22:48:26 +0000241
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
244
245 OutStreamer.AddComment(Twine(SReg));
246 EmitULEB128(Rx);
247
248 if (odd) {
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
251 EmitULEB128(32);
252 EmitULEB128(32);
253 } else {
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
256 EmitULEB128(32);
257 EmitULEB128(0);
258 }
Devang Patel71f3f112011-04-21 23:22:35 +0000259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
Devang Patel0a6ea832011-04-22 16:44:29 +0000260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
Devang Patel71f3f112011-04-21 23:22:35 +0000261 // Q registers Q0-Q15 are described by composing two D registers together.
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
263 // DW_OP_piece(8)
Devang Patel71f3f112011-04-21 23:22:35 +0000264
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000268
Devang Patel71f3f112011-04-21 23:22:35 +0000269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
271 EmitULEB128(D1);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
274 EmitULEB128(8);
275
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
278 EmitULEB128(D2);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
281 EmitULEB128(8);
Devang Patel27f5acb2011-04-21 22:48:26 +0000282 }
283 }
284}
285
Jim Grosbach3e965312012-05-18 19:12:01 +0000286void ARMAsmPrinter::EmitFunctionBodyEnd() {
287 // Make sure to terminate any constant pools that were at the end
288 // of the function.
289 if (!InConstantPool)
290 return;
291 InConstantPool = false;
292 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
293}
Owen Anderson2fec6c52011-10-04 23:26:17 +0000294
Jim Grosbach3e965312012-05-18 19:12:01 +0000295void ARMAsmPrinter::EmitFunctionEntryLabel() {
Chris Lattner953ebb72010-01-27 23:58:11 +0000296 if (AFI->isThumbFunction()) {
Jim Grosbachce792992010-11-05 22:08:08 +0000297 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
Rafael Espindola64695402011-05-16 16:17:21 +0000298 OutStreamer.EmitThumbFunc(CurrentFnSym);
Chris Lattner953ebb72010-01-27 23:58:11 +0000299 }
Jim Grosbachb0739b72010-09-02 01:02:06 +0000300
Chris Lattner953ebb72010-01-27 23:58:11 +0000301 OutStreamer.EmitLabel(CurrentFnSym);
302}
303
James Molloy34982572012-01-26 09:25:43 +0000304void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
305 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
306 assert(Size && "C++ constructor pointer had zero size!");
307
Bill Wendling4a1ff2f2012-02-15 09:14:08 +0000308 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
James Molloy34982572012-01-26 09:25:43 +0000309 assert(GV && "C++ constructor pointer was not a GlobalValue!");
310
311 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
312 (Subtarget->isTargetDarwin()
313 ? MCSymbolRefExpr::VK_None
314 : MCSymbolRefExpr::VK_ARM_TARGET1),
315 OutContext);
316
317 OutStreamer.EmitValue(E, Size);
318}
319
Jim Grosbach2317e402010-09-30 01:57:53 +0000320/// runOnMachineFunction - This uses the EmitInstruction()
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000321/// method to print assembly for each instruction.
322///
323bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
Evan Chenga8e29892007-01-19 07:51:42 +0000324 AFI = MF.getInfo<ARMFunctionInfo>();
Evan Cheng6d63a722008-09-18 07:27:23 +0000325 MCP = MF.getConstantPool();
Rafael Espindola4b442b52006-05-23 02:48:20 +0000326
Chris Lattnerd49fe1b2010-01-28 01:28:58 +0000327 return AsmPrinter::runOnMachineFunction(MF);
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000328}
329
Evan Cheng055b0312009-06-29 07:51:04 +0000330void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
Chris Lattner35c33bd2010-04-04 04:47:45 +0000331 raw_ostream &O, const char *Modifier) {
Evan Cheng055b0312009-06-29 07:51:04 +0000332 const MachineOperand &MO = MI->getOperand(OpNum);
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000333 unsigned TF = MO.getTargetFlags();
334
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000335 switch (MO.getType()) {
Craig Topperbc219812012-02-07 02:50:20 +0000336 default: llvm_unreachable("<unknown operand type>");
Bob Wilson5bafff32009-06-22 23:27:02 +0000337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
Jim Grosbach35636282010-10-06 21:22:32 +0000340 assert(!MO.getSubReg() && "Subregs should be eliminated!");
341 O << ARMInstPrinter::getRegisterName(Reg);
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000342 break;
Bob Wilson5bafff32009-06-22 23:27:02 +0000343 }
Evan Chenga8e29892007-01-19 07:51:42 +0000344 case MachineOperand::MO_Immediate: {
Evan Cheng5adb66a2009-09-28 09:14:39 +0000345 int64_t Imm = MO.getImm();
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000346 O << '#';
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000347 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000348 (TF == ARMII::MO_LO16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000349 O << ":lower16:";
350 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000351 (TF == ARMII::MO_HI16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000352 O << ":upper16:";
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000353 O << Imm;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000354 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000355 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000356 case MachineOperand::MO_MachineBasicBlock:
Chris Lattner1b2eb0e2010-03-13 21:04:28 +0000357 O << *MO.getMBB()->getSymbol();
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000358 return;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000359 case MachineOperand::MO_GlobalAddress: {
Dan Gohman46510a72010-04-15 01:51:59 +0000360 const GlobalValue *GV = MO.getGlobal();
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
363 O << ":lower16:";
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
366 O << ":upper16:";
Chris Lattnerd62f1b42010-03-12 21:19:23 +0000367 O << *Mang->getSymbol(GV);
Anton Korobeynikov7751ad92008-11-22 16:15:34 +0000368
Chris Lattner0c08d092010-04-03 22:28:33 +0000369 printOffset(MO.getOffset(), O);
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000370 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000371 O << "(PLT)";
Evan Chenga8e29892007-01-19 07:51:42 +0000372 break;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000373 }
Evan Chenga8e29892007-01-19 07:51:42 +0000374 case MachineOperand::MO_ExternalSymbol: {
Chris Lattner10b318b2010-01-17 21:43:43 +0000375 O << *GetExternalSymbolSymbol(MO.getSymbolName());
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000376 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000377 O << "(PLT)";
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000378 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000379 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000380 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000381 O << *GetCPISymbol(MO.getIndex());
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000382 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000383 case MachineOperand::MO_JumpTableIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000384 O << *GetJTISymbol(MO.getIndex());
Evan Chenga8e29892007-01-19 07:51:42 +0000385 break;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000386 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000387}
388
Evan Cheng055b0312009-06-29 07:51:04 +0000389//===--------------------------------------------------------------------===//
390
Chris Lattner0890cf12010-01-25 19:51:38 +0000391MCSymbol *ARMAsmPrinter::
392GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
393 const MachineBasicBlock *MBB) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000396 << getFunctionNumber() << '_' << uid << '_' << uid2
Chris Lattner0890cf12010-01-25 19:51:38 +0000397 << "_set_" << MBB->getNumber();
Chris Lattner9b97a732010-03-30 18:10:53 +0000398 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattner0890cf12010-01-25 19:51:38 +0000399}
400
401MCSymbol *ARMAsmPrinter::
402GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
403 SmallString<60> Name;
404 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
Chris Lattner281e7762010-01-25 23:28:03 +0000405 << getFunctionNumber() << '_' << uid << '_' << uid2;
Chris Lattner9b97a732010-03-30 18:10:53 +0000406 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000407}
408
Jim Grosbach433a5782010-09-24 20:47:58 +0000409
410MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
411 SmallString<60> Name;
412 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
413 << getFunctionNumber();
414 return OutContext.GetOrCreateSymbol(Name.str());
415}
416
Evan Cheng055b0312009-06-29 07:51:04 +0000417bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000418 unsigned AsmVariant, const char *ExtraCode,
419 raw_ostream &O) {
Evan Chenga8e29892007-01-19 07:51:42 +0000420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Anton Korobeynikov8e9ece72009-08-08 23:10:41 +0000423
Evan Chenga8e29892007-01-19 07:51:42 +0000424 switch (ExtraCode[0]) {
Jack Carter0518fca2012-06-26 13:49:27 +0000425 default:
426 // See if this is a generic print operand
427 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000428 case 'a': // Print as a memory address.
429 if (MI->getOperand(OpNum).isReg()) {
Jim Grosbach2f24c4e2010-09-30 15:25:22 +0000430 O << "["
431 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
432 << "]";
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000433 return false;
434 }
435 // Fallthrough
436 case 'c': // Don't print "#" before an immediate operand.
Bob Wilson4f38b382009-08-21 21:58:55 +0000437 if (!MI->getOperand(OpNum).isImm())
438 return true;
Jim Grosbach2317e402010-09-30 01:57:53 +0000439 O << MI->getOperand(OpNum).getImm();
Bob Wilson8f343462009-04-06 21:46:51 +0000440 return false;
Evan Chenge21e3962007-04-04 00:13:29 +0000441 case 'P': // Print a VFP double precision register.
Evan Chengd831cda2009-12-08 23:06:22 +0000442 case 'q': // Print a NEON quad precision register.
Chris Lattner35c33bd2010-04-04 04:47:45 +0000443 printOperand(MI, OpNum, O);
Evan Cheng23a95702007-03-08 22:42:46 +0000444 return false;
Eric Christopher0628d382011-05-24 22:10:34 +0000445 case 'y': // Print a VFP single precision register as indexed double.
Eric Christopher0628d382011-05-24 22:10:34 +0000446 if (MI->getOperand(OpNum).isReg()) {
447 unsigned Reg = MI->getOperand(OpNum).getReg();
448 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
Jakob Stoklund Olesen4c91bda2012-05-30 23:00:43 +0000449 // Find the 'd' register that has this 's' register as a sub-register,
450 // and determine the lane number.
451 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
452 if (!ARM::DPRRegClass.contains(*SR))
453 continue;
454 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
455 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
456 return false;
457 }
Eric Christopher0628d382011-05-24 22:10:34 +0000458 }
Eric Christopher4db7dec2011-05-24 23:27:13 +0000459 return true;
Eric Christopherfef50062011-05-24 22:27:43 +0000460 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
Eric Christophere1739d52011-05-24 23:15:43 +0000461 if (!MI->getOperand(OpNum).isImm())
462 return true;
463 O << ~(MI->getOperand(OpNum).getImm());
464 return false;
Eric Christopherfef50062011-05-24 22:27:43 +0000465 case 'L': // The low 16 bits of an immediate constant.
Eric Christopher4db7dec2011-05-24 23:27:13 +0000466 if (!MI->getOperand(OpNum).isImm())
467 return true;
468 O << (MI->getOperand(OpNum).getImm() & 0xffff);
469 return false;
Eric Christopher3c14f242011-05-28 01:40:44 +0000470 case 'M': { // A register range suitable for LDM/STM.
471 if (!MI->getOperand(OpNum).isReg())
472 return true;
473 const MachineOperand &MO = MI->getOperand(OpNum);
474 unsigned RegBegin = MO.getReg();
475 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
476 // already got the operands in registers that are operands to the
477 // inline asm statement.
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000478
Eric Christopher3c14f242011-05-28 01:40:44 +0000479 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000480
Eric Christopher3c14f242011-05-28 01:40:44 +0000481 // FIXME: The register allocator not only may not have given us the
482 // registers in sequence, but may not be in ascending registers. This
483 // will require changes in the register allocator that'll need to be
484 // propagated down here if the operands change.
485 unsigned RegOps = OpNum + 1;
486 while (MI->getOperand(RegOps).isReg()) {
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000487 O << ", "
Eric Christopher3c14f242011-05-28 01:40:44 +0000488 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
489 RegOps++;
490 }
491
492 O << "}";
493
494 return false;
495 }
Rafael Espindolaf5ade5d2011-08-10 16:26:42 +0000496 case 'R': // The most significant register of a pair.
497 case 'Q': { // The least significant register of a pair.
498 if (OpNum == 0)
499 return true;
500 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
501 if (!FlagsOP.isImm())
502 return true;
503 unsigned Flags = FlagsOP.getImm();
504 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
505 if (NumVals != 2)
506 return true;
507 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
508 if (RegOp >= MI->getNumOperands())
509 return true;
510 const MachineOperand &MO = MI->getOperand(RegOp);
511 if (!MO.isReg())
512 return true;
513 unsigned Reg = MO.getReg();
514 O << ARMInstPrinter::getRegisterName(Reg);
515 return false;
516 }
517
Eric Christopherfef50062011-05-24 22:27:43 +0000518 case 'e': // The low doubleword register of a NEON quad register.
Bob Wilson9cd2b952011-12-12 21:45:15 +0000519 case 'f': { // The high doubleword register of a NEON quad register.
520 if (!MI->getOperand(OpNum).isReg())
521 return true;
522 unsigned Reg = MI->getOperand(OpNum).getReg();
523 if (!ARM::QPRRegClass.contains(Reg))
524 return true;
525 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
526 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
527 ARM::dsub_0 : ARM::dsub_1);
528 O << ARMInstPrinter::getRegisterName(SubReg);
529 return false;
530 }
531
532 // These modifiers are not yet supported.
Eric Christopherfef50062011-05-24 22:27:43 +0000533 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
Eric Christopherfef50062011-05-24 22:27:43 +0000534 case 'H': // The highest-numbered register of a pair.
Bob Wilsond984eb62010-05-27 20:23:42 +0000535 return true;
Evan Cheng84f60b72010-05-27 22:08:38 +0000536 }
Evan Chenga8e29892007-01-19 07:51:42 +0000537 }
Jim Grosbache9952212009-09-04 01:38:51 +0000538
Chris Lattner35c33bd2010-04-04 04:47:45 +0000539 printOperand(MI, OpNum, O);
Evan Chenga8e29892007-01-19 07:51:42 +0000540 return false;
541}
542
Bob Wilson224c2442009-05-19 05:53:42 +0000543bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
Evan Cheng055b0312009-06-29 07:51:04 +0000544 unsigned OpNum, unsigned AsmVariant,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000545 const char *ExtraCode,
546 raw_ostream &O) {
Eric Christopher8f894632011-05-25 20:51:58 +0000547 // Does this asm operand have a single letter operand modifier?
548 if (ExtraCode && ExtraCode[0]) {
549 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000550
Eric Christopher8f894632011-05-25 20:51:58 +0000551 switch (ExtraCode[0]) {
Eric Christopher32bfb2c2011-05-26 18:22:26 +0000552 case 'A': // A memory operand for a VLD1/VST1 instruction.
Eric Christopher8f894632011-05-25 20:51:58 +0000553 default: return true; // Unknown modifier.
554 case 'm': // The base register of a memory operand.
555 if (!MI->getOperand(OpNum).isReg())
556 return true;
557 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
558 return false;
559 }
560 }
Jim Grosbach8e0c7692011-09-02 18:46:15 +0000561
Bob Wilson765cc0b2009-10-13 20:50:28 +0000562 const MachineOperand &MO = MI->getOperand(OpNum);
563 assert(MO.isReg() && "unexpected inline asm memory operand");
Jim Grosbach2317e402010-09-30 01:57:53 +0000564 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
Bob Wilson224c2442009-05-19 05:53:42 +0000565 return false;
566}
567
Bob Wilson812209a2009-09-30 22:06:26 +0000568void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
Bob Wilson0fb34682009-09-30 00:23:42 +0000569 if (Subtarget->isTargetDarwin()) {
570 Reloc::Model RelocM = TM.getRelocationModel();
571 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
572 // Declare all the text sections up front (before the DWARF sections
573 // emitted by AsmPrinter::doInitialization) so the assembler will keep
574 // them together at the beginning of the object file. This helps
575 // avoid out-of-range branches that are due a fundamental limitation of
576 // the way symbol offsets are encoded with the current Darwin ARM
577 // relocations.
Jim Grosbachb0739b72010-09-02 01:02:06 +0000578 const TargetLoweringObjectFileMachO &TLOFMacho =
Dan Gohman0d805c32010-04-17 16:44:48 +0000579 static_cast<const TargetLoweringObjectFileMachO &>(
580 getObjFileLowering());
Bob Wilson29e06692009-09-30 22:25:37 +0000581 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
582 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
583 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
584 if (RelocM == Reloc::DynamicNoPIC) {
585 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000586 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
587 MCSectionMachO::S_SYMBOL_STUBS,
588 12, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000589 OutStreamer.SwitchSection(sect);
590 } else {
591 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000592 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
593 MCSectionMachO::S_SYMBOL_STUBS,
594 16, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000595 OutStreamer.SwitchSection(sect);
596 }
Bob Wilson63db5942010-07-30 19:55:47 +0000597 const MCSection *StaticInitSect =
598 OutContext.getMachOSection("__TEXT", "__StaticInit",
599 MCSectionMachO::S_REGULAR |
600 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
601 SectionKind::getText());
602 OutStreamer.SwitchSection(StaticInitSect);
Bob Wilson0fb34682009-09-30 00:23:42 +0000603 }
604 }
605
Jim Grosbache5165492009-11-09 00:11:35 +0000606 // Use unified assembler syntax.
Jason W Kimafd1cc22010-09-30 02:45:56 +0000607 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
Anton Korobeynikovd61eca52009-06-17 23:43:18 +0000608
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000609 // Emit ARM Build Attributes
Evan Cheng07043272012-02-21 20:46:00 +0000610 if (Subtarget->isTargetELF())
Jason W Kimdef9ac42010-10-06 22:36:46 +0000611 emitAttributes();
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000612}
613
Anton Korobeynikov0f3cc652008-08-07 09:54:23 +0000614
Chris Lattner4a071d62009-10-19 17:59:19 +0000615void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
Evan Cheng5be54b02007-01-19 19:25:36 +0000616 if (Subtarget->isTargetDarwin()) {
Chris Lattnerf61159b2009-08-03 22:18:15 +0000617 // All darwin targets use mach-o.
Dan Gohman0d805c32010-04-17 16:44:48 +0000618 const TargetLoweringObjectFileMachO &TLOFMacho =
619 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000620 MachineModuleInfoMachO &MMIMacho =
621 MMI->getObjFileInfo<MachineModuleInfoMachO>();
Jim Grosbache9952212009-09-04 01:38:51 +0000622
Evan Chenga8e29892007-01-19 07:51:42 +0000623 // Output non-lazy-pointers for external and common global variables.
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000624 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
Bill Wendlingcebae362010-03-10 22:34:10 +0000625
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000626 if (!Stubs.empty()) {
Chris Lattnerff4bc462009-08-10 01:39:42 +0000627 // Switch with ".non_lazy_symbol_pointer" directive.
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000628 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
Chris Lattnerc076a972009-08-10 18:01:34 +0000629 EmitAlignment(2);
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000630 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000631 // L_foo$stub:
632 OutStreamer.EmitLabel(Stubs[i].first);
633 // .indirect_symbol _foo
Bill Wendling52a50e52010-03-11 01:18:13 +0000634 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
635 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000636
Bill Wendling52a50e52010-03-11 01:18:13 +0000637 if (MCSym.getInt())
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000638 // External to current translation unit.
639 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
640 else
641 // Internal to current translation unit.
Bill Wendling5e1b55d2010-03-31 18:47:10 +0000642 //
Jim Grosbach1b935a32010-09-22 16:45:13 +0000643 // When we place the LSDA into the TEXT section, the type info
644 // pointers need to be indirect and pc-rel. We accomplish this by
645 // using NLPs; however, sometimes the types are local to the file.
646 // We need to fill in the value for the NLP in those cases.
Bill Wendling52a50e52010-03-11 01:18:13 +0000647 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
648 OutContext),
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000649 4/*size*/, 0/*addrspace*/);
Evan Chengae94e592008-12-05 01:06:39 +0000650 }
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000651
652 Stubs.clear();
653 OutStreamer.AddBlankLine();
Evan Chenga8e29892007-01-19 07:51:42 +0000654 }
655
Chris Lattnere4d9ea82009-10-19 18:44:38 +0000656 Stubs = MMIMacho.GetHiddenGVStubList();
657 if (!Stubs.empty()) {
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000658 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
Chris Lattnerf3231de2009-08-10 18:02:16 +0000659 EmitAlignment(2);
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000660 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
661 // L_foo$stub:
662 OutStreamer.EmitLabel(Stubs[i].first);
663 // .long _foo
Bill Wendlingcebae362010-03-10 22:34:10 +0000664 OutStreamer.EmitValue(MCSymbolRefExpr::
665 Create(Stubs[i].second.getPointer(),
666 OutContext),
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000667 4/*size*/, 0/*addrspace*/);
668 }
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000669
670 Stubs.clear();
671 OutStreamer.AddBlankLine();
Evan Chengae94e592008-12-05 01:06:39 +0000672 }
673
Evan Chenga8e29892007-01-19 07:51:42 +0000674 // Funny Darwin hack: This flag tells the linker that no global symbols
675 // contain code that falls through to other global symbols (e.g. the obvious
676 // implementation of multiple entry points). If this doesn't occur, the
677 // linker can safely perform dead code stripping. Since LLVM never
678 // generates code that does this, it is always safe to set.
Chris Lattnera5ad93a2010-01-23 06:39:22 +0000679 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
Rafael Espindolab01c4bb2006-07-27 11:38:51 +0000680 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000681}
Anton Korobeynikov0bd89712008-08-17 13:55:10 +0000682
Chris Lattner97f06932009-10-19 20:20:46 +0000683//===----------------------------------------------------------------------===//
Jason W Kimdef9ac42010-10-06 22:36:46 +0000684// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
685// FIXME:
686// The following seem like one-off assembler flags, but they actually need
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000687// to appear in the .ARM.attributes section in ELF.
Jason W Kimdef9ac42010-10-06 22:36:46 +0000688// Instead of subclassing the MCELFStreamer, we do the work here.
689
690void ARMAsmPrinter::emitAttributes() {
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000691
Jason W Kim17b443d2010-10-11 23:01:44 +0000692 emitARMAttributeSection();
693
Renato Golin728ff0d2011-02-28 22:04:27 +0000694 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
695 bool emitFPU = false;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000696 AttributeEmitter *AttrEmitter;
Renato Golin728ff0d2011-02-28 22:04:27 +0000697 if (OutStreamer.hasRawTextSupport()) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000698 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
Renato Golin728ff0d2011-02-28 22:04:27 +0000699 emitFPU = true;
700 } else {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000701 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
702 AttrEmitter = new ObjectAttributeEmitter(O);
703 }
704
705 AttrEmitter->MaybeSwitchVendor("aeabi");
706
Jason W Kimdef9ac42010-10-06 22:36:46 +0000707 std::string CPUString = Subtarget->getCPUString();
Jason W Kimf009a962011-02-07 00:49:53 +0000708
709 if (CPUString == "cortex-a8" ||
710 Subtarget->isCortexA8()) {
Jason W Kimc046d642011-02-07 19:07:11 +0000711 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
Jason W Kimf009a962011-02-07 00:49:53 +0000712 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
713 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
714 ARMBuildAttrs::ApplicationProfile);
715 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
716 ARMBuildAttrs::Allowed);
717 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
718 ARMBuildAttrs::AllowThumb32);
719 // Fixme: figure out when this is emitted.
720 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
721 // ARMBuildAttrs::AllowWMMXv1);
722 //
723
724 /// ADD additional Else-cases here!
Rafael Espindolab8adb8a2011-05-20 20:10:34 +0000725 } else if (CPUString == "xscale") {
726 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
727 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
728 ARMBuildAttrs::Allowed);
729 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
730 ARMBuildAttrs::Allowed);
Jason W Kimf009a962011-02-07 00:49:53 +0000731 } else if (CPUString == "generic") {
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000732 // FIXME: Why these defaults?
733 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
Jason W Kimf009a962011-02-07 00:49:53 +0000734 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
735 ARMBuildAttrs::Allowed);
736 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
737 ARMBuildAttrs::Allowed);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000738 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000739
Renato Goline89a0532011-03-02 21:20:09 +0000740 if (Subtarget->hasNEON() && emitFPU) {
Renato Golin728ff0d2011-02-28 22:04:27 +0000741 /* NEON is not exactly a VFP architecture, but GAS emit one of
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +0000742 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
Evan Chengbee78fe2012-04-11 05:33:07 +0000743 if (Subtarget->hasVFP4())
Jim Grosbachd4f020a2012-04-06 23:43:50 +0000744 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
745 "neon-vfpv4");
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +0000746 else
Sebastian Pop74bebde2012-03-05 17:39:52 +0000747 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
Renato Golin728ff0d2011-02-28 22:04:27 +0000748 /* If emitted for NEON, omit from VFP below, since you can have both
749 * NEON and VFP in build attributes but only one .fpu */
750 emitFPU = false;
751 }
752
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +0000753 /* VFPv4 + .fpu */
754 if (Subtarget->hasVFP4()) {
755 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
756 ARMBuildAttrs::AllowFPv4A);
757 if (emitFPU)
758 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
759
Renato Golin728ff0d2011-02-28 22:04:27 +0000760 /* VFPv3 + .fpu */
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +0000761 } else if (Subtarget->hasVFP3()) {
Renato Golin728ff0d2011-02-28 22:04:27 +0000762 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
763 ARMBuildAttrs::AllowFPv3A);
764 if (emitFPU)
765 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
766
767 /* VFPv2 + .fpu */
768 } else if (Subtarget->hasVFP2()) {
Jason W Kimf009a962011-02-07 00:49:53 +0000769 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
770 ARMBuildAttrs::AllowFPv2);
Renato Golin728ff0d2011-02-28 22:04:27 +0000771 if (emitFPU)
772 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
773 }
774
775 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
Cameron Zwarich375db7f2011-07-07 08:28:52 +0000776 * since NEON can have 1 (allowed) or 2 (MAC operations) */
Renato Golin728ff0d2011-02-28 22:04:27 +0000777 if (Subtarget->hasNEON()) {
778 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
779 ARMBuildAttrs::Allowed);
780 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000781
782 // Signal various FP modes.
Nick Lewycky8a8d4792011-12-02 22:16:29 +0000783 if (!TM.Options.UnsafeFPMath) {
Jason W Kimf009a962011-02-07 00:49:53 +0000784 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
785 ARMBuildAttrs::Allowed);
786 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
787 ARMBuildAttrs::Allowed);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000788 }
789
Nick Lewycky8a8d4792011-12-02 22:16:29 +0000790 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
Jason W Kimf009a962011-02-07 00:49:53 +0000791 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
792 ARMBuildAttrs::Allowed);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000793 else
Jason W Kimf009a962011-02-07 00:49:53 +0000794 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
795 ARMBuildAttrs::AllowIEE754);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000796
Jason W Kimf009a962011-02-07 00:49:53 +0000797 // FIXME: add more flags to ARMBuildAttrs.h
Jason W Kimdef9ac42010-10-06 22:36:46 +0000798 // 8-bytes alignment stuff.
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000799 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
800 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000801
802 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
Nick Lewycky8a8d4792011-12-02 22:16:29 +0000803 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000804 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
805 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000806 }
807 // FIXME: Should we signal R9 usage?
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000808
Jason W Kimf009a962011-02-07 00:49:53 +0000809 if (Subtarget->hasDivide())
810 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000811
812 AttrEmitter->Finish();
813 delete AttrEmitter;
Jason W Kimdef9ac42010-10-06 22:36:46 +0000814}
815
Jason W Kim17b443d2010-10-11 23:01:44 +0000816void ARMAsmPrinter::emitARMAttributeSection() {
817 // <format-version>
818 // [ <section-length> "vendor-name"
819 // [ <file-tag> <size> <attribute>*
820 // | <section-tag> <size> <section-number>* 0 <attribute>*
821 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
822 // ]+
823 // ]*
824
825 if (OutStreamer.hasRawTextSupport())
826 return;
827
828 const ARMElfTargetObjectFile &TLOFELF =
829 static_cast<const ARMElfTargetObjectFile &>
830 (getObjFileLowering());
831
832 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
Jason W Kim17b443d2010-10-11 23:01:44 +0000833
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000834 // Format version
835 OutStreamer.EmitIntValue(0x41, 1);
Jason W Kim17b443d2010-10-11 23:01:44 +0000836}
837
Jason W Kimdef9ac42010-10-06 22:36:46 +0000838//===----------------------------------------------------------------------===//
Chris Lattner97f06932009-10-19 20:20:46 +0000839
Jim Grosbach988ce092010-09-18 00:05:05 +0000840static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
841 unsigned LabelId, MCContext &Ctx) {
842
843 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
844 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
845 return Label;
846}
847
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000848static MCSymbolRefExpr::VariantKind
849getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
850 switch (Modifier) {
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000851 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
852 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
853 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
854 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
855 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
856 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
857 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000858 llvm_unreachable("Invalid ARMCPModifier!");
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000859}
860
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000861MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
862 bool isIndirect = Subtarget->isTargetDarwin() &&
863 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
864 if (!isIndirect)
865 return Mang->getSymbol(GV);
866
867 // FIXME: Remove this when Darwin transition to @GOT like syntax.
868 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
869 MachineModuleInfoMachO &MMIMachO =
870 MMI->getObjFileInfo<MachineModuleInfoMachO>();
871 MachineModuleInfoImpl::StubValueTy &StubSym =
872 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
873 MMIMachO.getGVStubEntry(MCSym);
874 if (StubSym.getPointer() == 0)
875 StubSym = MachineModuleInfoImpl::
876 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
877 return MCSym;
878}
879
Jim Grosbach5df08d82010-11-09 18:45:04 +0000880void ARMAsmPrinter::
881EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
882 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
883
884 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000885
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000886 MCSymbol *MCSym;
Jim Grosbach5df08d82010-11-09 18:45:04 +0000887 if (ACPV->isLSDA()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000888 SmallString<128> Str;
889 raw_svector_ostream OS(Str);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000890 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000891 MCSym = OutContext.GetOrCreateSymbol(OS.str());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000892 } else if (ACPV->isBlockAddress()) {
Bill Wendling5bb77992011-10-01 08:00:54 +0000893 const BlockAddress *BA =
894 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
895 MCSym = GetBlockAddressSymbol(BA);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000896 } else if (ACPV->isGlobalValue()) {
Bill Wendling5bb77992011-10-01 08:00:54 +0000897 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000898 MCSym = GetARMGVSymbol(GV);
Bill Wendlinge00897c2011-09-29 23:50:42 +0000899 } else if (ACPV->isMachineBasicBlock()) {
Bill Wendling3320f2a2011-10-01 09:30:42 +0000900 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
Bill Wendlinge00897c2011-09-29 23:50:42 +0000901 MCSym = MBB->getSymbol();
Jim Grosbach5df08d82010-11-09 18:45:04 +0000902 } else {
903 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
Bill Wendlingfe31e672011-10-01 08:58:29 +0000904 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
905 MCSym = GetExternalSymbolSymbol(Sym);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000906 }
907
908 // Create an MCSymbol for the reference.
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000909 const MCExpr *Expr =
910 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
911 OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000912
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000913 if (ACPV->getPCAdjustment()) {
914 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
915 getFunctionNumber(),
916 ACPV->getLabelId(),
917 OutContext);
918 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
919 PCRelExpr =
920 MCBinaryExpr::CreateAdd(PCRelExpr,
921 MCConstantExpr::Create(ACPV->getPCAdjustment(),
922 OutContext),
923 OutContext);
924 if (ACPV->mustAddCurrentAddress()) {
925 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
926 // label, so just emit a local label end reference that instead.
927 MCSymbol *DotSym = OutContext.CreateTempSymbol();
928 OutStreamer.EmitLabel(DotSym);
929 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
930 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000931 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000932 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000933 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000934 OutStreamer.EmitValue(Expr, Size);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000935}
936
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000937void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
938 unsigned Opcode = MI->getOpcode();
939 int OpNum = 1;
940 if (Opcode == ARM::BR_JTadd)
941 OpNum = 2;
942 else if (Opcode == ARM::BR_JTm)
943 OpNum = 3;
944
945 const MachineOperand &MO1 = MI->getOperand(OpNum);
946 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
947 unsigned JTI = MO1.getIndex();
948
949 // Emit a label for the jump table.
950 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
951 OutStreamer.EmitLabel(JTISymbol);
952
Jim Grosbach3e965312012-05-18 19:12:01 +0000953 // Mark the jump table as data-in-code.
954 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
955
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000956 // Emit each entry of the table.
957 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
958 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
959 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
960
961 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
962 MachineBasicBlock *MBB = JTBBs[i];
963 // Construct an MCExpr for the entry. We want a value of the form:
964 // (BasicBlockAddr - TableBeginAddr)
965 //
966 // For example, a table with entries jumping to basic blocks BB0 and BB1
967 // would look like:
968 // LJTI_0_0:
969 // .word (LBB0 - LJTI_0_0)
970 // .word (LBB1 - LJTI_0_0)
971 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
972
973 if (TM.getRelocationModel() == Reloc::PIC_)
974 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
975 OutContext),
976 OutContext);
Jim Grosbachde982732011-08-31 22:23:09 +0000977 // If we're generating a table of Thumb addresses in static relocation
978 // model, we need to add one to keep interworking correctly.
979 else if (AFI->isThumbFunction())
980 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
981 OutContext);
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000982 OutStreamer.EmitValue(Expr, 4);
983 }
Jim Grosbach3e965312012-05-18 19:12:01 +0000984 // Mark the end of jump table data-in-code region.
985 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000986}
987
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000988void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
989 unsigned Opcode = MI->getOpcode();
990 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
991 const MachineOperand &MO1 = MI->getOperand(OpNum);
992 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
993 unsigned JTI = MO1.getIndex();
994
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000995 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
996 OutStreamer.EmitLabel(JTISymbol);
997
998 // Emit each entry of the table.
999 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1000 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1001 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
Jim Grosbach205a5fa2010-09-22 17:15:35 +00001002 unsigned OffsetWidth = 4;
Jim Grosbach3e965312012-05-18 19:12:01 +00001003 if (MI->getOpcode() == ARM::t2TBB_JT) {
Jim Grosbach205a5fa2010-09-22 17:15:35 +00001004 OffsetWidth = 1;
Jim Grosbach3e965312012-05-18 19:12:01 +00001005 // Mark the jump table as data-in-code.
1006 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1007 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
Jim Grosbach205a5fa2010-09-22 17:15:35 +00001008 OffsetWidth = 2;
Jim Grosbach3e965312012-05-18 19:12:01 +00001009 // Mark the jump table as data-in-code.
1010 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1011 }
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001012
1013 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1014 MachineBasicBlock *MBB = JTBBs[i];
Jim Grosbach205a5fa2010-09-22 17:15:35 +00001015 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1016 OutContext);
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001017 // If this isn't a TBB or TBH, the entries are direct branch instructions.
Jim Grosbach205a5fa2010-09-22 17:15:35 +00001018 if (OffsetWidth == 4) {
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001019 MCInst BrInst;
1020 BrInst.setOpcode(ARM::t2B);
Jim Grosbach205a5fa2010-09-22 17:15:35 +00001021 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
Owen Anderson51f6a7a2011-09-09 21:48:23 +00001022 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1023 BrInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001024 OutStreamer.EmitInstruction(BrInst);
1025 continue;
1026 }
1027 // Otherwise it's an offset from the dispatch instruction. Construct an
Jim Grosbach205a5fa2010-09-22 17:15:35 +00001028 // MCExpr for the entry. We want a value of the form:
1029 // (BasicBlockAddr - TableBeginAddr) / 2
1030 //
1031 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1032 // would look like:
1033 // LJTI_0_0:
1034 // .byte (LBB0 - LJTI_0_0) / 2
1035 // .byte (LBB1 - LJTI_0_0) / 2
1036 const MCExpr *Expr =
1037 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1038 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1039 OutContext);
1040 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1041 OutContext);
1042 OutStreamer.EmitValue(Expr, OffsetWidth);
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001043 }
Jim Grosbachb3a119a2012-05-21 23:34:42 +00001044 // Mark the end of jump table data-in-code region. 32-bit offsets use
1045 // actual branch instructions here, so we don't mark those as a data-region
1046 // at all.
1047 if (OffsetWidth != 4)
1048 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001049}
1050
Jim Grosbach2d0f53b2010-09-28 17:05:56 +00001051void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1052 raw_ostream &OS) {
1053 unsigned NOps = MI->getNumOperands();
1054 assert(NOps==4);
1055 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1056 // cast away const; DIetc do not take const operands for some reason.
1057 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1058 OS << V.getName();
1059 OS << " <- ";
1060 // Frame address. Currently handles register +- offset only.
1061 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1062 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1063 OS << ']';
1064 OS << "+";
1065 printOperand(MI, NOps-2, OS);
1066}
1067
Jim Grosbach40edf732010-12-14 21:10:47 +00001068static void populateADROperands(MCInst &Inst, unsigned Dest,
1069 const MCSymbol *Label,
1070 unsigned pred, unsigned ccreg,
1071 MCContext &Ctx) {
1072 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1073 Inst.addOperand(MCOperand::CreateReg(Dest));
1074 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1075 // Add predicate operands.
1076 Inst.addOperand(MCOperand::CreateImm(pred));
1077 Inst.addOperand(MCOperand::CreateReg(ccreg));
1078}
1079
Anton Korobeynikov4d728602011-01-01 20:38:38 +00001080void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1081 unsigned Opcode) {
1082 MCInst TmpInst;
1083
1084 // Emit the instruction as usual, just patch the opcode.
1085 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1086 TmpInst.setOpcode(Opcode);
1087 OutStreamer.EmitInstruction(TmpInst);
1088}
1089
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001090void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1091 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1092 "Only instruction which are involved into frame setup code are allowed");
1093
1094 const MachineFunction &MF = *MI->getParent()->getParent();
1095 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
Anton Korobeynikovb3fcc062011-03-05 18:43:55 +00001096 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001097
1098 unsigned FramePtr = RegInfo->getFrameRegister(MF);
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001099 unsigned Opc = MI->getOpcode();
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001100 unsigned SrcReg, DstReg;
1101
Anton Korobeynikov3daccd82011-03-05 18:43:50 +00001102 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1103 // Two special cases:
1104 // 1) tPUSH does not have src/dst regs.
1105 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1106 // load. Yes, this is pretty fragile, but for now I don't see better
1107 // way... :(
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001108 SrcReg = DstReg = ARM::SP;
1109 } else {
Anton Korobeynikov3daccd82011-03-05 18:43:50 +00001110 SrcReg = MI->getOperand(1).getReg();
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001111 DstReg = MI->getOperand(0).getReg();
1112 }
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001113
1114 // Try to figure out the unwinding opcode out of src / dst regs.
Evan Cheng5a96b3d2011-12-07 07:15:52 +00001115 if (MI->mayStore()) {
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001116 // Register saves.
1117 assert(DstReg == ARM::SP &&
1118 "Only stack pointer as a destination reg is supported");
1119
1120 SmallVector<unsigned, 4> RegList;
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001121 // Skip src & dst reg, and pred ops.
1122 unsigned StartOp = 2 + 2;
1123 // Use all the operands.
1124 unsigned NumOffset = 0;
1125
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001126 switch (Opc) {
1127 default:
1128 MI->dump();
Craig Topperbc219812012-02-07 02:50:20 +00001129 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001130 case ARM::tPUSH:
1131 // Special case here: no src & dst reg, but two extra imp ops.
1132 StartOp = 2; NumOffset = 2;
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001133 case ARM::STMDB_UPD:
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001134 case ARM::t2STMDB_UPD:
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001135 case ARM::VSTMDDB_UPD:
1136 assert(SrcReg == ARM::SP &&
1137 "Only stack pointer as a source reg is supported");
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001138 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1139 i != NumOps; ++i)
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001140 RegList.push_back(MI->getOperand(i).getReg());
1141 break;
Owen Anderson793e7962011-07-26 20:54:26 +00001142 case ARM::STR_PRE_IMM:
1143 case ARM::STR_PRE_REG:
Evgeniy Stepanov73dd8bb2012-01-19 12:53:06 +00001144 case ARM::t2STR_PRE:
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001145 assert(MI->getOperand(2).getReg() == ARM::SP &&
1146 "Only stack pointer as a source reg is supported");
1147 RegList.push_back(SrcReg);
1148 break;
1149 }
1150 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1151 } else {
1152 // Changes of stack / frame pointer.
1153 if (SrcReg == ARM::SP) {
1154 int64_t Offset = 0;
1155 switch (Opc) {
1156 default:
1157 MI->dump();
Craig Topperbc219812012-02-07 02:50:20 +00001158 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001159 case ARM::MOVr:
Evgeniy Stepanov73dd8bb2012-01-19 12:53:06 +00001160 case ARM::tMOVr:
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001161 Offset = 0;
1162 break;
1163 case ARM::ADDri:
1164 Offset = -MI->getOperand(2).getImm();
1165 break;
1166 case ARM::SUBri:
Evgeniy Stepanov73dd8bb2012-01-19 12:53:06 +00001167 case ARM::t2SUBri:
Jim Grosbachf6fd9092011-06-29 23:25:04 +00001168 Offset = MI->getOperand(2).getImm();
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001169 break;
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001170 case ARM::tSUBspi:
Jim Grosbachf6fd9092011-06-29 23:25:04 +00001171 Offset = MI->getOperand(2).getImm()*4;
Anton Korobeynikov7a764162011-03-05 18:43:43 +00001172 break;
1173 case ARM::tADDspi:
1174 case ARM::tADDrSPi:
1175 Offset = -MI->getOperand(2).getImm()*4;
1176 break;
Anton Korobeynikovb3fcc062011-03-05 18:43:55 +00001177 case ARM::tLDRpci: {
1178 // Grab the constpool index and check, whether it corresponds to
1179 // original or cloned constpool entry.
1180 unsigned CPI = MI->getOperand(1).getIndex();
1181 const MachineConstantPool *MCP = MF.getConstantPool();
1182 if (CPI >= MCP->getConstants().size())
1183 CPI = AFI.getOriginalCPIdx(CPI);
1184 assert(CPI != -1U && "Invalid constpool index");
1185
1186 // Derive the actual offset.
1187 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1188 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1189 // FIXME: Check for user, it should be "add" instruction!
1190 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
Anton Korobeynikov3daccd82011-03-05 18:43:50 +00001191 break;
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001192 }
Anton Korobeynikovb3fcc062011-03-05 18:43:55 +00001193 }
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001194
1195 if (DstReg == FramePtr && FramePtr != ARM::SP)
Anton Korobeynikove5163792011-03-05 18:44:00 +00001196 // Set-up of the frame pointer. Positive values correspond to "add"
1197 // instruction.
1198 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001199 else if (DstReg == ARM::SP) {
Anton Korobeynikove5163792011-03-05 18:44:00 +00001200 // Change of SP by an offset. Positive values correspond to "sub"
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001201 // instruction.
1202 OutStreamer.EmitPad(Offset);
1203 } else {
1204 MI->dump();
Craig Topperbc219812012-02-07 02:50:20 +00001205 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001206 }
1207 } else if (DstReg == ARM::SP) {
1208 // FIXME: .movsp goes here
1209 MI->dump();
Craig Topperbc219812012-02-07 02:50:20 +00001210 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001211 }
1212 else {
1213 MI->dump();
Craig Topperbc219812012-02-07 02:50:20 +00001214 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001215 }
1216 }
1217}
1218
Chandler Carruth3eb4be02012-01-24 00:30:17 +00001219extern cl::opt<bool> EnableARMEHABI;
Anton Korobeynikov57caad72011-03-05 18:43:32 +00001220
Jim Grosbach53e3fc42011-07-08 17:40:42 +00001221// Simple pseudo-instructions have their lowering (with expansion to real
1222// instructions) auto-generated.
1223#include "ARMGenMCPseudoLowering.inc"
1224
Jim Grosbachb454cda2010-09-29 15:23:40 +00001225void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
Jim Grosbach3e965312012-05-18 19:12:01 +00001226 // If we just ended a constant pool, mark it as such.
1227 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1228 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1229 InConstantPool = false;
1230 }
Owen Anderson2fec6c52011-10-04 23:26:17 +00001231
Jim Grosbach5aa29a02011-08-23 21:32:34 +00001232 // Emit unwinding stuff for frame-related instructions
Chandler Carruth3eb4be02012-01-24 00:30:17 +00001233 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
Jim Grosbach5aa29a02011-08-23 21:32:34 +00001234 EmitUnwindingInstruction(MI);
1235
Jim Grosbach53e3fc42011-07-08 17:40:42 +00001236 // Do any auto-generated pseudo lowerings.
1237 if (emitPseudoExpansionLowering(OutStreamer, MI))
1238 return;
1239
Andrew Trick3be654f2011-09-21 02:20:46 +00001240 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1241 "Pseudo flag setting opcode should be expanded early");
1242
Jim Grosbach53e3fc42011-07-08 17:40:42 +00001243 // Check for manual lowerings.
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001244 unsigned Opc = MI->getOpcode();
1245 switch (Opc) {
Craig Topperbc219812012-02-07 02:50:20 +00001246 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
Jim Grosbach2d0f53b2010-09-28 17:05:56 +00001247 case ARM::DBG_VALUE: {
1248 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1249 SmallString<128> TmpStr;
1250 raw_svector_ostream OS(TmpStr);
1251 PrintDebugValueComment(MI, OS);
1252 OutStreamer.EmitRawText(StringRef(OS.str()));
1253 }
1254 return;
1255 }
Jim Grosbach40edf732010-12-14 21:10:47 +00001256 case ARM::LEApcrel:
Jim Grosbachd40963c2010-12-14 22:28:03 +00001257 case ARM::tLEApcrel:
Jim Grosbach40edf732010-12-14 21:10:47 +00001258 case ARM::t2LEApcrel: {
Jim Grosbachdff84b02010-12-02 00:28:45 +00001259 // FIXME: Need to also handle globals and externals
Jim Grosbachdff84b02010-12-02 00:28:45 +00001260 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +00001261 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1262 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1263 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +00001264 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1265 GetCPISymbol(MI->getOperand(1).getIndex()),
1266 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1267 OutContext);
Jim Grosbachdff84b02010-12-02 00:28:45 +00001268 OutStreamer.EmitInstruction(TmpInst);
1269 return;
1270 }
Jim Grosbachd40963c2010-12-14 22:28:03 +00001271 case ARM::LEApcrelJT:
1272 case ARM::tLEApcrelJT:
1273 case ARM::t2LEApcrelJT: {
Jim Grosbach5d14f9b2010-12-01 19:47:31 +00001274 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +00001275 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1276 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1277 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +00001278 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1279 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1280 MI->getOperand(2).getImm()),
1281 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1282 OutContext);
Jim Grosbach5d14f9b2010-12-01 19:47:31 +00001283 OutStreamer.EmitInstruction(TmpInst);
1284 return;
1285 }
Jim Grosbachf859a542011-03-12 00:45:26 +00001286 // Darwin call instructions are just normal call instructions with different
1287 // clobber semantics (they clobber R9).
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001288 case ARM::BX_CALL: {
1289 {
1290 MCInst TmpInst;
1291 TmpInst.setOpcode(ARM::MOVr);
1292 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1293 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1294 // Add predicate operands.
1295 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1296 TmpInst.addOperand(MCOperand::CreateReg(0));
1297 // Add 's' bit operand (always reg0 for this)
1298 TmpInst.addOperand(MCOperand::CreateReg(0));
1299 OutStreamer.EmitInstruction(TmpInst);
1300 }
1301 {
1302 MCInst TmpInst;
1303 TmpInst.setOpcode(ARM::BX);
1304 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1305 OutStreamer.EmitInstruction(TmpInst);
1306 }
1307 return;
1308 }
Cameron Zwarichad70f6d2011-05-25 21:53:50 +00001309 case ARM::tBX_CALL: {
1310 {
1311 MCInst TmpInst;
1312 TmpInst.setOpcode(ARM::tMOVr);
1313 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1314 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
Jim Grosbach63b46fa2011-06-30 22:10:46 +00001315 // Add predicate operands.
1316 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1317 TmpInst.addOperand(MCOperand::CreateReg(0));
Cameron Zwarichad70f6d2011-05-25 21:53:50 +00001318 OutStreamer.EmitInstruction(TmpInst);
1319 }
1320 {
1321 MCInst TmpInst;
1322 TmpInst.setOpcode(ARM::tBX);
1323 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1324 // Add predicate operands.
1325 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1326 TmpInst.addOperand(MCOperand::CreateReg(0));
1327 OutStreamer.EmitInstruction(TmpInst);
1328 }
1329 return;
1330 }
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001331 case ARM::BMOVPCRX_CALL: {
1332 {
1333 MCInst TmpInst;
1334 TmpInst.setOpcode(ARM::MOVr);
1335 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1336 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1337 // Add predicate operands.
1338 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1339 TmpInst.addOperand(MCOperand::CreateReg(0));
1340 // Add 's' bit operand (always reg0 for this)
1341 TmpInst.addOperand(MCOperand::CreateReg(0));
1342 OutStreamer.EmitInstruction(TmpInst);
1343 }
1344 {
1345 MCInst TmpInst;
1346 TmpInst.setOpcode(ARM::MOVr);
1347 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1348 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1349 // Add predicate operands.
1350 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1351 TmpInst.addOperand(MCOperand::CreateReg(0));
1352 // Add 's' bit operand (always reg0 for this)
1353 TmpInst.addOperand(MCOperand::CreateReg(0));
1354 OutStreamer.EmitInstruction(TmpInst);
1355 }
1356 return;
1357 }
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001358 case ARM::BMOVPCB_CALL: {
1359 {
1360 MCInst TmpInst;
1361 TmpInst.setOpcode(ARM::MOVr);
1362 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1363 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1364 // Add predicate operands.
1365 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1366 TmpInst.addOperand(MCOperand::CreateReg(0));
1367 // Add 's' bit operand (always reg0 for this)
1368 TmpInst.addOperand(MCOperand::CreateReg(0));
1369 OutStreamer.EmitInstruction(TmpInst);
1370 }
1371 {
1372 MCInst TmpInst;
1373 TmpInst.setOpcode(ARM::Bcc);
1374 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1375 MCSymbol *GVSym = Mang->getSymbol(GV);
1376 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1377 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1378 // Add predicate operands.
1379 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1380 TmpInst.addOperand(MCOperand::CreateReg(0));
1381 OutStreamer.EmitInstruction(TmpInst);
1382 }
1383 return;
1384 }
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001385 case ARM::t2BMOVPCB_CALL: {
1386 {
1387 MCInst TmpInst;
1388 TmpInst.setOpcode(ARM::tMOVr);
1389 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1390 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1391 // Add predicate operands.
1392 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1393 TmpInst.addOperand(MCOperand::CreateReg(0));
1394 OutStreamer.EmitInstruction(TmpInst);
1395 }
1396 {
1397 MCInst TmpInst;
1398 TmpInst.setOpcode(ARM::t2B);
1399 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1400 MCSymbol *GVSym = Mang->getSymbol(GV);
1401 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1402 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1403 // Add predicate operands.
1404 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1405 TmpInst.addOperand(MCOperand::CreateReg(0));
1406 OutStreamer.EmitInstruction(TmpInst);
1407 }
1408 return;
1409 }
Evan Cheng53519f02011-01-21 18:55:51 +00001410 case ARM::MOVi16_ga_pcrel:
1411 case ARM::t2MOVi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001412 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +00001413 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001414 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1415
Evan Cheng53519f02011-01-21 18:55:51 +00001416 unsigned TF = MI->getOperand(1).getTargetFlags();
1417 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001418 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1419 MCSymbol *GVSym = GetARMGVSymbol(GV);
1420 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001421 if (isPIC) {
1422 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1423 getFunctionNumber(),
1424 MI->getOperand(2).getImm(), OutContext);
1425 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1426 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1427 const MCExpr *PCRelExpr =
1428 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1429 MCBinaryExpr::CreateAdd(LabelSymExpr,
1430 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001431 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001432 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1433 } else {
1434 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1435 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1436 }
1437
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001438 // Add predicate operands.
1439 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1440 TmpInst.addOperand(MCOperand::CreateReg(0));
1441 // Add 's' bit operand (always reg0 for this)
1442 TmpInst.addOperand(MCOperand::CreateReg(0));
1443 OutStreamer.EmitInstruction(TmpInst);
1444 return;
1445 }
Evan Cheng53519f02011-01-21 18:55:51 +00001446 case ARM::MOVTi16_ga_pcrel:
1447 case ARM::t2MOVTi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001448 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +00001449 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1450 ? ARM::MOVTi16 : ARM::t2MOVTi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001451 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1452 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1453
Evan Cheng53519f02011-01-21 18:55:51 +00001454 unsigned TF = MI->getOperand(2).getTargetFlags();
1455 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001456 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1457 MCSymbol *GVSym = GetARMGVSymbol(GV);
1458 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001459 if (isPIC) {
1460 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1461 getFunctionNumber(),
1462 MI->getOperand(3).getImm(), OutContext);
1463 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1464 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1465 const MCExpr *PCRelExpr =
1466 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1467 MCBinaryExpr::CreateAdd(LabelSymExpr,
1468 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001469 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +00001470 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1471 } else {
1472 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1473 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1474 }
Evan Cheng5de5d4b2011-01-17 08:03:18 +00001475 // Add predicate operands.
1476 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1477 TmpInst.addOperand(MCOperand::CreateReg(0));
1478 // Add 's' bit operand (always reg0 for this)
1479 TmpInst.addOperand(MCOperand::CreateReg(0));
1480 OutStreamer.EmitInstruction(TmpInst);
1481 return;
1482 }
Jim Grosbachfbd18732010-09-17 23:41:53 +00001483 case ARM::tPICADD: {
1484 // This is a pseudo op for a label + instruction sequence, which looks like:
1485 // LPC0:
1486 // add r0, pc
1487 // This adds the address of LPC0 to r0.
1488
1489 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001490 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1491 getFunctionNumber(), MI->getOperand(2).getImm(),
1492 OutContext));
Jim Grosbachfbd18732010-09-17 23:41:53 +00001493
1494 // Form and emit the add.
1495 MCInst AddInst;
1496 AddInst.setOpcode(ARM::tADDhirr);
1497 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1498 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1499 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1500 // Add predicate operands.
1501 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1502 AddInst.addOperand(MCOperand::CreateReg(0));
1503 OutStreamer.EmitInstruction(AddInst);
1504 return;
1505 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001506 case ARM::PICADD: {
Chris Lattner4d152222009-10-19 22:23:04 +00001507 // This is a pseudo op for a label + instruction sequence, which looks like:
1508 // LPC0:
1509 // add r0, pc, r0
1510 // This adds the address of LPC0 to r0.
Jim Grosbachb0739b72010-09-02 01:02:06 +00001511
Chris Lattner4d152222009-10-19 22:23:04 +00001512 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001513 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1514 getFunctionNumber(), MI->getOperand(2).getImm(),
1515 OutContext));
Jim Grosbachb0739b72010-09-02 01:02:06 +00001516
Jim Grosbachf3f09522010-09-14 21:05:34 +00001517 // Form and emit the add.
Chris Lattner4d152222009-10-19 22:23:04 +00001518 MCInst AddInst;
1519 AddInst.setOpcode(ARM::ADDrr);
1520 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1521 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1522 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbach5b46d622010-09-14 21:28:17 +00001523 // Add predicate operands.
1524 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1525 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1526 // Add 's' bit operand (always reg0 for this)
1527 AddInst.addOperand(MCOperand::CreateReg(0));
Chris Lattner850d2e22010-02-03 01:16:28 +00001528 OutStreamer.EmitInstruction(AddInst);
Chris Lattner4d152222009-10-19 22:23:04 +00001529 return;
1530 }
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001531 case ARM::PICSTR:
1532 case ARM::PICSTRB:
1533 case ARM::PICSTRH:
1534 case ARM::PICLDR:
1535 case ARM::PICLDRB:
1536 case ARM::PICLDRH:
1537 case ARM::PICLDRSB:
1538 case ARM::PICLDRSH: {
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001539 // This is a pseudo op for a label + instruction sequence, which looks like:
1540 // LPC0:
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001541 // OP r0, [pc, r0]
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001542 // The LCP0 label is referenced by a constant pool entry in order to get
1543 // a PC-relative address at the ldr instruction.
1544
1545 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001546 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1547 getFunctionNumber(), MI->getOperand(2).getImm(),
1548 OutContext));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001549
1550 // Form and emit the load
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001551 unsigned Opcode;
1552 switch (MI->getOpcode()) {
1553 default:
1554 llvm_unreachable("Unexpected opcode!");
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001555 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1556 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001557 case ARM::PICSTRH: Opcode = ARM::STRH; break;
Jim Grosbach3e556122010-10-26 22:37:02 +00001558 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
Jim Grosbachc1d30212010-10-27 00:19:44 +00001559 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001560 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1561 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1562 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1563 }
1564 MCInst LdStInst;
1565 LdStInst.setOpcode(Opcode);
1566 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1567 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1568 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1569 LdStInst.addOperand(MCOperand::CreateImm(0));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001570 // Add predicate operands.
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001571 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1572 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1573 OutStreamer.EmitInstruction(LdStInst);
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001574
1575 return;
1576 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001577 case ARM::CONSTPOOL_ENTRY: {
Chris Lattnera70e6442009-10-19 22:33:05 +00001578 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1579 /// in the function. The first operand is the ID# for this instruction, the
1580 /// second is the index into the MachineConstantPool that this is, the third
1581 /// is the size in bytes of this constant pool entry.
Jakob Stoklund Olesen3e572ac2011-12-06 01:43:02 +00001582 /// The required alignment is specified on the basic block holding this MI.
Chris Lattnera70e6442009-10-19 22:33:05 +00001583 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1584 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1585
Jim Grosbach3e965312012-05-18 19:12:01 +00001586 // If this is the first entry of the pool, mark it.
1587 if (!InConstantPool) {
1588 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1589 InConstantPool = true;
1590 }
1591
Chris Lattner1b46f432010-01-23 07:00:21 +00001592 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
Chris Lattnera70e6442009-10-19 22:33:05 +00001593
1594 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1595 if (MCPE.isMachineConstantPoolEntry())
1596 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1597 else
1598 EmitGlobalConstant(MCPE.Val.ConstVal);
Chris Lattnera70e6442009-10-19 22:33:05 +00001599 return;
1600 }
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001601 case ARM::t2BR_JT: {
1602 // Lower and emit the instruction itself, then the jump table following it.
1603 MCInst TmpInst;
Jim Grosbach2a7b41b2011-06-30 23:38:17 +00001604 TmpInst.setOpcode(ARM::tMOVr);
Jim Grosbach5ca66692010-11-29 22:37:40 +00001605 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1606 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1607 // Add predicate operands.
1608 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1609 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001610 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbach5ca66692010-11-29 22:37:40 +00001611 // Output the data for the jump table itself
1612 EmitJump2Table(MI);
1613 return;
1614 }
1615 case ARM::t2TBB_JT: {
1616 // Lower and emit the instruction itself, then the jump table following it.
1617 MCInst TmpInst;
1618
1619 TmpInst.setOpcode(ARM::t2TBB);
1620 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1621 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1622 // Add predicate operands.
1623 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1624 TmpInst.addOperand(MCOperand::CreateReg(0));
1625 OutStreamer.EmitInstruction(TmpInst);
1626 // Output the data for the jump table itself
1627 EmitJump2Table(MI);
1628 // Make sure the next instruction is 2-byte aligned.
1629 EmitAlignment(1);
1630 return;
1631 }
1632 case ARM::t2TBH_JT: {
1633 // Lower and emit the instruction itself, then the jump table following it.
1634 MCInst TmpInst;
1635
1636 TmpInst.setOpcode(ARM::t2TBH);
1637 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1638 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1639 // Add predicate operands.
1640 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1641 TmpInst.addOperand(MCOperand::CreateReg(0));
1642 OutStreamer.EmitInstruction(TmpInst);
1643 // Output the data for the jump table itself
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001644 EmitJump2Table(MI);
1645 return;
1646 }
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001647 case ARM::tBR_JTr:
Jim Grosbach2dc77682010-11-29 18:37:44 +00001648 case ARM::BR_JTr: {
1649 // Lower and emit the instruction itself, then the jump table following it.
1650 // mov pc, target
1651 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001652 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
Jim Grosbach2a7b41b2011-06-30 23:38:17 +00001653 ARM::MOVr : ARM::tMOVr;
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001654 TmpInst.setOpcode(Opc);
Jim Grosbach2dc77682010-11-29 18:37:44 +00001655 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1656 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1657 // Add predicate operands.
1658 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1659 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001660 // Add 's' bit operand (always reg0 for this)
1661 if (Opc == ARM::MOVr)
1662 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach2dc77682010-11-29 18:37:44 +00001663 OutStreamer.EmitInstruction(TmpInst);
1664
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001665 // Make sure the Thumb jump table is 4-byte aligned.
Jim Grosbach2a7b41b2011-06-30 23:38:17 +00001666 if (Opc == ARM::tMOVr)
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001667 EmitAlignment(2);
1668
Jim Grosbach2dc77682010-11-29 18:37:44 +00001669 // Output the data for the jump table itself
1670 EmitJumpTable(MI);
1671 return;
1672 }
1673 case ARM::BR_JTm: {
1674 // Lower and emit the instruction itself, then the jump table following it.
1675 // ldr pc, target
1676 MCInst TmpInst;
1677 if (MI->getOperand(1).getReg() == 0) {
1678 // literal offset
1679 TmpInst.setOpcode(ARM::LDRi12);
1680 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1681 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1682 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1683 } else {
1684 TmpInst.setOpcode(ARM::LDRrs);
1685 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1686 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1687 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1688 TmpInst.addOperand(MCOperand::CreateImm(0));
1689 }
1690 // Add predicate operands.
1691 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1692 TmpInst.addOperand(MCOperand::CreateReg(0));
1693 OutStreamer.EmitInstruction(TmpInst);
1694
1695 // Output the data for the jump table itself
Jim Grosbacha2244cb2010-09-22 17:39:48 +00001696 EmitJumpTable(MI);
1697 return;
1698 }
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001699 case ARM::BR_JTadd: {
1700 // Lower and emit the instruction itself, then the jump table following it.
1701 // add pc, target, idx
Jim Grosbach2dc77682010-11-29 18:37:44 +00001702 MCInst TmpInst;
1703 TmpInst.setOpcode(ARM::ADDrr);
1704 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1705 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1706 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001707 // Add predicate operands.
Jim Grosbach2dc77682010-11-29 18:37:44 +00001708 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1709 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001710 // Add 's' bit operand (always reg0 for this)
Jim Grosbach2dc77682010-11-29 18:37:44 +00001711 TmpInst.addOperand(MCOperand::CreateReg(0));
1712 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001713
1714 // Output the data for the jump table itself
1715 EmitJumpTable(MI);
1716 return;
1717 }
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001718 case ARM::TRAP: {
1719 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1720 // FIXME: Remove this special case when they do.
1721 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001722 //.long 0xe7ffdefe @ trap
Jim Grosbachb2dda4b2010-09-23 19:42:17 +00001723 uint32_t Val = 0xe7ffdefeUL;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001724 OutStreamer.AddComment("trap");
1725 OutStreamer.EmitIntValue(Val, 4);
1726 return;
1727 }
1728 break;
1729 }
1730 case ARM::tTRAP: {
1731 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1732 // FIXME: Remove this special case when they do.
1733 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001734 //.short 57086 @ trap
Benjamin Kramerc8ab9eb2010-09-23 18:57:26 +00001735 uint16_t Val = 0xdefe;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001736 OutStreamer.AddComment("trap");
1737 OutStreamer.EmitIntValue(Val, 2);
1738 return;
1739 }
1740 break;
1741 }
Jim Grosbach433a5782010-09-24 20:47:58 +00001742 case ARM::t2Int_eh_sjlj_setjmp:
1743 case ARM::t2Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001744 case ARM::tInt_eh_sjlj_setjmp: {
Jim Grosbach433a5782010-09-24 20:47:58 +00001745 // Two incoming args: GPR:$src, GPR:$val
1746 // mov $val, pc
1747 // adds $val, #7
1748 // str $val, [$src, #4]
1749 // movs r0, #0
1750 // b 1f
1751 // movs r0, #1
1752 // 1:
1753 unsigned SrcReg = MI->getOperand(0).getReg();
1754 unsigned ValReg = MI->getOperand(1).getReg();
1755 MCSymbol *Label = GetARMSJLJEHLabel();
1756 {
1757 MCInst TmpInst;
Jim Grosbach2a7b41b2011-06-30 23:38:17 +00001758 TmpInst.setOpcode(ARM::tMOVr);
Jim Grosbach433a5782010-09-24 20:47:58 +00001759 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1760 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
Jim Grosbach63b46fa2011-06-30 22:10:46 +00001761 // Predicate.
1762 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1763 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach433a5782010-09-24 20:47:58 +00001764 OutStreamer.AddComment("eh_setjmp begin");
1765 OutStreamer.EmitInstruction(TmpInst);
1766 }
1767 {
1768 MCInst TmpInst;
1769 TmpInst.setOpcode(ARM::tADDi3);
1770 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1771 // 's' bit operand
1772 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1773 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1774 TmpInst.addOperand(MCOperand::CreateImm(7));
1775 // Predicate.
1776 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1777 TmpInst.addOperand(MCOperand::CreateReg(0));
1778 OutStreamer.EmitInstruction(TmpInst);
1779 }
1780 {
1781 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001782 TmpInst.setOpcode(ARM::tSTRi);
Jim Grosbach433a5782010-09-24 20:47:58 +00001783 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1784 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1785 // The offset immediate is #4. The operand value is scaled by 4 for the
1786 // tSTR instruction.
1787 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach433a5782010-09-24 20:47:58 +00001788 // Predicate.
1789 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1790 TmpInst.addOperand(MCOperand::CreateReg(0));
1791 OutStreamer.EmitInstruction(TmpInst);
1792 }
1793 {
1794 MCInst TmpInst;
1795 TmpInst.setOpcode(ARM::tMOVi8);
1796 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1797 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1798 TmpInst.addOperand(MCOperand::CreateImm(0));
1799 // Predicate.
1800 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1801 TmpInst.addOperand(MCOperand::CreateReg(0));
1802 OutStreamer.EmitInstruction(TmpInst);
1803 }
1804 {
1805 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1806 MCInst TmpInst;
1807 TmpInst.setOpcode(ARM::tB);
1808 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
Owen Anderson51f6a7a2011-09-09 21:48:23 +00001809 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1810 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach433a5782010-09-24 20:47:58 +00001811 OutStreamer.EmitInstruction(TmpInst);
1812 }
1813 {
1814 MCInst TmpInst;
1815 TmpInst.setOpcode(ARM::tMOVi8);
1816 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1817 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1818 TmpInst.addOperand(MCOperand::CreateImm(1));
1819 // Predicate.
1820 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1821 TmpInst.addOperand(MCOperand::CreateReg(0));
1822 OutStreamer.AddComment("eh_setjmp end");
1823 OutStreamer.EmitInstruction(TmpInst);
1824 }
1825 OutStreamer.EmitLabel(Label);
1826 return;
1827 }
1828
Jim Grosbach45390082010-09-23 23:33:56 +00001829 case ARM::Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001830 case ARM::Int_eh_sjlj_setjmp: {
Jim Grosbach45390082010-09-23 23:33:56 +00001831 // Two incoming args: GPR:$src, GPR:$val
1832 // add $val, pc, #8
1833 // str $val, [$src, #+4]
1834 // mov r0, #0
1835 // add pc, pc, #0
1836 // mov r0, #1
1837 unsigned SrcReg = MI->getOperand(0).getReg();
1838 unsigned ValReg = MI->getOperand(1).getReg();
1839
1840 {
1841 MCInst TmpInst;
1842 TmpInst.setOpcode(ARM::ADDri);
1843 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1844 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1845 TmpInst.addOperand(MCOperand::CreateImm(8));
1846 // Predicate.
1847 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1848 TmpInst.addOperand(MCOperand::CreateReg(0));
1849 // 's' bit operand (always reg0 for this).
1850 TmpInst.addOperand(MCOperand::CreateReg(0));
1851 OutStreamer.AddComment("eh_setjmp begin");
1852 OutStreamer.EmitInstruction(TmpInst);
1853 }
1854 {
1855 MCInst TmpInst;
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001856 TmpInst.setOpcode(ARM::STRi12);
Jim Grosbach45390082010-09-23 23:33:56 +00001857 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1858 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach45390082010-09-23 23:33:56 +00001859 TmpInst.addOperand(MCOperand::CreateImm(4));
1860 // Predicate.
1861 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1862 TmpInst.addOperand(MCOperand::CreateReg(0));
1863 OutStreamer.EmitInstruction(TmpInst);
1864 }
1865 {
1866 MCInst TmpInst;
1867 TmpInst.setOpcode(ARM::MOVi);
1868 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1869 TmpInst.addOperand(MCOperand::CreateImm(0));
1870 // Predicate.
1871 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1872 TmpInst.addOperand(MCOperand::CreateReg(0));
1873 // 's' bit operand (always reg0 for this).
1874 TmpInst.addOperand(MCOperand::CreateReg(0));
1875 OutStreamer.EmitInstruction(TmpInst);
1876 }
1877 {
1878 MCInst TmpInst;
1879 TmpInst.setOpcode(ARM::ADDri);
1880 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1881 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1882 TmpInst.addOperand(MCOperand::CreateImm(0));
1883 // Predicate.
1884 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1885 TmpInst.addOperand(MCOperand::CreateReg(0));
1886 // 's' bit operand (always reg0 for this).
1887 TmpInst.addOperand(MCOperand::CreateReg(0));
1888 OutStreamer.EmitInstruction(TmpInst);
1889 }
1890 {
1891 MCInst TmpInst;
1892 TmpInst.setOpcode(ARM::MOVi);
1893 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1894 TmpInst.addOperand(MCOperand::CreateImm(1));
1895 // Predicate.
1896 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1897 TmpInst.addOperand(MCOperand::CreateReg(0));
1898 // 's' bit operand (always reg0 for this).
1899 TmpInst.addOperand(MCOperand::CreateReg(0));
1900 OutStreamer.AddComment("eh_setjmp end");
1901 OutStreamer.EmitInstruction(TmpInst);
1902 }
1903 return;
1904 }
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001905 case ARM::Int_eh_sjlj_longjmp: {
1906 // ldr sp, [$src, #8]
1907 // ldr $scratch, [$src, #4]
1908 // ldr r7, [$src]
1909 // bx $scratch
1910 unsigned SrcReg = MI->getOperand(0).getReg();
1911 unsigned ScratchReg = MI->getOperand(1).getReg();
1912 {
1913 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001914 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001915 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1916 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001917 TmpInst.addOperand(MCOperand::CreateImm(8));
1918 // Predicate.
1919 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1920 TmpInst.addOperand(MCOperand::CreateReg(0));
1921 OutStreamer.EmitInstruction(TmpInst);
1922 }
1923 {
1924 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001925 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001926 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1927 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001928 TmpInst.addOperand(MCOperand::CreateImm(4));
1929 // Predicate.
1930 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1931 TmpInst.addOperand(MCOperand::CreateReg(0));
1932 OutStreamer.EmitInstruction(TmpInst);
1933 }
1934 {
1935 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001936 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001937 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1938 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001939 TmpInst.addOperand(MCOperand::CreateImm(0));
1940 // Predicate.
1941 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1942 TmpInst.addOperand(MCOperand::CreateReg(0));
1943 OutStreamer.EmitInstruction(TmpInst);
1944 }
1945 {
1946 MCInst TmpInst;
Bill Wendling6e46d842010-11-30 00:48:15 +00001947 TmpInst.setOpcode(ARM::BX);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001948 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1949 // Predicate.
1950 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1951 TmpInst.addOperand(MCOperand::CreateReg(0));
1952 OutStreamer.EmitInstruction(TmpInst);
1953 }
1954 return;
1955 }
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001956 case ARM::tInt_eh_sjlj_longjmp: {
1957 // ldr $scratch, [$src, #8]
1958 // mov sp, $scratch
1959 // ldr $scratch, [$src, #4]
1960 // ldr r7, [$src]
1961 // bx $scratch
1962 unsigned SrcReg = MI->getOperand(0).getReg();
1963 unsigned ScratchReg = MI->getOperand(1).getReg();
1964 {
1965 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001966 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001967 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1968 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1969 // The offset immediate is #8. The operand value is scaled by 4 for the
Bill Wendlingf4caf692010-12-14 03:36:38 +00001970 // tLDR instruction.
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001971 TmpInst.addOperand(MCOperand::CreateImm(2));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001972 // Predicate.
1973 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1974 TmpInst.addOperand(MCOperand::CreateReg(0));
1975 OutStreamer.EmitInstruction(TmpInst);
1976 }
1977 {
1978 MCInst TmpInst;
Jim Grosbach2a7b41b2011-06-30 23:38:17 +00001979 TmpInst.setOpcode(ARM::tMOVr);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001980 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1981 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1982 // Predicate.
1983 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1984 TmpInst.addOperand(MCOperand::CreateReg(0));
1985 OutStreamer.EmitInstruction(TmpInst);
1986 }
1987 {
1988 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001989 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001990 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1991 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1992 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001993 // Predicate.
1994 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1995 TmpInst.addOperand(MCOperand::CreateReg(0));
1996 OutStreamer.EmitInstruction(TmpInst);
1997 }
1998 {
1999 MCInst TmpInst;
Bob Wilson93abbc22012-04-07 16:51:59 +00002000 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00002001 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2002 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Bob Wilson93abbc22012-04-07 16:51:59 +00002003 TmpInst.addOperand(MCOperand::CreateImm(0));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00002004 // Predicate.
2005 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2006 TmpInst.addOperand(MCOperand::CreateReg(0));
2007 OutStreamer.EmitInstruction(TmpInst);
2008 }
2009 {
2010 MCInst TmpInst;
Cameron Zwarich421b1062011-05-26 03:41:12 +00002011 TmpInst.setOpcode(ARM::tBX);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00002012 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2013 // Predicate.
2014 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2015 TmpInst.addOperand(MCOperand::CreateReg(0));
2016 OutStreamer.EmitInstruction(TmpInst);
2017 }
2018 return;
2019 }
Chris Lattner97f06932009-10-19 20:20:46 +00002020 }
Jim Grosbachb0739b72010-09-02 01:02:06 +00002021
Chris Lattner97f06932009-10-19 20:20:46 +00002022 MCInst TmpInst;
Chris Lattner30e2cc22010-11-14 21:00:02 +00002023 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
Anton Korobeynikov57caad72011-03-05 18:43:32 +00002024
Chris Lattner850d2e22010-02-03 01:16:28 +00002025 OutStreamer.EmitInstruction(TmpInst);
Chris Lattner97f06932009-10-19 20:20:46 +00002026}
Daniel Dunbar2685a292009-10-20 05:15:36 +00002027
2028//===----------------------------------------------------------------------===//
2029// Target Registry Stuff
2030//===----------------------------------------------------------------------===//
2031
Daniel Dunbar2685a292009-10-20 05:15:36 +00002032// Force static initialization.
2033extern "C" void LLVMInitializeARMAsmPrinter() {
2034 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2035 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
Daniel Dunbar2685a292009-10-20 05:15:36 +00002036}