Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 43 | #define MDP_MIN_FETCH 9 |
| 44 | #define MDSS_MDP_MAX_FETCH 12 |
| 45 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 46 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 47 | |
| 48 | static int mdp_rev; |
| 49 | |
| 50 | void mdp_set_revision(int rev) |
| 51 | { |
| 52 | mdp_rev = rev; |
| 53 | } |
| 54 | |
| 55 | int mdp_get_revision() |
| 56 | { |
| 57 | return mdp_rev; |
| 58 | } |
| 59 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 60 | uint32_t mdss_mdp_intf_offset() |
| 61 | { |
| 62 | uint32_t mdss_mdp_intf_off; |
| 63 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 64 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 65 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 66 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 67 | mdss_mdp_intf_off = 0x59100; |
| 68 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 69 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 70 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 71 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 72 | |
| 73 | return mdss_mdp_intf_off; |
| 74 | } |
| 75 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 76 | void mdp_clk_gating_ctrl(void) |
| 77 | { |
| 78 | writel(0x40000000, MDP_CLK_CTRL0); |
| 79 | udelay(20); |
| 80 | writel(0x40000040, MDP_CLK_CTRL0); |
| 81 | writel(0x40000000, MDP_CLK_CTRL1); |
| 82 | writel(0x00400000, MDP_CLK_CTRL3); |
| 83 | udelay(20); |
| 84 | writel(0x00404000, MDP_CLK_CTRL3); |
| 85 | writel(0x40000000, MDP_CLK_CTRL4); |
| 86 | } |
| 87 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 88 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 89 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 90 | { |
| 91 | switch (pinfo->pipe_type) { |
| 92 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 93 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 94 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 95 | break; |
| 96 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 97 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 98 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 99 | break; |
| 100 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 101 | default: |
| 102 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 103 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 104 | break; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 109 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 110 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 111 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 112 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 113 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 114 | switch (pinfo->pipe_type) { |
| 115 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 116 | if (dual_pipe_single_ctl) |
| 117 | *ctl0_reg_val = 0x220D8; |
| 118 | else |
| 119 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 120 | *ctl1_reg_val = 0x24090; |
| 121 | break; |
| 122 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 123 | if (dual_pipe_single_ctl) |
| 124 | *ctl0_reg_val = 0x238C0; |
| 125 | else |
| 126 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 127 | *ctl1_reg_val = 0x25080; |
| 128 | break; |
| 129 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 130 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 131 | if (dual_pipe_single_ctl) |
| 132 | *ctl0_reg_val = 0x220C3; |
| 133 | else |
| 134 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 135 | *ctl1_reg_val = 0x24082; |
| 136 | break; |
| 137 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 138 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 139 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 140 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) { |
| 141 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 142 | *ctl1_reg_val |= BIT(31); |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 143 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
| 144 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109)) { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 145 | *ctl0_reg_val |= BIT(30); |
| 146 | *ctl1_reg_val |= BIT(29); |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 147 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 148 | } |
| 149 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 150 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 151 | *pinfo, uint32_t pipe_base) |
| 152 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 153 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 154 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 155 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 156 | uint32_t src_xy = 0, dst_xy = 0; |
| 157 | uint32_t height, width; |
| 158 | |
| 159 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 160 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 161 | |
| 162 | /* write active region size*/ |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 163 | src_size = (height << 16) + width; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 164 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 165 | if (pinfo->lcdc.dual_pipe) { |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 166 | out_size = (height << 16) + (width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 167 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 168 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 169 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 170 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | stride = (fb->stride * fb->bpp/8); |
| 174 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 175 | if (fb_off == 0) { /* left */ |
| 176 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 177 | src_xy = dst_xy; |
| 178 | } else { /* right */ |
| 179 | dst_xy = (pinfo->border_top << 16); |
| 180 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 181 | } |
| 182 | |
| 183 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 184 | __func__, out_size, fb_off, src_xy, dst_xy); |
| 185 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 186 | writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
| 187 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 188 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 189 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 190 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 191 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 192 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 193 | |
| 194 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 195 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 196 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 197 | |
| 198 | /* bit(0) is set if hflip is required. |
| 199 | * bit(1) is set if vflip is required. |
| 200 | */ |
| 201 | if (pinfo->orientation & 0x1) |
| 202 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 203 | if (pinfo->orientation & 0x2) |
| 204 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
| 205 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 206 | } |
| 207 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 208 | static void mdss_vbif_setup() |
| 209 | { |
| 210 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 211 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 212 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 213 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 214 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 215 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 216 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 217 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 218 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 219 | |
| 220 | /* |
| 221 | * Following configuration is needed because on some versions, |
| 222 | * recommended reset values are not stored. |
| 223 | */ |
| 224 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 225 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 226 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 227 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 228 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 229 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 230 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 231 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 232 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 233 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 234 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 235 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 236 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 237 | } |
| 238 | } |
| 239 | } |
| 240 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 241 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 242 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 243 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 244 | uint32_t i, j; |
| 245 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 246 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 247 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 248 | /* max 3 MMB per register */ |
| 249 | reg_val |= client_id << (((j++) % 3) * 8); |
| 250 | if ((j % 3) == 0) { |
| 251 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 252 | free_smp_offset); |
| 253 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 254 | free_smp_offset); |
| 255 | reg_val = 0; |
| 256 | free_smp_offset += 4; |
| 257 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 258 | } |
| 259 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 260 | if (j % 3) { |
| 261 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 262 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 263 | free_smp_offset += 4; |
| 264 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 265 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 266 | return free_smp_offset; |
| 267 | } |
| 268 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 269 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 270 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 271 | { |
| 272 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 273 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 274 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
| 275 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108)) { |
| 276 | switch (pinfo->pipe_type) { |
| 277 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 278 | *left_sspp_client_id = 0x7; /* 7 */ |
| 279 | *right_sspp_client_id = 0x11; /* 17 */ |
| 280 | break; |
| 281 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 282 | *left_sspp_client_id = 0x4; /* 4 */ |
| 283 | *right_sspp_client_id = 0xD; /* 13 */ |
| 284 | break; |
| 285 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 286 | default: |
| 287 | *left_sspp_client_id = 0x1; /* 1 */ |
| 288 | *right_sspp_client_id = 0x4; /* 4 */ |
| 289 | break; |
| 290 | } |
| 291 | } else { |
| 292 | switch (pinfo->pipe_type) { |
| 293 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 294 | *left_sspp_client_id = 0x10; /* 16 */ |
| 295 | *right_sspp_client_id = 0x11; /* 17 */ |
| 296 | break; |
| 297 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 298 | *left_sspp_client_id = 0xA; /* 10 */ |
| 299 | *right_sspp_client_id = 0xD; /* 13 */ |
| 300 | break; |
| 301 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 302 | default: |
| 303 | *left_sspp_client_id = 0x1; /* 1 */ |
| 304 | *right_sspp_client_id = 0x4; /* 4 */ |
| 305 | break; |
| 306 | } |
| 307 | } |
| 308 | } |
| 309 | |
| 310 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 311 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 312 | { |
| 313 | switch (pinfo->pipe_type) { |
| 314 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 315 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 316 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 317 | break; |
| 318 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 319 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 320 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 321 | break; |
| 322 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 323 | default: |
| 324 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 325 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 326 | break; |
| 327 | } |
| 328 | } |
| 329 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 330 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 331 | uint32_t right_pipe) |
| 332 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 333 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 334 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 335 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 336 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 337 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 338 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 339 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) { |
| 340 | /* 8Kb per SMP on 8916 */ |
| 341 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 342 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 343 | /* 10Kb per SMP on 8939 */ |
| 344 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 345 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 346 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 347 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 348 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 349 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 350 | fixed_smp_cnt = 2; |
| 351 | else |
| 352 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 353 | } |
| 354 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 355 | mdp_select_pipe_client_id(pinfo, |
| 356 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 357 | |
| 358 | /* Each pipe driving half the screen */ |
| 359 | if (pinfo->lcdc.dual_pipe) |
| 360 | xres /= 2; |
| 361 | |
| 362 | /* bpp = bytes per pixel of input image */ |
| 363 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 364 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 365 | |
| 366 | if (smp_cnt > 4) { |
| 367 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 368 | smp_cnt); |
| 369 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 370 | } |
| 371 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 372 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 373 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 374 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 375 | |
| 376 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 377 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 378 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 379 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 380 | } |
| 381 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 382 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 383 | fixed_smp_cnt, free_smp_offset); |
| 384 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 385 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 386 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 387 | } |
| 388 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 389 | void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 390 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 391 | uint32_t hsync_period, vsync_period; |
| 392 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 393 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 394 | uint32_t mdss_mdp_intf_off; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 395 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 396 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 397 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 398 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 399 | |
| 400 | if (pinfo == NULL) |
| 401 | return ERR_INVALID_ARGS; |
| 402 | |
| 403 | lcdc = &(pinfo->lcdc); |
| 404 | if (lcdc == NULL) |
| 405 | return ERR_INVALID_ARGS; |
| 406 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 407 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 408 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 409 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 410 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 411 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 412 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 413 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 414 | } |
| 415 | } |
| 416 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 417 | if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) { |
| 418 | writel(BIT(16), MDP_REG_PPB0_CONFIG); |
| 419 | writel(BIT(5), MDP_REG_PPB0_CNTL); |
| 420 | } |
| 421 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 422 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 423 | pinfo->fbc.comp_ratio = 1; |
| 424 | |
| 425 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 426 | itp.yres = pinfo->yres; |
| 427 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
| 428 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 429 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 430 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 431 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 432 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 433 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 434 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 435 | |
| 436 | itp.border_clr = pinfo->lcdc.border_clr; |
| 437 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 438 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 439 | |
| 440 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 441 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 442 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 443 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 444 | itp.width + itp.h_front_porch; |
| 445 | |
| 446 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 447 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 448 | |
| 449 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 450 | itp.hsync_pulse_width + |
| 451 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 452 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 453 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 454 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 455 | display_vstart = (itp.vsync_pulse_width + |
| 456 | itp.v_back_porch) |
| 457 | * hsync_period + itp.hsync_skew; |
| 458 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 459 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 460 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 461 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 462 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 463 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 464 | } |
| 465 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 466 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 467 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 468 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 469 | writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off); |
| 470 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
| 471 | mdss_mdp_intf_off); |
| 472 | writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 473 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 474 | MDP_VSYNC_PULSE_WIDTH_F0 + |
| 475 | mdss_mdp_intf_off); |
| 476 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off); |
| 477 | writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off); |
| 478 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
| 479 | mdss_mdp_intf_off); |
| 480 | writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off); |
| 481 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
| 482 | mdss_mdp_intf_off); |
| 483 | writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off); |
| 484 | writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off); |
| 485 | writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off); |
| 486 | writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off); |
| 487 | writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off); |
| 488 | writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off); |
| 489 | writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off); |
| 490 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 491 | if (intf_base == MDP_INTF_0_BASE) /* eDP */ |
| 492 | writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
| 493 | else |
| 494 | writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 495 | } |
| 496 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 497 | void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
| 498 | uint32_t intf_base) |
| 499 | { |
| 500 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 501 | uint32_t mdss_mdp_intf_off; |
| 502 | uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines; |
| 503 | uint32_t adjust_xres = 0; |
| 504 | |
| 505 | struct lcdc_panel_info *lcdc = NULL; |
| 506 | |
| 507 | if (pinfo == NULL) |
| 508 | return; |
| 509 | |
| 510 | lcdc = &(pinfo->lcdc); |
| 511 | if (lcdc == NULL) |
| 512 | return; |
| 513 | |
| 514 | /* |
| 515 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 516 | * Programmable fetch is not needed if vertical back porch |
| 517 | * is >= 9. |
| 518 | */ |
| 519 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
| 520 | lcdc->v_back_porch >= MDP_MIN_FETCH) |
| 521 | return; |
| 522 | |
| 523 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 524 | |
| 525 | adjust_xres = pinfo->xres; |
| 526 | if (pinfo->lcdc.split_display) |
| 527 | adjust_xres /= 2; |
| 528 | |
| 529 | /* |
| 530 | * Fetch should always be outside the active lines. If the fetching |
| 531 | * is programmed within active region, hardware behavior is unknown. |
| 532 | */ |
| 533 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 534 | lcdc->v_front_porch; |
| 535 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 536 | lcdc->h_front_porch; |
| 537 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 538 | |
| 539 | fetch_lines = v_total - vfp_start; |
| 540 | |
| 541 | /* |
| 542 | * In some cases, vertical front porch is too high. In such cases limit |
| 543 | * the mdp fetch lines as the last 12 lines of vertical front porch. |
| 544 | */ |
| 545 | if (fetch_lines > MDSS_MDP_MAX_FETCH) |
| 546 | fetch_lines = MDSS_MDP_MAX_FETCH; |
| 547 | |
| 548 | fetch_start = (v_total - fetch_lines) * h_total + 1; |
| 549 | |
| 550 | writel(fetch_start, MDP_PROG_FETCH_START + mdss_mdp_intf_off); |
| 551 | writel(BIT(31), MDP_INTF_CONFIG + mdss_mdp_intf_off); |
| 552 | } |
| 553 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 554 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 555 | *pinfo) |
| 556 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 557 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 558 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 559 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 560 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 561 | width = fb->width; |
| 562 | |
| 563 | if (pinfo->lcdc.dual_pipe) |
| 564 | width /= 2; |
| 565 | |
| 566 | /* write active region size*/ |
| 567 | mdp_rgb_size = (height << 16) | width; |
| 568 | |
| 569 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 570 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 571 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 572 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 573 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 574 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 575 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 576 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 577 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 578 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 579 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 580 | switch (pinfo->pipe_type) { |
| 581 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 582 | left_staging_level = 0x0000200; |
| 583 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 584 | break; |
| 585 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 586 | left_staging_level = 0x0040000; |
| 587 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 588 | break; |
| 589 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 590 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 591 | left_staging_level = 0x1; |
| 592 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 593 | break; |
| 594 | } |
| 595 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 596 | /* Base layer for layer mixer 0 */ |
| 597 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 598 | |
| 599 | if (pinfo->lcdc.dual_pipe) { |
| 600 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 601 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 602 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 603 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 604 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 605 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 606 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 607 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 608 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 609 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 610 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 611 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 612 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 613 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 614 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 615 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 616 | } |
| 617 | } |
| 618 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 619 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 620 | { |
| 621 | uint32_t mode = 0; |
| 622 | uint32_t budget_ctl = 0; |
| 623 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 624 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame^] | 625 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 626 | |
| 627 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 628 | |
| 629 | if (!pinfo->fbc.enabled) |
| 630 | return; |
| 631 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 632 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 633 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 634 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame^] | 635 | width = pinfo->xres; |
| 636 | if (enc_mode) |
| 637 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 638 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame^] | 639 | if (pinfo->mipi.dual_dsi) |
| 640 | width /= 2; |
| 641 | |
| 642 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 643 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 644 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 645 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 646 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 647 | |
| 648 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 649 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 650 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 651 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 652 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n", |
| 653 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 654 | |
| 655 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 656 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 657 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame^] | 658 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 659 | ((fbc->lossy_mode_thd) << 8) | |
| 660 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 661 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame^] | 662 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 663 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 664 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 665 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 666 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 667 | |
| 668 | if (pinfo->mipi.dual_dsi) { |
| 669 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 670 | writel(budget_ctl, MDP_PP_1_BASE + |
| 671 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 672 | writel(lossy_mode, MDP_PP_1_BASE + |
| 673 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 674 | } |
| 675 | } |
| 676 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 677 | void mdss_qos_remapper_setup(void) |
| 678 | { |
| 679 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 680 | uint32_t map; |
| 681 | |
| 682 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 683 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 684 | MDSS_MDP_HW_REV_102)) |
| 685 | map = 0xE9; |
| 686 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 687 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 688 | map = 0xA5; |
| 689 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 690 | MDSS_MDP_HW_REV_106) || |
| 691 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 692 | MDSS_MDP_HW_REV_108)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 693 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 694 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 695 | MDSS_MDP_HW_REV_105) || |
| 696 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 697 | MDSS_MDP_HW_REV_109)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 698 | map = 0xA4; |
| 699 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 700 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 701 | map = 0xFA; |
| 702 | else |
| 703 | return; |
| 704 | |
| 705 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 706 | } |
| 707 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 708 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 709 | { |
| 710 | uint32_t mask, reg_val, i; |
| 711 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 712 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 713 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
| 714 | |
| 715 | mdp_select_pipe_xin_id(pinfo, |
| 716 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 717 | |
| 718 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
| 719 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108)) { |
| 720 | vbif_qos[0] = 2; |
| 721 | vbif_qos[1] = 2; |
| 722 | vbif_qos[2] = 2; |
| 723 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 724 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
| 725 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 726 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 727 | vbif_qos[1] = 2; |
| 728 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 729 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 730 | } else { |
| 731 | return; |
| 732 | } |
| 733 | |
| 734 | for (i = 0; i < 4; i++) { |
| 735 | reg_val = readl(VBIF_VBIF_QOS_REMAP_00 + i*4); |
| 736 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 737 | reg_val &= ~(mask); |
| 738 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 739 | |
| 740 | if (pinfo->lcdc.dual_pipe) { |
| 741 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 742 | reg_val &= ~(mask); |
| 743 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 744 | } |
| 745 | writel(reg_val, VBIF_VBIF_QOS_REMAP_00 + i*4); |
| 746 | } |
| 747 | } |
| 748 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 749 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 750 | int is_main_ctl) |
| 751 | { |
| 752 | if (pinfo->lcdc.pipe_swap) { |
| 753 | if (is_main_ctl) |
| 754 | return BIT(4) | BIT(5); /* Interface 2 */ |
| 755 | else |
| 756 | return BIT(5); /* Interface 1 */ |
| 757 | } else { |
| 758 | if (is_main_ctl) |
| 759 | return BIT(5); /* Interface 1 */ |
| 760 | else |
| 761 | return BIT(4) | BIT(5); /* Interface 2 */ |
| 762 | } |
| 763 | } |
| 764 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 765 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 766 | struct fbcon_config *fb) |
| 767 | { |
| 768 | int ret = NO_ERROR; |
| 769 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 770 | uint32_t intf_sel = 0x100; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 771 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 772 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 773 | |
| 774 | mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 775 | mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 776 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 777 | if (pinfo->mipi.dual_dsi) { |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 778 | mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 779 | mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE); |
| 780 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 781 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 782 | mdp_clk_gating_ctrl(); |
| 783 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 784 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 785 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 786 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 787 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 788 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 789 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 790 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 791 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 792 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 793 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 794 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 795 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 796 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 797 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 798 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 799 | |
| 800 | /* enable 3D mux for dual_pipe but single interface config */ |
| 801 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 802 | !pinfo->lcdc.split_display) |
| 803 | reg |= BIT(19) | BIT(20); |
| 804 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 805 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 806 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 807 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 808 | CTL_1 path should not be set since CTL_0 itself is going |
| 809 | to split after DSPP block*/ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 810 | if (pinfo->fbc.enabled) |
| 811 | mdss_fbc_cfg(pinfo); |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 812 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 813 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 814 | if (!pinfo->lcdc.dst_split) { |
| 815 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 816 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 817 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 818 | intf_sel |= BIT(16); /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 819 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 820 | |
| 821 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 822 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 823 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 824 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 825 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 826 | |
| 827 | return 0; |
| 828 | } |
| 829 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 830 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 831 | { |
| 832 | int ret = NO_ERROR; |
| 833 | struct lcdc_panel_info *lcdc = NULL; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 834 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 835 | |
| 836 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 837 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 838 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 839 | mdp_clk_gating_ctrl(); |
| 840 | |
| 841 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 842 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 843 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 844 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 845 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 846 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 847 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 848 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 849 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 850 | |
| 851 | mdss_layer_mixer_setup(fb, pinfo); |
| 852 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 853 | if (pinfo->lcdc.dual_pipe) |
| 854 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 855 | else |
| 856 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 857 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 858 | writel(0x9, MDP_DISP_INTF_SEL); |
| 859 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 860 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 861 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 862 | |
| 863 | return 0; |
| 864 | } |
| 865 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 866 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 867 | { |
| 868 | int ret = NO_ERROR; |
| 869 | struct lcdc_panel_info *lcdc = NULL; |
| 870 | uint32_t left_pipe, right_pipe; |
| 871 | |
| 872 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE); |
| 873 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 874 | |
| 875 | mdp_clk_gating_ctrl(); |
| 876 | mdss_vbif_setup(); |
| 877 | |
| 878 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 879 | |
| 880 | mdss_qos_remapper_setup(); |
| 881 | |
| 882 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 883 | if (pinfo->lcdc.dual_pipe) |
| 884 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 885 | |
| 886 | mdss_layer_mixer_setup(fb, pinfo); |
| 887 | |
| 888 | if (pinfo->lcdc.dual_pipe) |
| 889 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 890 | else |
| 891 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 892 | |
| 893 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 894 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 895 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 896 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 897 | |
| 898 | return 0; |
| 899 | } |
| 900 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 901 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 902 | struct fbcon_config *fb) |
| 903 | { |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 904 | uint32_t intf_sel = BIT(8); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 905 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 906 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 907 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 908 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 909 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 910 | uint32_t mdss_mdp_intf_off = 0; |
| 911 | |
| 912 | if (pinfo == NULL) |
| 913 | return ERR_INVALID_ARGS; |
| 914 | |
| 915 | lcdc = &(pinfo->lcdc); |
| 916 | if (lcdc == NULL) |
| 917 | return ERR_INVALID_ARGS; |
| 918 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 919 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 920 | reg = BIT(1); /* Command mode */ |
| 921 | if (pinfo->lcdc.pipe_swap) |
| 922 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 923 | else |
| 924 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 925 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 926 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 927 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 928 | } |
| 929 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 930 | if (pinfo->lcdc.dst_split) { |
| 931 | writel(BIT(16), MDP_REG_PPB0_CONFIG); |
| 932 | writel(BIT(5), MDP_REG_PPB0_CNTL); |
| 933 | } |
| 934 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 935 | mdss_mdp_intf_off = mdss_mdp_intf_offset(); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 936 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 937 | mdp_clk_gating_ctrl(); |
| 938 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 939 | if (pinfo->mipi.dual_dsi) |
| 940 | intf_sel |= BIT(16); /* INTF 2 enable */ |
| 941 | |
| 942 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 943 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 944 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 945 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 946 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 947 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 948 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 949 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 950 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 951 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 952 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 953 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 954 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 955 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 956 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 957 | writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 958 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 959 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 960 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 961 | if (pinfo->fbc.enabled) |
| 962 | mdss_fbc_cfg(pinfo); |
| 963 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 964 | if (pinfo->mipi.dual_dsi) { |
| 965 | writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 966 | if (!pinfo->lcdc.dst_split) { |
| 967 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 968 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 969 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 970 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 971 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 972 | return ret; |
| 973 | } |
| 974 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 975 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 976 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 977 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 978 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 979 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 980 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 981 | writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 982 | |
| 983 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 984 | } |
| 985 | |
| 986 | int mdp_dsi_video_off() |
| 987 | { |
| 988 | if(!target_cont_splash_screen()) |
| 989 | { |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 990 | writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN + |
| 991 | mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 992 | mdelay(60); |
| 993 | /* Ping-Pong done Tear Check Read/Write */ |
| 994 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 995 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 996 | } |
| 997 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 998 | writel(0x00000000, MDP_INTR_EN); |
| 999 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1000 | return NO_ERROR; |
| 1001 | } |
| 1002 | |
| 1003 | int mdp_dsi_cmd_off() |
| 1004 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1005 | if(!target_cont_splash_screen()) |
| 1006 | { |
| 1007 | /* Ping-Pong done Tear Check Read/Write */ |
| 1008 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1009 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1010 | } |
| 1011 | writel(0x00000000, MDP_INTR_EN); |
| 1012 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1013 | return NO_ERROR; |
| 1014 | } |
| 1015 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1016 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1017 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1018 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1019 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1020 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1021 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1022 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1023 | return NO_ERROR; |
| 1024 | } |
| 1025 | |
| 1026 | void mdp_disable(void) |
| 1027 | { |
| 1028 | |
| 1029 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1030 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1031 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1032 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1033 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1034 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1035 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1036 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1037 | return NO_ERROR; |
| 1038 | } |
| 1039 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1040 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1041 | { |
| 1042 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1043 | |
| 1044 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1045 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1046 | |
| 1047 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1048 | |
| 1049 | return NO_ERROR; |
| 1050 | } |
| 1051 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1052 | int mdp_edp_off(void) |
| 1053 | { |
| 1054 | if (!target_cont_splash_screen()) { |
| 1055 | |
| 1056 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1057 | mdss_mdp_intf_offset()); |
| 1058 | mdelay(60); |
| 1059 | /* Ping-Pong done Tear Check Read/Write */ |
| 1060 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1061 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1062 | writel(0x00000000, MDP_INTR_EN); |
| 1063 | } |
| 1064 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1065 | writel(0x00000000, MDP_INTR_EN); |
| 1066 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1067 | return NO_ERROR; |
| 1068 | } |